papi-5.5.1/0000755000307100002310000000000013013651561012456 5ustar yarkhangraduatepapi-5.5.1/ChangeLogP510.txt0000644000307100002310000004560513013651444015426 0ustar yarkhangraduate2013-01-15 * 0917f567 src/threads.c: Cleaned up compiler warning (gcc version 4.4.6) * 06ca3faa src/components/bgpm/CNKunit/linux-CNKunit.c src/components/bgpm/IOunit/linux-IOunit.c src/components/bgpm/L2unit/linux-L2unit.c...: Cleaned up compiler warnings on BG/Q (gcc version 4.4.6 (BGQ-V1R1M2-120920)) 2013-01-14 * 56400627 .../build/lib.linux-x86_64-2.7/perfmon/__init__.py .../lib.linux-x86_64-2.7/perfmon/perfmon_int.py .../build/lib.linux-x86_64-2.7/perfmon/pmu.py...: libpfm4: remove extraneous build artifacts. Steve Kaufmann reported differences between the libpfm4 I imported into PAPI and the libpfm4 that can be attained with a git clone git://perfmon2.git.sourceforge.net/gitroot/perfmon2/libpfm4 Self: Do libpfm4 imports from a fresh clone of libpfm4. 2013-01-11 * 4ad994bc src/papi_events.csv: Clean up armv7 cortex a15 presets Clean up armv7 cortex a15 presets and add presets for L1 and L2 cache * d54dabf5 ChangeLogP510.txt RELEASENOTES.txt doc/Doxyfile-common...: Prepare the repo for a 5.1 release. * Bump the version number to 5.1 * Update the man pages * Create a changelog for 5.1 * Update RELEASENOTES * 8816a3b8 INSTALL.txt: Update INSTALL.txt Add information about installing PAPI on Intel MIC. Based upon information from Vince Weaver's PAPI MIC support page. http://www.eece.maine.edu/~vweaver/projects/mic/ * 8dc1ca23 TEST.TXT: Remove TEST.TXT This was a leftover from a switch over to git. * 292d6c9b src/papi_libpfm3_events.c: Fix build on ia64 When trying to build papi 5.0.1 for IA64, my collegue got compile errors due to perfmon.h not being included. We're not sure if this actually is a configure bug, but this patch fixed it. * 25424f41 src/extras.c: Fix kernel warning in _papi_hwi_stop_timer() In _papi_hwi_stop_timer() we were calling setitimer( timer, NULL, NULL ) to disable the itimer. Recent Linux kernels print warnings if you do this; NULL is not a valid second argument to setitimer() and possibly this wasn't really working before. According to the manpage the proper fix is to call setitimer() with a valid "new_value" field but with the values all 0. That is what this patch does. 2012-11-30 * a7d70127 src/components/micpower/README src/components/micpower/Rules.micpower src/components/micpower/linux-micpower.c...: MIC power component The Intel MIC (Xeon PHI) card reports power of several components of the card. These values are reported in a sysfs file, so this component is cloned from the coretemp component. 2013-01-08 * 121cd0a6 src/Makefile.in src/Rules.pfm4_pe src/configure...: configure: Add shortcut for mic support. * Add a --with-mic flag to enable the several options to cross compile for mic. MIC builds are cross-compiled and Matt and I were unable to figure out how to trigger cross compilation with just our flag. This is short-hand for setting --with-arch=k1om --without-ffsll --with-walltimer=clock_realtime_hr \ --with-perf-events --with-tls=__thread --with-virtualtimer=cputime_id * Automatically cause make to pass CONFIG_PFMLIB_ARCH_X86=y to libpfm4's make. So to build for the mic card one has to do: {Set pathing to find the x86_64-k1om-linux-gcc cross-compiler} $ ./configure --host=x86_64-k1om-linux --with-mic $ make Thanks to Matt Johnson for the legwork on configure shortcuting. 2013-01-07 * f65c9d9e src/papi_events.csv: Add preset events for ARM Cortex A15 2012-12-14 * 61a9c7b1 man/man3/PAPI_get_eventset_component.3 src/papi.c: Doxygen: Add a new API entry Add the manpage for the new PAPI_get_eventset_component api entry. 2013-01-02 * 38d969ab doc/Doxyfile-man1 doc/Doxyfile-man3 doc/Makefile...: Doxygen: Cleanup generated man pages. Mark a few \page sections as \htmlonly so that man pages are not built for them. Modify the makefile to rm some data structures that are generated. Doxyfile-man3: * Take out papi_vector.h, this file only defines a few data structures from which we don't need manpages. papi.h: * PAPI_get_component_index's inline comment had the close /**> to delimit its description, but doxygen uses /**<. papi_fwrappers.c: * Mark the group PAPIF as internal so that a man page is not generated for it. utils/*: * Remove some useless htmlonly directrives, doxygen will generate pages for any data structure, htmlonly doesn't stop that. Doxyfile-man1: * Change a flag in Doxyfile-man1 so that we don't document internal data structures in the utilities. We don't do this in -man3 because of the \class workaround we use to create manpages for each of the PAPI_* api entry points. Because we call them classes, they would be caught in the no data structures flag. * 7b790c09 doc/Doxyfile-html src/papi.h src/papi_fwrappers.c...: Doxygen: Cleanup some of the markup We were not using htmlonly correctly... The idea was to use \htmlonly to not build manpages for a few things. To properly hide \page s you want things like: /** \htmlonly \page Foo I don't want this to generate a manpage. \endhtmlonly */ 2012-12-07 * 152bac19 src/papi.c: Doxygen: Cleanup papi.c Cleanup some \ref s, \ref PAPI_function() isn't happy, use \ref PAPI_function it'll put in the proper links. Remove _papi_overflow_handler doc block. We had the block but no code. 2012-12-20 * 7a40c769 src/components/rapl/tests/rapl_overflow.c: RAPL test code: Add flexibility to the test code. Per Will Cohen; ------------------ I was reviewing some test results for the papi test and found that the rapl_overflow.c tests makes an assumption that there are exactly two packages. As a result the test will fail on machines with a single package. The following is a patch to make it a bit more flexible allow 1-n packages in the test. -Will ----------------- 2012-12-19 * 96c9afb0 src/components/appio/README src/components/appio/appio.c src/components/appio/appio.h...: Added events for seek statistics and support for intercepting lseek() calls. 2012-12-14 * 003abf6d src/Rules.perfctr-pfm: Rules.perfctr-pfm: pass CC in all cases. Perfctr user library was not being passed CC when built. 2012-12-05 * e2c05b29 src/papi_internal.c: papi_internal.c: Refactor dublicated code in cleanup and free eventset. Currently the code to free runtime state is duplicated in cleanup and free. The perf_event_uncore test exposed an issue where free cleaned up cpu_attach state but cleanup did not, causing a leak. Have _papi_hwi_free_EventSet call _papi_hwi_cleanup_eventset to free most of the runtime state of the eventset and then allow free_eventset to free the Eventset Info struct. 2012-12-13 * 7d020224 src/configure src/configure.in: configure: Change fortran compiler search order. Bandaid fix to buildbot errors. By default, configure would find icc before gcc but gfortran would be used before ifort. The real fix is to test that object code from the c compiler can be linked to by the fortran compiler. 2012-12-12 * 87b6e913 src/papi_events.csv: ivy_bridge: remove PAPI_HW_INT event Apparently recent Intel Vol3B documentation removed this event, and the most recent libpfm4 merge followed suit. I asked at Intel about this and possibly they only removed it because they didn't think anyone was using it. Maybe they'll ad it back 2012-12-10 * 293b26b9 src/Makefile.inc: Makefile.inc: Fix library link ordering. Per Will Cohen ----------------------------------------------------------- I ran across a problem when trying to build papi with the bundled libpfm and an earlier incompatible version of libpfm was already installed on the machine. The make would use the /usr/lib{64}/libpfm.so before trying to use the locally built version and this would cause problems. The attached patch changes the order of the linking and uses the local built libpfm before it tries the installed version. -Will ----------------------------------------------------------- 2012-12-12 * 57e6aa0d src/Makefile.in: Makefile.in: export CC_COMMON_NAME In 17cfcb4a I started using CC_COMMON_NAME in Rules.pfm4 but failed to have configure put it in Makefile. 2012-12-11 * 17cfcb4a src/Rules.pfm4_pe src/configure src/configure.in: Cleanup icc build Start using -diag-disable to quiet down some of the remarks icc carps about in libpfm4. Also have configure export CC_COMMON_NAME and check against that in Rules.pfm4_pe. afec8fc9a reverted us to passing -Wno-unused-parameter to icc, polluting buildbot. 2012-12-10 * afec8fc9 src/configure src/configure.in: configure: Attempt to better detect which C compiler we are using. This attempts to address trac bug 162. http://icl.cs.utk.edu/trac/papi/ticket/162 Specifying full paths for CC caused issues in our configure logic. We set several flags specific to gcc or icc and this was breaking down EG "/usr/bin/gcc" != "gcc" Now we attempt to execute whatever CC we are going to use and grep its version string. We set a CC_COMMON_NAME \in {"gcc", "icc", "xlc", "unknown"} based upon the above and later check CC_COMMON_NAME inplace of CC to set compiler specific flags. * 14432aa0 src/linux-timer.c src/papi.c: Minor Coverity fixes. Thanks, Will Cohen. 2012-12-07 * ba5e83d4 src/papi_user_events.c: papi_user_events.c: Fix memory leak. Reported by William Cohen as detected by the coverity tool. * 166498a8 src/components/nvml/linux-nvml.c: nvml component: fix detectDevices() The routine detectDevices() always returned with the error PAPI_ESYS when there was a device available. This resulted in that there were no nvml events available. Fixed. * 11ad5894 src/components/nvml/linux-nvml.c: nvml component: add missing variable declaration In the routine _papi_nvml_init_componen(), the variable papi_errorcode was not declared which prevented this component to build. Added declaration of papi_errorcode as int. 2012-12-06 * 9567dfef src/ftests/first.F src/ftests/second.F: Fix warning messages issued by gfortran 4.6.x regarding loss of precision when casting REAL to INT. Thanks to Heike for identifying the proper intrinsics. * 72588227 src/papi.c src/papi.h: Add PAPI_get_eventset_component() to get the component index from an event set. This is symmetric with PAPI_get_event_component which extracts the information from an event. In response to a request from John Mellor-Crummey. * 2e055d40 src/components/rapl/linux-rapl.c: Fix a compiler warning about a possibly uninitialized return value. 2012-12-05 * 1aae2246 src/utils/command_line.c: Reformat the floating point output string to recognize that you can't cast the *value* of a long long to a double and expect to get the right answer; you need to cast the *pointer* to a double, then everything works. * 0e834fc2 src/utils/command_line.c: Incorporated use of the new PAPI_add_named_event API. Restructured output to support formatted printing of built-in DATATYPEs: UINT64 prints as unsigned followed by (u); INT64 prints as signed; FP64 prints as float (but I don't like the default format); BIT64 prints a hex, prefixed by '0x'. Also if info.units is not empty, units are appended to output values. These features can be demo'd with the RAPL component. * af6abec2 src/papi.h: Rearranged DATATYPE enums so INT64 is now default (0) value. Also added a BIT64 type for unspecified bitfields. 2012-12-04 * 862033e0 src/components/bgpm/IOunit/linux-IOunit.c src/components/bgpm/IOunit/linux-IOunit.h src/components/bgpm/L2unit/linux-L2unit.c...: Resolved multiple components conflict on BG/Q when overflow is enabled for multiple events from different components at the same time. * 44744002 src/utils/command_line.c: Add -x and -u options to papi_command_line to allow printing counter values in hexadecimal and unsigned formats. 2012-11-30 * 25a914c5 src/papi_user_events.c: Cleanup unused variable warnings in user_events code. 2012-11-28 * 9a75f872 src/Rules.pfm4_pe src/configure src/configure.in: Cleanup the build under icc. libpfm4's build system uses a gcc specific flag, -Wno-unused-parameter. It does this via a variable, DBG, in config.mk: DBG?=-g -Wall -Werror -Wextra -Wno-unused-parameter The Intel compiler doesn't understand -Wno-unused-parameter and complains about it. In Rules.pfm4_pe we set DBG for icc builds. 2012-11-27 * 4def827b src/configure src/configure.in: Fix the perfctr build that was breaking due to missing CPU Mark Gates was reporting PAPI 5 wasn't running properly on Keeneland. It looks like some CPU cleanups in the configure code broke things. Hopefully this helps the situation. 2012-11-21 * 4316f172 src/perf_events.c: perf_events: get rid of "PAPI Error: Didn't close all events" error This was more meant as a warning; it could trigger when closing an EventSet that had an event partially added but failed for some reason. * 671e10bd src/utils/command_line.c: papi_command_line: fix error output The error messages got a bit weird looking due to the PAPI error printing changes a while back. * 959afa49 src/papi_internal.c: Fix _papi_hwi_add_event to report errors back to user. Previously _papi_hwi_add_event would report all errors returned by add_native_events() as being PAPI_ECNFLCT even though add_native_events() returned a wider range of errors. * 8ecb70ba src/perf_events.c: Have perf_event return PAPI_EPERM rather than PAPI_ECNFLCT if the kernel itself returns EPERM * 9053ca1c src/perf_events.c: Work around kernel issue with PERF_EVENT_IOC_REFRESH It's unclear exactly the best way to restart sampling. Refreshing with 1 is the "official" way as espoused by the kernel developers, but it doesn't work on Power. 0 works for Power and most other machines, but the kernel developers say not to use it. This makes power user 0 until we can figure out exactly what is going on. * e85df04b src/components/appio/tests/appio_test_socket.c: - added support distinguishing between network and file I/O. - added events to measure statistics for sockets - updated README 2012-11-15 * 248694ef src/x86_cpuid_info.c: Update x86_cpuid_info code for KNC. On Knight's Corner the leaf2 code returns 0 for the count value. We were printing a warning on this; better would be to just skip the cache detection code if we get this result. 2012-11-08 * 82c93156 src/linux-bgp-memory.c src/linux-bgp.c src/linux-bgp.h: There was more cleaning up necessary in order to get PAPI compiled on BG/P. It should work now with the recommended configure steps described in INSTALL. 2012-11-07 * 77da80b3 src/Makefile.inc src/configure src/configure.in...: Make BGP use papi_events.csv This was easier than trying to clean up the linux-bgp-preset-events.c file to have the proper file layout. * fc8a4168 src/linux-bgp.c: Fix some linux-bgp build issues. No one has tried compiling after all the PAPI 5.0 changes so many bugs slipped in. * c16ef312 src/ctests/perf_event_uncore.c: Fix type warnings in perf_event_uncore test. * 3947e9c8 src/ctests/perf_event_uncore.c: Put a bandaid on the perf_event_uncore test. Check for an Intel family 6 model 45 processor (sandybridge ep) before executing the test. 2012-09-27 * a23d95f8 src/papi.c src/papi.h src/papi_fwrappers.c...: Mark some comments @htmlonly. This cleans up what man pages are generated. 2012-11-07 * d239c350 src/Makefile.inc src/Rules.pfm4_pe: Factor out duplicate install code from Rules.pfm4_pe The Makefile.inc has a rule to installed shared libraries. However, Rules.pfm4_pe also has a slightly different set of rules to install code for shared libraries. This leads to the same shared library being installed under two different names. The duplicate code has been removed from Rules.pfm4_pe and a symbolic link has been added to ensure that any code that might have linked with libpapi.so.$(PAPIVER).$(PAPIREV).$(PAPIAGE) still runs. 2012-10-30 * fcc64ff9 src/papi_events.csv: Add PAPI_HW_INT event for IvyBridge 2012-10-26 * ef89fc56 src/papi_events.csv: MIC: update PAPI_FP_INS / PAPI_VEC_INS instruction We were using VPU_INSTRUCTIONS_EXECUTED for PAPI_FP_INS but really it's more appropriate for PAPI_VEC_INS This leaves PAPI_FP_INS undefined, which breaks a lot of the ctests. A long term goal should probably be modifying the tests to use another counter if PAPI_FP_INS isn't available (this affects Ivy Bridge too). 2012-10-25 * 975c03f1 src/perf_events.c: perf_event: fix granularity bug cut-and paste error in the last set of changes. Would have meant if you tried to explicitly set granularity to thread you'd get system instead. * 3cd3a62d src/configure src/configure.in src/ctests/Makefile...: Add perf_event_uncore ctest Also add a new type of ctest, perf_event specific In theory we should have configure only enable this if perf_event support is being used. * 5ee97430 src/perf_events.c: perf_event: add PAPI_DOM_SUPERVISOR to allowed perf_event domains perf_event supports this domain but since we didn't have it in the list PAPI wasn't letting us set/unset this. This is needed for uncore support, as for uncore domain must be set to allow monitoring everything. * c9325560 src/perf_events.c: perf_event enable granularity support Add support for PAPI_GRAN_SYS to perf_event. This is needed for uncore support. 2012-10-18 * 59d3d758 src/mb.h src/perf_events.c: Update the memory barriers It turns out PAPI fails on older 32-bit x86 machines because it tries to use an SSE rmb() memory barrier. (Yes, I'm trying to run PAPI on a Pentium II. Don't ask) It looks like our memory barriers were copied out of the kernel, which doesn't quite work because it expects some kernel infrastructure instead. This patch uses the definitions used by the "perf" tool instead. Also dropped the use of the mb() memory barrier on mmap tail write, as the perf tool itself did a while ago so I'm hoping it's safe to do so as well. It makes these definitions a lot simpler. 2012-10-08 * bcdce5bc src/perf_events.c: perf_event: clarify an error message The message was saying detecting rdpmc support broke, but the real error is that perf_events itself is totally broken on this machine and it's just rdpcm was the first code that tried to access it. 2012-10-02 * 3bb3558f src/mb.h: Update memory barries for Knights Corner Despite being x86_64 they don't support the SSE memory barrier instructions, so add a case in mb.h to handle this properly. 2012-10-01 * 38a5d74c src/libpfm4/README src/libpfm4/docs/Makefile src/libpfm4/docs/man3/libpfm_intel_atom.3...: Merge libpfm4 with Knights Corner Support * bf959960 src/papi_events.csv: Change "phi" to "knc" to match libpfm4 for Xeon Phi / Knights Corner support 2012-09-20 * d9249635 ChangeLogP501.txt RELEASENOTES.txt: Update releasenotes and add a changelog for 5.0.1 * a1e30348 man/man1/papi_avail.1 man/man1/papi_clockres.1 man/man1/papi_command_line.1...: Rebuild the manpages for a 5.0.1 release. papi-5.5.1/ChangeLogP500.txt0000644000307100002310000030757113013651444015430 0ustar yarkhangraduate2012-08-08 * 4b4f87ff ChangeLogP5000.txt: Changelog for PAPI5 * 6f208c06 doc/Doxyfile-common papi.spec src/Makefile.in...: Bump version numbers in prep for a 5.0 release. * c6fdbd11 release_procedure.txt: Update release_procedure.txt Change the order of when we branch git, so that the main dev branch gets some of the release related changes. 2012-04-17 * 97d4687f ChangeLogP440.txt: Pickup the changelog from papi 4.4 This was only included in the stable-4.4 branch. 2012-08-23 * 628c2b6e src/buildbot_configure_with_components.sh: Take debug out of the with several components build test config. When built with PAPI's memory wrapper routines, the threaded stress tests will sometimes get into poor performing situations. See trac ticket 148 for discussion. http://icl.utk.edu/trac/papi/ticket/148 2012-08-22 * 46faae8e src/ctests/overflow2.c src/ctests/overflow_single_event.c src/ctests/overflow_twoevents.c...: Move find_nonderived_event() from overflow_twoevents to test_utils and call it from overflow2 and overflow_single_event to insure that we're not trying to overflow on a derived event. * 3e7d8455 src/ctests/zero_smp.c: Fix a memory leak reported on the aix power7 machine. zero_smp.c did not unregister at the end of its thread function. * 3ad5782f src/perf_events.c: perf_events: fix segfault if DEBUG is enabled Was incorrectly using "i" as an index where it should be "0" in a debug statement. 2012-08-21 * a3cadbdb src/ftests/accum.F src/ftests/avail.F src/ftests/case1.F...: Take #2. Changing len_trim function in ftests to last_char. This time, I respect 72 char line limit. * c9db8fbf src/ctests/overflow_force_software.c: overflow_force_software was the only test that used a different hard_tolerance value (0.25) than the other overflow tests (0.75). This caused trouble on Power7/AIX. Now we are using the same hard_tolerance value in all overflow tests. * 70515343 src/ftests/accum.F src/ftests/avail.F src/ftests/case1.F...: Changed name of function len_trim to last_char. * 95168d79 src/components/cuda/linux-cuda.c: Cleanup cuda shutdown code. * The shutdown_thread code cleaned out the whole component's state. This has been split into shutdown_global for the whole component, and shutdown_thread is left to cleanup some control state info. * 56284f81 src/ctests/multiplex1_pthreads.c: Fix memory leaks in pthread multiplex tests. * aeead8b6 src/threads.c: Remove an outdated comment about _papi_hwi_free_EventSet holding INTERNAL lock * e598647b src/perf_events.c: perf_events: fix issue where we dereference a pointer before NULL check. Fix suggested by Will Cohen, based on a coverity report. * 4e0ed976 src/ctests/calibrate.c: Modify warning message to eliminate the word "error" Hopefully this will suppress it in buildbot outputs. * 50fbba18 src/ctests/api.c src/ftests/case2.F: Cleanup a few more warnings from the PAPI_perror change. * 1f06bf28 src/ftests/case2.F: Missed an instance of perror in the fortran code. * 93e6ae2c src/ftests/ftests_util.F: Fix warning in ftest_util.F 2012-08-20 * 60c6029e src/perf_events.c: perf_events: Update multiplexing code It * turns out the PERF_EVENT_IOC_RESET ioctl resets the count but not the multiplexing info. This means that when we fiddle with the events then reset them in check_scheduability(), we are not really resetting things to zero. The effect might be small, but since the new multiplex code by definition is always scheduable, then let's skip the test if multiplexing. * 9079236c src/ctests/zero.c: Change error reporting so FLOPS > 100% above theoretical FAIL and FLOPS > 25% above theoretical WARN. 2012-08-18 * 980558af src/papi_internal.c: papi_internal: fix memory leak When I made some changes a while back I forgot to free ESI->NativeBits properly. This was causing memory leak warnings on buildbot. 2012-08-17 * 83a14612 src/perf_events.c: perf_events: more cleanups and comments We really need to go back and figure out in more detail what the profile/sampling/overflow code is doing. * 7cafb941 src/perf_events.c: perf_events: more cleanups and comments * e9e39a4b src/perf_events.c: perf_events: disable kernel multiplexing * before 2.6.34 It turns out even our simple multiplexing won't work on kernels before 2.6.34, so fall back to sw multiplex in that case. * 05801901 src/perf_events.c: perf_events: more cleanup and comments * 268e31d7 src/perf_events.c: perf_events: more cleanup and commenting * d62fc2bf src/perf_events.c: perf_events: more cleanup and comments * fb0081bc src/perf_events.c: perf_events: more cleanups and comments * a1142fc8 src/perf_events.c: perf_events: cleanup and comment the kernel * bug workarounds * b8560369 src/perf_events.c: perf_events: minor cleanups and new comments * 6c320bb2 src/perf_events.c: perf_events: fix some debug messages I forget to test with --with-debug enabled * f7a3cccf src/perf_events.c: perf_events: enable new read_code This makes the read code much simpler. It finishes the multiplexing changes. To avoid complication, we no longer enable PERF_FORMAT_ID as reading that extra info is unnecessary with the current implementation. This passes all the tests on a recent kernel, but on 2.6.32 there are still a few issues. * 15749cff src/ctests/all_events.c src/ctests/all_native_events.c: Fix warning in all_events and all_native_events. In the perror semantic change, several strings for use in the old interface were left. 2012-08-16 * afdd25fa src/perf_events.c: perf_events: always enable kernel multiplexing The new code should work on any kernel version. * 9f5e23ae src/perf_events.c: Rewrite multiplex support. Drop support for the former "partitioned" multiplexing, as we could never use it. Instead use the simple/braindead model. This still needs more work, as sometimes reads are failing. * cdd29909 src/ftests/strtest.F: Fix strtest.F ftest It was still making some assumptions about PAPI_perror() writing to a string rather than directly to standard error. * 565f60b3 src/papi_internal.c: Missing code to set num_error_chunks to 0 The new _papi_hwi_cleanup_errors() function was not resetting num_error_chunks to 0, leading to a segfault in the fmultiplex1 test. 2012-08-02 * bb85bafd src/genpapifdef.c src/papi.c src/papi_common_strings.h...: Remove usage of _papi_hwi_err. Move PAPI over to storing errors in a runtime list. * Functions to add/lookup errors. * Generate the list of PAPI_E* errors at library_init time. * genpapifdef pulled the values for the PAPI_* error return codes from the _papi_hwi_err structure at configure time. Since this is now built at run-time, I added the appropriate values to genpapifdef's builting describe_t table. See : _papi_hwi_publish_error _papi_hwi_init_errors For usage hints. 2012-08-10 * e27af085 src/perf_events.c: perf_event: rename BRAINDEAD_MULTIPLEXING It is now "simple_multiplexing" and is a variable not an #ifdef This is needed before perf_event multiplexing can be sorted out. It's unclear if it actually works anyway. * 7f8e8c58 src/perf_events.c: perf_event: remove context "cookie" field It was a bit of overkill, we just need an initialized field. Also revamp how context and control are initialized. * 8cb8ac6d src/perf_events.c: perf_event: move all event specific info to * the control state previously half was in the context state and half in the control state perf_event has a strange architecture with each event being created having its own fd, which is context wide. In PAPI though we usually only have one eventset (control state) active at once, so there's no need to have the context be aware of this. 2012-08-09 * 8d7782cb src/perf_events.c: perf_event: rename evt_t to perf_event_info_t This just makes the code easier to follow. * 349de05c src/perf_events.c: perf_event: remove the superfluous per_event_info_t structure 2012-08-08 * da8ad0a2 src/ctests/all_native_events.c src/ctests/get_event_component.c src/utils/native_avail.c: Fix warnings about PAPI_enum_cmp_event() return not being checked Reported by coverity checker via Will Cohen Harmless warnings, and now the checker will likely complain about the value being checked but ignored. * b4719888 src/papi_user_events.c: Fix unused value in papi_user_events.c Reported by Coverity checker by Will Cohen * 6a8f255c src/utils/event_chooser.c: remove unused * PAPI_get_component_info() call in event_chooser Reported by Will Cohen from coverity checker 2012-08-06 * 62cda478 src/genpapifdef.c src/papi_common_strings.h src/papi_internal.c...: Remove usage of _papi_hwi_err. genpapifdef pulled the values for the PAPI_* error return codes from the _papi_hwi_err structure at configure time. Since this is now built at run-time, I added the appropriate values to genpapifdef's builting describe_t table. 2012-08-02 * d11259f3 src/papi.c src/papi_internal.c src/papi_internal.h...: Move over to generating the list of PAPI errors at library_init time. * 097ffc44 src/papi_internal.c: Functions to add/lookup errors. 2012-08-07 * 2530533f src/papi_events.csv: tests/zero fails on Power7 due to PAPI_FP_INS Error of 50%. Preset definition has been redefined and test now passes. * 8e17836f src/components/appio/Rules.appio src/components/appio/appio.c src/components/appio/appio.h...: We now intercept recv(). The support for recv() requires dynamic linkage. For static linkage, recv is not intercepted. 2012-08-06 * 8b1eb84c src/perf_events.c: perf_events: some whitespace cleanup and extra comments * f10edba6 src/perf_events.c: perf_events: MAX_READ was no longer being used, remove it * 08c06ed1 src/perf_events.c: perf_event event_id is actually 64-bit, so make our copy match * a33e8d9c src/perf_events.c: Rename context_t pe_context_t in perf_events.c Makes the code a bit clearer and matches how other components name things. * 96ce9dcd src/perf_events.c: Rename control_state_t pe_control_state_t This makes the code a bit easier to follow and matches how other components name things. 2012-08-03 * 4c5dce7f src/ctests/zero.c: Beef up error reporting. * 83b5d28a src/ctests/cycle_ratio.c: Have the cycle_ratio test skip if PAPI_REF_CYC event is not defined. 2012-08-02 * 25b1ba41 src/ctests/cycle_ratio.c: Removed all TESTS_QUIET blocks. They aren't needed because tests_quiet() overloads printf. We should probably remove TEST_QUIET blocks in ALL tests at some point for code clarity… * 8777d7d4 src/ctests/zero.c: Fixed error reporting. The error computation was inside a TESTS_QUIET block and wasn't getting executed when run quietly. Thus this test always passed on buildbot, even when it didn't. * 006fe8e9 src/ctests/Makefile: Fix typo in cycle_ratio make line. * 88e6d6a4 src/aix.c src/aix.h: Setting number of multiplex counters back to 32 for AIX. Before it was set equal to number of max HW counters. This caused ctests/sdsc-mpx to fail. * ab78deda src/papi_events.csv: ctests/calibrate on Power7/AIX failed with a 50% error all the way through. Updated the preset FP_OPS with a more appropriate definition. Now the calibrate errors range from 0.0002 to 0.0011% for double and single precision * fadce32f src/ctests/calibrate.c: Modify calibrate test in two ways: 1. add a -f flag to suppress failures and allow test to run to completion; 2. change error detection to allow warnings above MAX_WARN and failures above MAX_FAIL. Currently set to 10% and 80% respectively. This allows speculative over counting to pass with warning rather than fail completely. * 8a39ac9d src/papi_events.csv: LST_INS for Power7 was defined from 3 native events that cannot be counted together at the same time. Caused ctests/all_events to fail. Updated the preset with a more appropriate definition. * cdc16e5d src/papi_events.csv: L1_DCA for Power7 was defined from 3 native events that cannot be counted together at the same time. That caused ctests/tenth to fail. Updated the preset with a more appropriate definition. 2012-08-01 * 2bf44d13 src/papi_internal.c src/perf_events.c: icc does not like arithmetic on void pointers. Added cast to unsigned char* when arithmetic was being performed on void pointers in papi_internal and perf_events. * 7825ec14 src/ctests/api.c src/ctests/attach2.c src/ctests/attach3.c...: Modify tests that FAIL if PAPI_FP_OPS or PAPI_FP_INS not implemented. Now they will warn and continue. This is specifically to accommodate the brain-dead IvyBridge implementation. * fd70a015 src/testlib/test_utils.c: Re-writing of test_utils introduced new bugs that caused ctests/tenth to fail. test_events struct lists the same event twice (MASK_L1_DCW), hence PAPI_add_event() fails because it's forced to add the same preset twice. * 74ece3a0 src/run_tests.sh: run_tests.sh was clobbering $EXCLUDE variable if $CUDA was defined. Changed to add entries from run_tests_exclude_cuda.txt to $EXCLUDE which should already contain entries from run_tests_exclude.txt instead of replacing the entries already contained. * 11ed2364 src/libpfm4/config.mk: Added check in libpfm4/config.mk to check if using icc. If so, the -Wno-unused-parameter flag will no longer be used because icc does not provide it and provides no alternative. * dedf73f6 src/papi_user_events.c: fget() returns an int it should be treated as an int The coverity scan flagged that the int return by fget was stored in a char. The main concern with this is the EOF that fget() could return is -1. Do not want to mess up that value by typecasting to char and then back to int. * c4fcbe7e src/ctests/kufrin.c: Check return values of PAPI_get_cmp_opt() and calloc A coverity scan showed that PAPI_get_cmp_opt() could potentially return a negative number. Also it is good form to check the return value of calloc to ensure it is a non-null pointer. * e89d6ffa src/testlib/test_utils.c: Clean up test_print_event_header() There were a couple warnings flagged by coverity on test_print_events_header(). The function now checks for error conditions flagged by PAPI_get_cmp_opt() and also frees memory allocated by a calloc() function. * c81d8b60 src/threads.h: Eliminate deadcode from threads.h If HAVE_THREAD_LOCAL_STORAGE is defined, a portion of the _papi_hwi_lookup_thread() will never be executed. This patch make either one section or the other section of code be compiled. This will eliminate a coverity scan warning about unreachable code. * f70f3f56 src/ctests/all_native_events.c: Eliminate unused variable in ctests/all_native_events.c Coverity identified a variable that was set but never used in all_native_events.c. This patch removes the unused variable to eliminate that warning. * a9f29840 src/components/appio/appio.c: A couple places in appio.c used the FD_SET() without initializing the variable. Coverity scan pointed out this issue. * 9e535ae2 src/components/rapl/linux-rapl.c: A Coverity scan pointed out that read_msr() could potentially use an invalid value of fd for pread(). Need to check the value of fd before using it. * 7b55c675 src/components/rapl/linux-rapl.c: The arrays used for initialization were hard coded to 1024 packages. Want to avoid hard coding that so the day when machines with 1025 packages are available is a non-event. Also changed the initialization code to avoid having the initialization be O((number of packages)^2) in time complexity. 2012-07-27 * 3703995a src/papi_internal.c: Fix the component name predending code. When presented with a NULL component .short_name, the code did the wrong thing. * 5258db8b src/components/cuda/linux-cuda.c: Fix a warning in cuda. 2012-07-26 * ddd6f193 src/ctests/Makefile src/ctests/cycle_ratio.c: Add a test to compute nominal CPU MHz from real cycles and use PAPI_TOT_CYC and PAPI_REF_CYC to compute effective MHz. Warns if PAPI_REF_CYC is zero, which can happen on kernels < ~3.3. * fab5e9ef src/papiStdEventDefs.h src/papi_common_strings.h src/papi_events.csv: Add PAPI_REF_CYC preset event. Define it as UNHALTED_REFERENCE_CYCLES for all Intel platforms on which this native event is supported. 2012-07-25 * 8b9b6bef src/papi_events.csv: Modify SandyBridge and IvyBridge tables: SandyBridge FP_OPS only counts scalars; SP_OPS and DP_OPS now count correctly, including SSE and AVX. IvyBridge can't count FP at all; adjustments made to eliminate event differences with SandyBridge. 2012-07-26 * 5b11c982 src/components/cuda/linux-cuda.c: Fix the cuda component. The cuda component prepended CUDA. to all its event names, this is no longer the case. 2012-07-25 * db5b0857 src/papi_events.csv: Added 2 new preset definitions for BGQ. Note, these presets use the new feature where a generic event mask together with an ORed opcode string is used. This won't work until the new Q driver is released (currently scheduled for end of August). 2012-07-24 * af7cd721 src/components/coretemp/linux-coretemp.c src/components/coretemp/tests/coretemp_pretty.c src/components/cuda/linux-cuda.c...: Enforce all our components to use the same naming. We setteled on :'s as inter-event seperators. This also touches a few of the components' tests, we changed the name field so their searches needed help. 2012-07-23 * 57aeb9d4 src/papi_internal.c: Prepend component .short_name to each event name. Use ::: as a sep. 2012-07-24 * 762e9584 src/ctests/multiplex2.c src/sw_multiplex.c: Fix multiplex2 test It complained if it tried to add a multiplex event and PAPI properly told it that it couldn't. * 531870f1 src/papi_internal.c: Add sanity check at component init time Looks for num_cntrs being larger than num_mpx_cntrs which doesn't make much sense. * 53ad0259 src/extras.c src/genpapifdef.c src/papi.c...: Rename PAPI_MAX_HWCTRS to PAPI_EVENTS_IN_DERIVED_EVENT Hopefully this will make things a little less confusing. * 700af24b src/papi_internal.c: Change EventInfoArrayLength to always return num_mpx_cntrs Things should be consistently using num_mpx_cntrs rather than num_cntrs now. Issue reported by Steve Kaufmann * d1570bec src/sw_multiplex.c: Fix sw_multiplex bug when max SW counters is less than max HW counters this was causing kufrin and max_multiplex to fail * f47f5d6a src/aix.c src/components/appio/appio.c src/components/bgpm/CNKunit/linux-CNKunit.c...: Remove PAPI_MPX_DEF_DEG It was not well documented and being used in confused ways all over the code. Now there is a different define PAPI_MAX_SW_MPX_EVENTS used by the software multiplex code. All other components have had the value replaced with just the maximum number of counters. If a component can handle its own (non-software) multiplexing it is up to it to set .num_mpx_cntrs to a value that's different from .num_cntrs * 0d83f5db src/papi_internal.c src/papi_internal.h: Split NativeBits off of NativeInfoArray in EventSet previously we were doing some crazy thing where we allocated both at once and then split them afterward. The new code is easier to follow. * 98f2ecbd src/papi_internal.c: Clean up EventSet creation Sort out which sizes are used for allocating which structures. * e1024579 src/Makefile.inc src/multiplex.c src/multiplex.h...: Rename the multiplex files to be sw_multiplex That way it's more clear the stuff included only relates to software multiplexing, not generic multiplexing. * a6adc7ff src/multiplex.h src/papi_internal.c src/papi_internal.h: Move some sw-multiplex specific terms out of papi_internal.h and into multiplex.h 2012-07-23 * 1ddbe117 src/components/README: Added note that lmsensors component requires lmsensors version >=3.0.0 * 94676869 src/components/appio/appio.c src/components/appio/tests/appio_test_pthreads.c: proper checking of return codes in response to tests using coverity * ea958b18 src/components/appio/tests/appio_list_events.c src/components/appio/tests/appio_values_by_code.c: As component name in table has been changed from appio.c to appio, we now use appio in the tests. 2012-07-20 * f212cc34 src/components/appio/appio.c src/components/coretemp/linux-coretemp.c src/components/coretemp_freebsd/coretemp_freebsd.c...: Add .short_name entries to each component. * 1e755836 src/papi_libpfm4_events.c src/perf_events.c: Fix use-after-free bug in perf_events.c This turned up in the ctests/flops test, and Valgrind made it easy to track down. * 4580ed1d src/perf_events.c: Update perf_event.c rdpmc support Use the libpfm4 definition for mmap rather than our custom one, now that libpfm4 has been updated * 47558b2c src/libpfm4/examples/showevtinfo.c src/libpfm4/include/perfmon/perf_event.h src/libpfm4/lib/pfmlib_intel_nhm_unc.c...: Import current libpfm4 from libpfm4 git It has some minor uncore fixes plus the header changes needed for rdpmc. 2012-07-17 * 65d4c06c src/linux-common.c: Reorder statements to ensure the fclose() are performed Coverity pointed out that it was possible for resources to be leaked in linux-common.c if the fscanf() encountered error. This reordering of the statements ensures that the fclose() calls are done regards of the results of the fscanf() functions. 2012-07-18 * 7bf071ff src/papi_user_events.c: Ensure that load_user_event_table() frees files and memory on error A Coverity scan showed that an error condition in load_user_event_table() function would exit the the function without closing the table file or freeing allocated memory. This patch addresses those issues. 2012-07-17 * 1ba52e35 src/components/stealtime/linux-stealtime.c: Ensure that read_stealtime() closes the file in case of an error condition A Coverity scan showed that an error condition could cause read_stealtime() to exit without closing the file. This patch ensures that the file is closed regardless of success or failure. 2012-07-18 * f37f22e5 src/papi_libpfm4_events.c: Fix warning in papi_libpfm4_events.c We were setting a value but never using it. * 8e8401bc src/testlib/test_utils.c: Remove unused variable in test_utils.c Most of the machines in buildbot were complaining about this. * 133ce6a9 src/linux-timer.c: Add missing papi_vector.h include to linux-timer.c This was breaking on PPC Linux 2012-07-17 * 6fd3cedd src/perf_events.c: Fix perf_events.c warnings reported by ICC * 21c8f932 src/perfctr-x86.c: Fix perfctr-x86 build with debug enabled * 08f76743 src/configure src/configure.in src/linux-bgq.c: Attempt to fix linux-bgq compilation error. It turns out BGQ uses the standard linux-context.h header * 43457f4f src/linux-bgq.c: Made check for opcodes more robust. * d58116b4 src/perf_events.c: More cleanups of perf_events.c file * 409438b7 src/freebsd-context.h src/freebsd.c src/freebsd.h: Fix FreeBSD compile warnings Similar to the perfctr issues. * 1e6dfb02 src/aix.c src/aix.h: Fix AIX build warnings They were similar in cause to the perfctr issues. * 3d0b5785 src/Rules.perfmon2 src/components/appio/appio.c src/components/bgpm/CNKunit/linux-CNKunit.h...: Remove papi_vector.h include from papi_internal.h There were some semi-circular dependencies that came up with the context split changes. The easiest way to fix things for perfctr was just move papi_vector.h out to be included explicitly. This touches a lot of files because a lot of files include papi_internal.h This should also fix the perfctr and perfmon2 builds that were broken yesterday. 2012-07-16 * a7a14a5b src/ctests/zero.c src/testlib/test_utils.c: Modify zero test to warm up processor before measuring events, and report timing errors as signed deviations. Modify test_utils add_two_events code to check for errors after adding nominally valid events. This is a more rigorous test than just counting available registers. * de0860d3 src/perf_events.c: Remove perf_events.h module header It's no longer needed, everything important is merged into the perf_events.c file. * 22975f14 src/perf_events.c: Remove perf_event SYNCHRONIZED_RESET code This was never defined and never used, just remove the code. * 48750b8c src/perf_events.c: Remove papi_pe_allocate_registers On perf_event this code wasn't really doing anything useful, as update_control_state would end up re-doing any possible tests we could want to do here. * 1775566f src/Makefile.in src/Makefile.inc src/Rules.pfm4_pe...: Remove "include CPUCOMPONENT" from papi_internal.h This was the last major dependency on CPU component in common PAPI code. It was mostly necessary for the ucontext definitions when trying to get the instruction pointer when doing sampling. This change creates new OS-specific header files that handle the ucontext related code, and has papi_internal.h include that instead. * 969ce035 src/Rules.pfm4_pe src/Rules.pfm_pe src/configure...: Make perf_event libpfm4 only perf_event libpfm3 support is not really needed anymore and supporting it was cluttering up the perf_event component. 2012-07-13 * adad1d2a src/perf_events.c: Add init time error messages to perf_event component * 827ccc07 src/perf_events.c: Add perf_event rdpmc / fast_real_timer detection Currently we need a custom copy of struct perf_event_mmap_page because the version included with libpfm4 doesn't define the fields we need yet. * 4f82fe94 src/perf_events.c: Read in paranoid info on perf_events This indicates whether a regular user can read CPU-specific or system-wide measurements. * 03080450 src/perf_events.c: Add proper perf_event detection Using the official /proc/sys/kernel/perf_event_paranoid file * 6e71d3f7 src/linux-bgq.c: Updated BGQ opcode stuff; cleaned up code. 2012-07-11 * 3114d3dc src/multiplex.c src/papi_internal.c src/perf_events.c: Minor documentation improvements Plus fixes some typos 2012-07-09 * b60c0f0c src/perf_events.c: Minor cleanups to perf_events.c * 075278a0 src/aix.c src/freebsd.c src/linux-bgp.c...: Change return value for .allocate_registers For some reason it returned 1 on success and 0 on failure. Change it so you return PAPI_OK on success and a PAPI error on failure, to better match all of the other component vectors. * 29d9e62b src/testlib/test_utils.c: Fixed the print_header routine to report an error message if counters are not found, instead of a negative counter number. Tested by forcing the return value negative; not by running on a Mac, where the error first appeared. * 74257334 src/ctests/Makefile src/ctests/remove_events.c: Add remove_events test This just makes sure EventSets still work after an event has been removed. This is probably covered by other more elaborate tests, but I needed a simple test to make sure I wasn't breaking anything. * 1372714f src/papi.c src/papi_internal.c src/papi_internal.h: Clean up, rename, and comment _papi_hwi_remap_event_position I've found this section of code to be confusing for a long time. I think I finally have it mostly figured out. I've renamed it _papi_hwi_map_events_to_native() to better describe what it does. The issue is that the native event list in an EventSet can change at various times. At event add, event remove, and somewhat unexpectedly, whenever ->update_control_state is called (a component can re-arrange native events if it wants, to handle conflicts, etc.) Once the native event list has been changed, _papi_hwi_map_events_to_native() has to be called to make sure the events all map to the proper native_event again. Currently we have the _papi_hwi_map_events_to_native() calls in odd places. It seems to cover all possible needed locations, but analyzing that we do takes a lot of analysis... * f1b837d8 src/papi.c: Remove unused variable in papi.c * 541bcf44 src/papi_internal.h: Update commens in papi_internal.h Some of the EventSetInfo comments were out of date. * e6587847 src/papi.c src/papi_internal.c src/papi_internal.h: Remove unused paramater from _papi_hwi_remap_event_position The mysterious _papi_hwi_remap_event_position function had a "thisindex" field that was ignored. This will possibly speed PAPI_start() time as it was running a loop over num_native_events on _papi_hwi_remap_event_position even though each call did the same thing since the value being passed was ignored. * 3ad3d14b src/papi_internal.c: Clean up and comment add_native_events in papi_internal.c I'm chasing some weird perf_events behavior with the papi_event_chooser. The add_native_events code is very hard to understand, working on commenting it more. * 4e5e7664 src/utils/event_chooser.c: Fix coverity warning in papi_event_chooser * 666249a8 src/jni/EventSet.java src/jni/FlipInfo.java src/jni/FlopInfo.java...: RIP Java. Java PAPI wrappers have not been supported for years (2005?). They are being removed to declutter the source. * e18561fc src/papi_preset.c: Update cmpinfo->num_preset_events properly This value wasn't being set if we were reading the presets directly from the CSV file. * 290ab7c3 src/utils/component.c: Have papi_component_avail report counter and event info * 7c421b9c src/testlib/test_utils.c src/utils/native_avail.c: Remove counter number from the testlib header. The header was only reporting number of counters for the CPU component, even though the header is printed for many utils and the CPU component might not even be involved. This could be a bit confusing, so remove it. * 26432359 src/darwin-common.c src/darwin-memory.c: Improve OSX support This properly detects CPU information now. You can get results like this: Available native events and hardware information. - PAPI Version : 4.9.0.0 Vendor string and code : GenuineIntel (1) Model string and code : Intel(R) Core(TM) i5-2435M CPU @ 2.40GHz (42) CPU Revision : 7.000000 CPUID Info : Family: 6 Model: 42 Stepping: 7 CPU Max Megahertz : 2400 CPU Min Megahertz : 2400 CPUs per Node : 0 Total CPUs : 4 Running in a VM : no Number Hardware Counters : -4 Max Multiplex Counters : -4 - 2012-07-08 * 845d9ecb src/Makefile.inc src/configure src/configure.in...: Add Mac OSX support This is enough that things compile and simple utilities run. No CPU perf counter support. 2012-07-06 * ff6f9ab4 src/linux-bgq.c: missed to delete a debug output. 2012-04-17 * 12e9a11a RELEASENOTES.txt: Release notes for the 4.4 release. 2012-07-06 * ac2eac56 src/papi.c src/papi.h: Add a PAPI_disable_component_by_name entry point. * 8c490849 src/components/coretemp_freebsd/coretemp_freebsd.c src/freebsd.c: Fix FreeBSD to work I'm not sure how it ever worked in the past. With these changes I can at least do a papi_component_avail and a papi_native_avail and get sane results * 108b5ce6 src/freebsd.c src/freebsd.h src/freebsd/map-atom.c...: Fix FreeBSD build some of the recent changes broke the FreeBSD build * 40a60f0a src/linux-bgq.c src/linux-bgq.h: Added BGQ's opcode and generic event functionality to PAPI. For BGQ there are multiple ways to define presets. The naive way is to derive from multiple events. This eats up multiple counters and we lose sample capability as well as overflow capability. On the other side, some events come with multiple InstrGroup derived in the field. If that's the case we can use a generic event and opcodes to filter multiple groups in a single counter. This is not working properly yet due to a known error in BGPM. Bgpm_AddEvent() does not work properly when multiple generic events are added to an EventSet. The BGPM folks have been made aware of this issue, they confirmed the error, and they are currently working on a fix. * 6f72b70f src/papi_events_table.sh: Make this script robust enough to handle any line ending, including CR (Mac), CRLF (Windows), and LF (Unix). It appears that google mail now automagically converts attached files to CRLF format. * 765ed0d2 src/papi_internal.c: Fix a type warning in the UE code. * 94bc1b15 src/MACROS: Remove the MACROS file it held out of date info and hasn't been touched since 2004 * d19e73ba src/ctests/Makefile src/ctests/clockcore.c src/testlib/Makefile...: Move the clockcore.c file from ctests to testlib it's common code used by multiple tests, including some in the utils directory also add a function definition to fix a build-time warning * 1101a6aa src/aix-lock.h src/aix.h src/configure...: Make papi_lock.h changes for non Linux architectures 2012-07-05 * 3b82b03d src/Makefile.in src/Makefile.inc src/aix.c...: Make the PAPI locks be tied to OS, not to CPU There is not a papi_lock.h file that when included gets the proper lock include for the OS. This fixes a lot of previous build hacks where a CPU component was needed in order for locks to work. * 0632ef42 src/threads.c: Fix spurious init_thread call in threads.c threads.c was calling init_thread() on all components, even ones that were disabled Fix it to honor the disable bit, as well as for shutdown_thread(). This was causing perfctr disable code to not work. * 19d9de7f src/Makefile.in src/Makefile.inc src/Rules.pfm4_pe...: Replace SUBSTRATE with CPUCOMPONENT in build This was mostly a configure/build change but it also cleaned up some cases where we were including SUBSTRATE where we didn't have to. * 829780db src/solaris-common.c src/solaris-common.h src/solaris-niagara2.c...: Move some common solaris code to solaris-common * 681ef027 src/configure src/configure.in src/solaris-memory.c...: Merge solaris-memory.c and solaris-niagara2-memory.c * bbd41743 src/solaris-ultra/get_tick.S src/solaris.h: Remove solaris-ultra/get_tick.S Nothing was using it. * dc3b6920 src/papi_sys_headers.h src/solaris.h: Remove papi_sys_headers.h Solaris was the only thing including it, and it wasn't really using it. * 7ccfa9df src/Makefile.in src/Makefile.inc src/configure...: Move move OS specific code into the new OSFILESSRC Linux in particular was using MISC for this. * 6f16c0c5 src/configure: Re-run autoconf to pickup the substrate=>component change. * cfff1ede src/Makefile.in src/Makefile.inc src/configure...: Remove MEMSUBSTR In reality, what we want instead of a Memory Substrate is an idea of the OS-specific common code that includes the memory substrate. This change adds OSFILESSRC and OSFILESOBJ to handle this case in configure * ca4729e6 src/configure.in: Separate out MEMSUBSTR and make it per-OS * 3148cba5 src/Matlab/PAPI_Matlab.dsp src/ctests/calibrate.c src/ctests/flops.c...: RIP Windows, remove the windows support code. Windows has not been activly supported since the transition to Component PAPI (4.0) This cleans up the code-base. 2012-07-03 * a366adf7 src/papi.c src/utils/error_codes.c: Change PAPI_strerror and PAPI_perror to behave more like thir POSIX namesakes. PAPI_error_descr is made redundant and removed as a result. 2012-07-05 * 7df46f81 src/Rules.pfm src/aix.c src/components/coretemp/linux-coretemp.c...: Move uses of PAPI_ESBSTR to PAPI_ECMP I left PAPI_ESBSTR defined too for backward compatability. Also some of the changes update PAPI_ESBSTR to be a more relevant error code, it one is available. 2012-07-03 * fdb348ad src/components/coretemp_freebsd/coretemp_freebsd.c src/components/example/example.c src/components/net/linux-net.c...: A few more substrate removals * 791747c1 src/cpus.c src/papi.h src/perf_events.c...: Fix bugs introduced by substrate -> component change Fix some stupid compile bugs that I missed. * 79b01a47 src/aix.c src/components/appio/appio.c src/components/bgpm/CNKunit/linux-CNKunit.c...: More substrate -> component changes This changes the vectors .init_substrate -> .init_component .shutdown_substrate -> .shutdown_substrate .init -> .init_thread .shutdown -> .shutdown_thread hopefully this will make the code clearer. * 02a10d71 src/Makefile.inc src/aix.c src/cpus.c...: Rename "substrate" to "component" This first pass only re-names things in comments. 2012-07-02 * c4bbff1c src/papi.c src/papi.h: Minor documentation fixes Found when writing up the PAPI 5.0 changes document 2012-06-30 * f9cb7346 src/components/vmware/vmware.c: Fix vmware component apparently I forgot to test the build with the vmguestlib support disabled. 2012-06-22 * 599040d1 src/components/coretemp/linux-coretemp.c src/components/rapl/linux-rapl.c src/components/stealtime/linux-stealtime.c...: Fix libpfm4 ntv_event_to_info event_info_t on other components This was actually a widespead problem due to cut-and-paste. * 2b51b439 src/papi_libpfm4_events.c: Properly fix libpfm4 ntv_event_to_info event_info_t event value The previous fix was subtly wrong. This is the proper fix, which is to do nothing inside of papi_libpfm4_events.c because papi_internal.c does the right thing for us and we were overwriting that with the wrong value. * a4f576bf src/ctests/overflow_allcounters.c src/testlib/papi_test.h src/testlib/test_utils.c: Clean up overflow_allcounters code While tracking down a previous issue I also cleaned up the overflow_allcounters test code to use some of the new interfaces. * 6903e053 src/papi_libpfm4_events.c: Fix libpfm4 ntv_event_to_info event_info_t event value The recently added libpfm4 ntv_event_to_info function was not properly oring PAPI_NATIVE_MASK to the event value in the event_info_t struct. That means if you tried to use that event value to add an event it would fail. The overflow_allcounters test broke because of this. * 420c3d11 src/ctests/Makefile src/ctests/disable_component.c src/papi.c...: Add PAPI_get_component_index() and PAPI_disable_component() PAPI_get_component_index() will return a component index if you give it the name of a component to match. This saves you having to iterate the entire component list looking. PAPI_disable_component() will manually mark a component as disabled. It has to be run before PAPI_library_init() is called. * 11946525 src/aix.c src/components/cuda/linux-cuda.c src/components/example/example.c...: Standardize component names to not end in .c We were being inconsistent; the time to make them all be the same is now before 5.0 gets out. 2012-06-21 * 274e1ad8 src/components/vmware/tests/Makefile: Fix cut-and-paste error in the vmware component Makefile * 85d6438d src/utils/event_chooser.c: Update papi_event_chooser to work with components Now you can specify events from components and it will tell you all the other events on that component that can run with it. Previously the utility was limited to the CPU component (0) only. * 3c2fcc83 src/papi_libpfm3_events.c src/papi_libpfm4_events.c src/perf_events.c: Hook up .ntv_code_to_info on perf_event * 36e864b3 src/papi_libpfm4_events.c src/papi_libpfm_events.h src/perf_events.c: Enable support for showing extended umasks on perf_event With this change, papi_native_avail now shows event umasks such as :u, :k, :c, :e, and :i. (user, kernel, cmask, edge-trigger, invert) Thes are boolean or integer events. They were supported by previous PAPI but they were never enumerated. * 8f3e305e src/components/coretemp/linux-coretemp.c: Fix cut-and-paste error in linux-coretemp.c that could lead to wrong size being copied * 0eedd562 src/libpfm4/lib/events/intel_atom_events.h src/libpfm4/lib/events/intel_core_events.h src/libpfm4/lib/events/intel_coreduo_events.h...: Import most recent libpfm4 git This fixes an issue where there can be confusion between :i and :i=1 type events. It also has initial support for Uncore, though you need a specially patched kernel and PAPI does not support it yet. * 2f86ec78 src/components/appio/tests/Makefile src/components/appio/tests/appio_test_blocking.c .../appio/tests/appio_test_fread_fwrite.c...: - Fixed tests verbosity by using TESTS_QUIET macro - Fixed Makefile to only include necessary tests for automatic builds (skip blocking tests that read from stdin) * 6936b955 src/components/appio/README src/components/appio/appio.c src/components/appio/appio.h...: Added polling of read/write descriptor to check which operations would block. * 48cacccf src/papi.h: Add back PAPI_COMPONENT_INDEX() for backward compatability It turns out some people were using this for cases other than enumeration. The proper way to do things now is to use PAPI_get_event_component() which is what this PAPI_COMPONENT_INDEX() now maps to. * d1ed12b7 src/ctests/Makefile src/ctests/get_event_component.c src/papi.c...: Add PAPI_get_event_component() This function returns the component an event belongs to. It also adds a test to test this functionality. 2012-06-20 * ffccf633 src/papi.h: Add component_type field to .cmp_info The idea is we'll specify CPU, I/O, GPU, hardware, etc. * 9998eecc src/components/lmsensors/Rules.lmsensors: Another lmsensors build fix * caa94d64 src/components/lmsensors/linux-lmsensors.c: Update lmsensors component to actually compile. I finally found a machine with lmsensors installed. * fbcde325 src/components/lmsensors/linux-lmsensors.c src/components/lmsensors/linux-lmsensors.h: Update lmsensor component Unlike the other components it hadn't been updated to PAPI 5 standards. Also, it was wrongly de-allocating all state in "_shutdown" rather than "_shutdown_substrate" which was causing double-frees during tests. * 0d3c0ae2 src/papi_internal.c: Add some extra debugging to _papi_hwi_get_native_event_info * 5961c03d src/aix.c src/components/nvml/linux-nvml.c src/ctests/subinfo.c...: Remove cntr_groups from .cmp_info This information is better exposed by enumeration. * 2b4193fd src/utils/event_chooser.c: Cleanup and comment event_chooser code * 7f9fab2b src/ctests/all_native_events.c: Cleanup and add comments to all_native_events.c * a245b502 src/components/nvml/linux-nvml.c src/ctests/subinfo.c src/freebsd.c...: Remove profile_ear from .cmp_info The CPU components should handle this internally. * bca07f3c src/papi.c: Add comments to the PAPI_sprofil code. * b1e2090c src/papi.c: Minor papi.c cleanups Fix some minor cosmetic things, including a typo in a comment. * 8f3aef4a src/ctests/subinfo.c src/papi.h: Remove opcode_match_width field from .cmp_info This should be exposed via enumeration and not by a field in the generic cmp_info structure. * 047af629 src/components/nvml/linux-nvml.c src/ctests/subinfo.c src/papi.h...: Remove cntr_OPCM_events field from .cmp_info This should be exposed via enumeration and not by a field in the generic cmp_info structure. * 3f1f9e10 src/components/nvml/linux-nvml.c src/ctests/subinfo.c src/papi.h...: Remove cntr_DEAR_events field from .cmp_info This should be exposed via enumeration and not by a field in the generic cmp_info structure. * 962c642a src/components/nvml/linux-nvml.c src/ctests/subinfo.c src/papi.h...: Remove cntr_IEAR_events field from .cmp_info This should be exposed via enumeration and not by a field in the generic cmp_info structure. * 5aa7eac1 src/components/nvml/linux-nvml.c src/ctests/subinfo.c src/papi.h...: Remove instr_address_range from .cmp_info This feature should be deteced via enumeration, not via a flag in the generic .cmp_info structure. * 1bf68d5d src/components/nvml/linux-nvml.c src/ctests/subinfo.c src/papi.h...: Remove data_address_range field from .cmp_info The proper way to detect this feature is via enumeration. 2012-06-19 * 90037307 src/linux-context.h: Change Linux from using "struct siginfo" to "siginfo_t" This conforms to POSIX, and fixes newer Fedora where struct siginfo is no longer supported. This can in theory break on older setups (possibly kernel 2.4). If that happens, we need to somehow detect this using autoconf. 2012-06-18 * ad48b4fa src/Rules.perfctr-pfm: Fix the perfctr-pfm build; for buildbot, mostly. Have the perfctr-pfm build only build libpfm, like the perfevents builds. The icc build was choking on warnings (-Werror => errors) in the example programs with libpfm, this is not something we depend upon. 2012-06-17 * 358b14f9 src/papi_events.csv: Update BGQ presets * cf26fc87 src/components/bgpm/CNKunit/linux-CNKunit.c src/components/bgpm/IOunit/linux-IOunit.c src/components/bgpm/L2unit/linux-L2unit.c...: Update bgpm components according to the papi5 changes * a7b08a91 src/configure src/configure.in src/linux-bgq.c: Merging the BG/Q stuff from stable_4.2 to PAPI 5 did break it. It's corrected now; also predefined events are now working.) 2012-06-15 * 2d5a4205 src/components/bgpm/IOunit/linux-IOunit.c src/components/bgpm/L2unit/linux-L2unit.c src/configure...: Merging the BG/Q stuff from stable_4.2 to PAPI 5 did break it. It's corrected now (almost); predefined events are not working yet.) * 1b034920 src/papi.c: Re-enable PAPI_event_name_to_code() optimization In PAPI_event_name_to_code() there was a commented-out optimization where we would check if an event name begins with "PAPI_" before searching the entire preset list for an event name. The comment says we had to disable this due to "user events", but a check shows that was introduced in e7bd768850ecf90 and that the "user events" it means is not the current support, but the now-removed PAPI_set_event_info() function where you could change the names of presets on the fly (even to something not starting with PAPI_). Since we don't support that anymore, we can re-enable the optimization. 2012-06-14 * 9a26b43d src/papi_internal.c src/papi_internal.h src/papi_preset.c: Remove the 16-component limit This turned out to be easier than I thought it would be. Now determining which component an event is in is a two step process. Before, the code shifted and masked to find the component from bits 26-30. Now, _papi_hwi_component_index() is used. There's a new native event table which maps all native events (which are allocated incrementally at first use starting with 0x4000000) to two values, a component number and an "internal" event number. 2012-06-13 * d5c50353 src/papi_internal.c: Fix for the PAPI_COMPONENT_MASK change I missed two cases in papi_internal.c This was causing the overflow_allcounters test to fail * 46fd84ce src/components/bgpm/CNKunit/linux-CNKunit.c src/components/bgpm/CNKunit/linux-CNKunit.h src/components/bgpm/IOunit/linux-IOunit.c...: Updating the Q substrate according to the PAPI 5 changes * 05a8dcbf src/components/appio/appio.c src/components/appio/tests/appio_list_events.c src/components/appio/tests/appio_values_by_code.c...: First steps of removing 16-component limit This change removes PAPI_COMPONENT_INDEX(), PAPI_COMPONENT_MASK and PAPI_COMPONENT_AND_MASK. It adds the new functions _papi_hwi_component_index() _papi_hwi_native_to_eventcode() _papi_hwi_eventcode_to_native() By replacing all of the former macros with the equivelant of the latter functions, it allows all of the future 16-component limit changes to be made in the functions. Components now receive as events a plain 32-bit value as their internal native event; the high bits are not set. This may break some external components. This change should not break things, but a lot of testing is needed. * af4cbb86 src/run_tests_exclude.txt: Exclude iozone helper scripts from run_tests. run_tests.sh looks for executible files under components/*/tests Some of the plotting scripts in appio/iozone were getting picked up. 2012-06-12 * c10c7ccb src/configure src/configure.in: Configure does not work on BGQ due to missing subcomp feature. It worked for stable-4.2 but got lost in current git origin. * d9a58148 src/aix.c src/ctests/hwinfo.c src/ctests/overflow.c...: Update hw_info_t CPU frequency reporting. Previously PAPI reported "float mhz" and "int clock_mhz". In theory the first was the current CPU speed, and the latter was the resolution of the cycle counter. In practice they were both set to the same value (on Linux, read from /proc/cpuinfo) and not very useful when DVFS was enabled, as the value reported was usually lower than the actual frequency running once CPU started being used. This change adds two new values "cpu_max_mhz" and "cpu_min_mhz" which are read from /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq and /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_min_freq if they are available, and falls back to /proc/cpuinfo otherwise. All of the tests were updated to use cpu_max_mhz. The old mhz and clock_mhz values are left for compatability reasons (and set to cpu_max_mhz) but are currently unused otherwise. 2012-06-11 * 0f124891 src/papi_events.csv: Initial PAPI Ivy Bridge Support for now try to re-use the sandy bridge event presets * a1f46077 src/libpfm4/docs/man3/libpfm_intel_ivb.3 src/libpfm4/include/perfmon/err.h src/libpfm4/lib/events/intel_ivb_events.h...: Import libpfm4 git snapshot This adds IvyBridge support * 3bb983cc src/libpfm-3.y/examples_v2.x/self_smpl_multi.c: Fix a libpfm3 example program for icc, local fix because libpfm3 is deprecated. icc does have more enjoyable warnings than gcc, : error 186: pointless comparison of unsigned integer with zero on this: unsigned int foo; ... if ( foo < 0 ) 2012-06-06 * d28adccf src/papi_user_events.c: The user events code had a call to exit, this was bad... 2012-06-04 * 6bf43022 src/testlib/test_utils.c: Further the hack for testing for perf SW events. Events like - | perf::CPU-CLOCK | | PERF_COUNT_SW_CPU_CLOCK | - were passing the check, now we also check the event_info_struct.long_descr field for PERF_COUNT_SW.... * fa4b1a28 src/components/nvml/linux-nvml.c: Cleanup nvml code a little. A few print statements were left over from debugging. Also check errors from nvml and cuda pciinfo functions, disabling the component in a few more cases. 2012-06-01 * da144a94 src/components/nvml/Makefile.nvml.in src/components/nvml/README src/components/nvml/Rules.nvml...: Rewrite and merge of the nVidia Management library component. This component attempts to expose all supported 'performance counters' on each card cuda knows about at runtime. Much like the cuda component reads happen on the card you're executing on at PAPI_read time. The test included is a copy of the cuda helloworld test, but it attempts to start/stop the event on each gpgpu. If you select an event that is not supported on the card you're running on we should fail gracefully but this has not been tested. 2012-05-23 * b2d414dc src/components/stealtime/linux-stealtime.c: At units to stealtime component Added the function but forgot to add a function vector for it. * ce9d4500 src/components/stealtime/linux-stealtime.c: Add units to stealtime Properly report that the units are in micro seconds. * 149948c8 src/components/rapl/linux-rapl.c: Minor cleanup of RAPL code missing "void" paramter in init_substrate function * 6a7e22fa src/components/vmware/vmware.c: More vmware component fixes. This makes the component thread-safe. Also makes it fail more gracefully if the guestlib SDK is installed but does not support our hypervisor (for example, if we are running under VM Workstation). Still need to test on ESX. * 072d6473 src/components/appio/tests/appio_test_select.c: added code to intercept and time select() calls. 2012-05-22 * 12b6d0d7 src/components/vmware/vmware.c: Some more minor fixes to VMware component Try to handle things better if VMguest SDK not working * 6e015bc5 src/components/vmware/Rules.vmware src/components/vmware/vmware.c: More vmware component fixups Now works with the events from the VMguest SDK library * 5fc0f646 src/components/vmware/vmware.c: More cleanup of vmware component The pseudo-performance counters work again. Now they behave in accumulate mode, like all other PAPI counters. * f72b0967 src/components/vmware/tests/vmware_basic.c: Make vmware test a bit more complete * 070e5481 src/components/vmware/tests/Makefile src/components/vmware/tests/vmware_basic.c: Add a test for the vmware component * 7cf62498 src/components/vmware/Makefile.vmware.in src/components/vmware/Rules.vmware src/components/vmware/configure...: Clean up the vmware component. bring it up to date with other components. make it possible to build it without the vmguest library being installed * b32ae1ae src/components/stealtime/Rules.stealtime src/components/stealtime/linux-stealtime.c src/components/stealtime/tests/Makefile...: Add a stealtime component When running in a VM, this provides information on how much time was "stolen" by the hypervisor due to the VM being disabled. This info is gathered from column 8 of /proc/stat This currently only works on KVM. * 9e95b480 src/components/appio/tests/appio_test_blocking.c: Use a non-blocking select to determine which reads and writes would block 2012-05-19 * f60d991f src/components/appio/README src/components/appio/appio.c src/components/appio/tests/appio_test_read_write.c...: Interception of close() implemented. This allows us to correctly determine the number of currently open descriptors. 2012-05-17 * 7cd8b5a3 src/libpfm4/.gitignore src/libpfm4/config.mk src/libpfm4/lib/Makefile...: Update libpfm4 to current git tree * ebffdb7e src/components/rapl/tests/rapl_overflow.c: Skip rapl_overflow test if RAPL not available * 98d21ef3 src/components/example/example.c src/components/rapl/linux-rapl.c: Fix some component warnings. * 0447f373 src/configure src/configure.in src/linux-generic.h: Make build not stall if PAPI_EVENTS_CSV not set This is some fallout from the FreeBSD changes. PAPI_EVENTS_CSV could not be set, which would make the event creation script hang forever. Also catch various fallthroughs in the code where SUBSTR wasn't being set, which is how the above problem can happen. * ef484c00 src/linux-timer.h: Fix typo in linux-timer.h 2012-04-14 * 7c3385f4 src/components/bgpm/CNKunit/CVS/Entries src/components/bgpm/CNKunit/CVS/Repository src/components/bgpm/CNKunit/CVS/Root...: Removed CVS stuff from Q code. * 2cf4aeb2 src/configure src/configure.in src/linux-bgq.c...: Removed papi_events.csv parsing from Q code. (CVS stuff still needs to be taken care of.) 2012-04-12 * 153c2bb1 INSTALL.txt: Updated INSTALL notes for Q 2012-05-17 * ff6a43fb src/Makefile.in src/Makefile.inc src/components/README...: Added missing files for Q merge. Conflicts: src/configure src/configure.in src/freq.c 2012-04-12 * 0e142630 src/Rules.bgpm src/components/bgpm/CNKunit/CVS/Entries src/components/bgpm/CNKunit/CVS/Repository...: Added PAPI support for Blue Gene/Q. 2012-05-14 * ad7e3fa0 src/components/rapl/linux-rapl.c: Properly accumulate RAPL results Previously it was resetting the counts on read, instead of continuing to count as per other PAPI events. * c79e3018 src/components/rapl/tests/rapl_overflow.c: Fix some warnings in rapl_overflow test * 731afd1a src/components/rapl/tests/Makefile src/components/rapl/tests/rapl_overflow.c: Add rapl_overflow test This test sees if we can measure RAPL in conjunction with overflow CPU performance events. * b0e201bb src/components/rapl/utils/Makefile src/components/rapl/utils/rapl_plot.c: Remove derived "uncore" values from rapl tool They weren't really measuring uncore, but were just TOTAL - PP0. It was causing some confusion. 2012-05-09 * 547e9379 doc/Doxyfile-common papi.spec src/Makefile.in...: Bump the version number to 4.9.0.0 Read 4.9 as pre-5.0 master was at version number 4.2.1, this was archaic... Sorry for the confusion Tushar, master is the correct branch for the latest development code. * 133e3d67 src/configure src/configure.in: Fix perfctr build In the FreeBSD changes I removed the CPU determination by reading /proc/cpuinfo as that was prone to failure and non-portable. This broke perfctr as it was doing a huge CPU name lookup to determine if it was on an x86 system or not. This change fixes that. 2012-05-08 * 42b21d67 src/papi_libpfm4_events.c: Fix PAPI event enumeration inside of VMware VMware disables the availability of architectural events when virtualized PMU is not available. libpfm4 was checkign this when enumerating events, and we would end up in the situation where ix86arch was marked active but 0 events were available. We didn't check for this error condition and thus end up thoroughly confused. 2012-05-07 * fd79a584 src/freebsd.c: Fix event enumeration on FreeBSD It was passing PAPI_OK in all cases, causing papi_native_avail to try to do things like report groups even when groups weren't available. * 53732c2e src/freebsd.c: Add Virtual Machine detection support to FreeBSD again, support for this on x86 is OS Neutral * 7b4d7c96 src/configure src/configure.in src/freebsd-memory.c...: Add x86_cacheinfo support to FreeBSD The x86 cache and memory info is OS-independent, so add support for it to FreeBSD. * 91033df6 src/Makefile.in src/Makefile.inc src/configure...: Re-enable predefined events on FreeBSD * 36f6dc1b src/freebsd.c src/freebsd/map.c src/freebsd/map.h: Modify FreeBSD to use _papi_load_preset_table * 45651746 src/freebsd.c: Cleanup the freebsd code a bit. * e1554ed8 src/configure: re-run autoconf for updated configure * 1deb2f5d src/Makefile.inc: Make sure a proper dependency for papi_events_table.h exists Our Makefile code that builds a shared library is way broken; it will fail to rebuild in many cases where the static library properly detects thing. * 28e28006 src/configure.in: Make papi_events_table.h build normally, not by configure. * 9a66dfa5 src/configure.in: Another place papi_events_table.sh is called * 12e4a934 src/Makefile.inc src/papi_events_table.sh: Make papi_events_table.sh take a command line argument This way we can use it on any .csv file, not just papi_events.csv * 7018528f src/freebsd/memory.c: Remove unused freebsd/memory.c file * 819e5826 src/freebsd_events.csv: Make freebsd_events.csv a valid PAPI event file * 9cc4a468 src/freebsd.c src/freebsd/map-atom.c src/freebsd/map-core.c...: Fix FreeBSD build on head. This temporarily disables preset events. There are also a few other minor fixes. 2012-05-01 * ab36c0a2 src/Makefile.inc src/configure src/configure.in: Update build system for FreeBSD * 2b61d8b7 src/freebsd.c src/freebsd.h: Fix various compiler warnings on FreeBSD * 2c0bcc84 src/freebsd.c: Enable new Westmere events on FreeBSD * b0499663 src/freebsd/map-i7.c src/freebsd/map-i7.h src/freebsd/map-westmere.c...: Add Westmere event support for FreeBSD * e54cabc6 src/ctests/inherit.c: Fix the inherit ctest to compile on FreeBSD * d9dbdd31 src/components/appio/appio.c: - change in appio component (appio.c): removed reference to .ntv_bits_to_info as it doesn't exist in the PAPI component interface. 2012-04-27 * 5d661b2d src/Rules.pfm src/Rules.pfm_pe: Add the libpfm -Wno-override-init bandaid to the other rules files. In b33331b66137668155c02e52c98a7e389fad402e we test if gcc -Wextra complains about some structure initialization that libpfm does. This was incoperated into Rules.pfm4_pe only. Jim Galarowicz noticed the other Rules files didn't have it. * 4349b6fd src/Rules.pfm4_pe src/Rules.pfm_pe: Cleanup the perf events Rules files. Steve Kaufmann reported that CONFIG_PFMLIB_OLD_PFMV2 is only used for libpfm3 builds targeting old versions of perfmon2. 2012-04-26 * 8a7fef68 src/mb.h: Add memory barries for ia64 2012-04-24 * 9af4dd4a src/libpfm4/README src/libpfm4/config.mk src/libpfm4/include/perfmon/perf_event.h...: Import libpfm4 git snapshot This brings libpfm4 up to 9ffc45e048661a29c2a8ba4bfede78d3feb828f4 The important change is support for Intel Atom Cedarview. 2012-04-20 * fac6aec0 src/linux-bgp-memory.c src/linux-bgp.c: Some BG/P cleanups. Removed a lot of dead code, noticed when looking for any potential BG/P issues. * 977709f6 src/linux-bgp-preset-events.c src/linux-bgp.c: Fix PAPI compile on BG/P Thanks to Harald Servat 2012-04-19 * 5207799e release_procedure.txt: Modified release_procedure.txt to push tags. 2012-04-18 * b248ae80 doc/Makefile: Have clean remove the doxygen error file. * 1d4f75a3 doc/Doxyfile-man1 doc/Doxyfile-man3: Fix an error in the Doxygen config files. Doxygen includes things with @INCLUDE not @include. The html file had this, the man page files did not... 2012-04-17 * 979cda20 cvs2cl.pl delete_before_release.sh gitlog2changelog.py...: Update the release machinery for git. gitlog2changelog.py takes the output of git log and parses it to something like a changelog. * 67bdd45f doc/Doxyfile-html: Cover up an instance of doxygen using full paths. Doxygen ( up to 1.8.0, the most recent at this writing ) would use full paths in directory dependencies ignoring the use relative paths config option. 2012-04-13 * c38eb0b7 src/libpfm-3.y/lib/intel_corei7_events.h src/libpfm-3.y/lib/intel_wsm_events.h src/libpfm-3.y/lib/pfmlib_intel_nhm.c: Add missing update to libpfm3 Somehow during all of the troubles we had with importing libpfm3 into CVS, we lost some Nehalem/Westmere updates. Tested on a Nehalem machine to make sure this doesn't break anything. * 193d8d06 src/papi_libpfm3_events.c: Fix max_multiplex case on perf_event/libpfm3 num_mpx_cntrs was being set to 512 even though the real maximum is 32, causing a buffer overflow and segfault. 2012-04-12 * f1f7fb5b src/threads.h: Fix minor typo in a comment * 0373957d src/linux-timer.c: Fix potential fd leak Noticed by coverity checker. * 71727e38 src/ctests/max_multiplex.c: Improve max_multiplex ctest on perfmon2, this test was failing because the maximum number of multiplexed counters was much more than the available counters we could test with. This change modifies the test to not fail in this case. 2012-04-11 * fdbdac9f src/perfmon.c: Fix the perfmon substrate. It was missing a _papi_libpfm_init() call, which meant the number of events was being left at 0. 2012-04-09 * 2a44df97 src/libpfm-3.y/examples_v2.x/multiplex.c src/libpfm-3.y/examples_v2.x/pfmsetup.c src/libpfm-3.y/examples_v2.x/rtop.c...: Catch a few libpfm-3.y files up to libpfm-3.10. More skeletons keep falling out of the cvs closet. This is just what diff -q -r catches. 2012-04-04 * 0e05da68 src/components/rapl/utils/Makefile src/components/rapl/utils/README src/components/rapl/utils/rapl_plot.c: Add the rapl_plot utility to the RAPL component. This utility uses PAPI to periodicly poll the RAPL counters and generate average power results suitable for plotting. There's been a lot of interest in this utility so it's probably useful to include it with the RAPL component. * 2daa03ac src/papi_internal.c: Check if a component is disabled at init time. This change modifies the code so that at PAPI_library_init() time we check the component disable field, and we don't call the init routines for components the user has disabled. This allows code like the following to happen _before_ PAPI_library_init(): numcmp = PAPI_num_components(); for(cid=0; cidname,"cuda")) { cmpinfo->disabled=1; strncpy(cmpinfo->disabled_reason,"Disabled by user",PAPI_MAX_STR_LEN); } } We might want to add a specific PAPI_disable_component(int cid) call of maybe even a PAPI_disable_component(char *name) as the above code causes compiler warnings since cmpinfo is returned as a const pointer. This all works because currently PAPI currently statically allocates all of the components at compile time, so we can view and modify the cmp_info structure before PAPI_library_init() is called. * 3fd2b21e src/components/appio/README src/components/appio/appio.c src/components/appio/appio.h...: Added support to count reads that are interrupted or would block. 2012-04-03 * dd3a192f release_procedure.txt: Change chmod flags for doxygen stuff from 755 to 775 to allow group write permissions. 2012-03-30 * deac54cc src/components/coretemp/linux-coretemp.c src/components/coretemp/tests/coretemp_basic.c src/components/coretemp/tests/coretemp_pretty.c...: Add new PAPI_enum_cmp_event() function This will be needed when we remove the 16-component limit. Currently in PAPI_enum_event() the component number is gathered from bits 29-26 of the eventcode. This won't work anymore once we remove those bits. Also update the various components to not use PAPI_COMPONENT_MASK() as this too will go away in the transition. * 48331cc9 src/configure src/configure.in src/papi.c...: Place all compiled-in components in the _papi_hwd[] array. Previously we had separate compiled_in[] and _papi_hwd[] arrays. At init time a pointer to the compiled_in[] was copied to _papi_hwd[] if initialization passed. This kind of code setup makes enumerating components hard, and finding info from non-available components would require additional function entry points. This change leaves all compiled in components to _papi_hwd[]. Availability of the component can be checked with the new "disabled" field. This will make enumeration support a lot easier to add. It can possibly cause user confusion if they try to access component structures directly without checking the "disabled" field first. This change should also make any eventual support for run-time component enabling/disabling a lot easier. * 66a72f44 src/papi.c: Documentation was referring to nonexistent "PAPI_enum_events()" The actual function we have is PAPI_enum_event() * 0f2c2593 src/components/coretemp/linux-coretemp.c src/components/lustre/linux-lustre.c src/components/mx/linux-mx.c...: Add support for reporting reason for failed component initialization. This change adds the fields "disabled" and "disabled_reason" to the component_info_t structure. At initialization time, PAPI will set the "disabled" field to the value returned by component init (that is PAPI_OK if OK or an error otherwise). This can be checked later to find why component init failed. Also provided is the "disabled_reason" string. The components can set this at failure time, and this can be printed later. For example, this is sample output of the updated papi_component_avail routine: - Compiled-in components: Name: perf_events.c Linux perf_event CPU counters Name: linux-rapl Linux SandyBridge RAPL energy measurements \-> Disabled: Not a SandyBridge processor Name: example.c A simple example component Name: linux-coretemp Linux hwmon temperature and other info \-> Disabled: No coretemp events found Name: linux-net.c Linux network driver statistics Name: linux-mx.c Myricom MX (Myrinet Express) statistics \-> Disabled: No MX utilities found Name: linux-lustre.c Lustre filesystem statistics \-> Disabled: No lustre filesystems found Active components: Name: perf_events.c Linux perf_event CPU counters Name: example.c A simple example component Name: linux-net.c Linux network driver statistics 2012-03-29 * d84b144e src/components/rapl/Rules.rapl src/components/rapl/linux-rapl.c src/components/rapl/tests/Makefile...: Add a SandyBridge RAPL (Running Average Power Level) Component This component allows energy measurement at the package-level on Sandybridge machines. To run, you need the Linux x86-msr kernel module installed and read permissions to /dev/cpu/*/msr The output from the rapl_busy test looks like this on a SandyBridge-EP machine: Trying all RAPL events Found rapl component at cid 2 Starting measurements... Doing a naive 1024x1024 MMM... Matrix multiply sum: s=1016404871450364.375000 Stopping measurements, took 3.979s, gathering results... Energy measurements: PACKAGE_ENERGY:PACKAGE0 175.786011J (Average Power 44.2W) PACKAGE_ENERGY:PACKAGE1 73.451096J (Average Power 18.5W) DRAM_ENERGY:PACKAGE0 11.663467J (Average Power 2.9W) DRAM_ENERGY:PACKAGE1 8.055389J (Average Power 2.0W) PP0_ENERGY:PACKAGE0 119.215500J (Average Power 30.0W) PP0_ENERGY:PACKAGE1 16.315216J (Average Power 4.1W) Fixed values: THERMAL_SPEC:PACKAGE0 135.000W THERMAL_SPEC:PACKAGE1 135.000W MINIMUM_POWER:PACKAGE0 51.000W MINIMUM_POWER:PACKAGE1 51.000W MAXIMUM_POWER:PACKAGE0 215.000W MAXIMUM_POWER:PACKAGE1 215.000W MAXIMUM_TIME_WINDOW:PACKAGE0 0.046s MAXIMUM_TIME_WINDOW:PACKAGE1 0.046s rapl_basic.c PASSED 2012-03-26 * b44d60ca src/components/appio/appio.c src/components/appio/appio.h src/components/appio/tests/appio_test_read_write.c: Added support for intercepting open calls. 2012-03-23 * 9e9fac4b src/Makefile.in src/Rules.pfm4_pe src/configure...: Fix the test case in configure at 0cea1848 Make use of the structure we're using for the override-init test case. * 0cea1848 src/configure src/configure.in: Doctor CFLAGS when testing for a gcc warning. -Wextra was not in CFLAGS when I attempted to check for the initialized field overwritten warning. So we set -Wall -Wextra -Werror when running the test code. 2012-03-22 * b33331b6 src/Makefile.in src/Rules.pfm4_pe src/configure...: Fix initialized field overwritten warning when building libpfm4 on some gcc versions. In gcc 4.2 or so, -Woverride-init was added to -Wextra causing issues with code like struct foo { int a; int b;}; struct foo bar = { .a=0, .b=0, .b=5; }; --Wno-override-init allows us to keep -Werror for libpfm4 compiles. 2012-03-21 * ae149766 src/papi_internal.h: Delete an old comment. Yes, Dan in 2003, we should and do use MAX_COUNTER_TERMS as the size of the event position array. 2012-03-20 * b937cdd8 src/papi_user_events.c: Move the user events code over to using the new preset event data structure. 2012-03-14 * 6ca599e2 src/papi_internal.c: Fix a small memory leak. We weren't freeing _papi_hwd, causing a lot of MEM_LEAK warnings in buildbot. 2012-03-13 * 473b8203 src/aix.h src/configure src/configure.in...: Remove last MY_VECTOR usage. Have configure explicitly set the name of the perf counter substrate vector in the components_config.h file This removes one more special case, and gets us slightly closer to being able to have multiple CPU substrates compiled in at once. * 360c3003 src/papi.c src/papi_libpfm3_events.c src/papi_libpfm_events.h...: Clean up the papi_libpfm3_events.c code. Move code that was perfctr specific into perfctr-x86.c * 03de65e3 src/libpfm-3.y/examples_v2.x/multiplex.c src/libpfm-3.y/examples_v2.x/pfmsetup.c src/libpfm-3.y/examples_v2.x/rtop.c...: Fix some libpfm3 warnings. libpfm3 is not maintained anymore, so applied these changes locally. libpfm3 is compiled with -Werror so they broke the build with newer gcc even though they are just warnings in example programs. * ad490353 src/ctests/zero_named.c src/utils/multiplex_cost.c: Fix a few compiler warnings in the tests. * a0fec783 src/linux-timer.c: Fix another linux-timer.c compile problem. I hadn't tested with debug enabled, so all of buildbot failed last night. 2012-03-12 * a3733ecd src/linux-timer.h: Fix typo in the linux-timer.h header _linux_get_virt_usec_timess should have been _linux_get_virt_usec_times Thanks to Steve Kaufmann for noticing this. * 785db5ae src/linux-common.c src/linux-timer.c: Fix timer compile on Power machines Power, ARM, and MIPS have no get_cycles() call so provide a dummy function on these architectures. * 708090ee src/linux-common.c src/linux-timer.h: Another fix for non-POSIX timers The recent changes had the name of the fallback usec method wrong. * 88e8d355 src/papi_libpfm3_events.c: Fix a warning in the libpfm3 code. * 8ca63705 src/configure src/configure.in src/linux-common.c...: Fix build when not using POSIX timers The PAPI build system was being overly clever with how it defined what kind of wall clock timers were to be used, so of course I broke things when breaking the timer code out to make it a bit more understandable. This patch breaks out the timer define into two pieces; one saying it's a POSIX timer and one saying whether to use HR timers or not. 2012-03-09 * b69ad727 src/linux-common.c src/linux-timer.c src/linux-timer.h: Add Linux posix gettime() nanosecond functions * af2c9a49 src/papi.c src/papi_vector.c src/papi_vector.h: Add ->get_virt_nsec() and ->get_real_nsec() OS vectors Currently PAPI was just cheating and running the usec functions and multiplying by 1000. Make this the default, but allow the OS code to override if they have timers capable of returning nsec percision. * 24c68dbe src/aix.c src/freebsd.c src/linux-bgp.c...: Clean up ->get_virt_usec() It no longer needs to be passed a context, so remove that from all callers. Also, ->get_virt_cycles() was just a get_virt_usec()*MHz on most platforms. While this is a bit dubious (especially as MHz can't be relied on) make this a common routine that will be added at innoculate time if ->get_virt_cycles() is set to NULL. * a3ef7cef src/linux-common.c src/linux-timer.c src/linux-timer.h: Cleanup the Linux timer code. Split things up a bit to make the code more readable. * 50ce8ea0 src/papi_internal.c: Change a strcpy() to strncpy() just to be a bit safer. * 0526b125 src/components/lmsensors/linux-lmsensors.c: Fix buffer overrun in lmsensors component * b088db70 src/libpfm4/config.mk src/libpfm4/docs/man3/pfm_get_os_event_encoding.3 src/libpfm4/examples/showevtinfo.c...: Update to current git libpfm4 snapshot * ccb45f61 src/aix.c src/extras.c: Fix segfault on AIX During some of the cleanups, the extras.h header was not added to aix.c This made some of the functions (silently) use default data types for the function parameters, leading to segfaults in some of the tests. 2012-03-08 * 1cb22d0b src/components/coretemp/linux-coretemp.c src/utils/native_avail.c: Make "native_avail -d" report units if available Add units support to the coretemp component, have native_avail -d (detailed mode) print it to make sure it works. * 9c54840e src/extras.c src/extras.h src/papi_internal.c...: Add new ntv_code_to_info vector This will allow components to return the extended event_info data for native events. If a component doesn't implement ntv_code_to_info then get_event_info falls back to the old way of just reporting symbol name and long description. * c4579559 src/papi.h: Add new event_info fields New fields are added to event_info that allow passing on extended information. This includes things such as measurement units, data type, location, timescope, etc. * 17533e4e src/ctests/all_events.c src/ctests/derived.c src/ctests/kufrin.c...: Restore fields to event_info structure The changes made were probably too ambitious, even for a 5.0 release. In the end it looks like we can remain API compatible while just using up a little more memory. We can still save space by shrinking preset_t behind the scenes. * 6f13a5f6 src/aix.c src/components/coretemp/linux-coretemp.c src/components/coretemp_freebsd/coretemp_freebsd.c...: Remove ->ntv_bits_to_info vector from component interface We weren't using it anymore, and many of the components were just setting it to NULL unncessarily. We'll be replacing the functionality soon with ntv_code_to_info * 401f37bc src/components/example/example.c src/ctests/subinfo.c src/papi.h: Remove invert and edge_detect fields from component info These fields were there to indicate if a CPU component supported these attributes (for Intel processors) but in the end we never used these. The proper way to export this info is during event enumeration. * f32fe481 src/papi_events.csv: We had the PAPI_VEC_INS preset wrong on amd fam12h llano * 38a8d8a7 src/ctests/multiplex2.c src/papi_preset.c: Fix preset adding code to be more robust. If an invalid event is in a preset definition, we'd currently add it with an eventcode of 0 to the preset, which would break if you tried to use the event. This change properly prints a warning in this case, and sets the preset to be unavailable. * 2591a546 src/ctests/val_omp.c src/ctests/zero_omp.c: Remove the hw_info field from add_two_events calls. Two ctests missed the bus when Vince reworked the add_two_events call. * 358a2e32 src/papi_internal.c src/papi_preset.c: Fix segfault seen on an AMD fusion machine With the recent preset and component hanges, we were not properly resetting papi_num_components if PAPI_library_init()/PAPI_shutdown() was called multiple times. 2012-03-07 * 7751f5d8 src/ftests/zeronamed.F: Fix a compile error on aix. Dan ran over 72 characters on a single line. xlf actually enforced that part the Fortran spec. 2012-03-06 * 1c87d89c src/ftests/Makefile src/ftests/zeronamed.F src/papi_fwrappers.c: Add support for {add, remove, query}_named to Fortran interface; add zero named.F test case; modify ftests Makefile to support "all" tag. * 71bd4fdd src/configure src/configure.in: Modify configure to define the default FTEST_TARGETS as "all" * 54e39855 src/components/vmware/vmware.c: Changed tri8ggering environment variable to PAPI_VMWARE_PSEUDOPERFORMANCE per Vince's earlier email. This should complete all the VMware component changes. 2012-03-05 * 845503fb src/Makefile.inc: Add missing MISCSRCS line to Makefile.inc This was breaking the shared library build 2012-02-01 * 11be8e4b .../appio/tests/appio_test_fread_fwrite.c src/components/appio/tests/appio_test_pthreads.c src/components/appio/tests/appio_test_read_write.c: updated these tests to print timing information * 9ad62ab1 src/components/appio/README src/components/appio/appio.c src/components/appio/appio.h...: Added support for timing I/O calls. Updated tests and README. 2012-01-31 * beaa5ff0 src/components/appio/tests/iozone/Changes.txt src/components/appio/tests/iozone/Generate_Graphs src/components/appio/tests/iozone/Gnuplot.txt...: added the latest stable iozone to the appio tests. * 4af58174 src/components/appio/README src/components/appio/tests/Makefile src/components/appio/tests/init_fini.c: added a hook to run the appio test for iozone. 2012-01-21 * 15c733cf src/components/appio/CHANGES src/components/appio/README src/components/appio/appio.c...: Removed stray 'net' references. All remaining references are only for the purpose of giving credit. Updated change log. 2012-01-20 * ca4b6785 src/components/appio/README src/components/appio/appio.c src/components/appio/tests/appio_list_events.c...: - general cleanup - improved tests to be quiet and be conform to other PAPI tests - replaced hardwire constants in appio.c with symbolic ones - tests will now write to /dev/null to avoid filling the terminal screen with useless text - more comments added - @author added to files - updated README 2012-01-18 * bb22ed9f src/components/appio/README src/components/appio/Rules.appio src/components/appio/appio.c...: - Added support to measure bytes/calls/eof/short calls for read/write calls. - Interception of read/write and fread/fwrite calls. - Works for static and dynamic linkage (without need for LD_PRELOAD) - Tested OK on 32-bit i686 Linux 2.6.38. Tushar 2011-12-03 * d58b34b6 src/components/appio/tests/Makefile src/components/appio/tests/appio_list_events.c src/components/appio/tests/appio_values_by_code.c...: *** empty log message *** * cd7d7acc src/components/appio/tests/appio_values_by_name.c: file appio_values_by_name.c was added on branch appio on 2011-12-03 05:22:06 +0000 * 425e4d09 src/components/appio/tests/appio_values_by_code.c: file appio_values_by_code.c was added on branch appio on 2011-12-03 05:22:06 +0000 * 596ad9bb src/components/appio/tests/appio_list_events.c: file appio_list_events.c was added on branch appio on 2011-12-03 05:22:06 +0000 * 119543dc src/components/appio/tests/Makefile: file Makefile was added on branch appio on 2011-12-03 05:22:06 +0000 2012-03-05 * ba748a41 src/components/vmware/configure: Remove old configuration parameters from vmware/configure 2012-03-02 * 2b7e2abb src/ctests/Makefile src/ctests/max_multiplex.c: Add a new max_multiplex test This tries to use the maximum number of multiplexed events. This was written in response to the 32/64 perf_event multiplexed event limit reported by Mohammad j. Ranji * a0985ff5 src/multiplex.c src/papi_internal.c src/papi_libpfm4_events.c...: Fix issue when using more than 32 multiplexed events on perf_event On perf_event we were setting num_mpx_cntrs to 64. This broke, as the MPX_EventSet struct only allocates room for PAPI_MPX_DEF_DEG events, which is 32. This patch makes perf_event use a value of 32 for num_mpx_cntrs, especially as 64 was arbitrarily chosen at some point (the actual value perf_event can support is static, but I'm pretty sure it is higher than 64). * 331c516c src/ctests/acpi.c: Remove the acpi.c file from ctests It wasn't being built, and we removed the ACPI component a while ago. * 73e7d191 src/components/vmware/vmware.c: Removed all old references to #define VMWARE_PSEUDO_PPERF and switched over to getenv 2012-03-01 * 969b8aa9 src/ctests/Makefile src/ctests/zero_named.c src/papi.c: Three new APIs: PAPI_query_named_event PAPI_add_named_event PAPI_remove_named_event and a new test: zero_named Still to do: maybe test named native events and support Fortran * 97bf9bf8 src/papi.c src/papi.h: First pass implementation of {add, remove, query}_named_event * 2416af88 src/components/vmware/vmware.c: Add functionality to getenv selectors * 297f9cd6 src/papi.c: Fix possible race in _papi_hwi_gather_all_thrspec_data The valgrind helgrind tool noticed this with the thrspecific test * be599976 src/papi_internal.c: Add some locking in _papi_hwi_shutdown_global_internal This caused a glibc double-free warning, and was caught by the Valgrind helgrind tool in krentel_pthreads There are some other potential locking issues in PAPI_shutdown, especially when debug is enabled. * 8444d577 src/utils/clockres.c src/utils/command_line.c: Cleanup the oxygen markup for the utilities. * 7144394f doc/Doxyfile-html: Missed a recursive tag for the html config file. * 63b2efc4 src/papi_preset.c: Fix segfaults in tests on AMD machines The papi_preset code was wrongly calling papi_free() on some code that was allocated with strdup() (not with papi_malloc). We were only noticing this on AMD machines because it was the code for freeing developer notes in presets, and currently only AMD events have developer notes. * 0b1350df src/linux-common.c: Touch 'virtual_vendor_name' to cleanup a warning on bluegrass. 2012-02-29 * 1f17b571 src/Makefile.inc src/Rules.perfctr-pfm src/Rules.pfm4_pe...: Merge the contents of papi_libpfm_presets.c into papi_preset.c The code isn't libpfm specific at all anymore, it's the generic "read presets from a file" code. It makes more sense to find it in papi_presets.c * d087d49f src/papi_fwrappers.c: Fix Fortran breakage after the preset event changes * 156141ec src/papi_libpfm_presets.c src/papi_preset.c src/papi_preset.h: Simplify papi_libpfm_presets.c Previously adding presets from papi_events.csv was a three step process. 1. Load the presets from the file, put in temporary structure. 2. Convert this temporary structure to a "findem" dense structure 3. Pass this dense structure to _papi_hwi_setup_all_presets for final assignment. This change creates the final assignment directly without the intermediate two steps. * 8bc2bafd src/papi.c src/papi.h src/papi_common_strings.h...: Make the internal preset_info match the one exported by papi.h There were a lot of cases where the same structure fields were available, just with different names. That was confusing. Also, this allows using a pointer to the preset info instead of having to copy values out of the structure when gathering event info for presets. * 8fda68cb src/genpapifdef.c src/papi.c src/papi_common_strings.h...: Merge the 4 separate preset structs into one. _papi_hwi_presets was a structure containing pointers to 4 other arrays of structures which held the actual preset data. This change merges all of these into one big structure. 2012-02-28 * e69815d7 src/linux-bgp.c src/papi_internal.c src/papi_internal.h...: Removing remaining vestiges of references to bipartite routines. Now the only references are in papi_bipartite.h, perfctr-x86.c and winpmc-p3.c. * 5766b641 src/papi_bipartite.h src/perfctr-x86.c src/win2k/substrate/winpmc-p3.c: These changes implement the bipartite allocation routine as a header file to be included in whatever cpu component needs it. Right now, that's just perfecter-x86 and windows. Both components have been modified and perfecter-86 compiles cleanly. Neither has been tested since I don't have access to a test bed. * 7f444b76 src/papi_libpfm_presets.c src/papi_preset.c src/papi_preset.h: Merge the hwi_dev_notes structure into hwi_preset_data * 21a1d197 src/components/vmware/vmware.c: add getenv * 08c1b474 src/perfctr-x86.c: Merge bipartite routine into perfecter-x86 component, since this is effectively the only place it is used. * 9ed9b1f5 src/papi.c: Remove a reference to PAPI_set_event_info() which was removed for PAPI 4 * c626f064 src/ctests/all_events.c src/ctests/derived.c src/ctests/kufrin.c...: Convert PAPI_event_info_t to separate preset event info This moves the preset event info to its own separate structure, which reduces greatly the large string overhead that is not used by the native events. * 787d6822 src/perfctr-x86.c: Move bipartite stuff to perfctr_x86 since that's really the only place it's currently used. * 229c8b41 src/components/vmware/vmware.h: Add env_var definition to vmware.h * 46aaf6ca src/components/vmware/vmware.c: Remove all unneeded cases * 874a5718 src/freebsd.c src/perfctr-ppc64.c: Remove more unused references to .bpt_ routines in preparation for refactoring. * 74e5a5fd src/components/vmware/vmware.h: Remove uneeded defines from vmware.h header * 58b51367 src/components/coretemp_freebsd/coretemp_freebsd.c src/components/vmware/vmware.c src/solaris-niagara2.c...: Remove unused references to .bpt_ routines in preparation for refactoring. 2012-02-27 * 6b184158 src/Makefile.inc src/components/coretemp/linux-coretemp.c src/configure...: Have separate concept of "compiled-in" versus "active" components With this change, the _papi_hwd[] component info array only contains a null-terminated list of _active_ components. The _papi_compiled_components[] array has the original full list. At init_substrate[] time a pointer to a component is only put in the _papi_hwd[] list if it is successfully initialized. In addition the PAPI_num_compiled_components() and PAPI_get_compiled_component_info() calls have been added, but this is probably a confusing interface so they might only be temporary additions. * 042bfd5b src/Makefile.inc src/papi.c src/papi_data.c...: Split the contents of papi_data.c to various other files. The data declarations in papi_data.c were mostly used in other files. Move these into more relevant locations. * 1877862c src/papiStdEventDefs.h src/papi_common_strings.h: Remove the BGL and BGP specific pre-defined events. They can be better replaced by user-events, and we also had already removed BGL support completely a while back. This removes some ifdefs from the pre-defined event list and keeps future pre-defined events from having different eventcodes on different platforms. * c3986b79 src/components/coretemp/linux-coretemp.c src/components/cuda/linux-cuda.c src/components/infiniband/linux-infiniband.c...: Add names and descriptions for components. Also fixes cuda and lmsensors build issues introduced by vector.h cleanup * 2c84f920 src/aix.c src/freebsd.c src/perf_events.c...: Add names and descriptions to all of the CPU substrates. * 9f3e634a src/components/example/example.c src/papi.h src/utils/component.c: Add new "description" and "short_name" fields to .cmp_info structure This description field allows components to provide extra information on what they do. The short_name field will eventually be used to pre-pend event names. The papi_component_avail utility has been updated to print the description. The example component was updated to fill in these values. * ab61c9a7 src/Makefile.inc src/genpapifdef.c src/papi_common_strings.h...: Split papi_data.c into two parts papi_data.c was half data structure definitions for all of PAPI and half string definitions used by both PAPI *and* genpapifdef This splits the common string definitions to papi_common_strings.h so that genpapifdef can still be built w/o linking libpapi.a while making the code a lot easier to follow. * b8e6294c src/solaris-ultra.c: Remove unncessary extern declarations from solaris-ultra.c. * 5ddaff91 src/sys_perf_event_open.c: Remove unncessary extern declarations from sys_perf_event_open.c * a6c463b7 doc/Doxyfile-common.config: Create a common config file for doxygen. As part of streamlining the doxygen process, this is a new template doxygen config files. This is a blank template file generated by doxygen 1.7.4 (the version currently mandated by the release procedure ) * dc2c11fa src/aix.c src/aix.h src/perfmon.c...: The vector pre-definition should be in the .c file, not the .h file * 0b3c83c3 src/perf_events.c: Remove unnecessary extern declarations in perf_events.c * b93efca0 src/perfmon.c src/perfmon.h: Remove unnecessary extern declarations in perfmon.c * 7f7a2359 src/papi_preset.c: Remove unnecessary extern declarations from papi_preset.c * ecec03ad src/papi_libpfm_presets.c: Remove extraneous extern declarations from papi_libpfm_presets.c * 7b5f3991 src/extras.c: remove extraneous extern declarations from extras.c * f6470e4d src/aix-memory.c src/aix.c src/aix.h: Remove unncessary extern declarations from aix.c * f197d4ab src/papi_data.h src/papi_internal.c: Remove unncessary extern declarations in papi_internal.c * e7b39d48 src/papi.c src/papi_data.c src/papi_data.h...: remove unnecessary extern definitions from papi.c 2012-02-24 * 92689f62 src/configure src/configure.in src/linux-common.c...: Add a --with-pthread-mutexes option to enable using pthread mutexes rather than PAPI custom locks This is useful when running on new architectures that don't have a custom PAPI lock coded yet, and also for running valgrind deadlock detection utilities that only work with pthread based locking. * ca51ae67 src/papi_events.csv: Fix broken Pentium 4 Prescott support We were missing the netbusrt_p declaration in papi_events.csv * f6460736 src/linux-common.c: Fix build on POWER, broken by the virtualization change. * 91d32585 src/perfctr-x86.c src/perfmon.c: Fix some warnings that have appeared due to recent changes. * ae0cf00f src/linux-common.c src/papi_libpfm3_events.c src/papi_libpfm4_events.c...: Clean up the Linux lock files The locking primitives for some reason were spread among the libpfm code and the substrate codes. This change moves them into linux-common and has them part of the OS code. This way they will get properly initialized even if the perf counter or libpfm code isn't being used. 2012-02-23 * 88847e52 src/papi.c src/papi_memory.h: Remove _papi_cleanup_all_memory define from papi_memory.h The code in papi_memory.h said: /* define an alternate entry point for compatibility with papi.c for 3.1.x*/ /* this line should be deleted for the papi 4.0 head */ Since we are post papi-4.0 I thought it was time to act on this. Of course papi.c was still using the old name in one place. * 1d29dfc6 src/papi_libpfm_presets.c src/perfctr.c src/perfmon.c: Fix some missing includes found after the header cleanup. * b425a9f4 src/Makefile.inc src/extras.c src/extras.h...: Header file cleanup The papi_protos.h file contained a lot of no-longer in use exports. I split up the ones that are still relevant to header files corresponding to the C file that the functions are defined in. * 07199b41 src/extras.c src/papi_vector.c src/papi_vector.h: Clean up the papi_vector code. Remove things no longer being used, mark static functions as static. * d7496311 src/linux-common.c src/x86_cpuid_info.c src/x86_cpuid_info.h: Fix a missing "return 1" which meant that the virtualization flag wasn't being set right. With this fix, on saturn-vm1 we now get: Running in a VM : yes VM Vendor: : VMwareVMware in the papi_native_avail header * 8da36222 src/freebsd.c src/linux-bgp.c src/papi.c...: Remove the ->add_prog_event function vector As far as I can tell this is a PAPI 2.0 remnant that was never properly removed. This also removes PAPI_add_pevent(), PAPI_save(), and PAPI_restore(), none of which were exported in papi.h so in theory no one could have been using them. Also removes _papi_hwi_add_pevent() * a5f3c8b5 src/aix.c src/freebsd.c src/linux-timer.c...: Reduce the usage of MY_VECTOR whenever possible. This is an attempt to make the cpu-counter components to be as similar as possible to external components. * abbcbf29 src/any-null.h: Missed removing any-null.h during the any-null removal. * 665d4c5c src/linux-common.c: Somehow missed an include during the virtualization addition. * 0c06147b src/perfctr-2.6.x/usr.lib/event_set_centaur.os src/perfctr-2.6.x/usr.lib/event_set_p5.os src/perfctr-2.6.x/usr.lib/event_set_p6.os: Removes the last of the binary files from perfctr2.6.x Some binary files were left out in the cold after a mishap trying to configure perfctr for the build test. * 3acb7d57 src/Makefile.inc src/configure src/configure.in...: Add support for reporting if we are running in a virtualized environment to the PAPI_hw_info_t structure. This currently only works on x86. it works by looking at bit 31 of ecx after a cpuid (the "in a VM" bit) and then using leaf 0x40000000 to get the name of the VM software (this works for VMware and Xen at least) x86_cache_info.c was renamed to x86_cpuid_info.c to better reflect what goes on in that file (it does various things based on the cpuid instruction). the testlib header was updated to report virtualization status in the papi header (printed for things like papi_native_avail). 2012-02-22 * 9c7659b5 src/Makefile.inc src/freq.c: Remove the freq.c file as nothing seemed to be using it. * d205e2d3 src/perfctr-x86.c: Made a stupid typo when converting perfctr to call libpfm functions with the component id. * 25b41779 src/papi_libpfm3_events.c src/papi_libpfm4_events.c src/papi_libpfm_events.h...: When updating the preset code to take a component index I missed a few callers. * a713ffb1 src/papi_internal.c src/papi_vector.c: Remove any-null component * 27e1c2c5 src/any-null-memory.c src/any-null.c src/any-proc-null.c...: Remove the any-null component. * 25779ae0 PAPI_FAQ.html: Saving another version of the FAQ after adding a git section, and removing several obsolete sections. These questions still need detailed review for relevance and timeliness. * 449a1a61 src/ctests/overflow_allcounters.c: Fix overflow_allcounters which was making assumptions about component 0 existing. * f21be742 src/ctests/hwinfo.c: Make the hwinfo test not bail out if no counters are available. * ebc675e6 src/ctests/memory.c: Make sure the memory ctest runs even if no components are available. * 9b3de551 src/linux-common.c src/perf_events.c src/perfmon-ia64.c...: Make sure the system info init happens at os init time. Otherwise the system info never gets set if a perfcounter component isn't available. * 59e47e12 src/papi_internal.c: Make sure that _papi_hwi_assign_eventset() does the right thing if no components are available. * dd51e5d6 src/ctests/api.c: The api test would fail in the no cpu component case. Fix it to properly check for errors before attempting to run high-level PAPI tests. * 069e9d2f src/aix.c src/papi.c src/papi_internal.h...: Fix code that was depending on _papi_hwd[0] existing. Most of this was in the presets code. The preset code had many assumptions so that you can only code presets with component[0]. This fixes some of them by passing the component index around. * 7259eaec src/papi_vector.c: Fix up papi_vector to get rid of some warnings introduced on AIX. * 16fe0a61 src/aix.c src/solaris-ultra.c: Fix two last substrates where I missed some fields in the OS structure conversion. * 625871ec src/perfmon.c: Missed a cmp_info field in perfmon.c * 680919d9 PAPI_FAQ.html: Saving the latest version of the FAQ before undertaking major revisions. * 3d4fa2e5 src/linux-timer.c src/perfctr-x86.h: Fix the perfctr code to compile if configured with --with-virtualtimer=perfctr * bbd7871f src/perfctr.c: Missed two OS vector calls in the perfctr code during the conversion. * bc6d1713 src/Makefile.inc: Removed one of the two instances of MISCOBJS listed in Makefile.inc. 2012-02-21 * 40bc4c57 src/papi_vector.c src/papi_vector.h: Remove now-unused OS vectors from the main papi vector table. * 3c6a0f7b src/aix.c src/freebsd.c src/linux-bgp.c...: Convert PAPI to use the _papi_os_vector for the operating-system specific function vectors. * 568abad5 src/papi_vector.h: Add new _papi_os_vector structure to hold operating-system specific function vectors. * a39d2373 src/ctests/subinfo.c: Missed removing a field from the subinfo ctest. * 1d930868 src/papi.h: Remove fields now in PAPI_os_info_t from the component_info_t struct. * d397d74a src/components/example/example.c: Remove fields now in PAPI_os_info_t from the example component. * 8cd5c8e0 src/aix.c src/freebsd.c src/linux-bgp.c...: Modify all the substrates to use _papi_os_info. instead of _papi_hwd[0]->cmp_info for the values moved to the OS struct * 58855d3a src/papi_internal.h: Add padding for future expansion to PAPI_os_info_t Add _papi_hwi_init_os(void); definition * ea1930e1 src/papi_internal.h: Add new PAPI_os_info_t structure to papi_internal.h * 0eac1b29 src/utils/multiplex_cost.c: Modify multiplex_cost to properly use the API_get_opt() interface to get itimer data, rather than directly accessing the fields from the cmp_info structure. This would have broken after the OS split. * 87c2aa2f src/ctests/subinfo.c: subinfo was printing itimer data from the cmpinfo structure. These values will not be in cmpinfo once the OS split happens. * f2c62d50 src/components/vmware/vmware.h: Clean up the VMware Header a bit 2012-02-17 * 6f0c1230 src/aix.c src/components/coretemp/linux-coretemp.c src/components/coretemp_freebsd/coretemp_freebsd.c...: The git conversion reset all of the CVS $Id$ lines to just $Id$ Since we depend on the $Id$ lines for the component names, I had to go back and fix all of them to be the component names again. * 2d208d0e src/perfctr-2.6.x/usr.lib/event_set_centaur.o src/perfctr-2.6.x/usr.lib/event_set_p5.o src/perfctr-2.6.x/usr.lib/event_set_p6.o: Remove a few binary files in perfctr-2.6.x * f78bf1af src/libpfm-3.y/Makefile src/libpfm-3.y/README src/libpfm-3.y/docs/Makefile...: More cleanups from the migration, latest version of libpfm-3.y perfctr-2.[6,7] Version numbers got really confused in cvs and the git cvsimport didn't know that eg 1.1.1.28 > 1.1 ( see perfctr-2.6.x/CHANGES revision 1.1.1.28.6.1 :~) * e8aa2e61 INSTALL.txt: Explicitly state that 3.7 was the last version of PAPI with good windows support. * 546901fa src/components/cuda/linux-cuda.c: Modified CUDA component so that a PAPI version - that was configured with CUDA - will successfully build on a machine that does not have GPUs. 2012-02-16 * 49d9f71c src/.gitignore: Add a .gitignore file with the files that PAPI autogenerates. This way they won't clutter up "git status" messages papi-5.5.1/src/0000755000307100002310000000000013013651551013244 5ustar yarkhangraduatepapi-5.5.1/src/papi_internal.c0000644000307100002310000024153013013651453016243 0ustar yarkhangraduate/****************************/ /* THIS IS OPEN SOURCE CODE */ /****************************/ /* * File: papi_internal.c * * Author: Philip Mucci * mucci@cs.utk.edu * Mods: dan terpstra * terpstra@cs.utk.edu * Mods: Min Zhou * min@cs.utk.edu * Mods: Kevin London * london@cs.utk.edu * Mods: Per Ekman * pek@pdc.kth.se * Mods: Haihang You * you@cs.utk.edu * Mods: Maynard Johnson * maynardj@us.ibm.com * Mods: Brian Sheely * bsheely@eecs.utk.edu * Mods: * * Mods: * */ #include #include #include #include #include #include #include "papi.h" #include "papi_internal.h" #include "papi_vector.h" #include "papi_memory.h" #include "sw_multiplex.h" #include "extras.h" #include "papi_preset.h" #include "cpus.h" #include "papi_common_strings.h" /* Advanced definitons */ static int default_debug_handler( int errorCode ); static long long handle_derived( EventInfo_t * evi, long long *from ); /* Global definitions used by other files */ int init_level = PAPI_NOT_INITED; int _papi_hwi_error_level = PAPI_QUIET; PAPI_debug_handler_t _papi_hwi_debug_handler = default_debug_handler; papi_mdi_t _papi_hwi_system_info; int _papi_hwi_errno = PAPI_OK; int _papi_hwi_num_errors = 0; hwi_presets_t user_defined_events[PAPI_MAX_USER_EVENTS]; int user_defined_events_count = 0; /*****************************/ /* Native Event Mapping Code */ /*****************************/ #define NATIVE_EVENT_CHUNKSIZE 1024 struct native_event_info { int cidx; int component_event; int ntv_idx; char *evt_name; }; // The following array is indexed by the papi event code (after the native bit has been removed) static struct native_event_info *_papi_native_events=NULL; static int num_native_events=0; static int num_native_chunks=0; char **_papi_errlist= NULL; static int num_error_chunks = 0; // pointer to event:mask string associated with last enum call to a components // will be NULL for non libpfm4 components // this is needed because libpfm4 event codes and papi event codes do not contain mask information char *papi_event_string = NULL; void _papi_hwi_set_papi_event_string (const char *event_string) { INTDBG("event_string: %s\n", event_string); if (papi_event_string != NULL) { free (papi_event_string); papi_event_string = NULL; } if (event_string != NULL) { papi_event_string = strdup(event_string); } return; } char * _papi_hwi_get_papi_event_string () { INTDBG("papi_event_string: %s\n", papi_event_string); return papi_event_string; } void _papi_hwi_free_papi_event_string() { if (papi_event_string != NULL) { free(papi_event_string); papi_event_string = NULL; } return; } // A place to keep the current papi event code so some component functions can fetch its value // The current event code can be stored here prior to component calls and cleared after the component returns static unsigned int papi_event_code = -1; static int papi_event_code_changed = -1; void _papi_hwi_set_papi_event_code (unsigned int event_code, int update_flag) { INTDBG("new event_code: %#x, update_flag: %d, previous event_code: %#x\n", event_code, update_flag, papi_event_code); // if call is just to reset and start over, set both flags to show nothing saved yet if (update_flag < 0) { papi_event_code_changed = -1; papi_event_code = -1; return; } // if 0, it is being set prior to calling a component, if >0 it is being changed by the component papi_event_code_changed = update_flag; // save the event code passed in papi_event_code = event_code; return; } unsigned int _papi_hwi_get_papi_event_code () { INTDBG("papi_event_code: %#x\n", papi_event_code); return papi_event_code; } /* Get the index into the ESI->NativeInfoArray for the current PAPI event code */ int _papi_hwi_get_ntv_idx (unsigned int papi_evt_code) { INTDBG("ENTER: papi_evt_code: %#x\n", papi_evt_code); int result; int event_index; if (papi_evt_code == 0) { INTDBG("EXIT: PAPI_ENOEVNT, invalid papi event code\n"); return PAPI_ENOEVNT; } event_index=papi_evt_code&PAPI_NATIVE_AND_MASK; if ((event_index<0) || (event_index>=num_native_events)) { INTDBG("EXIT: PAPI_ENOEVNT, invalid index into native event array\n"); return PAPI_ENOEVNT; } result=_papi_native_events[event_index].ntv_idx; INTDBG("EXIT: result: %d\n", result); return result; } // // Check for the presence of a component name or pmu name in the event string. // If found check if it matches this component or one of the pmu's supported by this component. // // returns true if the event could be for this component and false if it is not for this component. // if there is no component or pmu name then it could be for this component and returns true. // static int is_supported_by_component(int cidx, char *event_name) { INTDBG("ENTER: cidx: %d, event_name: %s\n", cidx, event_name); int i; int component_name = 0; int pmu_name = 0; char *wptr = NULL; // if event does not have a component name or pmu name, return to show it could be supported by this component // when component and pmu names are not provided, we just have to call the components to see if they recognize the event // // look for component names first if ((wptr = strstr(event_name, ":::")) != NULL) { component_name = 1; } else if ((wptr = strstr(event_name, "::")) != NULL) { pmu_name = 1; } else { INTDBG("EXIT: No Component or PMU name in event string, try this component\n"); // need to force all components to be called to find owner of this event // ???? can we assume the default pmu when no component or pmu name is provided ???? return 1; } // get a temporary copy of the component or pmu name int name_len = wptr - event_name; wptr = strdup(event_name); wptr[name_len] = '\0'; // if a component name was found, compare it to the component name in the component info structure if (component_name) { // INTDBG("component_name: %s\n", _papi_hwd[cidx]->cmp_info.name); if (strcmp (wptr, _papi_hwd[cidx]->cmp_info.name) == 0) { free (wptr); INTDBG("EXIT: Component %s supports this event\n", _papi_hwd[cidx]->cmp_info.name); return 1; } } // if a pmu name was found, compare it to the pmu name list if the component info structure (if there is one) if (pmu_name) { for ( i=0 ; icmp_info.pmu_names[i] == NULL) { continue; } // INTDBG("pmu_name[%d]: %p (%s)\n", i, _papi_hwd[cidx]->cmp_info.pmu_names[i], _papi_hwd[cidx]->cmp_info.pmu_names[i]); if (strcmp (wptr, _papi_hwd[cidx]->cmp_info.pmu_names[i]) == 0) { INTDBG("EXIT: Component %s supports PMU %s and this event\n", _papi_hwd[cidx]->cmp_info.name, wptr); free (wptr); return 1; } } } free (wptr); INTDBG("EXIT: Component does not support this event\n"); return 0; } /** @internal * @class _papi_hwi_prefix_component_name * @brief Prefixes a component's name to each of its events. * @param *component_name * @param *event_name * @param *out * @param *out_len * * Given sane component_name and event_name it returns component_name:::event_name. * It is safe in the case that event_name == out and it checks against the * traditional PAPI 'cpu' components, opting to not prepend those. */ int _papi_hwi_prefix_component_name( char *component_name, char *event_name, char *out, int out_len) { int size1, size2; char temp[out_len]; size1 = strlen(event_name); size2 = strlen(component_name); /* sanity checks */ if ( size1 == 0 ) { return (PAPI_EBUG); /* hopefully event_name always has length?! */ } if ( size1 >= out_len ) return (PAPI_ENOMEM); /* Guard against event_name == out */ memcpy( temp, event_name, out_len ); /* no component name to prefix */ if ( size2 == 0 ) { sprintf(out, "%s%c", temp, '\0' ); return (PAPI_OK); } /* Don't prefix 'cpu' component names for now */ if ( strstr(component_name, "pe") || strstr(component_name, "bgq") || strstr(component_name, "bgp") ) { sprintf( out, "%s%c", temp, '\0'); return (PAPI_OK); } /* strlen(component_name) + ::: + strlen(event_name) + NULL */ if ( size1+size2+3+1 > out_len ) return (PAPI_ENOMEM); sprintf( out, "%s:::%s%c" , component_name, temp, '\0'); return (PAPI_OK); } /** @internal * @class _papi_hwi_strip_component_prefix * @brief Strip off cmp_name::: from an event name. * * @param *event_name * @return Start of the component consumable portion of the name. * * This function checks specifically for ':::' and will return the start of * event_name if it doesn't find the ::: . */ char *_papi_hwi_strip_component_prefix(char *event_name) { char *start = NULL; /* We assume ::: is the seperator * eg: * papi_component:::event_name */ start = strstr( event_name, ":::" ); if ( start != NULL ) start+= 3; /* return the actual start of event_name */ else start = event_name; return (start); } /* find the papi event code (4000xxx) associated with the specified component, native event, and event name */ static int _papi_hwi_find_native_event(int cidx, int event, const char *event_name) { INTDBG("ENTER: cidx: %x, event: %#x, event_name: %s\n", cidx, event, event_name); int i; // if no event name passed in, it can not be found if (event_name == NULL) { INTDBG("EXIT: PAPI_ENOEVNT\n"); return PAPI_ENOEVNT; } for(i=0;i=num_native_chunks*NATIVE_EVENT_CHUNKSIZE) { num_native_chunks++; _papi_native_events=realloc(_papi_native_events, num_native_chunks*NATIVE_EVENT_CHUNKSIZE* sizeof(struct native_event_info)); if (_papi_native_events==NULL) { new_native_event=PAPI_ENOMEM; goto native_alloc_early_out; } } _papi_native_events[num_native_events].cidx=cidx; _papi_native_events[num_native_events].component_event=ntv_event; _papi_native_events[num_native_events].ntv_idx=ntv_idx; if (event_name != NULL) { _papi_native_events[num_native_events].evt_name=strdup(event_name); } else { _papi_native_events[num_native_events].evt_name=NULL; } new_native_event=num_native_events|PAPI_NATIVE_MASK; num_native_events++; native_alloc_early_out: _papi_hwi_unlock( INTERNAL_LOCK ); INTDBG("EXIT: new_native_event: %#x, num_native_events: %d\n", new_native_event, num_native_events); return new_native_event; } /** @internal * @class _papi_hwi_add_error * * Adds a new error string to PAPI's internal store. * MAKE SURE you are not holding INTERNAL_LOCK when you call me! */ static int _papi_hwi_add_error( char *error ) { INTDBG("Adding a new Error message |%s|\n", error); _papi_hwi_lock(INTERNAL_LOCK); if (_papi_hwi_num_errors >= num_error_chunks*NATIVE_EVENT_CHUNKSIZE) { num_error_chunks++; _papi_errlist=realloc(_papi_errlist, num_error_chunks*NATIVE_EVENT_CHUNKSIZE*sizeof(char *)); if (_papi_errlist==NULL) { _papi_hwi_num_errors = -2; goto bail; } } _papi_errlist[_papi_hwi_num_errors] = strdup( error ); if ( _papi_errlist[_papi_hwi_num_errors] == NULL ) _papi_hwi_num_errors = -2; bail: _papi_hwi_unlock(INTERNAL_LOCK); return _papi_hwi_num_errors++; } static void _papi_hwi_cleanup_errors() { int i; if ( _papi_errlist == NULL || _papi_hwi_num_errors == 0 ) return; _papi_hwi_lock( INTERNAL_LOCK ); for (i=0; i < _papi_hwi_num_errors; i++ ) { free( _papi_errlist[i]); _papi_errlist[i] = NULL; } free( _papi_errlist ); _papi_errlist = NULL; _papi_hwi_num_errors = 0; num_error_chunks=0; _papi_hwi_unlock( INTERNAL_LOCK ); } static int _papi_hwi_lookup_error( char *error ) { int i; for (i=0; i<_papi_hwi_num_errors; i++) { if ( !strncasecmp( _papi_errlist[i], error, strlen( error ) ) ) return i; } return (-1); } /** @internal * @class _papi_hwi_publish_error * * @return * <= 0 : Code for the error. * < 0 : We couldn't get memory to allocate for your error. * * An internal interface for adding an error code to the library. * The returned code is suitable for returning to users. * */ int _papi_hwi_publish_error( char *error ) { int error_code = -1; if ( (error_code = _papi_hwi_lookup_error( error )) < 0 ) error_code = _papi_hwi_add_error(error); return (-error_code); /* internally error_code is an index, externally, it should be <= 0 */ } void _papi_hwi_init_errors(void) { /* we use add error to avoid the cost of lookups, we know the errors are not there yet */ _papi_hwi_add_error("No error"); _papi_hwi_add_error("Invalid argument"); _papi_hwi_add_error("Insufficient memory"); _papi_hwi_add_error("A System/C library call failed"); _papi_hwi_add_error("Not supported by component"); _papi_hwi_add_error("Access to the counters was lost or interrupted"); _papi_hwi_add_error("Internal error, please send mail to the developers"); _papi_hwi_add_error("Event does not exist"); _papi_hwi_add_error("Event exists, but cannot be counted due to hardware resource limits"); _papi_hwi_add_error("EventSet is currently not running"); _papi_hwi_add_error("EventSet is currently counting"); _papi_hwi_add_error("No such EventSet available"); _papi_hwi_add_error("Event in argument is not a valid preset"); _papi_hwi_add_error("Hardware does not support performance counters"); _papi_hwi_add_error("Unknown error code"); _papi_hwi_add_error("Permission level does not permit operation"); _papi_hwi_add_error("PAPI hasn't been initialized yet"); _papi_hwi_add_error("Component Index isn't set"); _papi_hwi_add_error("Not supported"); _papi_hwi_add_error("Not implemented"); _papi_hwi_add_error("Buffer size exceeded"); _papi_hwi_add_error("EventSet domain is not supported for the operation"); _papi_hwi_add_error("Invalid or missing event attributes"); _papi_hwi_add_error("Too many events or attributes"); _papi_hwi_add_error("Bad combination of features"); } int _papi_hwi_invalid_cmp( int cidx ) { return ( cidx < 0 || cidx >= papi_num_components ); } int _papi_hwi_component_index( int event_code ) { INTDBG("ENTER: event_code: %#x\n", event_code); int cidx; int event_index; /* currently assume presets are for component 0 only */ if (IS_PRESET(event_code)) { INTDBG("EXIT: Event %#x is a PRESET, assigning component %d\n", event_code,0); return 0; } /* user defined events are treated like preset events (component 0 only) */ if (IS_USER_DEFINED(event_code)) { INTDBG("EXIT: Event %#x is USER DEFINED, assigning component %d\n", event_code,0); return 0; } event_index=event_code&PAPI_NATIVE_AND_MASK; if ( (event_index < 0) || (event_index>=num_native_events)) { INTDBG("EXIT: Event index %#x is out of range, num_native_events: %d\n", event_index, num_native_events); return PAPI_ENOEVNT; } cidx=_papi_native_events[event_index].cidx; if ((cidx<0) || (cidx >= papi_num_components)) { INTDBG("EXIT: Component index %#x is out of range, papi_num_components: %d\n", cidx, papi_num_components); return PAPI_ENOCMP; } INTDBG("EXIT: Found cidx: %d event_index: %d, event_code: %#x\n", cidx, event_index, event_code); return cidx; } /* Convert an internal component event to a papi event code */ int _papi_hwi_native_to_eventcode(int cidx, int event_code, int ntv_idx, const char *event_name) { INTDBG("Entry: cidx: %d, event: %#x, ntv_idx: %d, event_name: %s\n", cidx, event_code, ntv_idx, event_name); int result; if (papi_event_code_changed > 0) { result = _papi_hwi_get_papi_event_code(); INTDBG("EXIT: papi_event_code: %#x set by the component\n", result); return result; } result=_papi_hwi_find_native_event(cidx, event_code, event_name); if (result==PAPI_ENOEVNT) { // Need to create one result=_papi_hwi_add_native_event(cidx, event_code, ntv_idx, event_name); } INTDBG("EXIT: result: %#x\n", result); return result; } /* Convert a native_event code to an internal event code */ int _papi_hwi_eventcode_to_native(int event_code) { INTDBG("ENTER: event_code: %#x\n", event_code); int result; int event_index; event_index=event_code&PAPI_NATIVE_AND_MASK; if ((event_index < 0) || (event_index>=num_native_events)) { INTDBG("EXIT: PAPI_ENOEVNT\n"); return PAPI_ENOEVNT; } result=_papi_native_events[event_index].component_event; INTDBG("EXIT: result: %#x\n", result); return result; } /*********************/ /* Utility functions */ /*********************/ void PAPIERROR( char *format, ... ) { va_list args; if ( ( _papi_hwi_error_level != PAPI_QUIET ) || ( getenv( "PAPI_VERBOSE" ) ) ) { va_start( args, format ); fprintf( stderr, "\nPAPI Error: " ); vfprintf( stderr, format, args ); fprintf( stderr, ".\n" ); va_end( args ); } } static int default_debug_handler( int errorCode ) { char str[PAPI_HUGE_STR_LEN]; if ( errorCode == PAPI_OK ) return ( errorCode ); if ( ( errorCode > 0 ) || ( -errorCode > _papi_hwi_num_errors ) ) { PAPIERROR( "%s %d,%s,Bug! Unknown error code", PAPI_ERROR_CODE_str, errorCode, "" ); return ( PAPI_EBUG ); } switch ( _papi_hwi_error_level ) { case PAPI_VERB_ECONT: case PAPI_VERB_ESTOP: /* gcc 2.96 bug fix, do not change */ /* fprintf(stderr,"%s %d: %s: %s\n",PAPI_ERROR_CODE_str,errorCode,_papi_hwi_err[-errorCode].name,_papi_hwi_err[-errorCode].descr); */ sprintf( str, "%s %d,%s", PAPI_ERROR_CODE_str, errorCode, _papi_errlist[-errorCode] ); if ( errorCode == PAPI_ESYS ) sprintf( str + strlen( str ), ": %s", strerror( errno ) ); PAPIERROR( str ); if ( _papi_hwi_error_level == PAPI_VERB_ESTOP ) abort( ); /* patch provided by will cohen of redhat */ else return errorCode; break; case PAPI_QUIET: default: return errorCode; } return ( PAPI_EBUG ); /* Never get here */ } static int allocate_eventset_map( DynamicArray_t * map ) { /* Allocate and clear the Dynamic Array structure */ if ( map->dataSlotArray != NULL ) papi_free( map->dataSlotArray ); memset( map, 0x00, sizeof ( DynamicArray_t ) ); /* Allocate space for the EventSetInfo_t pointers */ map->dataSlotArray = ( EventSetInfo_t ** ) papi_malloc( PAPI_INIT_SLOTS * sizeof ( EventSetInfo_t * ) ); if ( map->dataSlotArray == NULL ) { return ( PAPI_ENOMEM ); } memset( map->dataSlotArray, 0x00, PAPI_INIT_SLOTS * sizeof ( EventSetInfo_t * ) ); map->totalSlots = PAPI_INIT_SLOTS; map->availSlots = PAPI_INIT_SLOTS; map->fullSlots = 0; return ( PAPI_OK ); } static int expand_dynamic_array( DynamicArray_t * DA ) { int number; EventSetInfo_t **n; /*realloc existing PAPI_EVENTSET_MAP.dataSlotArray */ number = DA->totalSlots * 2; n = ( EventSetInfo_t ** ) papi_realloc( DA->dataSlotArray, ( size_t ) number * sizeof ( EventSetInfo_t * ) ); if ( n == NULL ) return ( PAPI_ENOMEM ); /* Need to assign this value, what if realloc moved it? */ DA->dataSlotArray = n; memset( DA->dataSlotArray + DA->totalSlots, 0x00, ( size_t ) DA->totalSlots * sizeof ( EventSetInfo_t * ) ); DA->totalSlots = number; DA->availSlots = number - DA->fullSlots; return ( PAPI_OK ); } static int EventInfoArrayLength( const EventSetInfo_t * ESI ) { return ( _papi_hwd[ESI->CmpIdx]->cmp_info.num_mpx_cntrs ); } /*========================================================================*/ /* This function allocates space for one EventSetInfo_t structure and for */ /* all of the pointers in this structure. If any malloc in this function */ /* fails, all memory malloced to the point of failure is freed, and NULL */ /* is returned. Upon success, a pointer to the EventSetInfo_t data */ /* structure is returned. */ /*========================================================================*/ static int create_EventSet( EventSetInfo_t ** here ) { EventSetInfo_t *ESI; ESI = ( EventSetInfo_t * ) papi_calloc( 1, sizeof ( EventSetInfo_t ) ); if ( ESI == NULL ) { return PAPI_ENOMEM; } *here = ESI; return PAPI_OK; } int _papi_hwi_assign_eventset( EventSetInfo_t *ESI, int cidx ) { INTDBG("ENTER: ESI: %p (%d), cidx: %d\n", ESI, ESI->EventSetIndex, cidx); int retval; size_t max_counters; char *ptr; unsigned int i, j; /* If component doesn't exist... */ if (_papi_hwi_invalid_cmp(cidx)) return PAPI_ECMP; /* Assigned at create time */ ESI->domain.domain = _papi_hwd[cidx]->cmp_info.default_domain; ESI->granularity.granularity = _papi_hwd[cidx]->cmp_info.default_granularity; ESI->CmpIdx = cidx; /* ??? */ max_counters = ( size_t ) _papi_hwd[cidx]->cmp_info.num_mpx_cntrs; ESI->ctl_state = (hwd_control_state_t *) papi_calloc( 1, (size_t) _papi_hwd[cidx]->size.control_state ); ESI->sw_stop = (long long *) papi_calloc( ( size_t ) max_counters, sizeof ( long long ) ); ESI->hw_start = ( long long * ) papi_calloc( ( size_t ) max_counters, sizeof ( long long ) ); ESI->EventInfoArray = ( EventInfo_t * ) papi_calloc( (size_t) max_counters, sizeof ( EventInfo_t ) ); /* allocate room for the native events and for the component-private */ /* register structures */ /* ugh is there a cleaner way to allocate this? vmw */ ESI->NativeInfoArray = ( NativeInfo_t * ) papi_calloc( ( size_t ) max_counters, sizeof ( NativeInfo_t )); ESI->NativeBits = papi_calloc(( size_t ) max_counters, ( size_t ) _papi_hwd[cidx]->size.reg_value ); /* NOTE: the next two malloc allocate blocks of memory that are later */ /* parcelled into overflow and profile arrays */ ESI->overflow.deadline = ( long long * ) papi_malloc( ( sizeof ( long long ) + sizeof ( int ) * 3 ) * ( size_t ) max_counters ); ESI->profile.prof = ( PAPI_sprofil_t ** ) papi_malloc( ( sizeof ( PAPI_sprofil_t * ) * ( size_t ) max_counters + ( size_t ) max_counters * sizeof ( int ) * 4 ) ); /* If any of these allocations failed, free things up and fail */ if ( ( ESI->ctl_state == NULL ) || ( ESI->sw_stop == NULL ) || ( ESI->hw_start == NULL ) || ( ESI->NativeInfoArray == NULL ) || ( ESI->NativeBits == NULL ) || ( ESI->EventInfoArray == NULL ) || ( ESI->profile.prof == NULL ) || ( ESI->overflow.deadline == NULL ) ) { if ( ESI->sw_stop ) papi_free( ESI->sw_stop ); if ( ESI->hw_start ) papi_free( ESI->hw_start ); if ( ESI->EventInfoArray ) papi_free( ESI->EventInfoArray ); if ( ESI->NativeInfoArray ) papi_free( ESI->NativeInfoArray ); if ( ESI->NativeBits ) papi_free( ESI->NativeBits ); if ( ESI->ctl_state ) papi_free( ESI->ctl_state ); if ( ESI->overflow.deadline ) papi_free( ESI->overflow.deadline ); if ( ESI->profile.prof ) papi_free( ESI->profile.prof ); papi_free( ESI ); return PAPI_ENOMEM; } /* Carve up the overflow block into separate arrays */ ptr = ( char * ) ESI->overflow.deadline; ptr += sizeof ( long long ) * max_counters; ESI->overflow.threshold = ( int * ) ptr; ptr += sizeof ( int ) * max_counters; ESI->overflow.EventIndex = ( int * ) ptr; ptr += sizeof ( int ) * max_counters; ESI->overflow.EventCode = ( int * ) ptr; /* Carve up the profile block into separate arrays */ ptr = ( char * ) ESI->profile.prof + ( sizeof ( PAPI_sprofil_t * ) * max_counters ); ESI->profile.count = ( int * ) ptr; ptr += sizeof ( int ) * max_counters; ESI->profile.threshold = ( int * ) ptr; ptr += sizeof ( int ) * max_counters; ESI->profile.EventIndex = ( int * ) ptr; ptr += sizeof ( int ) * max_counters; ESI->profile.EventCode = ( int * ) ptr; /* initialize_EventInfoArray */ for ( i = 0; i < max_counters; i++ ) { ESI->EventInfoArray[i].event_code=( unsigned int ) PAPI_NULL; ESI->EventInfoArray[i].ops = NULL; ESI->EventInfoArray[i].derived=NOT_DERIVED; for ( j = 0; j < PAPI_EVENTS_IN_DERIVED_EVENT; j++ ) { ESI->EventInfoArray[i].pos[j] = PAPI_NULL; } } /* initialize_NativeInfoArray */ for( i = 0; i < max_counters; i++ ) { ESI->NativeInfoArray[i].ni_event = -1; ESI->NativeInfoArray[i].ni_position = -1; ESI->NativeInfoArray[i].ni_papi_code = -1; ESI->NativeInfoArray[i].ni_owners = 0; ESI->NativeInfoArray[i].ni_bits = ((unsigned char*)ESI->NativeBits) + (i*_papi_hwd[cidx]->size.reg_value); } ESI->NativeCount = 0; ESI->state = PAPI_STOPPED; /* these used to be init_config */ retval = _papi_hwd[cidx]->init_control_state( ESI->ctl_state ); retval |= _papi_hwd[cidx]->set_domain( ESI->ctl_state, ESI->domain.domain); return retval; } /*========================================================================*/ /* This function should free memory for one EventSetInfo_t structure. */ /* The argument list consists of a pointer to the EventSetInfo_t */ /* structure, *ESI. */ /* The calling function should check for ESI==NULL. */ /*========================================================================*/ void _papi_hwi_free_EventSet( EventSetInfo_t * ESI ) { _papi_hwi_cleanup_eventset( ESI ); #ifdef DEBUG memset( ESI, 0x00, sizeof ( EventSetInfo_t ) ); #endif papi_free( ESI ); } static int add_EventSet( EventSetInfo_t * ESI, ThreadInfo_t * master ) { DynamicArray_t *map = &_papi_hwi_system_info.global_eventset_map; int i, errorCode; _papi_hwi_lock( INTERNAL_LOCK ); if ( map->availSlots == 0 ) { errorCode = expand_dynamic_array( map ); if ( errorCode < PAPI_OK ) { _papi_hwi_unlock( INTERNAL_LOCK ); return ( errorCode ); } } i = 0; for ( i = 0; i < map->totalSlots; i++ ) { if ( map->dataSlotArray[i] == NULL ) { ESI->master = master; ESI->EventSetIndex = i; map->fullSlots++; map->availSlots--; map->dataSlotArray[i] = ESI; _papi_hwi_unlock( INTERNAL_LOCK ); return ( PAPI_OK ); } } _papi_hwi_unlock( INTERNAL_LOCK ); return ( PAPI_EBUG ); } int _papi_hwi_create_eventset( int *EventSet, ThreadInfo_t * handle ) { EventSetInfo_t *ESI; int retval; /* Is the EventSet already in existence? */ if ( ( EventSet == NULL ) || ( handle == NULL ) ) return PAPI_EINVAL; if ( *EventSet != PAPI_NULL ) return PAPI_EINVAL; /* Well, then allocate a new one. Use n to keep track of a NEW EventSet */ retval = create_EventSet( &ESI ); if ( retval != PAPI_OK ) return retval; ESI->CmpIdx = -1; /* when eventset is created, it is not decided yet which component it belongs to, until first event is added */ ESI->state = PAPI_STOPPED; /* Add it to the global table */ retval = add_EventSet( ESI, handle ); if ( retval < PAPI_OK ) { _papi_hwi_free_EventSet( ESI ); return retval ; } *EventSet = ESI->EventSetIndex; INTDBG( "(%p,%p): new EventSet in slot %d\n", ( void * ) EventSet, handle, *EventSet ); return retval; } /* This function returns the index of the the next free slot in the EventInfoArray. If EventCode is already in the list, it returns PAPI_ECNFLCT. */ static int get_free_EventCodeIndex( const EventSetInfo_t * ESI, unsigned int EventCode ) { int k; int lowslot = PAPI_ECNFLCT; int limit = EventInfoArrayLength( ESI ); /* Check for duplicate events and get the lowest empty slot */ for ( k = 0; k < limit; k++ ) { if ( ESI->EventInfoArray[k].event_code == EventCode ) return ( PAPI_ECNFLCT ); /*if ((ESI->EventInfoArray[k].event_code == PAPI_NULL) && (lowslot == PAPI_ECNFLCT)) */ if ( ESI->EventInfoArray[k].event_code == ( unsigned int ) PAPI_NULL ) { lowslot = k; break; } } return ( lowslot ); } /* This function returns the index of the EventCode or error */ /* Index to what? The index to everything stored EventCode in the */ /* EventSet. */ int _papi_hwi_lookup_EventCodeIndex( const EventSetInfo_t * ESI, unsigned int EventCode ) { int i; int limit = EventInfoArrayLength( ESI ); for ( i = 0; i < limit; i++ ) { if ( ESI->EventInfoArray[i].event_code == EventCode ) { return i; } } return PAPI_EINVAL; } /* This function only removes empty EventSets */ int _papi_hwi_remove_EventSet( EventSetInfo_t * ESI ) { DynamicArray_t *map = &_papi_hwi_system_info.global_eventset_map; int i; i = ESI->EventSetIndex; _papi_hwi_lock( INTERNAL_LOCK ); _papi_hwi_free_EventSet( ESI ); /* do bookkeeping for PAPI_EVENTSET_MAP */ map->dataSlotArray[i] = NULL; map->availSlots++; map->fullSlots--; _papi_hwi_unlock( INTERNAL_LOCK ); return PAPI_OK; } /* this function checks if an event is already in an EventSet Success, return ESI->NativeInfoArray[] index Fail, return PAPI_ENOEVNT; */ static int event_already_in_eventset( EventSetInfo_t * ESI, int papi_event ) { INTDBG( "ENTER: ESI: %p, papi_event: %#x\n", ESI, papi_event); int i; int nevt = _papi_hwi_eventcode_to_native(papi_event); /* to find the native event from the native events list */ for( i = 0; i < ESI->NativeCount; i++ ) { if ( nevt == ESI->NativeInfoArray[i].ni_event ) { // Also need to check papi event code if set because the same event with different masks // will generate the same libpfm4 event code (what was checked above). But there will be // different papi events created for it and they need to be handled separately. if (papi_event == ESI->NativeInfoArray[i].ni_papi_code) { INTDBG( "EXIT: event: %#x already mapped at index: %d\n", papi_event, i); return i; } } } INTDBG( "EXIT: PAPI_ENOEVNT\n"); return PAPI_ENOEVNT; } /* This function goes through the events in an EventSet's EventInfoArray */ /* And maps each event (whether native or part of a preset) to */ /* an event in the EventSets NativeInfoArray. */ /* We need to do this every time a native event is added to or removed */ /* from an eventset. */ /* It is also called after a update controlstate as the components are */ /* allowed to re-arrange the native events to fit hardware constraints. */ void _papi_hwi_map_events_to_native( EventSetInfo_t *ESI) { INTDBG("ENTER: ESI: %p, ESI->EventInfoArray: %p, ESI->NativeInfoArray: %p, ESI->NumberOfEvents: %d, ESI->NativeCount: %d\n", ESI, ESI->EventInfoArray, ESI->NativeInfoArray, ESI->NumberOfEvents, ESI->NativeCount); int i, event, k, n, preset_index = 0, nevt; int total_events = ESI->NumberOfEvents; event = 0; for( i = 0; i < total_events; i++ ) { /* find the first event that isn't PAPI_NULL */ /* Is this really necessary? --vmw */ while ( ESI->EventInfoArray[event].event_code == ( unsigned int ) PAPI_NULL ) { event++; } /* If it's a preset */ if ( IS_PRESET(ESI->EventInfoArray[event].event_code) ) { preset_index = ( int ) ESI->EventInfoArray[event].event_code & PAPI_PRESET_AND_MASK; /* walk all sub-events in the preset */ for( k = 0; k < PAPI_EVENTS_IN_DERIVED_EVENT; k++ ) { nevt = _papi_hwi_presets[preset_index].code[k]; if ( nevt == PAPI_NULL ) { break; } INTDBG("Looking for subevent %#x\n",nevt); /* Match each sub-event to something in the Native List */ for( n = 0; n < ESI->NativeCount; n++ ) { if ( nevt == ESI->NativeInfoArray[n].ni_papi_code ) { INTDBG("Found papi event: %#x, &ESI->NativeInfoArray[%d]: %p, ni_event: %#x, ni_position %d\n", nevt, n, &(ESI->NativeInfoArray[n]), ESI->NativeInfoArray[n].ni_event, ESI->NativeInfoArray[n].ni_position); ESI->EventInfoArray[event].pos[k] = ESI->NativeInfoArray[n].ni_position; break; } } } } /* If it's a native event */ else if( IS_NATIVE(ESI->EventInfoArray[event].event_code) ) { nevt = ( int ) ESI->EventInfoArray[event].event_code; // get index into native info array for this event int nidx = event_already_in_eventset( ESI, nevt ); // if not found, then we need to return an error if (nidx == PAPI_ENOEVNT) { INTDBG("EXIT: needed event not found\n"); return; } ESI->EventInfoArray[event].pos[0] = ESI->NativeInfoArray[nidx].ni_position; INTDBG("nidx: %d, ni_position: %d\n", nidx, ESI->NativeInfoArray[nidx].ni_position); } /* If it's a user-defined event */ else if ( IS_USER_DEFINED(ESI->EventInfoArray[event].event_code) ) { preset_index = ( int ) ESI->EventInfoArray[event].event_code & PAPI_UE_AND_MASK; for ( k = 0; k < PAPI_EVENTS_IN_DERIVED_EVENT; k++ ) { nevt = user_defined_events[preset_index].code[k]; INTDBG("nevt: %#x, user_defined_events[%d].code[%d]: %#x, code[%d]: %#x\n", nevt, preset_index, k, user_defined_events[preset_index].code[k], k+1, user_defined_events[preset_index].code[k+1]); if ( nevt == PAPI_NULL ) break; /* Match each sub-event to something in the Native List */ for ( n = 0; n < ESI->NativeCount; n++ ) { // if this is the event we are looking for, set its position and exit inner loop to look for next sub-event if ( _papi_hwi_eventcode_to_native(nevt) == ESI->NativeInfoArray[n].ni_event ) { ESI->EventInfoArray[event].pos[k] = ESI->NativeInfoArray[n].ni_position; break; } } } } event++; } INTDBG("EXIT: \n"); return; } static int add_native_fail_clean( EventSetInfo_t *ESI, int nevt ) { INTDBG("ENTER: ESI: %p, nevt: %#x\n", ESI, nevt); int i, max_counters; int cidx; cidx = _papi_hwi_component_index( nevt ); if (cidx<0) return PAPI_ENOCMP; max_counters = _papi_hwd[cidx]->cmp_info.num_mpx_cntrs; /* to find the native event from the native events list */ for( i = 0; i < max_counters; i++ ) { // INTDBG("ESI->NativeInfoArray[%d]: %p, ni_event: %#x, ni_papi_event_code: %#x, ni_position: %d, ni_owners: %d\n", // i, &(ESI->NativeInfoArray[i]), ESI->NativeInfoArray[i].ni_event, ESI->NativeInfoArray[i].ni_papi_code, ESI->NativeInfoArray[i].ni_position, ESI->NativeInfoArray[i].ni_owners); if ( nevt == ESI->NativeInfoArray[i].ni_papi_code ) { ESI->NativeInfoArray[i].ni_owners--; /* to clean the entry in the nativeInfo array */ if ( ESI->NativeInfoArray[i].ni_owners == 0 ) { ESI->NativeInfoArray[i].ni_event = -1; ESI->NativeInfoArray[i].ni_position = -1; ESI->NativeInfoArray[i].ni_papi_code = -1; ESI->NativeCount--; } INTDBG( "EXIT: nevt: %#x, returned: %d\n", nevt, i); return i; } } INTDBG( "EXIT: returned: -1\n"); return -1; } /* since update_control_state trashes overflow settings, this puts things back into balance. */ static int update_overflow( EventSetInfo_t * ESI ) { int i, retval = PAPI_OK; if ( ESI->overflow.flags & PAPI_OVERFLOW_HARDWARE ) { for( i = 0; i < ESI->overflow.event_counter; i++ ) { retval = _papi_hwd[ESI->CmpIdx]->set_overflow( ESI, ESI->overflow.EventIndex[i], ESI->overflow.threshold[i] ); if ( retval != PAPI_OK ) { break; } } } return retval; } /* this function is called by _papi_hwi_add_event when adding native events ESI: event set to add the events to nevnt: pointer to array of native event table indexes to add size: number of native events to add out: ??? return: < 0 = error 0 = no new events added 1 = new events added */ static int add_native_events( EventSetInfo_t *ESI, unsigned int *nevt, int size, EventInfo_t *out ) { INTDBG ("ENTER: ESI: %p, nevt: %p, size: %d, out: %p\n", ESI, nevt, size, out); int nidx, i, j, added_events = 0; int retval, retval2; int max_counters; hwd_context_t *context; max_counters = _papi_hwd[ESI->CmpIdx]->cmp_info.num_mpx_cntrs; /* Walk through the list of native events, adding them */ for( i = 0; i < size; i++ ) { /* Check to see if event is already in EventSet */ nidx = event_already_in_eventset( ESI, nevt[i] ); if ( nidx >= 0 ) { /* Event is already there. Set position */ out->pos[i] = ESI->NativeInfoArray[nidx].ni_position; ESI->NativeInfoArray[nidx].ni_owners++; continue; } /* Event wasn't already there */ if ( ESI->NativeCount == max_counters ) { /* No more room in counters! */ for( j = 0; j < i; j++ ) { if ( ( nidx = add_native_fail_clean( ESI, nevt[j] ) ) >= 0 ) { out->pos[j] = -1; continue; } INTDBG( "should not happen!\n" ); } INTDBG( "EXIT: counters are full!\n" ); return PAPI_ECOUNT; } /* there is an empty slot for the native event; */ /* initialize the native index for the new added event */ INTDBG( "Adding nevt[%d]: %#x, ESI->NativeInfoArray[%d]: %p, Component: %d\n", i, nevt[i], ESI->NativeCount, &ESI->NativeInfoArray[ESI->NativeCount], ESI->CmpIdx ); ESI->NativeInfoArray[ESI->NativeCount].ni_event = _papi_hwi_eventcode_to_native(nevt[i]); ESI->NativeInfoArray[ESI->NativeCount].ni_papi_code = nevt[i]; ESI->NativeInfoArray[ESI->NativeCount].ni_owners = 1; ESI->NativeCount++; added_events++; } INTDBG("added_events: %d\n", added_events); /* if we added events we need to tell the component so it */ /* can add them too. */ if ( added_events ) { /* get the context we should use for this event set */ context = _papi_hwi_get_context( ESI, NULL ); if ( _papi_hwd[ESI->CmpIdx]->allocate_registers( ESI ) == PAPI_OK ) { retval = _papi_hwd[ESI->CmpIdx]->update_control_state( ESI->ctl_state, ESI->NativeInfoArray, ESI->NativeCount, context); if ( retval != PAPI_OK ) { clean: for( i = 0; i < size; i++ ) { if ( ( nidx = add_native_fail_clean( ESI, nevt[i] ) ) >= 0 ) { out->pos[i] = -1; continue; } INTDBG( "should not happen!\n" ); } /* re-establish the control state after the previous error */ retval2 = _papi_hwd[ESI->CmpIdx]->update_control_state( ESI->ctl_state, ESI->NativeInfoArray, ESI->NativeCount, context); if ( retval2 != PAPI_OK ) { PAPIERROR("update_control_state failed to re-establish working events!" ); INTDBG( "EXIT: update_control_state returned: %d\n", retval2); return retval2; } INTDBG( "EXIT: update_control_state returned: %d\n", retval); return retval; } INTDBG( "EXIT: update_control_state returned: %d, we return: 1 (need remap)\n", retval); return 1; /* need remap */ } else { retval = PAPI_EMISC; goto clean; } } INTDBG( "EXIT: PAPI_OK\n"); return PAPI_OK; } int _papi_hwi_add_event( EventSetInfo_t * ESI, int EventCode ) { INTDBG("ENTER: ESI: %p (%d), EventCode: %#x\n", ESI, ESI->EventSetIndex, EventCode); int i, j, thisindex, remap, retval = PAPI_OK; int cidx; cidx=_papi_hwi_component_index( EventCode ); if (cidx<0) return PAPI_ENOCMP; /* Sanity check that the new EventCode is from the same component */ /* as previous events. */ if ( ESI->CmpIdx < 0 ) { if ( ( retval = _papi_hwi_assign_eventset( ESI, cidx)) != PAPI_OK ) { INTDBG("EXIT: Error assigning eventset to component index %d\n", cidx); return retval; } } else { if ( ESI->CmpIdx != cidx ) { INTDBG("EXIT: Event is not valid for component index %d\n", cidx); return PAPI_EINVAL; } } /* Make sure the event is not present and get the next free slot. */ thisindex = get_free_EventCodeIndex( ESI, ( unsigned int ) EventCode ); if ( thisindex < PAPI_OK ) { return thisindex; } INTDBG("Adding event to slot %d of EventSet %d\n",thisindex,ESI->EventSetIndex); /* If it is a software MPX EventSet, add it to the multiplex data structure */ /* and this thread's multiplex list */ if ( !_papi_hwi_is_sw_multiplex( ESI ) ) { /* Handle preset case */ if ( IS_PRESET(EventCode) ) { int count; int preset_index = EventCode & ( int ) PAPI_PRESET_AND_MASK; /* Check if it's within the valid range */ if ( ( preset_index < 0 ) || ( preset_index >= PAPI_MAX_PRESET_EVENTS ) ) { return PAPI_EINVAL; } /* count the number of native events in this preset */ count = ( int ) _papi_hwi_presets[preset_index].count; /* Check if event exists */ if ( !count ) { return PAPI_ENOEVNT; } /* check if the native events have been used as overflow events */ /* this is not allowed */ if ( ESI->state & PAPI_OVERFLOWING ) { for( i = 0; i < count; i++ ) { for( j = 0; j < ESI->overflow.event_counter; j++ ) { if ( ESI->overflow.EventCode[j] ==(int) ( _papi_hwi_presets[preset_index].code[i] ) ) { return PAPI_ECNFLCT; } } } } /* Try to add the preset. */ remap = add_native_events( ESI, _papi_hwi_presets[preset_index].code, count, &ESI->EventInfoArray[thisindex] ); if ( remap < 0 ) { return remap; } else { /* Fill in the EventCode (machine independent) information */ ESI->EventInfoArray[thisindex].event_code = ( unsigned int ) EventCode; ESI->EventInfoArray[thisindex].derived = _papi_hwi_presets[preset_index].derived_int; ESI->EventInfoArray[thisindex].ops = _papi_hwi_presets[preset_index].postfix; ESI->NumberOfEvents++; _papi_hwi_map_events_to_native( ESI ); } } /* Handle adding Native events */ else if ( IS_NATIVE(EventCode) ) { /* Check if native event exists */ if ( _papi_hwi_query_native_event( ( unsigned int ) EventCode ) != PAPI_OK ) { return PAPI_ENOEVNT; } /* check if the native events have been used as overflow events */ /* This is not allowed */ if ( ESI->state & PAPI_OVERFLOWING ) { for( j = 0; j < ESI->overflow.event_counter; j++ ) { if ( EventCode == ESI->overflow.EventCode[j] ) { return PAPI_ECNFLCT; } } } /* Try to add the native event. */ remap = add_native_events( ESI, (unsigned int *)&EventCode, 1, &ESI->EventInfoArray[thisindex] ); if ( remap < 0 ) { return remap; } else { /* Fill in the EventCode (machine independent) information */ ESI->EventInfoArray[thisindex].event_code = ( unsigned int ) EventCode; ESI->NumberOfEvents++; _papi_hwi_map_events_to_native( ESI ); } } else if ( IS_USER_DEFINED( EventCode ) ) { int count; int index = EventCode & PAPI_UE_AND_MASK; if ( index < 0 || index >= user_defined_events_count ) return ( PAPI_EINVAL ); count = ( int ) user_defined_events[index].count; for ( i = 0; i < count; i++ ) { for ( j = 0; j < ESI->overflow.event_counter; j++ ) { if ( ESI->overflow.EventCode[j] == (int)(user_defined_events[index].code[i]) ) { return ( PAPI_EBUG ); } } } remap = add_native_events( ESI, user_defined_events[index].code, count, &ESI->EventInfoArray[thisindex] ); if ( remap < 0 ) { return remap; } else { ESI->EventInfoArray[thisindex].event_code = (unsigned int) EventCode; ESI->EventInfoArray[thisindex].derived = user_defined_events[index].derived_int; ESI->EventInfoArray[thisindex].ops = user_defined_events[index].postfix; ESI->NumberOfEvents++; _papi_hwi_map_events_to_native( ESI ); } } else { /* not Native, Preset, or User events */ return PAPI_EBUG; } } else { /* Multiplexing is special. See multiplex.c */ retval = mpx_add_event( &ESI->multiplex.mpx_evset, EventCode, ESI->domain.domain, ESI->granularity.granularity ); if ( retval < PAPI_OK ) { return retval; } /* Relevant (???) */ ESI->EventInfoArray[thisindex].event_code = ( unsigned int ) EventCode; ESI->EventInfoArray[thisindex].derived = NOT_DERIVED; ESI->NumberOfEvents++; /* event is in the EventInfoArray but not mapped to the NativeEvents */ /* this causes issues if you try to set overflow on the event. */ /* in theory this wouldn't matter anyway. */ } /* reinstate the overflows if any */ retval=update_overflow( ESI ); return retval; } static int remove_native_events( EventSetInfo_t *ESI, int *nevt, int size ) { INTDBG( "Entry: ESI: %p, nevt: %p, size: %d\n", ESI, nevt, size); NativeInfo_t *native = ESI->NativeInfoArray; hwd_context_t *context; int i, j, zero = 0, retval; /* Remove the references to this event from the native events: for all the metrics in this event, compare to each native event in this event set, and decrement owners if they match */ for( i = 0; i < size; i++ ) { int cevt = _papi_hwi_eventcode_to_native(nevt[i]); // INTDBG( "nevt[%d]: %#x, cevt: %#x\n", i, nevt[i], cevt); for( j = 0; j < ESI->NativeCount; j++ ) { if ((native[j].ni_event == cevt) && (native[j].ni_papi_code == nevt[i]) ) { // INTDBG( "native[%d]: %p, ni_papi_code: %#x, ni_event: %#x, ni_position: %d, ni_owners: %d\n", // j, &(native[j]), native[j].ni_papi_code, native[j].ni_event, native[j].ni_position, native[j].ni_owners); native[j].ni_owners--; if ( native[j].ni_owners == 0 ) { zero++; } break; } } } /* Remove any native events from the array if owners dropped to zero. The NativeInfoArray must be dense, with no empty slots, so if we remove an element, we must compact the list */ for( i = 0; i < ESI->NativeCount; i++ ) { if ( native[i].ni_event == -1 ) continue; if ( native[i].ni_owners == 0 ) { int copy = 0; int sz = _papi_hwd[ESI->CmpIdx]->size.reg_value; for( j = ESI->NativeCount - 1; j > i; j-- ) { if ( native[j].ni_event == -1 || native[j].ni_owners == 0 ) continue; else { /* copy j into i */ native[i].ni_event = native[j].ni_event; native[i].ni_position = native[j].ni_position; native[i].ni_owners = native[j].ni_owners; /* copy opaque [j].ni_bits to [i].ni_bits */ memcpy( native[i].ni_bits, native[j].ni_bits, ( size_t ) sz ); /* reset j to initialized state */ native[j].ni_event = -1; native[j].ni_position = -1; native[j].ni_owners = 0; copy++; break; } } if ( copy == 0 ) { /* set this structure back to empty state */ /* ni_owners is already 0 and contents of ni_bits doesn't matter */ native[i].ni_event = -1; native[i].ni_position = -1; } } } INTDBG( "ESI->NativeCount: %d, zero: %d\n", ESI->NativeCount, zero); /* to reset hwd_control_state values */ ESI->NativeCount -= zero; /* If we removed any elements, clear the now empty slots, reinitialize the index, and update the count. Then send the info down to the component to update the hwd control structure. */ retval = PAPI_OK; if ( zero ) { /* get the context we should use for this event set */ context = _papi_hwi_get_context( ESI, NULL ); retval = _papi_hwd[ESI->CmpIdx]->update_control_state( ESI->ctl_state, native, ESI->NativeCount, context); if ( retval == PAPI_OK ) retval = update_overflow( ESI ); } return ( retval ); } int _papi_hwi_remove_event( EventSetInfo_t * ESI, int EventCode ) { int j = 0, retval, thisindex; EventInfo_t *array; thisindex = _papi_hwi_lookup_EventCodeIndex( ESI, ( unsigned int ) EventCode ); if ( thisindex < PAPI_OK ) return ( thisindex ); /* If it is a MPX EventSet, remove it from the multiplex data structure and this threads multiplex list */ if ( _papi_hwi_is_sw_multiplex( ESI ) ) { retval = mpx_remove_event( &ESI->multiplex.mpx_evset, EventCode ); if ( retval < PAPI_OK ) return ( retval ); } else /* Remove the events hardware dependent stuff from the EventSet */ { if ( IS_PRESET(EventCode) ) { int preset_index = EventCode & PAPI_PRESET_AND_MASK; /* Check if it's within the valid range */ if ( ( preset_index < 0 ) || ( preset_index >= PAPI_MAX_PRESET_EVENTS ) ) return PAPI_EINVAL; /* Check if event exists */ if ( !_papi_hwi_presets[preset_index].count ) return PAPI_ENOEVNT; /* Remove the preset event. */ for ( j = 0; _papi_hwi_presets[preset_index].code[j] != (unsigned int)PAPI_NULL; j++ ); retval = remove_native_events( ESI, ( int * )_papi_hwi_presets[preset_index].code, j ); if ( retval != PAPI_OK ) return ( retval ); } else if ( IS_NATIVE(EventCode) ) { /* Check if native event exists */ if ( _papi_hwi_query_native_event( ( unsigned int ) EventCode ) != PAPI_OK ) return PAPI_ENOEVNT; /* Remove the native event. */ retval = remove_native_events( ESI, &EventCode, 1 ); if ( retval != PAPI_OK ) return ( retval ); } else if ( IS_USER_DEFINED( EventCode ) ) { int index = EventCode & PAPI_UE_AND_MASK; if ( (index < 0) || (index >= user_defined_events_count) ) return ( PAPI_EINVAL ); for( j = 0; j < PAPI_EVENTS_IN_DERIVED_EVENT && user_defined_events[index].code[j] != 0; j++ ) { retval = remove_native_events( ESI, ( int * )user_defined_events[index].code, j); if ( retval != PAPI_OK ) return ( retval ); } } else return ( PAPI_ENOEVNT ); } array = ESI->EventInfoArray; /* Compact the Event Info Array list if it's not the last event */ /* clear the newly empty slot in the array */ for ( ; thisindex < ESI->NumberOfEvents - 1; thisindex++ ) array[thisindex] = array[thisindex + 1]; array[thisindex].event_code = ( unsigned int ) PAPI_NULL; for ( j = 0; j < PAPI_EVENTS_IN_DERIVED_EVENT; j++ ) array[thisindex].pos[j] = PAPI_NULL; array[thisindex].ops = NULL; array[thisindex].derived = NOT_DERIVED; ESI->NumberOfEvents--; return ( PAPI_OK ); } int _papi_hwi_read( hwd_context_t * context, EventSetInfo_t * ESI, long long *values ) { INTDBG("ENTER: context: %p, ESI: %p, values: %p\n", context, ESI, values); int retval; long long *dp = NULL; int i, index; retval = _papi_hwd[ESI->CmpIdx]->read( context, ESI->ctl_state, &dp, ESI->state ); if ( retval != PAPI_OK ) { INTDBG("EXIT: retval: %d\n", retval); return retval; } /* This routine distributes hardware counters to software counters in the order that they were added. Note that the higher level EventInfoArray[i] entries may not be contiguous because the user has the right to remove an event. But if we do compaction after remove event, this function can be changed. */ for ( i = 0; i != ESI->NumberOfEvents; i++ ) { index = ESI->EventInfoArray[i].pos[0]; if ( index == -1 ) continue; INTDBG( "ESI->EventInfoArray: %p, pos[%d]: %d, dp[%d]: %lld, derived[%d]: %#x\n", ESI->EventInfoArray, i, index, index, dp[index], i, ESI->EventInfoArray[i].derived ); /* If this is not a derived event */ if ( ESI->EventInfoArray[i].derived == NOT_DERIVED ) { values[i] = dp[index]; INTDBG( "value: %#llx\n", values[i] ); } else { /* If this is a derived event */ values[i] = handle_derived( &ESI->EventInfoArray[i], dp ); #ifdef DEBUG if ( values[i] < ( long long ) 0 ) { INTDBG( "Derived Event is negative!!: %lld\n", values[i] ); } INTDBG( "derived value: %#llx \n", values[i] ); #endif } } INTDBG("EXIT: PAPI_OK\n"); return PAPI_OK; } int _papi_hwi_cleanup_eventset( EventSetInfo_t * ESI ) { int i, j, num_cntrs, retval; hwd_context_t *context; int EventCode; NativeInfo_t *native; if ( !_papi_hwi_invalid_cmp( ESI->CmpIdx ) ) { num_cntrs = _papi_hwd[ESI->CmpIdx]->cmp_info.num_mpx_cntrs; for(i=0;iEventInfoArray[i].event_code; /* skip if event not there */ if ( EventCode == PAPI_NULL ) continue; /* If it is a MPX EventSet, remove it from the multiplex */ /* data structure and this thread's multiplex list */ if ( _papi_hwi_is_sw_multiplex( ESI ) ) { retval = mpx_remove_event( &ESI->multiplex.mpx_evset, EventCode ); if ( retval < PAPI_OK ) return retval; } else { native = ESI->NativeInfoArray; /* clear out ESI->NativeInfoArray */ /* do we really need to do this, seeing as we free() it later? */ for( j = 0; j < ESI->NativeCount; j++ ) { native[j].ni_event = -1; native[j].ni_position = -1; native[j].ni_owners = 0; /* native[j].ni_bits?? */ } } /* do we really need to do this, seeing as we free() it later? */ ESI->EventInfoArray[i].event_code= ( unsigned int ) PAPI_NULL; for( j = 0; j < PAPI_EVENTS_IN_DERIVED_EVENT; j++ ) { ESI->EventInfoArray[i].pos[j] = PAPI_NULL; } ESI->EventInfoArray[i].ops = NULL; ESI->EventInfoArray[i].derived = NOT_DERIVED; } context = _papi_hwi_get_context( ESI, NULL ); /* calling with count of 0 equals a close? */ retval = _papi_hwd[ESI->CmpIdx]->update_control_state( ESI->ctl_state, NULL, 0, context); if (retval!=PAPI_OK) { return retval; } } ESI->CmpIdx = -1; ESI->NumberOfEvents = 0; ESI->NativeCount = 0; if ( ( ESI->state & PAPI_MULTIPLEXING ) && ESI->multiplex.mpx_evset ) papi_free( ESI->multiplex.mpx_evset ); if ( ( ESI->state & PAPI_CPU_ATTACH ) && ESI->CpuInfo ) _papi_hwi_shutdown_cpu( ESI->CpuInfo ); if ( ESI->ctl_state ) papi_free( ESI->ctl_state ); if ( ESI->sw_stop ) papi_free( ESI->sw_stop ); if ( ESI->hw_start ) papi_free( ESI->hw_start ); if ( ESI->EventInfoArray ) papi_free( ESI->EventInfoArray ); if ( ESI->NativeInfoArray ) papi_free( ESI->NativeInfoArray ); if ( ESI->NativeBits ) papi_free( ESI->NativeBits ); if ( ESI->overflow.deadline ) papi_free( ESI->overflow.deadline ); if ( ESI->profile.prof ) papi_free( ESI->profile.prof ); ESI->ctl_state = NULL; ESI->sw_stop = NULL; ESI->hw_start = NULL; ESI->EventInfoArray = NULL; ESI->NativeInfoArray = NULL; ESI->NativeBits = NULL; memset( &ESI->domain, 0x0, sizeof(EventSetDomainInfo_t) ); memset( &ESI->granularity, 0x0, sizeof(EventSetGranularityInfo_t) ); memset( &ESI->overflow, 0x0, sizeof(EventSetOverflowInfo_t) ); memset( &ESI->multiplex, 0x0, sizeof(EventSetMultiplexInfo_t) ); memset( &ESI->attach, 0x0, sizeof(EventSetAttachInfo_t) ); memset( &ESI->cpu, 0x0, sizeof(EventSetCpuInfo_t) ); memset( &ESI->profile, 0x0, sizeof(EventSetProfileInfo_t) ); memset( &ESI->inherit, 0x0, sizeof(EventSetInheritInfo_t) ); ESI->CpuInfo = NULL; return PAPI_OK; } int _papi_hwi_convert_eventset_to_multiplex( _papi_int_multiplex_t * mpx ) { int retval, i, j = 0, *mpxlist = NULL; EventSetInfo_t *ESI = mpx->ESI; int flags = mpx->flags; /* If there are any events in the EventSet, convert them to multiplex events */ if ( ESI->NumberOfEvents ) { mpxlist = ( int * ) papi_malloc( sizeof ( int ) * ( size_t ) ESI->NumberOfEvents ); if ( mpxlist == NULL ) return ( PAPI_ENOMEM ); /* Build the args to MPX_add_events(). */ /* Remember the EventInfoArray can be sparse and the data can be non-contiguous */ for ( i = 0; i < EventInfoArrayLength( ESI ); i++ ) if ( ESI->EventInfoArray[i].event_code != ( unsigned int ) PAPI_NULL ) mpxlist[j++] = ( int ) ESI->EventInfoArray[i].event_code; /* Resize the EventInfo_t array */ if ( ( _papi_hwd[ESI->CmpIdx]->cmp_info.kernel_multiplex == 0 ) || ( ( _papi_hwd[ESI->CmpIdx]->cmp_info.kernel_multiplex ) && ( flags & PAPI_MULTIPLEX_FORCE_SW ) ) ) { retval = MPX_add_events( &ESI->multiplex.mpx_evset, mpxlist, j, ESI->domain.domain, ESI->granularity.granularity ); if ( retval != PAPI_OK ) { papi_free( mpxlist ); return ( retval ); } } papi_free( mpxlist ); } /* Update the state before initialization! */ ESI->state |= PAPI_MULTIPLEXING; if ( _papi_hwd[ESI->CmpIdx]->cmp_info.kernel_multiplex && ( flags & PAPI_MULTIPLEX_FORCE_SW ) ) ESI->multiplex.flags = PAPI_MULTIPLEX_FORCE_SW; ESI->multiplex.ns = ( int ) mpx->ns; return ( PAPI_OK ); } #include "components_config.h" int papi_num_components = ( sizeof ( _papi_hwd ) / sizeof ( *_papi_hwd ) ) - 1; /* * Routine that initializes all available components. * A component is available if a pointer to its info vector * appears in the NULL terminated_papi_hwd table. */ int _papi_hwi_init_global( void ) { int retval, i = 0; retval = _papi_hwi_innoculate_os_vector( &_papi_os_vector ); if ( retval != PAPI_OK ) { return retval; } while ( _papi_hwd[i] ) { retval = _papi_hwi_innoculate_vector( _papi_hwd[i] ); if ( retval != PAPI_OK ) { return retval; } /* We can be disabled by user before init */ if (!_papi_hwd[i]->cmp_info.disabled) { retval = _papi_hwd[i]->init_component( i ); _papi_hwd[i]->cmp_info.disabled=retval; /* Do some sanity checking */ if (retval==PAPI_OK) { if (_papi_hwd[i]->cmp_info.num_cntrs > _papi_hwd[i]->cmp_info.num_mpx_cntrs) { fprintf(stderr,"Warning! num_cntrs %d is more than num_mpx_cntrs %d for component %s\n", _papi_hwd[i]->cmp_info.num_cntrs, _papi_hwd[i]->cmp_info.num_mpx_cntrs, _papi_hwd[i]->cmp_info.name); } } } i++; } return PAPI_OK; } /* Machine info struct initialization using defaults */ /* See _papi_mdi definition in papi_internal.h */ int _papi_hwi_init_global_internal( void ) { int retval; memset(&_papi_hwi_system_info,0x0,sizeof( _papi_hwi_system_info )); memset( _papi_hwi_using_signal,0x0,sizeof( _papi_hwi_using_signal )); /* Global struct to maintain EventSet mapping */ retval = allocate_eventset_map( &_papi_hwi_system_info.global_eventset_map ); if ( retval != PAPI_OK ) { return retval; } _papi_hwi_system_info.pid = 0; /* Process identifier */ /* PAPI_hw_info_t struct */ memset(&(_papi_hwi_system_info.hw_info),0x0,sizeof(PAPI_hw_info_t)); return PAPI_OK; } void _papi_hwi_shutdown_global_internal( void ) { _papi_hwi_cleanup_all_presets( ); _papi_hwi_cleanup_errors( ); _papi_hwi_lock( INTERNAL_LOCK ); papi_free( _papi_hwi_system_info.global_eventset_map.dataSlotArray ); memset( &_papi_hwi_system_info.global_eventset_map, 0x00, sizeof ( DynamicArray_t ) ); _papi_hwi_unlock( INTERNAL_LOCK ); if ( _papi_hwi_system_info.shlib_info.map ) { papi_free( _papi_hwi_system_info.shlib_info.map ); } memset( &_papi_hwi_system_info, 0x0, sizeof ( _papi_hwi_system_info ) ); } void _papi_hwi_dummy_handler( int EventSet, void *address, long long overflow_vector, void *context ) { /* This function is not used and shouldn't be called. */ ( void ) EventSet; /*unused */ ( void ) address; /*unused */ ( void ) overflow_vector; /*unused */ ( void ) context; /*unused */ return; } static long long handle_derived_add( int *position, long long *from ) { int pos, i; long long retval = 0; i = 0; while ( i < PAPI_EVENTS_IN_DERIVED_EVENT ) { pos = position[i++]; if ( pos == PAPI_NULL ) break; INTDBG( "Compound event, adding %lld to %lld\n", from[pos], retval ); retval += from[pos]; } return ( retval ); } static long long handle_derived_subtract( int *position, long long *from ) { int pos, i; long long retval = from[position[0]]; i = 1; while ( i < PAPI_EVENTS_IN_DERIVED_EVENT ) { pos = position[i++]; if ( pos == PAPI_NULL ) break; INTDBG( "Compound event, subtracting pos=%d %lld from %lld\n", pos, from[pos], retval ); retval -= from[pos]; } return ( retval ); } static long long units_per_second( long long units, long long cycles ) { return ( ( units * (long long) _papi_hwi_system_info.hw_info.cpu_max_mhz * (long long) 1000000 ) / cycles ); } static long long handle_derived_ps( int *position, long long *from ) { return ( units_per_second( from[position[1]], from[position[0]] ) ); } static long long handle_derived_add_ps( int *position, long long *from ) { long long tmp = handle_derived_add( position + 1, from ); return ( units_per_second( tmp, from[position[0]] ) ); } /* this function implement postfix calculation, it reads in a string where I use: | as delimiter N2 indicate No. 2 native event in the derived preset +, -, *, / as operator # as MHZ(million hz) got from _papi_hwi_system_info.hw_info.cpu_max_mhz*1000000.0 Haihang (you@cs.utk.edu) */ static long long _papi_hwi_postfix_calc( EventInfo_t * evi, long long *hw_counter ) { char *point = evi->ops, operand[16]; double stack[PAPI_EVENTS_IN_DERIVED_EVENT]; int i, val, top = 0; INTDBG("ENTER: evi: %p, evi->ops: %p (%s), evi->pos[0]: %d, evi->pos[1]: %d, hw_counter: %p (%lld %lld)\n", evi, evi->ops, evi->ops, evi->pos[0], evi->pos[1], hw_counter, hw_counter[0], hw_counter[1]); memset(&stack,0,PAPI_EVENTS_IN_DERIVED_EVENT*sizeof(double)); while ( *point != '\0' ) { if ( *point == '|' ) { /* consume '|' characters */ point++; } else if ( *point == 'N' ) { /* to get count for each native event */ point++; i = 0; while ( isdigit(*point) ) { assert(i<16); operand[i] = *point; point++; i++; } assert(0pos[val]]; top++; } else if ( *point == '#' ) { /* to get mhz */ point++; assert( top < PAPI_EVENTS_IN_DERIVED_EVENT ); stack[top] = _papi_hwi_system_info.hw_info.cpu_max_mhz * 1000000.0; top++; } else if ( isdigit( *point ) ) { i = 0; while ( isdigit(*point) ) { assert(i<16); operand[i] = *point; point++; i++; } assert(0= 2); stack[top - 2] += stack[top - 1]; top--; } else if ( *point == '-' ) { /* - calculation */ point++; assert(top >= 2); stack[top - 2] -= stack[top - 1]; top--; } else if ( *point == '*' ) { /* * calculation */ point++; assert(top >= 2); stack[top - 2] *= stack[top - 1]; top--; } else if ( *point == '/' ) { /* / calculation */ point++; assert(top >= 2); /* FIXME should handle runtime divide by zero */ stack[top - 2] /= stack[top - 1]; top--; } else { /* flag an error parsing the preset */ PAPIERROR( "BUG! Unable to parse \"%s\"", evi->ops ); return ( long long ) stack[0]; } } assert(top == 1); INTDBG("EXIT: stack[0]: %lld\n", (long long)stack[0]); return ( long long ) stack[0]; } static long long handle_derived( EventInfo_t * evi, long long *from ) { INTDBG("ENTER: evi: %p, evi->derived: %d, from: %p\n", evi, evi->derived, from); switch ( evi->derived ) { case DERIVED_ADD: return ( handle_derived_add( evi->pos, from ) ); case DERIVED_ADD_PS: return ( handle_derived_add_ps( evi->pos, from ) ); case DERIVED_SUB: return ( handle_derived_subtract( evi->pos, from ) ); case DERIVED_PS: return ( handle_derived_ps( evi->pos, from ) ); case DERIVED_POSTFIX: return ( _papi_hwi_postfix_calc( evi, from ) ); case DERIVED_CMPD: /* This type has existed for a long time, but was never implemented. Probably because its a no-op. However, if it's in a header, it should be supported. As I found out when I implemented it in Pentium 4 for testing...dkt */ return ( from[evi->pos[0]] ); default: PAPIERROR( "BUG! Unknown derived command %d, returning 0", evi->derived ); INTDBG("EXIT: Unknown derived command %d\n", evi->derived); return ( ( long long ) 0 ); } } /* table matching derived types to derived strings. used by get_info, encode_event, xml translator */ static const hwi_describe_t _papi_hwi_derived[] = { {NOT_DERIVED, "NOT_DERIVED", "Do nothing"}, {DERIVED_ADD, "DERIVED_ADD", "Add counters"}, {DERIVED_PS, "DERIVED_PS", "Divide by the cycle counter and convert to seconds"}, {DERIVED_ADD_PS, "DERIVED_ADD_PS", "Add 2 counters then divide by the cycle counter and xl8 to secs."}, {DERIVED_CMPD, "DERIVED_CMPD", "Event lives in first counter but takes 2 or more codes"}, {DERIVED_SUB, "DERIVED_SUB", "Sub all counters from first counter"}, {DERIVED_POSTFIX, "DERIVED_POSTFIX", "Process counters based on specified postfix string"}, {DERIVED_INFIX, "DERIVED_INFIX", "Process counters based on specified infix string"}, {-1, NULL, NULL} }; /* _papi_hwi_derived_type: Helper routine to extract a derived type from a derived string returns type value if found, otherwise returns -1 */ int _papi_hwi_derived_type( char *tmp, int *code ) { int i = 0; while ( _papi_hwi_derived[i].name != NULL ) { if ( strcasecmp( tmp, _papi_hwi_derived[i].name ) == 0 ) { *code = _papi_hwi_derived[i].value; return PAPI_OK; } i++; } INTDBG( "Invalid derived string %s\n", tmp ); return PAPI_EINVAL; } /* _papi_hwi_derived_string: Helper routine to extract a derived string from a derived type copies derived type string into derived if found, otherwise returns PAPI_EINVAL */ static int _papi_hwi_derived_string( int type, char *derived, int len ) { int j; for ( j = 0; _papi_hwi_derived[j].value != -1; j++ ) { if ( _papi_hwi_derived[j].value == type ) { strncpy( derived, _papi_hwi_derived[j].name, ( size_t )\ len ); return PAPI_OK; } } INTDBG( "Invalid derived type %d\n", type ); return PAPI_EINVAL; } /* _papi_hwi_get_preset_event_info: Assumes EventCode contains a valid preset code. But defensive programming says check for NULL pointers. Returns a filled in PAPI_event_info_t structure containing descriptive strings and values for the specified preset event. */ int _papi_hwi_get_preset_event_info( int EventCode, PAPI_event_info_t * info ) { INTDBG("ENTER: EventCode: %#x, info: %p\n", EventCode, info); int i = EventCode & PAPI_PRESET_AND_MASK; unsigned int j; if ( _papi_hwi_presets[i].symbol ) { /* if the event is in the preset table */ // since we are setting the whole structure to zero the strncpy calls below will // be leaving NULL terminates strings as long as they copy 1 less byte than the // buffer size of the field. memset( info, 0, sizeof ( PAPI_event_info_t ) ); info->event_code = ( unsigned int ) EventCode; strncpy( info->symbol, _papi_hwi_presets[i].symbol, sizeof(info->symbol)-1); if ( _papi_hwi_presets[i].short_descr != NULL ) strncpy( info->short_descr, _papi_hwi_presets[i].short_descr, sizeof ( info->short_descr )-1 ); if ( _papi_hwi_presets[i].long_descr != NULL ) strncpy( info->long_descr, _papi_hwi_presets[i].long_descr, sizeof ( info->long_descr )-1 ); info->event_type = _papi_hwi_presets[i].event_type; info->count = _papi_hwi_presets[i].count; _papi_hwi_derived_string( _papi_hwi_presets[i].derived_int, info->derived, sizeof ( info->derived ) ); if ( _papi_hwi_presets[i].postfix != NULL ) strncpy( info->postfix, _papi_hwi_presets[i].postfix, sizeof ( info->postfix )-1 ); for(j=0;j < info->count; j++) { info->code[j]=_papi_hwi_presets[i].code[j]; strncpy(info->name[j], _papi_hwi_presets[i].name[j], sizeof(info->name[j])-1); } if ( _papi_hwi_presets[i].note != NULL ) { strncpy( info->note, _papi_hwi_presets[i].note, sizeof ( info->note )-1 ); } return PAPI_OK; } else { return PAPI_ENOEVNT; } } /* _papi_hwi_get_user_event_info: Assumes EventCode contains a valid user event code. But defensive programming says check for NULL pointers. Returns a filled in PAPI_event_info_t structure containing descriptive strings and values for the specified preset event. */ int _papi_hwi_get_user_event_info( int EventCode, PAPI_event_info_t * info ) { INTDBG("ENTER: EventCode: %#x, info: %p\n", EventCode, info); unsigned int i = EventCode & PAPI_UE_AND_MASK; unsigned int j; // if event code not in valid range, return error if (i >= PAPI_MAX_USER_EVENTS) { INTDBG("EXIT: Invalid event index: %d, max value is: %d\n", i, PAPI_MAX_USER_EVENTS - 1); return( PAPI_ENOEVNT ); } if ( user_defined_events[i].symbol == NULL) { /* if the event is in the preset table */ INTDBG("EXIT: Event symbol for this event is NULL\n"); return PAPI_ENOEVNT; } /* set whole structure to 0 */ memset( info, 0, sizeof ( PAPI_event_info_t ) ); info->event_code = ( unsigned int ) EventCode; strncpy( info->symbol, user_defined_events[i].symbol, sizeof(info->symbol)-1); if ( user_defined_events[i].short_descr != NULL ) strncpy( info->short_descr, user_defined_events[i].short_descr, sizeof(info->short_descr)-1); if ( user_defined_events[i].long_descr != NULL ) strncpy( info->long_descr, user_defined_events[i].long_descr, sizeof(info->long_descr)-1); // info->event_type = user_defined_events[i].event_type; info->count = user_defined_events[i].count; _papi_hwi_derived_string( user_defined_events[i].derived_int, info->derived, sizeof(info->derived)-1); if ( user_defined_events[i].postfix != NULL ) strncpy( info->postfix, user_defined_events[i].postfix, sizeof(info->postfix)-1); for(j=0;j < info->count; j++) { info->code[j]=user_defined_events[i].code[j]; INTDBG("info->code[%d]: %#x\n", j, info->code[j]); strncpy(info->name[j], user_defined_events[i].name[j], sizeof(info->name[j])-1); } if ( user_defined_events[i].note != NULL ) { strncpy( info->note, user_defined_events[i].note, sizeof(info->note)-1); } INTDBG("EXIT: PAPI_OK: event_code: %#x, symbol: %s, short_desc: %s, long_desc: %s\n", info->event_code, info->symbol, info->short_descr, info->long_descr); return PAPI_OK; } /* Returns PAPI_OK if native EventCode found, or PAPI_ENOEVNT if not; Used to enumerate the entire array, e.g. for native_avail.c */ int _papi_hwi_query_native_event( unsigned int EventCode ) { INTDBG("ENTER: EventCode: %#x\n", EventCode); char name[PAPI_HUGE_STR_LEN]; /* probably overkill, */ /* but should always be big enough */ int cidx; int nevt_code; cidx = _papi_hwi_component_index( EventCode ); if (cidx<0) { INTDBG("EXIT: PAPI_ENOCMP\n"); return PAPI_ENOCMP; } // save event code so components can get it with call to: _papi_hwi_get_papi_event_code() _papi_hwi_set_papi_event_code(EventCode, 0); if ((nevt_code = _papi_hwi_eventcode_to_native(EventCode)) < 0) { INTDBG("EXIT: nevt_code: %d\n", nevt_code); return nevt_code; } int ret = _papi_hwd[cidx]->ntv_code_to_name( (unsigned int)nevt_code, name, sizeof(name)); INTDBG("EXIT: ret: %d\n", ret); return (ret); } /* Converts an ASCII name into a native event code usable by other routines Returns code = 0 and PAPI_OK if name not found. This allows for sparse native event arrays */ int _papi_hwi_native_name_to_code( char *in, int *out ) { INTDBG("ENTER: in: %s, out: %p\n", in, out); int retval = PAPI_ENOEVNT; char name[PAPI_HUGE_STR_LEN]; /* make sure it's big enough */ unsigned int i; int cidx; char *full_event_name; if (in == NULL) { INTDBG("EXIT: PAPI_EINVAL\n"); return PAPI_EINVAL; } full_event_name = strdup(in); in = _papi_hwi_strip_component_prefix(in); // look in each component for(cidx=0; cidx < papi_num_components; cidx++) { if (_papi_hwd[cidx]->cmp_info.disabled) continue; // if this component does not support the pmu which defines this event, no need to call it if (is_supported_by_component(cidx, full_event_name) == 0) continue; INTDBG("cidx: %d, name: %s, event: %s\n", cidx, _papi_hwd[cidx]->cmp_info.name, in); // show that we do not have an event code yet (the component may create one and update this info) // this also clears any values left over from a previous call _papi_hwi_set_papi_event_code(-1, -1); // if component has a ntv_name_to_code function, use it to get event code if (_papi_hwd[cidx]->ntv_name_to_code != NULL) { // try and get this events event code retval = _papi_hwd[cidx]->ntv_name_to_code( in, ( unsigned * ) out ); if (retval==PAPI_OK) { *out = _papi_hwi_native_to_eventcode(cidx, *out, -1, in); free (full_event_name); INTDBG("EXIT: PAPI_OK event: %s code: %#x\n", in, *out); return PAPI_OK; } } else { // force the code through the work around retval = PAPI_ECMP; } /* If not implemented, work around */ if ( retval==PAPI_ECMP) { i = 0; retval = _papi_hwd[cidx]->ntv_enum_events( &i, PAPI_ENUM_FIRST ); if (retval != PAPI_OK) { free (full_event_name); INTDBG("EXIT: retval: %d\n", retval); return retval; } // _papi_hwi_lock( INTERNAL_LOCK ); do { // save event code so components can get it with call to: _papi_hwi_get_papi_event_code() _papi_hwi_set_papi_event_code(i, 0); retval = _papi_hwd[cidx]->ntv_code_to_name(i, name, sizeof(name)); /* printf("%#x\nname =|%s|\ninput=|%s|\n", i, name, in); */ if ( retval == PAPI_OK && in != NULL) { if ( strcasecmp( name, in ) == 0 ) { *out = _papi_hwi_native_to_eventcode(cidx, i, -1, name); free (full_event_name); INTDBG("EXIT: PAPI_OK, event: %s, code: %#x\n", in, *out); return PAPI_OK; } retval = PAPI_ENOEVNT; } else { *out = 0; retval = PAPI_ENOEVNT; break; } } while ( ( _papi_hwd[cidx]->ntv_enum_events( &i, PAPI_ENUM_EVENTS ) == PAPI_OK ) ); // _papi_hwi_unlock( INTERNAL_LOCK ); } } free (full_event_name); INTDBG("EXIT: retval: %d\n", retval); return retval; } /* Returns event name based on native event code. Returns NULL if name not found */ int _papi_hwi_native_code_to_name( unsigned int EventCode, char *hwi_name, int len ) { INTDBG("ENTER: EventCode: %#x, hwi_name: %p, len: %d\n", EventCode, hwi_name, len); int cidx; int retval; int nevt_code; cidx = _papi_hwi_component_index( EventCode ); if (cidx<0) return PAPI_ENOEVNT; if ( EventCode & PAPI_NATIVE_MASK ) { // save event code so components can get it with call to: _papi_hwi_get_papi_event_code() _papi_hwi_set_papi_event_code(EventCode, 0); if ((nevt_code = _papi_hwi_eventcode_to_native(EventCode)) < 0) { INTDBG("EXIT: nevt_code: %d\n", nevt_code); return nevt_code; } if ( (retval = _papi_hwd[cidx]->ntv_code_to_name( (unsigned int)nevt_code, hwi_name, len) ) == PAPI_OK ) { retval = _papi_hwi_prefix_component_name( _papi_hwd[cidx]->cmp_info.short_name, hwi_name, hwi_name, len); INTDBG("EXIT: retval: %d\n", retval); return retval; } INTDBG("EXIT: retval: %d\n", retval); return (retval); } INTDBG("EXIT: PAPI_ENOEVNT\n"); return PAPI_ENOEVNT; } /* The native event equivalent of PAPI_get_event_info */ int _papi_hwi_get_native_event_info( unsigned int EventCode, PAPI_event_info_t *info ) { INTDBG("ENTER: EventCode: %#x, info: %p\n", EventCode, info); int retval; int cidx; int nevt_code; cidx = _papi_hwi_component_index( EventCode ); if (cidx<0) return PAPI_ENOCMP; if (_papi_hwd[cidx]->cmp_info.disabled) return PAPI_ENOCMP; if ( EventCode & PAPI_NATIVE_MASK ) { // save event code so components can get it with call to: _papi_hwi_get_papi_event_code() _papi_hwi_set_papi_event_code(EventCode, 0); /* clear the event info */ memset( info, 0, sizeof ( PAPI_event_info_t ) ); info->event_code = ( unsigned int ) EventCode; info->component_index = (unsigned int) cidx; retval = _papi_hwd[cidx]->ntv_code_to_info( _papi_hwi_eventcode_to_native(EventCode), info); /* If component error, it's missing the ntv_code_to_info vector */ /* so we'll have to fake it. */ if ( retval == PAPI_ECMP ) { INTDBG("missing NTV_CODE_TO_INFO, faking\n"); /* Fill in the info structure */ if ((nevt_code = _papi_hwi_eventcode_to_native(EventCode)) < 0) { INTDBG("EXIT: nevt_code: %d\n", nevt_code); return nevt_code; } if ( (retval = _papi_hwd[cidx]->ntv_code_to_name( (unsigned int)nevt_code, info->symbol, sizeof(info->symbol)) ) == PAPI_OK ) { } else { INTDBG("EXIT: retval: %d\n", retval); return retval; } if ((nevt_code = _papi_hwi_eventcode_to_native(EventCode)) <0) { INTDBG("EXIT: nevt_code: %d\n", nevt_code); return nevt_code; } retval = _papi_hwd[cidx]->ntv_code_to_descr( (unsigned int)nevt_code, info->long_descr, sizeof ( info->long_descr)); if (retval!=PAPI_OK) { INTDBG("Failed ntv_code_to_descr()\n"); } } retval = _papi_hwi_prefix_component_name( _papi_hwd[cidx]->cmp_info.short_name, info->symbol, info->symbol, sizeof(info->symbol) ); INTDBG("EXIT: retval: %d\n", retval); return retval; } INTDBG("EXIT: PAPI_ENOEVNT\n"); return PAPI_ENOEVNT; } EventSetInfo_t * _papi_hwi_lookup_EventSet( int eventset ) { const DynamicArray_t *map = &_papi_hwi_system_info.global_eventset_map; EventSetInfo_t *set; if ( ( eventset < 0 ) || ( eventset > map->totalSlots ) ) return ( NULL ); set = map->dataSlotArray[eventset]; #ifdef DEBUG if ( ( ISLEVEL( DEBUG_THREADS ) ) && ( _papi_hwi_thread_id_fn ) && ( set->master->tid != _papi_hwi_thread_id_fn( ) ) ) return ( NULL ); #endif return ( set ); } int _papi_hwi_is_sw_multiplex(EventSetInfo_t *ESI) { /* Are we multiplexing at all */ if ( ( ESI->state & PAPI_MULTIPLEXING ) == 0 ) { return 0; } /* Does the component support kernel multiplexing */ if ( _papi_hwd[ESI->CmpIdx]->cmp_info.kernel_multiplex ) { /* Have we forced software multiplexing */ if ( ESI->multiplex.flags == PAPI_MULTIPLEX_FORCE_SW ) { return 1; } /* Nope, using hardware multiplexing */ return 0; } /* We are multiplexing but the component does not support hardware */ return 1; } hwd_context_t * _papi_hwi_get_context( EventSetInfo_t * ESI, int *is_dirty ) { INTDBG("Entry: ESI: %p, is_dirty: %p\n", ESI, is_dirty); int dirty_ctx; hwd_context_t *ctx=NULL; /* assume for now the control state is clean (last updated by this ESI) */ dirty_ctx = 0; /* get a context pointer based on if we are counting for a thread or for a cpu */ if (ESI->state & PAPI_CPU_ATTACHED) { /* use cpu context */ ctx = ESI->CpuInfo->context[ESI->CmpIdx]; /* if the user wants to know if the control state was last set by the same event set, tell him */ if (is_dirty != NULL) { if (ESI->CpuInfo->from_esi != ESI) { dirty_ctx = 1; } *is_dirty = dirty_ctx; } ESI->CpuInfo->from_esi = ESI; } else { /* use thread context */ ctx = ESI->master->context[ESI->CmpIdx]; /* if the user wants to know if the control state was last set by the same event set, tell him */ if (is_dirty != NULL) { if (ESI->master->from_esi != ESI) { dirty_ctx = 1; } *is_dirty = dirty_ctx; } ESI->master->from_esi = ESI; } return( ctx ); } papi-5.5.1/src/libpfm-3.y/0000755000307100002310000000000013013651451015123 5ustar yarkhangraduatepapi-5.5.1/src/libpfm-3.y/docs/0000755000307100002310000000000013013651447016060 5ustar yarkhangraduatepapi-5.5.1/src/libpfm-3.y/docs/Makefile0000644000307100002310000000610013013651447017515 0ustar yarkhangraduate# # Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. # Contributed by Stephane Eranian # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies # of the Software, and to permit persons to whom the Software is furnished to do so, # subject to the following conditions: # # The above copyright notice and this permission notice shall be included in all # copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, # INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A # PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT # HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE # OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # TOPDIR := $(shell if [ "$$PWD" != "" ]; then echo $$PWD; else pwd; fi)/.. include $(TOPDIR)/config.mk include $(TOPDIR)/rules.mk ifeq ($(CONFIG_PFMLIB_ARCH_IA64),y) ARCH_MAN=libpfm_itanium.3 libpfm_itanium2.3 libpfm_montecito.3 endif ifeq ($(CONFIG_PFMLIB_ARCH_I386),y) ARCH_MAN=libpfm_p6.3 libpfm_core.3 libpfm_amd64.3 libpfm_atom.3 libpfm_nehalem.3 endif ifeq ($(CONFIG_PFMLIB_ARCH_X86_64),y) ARCH_MAN=libpfm_amd64.3 libpfm_core.3 libpfm_atom.3 libpfm_nehalem.3 endif ifeq ($(CONFIG_PFMLIB_ARCH_MIPS64),y) endif ifeq ($(CONFIG_PFMLIB_ARCH_POWERPC),y) ARCH_MAN=libpfm_powerpc.3 endif ifeq ($(CONFIG_PFMLIB_ARCH_CRAYXT),y) endif ifeq ($(CONFIG_PFMLIB_CELL),y) endif GEN_MAN= libpfm.3 pfm_dispatch_events.3 pfm_find_event.3 pfm_find_event_bycode.3 \ pfm_find_event_bycode_next.3 pfm_find_event_mask.3 pfm_find_full_event.3 \ pfm_force_pmu.3 pfm_get_cycle_event.3 pfm_get_event_code.3 pfm_get_event_code_counter.3 \ pfm_get_event_counters.3 pfm_get_event_description.3 pfm_get_event_mask_code.3 \ pfm_get_event_mask_description.3 pfm_get_event_mask_name.3 pfm_get_event_name.3 \ pfm_get_full_event_name.3 pfm_get_hw_counter_width.3 pfm_get_impl_counters.3 \ pfm_get_impl_pmcs.3 pfm_get_impl_pmds.3 pfm_get_inst_retired.3 pfm_get_max_event_name_len.3 \ pfm_get_num_counters.3 pfm_get_num_events.3 pfm_get_num_pmcs.3 \ pfm_get_num_pmds.3 pfm_get_pmu_name.3 pfm_get_pmu_name_bytype.3 \ pfm_get_pmu_type.3 pfm_get_version.3 pfm_initialize.3 \ pfm_list_supported_pmus.3 pfm_pmu_is_supported.3 pfm_regmask_and.3 \ pfm_regmask_clr.3 pfm_regmask_copy.3 pfm_regmask_eq.3 pfm_regmask_isset.3 \ pfm_regmask_or.3 pfm_regmask_set.3 pfm_regmask_weight.3 pfm_set_options.3 \ pfm_strerror.3 MAN=$(GEN_MAN) $(ARCH_MAN) install: -mkdir -p $(DESTDIR)$(MANDIR)/man3 ( cd man3; $(INSTALL) -m 644 $(MAN) $(DESTDIR)$(MANDIR)/man3 ) papi-5.5.1/src/libpfm-3.y/docs/man3/0000755000307100002310000000000013013651447016716 5ustar yarkhangraduatepapi-5.5.1/src/libpfm-3.y/docs/man3/pfm_get_num_counters.30000644000307100002310000000003513013651447023222 0ustar yarkhangraduate.so man3/pfm_get_impl_pmcs.3 papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_find_event_bycode.30000644000307100002310000000003213013651447023305 0ustar yarkhangraduate.so man3/pfm_find_event.3 papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_get_version.30000644000307100002310000000202213013651447022164 0ustar yarkhangraduate.TH LIBPFM 3 "November, 2003" "" "Linux Programmer's Manual" .SH NAME pfm_get_version \- get performance monitoring library version .SH SYNOPSIS .nf .B #include .sp .BI "int pfm_get_version(unsigned int *"version); .sp .SH DESCRIPTION This function can be called at any time to get the revision level of the library. The version is encoded into an unsigned integer and returned in the \fBversion\fR argument. A revision number is composed of two fields: a major number and a minor number. Both can be extracted from the returned argument using macros provided in the header file: .TP .B PFMLIB_MAJ_VERSION(v) returns the major number encoded in v. .TP .B PFMLIB_MIN_VERSION(v) returns the minor number encoded in v. .SH RETURN The function returns whether or not it was successful. A return value of \fBPFMLIB_SUCCESS\fR indicates success, otherwise the value is the error code. .SH ERRORS .TP .B PFMLIB_ERR_INVAL the argument is invalid, most likely a NULL pointer. .SH AUTHOR Stephane Eranian .PP papi-5.5.1/src/libpfm-3.y/docs/man3/libpfm_itanium.30000644000307100002310000004616413013651447022014 0ustar yarkhangraduate.TH LIBPFM 3 "November, 2003" "" "Linux Programmer's Manual" .SH NAME libpfm_itanium - support for Itanium specific PMU features .SH SYNOPSIS .nf .B #include .B #include .sp .BI "int pfm_ita_is_ear(unsigned int " i ");" .BI "int pfm_ita_is_dear(unsigned int " i ");" .BI "int pfm_ita_is_dear_tlb(unsigned int " i ");" .BI "int pfm_ita_is_dear_cache(unsigned int " i ");" .BI "int pfm_ita_is_iear(unsigned int " i ");" .BI "int pfm_ita_is_iear_tlb(unsigned int " i ");" .BI "int pfm_ita_is_iear_cache(unsigned int " i ");" .BI "int pfm_ita_is_btb(unsigned int " i ");" .BI "int pfm_ita_support_opcm(unsigned int " i ");" .BI "int pfm_ita_support_iarr(unsigned int " i ");" .BI "int pfm_ita_support_darr(unsigned int " i ");" .BI "int pfm_ita_get_event_maxincr(unsigned int " i ", unsigned int *"maxincr ");" .BI "int pfm_ita_get_event_umask(unsigned int " i ", unsigned long *"umask ");" .sp .SH DESCRIPTION The libpfm library provides full support for all the Itanium specific features of the PMU. The interface is defined in \fBpfmlib_itanium.h\fR. It consists of a set of functions and structures which describe and allow access to the Itanium specific PMU features. .sp The Itanium specific functions presented here are mostly used to retrieve the characteristics of an event. Given a opaque event descriptor, obtained by the \fBpfm_find_event()\fR or its derivative functions, they return a boolean value indicating whether this event support this features or is of a particular kind. .sp The \fBpfm_ita_is_ear()\fR function returns 1 if the event designated by \fBi\fR corresponds to a EAR event, i.e., an Event Address Register type of events. Otherwise 0 is returned. For instance, \fBDATA_EAR_CACHE_LAT4\fR is an ear event, but \fBCPU_CYCLES\fR is not. It can be a data or instruction EAR event. .sp The \fBpfm_ita_is_dear()\fR function returns 1 if the event designated by \fBi\fR corresponds to an Data EAR event. Otherwise 0 is returned. It can be a cache or TLB EAR event. .sp The \fBpfm_ita_is_dear_tlb()\fR function returns 1 if the event designated by \fBi\fR corresponds to a Data EAR TLB event. Otherwise 0 is returned. .sp The \fBpfm_ita_is_dear_cache()\fR function returns 1 if the event designated by \fBi\fR corresponds to a Data EAR cache event. Otherwise 0 is returned. .sp The \fBpfm_ita_is_iear()\fR function returns 1 if the event designated by \fBi\fR corresponds to an instruction EAR event. Otherwise 0 is returned. It can be a cache or TLB instruction EAR event. .sp The \fBpfm_ita_is_iear_tlb()\fR function returns 1 if the event designated by \fBi\fR corresponds to an instruction EAR TLB event. Otherwise 0 is returned. .sp The \fBpfm_ita_is_iear_cache()\fR function returns 1 if the event designated by \fBi\fR corresponds to an instruction EAR cache event. Otherwise 0 is returned. .sp The \fBpfm_ita_support_opcm()\fR function returns 1 if the event designated by \fBi\fR supports opcode matching, i.e., can this event be measured accurately when opcode matching via PMC8/PMC9 is active. Not all events supports this feature. .sp The \fBpfm_ita_support_iarr()\fR function returns 1 if the event designated by \fBi\fR supports code address range restrictions, i.e., can this event be measured accurately when code range restriction is active. Otherwise 0 is returned. Not all events supports this feature. .sp The \fBpfm_ita_support_darr()\fR function returns 1 if the event designated by \fBi\fR supports data address range restrictions, i.e., can this event be measured accurately when data range restriction is active. Otherwise 0 is returned. Not all events supports this feature. .sp The \fBpfm_ita_get_event_maxincr()\fR function returns in \fBmaxincr\fR the maximum number of occurrences per cycle for the event designated by \fBi\fR. Certain Itanium events can occur more than once per cycle. When an event occurs more than once per cycle, the PMD counter will be incremented accordingly. It is possible to restrict measurement when event occur more than once per cycle. For instance, \fBNOPS_RETIRED\fR can happen up to 6 times/cycle which means that the threshold can be adjusted between 0 and 5, where 5 would mean that the PMD counter would be incremented by 1 only when the nop instruction is executed more than 5 times/cycle. This function returns the maximum number of occurrences of the event per cycle, and is the non-inclusive upper bound for the threshold to program in the PMC register. .sp The \fBpfm_ita_get_event_umask()\fR function returns in \fBumask\fR the umask for the event designated by \fBi\fR. .sp When the Itanium specific features are needed to support a measurement their descriptions must be passed as model-specific input arguments to the \fBpfm_dispatch_events()\fR function. The Itanium specific input arguments are described in the \fBpfmlib_ita_input_param_t\fR structure and the output parameters in \fBpfmlib_ita_output_param_t\fR. They are defined as follows: .sp .nf typedef enum { PFMLIB_ITA_ISM_BOTH=0, PFMLIB_ITA_ISM_IA32=1, PFMLIB_ITA_ISM_IA64=2 } pfmlib_ita_ism_t; typedef struct { unsigned int flags; unsigned int thres; pfmlib_ita_ism_t ism; } pfmlib_ita_counter_t; typedef struct { unsigned char opcm_used; unsigned long pmc_val; } pfmlib_ita_opcm_t; typedef struct { unsigned char btb_used; unsigned char btb_tar; unsigned char btb_tac; unsigned char btb_bac; unsigned char btb_tm; unsigned char btb_ptm; unsigned char btb_ppm; unsigned int btb_plm; } pfmlib_ita_btb_t; typedef enum { PFMLIB_ITA_EAR_CACHE_MODE= 0, PFMLIB_ITA_EAR_TLB_MODE = 1, } pfmlib_ita_ear_mode_t; typedef struct { unsigned char ear_used; pfmlib_ita_ear_mode_t ear_mode; pfmlib_ita_ism_t ear_ism; unsigned int ear_plm; unsigned long ear_umask; } pfmlib_ita_ear_t; typedef struct { unsigned int rr_plm; unsigned long rr_start; unsigned long rr_end; } pfmlib_ita_input_rr_desc_t; typedef struct { unsigned long rr_soff; unsigned long rr_eoff; } pfmlib_ita_output_rr_desc_t; typedef struct { unsigned int rr_flags; pfmlib_ita_input_rr_desc_t rr_limits[4]; unsigned char rr_used; } pfmlib_ita_input_rr_t; typedef struct { unsigned int rr_nbr_used; pfmlib_ita_output_rr_desc_t rr_infos[4]; pfmlib_reg_t rr_br[8]; } pfmlib_ita_output_rr_t; typedef struct { pfmlib_ita_counter_t pfp_ita_counters[PMU_ITA_NUM_COUNTERS]; unsigned long pfp_ita_flags; pfmlib_ita_opcm_t pfp_ita_pmc8; pfmlib_ita_opcm_t pfp_ita_pmc9; pfmlib_ita_ear_t pfp_ita_iear; pfmlib_ita_ear_t pfp_ita_dear; pfmlib_ita_btb_t pfp_ita_btb; pfmlib_ita_input_rr_t pfp_ita_drange; pfmlib_ita_input_rr_t pfp_ita_irange; } pfmlib_ita_input_param_t; typedef struct { pfmlib_ita_output_rr_t pfp_ita_drange; pfmlib_ita_output_rr_t pfp_ita_irange; } pfmlib_ita_output_param_t; .fi .sp .SH INSTRUCTION SET .sp The Itanium processor provides two additional per-event features for counters: thresholding and instruction set selection. They can be set using the \fBpfp_ita_counters\fR data structure for each event. The \fBism\fR field can be initialized as follows: .TP .B PFMLIB_ITA_ISM_BOTH The event will be monitored during IA-64 and IA-32 execution .TP .B PFMLIB_ITA_ISM_IA32 The event will only be monitored during IA-32 execution .TP .B PFMLIB_ITA_ISM_IA64 The event will only be monitored during IA-64 execution .sp .LP If \fBism\fR has a value of zero, it will default to PFMLIB_ITA_ISM_BOTH. .sp The \fBthres\fR indicates the threshold for the event. A threshold of \fBn\fR means that the counter will be incremented by one only when the event occurs more than \fBn\fR times per cycle. The \fBflags\fR field contains event-specific flags. The currently defined flags are: .sp .TP PFMLIB_ITA_FL_EVT_NO_QUALCHECK When this flag is set it indicates that the library should ignore the qualifiers constraints for this event. Qualifiers includes opcode matching, code and data range restrictions. When an event is marked as not supporting a particular qualifier, it usually means that it is ignored, i.e., the extra level of filtering is ignored. For instance, the CPU_CYCLES events does not support code range restrictions and by default the library will refuse to program it if range restriction is also requested. Using the flag will override the check and the call to the \fBpfm_dispatch_events()\fR function will succeed. In this case, CPU_CYCLES will be measured for the entire program and not just for the code range requested. For certain measurements this is perfectly acceptable as the range restriction will only be applied relevant to events which support it. Make sure you understand which events do not support certain qualifiers before using this flag. .LP .SH OPCODE MATCHING .sp The \fBpfp_ita_pmc8\fR and \fBpfp_ita_pmc9\fR fields of type \fBpfmlib_ita_opcm_t\fR contain the description of what to do with the opcode matchers. Itanium supports opcode matching via PMC8 and PMC9. When this feature is used the \fBopcm_used\fR field must be set to 1, otherwise it is ignored by the library. The \fBpmc_val\fR simply contains the raw value to store in PMC8 or PMC9. The library does not modify the values for PMC8 and PMC9, they will be stored in the \fBpfp_pmcs\fR table of the generic output parameters. .SH EVENT ADDRESS REGISTERS .sp The \fBpfp_ita_iear\fR field of type \fBpfmlib_ita_ear_t\fR describes what to do with instruction Event Address Registers (I-EARs). Again if this feature is used the \fBear_used\fR must be set to 1, otherwise it will be ignored by the library. The \fBear_mode\fR must be set to either one of \fBPFMLIB_ITA_EAR_TLB_MODE\fR, \fBPFMLIB_ITA_EAR_CACHE_MODE\fRto indicate the type of EAR to program. The umask to store into PMC10 must be in \fBear_umask\fR. The privilege level mask at which the I-EAR will be monitored must be set in \fBear_plm\fR which can be any combination of \fBPFM_PLM0\fR, \fBPFM_PLM1\fR, \fBPFM_PLM2\fR, \fBPFM_PLM3\fR. If \fBear_plm\fR is 0 then the default privilege level mask in \fBpfp_dfl_plm\fR is used. Finally the instruction set for which to monitor is in \fBear_ism\fR and can be any one of \fBPFMLIB_ITA_ISM_BOTH\fR, \fBPFMLIB_ITA_ISM_IA32\fR, or \fBPFMLIB_ITA_ISM_IA64\fR. .sp The \fBpfp_ita_dear\fR field of type \fBpfmlib_ita_ear_t\fR describes what to do with data Event Address Registers (D-EARs). The description is identical to the I-EARs except that it applies to PMC11. In general, there are four different methods to program the EAR (data or instruction): .TP .B Method 1 There is an EAR event in the list of events to monitor and \fBear_used\fR is cleared. In this case the EAR will be programmed (PMC10 or PMC11) based on the information encoded in the event. A counting monitor (PMC4/PMD4-PMC7/PMD7) will be programmed to count DATA_EAR_EVENT or INSTRUCTION_EAR_EVENTS depending on the type of EAR. .TP .B Method 2 There is an EAR event in the list of events to monitor and \fBear_used\fR is set. In this case the EAR will be programmed (PMC10 or PMC11) using the information in the \fBpfp_ita_iear\fR or \fBpfp_ita_dear\fR structure because it contains more detailed information, such as privilege level and instruction set. A counting monitor (PMC4/PMD4-PMC7/PMD7) will be programmed to count DATA_EAR_EVENT or INSTRUCTION_EAR_EVENTS depending on the type of EAR. .TP .B Method 3 There is no EAR event in the list of events to monitor and and \fBear_used\fR is cleared. In this case no EAR is programmed. .TP .B Method 4 There is no EAR event in the list of events to monitor and and \fBear_used\fR is set. In this case case the EAR will be programmed (PMC10 or PMC11) using the information in the \fBpfp_ita_iear\fR or \fBpfp_ita_dear\fR structure. This is the free running mode for the EAR. .sp .SH BRANCH TRACE BUFFER The \fBpfp_ita_btb\fR of type \fBpfmlib_ita_btb_t\fR field is used to configure the Branch Trace Buffer (BTB). If the \fBbtb_used\fR is set, then the library will take the configuration into account, otherwise any BTB configuration will be ignored. The various fields in this structure provide means to filter out the kind of branches that gets recorded in the BTB. Each one represents an element of the branch architecture of the Itanium processor. Refer to the Itanium specific documentation for more details on the branch architecture. The fields are as follows: .TP .B btb_tar If the value of this field is 1, then branches predicted by the Target Address Register (TAR) predictions are captured. If 0 no branch predicted by the TAR is included. .TP .B btb_tac If this field is 1, then branches predicted by the Target Address Cache (TAC) are captured. If 0 no branch predicted by the TAC is included. .TP .B btb_bac If this field is 1, then branches predicted by the Branch Address Corrector (BAC) are captured. If 0 no branch predicted by the BAC is included. .TP .B btb_tm If this field is 0, then no branch is captured. If this field is 1, then non taken branches are captured. If this field is 2, then taken branches are captured. Finally if this field is 3 then all branches are captured. .TP .B btb_ptm If this field is 0, then no branch is captured. If this field is 1, then branches with a mispredicted target address are captured. If this field is 2, then branches with correctly predicted target address are captured. Finally if this field is 3 then all branches are captured regardless of target address prediction. .TP .B btb_ppm If this field is 0, then no branch is captured. If this field is 1, then branches with a mispredicted path (taken/non taken) are captured. If this field is 2, then branches with correctly predicted path are captured. Finally if this field is 3 then all branches are captured regardless of their path prediction. .TP .B btb_plm This is the privilege level mask at which the BTB captures branches. It can be any combination of \fBPFM_PLM0\fR, \fBPFM_PLM1\fR, \fBPFM_PLM2\fR, \fBPFM_PLM3\fR. If \fBbtb_plm\fR is 0 then the default privilege level mask in \fBpfp_dfl_plm\fR is used. .sp There are 4 methods to program the BTB and they are as follows: .sp .TP .B Method 1 The \fBBRANCH_EVENT\fR is in the list of events to monitor and \fBbtb_used\fR is cleared. In this case, the BTB will be configured (PMC12) to record ALL branches. A counting monitor (PMC4/PMD4-PMC7/PMD7) will be programmed to count \fBBRANCH_EVENT\fR. .TP .B Method 2 The \fBBRANCH_EVENT\fR is in the list of events to monitor and \fBbtb_used\fR is set. In this case, the BTB will be configured (PMC12) using the information in the \fBpfp_ita_btb\fR structure. A counting monitor (PMC4/PMD4-PMC7/PMD7) will be programmed to count \fBBRANCH_EVENT\fR. .TP .B Method 3 The \fBBRANCH_EVENT\fR is not in the list of events to monitor and \fBbtb_used\fR is set. In this case, the BTB will be configured (PMC12) using the information in the \fBpfp_ita_btb\fR structure. This is the free running mode for the BTB. .TP .B Method 4 The \fBBRANCH_EVENT\fR is not in the list of events to monitor and \fBbtb_used\fR is cleared. In this case, the BTB is not programmed. .sp .SH DATA AND CODE RANGE RESTRICTIONS The \fBpfp_ita_drange\fR and \fBpfp_ita_irange\fR fields control the range restrictions for the data and code respectively. The idea is that the application passes a set of ranges, each designated by a start and end address. Upon return from the \fBpfm_dispatch_events()\fR function, the application gets back the set of registers and their values that needs to be programmed via a kernel interface. Range restriction is implemented using the debug registers. There is a limited number of debug registers and they go in pair. With 8 data debug registers, a maximum of 4 distinct ranges can be specified. The same applies to code range restrictions. Moreover, there are some severe constraints on the alignment and size of the range. Given that the size range is specified using a bitmask, there can be situations where the actual range is larger than the requested range. The library will make the best effort to cover only what is requested. It will never cover less than what is requested. The algorithm uses more than one pair of debug registers to get a more precise range if necessary. Hence, up to the 4 pairs can be used to describe a single range. The library returns the start and end offsets of the actual range compared to the requested range. If range restriction is to be used, the \fBrr_used\fR field must be set to one, otherwise settings will be ignored. The ranges are described by the \fBpfmlib_ita_input_rr_t\fR structure. Up to 4 ranges can be defined. Each range is described in by a entry in \fBrr_limits\fR. The \fBpfmlib_ita_input_rr_desc_t\fR structure is defined as follows: .TP .B rr_plm The privilege level at which the range is active. It can be any combinations of \fBPFM_PLM0\fR, \fBPFM_PLM1\fR, \fBPFM_PLM2\fR, \fBPFM_PLM3\fR. If \fBrr_plm\fR is 0 then the default privilege level mask in \fBpfp_dfl_plm\fR is used.The privilege level is only relevant for code ranges, data ranges ignores the setting. .TP .B rr_start This is the start address of the range. Any address is supported but for code range it must be bundle aligned, i.e., 16-byte aligned. .TP .B rr_end This is the end address of the range. Any address is supported but for code range it must be bundle aligned, i.e., 16-byte aligned. .LP .sp The library will provide the values for the debug registers as well as some information about the actual ranges in the output parameters and more precisely in the \fBpfmlib_ita_output_rr_t\fR structure for each range. The structure is defined as follows: .TP .B rr_nbr_used Contains the number of debug registers used to cover the range. This is necessarily an even number as debug registers always go in pair. The value of this field is between 0 and 7. .TP .B rr_br This table contains the list of debug registers necessary to cover the ranges. Each element is of type \fBpfmlib_reg_t\fR. The \fBreg_num\fR field contains the debug register index while \fBreg_value\fR contains the debug register value. Both the index and value must be copied into the kernel specific argument to program the debug registers. The library never programs them. .TP .B rr_infos Contains information about the ranges defined. Because of alignment restrictions, the actual range covered by the debug registers may be larger than the requested range. This table describe the differences between the requested and actual ranges expressed as offsets: .TP .B rr_soff Contains the start offset of the actual range described by the debug registers. If zero, it means the library was able to match exactly the beginning of the range. Otherwise it represents the number of byte by which the actual range precedes the requested range. .TP .B rr_eoff Contains the end offset of the actual range described by the debug registers. If zero, it means the library was able to match exactly the end of the range. Otherwise it represents the number of bytes by which the actual range exceeds the requested range. .sp .LP .SH ERRORS Refer to the description of the \fBpfm_dispatch_events()\fR function for errors when using the Itanium specific input and output arguments. .SH SEE ALSO pfm_dispatch_events(3) and set of examples shipped with the library .SH AUTHOR Stephane Eranian .PP papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_get_event_counters.30000644000307100002310000000003613013651447023545 0ustar yarkhangraduate.so man3/pfm_get_event_name.3 papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_get_pmu_type.30000644000307100002310000000003413013651447022342 0ustar yarkhangraduate.so man3/pfm_get_pmu_name.3 papi-5.5.1/src/libpfm-3.y/docs/man3/libpfm_p6.30000644000307100002310000000457513013651447020673 0ustar yarkhangraduate.TH LIBPFM 3 "September, 2005" "" "Linux Programmer's Manual" .SH NAME libpfm_i386_p6 - support for Intel P6 processor family .SH SYNOPSIS .nf .B #include .B #include .sp .SH DESCRIPTION The libpfm library provides full support for the P6 processor family, including the Pentium M processor. The interface is defined in \fBpfmlib_i386_p6.h\fR. It consists of a set of functions and structures which describe and allow access to the P6 processors specific PMU features. .sp When P6 processor specific features are needed to support a measurement, their descriptions must be passed as model-specific input arguments to the \fBpfm_dispatch_events()\fR function. The P6 processors specific input arguments are described in the \fBpfmlib_i386_p6_input_param_t\fR structure and the output parameters in \fBpfmlib_i386_p6_output_param_t\fR. They are defined as follows: .sp .nf typedef struct { unsigned int cnt_mask; unsigned int flags; } pfmlib_i386_p6_counter_t; typedef struct { pfmlib_i386_p6_counter_t pfp_i386_p6_counters[PMU_I386_P6_NUM_COUNTERS]; uint64_t reserved[4]; } pfmlib_i386_p6_input_param_t; typedef struct { uint64_t reserved[8]; } pfmlib_i386_p6_output_param_t; .fi .sp .sp The P6 processor provides a few additional per-event features for counters: thresholding, inversion, edge detection. They can be set using the \fBpfp_i386_p6_counters\fR data structure for each event. The \fBflags\fR field can be initialized as follows: .TP .B PFMLIB_I386_P6_SEL_INV Inverse the results of the \fBcnt_mask\fR comparison when set .TP .B PFMLIB_I386_P6_SEL_EDGE Enables edge detection of events. .LP The \fBcnt_mask\fR field contains is used to set the event threshold. The value of the counter is incremented each time the number of occurrences per cycle of the event is greater or equal to the value of the field. When zero all occurrences are counted. .sp .SH Handling of Pentium M The library provides full support for the Pentium M PMU. A Pentium implements more events than a generic P6 processor. The library autodetects the host processor and can distinguish generic P6 processor from a Pentium. Thus no special call is needed. .sp .SH ERRORS Refer to the description of the \fBpfm_dispatch_events()\fR function for errors. .SH SEE ALSO pfm_dispatch_events(3) and set of examples shipped with the library .SH AUTHOR Stephane Eranian .PP papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_force_pmu.30000644000307100002310000000003413013651447021620 0ustar yarkhangraduate.so man3/pfm_get_pmu_name.3 papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_find_event_bycode_next.30000644000307100002310000000003213013651447024343 0ustar yarkhangraduate.so man3/pfm_find_event.3 papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_get_num_events.30000644000307100002310000000003613013651447022665 0ustar yarkhangraduate.so man3/pfm_get_event_name.3 papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_set_options.30000644000307100002310000000345413013651447022220 0ustar yarkhangraduate.TH LIBPFM 3 "November, 2003" "" "Linux Programmer's Manual" .SH NAME pfm_set_options \- set performance monitoring library debug options .SH SYNOPSIS .nf .B #include .sp .BI "int pfm_set_options(pfmlib_options_t *"opt); .sp .SH DESCRIPTION This function can be called at any time to adjust the level of debug of the library. In both cases, extra output will be generated on standard error when the library gets called. This can be useful to figure out how the PMC registers are initialized for instance. .sp The opt argument to this function is a pointer to a .B pfmlib_options_t structure which is defined as follows: .sp .nf typedef struct { unsigned int pfm_debug:1; unsigned int pfm_verbose:1; } pfmlib_options_t; .fi .sp .sp Setting \fBpfm_debug\fR to 1 will enable debug messages whereas setting \fBpfm_verbose\fR will enable verbose messages. .SH ENVIRONMENT VARIABLES Setting library options with this function has lower priority than with environment variables. As such, the call to this function may not have any actual effects. A user can set the following environment variables to control verbosity and debug output: .TP .B LIBPFM_VERBOSE Enable verbose output. Value must be 0 or 1. When not set, verbosity level can be controlled with this function. .TP .B LIBPFM_DEBUG Enable debug output. Value must be 0 or 1. When not set, debug level can be controlled with this function. .LP .SH RETURN The function returns whether or not it was successful. A return value of \fBPFMLIB_SUCCESS\fR indicates success, otherwise the value is the error code. .sp When environment variables exist, they take precedence and this function returns \fBPFMLIB_SUCCESS\fR. .SH ERRORS .TP .B PFMLIB_ERR_INVAL the argument is invalid, most likely a NULL pointer. .SH AUTHOR Stephane Eranian .PP papi-5.5.1/src/libpfm-3.y/docs/man3/libpfm_westmere.30000644000307100002310000001410213013651447022164 0ustar yarkhangraduate.TH LIBPFM 3 "January, 2009" "" "Linux Programmer's Manual" .SH NAME libpfm_nehalem - support for Intel Nehalem processor family .SH SYNOPSIS .nf .B #include .B #include .sp .SH DESCRIPTION The libpfm library provides full support for the Intel Nehalem processor family, such as Intel Core i7. The interface is defined in \fBpfmlib_intel_nhm.h\fR. It consists of a set of functions and structures describing the Intel Nehalem processor specific PMU features. The Intel Nehalem processor is a quad core, dual thread processor. It includes two types of PMU: core and uncore. The latter measures events at the socket level and is therefore disconnected from any of the four cores. The core PMU implements Intel architectural perfmon version 3 with four generic counters and three fixed counters. The uncore has eight generic counters and one fixed counter. Each Intel Nehalem core also implement a 16-deep branch trace buffer, called Last Branch Record (LBR), which can be used in combination with the core PMU. Intel Nehalem implements a newer version of the Precise Event-Based Sampling (PEBS) mechanism which has the ability to capture where cache misses occur. .sp When Intel Nehalem processor specific features are needed to support a measurement, their descriptions must be passed as model-specific input arguments to the \fBpfm_dispatch_events()\fR function. The Intel Nehalem processors specific input arguments are described in the \fBpfmlib_nhm_input_param_t\fR structure. No output parameters are currently defined. The input parameters are defined as follows: .sp .nf typedef struct { unsigned long cnt_mask; unsigned int flags; } pfmlib_nhm_counter_t; typedef struct { unsigned int lbr_used; unsigned int lbr_plm; unsigned int lbr_filter; } pfmlib_nhm_lbr_t; typedef struct { unsigned int pebs_used; unsigned int ld_lat_thres; } pfmlib_nhm_pebs_t; typedef struct { pfmlib_nhm_counter_t pfp_nhm_counters[PMU_NHM_NUM_COUNTERS]; pfmlib_nhm_pebs_t pfp_nhm_pebs; pfmlib_nhm_lbr_t pfm_nhm_lbr; uint64_t reserved[4]; } pfmlib_nhm_input_param_t; .fi .sp .sp The Intel Nehalem processor provides a few additional per-event features for counters: thresholding, inversion, edge detection, monitoring of both threads, occupancy. They can be set using the \fBpfp_nhm_counters\fR data structure for each event. The \fBflags\fR field can be initialized with the following values, depending on the event: .TP .B PFMLIB_NHM_SEL_INV Inverse the results of the \fBcnt_mask\fR comparison when set. This flag is supported for core and uncore PMU events. .TP .B PFMLIB_NHM_SEL_EDGE Enables edge detection of events. This flag is supported for core and uncore PMU events. .TP .B PFMLIB_NHM_SEL_ANYTHR Enable measuring the event in any of the two processor threads assuming hyper-threading is enabled. By default, only the current thread is measured. This flag is restricted to core PMU events. .TP .B PFMLIB_NHM_SEL_OCC_RST When set, the queue occupancy counter associated with the event is cleared. This flag is only available to uncore PMU events. .LP The \fBcnt_mask\fR field is used to set the event threshold. The value of the counter is incremented for each cycle in which the number of occurrences of the event is greater or equal to the value of the field. Thus, the event is modified to actually measure the number of qualifying cycles. When zero all occurrences are counted (this is the default). This flag is supported for core and uncore PMU events. .sp .SH Support for Precise-Event Based Sampling (PEBS) The library can be used to setup the PMC registers associated with PEBS. In this case, the \fBpfp_nhm_pebs_t\fR structure must be used and the \fBpebs_used\fR field must be set to 1. .sp To enable the PEBS load latency filtering capability, it is necessary to program the \fBMEM_INST_RETIRED:LATENCY_ABOVE_THRESHOLD\fR event into one generic counter. The latency threshold must be passed to the library in the \fBld_lat_thres\fR field. It is expressed in core cycles and \fBmust\fR greater than 3. Note that \fBpebs_used\fR must be set as well. .SH Support for Last Branch Record (LBR) The library can be used to setup LBR registers. On Intel Nehalem processors, the LBR is 16-entry deep and it is possible to filter branches, based on privilege level or type. To configure the LBR, the \fBpfm_nhm_lbr_t\fR structure must be used. .sp Like core PMU counters, LBR only distinguishes two privilege levels, 0 and the rest (1,2,3). When running Linux natively, the kernel is at privilege level 0, applications at level 3. It is possible to specify the privilege level of LBR using the \fBlbr_plm\fR. Any attempt to pass \fBPFM_PLM1\fB or \fBPFM_PLM2\fR will be rejected. If \fB\lbr_plm\fR is 0, then the global value in \fBpfmlib_input_param_t\fR and the \fBpfp_dfl_plm\fR is used. .sp By default, LBR captures all branches. It is possible to filter out branches by passing a set of flags in \fBlbr_select\fR. The flags are as follows: .TP .B PFMLIB_NHM_LBR_JCC When set, LBR does not capture conditional branches. Default: off. .TP .B PFM_NHM_LBR_NEAR_REL_CALL When set, LBR does not capture near calls. Default: off. .TP .B PFM_NHM_LBR_NEAR_IND_CALL When set, LBR does not capture indirect calls. Default: off. .TP .B PFM_NHM_LBR_NEAR_RET When set, LBR does not capture return branches. Default: off. .TP .B PFM_NHM_LBR_NEAR_IND_JMP When set, LBR does not capture indirect branches. Default: off. .TP .B PFM_NHM_LBR_NEAR_REL_JMP When set, LBR does not capture relative branches. Default: off. .TP .B PFM_NHM_LBR_FAR_BRANCH When set, LBR does not capture far branches. Default: off. .SH Support for uncore PMU By nature, the uncore PMU does not distinguish privilege levels, therefore it captures events at all privilege levels. To avoid any misinterpretation, the library enforces that uncore events be measured with both \fBPFM_PLM0\fR and \fBPFM_PLM3\fR set. Tools and operating system kernel interfaces may impose further restrictions on how the uncore PMU can be accessed. .SH SEE ALSO pfm_dispatch_events(3) and set of examples shipped with the library .SH AUTHOR Stephane Eranian .PP papi-5.5.1/src/libpfm-3.y/docs/man3/libpfm_atom.30000644000307100002310000000555213013651447021302 0ustar yarkhangraduate.TH LIBPFM 3 "November, 2006" "" "Linux Programmer's Manual" .SH NAME libpfm_core - support for Intel Atom processor family .SH SYNOPSIS .nf .B #include .B #include .sp .SH DESCRIPTION The libpfm library provides full support for the Intel Atom processor. This processor implements Intel architectural perfmon v3 with Precise Event-Based Sampling (PEBS) support. It also implements all architected events to which it adds lots of Atom specific events. .sp The libpfm interface is defined in \fBpfmlib_intel_atom.h\fR. It consists of a set of functions and structures which describe and allow access to the Intel Atom processor specific PMU features. .sp When Intel Atom processor specific features are needed to support a measurement, their descriptions must be passed as model-specific input arguments to the \fBpfm_dispatch_events()\fR function. The Intel Atom processors specific input arguments are described in the \fBpfmlib_intel_atom_input_param_t\fR structure. No output parameters are currently defined. The input parameters are defined as follows: .sp .nf typedef struct { unsigned int cnt_mask; unsigned int flags; } pfmlib_intel_atom_counter_t; typedef struct { pfmlib_intel_atom_counter_t pfp_intel_atom_counters[PMU_INTEL_ATOM_NUM_COUNTERS]; unsigned int pfp_intel_atom_pebs_used; uint64_t reserved[4]; } pfmlib_core_input_param_t; .fi .sp .sp The Intel Atom processor provides several additional per-event features for counters: thresholding, inversion, edge detection, monitoring both threads. They can be set using the \fBpfp_intel_atom_counters\fR data structure for each event. The \fBflags\fR field can be initialized with any combinations of the following values: .TP .B PFMLIB_INTEL_ATOM_SEL_INV Inverse the results of the \fBcnt_mask\fR comparison when set .TP .B PFMLIB_INTEL_ATOM_SEL_EDGE Enable edge detection of events. .TP .B PFMLIB_INTEL_ATOM_SEL_ANYTHR Enable measuring the event in any of the two threads. By default only the current thread is measured. .LP The \fBcnt_mask\fR field is used to set the event threshold. The value of the counter is incremented each time the number of occurrences per cycle of the event is greater or equal to the value of the field. Thus the event is modified to actually measure the number of qualifying cycles. When zero all occurrences are counted (this is the default). .sp .SH Support for Precise-Event Based Sampling (PEBS) The library can be used to setup the PMC registers when using PEBS. In this case, the \fBpfp_intel_atom_pebs_used\fR field must be set to 1. When using PEBS, it is not possible to use more than one event. .LP .SH ERRORS Refer to the description of the \fBpfm_dispatch_events()\fR function for errors. .SH SEE ALSO pfm_dispatch_events(3) and set of examples shipped with the library .SH AUTHOR Stephane Eranian .PP papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_get_pmu_name.30000644000307100002310000001345313013651447022312 0ustar yarkhangraduate.TH LIBPFM 3 "November, 2003" "" "Linux Programmer's Manual" .SH NAME pfm_get_pmu_name, pfm_get_pmu_type, pfm_get_pmu_name_bytype, pfm_pmu_is_supported, pfm_force_pmu,pfm_list_supported_pmu \- query library about supported PMU models .SH SYNOPSIS .nf .B #include .sp .BI "int pfm_get_pmu_name(char *"name ", int " maxlen); .BI "int pfm_get_pmu_type(int *" type); .BI "int pfm_get_pmu_name_bytype(int " type ", char *" name ", int " maxlen); .BI "int pfm_pmu_is_supported(int " type); .BI "int pfm_force_pmu(int " type); .BI "int pfm_list_supported_pmus(int (*" pf ")(const char *"fmt ",...));" .sp .SH DESCRIPTION These functions retrieve information about the detected host PMU and the PMU models supported by the library. More than one model can be supported by the same library. Each PMU model is assigned a type and a name. The latter is just a string and the former is a unique identifier. The currently supported types are: .TP .B PFMLIB_GENERIC_PMU Intel Itanium default architected PMU model, i.e., the basic model. .TP .B PFMLIB_ITANIUM_PMU Intel Itanium processor PMU model. The model is found in the first implementation of the IA-64 architecture, code name Merced. .TP .B PFMLIB_ITANIUM2_PMU Intel Itanium 2 processor PMU model. This is the model provided by McKinley, Madison, and Deerfield processors. .TP .B PFMLIB_MONTECITO_PMU Intel Dual-core Itanium 2 processor PMU model. This is the model provided by Montecito, Montvale processors. .TP .B PFMLIB_AMD64_PMU AMD AMD64 processors (family 15 and 16) .TP .B PFMLIB_GEN_IA32_PMU Intel X86 architectural PMU v1, v2, v3 .TP .B PFMLIB_I386_P6_PMU Intel P6 processors. That includes Pentium Pro, Pentium II, Pentium III, but excludes Pentium M .TP .B PFMLIB_I386_PM_PMU Intel Pentium M processors. .TP .B PFMLIB_INTEL_PII_PMU Intel Pentium II processors. .TP .B PFMLIB_PENTIUM4_PMU Intel processors based on Netburst micro-architecture. That includes Pentium 4. .TP .B PFMLIB_COREDUO_PMU Intel processors based on Yonah micro-architecture. That includes Intel Core Duo/Core Solo processors .TP .B PFMLIB_I386_PM_PMU Intel Pentium M processors .TP .B PFMLIB_INTEL_CORE_PMU Intel processors based on the Core micro-architecture. That includes Intel Core 2 Duo/Quad processors .TP .B PFMLIB_INTEL_ATOM_PMU Intel processors based on the Atom micro-architecture. .TP .B PFMLIB_INTEL_NHM_PMU Intel processors based on the Nehalem micro-architectures. That includes Intel Core i7 processors. .TP .B PFMLIB_MIPS_20KC_PMU MIPS 20KC processors .TP .B PFMLIB_MIPS_24K_PMU MIPS 24K processors .TP .B PFMLIB_MIPS_25KF_PMU MIPS 25KF processors .TP .B PFMLIB_MIPS_34K_PMU MIPS 34K processors .TP .B PFMLIB_MIPS_5KC_PMU MIPS 5KC processors .TP .B PFMLIB_MIPS_74K_PMU MIPS 74K processors .TP .B PFMLIB_MIPS_R10000_PMU MIPS R10000 processors .TP .B PFMLIB_MIPS_R12000_PMU MIPS R12000 processors .TP .B PFMLIB_MIPS_RM7000_PMU MIPS RM7000 processors .TP .B PFMLIB_MIPS_RM9000_PMU MIPS RM9000 processors .TP .B PFMLIB_MIPS_SB1_PMU MIPS SB1/SB1A processors .TP .B PFMLIB_MIPS_VR5432_PMU MIPS VR5432 processors .TP .B PFMLIB_MIPS_VR5500_PMU MIPS VR5500 processors .TP .B PFMLIB_MIPS_ICE9A_PMU SiCortex ICE9A .TP .B PFMLIB_MIPS_ICE9B_PMU SiCortex ICE9B .TP .B PFMLIB_POWERPC_PMU IBM POWERPC processors .TP .B PFMLIB_CRAYX2_PMU Cray X2 processors .TP .B PFMLIB_CELL_PMU IBM Cell processors .TP .B PFMLIB_PPC970_PMU IBM PowerPC 970(FX,GX) processors .TP .B PFMLIB_PPC970MP_PMU IBM PowerPC 970MP processors .TP .B PFMLIB_POWER3_PMU IBM POWER3 processors .TP .B PFMLIB_POWER4_PMU IBM POWER4 processors .TP .B PFMLIB_POWER5_PMU IBM POWER5 processors .TP .B PFMLIB_POWER5p_PMU BM POWER5+ processors .TP .B PFMLIB_POWER6_PMU IBM POWER6 processors .LP The \fBpfm_get_pmu_name()\fR function returns the name of the detected host PMU. The library must have been initialized properly before making this call. The name is returned in the \fBname\fR argument. The \fBmaxlen\fR argument indicates the maximum length of the buffer provided for \fBname\fR. Up to \fBmaxlen-1\fR characters will be returned, not including the termination character. .sp The \fBpfm_get_pmu_type()\fR function returns the type of the detected host PMU. The library must have been initialized properly before making this call. The type returned in \fBtype\fR can be any one of the three listed above. .sp The \fBpfm_get_pmu_name_bytype()\fR function returns the name of a PMU model in \fBname\fR given a type in the \fBtype\fR argument. The \fBmaxlen\fR argument indicates the maximum length of the buffer provided for \fBname\fR. Up to \fBmaxlen-1\fR characters will be returned, not including the termination character. .sp The \fBpfm_pmu_is_supported()\fR function returns \fBPFMLIB_SUCCESS\fR if the given PMU type is supported by the library independently of what the host PMU model is. .sp The \fBpfm_force_pmu()\fR function is used to forced the library to use a particular PMU model compared to what it has detected. The library checks that the selected type can be supported by the host PMU. This is mostly useful to force the library to the use generic PMU model \fBPFMLIB_GENERIC_PMU\fR. This function can be called at any time and upon return the library is considered initialized. .sp The \fBpfm_list_supported_pmu()\fR function is used to print the list PMU types that the library supports. The results is printed using the function provided in the \fBpf\fR argument, which must be a printf-style function. .SH RETURN The function returns whether or not it was successful. A return value of \fBPFMLIB_SUCCESS\fR indicates success, otherwise the value is the error code. .SH ERRORS .B PFMLIB_ERR_NOINIT the library has not been initialized properly. .TP .B PFMLIB_ERR_INVAL invalid argument was given, most likely invalid pointer or invalid PMU type. .TP .B PFMLIB_ERR_NOTSUPP the selected PMU type can be used on the host CPU. .SH AUTHOR Stephane Eranian .PP papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_get_event_description.30000644000307100002310000000003613013651447024226 0ustar yarkhangraduate.so man3/pfm_get_event_name.3 papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_find_event_mask.30000644000307100002310000000003213013651447022773 0ustar yarkhangraduate.so man3/pfm_find_event.3 papi-5.5.1/src/libpfm-3.y/docs/man3/libpfm.30000644000307100002310000001141313013651447020253 0ustar yarkhangraduate.TH LIBPFM 3 "March, 2008" "" "Linux Programmer's Manual" .SH NAME libpfm \- a helper library to program Hardware Performance Units (PMUs) .SH SYNOPSIS .nf .B #include .SH DESCRIPTION The libpfm library is a helper library which is used by applications to help program the Performance Monitoring Unit (PMU), i.e., the hardware performance counters of modern processors. It provides a generic and portable programming interface to help setup the PMU configuration registers given a list of events to measure. A diversity of PMU hardware is supported, a list can be found below under \fBSUPPORTED HARDWARE\fR. The library is primarily designed to be used in conjunction with the Perfmon2 Linux kernel interface. However, at its core, it is totally independent of that interface and could as well be used on other operating systems. It is important to realize that the library does not make the actual kernel calls to program the PMU, it simply helps applications figure out which PMU registers to use to measure certain events or access certain advanced PMU features. The library logically divides PMU registers into two categories. The performance monitoring data registers (PMD) are used to collect results, e.g., counts. The performance monitoring configuration registers (PMCS) are used to indicate what events to measure or what feature to enable. Programming the PMU consists in setting up the PMC registers and collecting the results in the PMD registers. The central piece of the library is the \fBpfm_dispatch_events\fR function. The number of PMC and PMD registers varies between architectures and CPU models. The association of PMC to PMD can also change. Moreover the number and encodings of events can also widely change. Finally, the structure of a PMC register can also change. All these factors make it quite difficult to write monitoring tools. This library is designed to simplify the programming of the PMC registers by hiding the complexity behind a simple interface. The library does this without limiting accessibility to model specific features by using a layered design. The library is structured in two layers. The common layer provides an interface that is shared across all PMU models. This layer is good enough to setup simple monitoring sessions which count occurrences of events. Then, there is a model-specific layer which gives access to the model-specific features. For instance, on Itanium, applications can use the library to setup the registers for the Branch Trace Buffer. Model-specific interfaces have the abbreviated PMU model name in their names. For instance, \fBpfm_ita2_get_event_umask()\fR is an Itanium2 (ita2) specific function. When the library is initialized, it automatically probes the host CPU and enables the right set of interfaces. The common interface is defined in the \fBpfmlib.h\fR header file. Model-specific interfaces are defined in model-specific header files. For instance, \fBpfmlib_amd64.h\fR provides the AMD64 interface. .SH ENVIRONMENT VARIABLES It is possible to enable certain debug output of the library using environment variables. The following variables are defined: .TP .B LIBPFM_VERBOSE Enable verbose output. Value must be 0 or 1. When not set, verbosity level can be controlled with this function. .TP .B LIBPFM_DEBUG Enable debug output. Value must be 0 or 1. When not set, debug level can be controlled with this function. .TP .B LIBPFM_DEBUG_STDOUT Redirect verbose and debug output to the standard output file descriptor (stdout). By default, the output is directed to the standard error file descriptor (stderr). .sp Alternatively, it is possible to control verbosity and debug output using the \fBpfm_set_options\fR function. .LP .SH SUPPORTED HARDWARE .nf libpfm_amd64(3) AMD64 processors K8 and Barcelona (families 0Fh and 10h) libpfm_core(3) Intel Core processor family libpfm_atom(3) Intel Atom processor family libpfm_itanium(3) Intel Itanium libpfm_itanium2(3) Intel Itanium 2 libpfm_montecito(3) Intel dual-core Itanium 2 9000 (Montecito) libpfm_p6(3) P6 processor family including the Pentium M processor libpfm_powerpc(3) IBM PowerPC and POWER processor families (PPC970(FX,GX), PPC970MP POWER4, POWER4+, POWER5, POWER5+, and POWER6) .fi .SH AUTHORS .nf Stephane Eranian Robert Richter .if .PP .SH SEE ALSO libpfm(3), libpfm_amd64(3), libpfm_core(3), libpfm_itanium2(3), libpfm_itanium(3), libpfm_montecito(3), libpfm_p6(3), libpfm_powerpc(3). .nf pfm_dispatch_events(3), pfm_find_event(3), pfm_set_options(3), pfm_get_cycle_event(3), pfm_get_event_name(3), pfm_get_impl_pmcs(3), pfm_get_pmu_name(3), pfm_get_version(3), pfm_initialize(3), pfm_regmask_set(3), pfm_set_options(3), pfm_strerror(3). .fi .sp Examples shipped with the library papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_get_hw_counter_width.30000644000307100002310000000003513013651447024055 0ustar yarkhangraduate.so man3/pfm_get_impl_pmcs.3 papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_regmask_weight.30000644000307100002310000000003313013651447022640 0ustar yarkhangraduate.so man3/pfm_regmask_set.3 papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_get_event_code.30000644000307100002310000000003613013651447022615 0ustar yarkhangraduate.so man3/pfm_get_event_name.3 papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_get_max_event_name_len.30000644000307100002310000000003613013651447024326 0ustar yarkhangraduate.so man3/pfm_get_event_name.3 papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_find_event.30000644000307100002310000001007113013651447021764 0ustar yarkhangraduate.TH LIBPFM 3 "August, 2006" "" "Linux Programmer's Manual" .SH NAME pfm_find_event, pfm_find_full_event, pfm_find_event_bycode, pfm_find_event_bycode_next, pfm_find_event_mask \- search for events and unit masks .SH SYNOPSIS .nf .B #include .sp .BI "int pfm_find_event(const char *"str ", unsigned int *"desc ");" .BI "int pfm_find_full_event(const char *"str ", pfmlib_event_t *"e ");" .BI "int pfm_find_event_bycode(int "code ", unsigned int *"desc ");" .BI "int pfm_find_event_bycode_next(unsigned int "desc1 ", int "code ", unsigned int *"desc ");" .BI "int pfm_find_event_mask(unsigned int "idx ", const char *"str ", unsigned int *"mask_idx ");" .sp .SH DESCRIPTION The PMU counters can be programmed to count the number of occurrences of certain events. The number of events varies from one PMU model to the other. Each event has a name and a code which is used to program the actual PMU register. Some event may need to be further qualified with unit masks. .sp The library does not directly expose the event code, nor unit mask code, to user applications because it is not necessary. Instead applications use names to query the library for particular information about events. Given an event name, the library returns an opaque descriptor. Each descriptor is unique and has no relationship to the event code. .sp The set of functions described here can be used to get an event descriptor given either the name of the event or its code. Several events may share the same code. An event name is a string structured as: event_name[:unit_mask1[:unit_mask2]]. .sp The \fBpfm_find_event()\fR function is a general purpose search routine. Given an event name in \fBstr\fR, it returns the descriptor for the corresponding event. If unit masks are provided, they are not taken into account. This function is being \fBdeprecated\fR in favor of the \fBpfm_find_full_event()\fR function. .sp The \fBpfm_find_full_event()\fR function is the general purpose search routine. Given an event name in \fBstr\fR, it returns in \fBev\fR, the full event descriptor that includes the event descriptor in \fBev->event\fR and the unit mask descriptors in \fBev->unit_masks\fR. The number of unit masks descriptors returned is indicated in \fBev->num_masks\fR. Unit masks are specified as a colon separated list of unit mask names, exact values or value combinations. For instance, if event A supports unit masks M1 (0x1) and M2 (0x40), and both unit masks are to be measured, then the following values for \fBstr\fR are valid: "A:M1:M2", "A:M1:0x40", "A:M2:0x1", "A:0x1:0x40", "A:0x41". .sp The \fBpfm_find_event_bycode()\fR function searches for an event given its \fBcode\fR represented as an integer. It returns in \fBdesc\fR, the event code. Unit masks are ignored. .sp Because there can be several events with the same code, the library provides the \fBpfm_find_event_bycode_next()\fR function to search for other events with the same code. Given an event \fBdesc1\fR and a \fBcode\fR, this function will look for the next event with the same code. If such an event exists, its descriptor will be stored into \fBdesc\fR. It is not necessary to have called the \fBpfm_find_event_bycode()\fR function prior to calling this function. This function is fully threadsafe as it does not maintain any state between calls. .sp The \fBpfm_find_event_mask()\fR function is used to find the unit mask descriptor based on its name or numerical value passed in \fBstr\fR for the event specified in \fBidx\fR. The numeric value must be an exact match of an existing unit mask value, i.e., all bits must match. Some events do not have unit masks, in which case this function returns an error. .SH RETURN All functions return whether or not the call was successful. A return value of \fBPFMLIB_SUCCESS\fR indicates success, otherwise the value is the error code. .SH ERRORS .B PFMLIB_ERR_NOINIT the library has not been initialized properly. .TP .B PFMLIB_ERR_INVAL the event descriptor is invalid, or the pointer argument is NULL. .TP .B PFMLIB_ERR_NOTFOUND no matching event or unit mask was found. .SH AUTHOR Stephane Eranian .PP papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_get_impl_pmcs.30000644000307100002310000000575513013651447022502 0ustar yarkhangraduate.TH LIBPFM 3 "July, 2003" "" "Linux Programmer's Manual" .SH NAME pfm_get_impl_pmcs, pfm_get_impl_pmds, pfm_get_impl_counters, pfm_get_num_counters, pfm_get_num_pmcs, pfm_get_num_pmds, pfm_get_hw_counter_width \- return bitmask of implemented PMU registers or number of PMU registers .SH SYNOPSIS .nf .B #include .sp .BI "int pfm_get_impl_pmcs(pfmlib_regmask_t *" impl_pmcs ");" .BI "int pfm_get_impl_pmds(pfmlib_regmask_t *" impl_pmds ");" .BI "int pfm_get_impl_counters(pfmlib_regmask_t *" impl_counters ");" .BI "int pfm_get_num_counters(unsigned int *"num ");" .BI "int pfm_get_num_pmcs(unsigned int *"num ");" .BI "int pfm_get_num_pmds(unsigned int *"num ");" .BI "int pfm_get_num_counters(unsigned int *"num ");" .BI "int pfm_get_hw_counter_width(unsigned int *"width ");" .sp .SH DESCRIPTION The \fBpfm_get_impl_*()\fR functions can be used to figure out which PMU registers are implemented on the host CPU. All implemented registers may not necessarily be available to applications. Programs need to query the operating system kernel monitoring interface to figure out the list of available registers. .sp The \fBpfm_get_impl_*()\fR functions all return a bitmask of registers corresponding to the query. The bitmask pointer passed as argument is reset to zero by each function. The returned bitmask must be accessed using the set of functions provided by the library to ensure portability. See related man pages below. .sp The \fBpfm_get_num_*()\fR functions return the number of implemented PMC or PMD registers. Those numbers may be different from the actual number of registers available to applications. .sp The \fBpfm_get_impl_pmcs()\fR function returns in \fBimpl_pmcs\fR the bitmask of implemented PMCS. The \fBpfm_get_impl_pmds()\fR function returns in \fBimpl_pmds\fR the bitmask of implemented PMDS. The \fBpfm_get_impl_counters()\fR function returns in \fBimpl_counters\fR a bitmask of the PMD registers used as counters. Depending on the PMU mode, not all PMD registers are necessarily used as counters. .sp The \fBpfm_get_num_counters()\fR function returns in \fBnum\fR the number of PMD used as counters. A counter is a PMD which is used to accumulate the number of occurrences of an event. The \fBpfm_get_num_pmcs()\fR function returns in \fBnum\fR the number of implemented PMCs by the host PMU. The \fBpfm_get_num_pmds()\fR function returns in \fBnum\fR the number of implemented PMDs by the host PMU. The \fBpfm_get_hw_counter_width()\fR function returns the width in bits of the counters in \fBwidth\fR. PMU implementations can have different number of bits implemented. For instance, Itanium has 32-bit counters, while Itanium 2 has 47-bits. .SH RETURN The function returns whether or not it was successful. A return value of \fBPFMLIB_SUCCESS\fR indicates success, otherwise the value is the error code. .SH ERRORS .B PFMLIB_ERR_NOINIT the library has not been initialized properly. .SH SEE ALSO pfm_regmask_set(3), pfm_regmask_isset(3) .SH AUTHOR Stephane Eranian .PP papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_get_event_mask_name.30000644000307100002310000000003613013651447023636 0ustar yarkhangraduate.so man3/pfm_get_event_name.3 papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_pmu_is_supported.30000644000307100002310000000003413013651447023242 0ustar yarkhangraduate.so man3/pfm_get_pmu_name.3 papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_get_impl_counters.30000644000307100002310000000003513013651447023364 0ustar yarkhangraduate.so man3/pfm_get_impl_pmcs.3 papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_list_supported_pmus.30000644000307100002310000000003413013651447023765 0ustar yarkhangraduate.so man3/pfm_get_pmu_name.3 papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_initialize.30000644000307100002310000000163213013651447022007 0ustar yarkhangraduate.TH LIBPFM 3 "November, 2003" "" "Linux Programmer's Manual" .SH NAME pfm_initialize \- initialize performance monitoring library .SH SYNOPSIS .nf .B #include .sp .BI "int pfm_initialize(void);" .sp .SH DESCRIPTION This is the first function that a program using the library \fBmust\fR call otherwise the library will not function at all. This function probes the host PMU and initialize the internal state of the library. In the case of a multi-threaded application, this function needs to be called only once, most likely by the initial thread. .SH RETURN The function returns whether or not it was successful, i.e., the host PMU has been correctly identified and is supported. A return value of \fBPFMLIB_SUCCESS\fR indicates success, otherwise the value is an error code. .SH ERRORS .TP .B PFMLIB_ERR_NOTSUPP the host PMU is not supported. .SH AUTHOR Stephane Eranian .PP papi-5.5.1/src/libpfm-3.y/docs/man3/libpfm_amd64.30000644000307100002310000001306513013651447021253 0ustar yarkhangraduate.TH LIBPFM 3 "April, 2008" "" "Linux Programmer's Manual" .SH NAME libpfm_amd64 - support for AMD64 processors .SH SYNOPSIS .nf .B #include .B #include .sp .SH DESCRIPTION The libpfm library provides full support for the AMD64 processor families 0Fh and 10H (K8, Barcelona, Phenom) when running in either 32-bit or 64-bit mode. The interface is defined in \fBpfmlib_amd64.h\fR. It consists of a set of functions and structures which describe and allow access to the AMD64 specific PMU features. Note that it only supports AMD processors. .sp When AMD64 processor-specific features are needed to support a measurement, their descriptions must be passed as model-specific input arguments to the \fBpfm_dispatch_events()\fR function. The AMD64 processor-specific input arguments are described in the \fBpfmlib_amd64_input_param_t\fR structure and the output parameters in \fBpfmlib_amd64_output_param_t\fR. They are defined as follows: .sp .nf typedef struct { uint32_t cnt_mask; uint32_t flags; } pfmlib_amd64_counter_t; typedef struct { unsigned int maxcnt; unsigned int options; } ibs_param_t; typedef struct { pfmlib_amd64_counter_t pfp_amd64_counters[PMU_AMD64_MAX_COUNTERS]; uint32_t flags; uint32_t reserved1; ibs_param_t ibsfetch; ibs_param_t ibsop; uint64_t reserved2; } pfmlib_amd64_input_param_t; typedef struct { uint32_t ibsfetch_base; uint32_t ibsop_base; uint64_t reserved[7]; } pfmlib_amd64_output_param_t; .fi .LP The \fBflags\fR field of \fBpfmlib_amd64_input_param_t\fR describes which features of the PMU to use. Following use flags exist: .TP .B PFMLIB_AMD64_USE_IBSFETCH Profile IBS fetch performance (see below under \fBINSTRUCTION BASED SAMPLING\fR) .TP .B PFMLIB_AMD64_USE_IBSOP Profile IBS execution performance (see below under \fBINSTRUCTION BASED SAMPLING\fR) .LP Multiple features can be selected. Note that there are no use flags needed for \fBADDITIONAL PER-EVENT FEATURES\fR. .LP Various typedefs for MSR encoding and decoding are available. See \fBpfmlib_amd64.h\fR for details. .SS ADDITIONAL PER-EVENT FEATURES AMD64 processors provide a few additional per-event features for counters: thresholding, inversion, edge detection, virtualization. They can be set using the \fBpfp_amd64_counters\fR data structure for each event. The \fBflags\fR field of \fBpfmlib_amd64_counter_t\fR can be initialized as follows: .TP .B PFMLIB_AMD64_SEL_INV Inverse the results of the \fBcnt_mask\fR comparison when set .TP .B PFMLIB_AMD64_SEL_EDGE Enables edge detection of events. .TP .B PFMLIB_AMD64_SEL_GUEST On AMD64 Family 10h processors only. Event is only measured when processor is in guest mode. .TP .B PFMLIB_AMD64_SEL_HOST On AMD64 Family 10h processors only. Event is only measured when processor is in host mode. .LP The \fBcnt_mask\fR field is used to set the event threshold. The value of the counter is incremented each time the number of occurrences per cycle of the event is greater or equal to the value of the field. When zero all occurrences are counted. .SS INSTRUCTION BASED SAMPLING (IBS) The libpfm_amd64 provides access to the model specific feature Instruction Based Sampling (IBS). IBS has been introduced with family 10h. .LP The IBS setup is using the structures \fBpfmlib_amd64_input_param_t\fR and \fBpfmlib_amd64_output_param_t\fR with its members \fBflags\fR, \fBibsfetch\fR, \fBibsop\fR, \fBibsfetch_base\fR, \fBibsop_base\fR. The input arguments \fBibsop\fR and \fBibsfetch\fR can be set in inp_mod (type \fBpfmlib_amd64_input_param_t\fR). The corresponding \fBflags\fR must be set to enable a feature. .LP Both, IBS execution profiling and IBS fetch profiling, require a maximum count value of the periodic counter (\fBmaxcnt\fR) as parameter. This is a 20 bit value, bits 3:0 are always set to zero. Additionally, there is an option (\fBoptions\fR) to enable randomization (\fBIBS_OPTIONS_RANDEN\fR) for IBS fetch profiling. .LP The IBS registers IbsFetchCtl (0xC0011030) and IbsOpCtl (0xC0011033) are available as PMC and PMD in Perfmon. The function \fBpfm_dispatch_events()\fR initializes these registers according to the input parameters in \fBpfmlib_amd64_input_param_t\fR. .LP Also, \fBpfm_dispatch_events()\fR passes back the index in pfp_pmds[] of the IbsOpCtl and IbsFetchCtl register. For this there are the entries \fBibsfetch_base\fR and \fBibsop_base\fR in \fBpfmlib_amd64_output_param_t\fR. The index may vary depending on other PMU settings, especially counter settings. If using the PMU with only one IBS feature and no counters, the index of the base register is 0. .LP Example code: .LP .nf /* initialize IBS */ inp_mod.ibsop.maxcnt = 0xFFFF0; inp_mod.flags |= PFMLIB_AMD64_USE_IBSOP; ret = pfm_dispatch_events(NULL, &inp_mod, &outp, &outp_mod); if (ret != PFMLIB_SUCCESS) { ... } /* setup PMU */ /* PMC_IBSOPCTL */ pc[0].reg_num = outp.pfp_pmcs[0].reg_num; pc[0].reg_value = outp.pfp_pmcs[0].reg_value; /* PMD_IBSOPCTL */ pd[0].reg_num = outp.pfp_pmds[0].reg_num; pd[0].reg_value = 0; /* setup sampling */ pd[0].reg_flags = PFM_REGFL_OVFL_NOTIFY; /* add range check here */ pd[0].reg_smpl_pmds[0] = ((1UL << PMD_IBSOP_NUM) - 1) << outp.pfp_pmds[0].reg_num; /* write pc and pd to PMU */ ... .fi .SH ERRORS Refer to the description of the \fBpfm_dispatch_events()\fR function for errors. .SH SEE ALSO pfm_dispatch_events(3) and set of examples shipped with the library .SH AUTHORS .nf Stephane Eranian Robert Richter .if .PP papi-5.5.1/src/libpfm-3.y/docs/man3/libpfm_nehalem.30000644000307100002310000001410213013651447021742 0ustar yarkhangraduate.TH LIBPFM 3 "January, 2009" "" "Linux Programmer's Manual" .SH NAME libpfm_nehalem - support for Intel Nehalem processor family .SH SYNOPSIS .nf .B #include .B #include .sp .SH DESCRIPTION The libpfm library provides full support for the Intel Nehalem processor family, such as Intel Core i7. The interface is defined in \fBpfmlib_intel_nhm.h\fR. It consists of a set of functions and structures describing the Intel Nehalem processor specific PMU features. The Intel Nehalem processor is a quad core, dual thread processor. It includes two types of PMU: core and uncore. The latter measures events at the socket level and is therefore disconnected from any of the four cores. The core PMU implements Intel architectural perfmon version 3 with four generic counters and three fixed counters. The uncore has eight generic counters and one fixed counter. Each Intel Nehalem core also implement a 16-deep branch trace buffer, called Last Branch Record (LBR), which can be used in combination with the core PMU. Intel Nehalem implements a newer version of the Precise Event-Based Sampling (PEBS) mechanism which has the ability to capture where cache misses occur. .sp When Intel Nehalem processor specific features are needed to support a measurement, their descriptions must be passed as model-specific input arguments to the \fBpfm_dispatch_events()\fR function. The Intel Nehalem processors specific input arguments are described in the \fBpfmlib_nhm_input_param_t\fR structure. No output parameters are currently defined. The input parameters are defined as follows: .sp .nf typedef struct { unsigned long cnt_mask; unsigned int flags; } pfmlib_nhm_counter_t; typedef struct { unsigned int lbr_used; unsigned int lbr_plm; unsigned int lbr_filter; } pfmlib_nhm_lbr_t; typedef struct { unsigned int pebs_used; unsigned int ld_lat_thres; } pfmlib_nhm_pebs_t; typedef struct { pfmlib_nhm_counter_t pfp_nhm_counters[PMU_NHM_NUM_COUNTERS]; pfmlib_nhm_pebs_t pfp_nhm_pebs; pfmlib_nhm_lbr_t pfm_nhm_lbr; uint64_t reserved[4]; } pfmlib_nhm_input_param_t; .fi .sp .sp The Intel Nehalem processor provides a few additional per-event features for counters: thresholding, inversion, edge detection, monitoring of both threads, occupancy. They can be set using the \fBpfp_nhm_counters\fR data structure for each event. The \fBflags\fR field can be initialized with the following values, depending on the event: .TP .B PFMLIB_NHM_SEL_INV Inverse the results of the \fBcnt_mask\fR comparison when set. This flag is supported for core and uncore PMU events. .TP .B PFMLIB_NHM_SEL_EDGE Enables edge detection of events. This flag is supported for core and uncore PMU events. .TP .B PFMLIB_NHM_SEL_ANYTHR Enable measuring the event in any of the two processor threads assuming hyper-threading is enabled. By default, only the current thread is measured. This flag is restricted to core PMU events. .TP .B PFMLIB_NHM_SEL_OCC_RST When set, the queue occupancy counter associated with the event is cleared. This flag is only available to uncore PMU events. .LP The \fBcnt_mask\fR field is used to set the event threshold. The value of the counter is incremented for each cycle in which the number of occurrences of the event is greater or equal to the value of the field. Thus, the event is modified to actually measure the number of qualifying cycles. When zero all occurrences are counted (this is the default). This flag is supported for core and uncore PMU events. .sp .SH Support for Precise-Event Based Sampling (PEBS) The library can be used to setup the PMC registers associated with PEBS. In this case, the \fBpfp_nhm_pebs_t\fR structure must be used and the \fBpebs_used\fR field must be set to 1. .sp To enable the PEBS load latency filtering capability, it is necessary to program the \fBMEM_INST_RETIRED:LATENCY_ABOVE_THRESHOLD\fR event into one generic counter. The latency threshold must be passed to the library in the \fBld_lat_thres\fR field. It is expressed in core cycles and \fBmust\fR greater than 3. Note that \fBpebs_used\fR must be set as well. .SH Support for Last Branch Record (LBR) The library can be used to setup LBR registers. On Intel Nehalem processors, the LBR is 16-entry deep and it is possible to filter branches, based on privilege level or type. To configure the LBR, the \fBpfm_nhm_lbr_t\fR structure must be used. .sp Like core PMU counters, LBR only distinguishes two privilege levels, 0 and the rest (1,2,3). When running Linux natively, the kernel is at privilege level 0, applications at level 3. It is possible to specify the privilege level of LBR using the \fBlbr_plm\fR. Any attempt to pass \fBPFM_PLM1\fB or \fBPFM_PLM2\fR will be rejected. If \fB\lbr_plm\fR is 0, then the global value in \fBpfmlib_input_param_t\fR and the \fBpfp_dfl_plm\fR is used. .sp By default, LBR captures all branches. It is possible to filter out branches by passing a set of flags in \fBlbr_select\fR. The flags are as follows: .TP .B PFMLIB_NHM_LBR_JCC When set, LBR does not capture conditional branches. Default: off. .TP .B PFM_NHM_LBR_NEAR_REL_CALL When set, LBR does not capture near calls. Default: off. .TP .B PFM_NHM_LBR_NEAR_IND_CALL When set, LBR does not capture indirect calls. Default: off. .TP .B PFM_NHM_LBR_NEAR_RET When set, LBR does not capture return branches. Default: off. .TP .B PFM_NHM_LBR_NEAR_IND_JMP When set, LBR does not capture indirect branches. Default: off. .TP .B PFM_NHM_LBR_NEAR_REL_JMP When set, LBR does not capture relative branches. Default: off. .TP .B PFM_NHM_LBR_FAR_BRANCH When set, LBR does not capture far branches. Default: off. .SH Support for uncore PMU By nature, the uncore PMU does not distinguish privilege levels, therefore it captures events at all privilege levels. To avoid any misinterpretation, the library enforces that uncore events be measured with both \fBPFM_PLM0\fR and \fBPFM_PLM3\fR set. Tools and operating system kernel interfaces may impose further restrictions on how the uncore PMU can be accessed. .SH SEE ALSO pfm_dispatch_events(3) and set of examples shipped with the library .SH AUTHOR Stephane Eranian .PP papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_get_event_mask_description.30000644000307100002310000000003613013651447025241 0ustar yarkhangraduate.so man3/pfm_get_event_name.3 papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_regmask_and.30000644000307100002310000000003313013651447022113 0ustar yarkhangraduate.so man3/pfm_regmask_set.3 papi-5.5.1/src/libpfm-3.y/docs/man3/libpfm_core.30000644000307100002310000000567013013651447021273 0ustar yarkhangraduate.TH LIBPFM 3 "November, 2006" "" "Linux Programmer's Manual" .SH NAME libpfm_core - support for Intel Core processor family .SH SYNOPSIS .nf .B #include .B #include .sp .SH DESCRIPTION The libpfm library provides full support for the Intel Core processor family, including the Core 2 Duo and Quad series. The interface is defined in \fBpfmlib_core.h\fR. It consists of a set of functions and structures which describe and allow access to the Intel Core processors specific PMU features. .sp When Intel Core processor specific features are needed to support a measurement, their descriptions must be passed as model-specific input arguments to the \fBpfm_dispatch_events()\fR function. The Intel Core processors specific input arguments are described in the \fBpfmlib_core_input_param_t\fR structure. No output parameters are currently defined. The input parameters are defined as follows: .sp .nf typedef struct { unsigned int cnt_mask; unsigned int flags; } pfmlib_core_counter_t; typedef struct { unsigned int pebs_used; } pfmlib_core_pebs_t; typedef struct { pfmlib_core_counter_t pfp_core_counters[PMU_CORE_NUM_COUNTERS]; pfmlib_core_pebs_t pfp_core_pebs; uint64_t reserved[4]; } pfmlib_core_input_param_t; .fi .sp .sp The Intel Core processor provides a few additional per-event features for counters: thresholding, inversion, edge detection. They can be set using the \fBpfp_core_counters\fR data structure for each event. The \fBflags\fR field can be initialized with any combinations of the following values: .TP .B PFMLIB_CORE_SEL_INV Inverse the results of the \fBcnt_mask\fR comparison when set .TP .B PFMLIB_CORE_SEL_EDGE Enables edge detection of events. .LP The \fBcnt_mask\fR field is used to set the event threshold. The value of the counter is incremented each time the number of occurrences per cycle of the event is greater or equal to the value of the field. Thus the event is modified to actually measure the number of qualifying cycles. When zero all occurrences are counted (this is the default). .sp .SH Support for Precise-Event Based Sampling (PEBS) The library can be used to setup the PMC registers when using PEBS. In this case, the \fBpfp_core_pebs\fR structure must be used and the \fBpebs_used\fR field must be set to 1. When using PEBS, it is not possible to use more than one event. .SH Support for Intel Core 2 Duo and Quad processors The Intel Core 2 Duo and Quad processors are based on the Intel Core micro-architecture. They implement the Intel architectural PMU and some extensions such as PEBS. They support all the architectural events and a lot more Core 2 specific events. The library auto-detects the processor and provides access to Core 2 events whenever possible. .LP .SH ERRORS Refer to the description of the \fBpfm_dispatch_events()\fR function for errors. .SH SEE ALSO pfm_dispatch_events(3) and set of examples shipped with the library .SH AUTHOR Stephane Eranian .PP papi-5.5.1/src/libpfm-3.y/docs/man3/libpfm_powerpc.30000644000307100002310000000331113013651447022010 0ustar yarkhangraduate.TH LIBPFM 3 "October, 2007" "" "Linux Programmer's Manual" .SH NAME libpfm_powerpc - support for IBM PowerPC and POWER processor families .SH SYNOPSIS .nf .B #include .B #include .sp .SH DESCRIPTION The libpfm library provides support for the IBM PowerPC and POWER processor families. Specifically, it currently provides support for the following processors: PPC970(FX,GX), PPC970MP POWER4, POWER4+, POWER5, POWER5+, and POWER6. .sp .SH MODEL-SPECIFIC PARAMETERS At present, the model_in and model_out model-specific input and output parameters are not used by \fBpfm_dispatch_events()\fR function. For future compatibility, NULLs must be passed for these arguments. .sp .SH COMBINING EVENTS IN A SET As with many architecture's PMU hardware design, events can not be combined together arbitrarily in the same event set, even if there are a sufficient number of counters available. This implementation for IBM PowerPC/POWER bases the event compatibility on a set of previously-defined compatible event groups. If the events placed in an event set are all members of one of the predefined event groups, a call to the \fBpfm_dispatch_events()\fR function will be successful. With the current interface, there is no way to discover apriori which events are compatible, so application software that wishes to combine events must do so by trial and error, possibly using multiplexed event sets to count events that cannot otherwise be combined in the same set. .sp .SH ERRORS Refer to the description of the \fBpfm_dispatch_events()\fR function for errors. .SH SEE ALSO pfm_dispatch_events(3) and set of examples shipped with the library .SH AUTHOR Corey Ashford .PP papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_regmask_or.30000644000307100002310000000003313013651447021771 0ustar yarkhangraduate.so man3/pfm_regmask_set.3 papi-5.5.1/src/libpfm-3.y/docs/man3/libpfm_montecito.30000644000307100002310000006167013013651447022346 0ustar yarkhangraduate.TH LIBPFM 3 "November, 2003" "" "Linux Programmer's Manual" .SH NAME libpfm_montecito - support for Itanium 2 9000 (Montecito) processor specific PMU features .SH SYNOPSIS .nf .B #include .B #include .sp .BI "int pfm_mont_is_ear(unsigned int " i ");" .BI "int pfm_mont_is_dear(unsigned int " i ");" .BI "int pfm_mont_is_dear_tlb(unsigned int " i ");" .BI "int pfm_mont_is_dear_cache(unsigned int " i ");" .BI "int pfm_mont_is_dear_alat(unsigned int " i ");" .BI "int pfm_mont_is_iear(unsigned int " i ");" .BI "int pfm_mont_is_iear_tlb(unsigned int " i ");" .BI "int pfm_mont_is_iear_cache(unsigned int " i ");" .BI "int pfm_mont_is_etb(unsigned int " i ");" .BI "int pfm_mont_support_opcm(unsigned int " i ");" .BI "int pfm_mont_support_iarr(unsigned int " i ");" .BI "int pfm_mont_support_darr(unsigned int " i ");" .BI "int pfm_mont_get_event_maxincr(unsigned int "i ", unsigned int *"maxincr ");" .BI "int pfm_mont_get_event_umask(unsigned int "i ", unsigned long *"umask ");" .BI "int pfm_mont_get_event_group(unsigned int "i ", int *"grp ");" .BI "int pfm_mont_get_event_set(unsigned int "i ", int *"set ");" .BI "int pfm_mont_get_event_type(unsigned int "i ", int *"type ");" .BI "int pfm_mont_get_ear_mode(unsigned int "i ", pfmlib_mont_ear_mode_t *"mode ");" .BI "int pfm_mont_irange_is_fine(pfmlib_output_param_t *"outp ", pfmlib_mont_output_param_t *"mod_out ");" .sp .SH DESCRIPTION The libpfm library provides full support for all the Itanium 2 900 (Montecito) processor specific features of the PMU. The interface is defined in \fBpfmlib_montecito.h\fR. It consists of a set of functions and structures which describe and allow access to the model specific PMU features. .sp The Itanium 2 900 (Montecito) processor specific functions presented here are mostly used to retrieve the characteristics of an event. Given a opaque event descriptor, obtained by the \fBpfm_find_event()\fR or its derivative functions, they return a boolean value indicating whether this event support this feature or is of a particular kind. .sp The \fBpfm_mont_is_ear()\fR function returns 1 if the event designated by \fBi\fR corresponds to a EAR event, i.e., an Event Address Register type of events. Otherwise 0 is returned. For instance, \fBDATA_EAR_CACHE_LAT4\fR is an ear event, but \fBCPU_OP_CYCLES_ALL\fR is not. It can be a data or instruction EAR event. .sp The \fBpfm_mont_is_dear()\fR function returns 1 if the event designated by \fBi\fR corresponds to an Data EAR event. Otherwise 0 is returned. It can be a cache or TLB EAR event. .sp The \fBpfm_mont_is_dear_tlb()\fR function returns 1 if the event designated by \fBi\fR corresponds to a Data EAR TLB event. Otherwise 0 is returned. .sp The \fBpfm_mont_is_dear_cache()\fR function returns 1 if the event designated by \fBi\fR corresponds to a Data EAR cache event. Otherwise 0 is returned. .sp The \fBpfm_mont_is_dear_alat()\fR function returns 1 if the event designated by \fBi\fR corresponds to a ALAT EAR cache event. Otherwise 0 is returned. .sp The \fBpfm_mont_is_iear()\fR function returns 1 if the event designated by \fBi\fR corresponds to an instruction EAR event. Otherwise 0 is returned. It can be a cache or TLB instruction EAR event. .sp The \fBpfm_mont_is_iear_tlb()\fR function returns 1 if the event designated by \fBi\fR corresponds to an instruction EAR TLB event. Otherwise 0 is returned. .sp The \fBpfm_mont_is_iear_cache()\fR function returns 1 if the event designated by \fBi\fR corresponds to an instruction EAR cache event. Otherwise 0 is returned. .sp The \fBpfm_mont_support_opcm()\fR function returns 1 if the event designated by \fBi\fR supports opcode matching, i.e., can this event be measured accurately when opcode matching via PMC32/PMC34 is active. Not all events supports this feature. .sp The \fBpfm_mont_support_iarr()\fR function returns 1 if the event designated by \fBi\fR supports code address range restrictions, i.e., can this event be measured accurately when code range restriction is active. Otherwise 0 is returned. Not all events supports this feature. .sp The \fBpfm_mont_support_darr()\fR function returns 1 if the event designated by \fBi\fR supports data address range restrictions, i.e., can this event be measured accurately when data range restriction is active. Otherwise 0 is returned. Not all events supports this feature. .sp The \fBpfm_mont_get_event_maxincr()\fR function returns in \fBmaxincr\fR the maximum number of occurrences per cycle for the event designated by \fBi\fR. Certain Itanium 2 9000 (Montecito) events can occur more than once per cycle. When an event occurs more than once per cycle, the PMD counter will be incremented accordingly. It is possible to restrict measurement when event occur more than once per cycle. For instance, \fBNOPS_RETIRED\fR can happen up to 6 times/cycle which means that the threshold can be adjusted between 0 and 5, where 5 would mean that the PMD counter would be incremented by 1 only when the nop instruction is executed more than 5 times/cycle. This function returns the maximum number of occurrences of the event per cycle, and is the non-inclusive upper bound for the threshold to program in the PMC register. .sp The \fBpfm_mont_get_event_umask()\fR function returns in \fBumask\fR the umask for the event designated by \fBi\fR. .sp The \fBpfm_mont_get_event_grp()\fR function returns in \fBgrp\fR the group to which the event designated by \fBi\fR belongs. The notion of group is used for L1D and L2D cache events only. For all other events, a group is irrelevant and can be ignored. If the event is an L2D cache event then the value of \fBgrp\fR will be \fBPFMLIB_MONT_EVT_L2D_CACHE_GRP\fR. Similarly, if the event is an L1D cache event, the value of \fBgrp\fR will be \fBPFMLIB_MONT_EVT_L1D_CACHE_GRP\fR. In any other cases, the value of \fBgrp\fR will be \fBPFMLIB_MONT_EVT_NO_GRP\fR. .sp The \fBpfm_mont_get_event_set()\fR function returns in \fBset\fR the set to which the event designated by \fBi\fR belongs. A set is a subdivision of a group and is therefore only relevant for L1 and L2 cache events. An event can only belong to one group and one set. This partitioning of the cache events is due to some hardware limitations which impose some restrictions on events. For a given group, events from different sets cannot be measured at the same time. If the event does not belong to a group then the value of \fBset\fR is \fBPFMLIB_MONT_EVT_NO_SET\fR. .sp The \fBpfm_mont_get_event_type()\fR function returns in \fBtype\fR the type of the event designated by \fBi\fR belongs. The itanium2 9000 (Montecito) events can have any one of the following types: .sp .TP .B PFMLIB_MONT_EVT_ACTIVE The event can only occur when the processor thread that generated it is currently active .TP .B PFMLIB_MONT_EVT_FLOATING The event can be generated when the processor thread is inactive .TP .B PFMLIB_MONT_EVT_CAUSAL The event does not belong to a processor thread .TP .B PFMLIB_MONT_EVT_SELF_FLOATING Hybrid event. It is floating if measured with .me. If is causal otherwise. .LP .sp The \fBpfm_mont_irange_is_fine()\fR function returns 1 if the configuration description passed in \fBoutp\fR, the generic output parameters and \fBmod_out\fR, the Itanium 2 9000 (Montecito) specific output parameters, use code range restriction in fine mode. Otherwise the function returns 0. This function can only be called after a call to the \fBpfm_dispatch_events()\fR function returns successfully and had the data structures pointed to by \fBoutp\fR and \fBmod_out\fR as output parameters. .sp The \fBpfm_mont_get_event_ear_mode()\fR function returns in \fBmode\fR the EAR mode of the event designated by \fBi\fR. If the event is not an EAR event, then \fBPFMLIB_ERR_INVAL\fR is returned and mode is not updated. Otherwise mode can have the following values: .TP .B PFMLIB_MONT_EAR_TLB_MODE The event is an EAR TLB mode. It can be either data or instruction TLB EAR. .TP .B PFMLIB_MONT_EAR_CACHE_MODE The event is a cache EAR. It can be either data or instruction cache EAR. .TP .B PFMLIB_MONT_EAR_ALAT_MODE The event is an ALAT EAR. It can only be a data EAR event. .sp .LP When the Itanium 2 9000 (Montecito) specific features are needed to support a measurement their descriptions must be passed as model-specific input arguments to the \fBpfm_dispatch_events()\fR function. The Itanium 2 9000 (Montecito) specific input arguments are described in the \fBpfmlib_mont_input_param_t\fR structure and the output parameters in \fBpfmlib_mont_output_param_t\fR. They are defined as follows: .sp .nf typedef struct { unsigned int flags; unsigned int thres; } pfmlib_mont_counter_t; typedef struct { unsigned char opcm_used; unsigned char opcm_m; unsigned char opcm_i; unsigned char opcm_f; unsigned char opcm_b; unsigned long opcm_match; unsigned long opcm_mask; } pfmlib_mont_opcm_t; typedef struct { unsigned char etb_used; unsigned int etb_plm; unsigned char etb_ds; unsigned char etb_tm; unsigned char etb_ptm; unsigned char etb_ppm; unsigned char etb_brt; } pfmlib_mont_etb_t; typedef struct { unsigned char ipear_used; unsigned int ipear_plm; unsigned short ipear_delay; } pfmlib_mont_ipear_t; typedef enum { PFMLIB_MONT_EAR_CACHE_MODE= 0, PFMLIB_MONT_EAR_TLB_MODE = 1, PFMLIB_MONT_EAR_ALAT_MODE = 2 } pfmlib_mont_ear_mode_t; typedef struct { unsigned char ear_used; pfmlib_mont_ear_mode_t ear_mode; unsigned int ear_plm; unsigned long ear_umask; } pfmlib_mont_ear_t; typedef struct { unsigned int rr_plm; unsigned long rr_start; unsigned long rr_end; } pfmlib_mont_input_rr_desc_t; typedef struct { unsigned long rr_soff; unsigned long rr_eoff; } pfmlib_mont_output_rr_desc_t; typedef struct { unsigned int rr_flags; pfmlib_mont_input_rr_desc_t rr_limits[4]; unsigned char rr_used; } pfmlib_mont_input_rr_t; typedef struct { unsigned int rr_nbr_used; pfmlib_mont_output_rr_desc_t rr_infos[4]; pfmlib_reg_t rr_br[8]; } pfmlib_mont_output_rr_t; typedef struct { pfmlib_mont_counter_t pfp_mont_counters[PMU_MONT_NUM_COUNTERS]; unsigned long pfp_mont_flags; pfmlib_mont_opcm_t pfp_mont_opcm1; pfmlib_mont_opcm_t pfp_mont_opcm2; pfmlib_mont_ear_t pfp_mont_iear; pfmlib_mont_ear_t pfp_mont_dear; pfmlib_mont_ipear_t pfp_mont_ipear; pfmlib_mont_etb_t pfp_mont_etb; pfmlib_mont_input_rr_t pfp_mont_drange; pfmlib_mont_input_rr_t pfp_mont_irange; } pfmlib_mont_input_param_t; typedef struct { pfmlib_mont_output_rr_t pfp_mont_drange; pfmlib_mont_output_rr_t pfp_mont_irange; } pfmlib_mont_output_param_t; .fi .sp .SH PER-EVENT OPTIONS .sp The Itanium 2 9000 (Montecito) processor provides one per-event feature for counters: thresholding. It can be set using the \fBpfp_mont_counters\fR data structure for each event. .sp The \fBthres\fR indicates the threshold for the event. A threshold of \fBn\fR means that the counter will be incremented by one only when the event occurs more than \fBn\fR times per cycle. The \fBflags\fR field contains event-specific flags. The currently defined flags are: .sp .TP PFMLIB_MONT_FL_EVT_NO_QUALCHECK When this flag is set it indicates that the library should ignore the qualifiers constraints for this event. Qualifiers includes opcode matching, code and data range restrictions. When an event is marked as not supporting a particular qualifier, it usually means that it is ignored, i.e., the extra level of filtering is ignored. For instance, the FE_BUBBLE_ALL event does not support code range restrictions and by default the library will refuse to program it if range restriction is also requested. Using the flag will override the check and the call to the \fBpfm_dispatch_events()\fR function will succeed. In this case, FE_BUBBLE_ALL will be measured for the entire program and not just for the code range requested. For certain measurements this is perfectly acceptable as the range restriction will only be applied relevant to events which support it. Make sure you understand which events do not support certain qualifiers before using this flag. .LP .SH OPCODE MATCHING .sp The \fBpfp_mont_opcm1\fR and \fBpfp_mont_opcm2\fR fields of type \fBpfmlib_mont_opcm_t\fR contain the description of what to do with the opcode matchers. The Itanium 2 9000 (Montecito) processor supports opcode matching via PMC32 and PMC34. When this feature is used the \fBopcm_used\fR field must be set to 1, otherwise it is ignored by the library. The Itanium 2 9000 (Montecito) processor implements two full 41-bit opcode matchers. As such, it is possible to match all instructions individually. It is possible to match a single instruction or an instruction pattern based on opcode or slot type. The slots are specified in: .TP .B opcm_m Match when the instruction is in a M-slot (memory) .TP .B opcm_i Match when the instruction is in an I-slot (ALU) .TP .B opcm_f Match when the instruction is in an F-slot (FPU) .TP .B opcm_b Match when the instruction is in a B-slot (Branch) .sp .LP Any combinations of slot settings is supported. To match all slot types, simply set all fields to 1. .sp The 41-bit opcode is specified in \fBopcm_match\fR and a 41-bit mask is passed in \fBopcm_mask\fR. When a bit is set in \fBopcm_mask\fR the corresponding bit is ignored in \fBopcm_match\fR. .SH EVENT ADDRESS REGISTERS .sp The \fBpfp_mont_iear\fR field of type \fBpfmlib_mont_ear_t\fR describes what to do with instruction Event Address Registers (I-EARs). Again if this feature is used the \fBear_used\fR must be set to 1, otherwise it will be ignored by the library. The \fBear_mode\fR must be set to either one of \fBPFMLIB_MONT_EAR_TLB_MODE\fR, \fBPFMLIB_MONT_EAR_CACHE_MODE\fRto indicate the type of EAR to program. The umask to store into PMC10 must be in \fBear_umask\fR. The privilege level mask at which the I-EAR will be monitored must be set in \fBear_plm\fR which can be any combination of \fBPFM_PLM0\fR, \fBPFM_PLM1\fR, \fBPFM_PLM2\fR, \fBPFM_PLM3\fR. If \fBear_plm\fR is 0 then the default privilege level mask in \fBpfp_dfl_plm\fR is used. .sp The \fBpfp_mont_dear\fR field of type \fBpfmlib_mont_ear_t\fR describes what to do with data Event Address Registers (D-EARs). The description is identical to the I-EARs except that it applies to PMC11 and that a \fBear_mode\fR of \fBPFMLIB_MONT_EAR_ALAT_MODE\fR is possible. In general, there are four different methods to program the EAR (data or instruction): .TP .B Method 1 There is an EAR event in the list of events to monitor and \fBear_used\fR is cleared. In this case the EAR will be programmed (PMC10 or PMC11) based on the information encoded in the event. A counting monitor (PMC4/PMD4-PMC7/PMD7) will be programmed to count \fBDATA_EAR_EVENT\fR or \fBL1I_EAR_EVENTS\fR depending on the type of EAR. .TP .B Method 2 There is an EAR event in the list of events to monitor and \fBear_used\fR is set. In this case the EAR will be programmed (PMC10 or PMC11) using the information in the \fBpfp_ita_iear\fR or \fBpfp_ita_dear\fR structure because it contains more detailed information, such as privilege level and instruction set. A counting monitor (PMC4/PMD4-PMC7/PMD7) will be programmed to count DATA_EAR_EVENT or L1I_EAR_EVENTS depending on the type of EAR. .TP .B Method 3 There is no EAR event in the list of events to monitor and and \fBear_used\fR is cleared. In this case no EAR is programmed. .TP .B Method 4 There is no EAR event in the list of events to monitor and and \fBear_used\fR is set. In this case case the EAR will be programmed (PMC10 or PMC11) using the information in the \fBpfp_mont_iear\fR or \fBpfp_mont_dear\fR structure. This is the free running mode for the EAR. .sp .SH EXECUTION TRACE BUFFER The \fBpfp_mont_etb\fR of type \fBpfmlib_mont_etb_t\fR field is used to configure the Execution Trace Buffer (ETB). If the \fBetb_used\fR is set, then the library will take the configuration into account, otherwise any ETB configuration will be ignored. The various fields in this structure provide means to filter out the kind of changes in the control flow (branches, traps, rfi, ...) that get recorded in the ETB. Each one represents an element of the branch architecture of the Itanium 2 9000 (Montecito) processor. Refer to the Itanium 2 9000 (Montecito) specific documentation for more details on the branch architecture. The fields are as follows: .TP .B etb_tm If this field is 0, then no branch is captured. If this field is 1, then non taken branches are captured. If this field is 2, then taken branches are captured. Finally if this field is 3 then all branches are captured. .TP .B etb_ptm If this field is 0, then no branch is captured. If this field is 1, then branches with a mispredicted target address are captured. If this field is 2, then branches with correctly predicted target address are captured. Finally if this field is 3 then all branches are captured regardless of target address prediction. .TP .B etb_ppm If this field is 0, then no branch is captured. If this field is 1, then branches with a mispredicted path (taken/non taken) are captured. If this field is 2, then branches with correctly predicted path are captured. Finally if this field is 3 then all branches are captured regardless of their path prediction. .TP .B etb_brt If this field is 0, then no branch is captured. If this field is 1, then only IP-relative branches are captured. If this field is 2, then only return branches are captured. Finally if this field is 3 then only non-return indirect branches are captured. .TP .B etb_plm This is the privilege level mask at which the ETB captures branches. It can be any combination of \fBPFM_PLM0\fR, \fBPFM_PLM1\fR, \fBPFM_PLM2\fR, \fBPFM_PLM3\fR. If \fBetb_plm\fR is 0 then the default privilege level mask in \fBpfp_dfl_plm\fR is used. .sp There are 4 methods to program the ETB and they are as follows: .sp .TP .B Method 1 The \fBETB_EVENT\fR is in the list of event to monitor and \fBetb_used\fR is cleared. In this case, the ETB will be configured (PMC39) to record ALL branches. A counting monitor will be programmed to count \fBETB_EVENT\fR. .TP .B Method 2 The \fBETB_EVENT\fR is in the list of events to monitor and \fBetb_used\fR is set. In this case, the BTB will be configured (PMC39) using the information in the \fBpfp_mont_etb\fR structure. A counting monitor (PMC4/PMD4-PMC7/PMD7) will be programmed to count \fBBRANCH_EVENT\fR. .TP .B Method 3 The \fBETB_EVENT\fR is not in the list of events to monitor and \fBetb_used\fR is set. In this case, the ETB will be configured (PMC39) using the information in the \fBpfp_mont_etb\fR structure. This is the free running mode for the ETB. .TP .B Method 4 The \fBETB_EVENT\fR is not in the list of events to monitor and \fBetb_used\fR is cleared. In this case, the ETB is not programmed. .SH DATA AND CODE RANGE RESTRICTIONS The \fBpfp_mont_drange\fR and \fBpfp_mont_irange\fR fields control the range restrictions for the data and code respectively. The idea is that the application passes a set of ranges, each designated by a start and end address. Upon return from the \fBpfm_dispatch_events()\fR function, the application gets back the set of registers and their values that needs to be programmed via a kernel interface. Range restriction is implemented using the debug registers. There is a limited number of debug registers and they go in pair. With 8 data debug registers, a maximum of 4 distinct ranges can be specified. The same applies to code range restrictions. Moreover, there are some severe constraints on the alignment and size of the ranges. Given that the size of a range is specified using a bitmask, there can be situations where the actual range is larger than the requested range. For code ranges, Itanium 2 9000 (Montecito) processor can use what is called a fine mode, where a range is designated using two pairs of code debug registers. In this mode, the bitmask is not used, the start and end addresses are directly specified. Not all code ranges qualify for fine mode, the size of the range must be 64KB or less and the range cannot cross a 64KB page boundary. The library will make a best effort in choosing the right mode for each range. For code ranges, it will try the fine mode first and will default to using the bitmask mode otherwise. Fine mode applies to all code debug registers or none, i.e., you cannot have a range using fine mode and another using the bitmask. The Itanium 2 9000 (Montecito) processor somehow limits the use of multiple pairs to accurately cover a code range. This can only be done for \fBIA64_INST_RETIRED\fR and even then, you need several events to collect the counts. For all other events, only one pair can be used, which leads to more inaccuracy due to approximation. Data ranges can used multiple debug register pairs to gain more accuracy. The library will never cover less than what is requested. The algorithm will use more than one pair of debug registers whenever possible to get a more precise range. Hence, up to the 4 pairs can be used to describe a single range. If range restriction is to be used, the \fBrr_used\fR field must be set to one, otherwise settings will be ignored. The ranges are described by the \fBpfmlib_mont_input_rr_t\fR structure. Up to 4 ranges can be defined. Each range is described in by a entry in \fBrr_limits\fR. Some flags for all ranges can be defined in \fBrr_flags\fR. Currently defined flags are: .sp .TP .B PFMLIB_MONT_RR_INV Inverse the code ranges. The qualifying events will be measurement when executing outside the specified ranges. .TP .B PFMLIB_MONT_RR_NO_FINE_MODE Force non fine mode for all code ranges (mostly for debug) .sp .LP The \fBpfmlib_mont_input_rr_desc_t\fR structure is defined as follows: .TP .B rr_plm The privilege level at which the range is active. It can be any combinations of \fBPFM_PLM0\fR, \fBPFM_PLM1\fR, \fBPFM_PLM2\fR, \fBPFM_PLM3\fR. If \fBetb_plm\fR is 0 then the default privilege level mask in \fBpfp_dfl_plm\fR is used. The privilege level is only relevant for code ranges, data ranges ignores the setting. .TP .B rr_start This is the start address of the range. Any address is supported but for code range it must be bundle aligned, i.e., 16-byte aligned. .TP .B rr_end This is the end address of the range. Any address is supported but for code range it must be bundle aligned, i.e., 16-byte aligned. .sp .LP The library will provide the values for the debug registers as well as some information about the actual ranges in the output parameters and more precisely in the \fBpfmlib_mont_output_rr_t\fR structure for each range. The structure is defined as follows: .TP .B rr_nbr_used Contains the number of debug registers used to cover the range. This is necessarily an even number as debug registers always go in pair. The value of this field is between 0 and 7. .TP .B rr_br This table contains the list of debug registers necessary to cover the ranges. Each element is of type \fBpfmlib_reg_t\fR. The \fBreg_num\fR field contains the debug register index while \fBreg_value\fR contains the debug register value. Both the index and value must be copied into the kernel specific argument to program the debug registers. The library never programs them. .TP .B rr_infos Contains information about the ranges defined. Because of alignment restrictions, the actual range covered by the debug registers may be larger than the requested range. This table describe the differences between the requested and actual ranges expressed as offsets: .TP .B rr_soff Contains the start offset of the actual range described by the debug registers. If zero, it means the library was able to match exactly the beginning of the range. Otherwise it represents the number of byte by which the actual range precedes the requested range. .TP .B rr_eoff Contains the end offset of the actual range described by the debug registers. If zero, it means the library was able to match exactly the end of the range. Otherwise it represents the number of bytes by which the actual range exceeds the requested range. .sp .LP .SH IP EVENT CAPTURE (IP-EAR) The Execution Trace Buffer (ETB) can be configured to record the addresses of consecutive retiring instructions. In this case the ETB contains IP addresses and not branches related information. This feature cannot be used in conjunction with regular branch captures as described above. To active this feature the \fBipear_used\fR field of the \fBpfmlib_mont_ipear_t\fR must be set to 1. The other fields in this structure are used as follows: .sp .TP .B ipear_plm The privilege level of the instructions to capture. It can be any combination of \fBPFM_PLM0\fR, \fBPFM_PLM1\fR, \fBPFM_PLM2\fR, \fBPFM_PLM3\fR. If \fBetb_plm\fR is 0 then the default privilege level mask in \fBpfp_dfl_plm\fR is used. .TP .B ipear_delay The number of cycles by which to delay the freeze of the ETB after a PMU interrupt (which freeze the rest of counters). .LP .sp .SH ERRORS Refer to the description of the \fBpfm_dispatch_events()\fR function for errors when using the Itanium 2 9000 (Montecito) specific input and output arguments. .SH SEE ALSO pfm_dispatch_events(3) and set of examples shipped with the library .SH AUTHOR Stephane Eranian .PP papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_get_full_event_name.30000644000307100002310000000003613013651447023645 0ustar yarkhangraduate.so man3/pfm_get_event_name.3 papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_regmask_eq.30000644000307100002310000000003313013651447021756 0ustar yarkhangraduate.so man3/pfm_regmask_set.3 papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_get_event_name.30000644000307100002310000001521013013651447022623 0ustar yarkhangraduate.TH LIBPFM 3 "August, 2006" "" "Linux Programmer's Manual" .SH NAME pfm_get_event_name, pfm_get_full_event_name, pfm_get_event_mask_name, pfm_get_event_code, pfm_get_event_mask_code, pfm_get_event_counters, pfm_get_num_events, pfm_get_max_event_name_len, pfm_get_event_description, pfm_get_event_mask_description \- get event information .SH SYNOPSIS .nf .B #include .sp .BI "int pfm_get_event_name(unsigned int " e ", char *"name ", size_t " maxlen ");" .BI "int pfm_get_full_event_name(pfmlib_event_t *" ev ", char *"name ", size_t " maxlen ");" .BI "int pfm_get_event_mask_name(unsigned int " e ", unsigned int "mask ", char *"name ", size_t " maxlen ");" .BI "int pfm_get_event_code(unsigned int " e ", int *"code ");" .BI "int pfm_get_event_mask_code(unsigned int " e ", unsigned int "mask ", int *"code ");" .BI "int pfm_get_event_code_counter(unsigned int " e ", unsigned int " cnt ", int *"code ");" .BI "int pfm_get_event_counters(int " e ", pfmlib_regmask_t "counters ");" .BI "int pfm_get_num_events(unsigned int *" count ");" .BI "int pfm_get_max_event_name_len(size_t *" len ");" .BI "int pfm_get_event_description(unsigned int " ev ", char **" str ");" .BI "int pfm_get_event_mask_description(unsigned int " ev ", unsigned int "mask ", char **" str ");" .sp .SH DESCRIPTION The \fBpfm_get_event_name()\fR function returns in \fBname\fR the event name given its opaque descriptor in \fBe\fR. The \fBmaxlen\fR argument indicates the maximum length of the buffer provided for \fBname\fR. Up to \fBmaxlen\fR-1 characters are stored in the buffer. The buffer size must be large enough to store the event name, otherwise an error is returned. This behavior is required to avoid returning partial names with no way for the caller to verify this is not the full name, except by failing other calls. The buffer can be appropriately sized using the \fBpfm_get_max_event_name_len()\fR function. The returned name is a null terminated string with all upper-case characters and no spaces. .sp The \fBpfm_get_full_event_name()\fR function returns in \fBname\fR the event name given the full event description in \fBev\fR. The description contains the event code in \fBev->event\fR and optional unit masks descriptors in \fBev->unit_masks\fR. The \fBmaxlen\fR argument indicates the maximum length of the buffer provided for \fBname\fR. If more than \fBmaxlen\fR-1 characters are needed to represent the event, an error is returned. Applications may use the \fBpfm_get_max_event_name_len()\fR function to size the buffer correctly. In case unit masks are provided, the final event name string is structured as: event_name:unit_masks1[:unit_masks2]. Event names and unit masks names are returned in all upper case. .sp The \fBpfm_get_event_code()\fR function returns the event code in \fBcode\fR given its opaque descriptor \fBe\fR. .sp On some PMU models, the code associated with an event is different based on the counter it is programmed into. The \fBpfm_get_event_code_counter()\fR function is used to retrieve the event code in \fBcode\fR when the event \fBe\fR is programmed into counter \fBcnt\fR. The counter index \fBcnt\fR must correspond to of a counting PMD register. .sp Given an opaque event descriptor \fBe\fR, the \fBpfm_get_event_counters()\fR function returns in \fBcounters\fR a bitmask of type \fBpfmlib_regmask_t\fR where each bit set represents a PMU config register which can be used to program this event. The bitmask must be accessed using accessor macros defined by the library. .so The \fBpfm_get_num_events()\fR function returns in \fBcount\fR the total number of events available for the PMU model. On some PMU models, however, not all events in the table may be useable due to processor stepping changes. However, The library guarantees that no more that \fBcount\fR events are available. .sp It is possible to list all existing events for the detected host PMU using accessor functions as the full table of events is not accessible to the applications. The index of the first event is always zero, then using the \fBpfm_get_num_events()\fR function you get the total number of events. On some PMU models, e.g., AMD64, not all events are necessarily supported by the host PMU, therefore the count returned by this calls may not be the actual number of available events. Event descriptors are contiguous therefore a simple loop will allow complete scanning. The typical scan loop is constructed as follows: .sp .nf unsigned int i, count; char name[256]; int ret; pfm_get_num_events(&count); for(i=0;i < count; i++) { ret = pfm_get_event_name(i, name, 256); if (ret != PFMLIB_SUCCESS) continue; printf("%s\\n", name); } .fi .sp The \fBpfm_get_max_event_name_len()\fR function returns in \fBlen\fR the maximum length in bytes for the name of the events or its unit masks, if any, available on one PMU implementation. The value excludes the string termination character ('\\0'). .sp The \fBpfm_get_event_description()\fR function returns in \fBstr\fR the description string associated with the event specified in \fBev\fR. The description is returned into a buffer that is allocated to hold the entire description text. It is the responsibility of the caller to free the buffer when it becomes useless by calling the \fBfree(3)\fR function. .sp The \fBpfm_get_event_mask_code()\fR function must be used to retrieve the actual unit mask value given a event descriptor in \fBe\fR and a unit mask descriptor in \fBmask\fR. The value is returned in \fBcode\fR. .sp The \fBpfm_get_event_mask_name()\fR function must be used to retrieve the name associated with a unit mask specified in \fBmask\fR for event \fBe\fR. The name is returned in the buffer specified in \fBname\fR. The maximum size of the buffer must be specified in \fBmaxlen\fR. .sp The \fBpfm_get_event_mask_description()\fR function returns in \fBstr\fR the description string associated with the unit mask specified in \fBmask\fR for the event specified in \fBev\fR. The description is returned into a buffer that is allocated to hold the entire description text. It is the responsibility of the caller to free the buffer when it becomes useless by calling the \fBfree(3)\fR function. .SH RETURN All functions return whether or not the call was successful. A return value of \fBPFMLIB_SUCCESS\fR indicates success, otherwise the value is the error code. .SH ERRORS .B PFMLIB_ERR_NOINIT the library has not been initialized properly. .TP .B PFMLIB_ERR_FULL the string buffer provided is too small .TP .B PFMLIB_ERR_INVAL the event or unit mask descriptor, or the \fBcnt\fR argument is invalid, or a pointer argument is NULL. .SH SEE ALSO pfm_get_impl_counters(3), pfm_get_max_event_name_len(3), free(3) .SH AUTHOR Stephane Eranian .PP papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_strerror.30000644000307100002310000000145213013651447021530 0ustar yarkhangraduate.TH LIBPFM 3 "November, 2003" "" "Linux Programmer's Manual" .SH NAME pfm_strerror \- return string describing error code .SH SYNOPSIS .nf .B #include .sp .BI "char *pfm_strerror(int "code); .sp .SH DESCRIPTION This function returns a string which describes the libpfm error value in \fBcode\fR. The string returned by the call must be considered as read only. The function must \fBonly\fR be used on libpfm calls. It is not designed to handle OS system call errors. .SH RETURN The function returns a pointer to the string describing the error code. If code is invalid then the default error message is returned. .SH ERRORS If the error code is invalid, then the function returns a pointer to a string which says "unknown error code". .SH AUTHOR Stephane Eranian .PP papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_find_full_event.30000644000307100002310000000003213013651447023002 0ustar yarkhangraduate.so man3/pfm_find_event.3 papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_regmask_set.30000644000307100002310000000507013013651447022152 0ustar yarkhangraduate.TH LIBPFM 3 "Apr, 2006" "" "Linux Programmer's Manual" .SH NAME pfm_regmask_set, pfm_regmask_isset, pfm_regmask_clr, pfm_regmask_weight, pfm_regmask_eq, pfm_regmask_and, pfm_regmask_or, pfm_regmask_copy -\ operations on pfmlib_regmask_t bitmasks .SH SYNOPSIS .nf .B #include .sp .BI "int pfm_regmask_isset(pfmlib_regmask_t *"mask ", unsigned int "b ");" .BI "int pfm_regmask_set(pfmlib_regmask_t *"mask ", unsigned int "b ");" .BI "int pfm_regmask_clr(pfmlib_regmask_t *"mask ", unsigned int "b ");" .BI "int pfm_regmask_weight(pfmlib_regmask_t *"mask ", unsigned int *"w ");" .BI "int pfm_regmask_eq(pfmlib_regmask_t *"mask1 ", pfmlib_regmask_t *"mask2 ");" .BI "int pfm_regmask_and(pfmlib_regmask_t *"dest ", pfmlib_regmask_t *"m1 ", pmlib_regmask_t *"m2 ");" .BI "int pfm_regmask_or(pfmlib_regmask_t *"dest ", pfmlib_regmask_t *"m1 ", pmlib_regmask_t *"m2 ");" .BI "int pfm_regmask_copy(pfmlib_regmask_t *"dest ", pfmlib_regmask_t *"src ");" .sp .SH DESCRIPTION This set of function is used to operate of the \fBpfmlib_regmask_t\fR bitmasks that are returned by certain functions or passed to the \fBpfm_dispatch_events()\fR function. To ensure portability, it is important that applications use \fBonly\fR the functions specified here to access the bitmasks. It is strongly discouraged to access the internal fields of the \fBpfm_regmask_t\fR structure. The \fBpfm_regmask_set()\fR function is used to set bit \fBb\fR in the bitmask \fBmask\fR. The \fBpfm_regmask_clr()\fR function is used to clear bit \fBb\fR in the bitmask \fBmask\fR. The \fBpfm_regmask_isset()\fR function returns a non-zero value if \fBb\fR is set in the bitmask \fBmask\fR. The \fBpfm_regmask_weight()\fR function returns in \fBw\fR the number of bits set in the bitmask \fBmask\fR. The \fBpfm_regmask_eq()\fR function returns a non-zero value if the bitmasks \fBmask1\fR and \fBmask2\fR are identical. The \fBpfm_regmask_and()\fR function returns in bitmask \fBdest\fR the result of the logical AND operation between bitmask \fBm1\fR and bitmask \fBm2\fR. The \fBpfm_regmask_or()\fR function returns in bitmask \fBdest\fR the result of the logical OR operation between bitmask \fBm1\fR and bitmask \fBm2\fR. The \fBpfm_regmask_copy()\fR function copies bitmask \fBsrc\fR into bitmask \fRdest\fR. .SH RETURN The function returns whether or not it was successful. A return value of \fBPFMLIB_SUCCESS\fR indicates success, otherwise the value is the error code. .SH ERRORS .B PFMLIB_ERR_INVAL the bit \fBb\fR exceeds the limit supported by the library .SH AUTHOR Stephane Eranian .PP papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_get_event_code_counter.30000644000307100002310000000003613013651447024354 0ustar yarkhangraduate.so man3/pfm_get_event_name.3 papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_get_cycle_event.30000644000307100002310000000407313013651447023007 0ustar yarkhangraduate.TH LIBPFM 3 "September, 2006" "" "Linux Programmer's Manual" .SH NAME pfm_get_cycle_event, pfm_get_inst_retired_event - get basic event descriptors .SH SYNOPSIS .nf .B #include .sp .BI "int pfm_get_cycle_event(pfmlib_event_t *"ev ");" .BI "int pfm_get_inst_retired_event(pfmlib_event_t *"ev ");" .sp .SH DESCRIPTION In order to build very simple generic examples that work across all PMU models, the library provides a way to retrieve information about two basic events that are present in most PMU models: cycles and instruction retired. The first event, cycles, counts the number of elapsed cycles. The second event, instruction retired, counts the number of instructions that have executed and retired from the processor pipeline. Depending on the PMU model, there may be variations in the exact definition of those events. The library provides this information on a best effort basis. User must refer to PMU model specific documentation to validate the event definition. .sp The \fBpfm_get_cycle_event()\fR function returns in \fBev\fR the event and optional unit mask descriptors for the event that counts elapsed cycles. Depending on the PMU model, there may be unit mask(s) necessary to count cycles. Application must check the value returned in \fBev->num_masks\fR. .sp The \fBpfm_get_inst_retired_event()\fR function returns in \fBev\fR the event and optional unit mask descriptors for the event that counts the number of returned instruction. Depending on the PMU model, there may be unit mask(s) necessary to count retired instructions. Application must check the value returned in \fBev->num_masks\fR. .SH RETURN All functions return whether or not the call was successful. A return value of \fBPFMLIB_SUCCESS\fR indicates success, otherwise the value is the error code. .SH ERRORS .B PFMLIB_ERR_NOINIT the library has not been initialized properly. .TP .B PFMLIB_ERR_INVAL the \fBev\fR parameter is NULL. .TP .B PFMLIB_ERR_NOTSUPP the host PMU does not define an event to count cycles or instructions retired. .TP .SH AUTHOR Stephane Eranian .PP papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_regmask_clr.30000644000307100002310000000003313013651447022131 0ustar yarkhangraduate.so man3/pfm_regmask_set.3 papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_regmask_isset.30000644000307100002310000000003313013651447022500 0ustar yarkhangraduate.so man3/pfm_regmask_set.3 papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_dispatch_events.30000644000307100002310000002510413013651447023031 0ustar yarkhangraduate.TH LIBPFM 3 "July , 2003" "" "Linux Programmer's Manual" .SH NAME pfm_dispatch_events \- determine PMC registers values for a set of events to measure .SH SYNOPSIS .nf .B #include .sp .BI "int pfm_dispatch_events(pfmlib_input_param_t *"p ", void *" mod_in ", pfmlib_output_param_t *" q, "void *" mod_out ");" .sp .SH DESCRIPTION This function is the central piece of the library. It is important to understand that the library does not effectively program the PMU, i.e., it does not make the operating system calls. The PMU is never actually accessed by the library. Instead, the library helps applications prepare the arguments to pass to the kernel. In particular, it sets up the values to program into the PMU configuration registers (PMC). The list of used data registers (PMD) is also returned. .sp The input argument are divided into two categories: the generic arguments in \fBp\fR and the optional PMU model specific arguments in \fBmod_in\fR. The same applies for the output arguments: \fBq\fR contains the generic output arguments and \fBmod_out\fR the optional PMU model specific arguments. .sp An application describes what it wants to measure in the \fBin\fR and if it uses some model specific features, such as opcode matching on Itanium 2 processors, it must pass a pointer to the relevant model-specific input parameters in \fBmod_in\fR. The generic output parameters contains the register index and values for the PMC and PMD registers needed to make the measurement. The index mapping is guaranteed to match the mapping used by the Linux perfmon2 interface. In case the library is not used on this system, the hardware register addresses or indexes can also be retrieved from the output structure. .sp The \fBpfmlib_input_param_t\fR structure is defined as follows: .sp .nf typedef struct int event; unsigned int plm; unsigned long flags; unsigned int unit_masks[PFMLIB_MAX_MASKS_PER_EVENT]; unsigned int num_masks; } pfmlib_event_t; typedef struct { unsigned int pfp_event_count; unsigned int pfp_dfl_plm; unsigned int pfp_flags; pfmlib_event_t pfp_events[PFMLIB_MAX_PMCS]; pfmlib_regmask_t pfp_unavail_pmcs; } pfmlib_input_param_t; .fi .sp The structure mostly contains one table, called \fBpfp_events\fR which describes the events to be measured. The number of submitted events is indicated by \fBpfp_event_count\fR. Each event is described in the \fBpfp_events\fR table by an opaque descriptor stored in the \fBevent\fR field. This descriptor is obtained with the \fBpfm_find_full_event()\fR or derivative functions. For some events, it may be necessary to specify at least one unit mask in the \fBunit_masks\fR table. A unit mask is yet another opaque descriptor obtained via the \fBpfm_find_event_mask()\fR or \fBpfm_find_full_event()\fR functions. Typically, if an event supports multiple unit masks, they can be combined in which case more than one entry in \fBunit_masks\fR must be specified. The actual number of unit mask descriptors passed must be indicated in \fBnum_masks\fR. When no unit mask is used, this field must be set to 0. A privilege level mask for the event can be provided in \fBplm\fR. This is a bitmask where each bit indicates a privilege level at which to monitor, more than one bit can be set. The library supports up to four levels, but depending on the PMU model, some levels may not be available. The levels are as follows: .TP .B PFM_PLM0 monitor at the privilege level 0. For many architectures, this means kernel level .TP .B PFM_PLM1 monitor at privilege level 1 .TP .B PFM_PLM2 monitor at privilege level 2 .TP .B PFM_PLM3 monitor at the privilege level 3. For many architectures, this means user level .LP .sp .sp Events with a \fBplm\fR value of 0 will use the default privilege level mask as indicated by \fBpfp_dfl_plm\fR which must be set to any combinations of values described above. It is illegal to have a value of 0 for this field. .sp The \fBpfp_flags\fR field contains a set of flags that affect the whole set of events to be monitored. The currently defined flags are: .TP .B PFMLIB_PFP_SYSTEMWIDE indicates that the monitors are to be used in a system-wide monitoring session. This could influence the way the library sets up some register values. .sp .LP The \fBpfp_unavail_pmcs\fR bitmask can be used by applications to communicate to the library the list of PMC registers which are not available on the system. Some kernels may allocate certain PMC registers (and associated data registers) for other purposes. Those registers must not be used by the library otherwise the assignment of events to PMC registers may be rejected by the kernel. Applications must figure out which registers are available using a kernel interface at their disposal, the library does not provide this service. The library expect the restrictions to be expressed using the Linux perfmon2 PMC register mapping. .LP Refer to the PMU specific manual for a description of the model-specific input parameters to be passed in \fBmod_in\fR. The generic output parameters are contained in the fBpfmlib_output_param_t\fR structure which is defined as: .sp .nf typedef struct { unsigned long long reg_value; unsigned int reg_num; unsigned long reg_addr; } pfmlib_reg_t; typedef struct { unsigned int pfp_pmc_count; unsigned int pfp_pmd_count; pfmlib_reg_t pfp_pmcs[PFMLIB_MAX_PMCS]; pfmlib_reg_t pfp_pmds[PFMLIB_MAX_PMDS]; } pfmlib_output_param_t; .fi .sp The number of valid entries in the \fBpfp_pmcs\fR table is indicated by \fBpfp_pmc_count\fR. The number of valid entries in the \fBpfp_pmds\fR table is indicated by \fBpfp_pmd_count\fR. Each entry in both tables is of type \fBpfmlib_reg_t\fR. .sp In the \fBpfp_pmcs\fR table, the \fBreg_num\fR contains the PMC register index (perfmon2 mapping), and the \fBreg_value\fR contains a 64-bit value to be used to program the PMC register. The \fBreg_addr\fR indicates the hardware address or index for the PMC register. .sp In the \fBpfp_pmds\fR table, the \fBreg_num\fR contains the PMD register index (perfmon2 mapping). the \fBreg_value\fR is ignored. The \fBreg_addr\fR indicates the hardware address or index for the PMC register. .sp Refer to the PMU specific manual for a description of the model-specific output parameters to be returned in \fBmod_out\fR. .sp The current implementation of the \fBpfm_dispatch_events()\fR function completely overwrites the \fBpfmlib_output_param\fR structure. In other words, results do not accumulate into the \fBpfp_pmcs\fR table across multiple calls. Unused fields are guaranteed to be zeroed upon successful return. .sp Depending on the PMU model, there may not always be a one to one mapping between a PMC register and a data register. Register dependencies may be more intricate. However the \fBpfm_dispatch_events()\fR function guarantees certain ordering between the \fBpfp_pmcs\fR and \fBpfp_pmds\fR tables. In particular, it guarantees that the \fBpfp_pmds\fR table always starts with the counters corresponding, in the same order, to the events as provided in the \fBpfp_event\fR table on input. There is always one counter per event. Additional PMD registers, if any, come after. .SH EXAMPLE Here is a typical sequence using the perfmon2 interface: .nf #include ... pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfarg_ctx_t ctx; pfarg_pmd_t pd[1]; pfarg_pmc_t pc[1]; pfarg_load_t load_arg; int fd, i; int ret; if (pfm_initialize() != PFMLIB_SUCCESS) { fprintf(stderr, "can't initialize library\\n"); exit(1); } memset(&ctx,0, sizeof(ctx)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(pd, 0, sizeof(pd)); memset(pc, 0, sizeof(pc)); memset(&load_arg, 0, sizeof(load_arg)); ret = pfm_get_cycle_event(&inp.pfp_events[0]); if (ret != PFMLIB_SUCCESS) { fprintf(stderr, "cannot find cycle event\\n"); exit(1); } inp.pfp_dfl_plm = PFM_PLM3; inp.pfp_event_count = 1; ret = pfm_dispatch_events(&inp, NULL, &outp, NULL); if (ret != PFMLIB_SUCCESS) { fprintf(stderr, "cannot dispatch events: %s\\n", pfm_strerror(ret)); exit(1); } /* propagate pmc value to perfmon2 structures */ for(i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } for(i=0; i < outp.pfp_pmd_count; i++) { pd[i].reg_num = outp.pfp_pmds[i].reg_num; pd[i].reg_value = 0; } ... if (pfm_create_context(&ctx, NULL, 0) == -1 ) { ... } fd = ctx.ctx_fd; if (pfm_write_pmcs(fd, pc, outp.pfp_pmc_count) == -1) { ... } if (pfm_write_pmds(fd, pd, outp.pfp_pmd_count) == -1) { ... } load_arg.load_pid = getpid(); if (pfm_load_context(fd, &load_arg) == -1) { ... } pfm_start(fd, NULL); /* code to monitor */ pfm_stop(fd); if (pfm_read_pmds(fd, pd, evt.pfp_event_count) == -1) { ... } printf("results: %llu\n", pd[0].reg_value); ... close(fd); ... .fi .SH RETURN The function returns whether or not the call was successful. A return value of \fBPFMLIB_SUCCESS\fR indicates success, otherwise the value is the error code. .SH ERRORS .B PFMLIB_ERR_NOINIT The library has not been initialized properly. .TP .B PFMLIB_ERR_INVAL Some arguments were invalid. For instance the value of *count is zero. This can also be due to he content of the \fBpfmlib_param_t\fR structure. .TP .B PFMLIB_ERR_NOTFOUND No matching event was found. .TP .B PFMLIB_ERR_TOOMANY The number of events to monitor exceed the number of implemented counters. .TP .B PFMLIB_ERR_NOASSIGN The events cannot be dispatched to the PMC because events have conflicting constraints. .TP .B PFMLIB_ERR_MAGIC The model specific extension does not have the right magic number. .TP .B PFMLIB_ERR_FEATCOMB The set of events and features cannot be combined. .TP .B PFMLIB_ERR_EVTMANY An event has been supplied more than once and is causing resource (PMC) conflicts. .TP .B PFMLIB_ERR_IRRINVAL Invalid code range restriction (Itanium, Itanium 2). .TP .B PFMLIB_ERR_IRRALIGN Code range has invalid alignment (Itanium, Itanium 2). .TP .B PFMLIB_ERR_IRRTOOMANY Cannot satisfy all the code ranges (Itanium, Itanium 2). .TP .B PFMLIB_ERR_DRRTOOMANY Cannot satisfy all the data ranges (Itanium, Itanium 2). .TP .B PFMLIB_ERR_DRRINVAL Invalid data range restriction (Itanium, Itanium 2). .TP .B PFMLIB_ERR_EVTSET Some events belong to incompatible sets (Itanium 2). .TP .B PFMLIB_ERR_EVTINCOMP Some events cannot be measured at the same time (Itanium 2). .TP .B PFMLIB_ERR_IRRTOOBIG Code range is too big (Itanium 2). .TP .B PFMLIB_ERR_UMASK Invalid or missing unit mask. .SH SEE ALSO libpfm_itanium(3), libpfm_itanium2(3), pfm_regmask_set(3), pfm_regmask_clr(3), pfm_find_event_code_mask(3) .SH AUTHOR Stephane Eranian .PP papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_get_impl_pmds.30000644000307100002310000000003513013651447022465 0ustar yarkhangraduate.so man3/pfm_get_impl_pmcs.3 papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_get_num_pmds.30000644000307100002310000000003513013651447022323 0ustar yarkhangraduate.so man3/pfm_get_impl_pmcs.3 papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_get_pmu_name_bytype.30000644000307100002310000000003413013651447023675 0ustar yarkhangraduate.so man3/pfm_get_pmu_name.3 papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_get_inst_retired.30000644000307100002310000000003713013651447023176 0ustar yarkhangraduate.so man3/pfm_get_cycle_event.3 papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_regmask_copy.30000644000307100002310000000003313013651447022323 0ustar yarkhangraduate.so man3/pfm_regmask_set.3 papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_get_num_pmcs.30000644000307100002310000000003513013651447022322 0ustar yarkhangraduate.so man3/pfm_get_impl_pmcs.3 papi-5.5.1/src/libpfm-3.y/docs/man3/libpfm_itanium2.30000644000307100002310000005646713013651447022105 0ustar yarkhangraduate.TH LIBPFM 3 "November, 2003" "" "Linux Programmer's Manual" .SH NAME libpfm_itanium2 - support for Itanium2 specific PMU features .SH SYNOPSIS .nf .B #include .B #include .sp .BI "int pfm_ita2_is_ear(unsigned int " i ");" .BI "int pfm_ita2_is_dear(unsigned int " i ");" .BI "int pfm_ita2_is_dear_tlb(unsigned int " i ");" .BI "int pfm_ita2_is_dear_cache(unsigned int " i ");" .BI "int pfm_ita2_is_dear_alat(unsigned int " i ");" .BI "int pfm_ita2_is_iear(unsigned int " i ");" .BI "int pfm_ita2_is_iear_tlb(unsigned int " i ");" .BI "int pfm_ita2_is_iear_cache(unsigned int " i ");" .BI "int pfm_ita2_is_btb(unsigned int " i ");" .BI "int pfm_ita2_support_opcm(unsigned int " i ");" .BI "int pfm_ita2_support_iarr(unsigned int " i ");" .BI "int pfm_ita2_support_darr(unsigned int " i ");" .BI "int pfm_ita2_get_event_maxincr(unsigned int "i ", unsigned int *"maxincr ");" .BI "int pfm_ita2_get_event_umask(unsigned int "i ", unsigned long *"umask ");" .BI "int pfm_ita2_get_event_group(unsigned int "i ", int *"grp ");" .BI "int pfm_ita2_get_event_set(unsigned int "i ", int *"set ");" .BI "int pfm_ita2_get_ear_mode(unsigned int "i ", pfmlib_ita2_ear_mode_t *"mode ");" .BI "int pfm_ita2_irange_is_fine(pfmlib_output_param_t *"outp ", pfmlib_ita2_output_param_t *"mod_out ");" .sp .SH DESCRIPTION The libpfm library provides full support for all the Itanium 2 specific features of the PMU. The interface is defined in \fBpfmlib_itanium2.h\fR. It consists of a set of functions and structures which describe and allow access to the Itanium 2 specific PMU features. .sp The Itanium 2 specific functions presented here are mostly used to retrieve the characteristics of an event. Given a opaque event descriptor, obtained by the \fBpfm_find_event()\fR or its derivative functions, they return a boolean value indicating whether this event support this feature or is of a particular kind. .sp The \fBpfm_ita2_is_ear()\fR function returns 1 if the event designated by \fBi\fR corresponds to a EAR event, i.e., an Event Address Register type of events. Otherwise 0 is returned. For instance, \fBDATA_EAR_CACHE_LAT4\fR is an ear event, but \fBCPU_CYCLES\fR is not. It can be a data or instruction EAR event. .sp The \fBpfm_ita2_is_dear()\fR function returns 1 if the event designated by \fBi\fR corresponds to an Data EAR event. Otherwise 0 is returned. It can be a cache or TLB EAR event. .sp The \fBpfm_ita2_is_dear_tlb()\fR function returns 1 if the event designated by \fBi\fR corresponds to a Data EAR TLB event. Otherwise 0 is returned. .sp The \fBpfm_ita2_is_dear_cache()\fR function returns 1 if the event designated by \fBi\fR corresponds to a Data EAR cache event. Otherwise 0 is returned. .sp The \fBpfm_ita2_is_dear_alat()\fR function returns 1 if the event designated by \fBi\fR corresponds to a ALAT EAR cache event. Otherwise 0 is returned. .sp The \fBpfm_ita2_is_iear()\fR function returns 1 if the event designated by \fBi\fR corresponds to an instruction EAR event. Otherwise 0 is returned. It can be a cache or TLB instruction EAR event. .sp The \fBpfm_ita2_is_iear_tlb()\fR function returns 1 if the event designated by \fBi\fR corresponds to an instruction EAR TLB event. Otherwise 0 is returned. .sp The \fBpfm_ita2_is_iear_cache()\fR function returns 1 if the event designated by \fBi\fR corresponds to an instruction EAR cache event. Otherwise 0 is returned. .sp The \fBpfm_ita2_support_opcm()\fR function returns 1 if the event designated by \fBi\fR supports opcode matching, i.e., can this event be measured accurately when opcode matching via PMC8/PMC9 is active. Not all events supports this feature. .sp The \fBpfm_ita2_support_iarr()\fR function returns 1 if the event designated by \fBi\fR supports code address range restrictions, i.e., can this event be measured accurately when code range restriction is active. Otherwise 0 is returned. Not all events supports this feature. .sp The \fBpfm_ita2_support_darr()\fR function returns 1 if the event designated by \fBi\fR supports data address range restrictions, i.e., can this event be measured accurately when data range restriction is active. Otherwise 0 is returned. Not all events supports this feature. .sp The \fBpfm_ita2_get_event_maxincr()\fR function returns in \fBmaxincr\fR the maximum number of occurrences per cycle for the event designated by \fBi\fR. Certain Itanium 2 events can occur more than once per cycle. When an event occurs more than once per cycle, the PMD counter will be incremented accordingly. It is possible to restrict measurement when event occur more than once per cycle. For instance, \fBNOPS_RETIRED\fR can happen up to 6 times/cycle which means that the threshold can be adjusted between 0 and 5, where 5 would mean that the PMD counter would be incremented by 1 only when the nop instruction is executed more than 5 times/cycle. This function returns the maximum number of occurrences of the event per cycle, and is the non-inclusive upper bound for the threshold to program in the PMC register. .sp The \fBpfm_ita2_get_event_umask()\fR function returns in \fBumask\fR the umask for the event designated by \fBi\fR. .sp The \fBpfm_ita2_get_event_grp()\fR function returns in \fBgrp\fR the group to which the event designated by \fBi\fR belongs. The notion of group is used for L1 and L2 cache events only. For all other events, a group is irrelevant and can be ignored. If the event is an L2 cache event then the value of \fBgrp\fR will be \fBPFMLIB_ITA2_EVT_L2_CACHE_GRP\fR. Similarly, if the event is an L1 cache event, the value of \fBgrp\fR will be \fBPFMLIB_ITA2_EVT_L1_CACHE_GRP\fR. In any other cases, the value of \fBgrp\fR will be \fBPFMLIB_ITA2_EVT_NO_GRP\fR. .sp The \fBpfm_ita2_get_event_set()\fR function returns in \fBset\fR the set to which the event designated by \fBi\fR belongs. A set is a subdivision of a group and is therefore only relevant for L1 and L2 cache events. An event can only belong to one group and one set. This partitioning of the cache events is due to some hardware limitations which impose some restrictions on events. For a given group, events from different sets cannot be measured at the same time. If the event does not belong to a group then the value of \fBset\fR is \fBPFMLIB_MONT_EVT_NO_SET\fR. .sp The \fBpfm_ita2_irange_is_fine()\fR function returns 1 if the configuration description passed in \fBoutp\fR, the generic output parameters and \fBmod_out\fR, the Itanium2 specific output parameters, use code range restriction in fine mode. Otherwise the function returns 0. This function can only be called after a call to the \fBpfm_dispatch_events()\fR function returns successfully and had the data structures pointed to by \fBoutp\fR and \fBmod_out\fR as output parameters. .sp The \fBpfm_ita2_get_event_ear_mode()\fR function returns in \fBmode\fR the EAR mode of the event designated by \fBi\fR. If the event is not an EAR event, then \fBPFMLIB_ERR_INVAL\fR is returned and mode is not updated. Otherwise mode can have the following values: .TP .B PFMLIB_ITA2_EAR_TLB_MODE The event is an EAR TLB mode. It can be either data or instruction TLB EAR. .TP .B PFMLIB_ITA2_EAR_CACHE_MODE The event is a cache EAR. It can be either data or instruction cache EAR. .TP .B PFMLIB_ITA2_EAR_ALAT_MODE The event is an ALAT EAR. It can only be a data EAR event. .sp .LP When the Itanium 2 specific features are needed to support a measurement their descriptions must be passed as model-specific input arguments to the \fBpfm_dispatch_events()\fR function. The Itanium 2 specific input arguments are described in the \fBpfmlib_ita2_input_param_t\fR structure and the output parameters in \fBpfmlib_ita2_output_param_t\fR. They are defined as follows: .sp .nf typedef enum { PFMLIB_ITA2_ISM_BOTH=0, PFMLIB_ITA2_ISM_IA32=1, PFMLIB_ITA2_ISM_IA64=2 } pfmlib_ita2_ism_t; typedef struct { unsigned int flags; unsigned int thres; pfmlib_ita2_ism_t ism; } pfmlib_ita2_counter_t; typedef struct { unsigned char opcm_used; unsigned long pmc_val; } pfmlib_ita2_opcm_t; typedef struct { unsigned char btb_used; unsigned char btb_ds; unsigned char btb_tm; unsigned char btb_ptm; unsigned char btb_ppm; unsigned char btb_brt; unsigned int btb_plm; } pfmlib_ita2_btb_t; typedef enum { PFMLIB_ITA2_EAR_CACHE_MODE= 0, PFMLIB_ITA2_EAR_TLB_MODE = 1, PFMLIB_ITA2_EAR_ALAT_MODE = 2 } pfmlib_ita2_ear_mode_t; typedef struct { unsigned char ear_used; pfmlib_ita2_ear_mode_t ear_mode; pfmlib_ita2_ism_t ear_ism; unsigned int ear_plm; unsigned long ear_umask; } pfmlib_ita2_ear_t; typedef struct { unsigned int rr_plm; unsigned long rr_start; unsigned long rr_end; } pfmlib_ita2_input_rr_desc_t; typedef struct { unsigned long rr_soff; unsigned long rr_eoff; } pfmlib_ita2_output_rr_desc_t; typedef struct { unsigned int rr_flags; pfmlib_ita2_input_rr_desc_t rr_limits[4]; unsigned char rr_used; } pfmlib_ita2_input_rr_t; typedef struct { unsigned int rr_nbr_used; pfmlib_ita2_output_rr_desc_t rr_infos[4]; pfmlib_reg_t rr_br[8]; } pfmlib_ita2_output_rr_t; typedef struct { pfmlib_ita2_counter_t pfp_ita2_counters[PMU_ITA2_NUM_COUNTERS]; unsigned long pfp_ita2_flags; pfmlib_ita2_opcm_t pfp_ita2_pmc8; pfmlib_ita2_opcm_t pfp_ita2_pmc9; pfmlib_ita2_ear_t pfp_ita2_iear; pfmlib_ita2_ear_t pfp_ita2_dear; pfmlib_ita2_btb_t pfp_ita2_btb; pfmlib_ita2_input_rr_t pfp_ita2_drange; pfmlib_ita2_input_rr_t pfp_ita2_irange; } pfmlib_ita2_input_param_t; typedef struct { pfmlib_ita2_output_rr_t pfp_ita2_drange; pfmlib_ita2_output_rr_t pfp_ita2_irange; } pfmlib_ita2_output_param_t; .fi .sp .SH PER-EVENT OPTIONS .sp The Itanium 2 processor provides two additional per-event features for counters: thresholding and instruction set selection. They can be set using the \fBpfp_ita2_counters\fR data structure for each event. The \fBism\fR field can be initialized as follows: .TP .B PFMLIB_ITA2_ISM_BOTH The event will be monitored during IA-64 and IA-32 execution .TP .B PFMLIB_ITA2_ISM_IA32 The event will only be monitored during IA-32 execution .TP .B PFMLIB_ITA2_ISM_IA64 The event will only be monitored during IA-64 execution .sp .LP If \fBism\fR has a value of zero, it will default to PFMLIB_ITA2_ISM_BOTH. The \fBthres\fR indicates the threshold for the event. A threshold of \fBn\fR means that the counter will be incremented by one only when the event occurs more than \fBn\fR times per cycle. The \fBflags\fR field contains event-specific flags. The currently defined flags are: .sp .TP PFMLIB_ITA2_FL_EVT_NO_QUALCHECK When this flag is set it indicates that the library should ignore the qualifiers constraints for this event. Qualifiers includes opcode matching, code and data range restrictions. When an event is marked as not supporting a particular qualifier, it usually means that it is ignored, i.e., the extra level of filtering is ignored. For instance, the CPU_CYCLES event does not support code range restrictions and by default the library will refuse to program it if range restriction is also requested. Using the flag will override the check and the call to the \fBpfm_dispatch_events()\fR function will succeed. In this case, CPU_CYCLES will be measured for the entire program and not just for the code range requested. For certain measurements this is perfectly acceptable as the range restriction will only be applied relevant to events which support it. Make sure you understand which events do not support certain qualifiers before using this flag. .LP .SH OPCODE MATCHING .sp The \fBpfp_ita2_pmc8\fR and \fBpfp_ita2_pmc9\fR fields of type \fBpfmlib_ita2_opcm_t\fR contain the description of what to do with the opcode matchers. Itanium 2 supports opcode matching via PMC8 and PMC9. When this feature is used the \fBopcm_used\fR field must be set to 1, otherwise it is ignored by the library. The \fBpmc_val\fR simply contains the raw value to store in PMC8 or PMC9. The library may adjust the value to enable/disable some options depending on the set of features being used. The final value for PMC8 and PMC9 will be stored in the \fBpfp_pmcs\fR table of the generic output parameters. .SH EVENT ADDRESS REGISTERS .sp The \fBpfp_ita2_iear\fR field of type \fBpfmlib_ita2_ear_t\fR describes what to do with instruction Event Address Registers (I-EARs). Again if this feature is used the \fBear_used\fR must be set to 1, otherwise it will be ignored by the library. The \fBear_mode\fR must be set to either one of \fBPFMLIB_ITA2_EAR_TLB_MODE\fR, \fBPFMLIB_ITA2_EAR_CACHE_MODE\fRto indicate the type of EAR to program. The umask to store into PMC10 must be in \fBear_umask\fR. The privilege level mask at which the I-EAR will be monitored must be set in \fBear_plm\fR which can be any combination of \fBPFM_PLM0\fR, \fBPFM_PLM1\fR, \fBPFM_PLM2\fR, \fBPFM_PLM3\fR. If \fBear_plm\fR is 0 then the default privilege level mask in \fBpfp_dfl_plm\fR is used. Finally the instruction set for which to monitor is in \fBear_ism\fR and can be any one of \fBPFMLIB_ITA2_ISM_BOTH\fR, \fBPFMLIB_ITA2_ISM_IA32\fR, or \fBPFMLIB_ITA2_ISM_IA64\fR. .sp The \fBpfp_ita2_dear\fR field of type \fBpfmlib_ita2_ear_t\fR describes what to do with data Event Address Registers (D-EARs). The description is identical to the I-EARs except that it applies to PMC11 and that a \fBear_mode\fR of \fBPFMLIB_ITA2_EAR_ALAT_MODE\fR is possible. In general, there are four different methods to program the EAR (data or instruction): .TP .B Method 1 There is an EAR event in the list of events to monitor and \fBear_used\fR is cleared. In this case the EAR will be programmed (PMC10 or PMC11) based on the information encoded in the event. A counting monitor (PMC4/PMD4-PMC7/PMD7) will be programmed to count \fBDATA_EAR_EVENT\fR or \fBL1I_EAR_EVENTS\fR depending on the type of EAR. .TP .B Method 2 There is an EAR event in the list of events to monitor and \fBear_used\fR is set. In this case the EAR will be programmed (PMC10 or PMC11) using the information in the \fBpfp_ita2_iear\fR or \fBpfp_ita2_dear\fR structure because it contains more detailed information, such as privilege level and instruction set. A counting monitor (PMC4/PMD4-PMC7/PMD7) will be programmed to count DATA_EAR_EVENT or L1I_EAR_EVENTS depending on the type of EAR. .TP .B Method 3 There is no EAR event in the list of events to monitor and and \fBear_used\fR is cleared. In this case no EAR is programmed. .TP .B Method 4 There is no EAR event in the list of events to monitor and and \fBear_used\fR is set. In this case case the EAR will be programmed (PMC10 or PMC11) using the information in the \fBpfp_ita2_iear\fR or \fBpfp_ita2_dear\fR structure. This is the free running mode for the EAR. .sp .SH BRANCH TRACE BUFFER The \fBpfp_ita2_btb\fR of type \fBpfmlib_ita2_btb_t\fR field is used to configure the Branch Trace Buffer (BTB). If the \fBbtb_used\fR is set, then the library will take the configuration into account, otherwise any BTB configuration will be ignored. The various fields in this structure provide means to filter out the kind of branches that gets recorded in the BTB. Each one represents an element of the branch architecture of the Itanium 2 processor. Refer to the Itanium 2 specific documentation for more details on the branch architecture. The fields are as follows: .TP .B btb_ds If the value of this field is 1, then detailed information about the branch prediction are recorded in place of information about the target address. If the value is 0, then information about the target address of the branch is recorded instead. .TP .B btb_tm If this field is 0, then no branch is captured. If this field is 1, then non taken branches are captured. If this field is 2, then taken branches are captured. Finally if this field is 3 then all branches are captured. .TP .B btb_ptm If this field is 0, then no branch is captured. If this field is 1, then branches with a mispredicted target address are captured. If this field is 2, then branches with correctly predicted target address are captured. Finally if this field is 3 then all branches are captured regardless of target address prediction. .TP .B btb_ppm If this field is 0, then no branch is captured. If this field is 1, then branches with a mispredicted path (taken/non taken) are captured. If this field is 2, then branches with correctly predicted path are captured. Finally if this field is 3 then all branches are captured regardless of their path prediction. .TP .B btb_brt If this field is 0, then all branches are captured. If this field is 1, then only IP-relative branches are captured. If this field is 2, then only return branches are captured. Finally if this field is 3 then only non-return indirect branches are captured. .TP .B btb_plm This is the privilege level mask at which the BTB captures branches. It can be any combination of \fBPFM_PLM0\fR, \fBPFM_PLM1\fR, \fBPFM_PLM2\fR, \fBPFM_PLM3\fR. If \fBbtb_plm\fR is 0 then the default privilege level mask in \fBpfp_dfl_plm\fR is used. .sp There are 4 methods to program the BTB and they are as follows: .sp .TP .B Method 1 The \fBBRANCH_EVENT\fR is in the list of event to monitor and \fBbtb_used\fR is cleared. In this case, the BTB will be configured (PMC12) to record ALL branches. A counting monitor (PMC4/PMD4-PMC7/PMD7) will be programmed to count \fBBRANCH_EVENT\fR. .TP .B Method 2 The \fBBRANCH_EVENT\fR is in the list of events to monitor and \fBbtb_used\fR is set. In this case, the BTB will be configured (PMC12) using the information in the \fBpfp_ita2_btb\fR structure. A counting monitor (PMC4/PMD4-PMC7/PMD7) will be programmed to count \fBBRANCH_EVENT\fR. .TP .B Method 3 The \fBBRANCH_EVENT\fR is not in the list of events to monitor and \fBbtb_used\fR is set. In this case, the BTB will be configured (PMC12) using the information in the \fBpfp_ita2_btb\fR structure. This is the free running mode for the BTB. .TP .B Method 4 The \fBBRANCH_EVENT\fR is not in the list of events to monitor and \fBbtb_used\fR is cleared. In this case, the BTB is not programmed. .SH DATA AND CODE RANGE RESTRICTIONS The \fBpfp_ita2_drange\fR and \fBpfp_ita2_irange\fR fields control the range restrictions for the data and code respectively. The idea is that the application passes a set of ranges, each designated by a start and end address. Upon return from the \fBpfm_dispatch_events()\fR function, the application gets back the set of registers and their values that needs to be programmed via a kernel interface. Range restriction is implemented using the debug registers. There is a limited number of debug registers and they go in pair. With 8 data debug registers, a maximum of 4 distinct ranges can be specified. The same applies to code range restrictions. Moreover, there are some severe constraints on the alignment and size of the ranges. Given that the size of a range is specified using a bitmask, there can be situations where the actual range is larger than the requested range. For code ranges, the Itanium 2 processor can use what is called a fine mode, where a range is designated using two pairs of code debug registers. In this mode, the bitmask is not used, the start and end addresses are directly specified. Not all code ranges qualify for fine mode, the size of the range must be 4KB or less and the range cannot cross a 4KB page boundary. The library will make a best effort in choosing the right mode for each range. For code ranges, it will try the fine mode first and will default to using the bitmask mode otherwise. Fine mode applies to all code debug registers or none, i.e., you cannot have a range using fine mode and another using the bitmask. the Itanium 2 processor somehow limits the use of multiple pairs to accurately cover a code range. This can only be done for \fBIA64_INST_RETIRED\fR and even then, you need several events to collect the counts. For all other events, only one pair can be used, which leads to more inaccuracy due to approximation. Data ranges can used multiple debug register pairs to gain more accuracy. The library will never cover less than what is requested. The algorithm will use more than one pair of debug registers whenever possible to get a more precise range. Hence, up to the 4 pairs can be used to describe a single range. If range restriction is to be used, the \fBrr_used\fR field must be set to one, otherwise settings will be ignored. The ranges are described by the \fBpfmlib_ita2_input_rr_t\fR structure. Up to 4 ranges can be defined. Each range is described in by a entry in \fBrr_limits\fR. Some flags for all ranges can be defined in \fBrr_flags\fR. Currently defined flags are: .sp .TP .B PFMLIB_ITA2_RR_INV Inverse the code ranges. The qualifying events will be measurement when executing outside the specified ranges. .TP .B PFMLIB_ITA2_RR_NO_FINE_MODE Force non fine mode for all code ranges (mostly for debug) .sp .LP The \fBpfmlib_ita2_input_rr_desc_t\fR structure is defined as follows: .TP .B rr_plm The privilege level at which the range is active. It can be any combinations of \fBPFM_PLM0\fR, \fBPFM_PLM1\fR, \fBPFM_PLM2\fR, \fBPFM_PLM3\fR. If \fBbtb_plm\fR is 0 then the default privilege level mask in \fBpfp_dfl_plm\fR is used. The privilege level is only relevant for code ranges, data ranges ignores the setting. .TP .B rr_start This is the start address of the range. Any address is supported but for code range it must be bundle aligned, i.e., 16-byte aligned. .TP .B rr_end This is the end address of the range. Any address is supported but for code range it must be bundle aligned, i.e., 16-byte aligned. .sp .LP The library will provide the values for the debug registers as well as some information about the actual ranges in the output parameters and more precisely in the \fBpfmlib_ita2_output_rr_t\fR structure for each range. The structure is defined as follows: .TP .B rr_nbr_used Contains the number of debug registers used to cover the range. This is necessarily an even number as debug registers always go in pair. The value of this field is between 0 and 7. .TP .B rr_br This table contains the list of debug registers necessary to cover the ranges. Each element is of type \fBpfmlib_reg_t\fR. The \fBreg_num\fR field contains the debug register index while \fBreg_value\fR contains the debug register value. Both the index and value must be copied into the kernel specific argument to program the debug registers. The library never programs them. .TP .B rr_infos Contains information about the ranges defined. Because of alignment restrictions, the actual range covered by the debug registers may be larger than the requested range. This table describe the differences between the requested and actual ranges expressed as offsets: .TP .B rr_soff Contains the start offset of the actual range described by the debug registers. If zero, it means the library was able to match exactly the beginning of the range. Otherwise it represents the number of byte by which the actual range precedes the requested range. .TP .B rr_eoff Contains the end offset of the actual range described by the debug registers. If zero, it means the library was able to match exactly the end of the range. Otherwise it represents the number of bytes by which the actual range exceeds the requested range. .sp .LP .SH ERRORS Refer to the description of the \fBpfm_dispatch_events()\fR function for errors when using the Itanium 2 specific input and output arguments. .SH SEE ALSO pfm_dispatch_events(3) and set of examples shipped with the library .SH AUTHOR Stephane Eranian .PP papi-5.5.1/src/libpfm-3.y/docs/man3/pfm_get_event_mask_code.30000644000307100002310000000003613013651447023630 0ustar yarkhangraduate.so man3/pfm_get_event_name.3 papi-5.5.1/src/libpfm-3.y/lib/0000755000307100002310000000000013013651450015670 5ustar yarkhangraduatepapi-5.5.1/src/libpfm-3.y/lib/pfmlib_priv_comp.h0000644000307100002310000000312013013651450021364 0ustar yarkhangraduate/* * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #ifndef __PFMLIB_PRIV_COMP_H__ #define __PFMLIB_PRIV_COMP_H__ #include /* * this header file contains all the macros, inline assembly, instrinsics needed * by the library and which are compiler-specific */ #ifdef __ia64__ #include "pfmlib_priv_comp_ia64.h" #endif #endif papi-5.5.1/src/libpfm-3.y/lib/amd64_events.h0000644000307100002310000000466313013651450020351 0ustar yarkhangraduate/* * Copyright (c) 2006, 2007 Advanced Micro Devices, Inc. * Contributed by Ray Bryant * Contributed by Robert Richter * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #include "amd64_events_k7.h" #include "amd64_events_k8.h" #include "amd64_events_fam10h.h" #include "amd64_events_fam15h.h" struct pme_amd64_table { unsigned int num; pme_amd64_entry_t *events; unsigned int cpu_clks; unsigned int ret_inst; }; static struct pme_amd64_table amd64_k7_table = { .num = PME_AMD64_K7_EVENT_COUNT, .events = amd64_k7_pe, .cpu_clks = PME_AMD64_K7_CPU_CLK_UNHALTED, .ret_inst = PME_AMD64_K7_RETIRED_INSTRUCTIONS, }; static struct pme_amd64_table amd64_k8_table = { .num = PME_AMD64_K8_EVENT_COUNT, .events = amd64_k8_pe, .cpu_clks = PME_AMD64_K8_CPU_CLK_UNHALTED, .ret_inst = PME_AMD64_K8_RETIRED_INSTRUCTIONS, }; static struct pme_amd64_table amd64_fam10h_table = { .num = PME_AMD64_FAM10H_EVENT_COUNT, .events = amd64_fam10h_pe, .cpu_clks = PME_AMD64_FAM10H_CPU_CLK_UNHALTED, .ret_inst = PME_AMD64_FAM10H_RETIRED_INSTRUCTIONS, }; static struct pme_amd64_table amd64_fam15h_table = { .num = PME_AMD64_FAM15H_EVENT_COUNT, .events = amd64_fam15h_pe, .cpu_clks = PME_AMD64_FAM15H_CPU_CLK_UNHALTED, .ret_inst = PME_AMD64_FAM15H_RETIRED_INSTRUCTIONS, }; papi-5.5.1/src/libpfm-3.y/lib/core_events.h0000644000307100002310000012141413013651450020360 0ustar yarkhangraduate/* * Copyright (c) 2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #define INTEL_CORE_MESI_UMASKS \ { .pme_uname = "MESI",\ .pme_udesc = "Any cacheline access (default)",\ .pme_ucode = 0xf\ },\ { .pme_uname = "I_STATE",\ .pme_udesc = "Invalid cacheline",\ .pme_ucode = 0x1\ },\ { .pme_uname = "S_STATE",\ .pme_udesc = "Shared cacheline",\ .pme_ucode = 0x2\ },\ { .pme_uname = "E_STATE",\ .pme_udesc = "Exclusive cacheline",\ .pme_ucode = 0x4\ },\ { .pme_uname = "M_STATE",\ .pme_udesc = "Modified cacheline",\ .pme_ucode = 0x8\ } #define INTEL_CORE_SPECIFICITY_UMASKS \ { .pme_uname = "SELF",\ .pme_udesc = "This core",\ .pme_ucode = 0x40\ },\ { .pme_uname = "BOTH_CORES",\ .pme_udesc = "Both cores",\ .pme_ucode = 0xc0\ } #define INTEL_CORE_HW_PREFETCH_UMASKS \ { .pme_uname = "ANY",\ .pme_udesc = "All inclusive",\ .pme_ucode = 0x30\ },\ { .pme_uname = "PREFETCH",\ .pme_udesc = "Hardware prefetch only",\ .pme_ucode = 0x10\ } #define INTEL_CORE_AGENT_UMASKS \ { .pme_uname = "THIS_AGENT",\ .pme_udesc = "This agent",\ .pme_ucode = 0x00\ },\ { .pme_uname = "ALL_AGENTS",\ .pme_udesc = "Any agent on the bus",\ .pme_ucode = 0x20\ } static pme_core_entry_t core_pe[]={ /* * BEGIN: architected Core events */ {.pme_name = "UNHALTED_CORE_CYCLES", .pme_code = 0x003c, .pme_flags = PFMLIB_CORE_FIXED1, .pme_desc = "count core clock cycles whenever the clock signal on the specific core is running (not halted). Alias to event CPU_CLK_UNHALTED:CORE_P" }, {.pme_name = "INSTRUCTIONS_RETIRED", .pme_code = 0x00c0, .pme_flags = PFMLIB_CORE_FIXED0, .pme_desc = "count the number of instructions at retirement. Alias to event INST_RETIRED:ANY_P", }, {.pme_name = "UNHALTED_REFERENCE_CYCLES", .pme_code = 0x013c, .pme_flags = PFMLIB_CORE_FIXED2_ONLY, .pme_desc = "Unhalted reference cycles. Alias to event CPU_CLK_UNHALTED:REF", }, {.pme_name = "LAST_LEVEL_CACHE_REFERENCES", .pme_code = 0x4f2e, .pme_desc = "count each request originating from the core to reference a cache line in the last level cache. The count may include speculation, but excludes cache line fills due to hardware prefetch. Alias to L2_RQSTS:SELF_DEMAND_MESI", }, {.pme_name = "LAST_LEVEL_CACHE_MISSES", .pme_code = 0x412e, .pme_desc = "count each cache miss condition for references to the last level cache. The event count may include speculation, but excludes cache line fills due to hardware prefetch. Alias to event L2_RQSTS:SELF_DEMAND_I_STATE", }, {.pme_name = "BRANCH_INSTRUCTIONS_RETIRED", .pme_code = 0x00c4, .pme_desc = "count branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instruction. Alias to event BR_INST_RETIRED:ANY", }, {.pme_name = "MISPREDICTED_BRANCH_RETIRED", .pme_code = 0x00c5, .pme_desc = "count mispredicted branch instructions at retirement. Specifically, this event counts at retirement of the last micro-op of a branch instruction in the architectural path of the execution and experienced misprediction in the branch prediction hardware. Alias to BR_INST_RETIRED:MISPRED", }, /* * END: architected events */ /* * BEGIN: Core 2 Duo events */ { .pme_name = "RS_UOPS_DISPATCHED_CYCLES", .pme_code = 0xa1, .pme_flags = PFMLIB_CORE_PMC0, .pme_desc = "Cycles micro-ops dispatched for execution", .pme_umasks = { { .pme_uname = "PORT_0", .pme_udesc = "on port 0", .pme_ucode = 0x1 }, { .pme_uname = "PORT_1", .pme_udesc = "on port 1", .pme_ucode = 0x2 }, { .pme_uname = "PORT_2", .pme_udesc = "on port 2", .pme_ucode = 0x4 }, { .pme_uname = "PORT_3", .pme_udesc = "on port 3", .pme_ucode = 0x8 }, { .pme_uname = "PORT_4", .pme_udesc = "on port 4", .pme_ucode = 0x10 }, { .pme_uname = "PORT_5", .pme_udesc = "on port 5", .pme_ucode = 0x20 }, { .pme_uname = "ANY", .pme_udesc = "on any port", .pme_ucode = 0x3f }, }, .pme_numasks = 7 }, { .pme_name = "RS_UOPS_DISPATCHED", .pme_code = 0xa0, .pme_desc = "Number of micro-ops dispatched for execution", }, { .pme_name = "RS_UOPS_DISPATCHED_NONE", .pme_code = 0xa0 | (1 << 23 | 1 << 24), .pme_desc = "Number of of cycles in which no micro-ops is dispatched for execution", }, { .pme_name = "LOAD_BLOCK", .pme_code = 0x3, .pme_flags = 0, .pme_desc = "Loads blocked", .pme_umasks = { { .pme_uname = "STA", .pme_udesc = "Loads blocked by a preceding store with unknown address", .pme_ucode = 0x2 }, { .pme_uname = "STD", .pme_udesc = "Loads blocked by a preceding store with unknown data", .pme_ucode = 0x4 }, { .pme_uname = "OVERLAP_STORE", .pme_udesc = "Loads that partially overlap an earlier store, or 4K aliased with a previous store", .pme_ucode = 0x8 }, { .pme_uname = "UNTIL_RETIRE", .pme_udesc = "Loads blocked until retirement", .pme_ucode = 0x10 }, { .pme_uname = "L1D", .pme_udesc = "Loads blocked by the L1 data cache", .pme_ucode = 0x20 } }, .pme_numasks = 5 }, { .pme_name = "SB_DRAIN_CYCLES", .pme_code = 0x104, .pme_flags = 0, .pme_desc = "Cycles while stores are blocked due to store buffer drain" }, { .pme_name = "STORE_BLOCK", .pme_code = 0x4, .pme_flags = 0, .pme_desc = "Cycles while store is waiting", .pme_umasks = { { .pme_uname = "ORDER", .pme_udesc = "Cycles while store is waiting for a preceding store to be globally observed", .pme_ucode = 0x2 }, { .pme_uname = "SNOOP", .pme_udesc = "A store is blocked due to a conflict with an external or internal snoop", .pme_ucode = 0x8 } }, .pme_numasks = 2 }, { .pme_name = "SEGMENT_REG_LOADS", .pme_code = 0x6, .pme_flags = 0, .pme_desc = "Number of segment register loads" }, { .pme_name = "SSE_PRE_EXEC", .pme_code = 0x7, .pme_flags = 0, .pme_desc = "Streaming SIMD Extensions (SSE) Prefetch instructions executed", .pme_umasks = { { .pme_uname = "NTA", .pme_udesc = "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed", .pme_ucode = 0x0 }, { .pme_uname = "L1", .pme_udesc = "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed", .pme_ucode = 0x1 }, { .pme_uname = "L2", .pme_udesc = "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed", .pme_ucode = 0x2 }, { .pme_uname = "STORES", .pme_udesc = "Streaming SIMD Extensions (SSE) Weakly-ordered store instructions executed", .pme_ucode = 0x3 } }, .pme_numasks = 4 }, { .pme_name = "DTLB_MISSES", .pme_code = 0x8, .pme_flags = 0, .pme_desc = "Memory accesses that missed the DTLB", .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "Any memory access that missed the DTLB", .pme_ucode = 0x1 }, { .pme_uname = "MISS_LD", .pme_udesc = "DTLB misses due to load operations", .pme_ucode = 0x2 }, { .pme_uname = "L0_MISS_LD", .pme_udesc = "L0 DTLB misses due to load operations", .pme_ucode = 0x4 }, { .pme_uname = "MISS_ST", .pme_udesc = "DTLB misses due to store operations", .pme_ucode = 0x8 } }, .pme_numasks = 4 }, { .pme_name = "MEMORY_DISAMBIGUATION", .pme_code = 0x9, .pme_flags = 0, .pme_desc = "Memory disambiguation", .pme_umasks = { { .pme_uname = "RESET", .pme_udesc = "Memory disambiguation reset cycles", .pme_ucode = 0x1 }, { .pme_uname = "SUCCESS", .pme_udesc = "Number of loads that were successfully disambiguated", .pme_ucode = 0x2 } }, .pme_numasks = 2 }, { .pme_name = "PAGE_WALKS", .pme_code = 0xc, .pme_flags = 0, .pme_desc = "Number of page-walks executed", .pme_umasks = { { .pme_uname = "COUNT", .pme_udesc = "Number of page-walks executed", .pme_ucode = 0x1 }, { .pme_uname = "CYCLES", .pme_udesc = "Duration of page-walks in core cycles", .pme_ucode = 0x2 } }, .pme_numasks = 2 }, { .pme_name = "FP_COMP_OPS_EXE", .pme_code = 0x10, .pme_flags = PFMLIB_CORE_PMC0, .pme_desc = "Floating point computational micro-ops executed" }, { .pme_name = "FP_ASSIST", .pme_code = 0x11, .pme_flags = PFMLIB_CORE_PMC1, .pme_desc = "Floating point assists" }, { .pme_name = "MUL", .pme_code = 0x12, .pme_flags = PFMLIB_CORE_PMC1, .pme_desc = "Multiply operations executed" }, { .pme_name = "DIV", .pme_code = 0x13, .pme_flags = PFMLIB_CORE_PMC1, .pme_desc = "Divide operations executed" }, { .pme_name = "CYCLES_DIV_BUSY", .pme_code = 0x14, .pme_flags = PFMLIB_CORE_PMC0, .pme_desc = "Cycles the divider is busy" }, { .pme_name = "IDLE_DURING_DIV", .pme_code = 0x18, .pme_flags = PFMLIB_CORE_PMC0, .pme_desc = "Cycles the divider is busy and all other execution units are idle" }, { .pme_name = "DELAYED_BYPASS", .pme_code = 0x19, .pme_flags = PFMLIB_CORE_PMC1, .pme_desc = "Delayed bypass", .pme_umasks = { { .pme_uname = "FP", .pme_udesc = "Delayed bypass to FP operation", .pme_ucode = 0x0 }, { .pme_uname = "SIMD", .pme_udesc = "Delayed bypass to SIMD operation", .pme_ucode = 0x1 }, { .pme_uname = "LOAD", .pme_udesc = "Delayed bypass to load operation", .pme_ucode = 0x2 } }, .pme_numasks = 3 }, { .pme_name = "L2_ADS", .pme_code = 0x21, .pme_flags = PFMLIB_CORE_CSPEC, .pme_desc = "Cycles L2 address bus is in use", .pme_umasks = { INTEL_CORE_SPECIFICITY_UMASKS }, .pme_numasks = 2 }, { .pme_name = "L2_DBUS_BUSY_RD", .pme_code = 0x23, .pme_flags = PFMLIB_CORE_CSPEC, .pme_desc = "Cycles the L2 transfers data to the core", .pme_umasks = { INTEL_CORE_SPECIFICITY_UMASKS }, .pme_numasks = 2 }, { .pme_name = "L2_LINES_IN", .pme_code = 0x24, .pme_flags = PFMLIB_CORE_CSPEC, .pme_desc = "L2 cache misses", .pme_umasks = { INTEL_CORE_SPECIFICITY_UMASKS, INTEL_CORE_HW_PREFETCH_UMASKS }, .pme_numasks = 4 }, { .pme_name = "L2_M_LINES_IN", .pme_code = 0x25, .pme_flags = PFMLIB_CORE_CSPEC, .pme_desc = "L2 cache line modifications", .pme_umasks = { INTEL_CORE_SPECIFICITY_UMASKS }, .pme_numasks = 2 }, { .pme_name = "L2_LINES_OUT", .pme_code = 0x26, .pme_flags = PFMLIB_CORE_CSPEC, .pme_desc = "L2 cache lines evicted", .pme_umasks = { INTEL_CORE_SPECIFICITY_UMASKS, INTEL_CORE_HW_PREFETCH_UMASKS }, .pme_numasks = 4 }, { .pme_name = "L2_M_LINES_OUT", .pme_code = 0x27, .pme_flags = PFMLIB_CORE_CSPEC, .pme_desc = "Modified lines evicted from the L2 cache", .pme_umasks = { INTEL_CORE_SPECIFICITY_UMASKS, INTEL_CORE_HW_PREFETCH_UMASKS }, .pme_numasks = 4 }, { .pme_name = "L2_IFETCH", .pme_code = 0x28, .pme_flags = PFMLIB_CORE_CSPEC|PFMLIB_CORE_MESI, .pme_desc = "L2 cacheable instruction fetch requests", .pme_umasks = { INTEL_CORE_MESI_UMASKS, INTEL_CORE_SPECIFICITY_UMASKS }, .pme_numasks = 7 }, { .pme_name = "L2_LD", .pme_code = 0x29, .pme_flags = PFMLIB_CORE_CSPEC|PFMLIB_CORE_MESI, .pme_desc = "L2 cache reads", .pme_umasks = { INTEL_CORE_MESI_UMASKS, INTEL_CORE_SPECIFICITY_UMASKS, INTEL_CORE_HW_PREFETCH_UMASKS }, .pme_numasks = 9 }, { .pme_name = "L2_ST", .pme_code = 0x2a, .pme_flags = PFMLIB_CORE_CSPEC|PFMLIB_CORE_MESI, .pme_desc = "L2 store requests", .pme_umasks = { INTEL_CORE_MESI_UMASKS, INTEL_CORE_SPECIFICITY_UMASKS }, .pme_numasks = 7 }, { .pme_name = "L2_LOCK", .pme_code = 0x2b, .pme_flags = PFMLIB_CORE_CSPEC|PFMLIB_CORE_MESI, .pme_desc = "L2 locked accesses", .pme_umasks = { INTEL_CORE_MESI_UMASKS, INTEL_CORE_SPECIFICITY_UMASKS }, .pme_numasks = 7 }, { .pme_name = "L2_RQSTS", .pme_code = 0x2e, .pme_flags = PFMLIB_CORE_CSPEC|PFMLIB_CORE_MESI, .pme_desc = "L2 cache requests", .pme_umasks = { INTEL_CORE_MESI_UMASKS, INTEL_CORE_SPECIFICITY_UMASKS, INTEL_CORE_HW_PREFETCH_UMASKS }, .pme_numasks = 9 }, { .pme_name = "L2_REJECT_BUSQ", .pme_code = 0x30, .pme_flags = PFMLIB_CORE_CSPEC|PFMLIB_CORE_MESI, .pme_desc = "Rejected L2 cache requests", .pme_umasks = { INTEL_CORE_MESI_UMASKS, INTEL_CORE_SPECIFICITY_UMASKS, INTEL_CORE_HW_PREFETCH_UMASKS }, .pme_numasks = 9 }, { .pme_name = "L2_NO_REQ", .pme_code = 0x32, .pme_flags = PFMLIB_CORE_CSPEC, .pme_desc = "Cycles no L2 cache requests are pending", .pme_umasks = { INTEL_CORE_SPECIFICITY_UMASKS }, .pme_numasks = 2 }, { .pme_name = "EIST_TRANS", .pme_code = 0x3a, .pme_flags = 0, .pme_desc = "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions" }, { .pme_name = "THERMAL_TRIP", .pme_code = 0xc03b, .pme_flags = 0, .pme_desc = "Number of thermal trips" }, { .pme_name = "CPU_CLK_UNHALTED", .pme_code = 0x3c, .pme_flags = PFMLIB_CORE_UMASK_NCOMBO, .pme_desc = "Core cycles when core is not halted", .pme_umasks = { { .pme_uname = "CORE_P", .pme_udesc = "Core cycles when core is not halted", .pme_ucode = 0x0, }, { .pme_uname = "REF", .pme_udesc = "Reference cycles. This event is not affected by core changes such as P-states or TM2 transitions but counts at the same frequency as the time stamp counter. This event can approximate elapsed time. This event has a constant ratio with the CPU_CLK_UNHALTED:BUS event", .pme_ucode = 0x1, .pme_flags = PFMLIB_CORE_FIXED2_ONLY /* Can only be measured on FIXED_CTR2 */ }, { .pme_uname = "BUS", .pme_udesc = "Bus cycles when core is not halted. This event can give a measurement of the elapsed time. This events has a constant ratio with CPU_CLK_UNHALTED:REF event, which is the maximum bus to processor frequency ratio", .pme_ucode = 0x1, }, { .pme_uname = "NO_OTHER", .pme_udesc = "Bus cycles when core is active and the other is halted", .pme_ucode = 0x2 } }, .pme_numasks = 4 }, { .pme_name = "L1D_CACHE_LD", .pme_code = 0x40, .pme_flags = PFMLIB_CORE_MESI, .pme_desc = "L1 cacheable data reads", .pme_umasks = { INTEL_CORE_MESI_UMASKS }, .pme_numasks = 5 }, { .pme_name = "L1D_CACHE_ST", .pme_code = 0x41, .pme_flags = PFMLIB_CORE_MESI, .pme_desc = "L1 cacheable data writes", .pme_umasks = { INTEL_CORE_MESI_UMASKS }, .pme_numasks = 5 }, { .pme_name = "L1D_CACHE_LOCK", .pme_code = 0x42, .pme_flags = PFMLIB_CORE_MESI, .pme_desc = "L1 data cacheable locked reads", .pme_umasks = { INTEL_CORE_MESI_UMASKS }, .pme_numasks = 5 }, { .pme_name = "L1D_ALL_REF", .pme_code = 0x143, .pme_flags = 0, .pme_desc = "All references to the L1 data cache" }, { .pme_name = "L1D_ALL_CACHE_REF", .pme_code = 0x243, .pme_flags = 0, .pme_desc = "L1 Data cacheable reads and writes" }, { .pme_name = "L1D_REPL", .pme_code = 0xf45, .pme_flags = 0, .pme_desc = "Cache lines allocated in the L1 data cache" }, { .pme_name = "L1D_M_REPL", .pme_code = 0x46, .pme_flags = 0, .pme_desc = "Modified cache lines allocated in the L1 data cache" }, { .pme_name = "L1D_M_EVICT", .pme_code = 0x47, .pme_flags = 0, .pme_desc = "Modified cache lines evicted from the L1 data cache" }, { .pme_name = "L1D_PEND_MISS", .pme_code = 0x48, .pme_flags = 0, .pme_desc = "Total number of outstanding L1 data cache misses at any cycle" }, { .pme_name = "L1D_SPLIT", .pme_code = 0x49, .pme_flags = 0, .pme_desc = "Cache line split from L1 data cache", .pme_umasks = { { .pme_uname = "LOADS", .pme_udesc = "Cache line split loads from the L1 data cache", .pme_ucode = 0x1 }, { .pme_uname = "STORES", .pme_udesc = "Cache line split stores to the L1 data cache", .pme_ucode = 0x2 } }, .pme_numasks = 2 }, { .pme_name = "SSE_PRE_MISS", .pme_code = 0x4b, .pme_flags = 0, .pme_desc = "Streaming SIMD Extensions (SSE) instructions missing all cache levels", .pme_umasks = { { .pme_uname = "NTA", .pme_udesc = "Streaming SIMD Extensions (SSE) Prefetch NTA instructions missing all cache levels", .pme_ucode = 0x0 }, { .pme_uname = "L1", .pme_udesc = "Streaming SIMD Extensions (SSE) PrefetchT0 instructions missing all cache levels", .pme_ucode = 0x1 }, { .pme_uname = "L2", .pme_udesc = "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions missing all cache levels", .pme_ucode = 0x2 }, }, .pme_numasks = 3 }, { .pme_name = "LOAD_HIT_PRE", .pme_code = 0x4c, .pme_flags = 0, .pme_desc = "Load operations conflicting with a software prefetch to the same address" }, { .pme_name = "L1D_PREFETCH", .pme_code = 0x4e, .pme_flags = 0, .pme_desc = "L1 data cache prefetch", .pme_umasks = { { .pme_uname = "REQUESTS", .pme_udesc = "L1 data cache prefetch requests", .pme_ucode = 0x10 } }, .pme_numasks = 1 }, { .pme_name = "BUS_REQUEST_OUTSTANDING", .pme_code = 0x60, .pme_flags = PFMLIB_CORE_CSPEC, .pme_desc = "Number of pending full cache line read transactions on the bus occurring in each cycle", .pme_umasks = { INTEL_CORE_SPECIFICITY_UMASKS, INTEL_CORE_AGENT_UMASKS }, .pme_numasks = 4 }, { .pme_name = "BUS_BNR_DRV", .pme_code = 0x61, .pme_flags = 0, .pme_desc = "Number of Bus Not Ready signals asserted", .pme_umasks = { INTEL_CORE_AGENT_UMASKS }, .pme_numasks = 2 }, { .pme_name = "BUS_DRDY_CLOCKS", .pme_code = 0x62, .pme_flags = 0, .pme_desc = "Bus cycles when data is sent on the bus", .pme_umasks = { INTEL_CORE_AGENT_UMASKS }, .pme_numasks = 2 }, { .pme_name = "BUS_LOCK_CLOCKS", .pme_code = 0x63, .pme_flags = PFMLIB_CORE_CSPEC, .pme_desc = "Bus cycles when a LOCK signal is asserted", .pme_umasks = { INTEL_CORE_SPECIFICITY_UMASKS, INTEL_CORE_AGENT_UMASKS }, .pme_numasks = 4 }, { .pme_name = "BUS_DATA_RCV", .pme_code = 0x64, .pme_flags = PFMLIB_CORE_CSPEC, .pme_desc = "Bus cycles while processor receives data", .pme_umasks = { INTEL_CORE_SPECIFICITY_UMASKS }, .pme_numasks = 2 }, { .pme_name = "BUS_TRANS_BRD", .pme_code = 0x65, .pme_flags = PFMLIB_CORE_CSPEC, .pme_desc = "Burst read bus transactions", .pme_umasks = { INTEL_CORE_SPECIFICITY_UMASKS, INTEL_CORE_AGENT_UMASKS }, .pme_numasks = 4 }, { .pme_name = "BUS_TRANS_RFO", .pme_code = 0x66, .pme_flags = PFMLIB_CORE_CSPEC, .pme_desc = "RFO bus transactions", .pme_umasks = { INTEL_CORE_SPECIFICITY_UMASKS, INTEL_CORE_AGENT_UMASKS }, .pme_numasks = 4 }, { .pme_name = "BUS_TRANS_WB", .pme_code = 0x67, .pme_flags = PFMLIB_CORE_CSPEC, .pme_desc = "Explicit writeback bus transactions", .pme_umasks = { INTEL_CORE_SPECIFICITY_UMASKS, INTEL_CORE_AGENT_UMASKS }, .pme_numasks = 4 }, { .pme_name = "BUS_TRANS_IFETCH", .pme_code = 0x68, .pme_flags = PFMLIB_CORE_CSPEC, .pme_desc = "Instruction-fetch bus transactions", .pme_umasks = { INTEL_CORE_SPECIFICITY_UMASKS, INTEL_CORE_AGENT_UMASKS }, .pme_numasks = 4 }, { .pme_name = "BUS_TRANS_INVAL", .pme_code = 0x69, .pme_flags = PFMLIB_CORE_CSPEC, .pme_desc = "Invalidate bus transactions", .pme_umasks = { INTEL_CORE_SPECIFICITY_UMASKS, INTEL_CORE_AGENT_UMASKS }, .pme_numasks = 4 }, { .pme_name = "BUS_TRANS_PWR", .pme_code = 0x6a, .pme_flags = PFMLIB_CORE_CSPEC, .pme_desc = "Partial write bus transaction", .pme_umasks = { INTEL_CORE_SPECIFICITY_UMASKS, INTEL_CORE_AGENT_UMASKS }, .pme_numasks = 4 }, { .pme_name = "BUS_TRANS_P", .pme_code = 0x6b, .pme_flags = PFMLIB_CORE_CSPEC, .pme_desc = "Partial bus transactions", .pme_umasks = { INTEL_CORE_SPECIFICITY_UMASKS, INTEL_CORE_AGENT_UMASKS }, .pme_numasks = 4 }, { .pme_name = "BUS_TRANS_IO", .pme_code = 0x6c, .pme_flags = PFMLIB_CORE_CSPEC, .pme_desc = "IO bus transactions", .pme_umasks = { INTEL_CORE_SPECIFICITY_UMASKS, INTEL_CORE_AGENT_UMASKS }, .pme_numasks = 4 }, { .pme_name = "BUS_TRANS_DEF", .pme_code = 0x6d, .pme_flags = PFMLIB_CORE_CSPEC, .pme_desc = "Deferred bus transactions", .pme_umasks = { INTEL_CORE_SPECIFICITY_UMASKS, INTEL_CORE_AGENT_UMASKS }, .pme_numasks = 4 }, { .pme_name = "BUS_TRANS_BURST", .pme_code = 0x6e, .pme_flags = PFMLIB_CORE_CSPEC, .pme_desc = "Burst (full cache-line) bus transactions", .pme_umasks = { INTEL_CORE_SPECIFICITY_UMASKS, INTEL_CORE_AGENT_UMASKS }, .pme_numasks = 4 }, { .pme_name = "BUS_TRANS_MEM", .pme_code = 0x6f, .pme_flags = PFMLIB_CORE_CSPEC, .pme_desc = "Memory bus transactions", .pme_umasks = { INTEL_CORE_SPECIFICITY_UMASKS, INTEL_CORE_AGENT_UMASKS }, .pme_numasks = 4 }, { .pme_name = "BUS_TRANS_ANY", .pme_code = 0x70, .pme_flags = PFMLIB_CORE_CSPEC, .pme_desc = "All bus transactions", .pme_umasks = { INTEL_CORE_SPECIFICITY_UMASKS, INTEL_CORE_AGENT_UMASKS }, .pme_numasks = 4 }, { .pme_name = "EXT_SNOOP", .pme_code = 0x77, .pme_flags = 0, .pme_desc = "External snoops responses", .pme_umasks = { INTEL_CORE_AGENT_UMASKS, { .pme_uname = "ANY", .pme_udesc = "Any external snoop response", .pme_ucode = 0xb }, { .pme_uname = "CLEAN", .pme_udesc = "External snoop CLEAN response", .pme_ucode = 0x1 }, { .pme_uname = "HIT", .pme_udesc = "External snoop HIT response", .pme_ucode = 0x2 }, { .pme_uname = "HITM", .pme_udesc = "External snoop HITM response", .pme_ucode = 0x8 } }, .pme_numasks = 6 }, { .pme_name = "CMP_SNOOP", .pme_code = 0x78, .pme_flags = PFMLIB_CORE_CSPEC, .pme_desc = "L1 data cache is snooped by other core", .pme_umasks = { INTEL_CORE_SPECIFICITY_UMASKS, { .pme_uname = "ANY", .pme_udesc = "L1 data cache is snooped by other core", .pme_ucode = 0x03 }, { .pme_uname = "SHARE", .pme_udesc = "L1 data cache is snooped for sharing by other core", .pme_ucode = 0x01 }, { .pme_uname = "INVALIDATE", .pme_udesc = "L1 data cache is snooped for Invalidation by other core", .pme_ucode = 0x02 } }, .pme_numasks = 5 }, { .pme_name = "BUS_HIT_DRV", .pme_code = 0x7a, .pme_flags = 0, .pme_desc = "HIT signal asserted", .pme_umasks = { INTEL_CORE_AGENT_UMASKS }, .pme_numasks = 2 }, { .pme_name = "BUS_HITM_DRV", .pme_code = 0x7b, .pme_flags = 0, .pme_desc = "HITM signal asserted", .pme_umasks = { INTEL_CORE_AGENT_UMASKS }, .pme_numasks = 2 }, { .pme_name = "BUSQ_EMPTY", .pme_code = 0x7d, .pme_flags = 0, .pme_desc = "Bus queue is empty", .pme_umasks = { INTEL_CORE_AGENT_UMASKS }, .pme_numasks = 2 }, { .pme_name = "SNOOP_STALL_DRV", .pme_code = 0x7e, .pme_flags = PFMLIB_CORE_CSPEC, .pme_desc = "Bus stalled for snoops", .pme_umasks = { INTEL_CORE_SPECIFICITY_UMASKS, INTEL_CORE_AGENT_UMASKS }, .pme_numasks = 4 }, { .pme_name = "BUS_IO_WAIT", .pme_code = 0x7f, .pme_flags = PFMLIB_CORE_CSPEC, .pme_desc = "IO requests waiting in the bus queue", .pme_umasks = { INTEL_CORE_SPECIFICITY_UMASKS }, .pme_numasks = 2 }, { .pme_name = "L1I_READS", .pme_code = 0x80, .pme_flags = 0, .pme_desc = "Instruction fetches" }, { .pme_name = "L1I_MISSES", .pme_code = 0x81, .pme_flags = 0, .pme_desc = "Instruction Fetch Unit misses" }, { .pme_name = "ITLB", .pme_code = 0x82, .pme_flags = 0, .pme_desc = "ITLB small page misses", .pme_umasks = { { .pme_uname = "SMALL_MISS", .pme_udesc = "ITLB small page misses", .pme_ucode = 0x2 }, { .pme_uname = "LARGE_MISS", .pme_udesc = "ITLB large page misses", .pme_ucode = 0x10 }, { .pme_uname = "FLUSH", .pme_udesc = "ITLB flushes", .pme_ucode = 0x40 }, { .pme_uname = "MISSES", .pme_udesc = "ITLB misses", .pme_ucode = 0x12 } }, .pme_numasks = 4 }, { .pme_name = "INST_QUEUE", .pme_code = 0x83, .pme_flags = 0, .pme_desc = "Cycles during which the instruction queue is full", .pme_umasks = { { .pme_uname = "FULL", .pme_udesc = "Cycles during which the instruction queue is full", .pme_ucode = 0x2 } }, .pme_numasks = 1 }, { .pme_name = "CYCLES_L1I_MEM_STALLED", .pme_code = 0x86, .pme_flags = 0, .pme_desc = "Cycles during which instruction fetches are stalled" }, { .pme_name = "ILD_STALL", .pme_code = 0x87, .pme_flags = 0, .pme_desc = "Instruction Length Decoder stall cycles due to a length changing prefix" }, { .pme_name = "BR_INST_EXEC", .pme_code = 0x88, .pme_flags = 0, .pme_desc = "Branch instructions executed" }, { .pme_name = "BR_MISSP_EXEC", .pme_code = 0x89, .pme_flags = 0, .pme_desc = "Mispredicted branch instructions executed" }, { .pme_name = "BR_BAC_MISSP_EXEC", .pme_code = 0x8a, .pme_flags = 0, .pme_desc = "Branch instructions mispredicted at decoding" }, { .pme_name = "BR_CND_EXEC", .pme_code = 0x8b, .pme_flags = 0, .pme_desc = "Conditional branch instructions executed" }, { .pme_name = "BR_CND_MISSP_EXEC", .pme_code = 0x8c, .pme_flags = 0, .pme_desc = "Mispredicted conditional branch instructions executed" }, { .pme_name = "BR_IND_EXEC", .pme_code = 0x8d, .pme_flags = 0, .pme_desc = "Indirect branch instructions executed" }, { .pme_name = "BR_IND_MISSP_EXEC", .pme_code = 0x8e, .pme_flags = 0, .pme_desc = "Mispredicted indirect branch instructions executed" }, { .pme_name = "BR_RET_EXEC", .pme_code = 0x8f, .pme_flags = 0, .pme_desc = "RET instructions executed" }, { .pme_name = "BR_RET_MISSP_EXEC", .pme_code = 0x90, .pme_flags = 0, .pme_desc = "Mispredicted RET instructions executed" }, { .pme_name = "BR_RET_BAC_MISSP_EXEC", .pme_code = 0x91, .pme_flags = 0, .pme_desc = "RET instructions executed mispredicted at decoding" }, { .pme_name = "BR_CALL_EXEC", .pme_code = 0x92, .pme_flags = 0, .pme_desc = "CALL instructions executed" }, { .pme_name = "BR_CALL_MISSP_EXEC", .pme_code = 0x93, .pme_flags = 0, .pme_desc = "Mispredicted CALL instructions executed" }, { .pme_name = "BR_IND_CALL_EXEC", .pme_code = 0x94, .pme_flags = 0, .pme_desc = "Indirect CALL instructions executed" }, { .pme_name = "BR_TKN_BUBBLE_1", .pme_code = 0x97, .pme_flags = 0, .pme_desc = "Branch predicted taken with bubble I" }, { .pme_name = "BR_TKN_BUBBLE_2", .pme_code = 0x98, .pme_flags = 0, .pme_desc = "Branch predicted taken with bubble II" }, #if 0 /* * Looks like event 0xa1 supersedes this one */ { .pme_name = "RS_UOPS_DISPATCHED", .pme_code = 0xa0, .pme_flags = 0, .pme_desc = "Micro-ops dispatched for execution" }, #endif { .pme_name = "MACRO_INSTS", .pme_code = 0xaa, .pme_flags = 0, .pme_desc = "Instructions decoded", .pme_umasks = { { .pme_uname = "DECODED", .pme_udesc = "Instructions decoded", .pme_ucode = 0x1 }, { .pme_uname = "CISC_DECODED", .pme_udesc = "CISC instructions decoded", .pme_ucode = 0x8 } }, .pme_numasks = 2 }, { .pme_name = "ESP", .pme_code = 0xab, .pme_flags = 0, .pme_desc = "ESP register content synchronization", .pme_umasks = { { .pme_uname = "SYNCH", .pme_udesc = "ESP register content synchronization", .pme_ucode = 0x1 }, { .pme_uname = "ADDITIONS", .pme_udesc = "ESP register automatic additions", .pme_ucode = 0x2 } }, .pme_numasks = 2 }, { .pme_name = "SIMD_UOPS_EXEC", .pme_code = 0xb0, .pme_flags = 0, .pme_desc = "SIMD micro-ops executed (excluding stores)" }, { .pme_name = "SIMD_SAT_UOP_EXEC", .pme_code = 0xb1, .pme_flags = 0, .pme_desc = "SIMD saturated arithmetic micro-ops executed" }, { .pme_name = "SIMD_UOP_TYPE_EXEC", .pme_code = 0xb3, .pme_flags = 0, .pme_desc = "SIMD packed multiply micro-ops executed", .pme_umasks = { { .pme_uname = "MUL", .pme_udesc = "SIMD packed multiply micro-ops executed", .pme_ucode = 0x1 }, { .pme_uname = "SHIFT", .pme_udesc = "SIMD packed shift micro-ops executed", .pme_ucode = 0x2 }, { .pme_uname = "PACK", .pme_udesc = "SIMD pack micro-ops executed", .pme_ucode = 0x4 }, { .pme_uname = "UNPACK", .pme_udesc = "SIMD unpack micro-ops executed", .pme_ucode = 0x8 }, { .pme_uname = "LOGICAL", .pme_udesc = "SIMD packed logical micro-ops executed", .pme_ucode = 0x10 }, { .pme_uname = "ARITHMETIC", .pme_udesc = "SIMD packed arithmetic micro-ops executed", .pme_ucode = 0x20 } }, .pme_numasks = 6 }, { .pme_name = "INST_RETIRED", .pme_code = 0xc0, .pme_desc = "Instructions retired", .pme_umasks = { { .pme_uname = "ANY_P", .pme_udesc = "Instructions retired (precise event)", .pme_ucode = 0x0, .pme_flags = PFMLIB_CORE_PEBS }, { .pme_uname = "LOADS", .pme_udesc = "Instructions retired, which contain a load", .pme_ucode = 0x1 }, { .pme_uname = "STORES", .pme_udesc = "Instructions retired, which contain a store", .pme_ucode = 0x2 }, { .pme_uname = "OTHER", .pme_udesc = "Instructions retired, with no load or store operation", .pme_ucode = 0x4 } }, .pme_numasks = 4 }, { .pme_name = "X87_OPS_RETIRED", .pme_code = 0xc1, .pme_flags = 0, .pme_desc = "FXCH instructions retired", .pme_umasks = { { .pme_uname = "FXCH", .pme_udesc = "FXCH instructions retired", .pme_ucode = 0x1 }, { .pme_uname = "ANY", .pme_udesc = "Retired floating-point computational operations (precise event)", .pme_ucode = 0xfe, .pme_flags = PFMLIB_CORE_PEBS } }, .pme_numasks = 2 }, { .pme_name = "UOPS_RETIRED", .pme_code = 0xc2, .pme_flags = 0, .pme_desc = "Fused load+op or load+indirect branch retired", .pme_umasks = { { .pme_uname = "LD_IND_BR", .pme_udesc = "Fused load+op or load+indirect branch retired", .pme_ucode = 0x1 }, { .pme_uname = "STD_STA", .pme_udesc = "Fused store address + data retired", .pme_ucode = 0x2 }, { .pme_uname = "MACRO_FUSION", .pme_udesc = "Retired instruction pairs fused into one micro-op", .pme_ucode = 0x4 }, { .pme_uname = "NON_FUSED", .pme_udesc = "Non-fused micro-ops retired", .pme_ucode = 0x8 }, { .pme_uname = "FUSED", .pme_udesc = "Fused micro-ops retired", .pme_ucode = 0x7 }, { .pme_uname = "ANY", .pme_udesc = "Micro-ops retired", .pme_ucode = 0xf } }, .pme_numasks = 6 }, { .pme_name = "MACHINE_NUKES", .pme_code = 0xc3, .pme_flags = 0, .pme_desc = "Self-Modifying Code detected", .pme_umasks = { { .pme_uname = "SMC", .pme_udesc = "Self-Modifying Code detected", .pme_ucode = 0x1 }, { .pme_uname = "MEM_ORDER", .pme_udesc = "Execution pipeline restart due to memory ordering conflict or memory disambiguation misprediction", .pme_ucode = 0x4 } }, .pme_numasks = 2 }, { .pme_name = "BR_INST_RETIRED", .pme_code = 0xc4, .pme_flags = 0, .pme_desc = "Retired branch instructions", .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "Retired branch instructions", .pme_ucode = 0x0 }, { .pme_uname = "PRED_NOT_TAKEN", .pme_udesc = "Retired branch instructions that were predicted not-taken", .pme_ucode = 0x1 }, { .pme_uname = "MISPRED_NOT_TAKEN", .pme_udesc = "Retired branch instructions that were mispredicted not-taken", .pme_ucode = 0x2 }, { .pme_uname = "PRED_TAKEN", .pme_udesc = "Retired branch instructions that were predicted taken", .pme_ucode = 0x4 }, { .pme_uname = "MISPRED_TAKEN", .pme_udesc = "Retired branch instructions that were mispredicted taken", .pme_ucode = 0x8 }, { .pme_uname = "TAKEN", .pme_udesc = "Retired taken branch instructions", .pme_ucode = 0xc } }, .pme_numasks = 6 }, { .pme_name = "BR_INST_RETIRED_MISPRED", .pme_code = 0x00c5, .pme_desc = "Retired mispredicted branch instructions (precise_event)", .pme_flags = PFMLIB_CORE_PEBS }, { .pme_name = "CYCLES_INT_MASKED", .pme_code = 0x1c6, .pme_flags = 0, .pme_desc = "Cycles during which interrupts are disabled" }, { .pme_name = "CYCLES_INT_PENDING_AND_MASKED", .pme_code = 0x2c6, .pme_flags = 0, .pme_desc = "Cycles during which interrupts are pending and disabled" }, { .pme_name = "SIMD_INST_RETIRED", .pme_code = 0xc7, .pme_flags = 0, .pme_desc = "Retired Streaming SIMD Extensions (SSE) packed-single instructions", .pme_umasks = { { .pme_uname = "PACKED_SINGLE", .pme_udesc = "Retired Streaming SIMD Extensions (SSE) packed-single instructions", .pme_ucode = 0x1 }, { .pme_uname = "SCALAR_SINGLE", .pme_udesc = "Retired Streaming SIMD Extensions (SSE) scalar-single instructions", .pme_ucode = 0x2 }, { .pme_uname = "PACKED_DOUBLE", .pme_udesc = "Retired Streaming SIMD Extensions 2 (SSE2) packed-double instructions", .pme_ucode = 0x4 }, { .pme_uname = "SCALAR_DOUBLE", .pme_udesc = "Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions", .pme_ucode = 0x8 }, { .pme_uname = "VECTOR", .pme_udesc = "Retired Streaming SIMD Extensions 2 (SSE2) vector integer instructions", .pme_ucode = 0x10 }, { .pme_uname = "ANY", .pme_udesc = "Retired Streaming SIMD instructions (precise event)", .pme_ucode = 0x1f, .pme_flags = PFMLIB_CORE_PEBS } }, .pme_numasks = 6 }, { .pme_name = "HW_INT_RCV", .pme_code = 0xc8, .pme_desc = "Hardware interrupts received" }, { .pme_name = "ITLB_MISS_RETIRED", .pme_code = 0xc9, .pme_flags = 0, .pme_desc = "Retired instructions that missed the ITLB" }, { .pme_name = "SIMD_COMP_INST_RETIRED", .pme_code = 0xca, .pme_flags = 0, .pme_desc = "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions", .pme_umasks = { { .pme_uname = "PACKED_SINGLE", .pme_udesc = "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions", .pme_ucode = 0x1 }, { .pme_uname = "SCALAR_SINGLE", .pme_udesc = "Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions", .pme_ucode = 0x2 }, { .pme_uname = "PACKED_DOUBLE", .pme_udesc = "Retired computational Streaming SIMD Extensions 2 (SSE2) packed-double instructions", .pme_ucode = 0x4 }, { .pme_uname = "SCALAR_DOUBLE", .pme_udesc = "Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions", .pme_ucode = 0x8 } }, .pme_numasks = 4 }, { .pme_name = "MEM_LOAD_RETIRED", .pme_code = 0xcb, .pme_desc = "Retired loads that miss the L1 data cache", .pme_flags = PFMLIB_CORE_PMC0, .pme_umasks = { { .pme_uname = "L1D_MISS", .pme_udesc = "Retired loads that miss the L1 data cache (precise event)", .pme_ucode = 0x1, .pme_flags = PFMLIB_CORE_PEBS }, { .pme_uname = "L1D_LINE_MISS", .pme_udesc = "L1 data cache line missed by retired loads (precise event)", .pme_ucode = 0x2, .pme_flags = PFMLIB_CORE_PEBS }, { .pme_uname = "L2_MISS", .pme_udesc = "Retired loads that miss the L2 cache (precise event)", .pme_ucode = 0x4, .pme_flags = PFMLIB_CORE_PEBS }, { .pme_uname = "L2_LINE_MISS", .pme_udesc = "L2 cache line missed by retired loads (precise event)", .pme_ucode = 0x8, .pme_flags = PFMLIB_CORE_PEBS }, { .pme_uname = "DTLB_MISS", .pme_udesc = "Retired loads that miss the DTLB (precise event)", .pme_ucode = 0x10, .pme_flags = PFMLIB_CORE_PEBS } }, .pme_numasks = 5 }, { .pme_name = "FP_MMX_TRANS", .pme_code = 0xcc, .pme_flags = PFMLIB_CORE_PEBS, .pme_desc = "Transitions from MMX (TM) Instructions to Floating Point Instructions", .pme_umasks = { { .pme_uname = "TO_FP", .pme_udesc = "Transitions from MMX (TM) Instructions to Floating Point Instructions", .pme_ucode = 0x2 }, { .pme_uname = "TO_MMX", .pme_udesc = "Transitions from Floating Point to MMX (TM) Instructions", .pme_ucode = 0x1 } }, .pme_numasks = 2 }, { .pme_name = "SIMD_ASSIST", .pme_code = 0xcd, .pme_flags = 0, .pme_desc = "SIMD assists invoked" }, { .pme_name = "SIMD_INSTR_RETIRED", .pme_code = 0xce, .pme_flags = 0, .pme_desc = "SIMD Instructions retired" }, { .pme_name = "SIMD_SAT_INSTR_RETIRED", .pme_code = 0xcf, .pme_flags = 0, .pme_desc = "Saturated arithmetic instructions retired" }, { .pme_name = "RAT_STALLS", .pme_code = 0xd2, .pme_flags = 0, .pme_desc = "ROB read port stalls cycles", .pme_umasks = { { .pme_uname = "ROB_READ_PORT", .pme_udesc = "ROB read port stalls cycles", .pme_ucode = 0x1 }, { .pme_uname = "PARTIAL_CYCLES", .pme_udesc = "Partial register stall cycles", .pme_ucode = 0x2 }, { .pme_uname = "FLAGS", .pme_udesc = "Flag stall cycles", .pme_ucode = 0x4 }, { .pme_uname = "FPSW", .pme_udesc = "FPU status word stall", .pme_ucode = 0x8 }, { .pme_uname = "ANY", .pme_udesc = "All RAT stall cycles", .pme_ucode = 0xf } }, .pme_numasks = 5 }, { .pme_name = "SEG_RENAME_STALLS", .pme_code = 0xd4, .pme_flags = 0, .pme_desc = "Segment rename stalls - ES ", .pme_umasks = { { .pme_uname = "ES", .pme_udesc = "Segment rename stalls - ES ", .pme_ucode = 0x1 }, { .pme_uname = "DS", .pme_udesc = "Segment rename stalls - DS", .pme_ucode = 0x2 }, { .pme_uname = "FS", .pme_udesc = "Segment rename stalls - FS", .pme_ucode = 0x4 }, { .pme_uname = "GS", .pme_udesc = "Segment rename stalls - GS", .pme_ucode = 0x8 }, { .pme_uname = "ANY", .pme_udesc = "Any (ES/DS/FS/GS) segment rename stall", .pme_ucode = 0xf } }, .pme_numasks = 5 }, { .pme_name = "SEG_REG_RENAMES", .pme_code = 0xd5, .pme_flags = 0, .pme_desc = "Segment renames - ES", .pme_umasks = { { .pme_uname = "ES", .pme_udesc = "Segment renames - ES", .pme_ucode = 0x1 }, { .pme_uname = "DS", .pme_udesc = "Segment renames - DS", .pme_ucode = 0x2 }, { .pme_uname = "FS", .pme_udesc = "Segment renames - FS", .pme_ucode = 0x4 }, { .pme_uname = "GS", .pme_udesc = "Segment renames - GS", .pme_ucode = 0x8 }, { .pme_uname = "ANY", .pme_udesc = "Any (ES/DS/FS/GS) segment rename", .pme_ucode = 0xf } }, .pme_numasks = 5 }, { .pme_name = "RESOURCE_STALLS", .pme_code = 0xdc, .pme_flags = 0, .pme_desc = "Cycles during which the ROB is full", .pme_umasks = { { .pme_uname = "ROB_FULL", .pme_udesc = "Cycles during which the ROB is full", .pme_ucode = 0x1 }, { .pme_uname = "RS_FULL", .pme_udesc = "Cycles during which the RS is full", .pme_ucode = 0x2 }, { .pme_uname = "LD_ST", .pme_udesc = "Cycles during which the pipeline has exceeded load or store limit or waiting to commit all stores", .pme_ucode = 0x4 }, { .pme_uname = "FPCW", .pme_udesc = "Cycles stalled due to FPU control word write", .pme_ucode = 0x8 }, { .pme_uname = "BR_MISS_CLEAR", .pme_udesc = "Cycles stalled due to branch misprediction", .pme_ucode = 0x10 }, { .pme_uname = "ANY", .pme_udesc = "Resource related stalls", .pme_ucode = 0x1f } }, .pme_numasks = 6 }, { .pme_name = "BR_INST_DECODED", .pme_code = 0xe0, .pme_flags = 0, .pme_desc = "Branch instructions decoded" }, { .pme_name = "BOGUS_BR", .pme_code = 0xe4, .pme_flags = 0, .pme_desc = "Bogus branches" }, { .pme_name = "BACLEARS", .pme_code = 0xe6, .pme_flags = 0, .pme_desc = "BACLEARS asserted" }, { .pme_name = "PREF_RQSTS_UP", .pme_code = 0xf0, .pme_flags = 0, .pme_desc = "Upward prefetches issued from the DPL" }, { .pme_name = "PREF_RQSTS_DN", .pme_code = 0xf8, .pme_flags = 0, .pme_desc = "Downward prefetches issued from the DPL" } }; #define PME_CORE_UNHALTED_CORE_CYCLES 0 #define PME_CORE_INSTRUCTIONS_RETIRED 1 #define PME_CORE_EVENT_COUNT (sizeof(core_pe)/sizeof(pme_core_entry_t)) papi-5.5.1/src/libpfm-3.y/lib/ultra4plus_events.h0000644000307100002310000004665013013651450021557 0ustar yarkhangraduatestatic pme_sparc_entry_t ultra4plus_pe[] = { /* These two must always be first. */ { .pme_name = "Cycle_cnt", .pme_desc = "Accumulated cycles", .pme_ctrl = PME_CTRL_S0 | PME_CTRL_S1, .pme_val = 0x0, }, { .pme_name = "Instr_cnt", .pme_desc = "Number of instructions completed", .pme_ctrl = PME_CTRL_S0 | PME_CTRL_S1, .pme_val = 0x1, }, /* PIC0 UltraSPARC-IV+ events */ { .pme_name = "Dispatch0_IC_miss", .pme_desc = "I-buffer is empty from I-Cache miss", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x2, }, { .pme_name = "IU_stat_jmp_correct_pred", .pme_desc = "Retired non-annulled register indirect jumps predicted correctly", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x3, }, { .pme_name = "Dispatch0_2nd_br", .pme_desc = "Stall cycles due to having two branch instructions line-up in one 4-instruction group causing the second branch in the group to be re-fetched, delaying it's entrance into the I-buffer", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x4, }, { .pme_name = "Rstall_storeQ", .pme_desc = "R-stage stall for a store instruction which is the next instruction to be executed, but it stailled due to the store queue being full", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x5, }, { .pme_name = "Rstall_IU_use", .pme_desc = "R-stage stall for an event that the next instruction to be executed depends on the result of a preceeding integer instruction in the pipeline that is not yet available", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x6, }, { .pme_name = "IU_stat_ret_correct_pred", .pme_desc = "Retired non-annulled returns predicted correctly", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x7, }, { .pme_name = "IC_ref", .pme_desc = "I-cache refrences", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x8, }, { .pme_name = "DC_rd", .pme_desc = "D-cache read references (including accesses that subsequently trap)", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x9, }, { .pme_name = "Rstall_FP_use", .pme_desc = "R-stage stall for an event that the next instruction to be executed depends on the result of a preceeding floating-point instruction in the pipeline that is not yet available", .pme_ctrl = PME_CTRL_S0, .pme_val = 0xa, }, { .pme_name = "SW_pf_instr", .pme_desc = "Retired SW prefetch instructions", .pme_ctrl = PME_CTRL_S0, .pme_val = 0xb, }, { .pme_name = "L2_ref", .pme_desc = "L2-cache references", .pme_ctrl = PME_CTRL_S0, .pme_val = 0xc, }, { .pme_name = "L2_write_hit_RTO", .pme_desc = "L2-cache exclusive requests that hit L2-cache in S, O, or Os state and thus, do a read-to-own bus transaction", .pme_ctrl = PME_CTRL_S0, .pme_val = 0xd, }, { .pme_name = "L2_snoop_inv_sh", .pme_desc = "L2 cache lines that were written back to the L3 cache due to requests from both cores", .pme_ctrl = PME_CTRL_S0, .pme_val = 0xe, }, { .pme_name = "L2_rd_miss", .pme_desc = "L2-cache miss events (including atomics) from D-cache events", .pme_ctrl = PME_CTRL_S0, .pme_val = 0xf, }, { .pme_name = "PC_rd", .pme_desc = "P-cache cacheable loads", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x10, }, { .pme_name = "SI_snoop_sh", .pme_desc = "Counts snoops from remote processor(s) including RTS, RTSR, RTO, RTOR, RS, RSR, RTSM, and WS", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x11, }, { .pme_name = "SI_ciq_flow_sh", .pme_desc = "Counts system clock cycles when the flow control (PauseOut) signal is asserted", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x12, }, { .pme_name = "Re_DC_miss", .pme_desc = "Stall due to loads that miss D-cache and get recirculated", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x13, }, { .pme_name = "SW_count_NOP0", .pme_desc = "Retired, non-annulled special software NOP instructions (which is equivalent to 'sethi %hi(0xfc000), %g0' instruction)", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x14, }, { .pme_name = "IU_Stat_Br_miss_taken", .pme_desc = "Retired branches that were predicted to be taken, but in fact were not taken", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x15, }, { .pme_name = "IU_Stat_Br_Count_taken", .pme_desc = "Retired taken branches", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x16, }, { .pme_name = "HW_pf_exec", .pme_desc = "Hardware prefetches enqueued in the prefetch queue", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x17, }, { .pme_name = "FA_pipe_completion", .pme_desc = "Instructions that complete execution on the FPG ALU pipelines", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x18, }, { .pme_name = "SSM_L3_wb_remote", .pme_desc = "L3 cache line victimizations from this core which generate R_WB transactions to non-LPA (remote physical address) regions", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x19, }, { .pme_name = "SSM_L3_miss_local", .pme_desc = "L3 cache misses to LPA (local physical address) from this core which generate an RTS, RTO, or RS transaction", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x1a, }, { .pme_name = "SSM_L3_miss_mtag_remote", .pme_desc = "L3 cache misses to LPA (local physical address) from this core which generate retry (R_*) transactions including R_RTS, R_RTO, and R_RS", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x1b, }, { .pme_name = "SW_pf_str_trapped", .pme_desc = "Strong software prefetch instructions trapping due to TLB miss", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x1c, }, { .pme_name = "SW_pf_PC_installed", .pme_desc = "Software prefetch instructions that installed lines in the P-cache", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x1d, }, { .pme_name = "IPB_to_IC_fill", .pme_desc = "I-cache filles from the instruction prefetch buffer", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x1e, }, { .pme_name = "L2_write_miss", .pme_desc = "L2-cache misses from this core by cacheable store requests", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x1f, }, { .pme_name = "MC_reads_0_sh", .pme_desc = "Read requests completed to memory bank 0", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x20, }, { .pme_name = "MC_reads_1_sh", .pme_desc = "Read requests completed to memory bank 1", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x21, }, { .pme_name = "MC_reads_2_sh", .pme_desc = "Read requests completed to memory bank 2", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x22, }, { .pme_name = "MC_reads_3_sh", .pme_desc = "Read requests completed to memory bank 3", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x23, }, { .pme_name = "MC_stalls_0_sh", .pme_desc = "Clock cycles that requests were stalled in the MCU queues because bank 0 was busy with a previous request", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x24, }, { .pme_name = "MC_stalls_2_sh", .pme_desc = "Clock cycles that requests were stalled in the MCU queues because bank 2 was busy with a previous request", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x25, }, { .pme_name = "L2_hit_other_half", .pme_desc = "L2 cache hits from this core to the ways filled by the other core when the cache is in the pseudo-split mode", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x26, }, { .pme_name = "L3_rd_miss", .pme_desc = "L3 cache misses sent out to SIU from this code by cacheable I-cache, D-cache, PO-cache, and W-cache (excluding block store) requests", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x28, }, { .pme_name = "Re_L2_miss", .pme_desc = "Stall cycles due to recirculation of cacheable loads that miss both D-cache and L2 cache", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x29, }, { .pme_name = "IC_miss_cancelled", .pme_desc = "I-cache miss requests cancelled due to new fetch stream", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x2a, }, { .pme_name = "DC_wr_miss", .pme_desc = "D-cache store accesses that miss D-cache", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x2b, }, { .pme_name = "L3_hit_I_state_sh", .pme_desc = "Tag hits in L3 cache when the line is in I state", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x2c, }, { .pme_name = "SI_RTS_src_data", .pme_desc = "Local RTS transactions due to I-cache, D-cache, or P-cache requests from this core where data is from the cache of another processor on the system, not from memory", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x2d, }, { .pme_name = "L2_IC_miss", .pme_desc = "L2 cache misses from this code by cacheable I-cache requests", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x2e, }, { .pme_name = "SSM_new_transaction_sh", .pme_desc = "New SSM transactions (RTSU, RTOU, UGM) observed by this processor on the Fireplane Interconnect", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x2f, }, { .pme_name = "L2_SW_pf_miss", .pme_desc = "L2 cache misses by software prefetch requests from this core", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x30, }, { .pme_name = "L2_wb", .pme_desc = "L2 cache lines that were written back to the L3 cache because of requests from this core", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x31, }, { .pme_name = "L2_wb_sh", .pme_desc = "L2 cache lines that were written back to the L3 cache because of requests from both cores", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x32, }, { .pme_name = "L2_snoop_cb_sh", .pme_desc = "L2 cache lines that were copied back due to other processors", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x33, }, /* PIC1 UltraSPARC-IV+ events */ { .pme_name = "Dispatch0_other", .pme_desc = "Stall cycles due to the event that no instructions are dispatched because the I-queue is empty due to various other events, including branch target address fetch and various events which cause an instruction to be refetched", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x2, }, { .pme_name = "DC_wr", .pme_desc = "D-cache write references by cacheable stores (excluding block stores)", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x3, }, { .pme_name = "Re_DC_missovhd", .pme_desc = "Stall cycles due to D-cache load miss", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x4, }, { .pme_name = "Re_FPU_bypass", .pme_desc = "Stall due to recirculation when an FPU bypass condition that does not have a direct bypass path occurs", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x5, }, { .pme_name = "L3_write_hit_RTO", .pme_desc = "L3 cache hits in O, Os, or S state by cacheable store requests from this core that do a read-to-own (RTO) bus transaction", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x6, }, { .pme_name = "L2L3_snoop_inv_sh", .pme_desc = "L2 and L3 cache lines that were invalidated due to other processors doing RTO, RTOR, RTOU, or WS transactions", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x7, }, { .pme_name = "IC_L2_req", .pme_desc = "I-cache requests sent to L2 cache", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x8, }, { .pme_name = "DC_rd_miss", .pme_desc = "Cacheable loads (excluding atomics and block loads) that miss D-cache as well as P-cache (for FP loads)", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x9, }, { .pme_name = "L2_hit_I_state_sh", .pme_desc = "Tag hits in L2 cache when the line is in I state", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xa, }, { .pme_name = "L3_write_miss_RTO", .pme_desc = "L3 cache misses from this core by cacheable store requests that do a read-to-own (RTO) bus transaction. This count does not include RTO requests for prefetch (fcn=2,3/22,23) instructions", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xb, }, { .pme_name = "L2_miss", .pme_desc = "L2 cache misses from this core by cacheable I-cache, D-cache, P-cache, and W-cache (excluding block stores) requests", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xc, }, { .pme_name = "SI_owned_sh", .pme_desc = "Number of times owned_in is asserted on bus requests from the local processor", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xd, }, { .pme_name = "SI_RTO_src_data", .pme_desc = "Number of local RTO transactions due to W-cache or P-cache requests from this core where data is from the cache of another processor on the system, not from memory", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xe, }, { .pme_name = "SW_pf_duplicate", .pme_desc = "Number of software prefetch instructions that were dropped because the prefetch request matched an outstanding requests in the prefetch queue or the request hit the P-cache", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xf, }, { .pme_name = "IU_stat_jmp_mispred", .pme_desc = "Number of retired non-annulled register indirect jumps mispredicted", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x10, }, { .pme_name = "ITLB_miss", .pme_desc = "I-TLB misses", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x11, }, { .pme_name = "DTLB_miss", .pme_desc = "D-TLB misses", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x12, }, { .pme_name = "WC_miss", .pme_desc = "W-cache misses", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x13, }, { .pme_name = "IC_fill", .pme_desc = "Number of I-cache fills excluding fills from the instruction prefetch buffer. This is the best approximation of the number of I-cache misses for instructions that were actually executed", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x14, }, { .pme_name = "IU_stat_ret_mispred", .pme_desc = "Number of retired non-annulled returns mispredicted", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x15, }, { .pme_name = "Re_L3_miss", .pme_desc = "Stall cycles due to recirculation of cacheable loads that miss D-cache, L2, and L3 cache", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x16, }, { .pme_name = "Re_PFQ_full", .pme_desc = "Stall cycles due to recirculation of prefetch instructions because the prefetch queue (PFQ) was full", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x17, }, { .pme_name = "PC_soft_hit", .pme_desc = "Number of cacheable FP loads that hit a P-cache line that was prefetched by a software prefetch instruction", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x18, }, { .pme_name = "PC_inv", .pme_desc = "Number of P-cache lines that were invalidated due to external snoops, internal stores, and L2 evictions", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x19, }, { .pme_name = "PC_hard_hit", .pme_desc = "Number of FP loads that hit a P-cache line that was fetched by a FP load or a hardware prefetch, irrespective of whether the loads hit or miss the D-cache", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x1a, }, { .pme_name = "IC_pf", .pme_desc = "Number of I-cache prefetch requests sent to L2 cache", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x1b, }, { .pme_name = "SW_count_NOP1", .pme_desc = "Retired, non-annulled special software NOP instructions (which is equivalent to 'sethi %hi(0xfc000), %g0' instruction)", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x1c, }, { .pme_name = "IU_stat_br_miss_untaken", .pme_desc = "Number of retired non-annulled conditional branches that were predicted to be not taken, but in fact were taken", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x1d, }, { .pme_name = "IU_stat_br_count_taken", .pme_desc = "Number of retired non-annulled conditional branches that were taken", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x1e, }, { .pme_name = "PC_miss", .pme_desc = "Number of cacheable FP loads that miss P-cache, irrespective of whether the loads hit or miss the D-cache", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x1f, }, { .pme_name = "MC_writes_0_sh", .pme_desc = "Number of write requests complete to memory bank 0", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x20, }, { .pme_name = "MC_writes_1_sh", .pme_desc = "Number of write requests complete to memory bank 1", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x21, }, { .pme_name = "MC_writes_2_sh", .pme_desc = "Number of write requests complete to memory bank 2", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x22, }, { .pme_name = "MC_writes_3_sh", .pme_desc = "Number of write requests complete to memory bank 3", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x23, }, { .pme_name = "MC_stalls_1_sh", .pme_desc = "Number of processor cycles that requests were stalled in the MCU queues because bank 0 was busy with a previous requests", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x24, }, { .pme_name = "MC_stalls_3_sh", .pme_desc = "Number of processor cycles that requests were stalled in the MCU queues because bank 3 was busy with a previous requests", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x25, }, { .pme_name = "Re_RAW_miss", .pme_desc = "Stall cycles due to recirculation when there is a load instruction in the E-stage of the pipeline which has a non-bypassable read-after-write (RAW) hazard with an earlier store instruction", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x26, }, { .pme_name = "FM_pipe_completion", .pme_desc = "Number of retired instructions that complete execution on the FLoat-Point/Graphics Multiply pipeline", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x27, }, { .pme_name = "SSM_L3_miss_mtag_remote", .pme_desc = "Number of L3 cache misses to LPA (local physical address) from this core which generate retry (R_*) transactions including R_RTS, R_RTO, and R_RS", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x28, }, { .pme_name = "SSM_L3_miss_remote", .pme_desc = "Number of L3 cache misses from this core which generate retry (R_*) transactions to non-LPA (non-local physical address) address space, or R_WS transactions due to block store (BST) / block store commit (BSTC) to any address space (LPA or non-LPA), or R_RTO due to atomic request on Os state to LPA space.", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x29, }, { .pme_name = "SW_pf_exec", .pme_desc = "Number of retired, non-trapping software prefetch instructions that completed, i.e. number of retired prefetch instructions that were not dropped due to the prefecth queue being full", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x2a, }, { .pme_name = "SW_pf_str_exec", .pme_desc = "Number of retired, non-trapping strong prefetch instructions that completed", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x2b, }, { .pme_name = "SW_pf_dropped", .pme_desc = "Number of software prefetch instructions dropped due to TLB miss or due to the prefetch queue being full", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x2c, }, { .pme_name = "SW_pf_L2_installed", .pme_desc = "Number of software prefetch instructions that installed lines in the L2 cache", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x2d, }, { .pme_name = "L2_HW_pf_miss", .pme_desc = "Number of L2 cache misses by hardware prefetch requests from this core", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x2f, }, { .pme_name = "L3_miss", .pme_desc = "Number of L3 cache misses sent out to SIU from this core by cacheable I-cache, D-cache, P-cache, and W-cache (exclusing block stores) requests", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x31, }, { .pme_name = "L3_IC_miss", .pme_desc = "Number of L3 cache misses by cacheable I-cache requests from this core", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x32, }, { .pme_name = "L3_SW_pf_miss", .pme_desc = "Number of L3 cache misses by software prefetch requests from this core", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x33, }, { .pme_name = "L3_hit_other_half", .pme_desc = "Number of L3 cache hits from this core to the ways filled by the other core when the cache is in pseudo-split mode", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x34, }, { .pme_name = "L3_wb", .pme_desc = "Number of L3 cache lines that were written back because of requests from this core", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x35, }, { .pme_name = "L3_wb_sh", .pme_desc = "Number of L3 cache lines that were written back because of requests from both cores", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x36, }, { .pme_name = "L2L3_snoop_cb_sh", .pme_desc = "Total number of L2 and L3 cache lines that were copied back due to other processors", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x37, }, }; #define PME_ULTRA4PLUS_EVENT_COUNT (sizeof(ultra4plus_pe)/sizeof(pme_sparc_entry_t)) papi-5.5.1/src/libpfm-3.y/lib/pfmlib_gen_ia32.c0000644000307100002310000005662613013651450020773 0ustar yarkhangraduate/* * pfmlib_gen_ia32.c : Intel architectural PMU v1, v2, v3 * * The file provides support for the Intel architectural PMU v1 and v2. * * Copyright (c) 2005-2007 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * * This file implements supports for the IA-32 architectural PMU as specified * in the following document: * "IA-32 Intel Architecture Software Developer's Manual - Volume 3B: System * Programming Guide" */ #include #include #include #include #include /* public headers */ #include /* private headers */ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_gen_ia32_priv.h" /* architecture private */ #include "gen_ia32_events.h" /* architected event table */ /* let's define some handy shortcuts! */ #define sel_event_select perfevtsel.sel_event_select #define sel_unit_mask perfevtsel.sel_unit_mask #define sel_usr perfevtsel.sel_usr #define sel_os perfevtsel.sel_os #define sel_edge perfevtsel.sel_edge #define sel_pc perfevtsel.sel_pc #define sel_int perfevtsel.sel_int #define sel_any perfevtsel.sel_any #define sel_en perfevtsel.sel_en #define sel_inv perfevtsel.sel_inv #define sel_cnt_mask perfevtsel.sel_cnt_mask pfm_pmu_support_t *gen_support; /* * Description of the PMC/PMD register mappings use by * this module (as reported in pfmlib_reg_t.reg_num) * * For V1 (up to 16 generic counters 0-15): * * 0 -> PMC0 -> PERFEVTSEL0 -> MSR @ 0x186 * 1 -> PMC1 -> PERFEVTSEL1 -> MSR @ 0x187 * ... * n -> PMCn -> PERFEVTSELn -> MSR @ 0x186+n * * 0 -> PMD0 -> IA32_PMC0 -> MSR @ 0xc1 * 1 -> PMD1 -> IA32_PMC1 -> MSR @ 0xc2 * ... * n -> PMDn -> IA32_PMCn -> MSR @ 0xc1+n * * For V2 (up to 16 generic and 16 fixed counters): * * 0 -> PMC0 -> PERFEVTSEL0 -> MSR @ 0x186 * 1 -> PMC1 -> PERFEVTSEL1 -> MSR @ 0x187 * ... * 15 -> PMC15 -> PERFEVTSEL15 -> MSR @ 0x186+15 * * 16 -> PMC16 -> IA32_FIXED_CTR_CTRL -> MSR @ 0x38d * * 0 -> PMD0 -> IA32_PMC0 -> MSR @ 0xc1 * 1 -> PMD1 -> IA32_PMC1 -> MSR @ 0xc2 * ... * 15 -> PMD15 -> IA32_PMC15 -> MSR @ 0xc1+15 * * 16 -> PMD16 -> IA32_FIXED_CTR0 -> MSR @ 0x309 * 17 -> PMD17 -> IA32_FIXED_CTR1 -> MSR @ 0x30a * ... * n -> PMDn -> IA32_FIXED_CTRn -> MSR @ 0x309+n */ #define GEN_IA32_SEL_BASE 0x186 #define GEN_IA32_CTR_BASE 0xc1 #define GEN_IA32_FIXED_CTR_BASE 0x309 #define FIXED_PMD_BASE 16 #define PFMLIB_GEN_IA32_ALL_FLAGS \ (PFM_GEN_IA32_SEL_INV|PFM_GEN_IA32_SEL_EDGE|PFM_GEN_IA32_SEL_ANYTHR) static char * pfm_gen_ia32_get_event_name(unsigned int i); static pme_gen_ia32_entry_t *gen_ia32_pe; static int gen_ia32_cycle_event, gen_ia32_inst_retired_event; static unsigned int num_fixed_cnt, num_gen_cnt, pmu_version; #ifdef __i386__ static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx) { /* * because ebx is used in Pic mode, we need to save/restore because * cpuid clobbers it. I could not figure out a way to get ebx out in * one cpuid instruction. To extract ebx, we need to move it to another * register (here eax) */ __asm__("pushl %%ebx;cpuid; popl %%ebx" :"=a" (*eax) : "a" (op) : "ecx", "edx"); __asm__("pushl %%ebx;cpuid; movl %%ebx, %%eax;popl %%ebx" :"=a" (*ebx) : "a" (op) : "ecx", "edx"); } #else static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx) { __asm__("cpuid" : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx) : "0" (op), "c"(0)); } #endif static pfmlib_regmask_t gen_ia32_impl_pmcs, gen_ia32_impl_pmds; /* * create architected event table */ static int create_arch_event_table(unsigned int mask) { pme_gen_ia32_entry_t *pe; unsigned int i, num_events = 0; unsigned int m; /* * first pass: count the number of supported events */ m = mask; for(i=0; i < 7; i++, m>>=1) { if ((m & 0x1) == 0) num_events++; } gen_ia32_support.pme_count = num_events; gen_ia32_pe = calloc(num_events, sizeof(pme_gen_ia32_entry_t)); if (gen_ia32_pe == NULL) return PFMLIB_ERR_NOTSUPP; /* * second pass: populate the table */ gen_ia32_cycle_event = gen_ia32_inst_retired_event = -1; m = mask; for(i=0, pe = gen_ia32_pe; i < 7; i++, m>>=1) { if ((m & 0x1) == 0) { *pe = gen_ia32_all_pe[i]; /* * setup default event: cycles and inst_retired */ if (i == PME_GEN_IA32_UNHALTED_CORE_CYCLES) gen_ia32_cycle_event = pe - gen_ia32_pe; if (i == PME_GEN_IA32_INSTRUCTIONS_RETIRED) gen_ia32_inst_retired_event = pe - gen_ia32_pe; pe++; } } return PFMLIB_SUCCESS; } static int check_arch_pmu(int family) { union { unsigned int val; pmu_eax_t eax; pmu_edx_t edx; } eax, ecx, edx, ebx; /* * check family number to reject for processors * older than Pentium (family=5). Those processors * did not have the CPUID instruction */ if (family < 5) return PFMLIB_ERR_NOTSUPP; /* * check if CPU supports 0xa function of CPUID * 0xa started with Core Duo. Needed to detect if * architected PMU is present */ cpuid(0x0, &eax.val, &ebx.val, &ecx.val, &edx.val); if (eax.val < 0xa) return PFMLIB_ERR_NOTSUPP; /* * extract architected PMU information */ cpuid(0xa, &eax.val, &ebx.val, &ecx.val, &edx.val); /* * version must be greater than zero */ return eax.eax.version < 1 ? PFMLIB_ERR_NOTSUPP : PFMLIB_SUCCESS; } static int pfm_gen_ia32_detect(void) { int ret, family; char buffer[128]; ret = __pfm_getcpuinfo_attr("vendor_id", buffer, sizeof(buffer)); if (ret == -1) return PFMLIB_ERR_NOTSUPP; if (strcmp(buffer, "GenuineIntel")) return PFMLIB_ERR_NOTSUPP; ret = __pfm_getcpuinfo_attr("cpu family", buffer, sizeof(buffer)); if (ret == -1) return PFMLIB_ERR_NOTSUPP; family = atoi(buffer); return check_arch_pmu(family); } static int pfm_gen_ia32_init(void) { union { unsigned int val; pmu_eax_t eax; pmu_edx_t edx; } eax, ecx, edx, ebx; unsigned int num_cnt, i; int ret; /* * extract architected PMU information */ if (forced_pmu == PFMLIB_NO_PMU) { cpuid(0xa, &eax.val, &ebx.val, &ecx.val, &edx.val); } else { /* * when forced, simulate v2 * with 2 generic and 3 fixed counters */ eax.eax.version = 3; eax.eax.num_cnt = 2; eax.eax.cnt_width = 40; eax.eax.ebx_length = 0; /* unused */ ebx.val = 0; edx.edx.num_cnt = 3; edx.edx.cnt_width = 40; } num_cnt = eax.eax.num_cnt; pmu_version = eax.eax.version; /* * populate impl_pm* bitmasks for generic counters */ for(i=0; i < num_cnt; i++) { pfm_regmask_set(&gen_ia32_impl_pmcs, i); pfm_regmask_set(&gen_ia32_impl_pmds, i); } /* check for fixed counters */ if (pmu_version >= 2) { /* * As described in IA-32 Developer's manual vol 3b * in section 18.12.2.1, early processors supporting * V2 may report invalid information concerning the fixed * counters. So we compensate for this here by forcing * num_cnt to 3. */ if (edx.edx.num_cnt == 0) edx.edx.num_cnt = 3; for(i=0; i < edx.edx.num_cnt; i++) pfm_regmask_set(&gen_ia32_impl_pmds, FIXED_PMD_BASE+i); if (i) pfm_regmask_set(&gen_ia32_impl_pmcs, 16); } num_gen_cnt = eax.eax.num_cnt; num_fixed_cnt = edx.edx.num_cnt; gen_ia32_support.pmc_count = num_gen_cnt + (num_fixed_cnt > 0); gen_ia32_support.pmd_count = num_gen_cnt + num_fixed_cnt; gen_ia32_support.num_cnt = num_gen_cnt + num_fixed_cnt; __pfm_vbprintf("Intel architected PMU: version=%d num_gen=%u num_fixed=%u pmc=%u pmd=%d\n", pmu_version, num_gen_cnt,num_fixed_cnt, gen_ia32_support.pmc_count, gen_ia32_support.pmd_count); ret = create_arch_event_table(ebx.val); if (ret != PFMLIB_SUCCESS) return ret; gen_support = &gen_ia32_support; return PFMLIB_SUCCESS; } static int pfm_gen_ia32_dispatch_counters_v1(pfmlib_input_param_t *inp, pfmlib_gen_ia32_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfmlib_gen_ia32_input_param_t *param = mod_in; pfmlib_gen_ia32_counter_t *cntrs; pfm_gen_ia32_sel_reg_t reg; pfmlib_event_t *e; pfmlib_reg_t *pc, *pd; pfmlib_regmask_t *r_pmcs; unsigned long plm; unsigned int i, j, cnt, k, ucode, val; unsigned int assign[PMU_GEN_IA32_MAX_COUNTERS]; e = inp->pfp_events; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; cnt = inp->pfp_event_count; r_pmcs = &inp->pfp_unavail_pmcs; cntrs = param ? param->pfp_gen_ia32_counters : NULL; if (PFMLIB_DEBUG()) { for (j=0; j < cnt; j++) { DPRINT("ev[%d]=%s\n", j, gen_ia32_pe[e[j].event].pme_name); } } if (cnt > gen_support->pmd_count) return PFMLIB_ERR_TOOMANY; for(i=0, j=0; j < cnt; j++) { if (e[j].plm & (PFM_PLM1|PFM_PLM2)) { DPRINT("event=%d invalid plm=%d\n", e[j].event, e[j].plm); return PFMLIB_ERR_INVAL; } if (e[j].flags & ~PFMLIB_GEN_IA32_ALL_FLAGS) { DPRINT("event=%d invalid flags=0x%lx\n", e[j].event, e[j].flags); return PFMLIB_ERR_INVAL; } if (cntrs && pmu_version != 3 && (cntrs[j].flags & PFM_GEN_IA32_SEL_ANYTHR)) { DPRINT("event=%d anythread requires architectural perfmon v3", e[j].event); return PFMLIB_ERR_INVAL; } /* * exclude restricted registers from assignment */ while(i < gen_support->pmc_count && pfm_regmask_isset(r_pmcs, i)) i++; if (i == gen_support->pmc_count) return PFMLIB_ERR_TOOMANY; /* * events can be assigned to any counter */ assign[j] = i++; } for (j=0; j < cnt ; j++ ) { reg.val = 0; /* assume reserved bits are zerooed */ /* if plm is 0, then assume not specified per-event and use default */ plm = e[j].plm ? e[j].plm : inp->pfp_dfl_plm; val = gen_ia32_pe[e[j].event].pme_code; reg.sel_event_select = val & 0xff; ucode = (val >> 8) & 0xff; for(k=0; k < e[j].num_masks; k++) ucode |= gen_ia32_pe[e[j].event].pme_umasks[e[j].unit_masks[k]].pme_ucode; val |= ucode << 8; reg.sel_unit_mask = ucode; /* use 8 least significant bits */ reg.sel_usr = plm & PFM_PLM3 ? 1 : 0; reg.sel_os = plm & PFM_PLM0 ? 1 : 0; reg.sel_en = 1; /* force enable bit to 1 */ reg.sel_int = 1; /* force APIC int to 1 */ reg.sel_cnt_mask = val >>24; reg.sel_inv = val >> 23; reg.sel_any = val >> 21;; reg.sel_edge = val >> 18; if (cntrs) { if (!reg.sel_cnt_mask) { /* * counter mask is 8-bit wide, do not silently * wrap-around */ if (cntrs[i].cnt_mask > 255) return PFMLIB_ERR_INVAL; reg.sel_cnt_mask = cntrs[j].cnt_mask; } if (!reg.sel_edge) reg.sel_edge = cntrs[j].flags & PFM_GEN_IA32_SEL_EDGE ? 1 : 0; if (!reg.sel_inv) reg.sel_inv = cntrs[j].flags & PFM_GEN_IA32_SEL_INV ? 1 : 0; } pc[j].reg_num = assign[j]; pc[j].reg_addr = GEN_IA32_SEL_BASE+assign[j]; pc[j].reg_value = reg.val; pd[j].reg_num = assign[j]; pd[j].reg_addr = GEN_IA32_CTR_BASE+assign[j]; __pfm_vbprintf("[PERFEVTSEL%u(pmc%u)=0x%llx event_sel=0x%x umask=0x%x os=%d usr=%d en=%d int=%d inv=%d edge=%d cnt_mask=%d] %s\n", assign[j], assign[j], reg.val, reg.sel_event_select, reg.sel_unit_mask, reg.sel_os, reg.sel_usr, reg.sel_en, reg.sel_int, reg.sel_inv, reg.sel_edge, reg.sel_cnt_mask, gen_ia32_pe[e[j].event].pme_name); __pfm_vbprintf("[PMC%u(pmd%u)]\n", pd[j].reg_num, pd[j].reg_num); } /* number of evtsel registers programmed */ outp->pfp_pmc_count = cnt; outp->pfp_pmd_count = cnt; return PFMLIB_SUCCESS; } static const char *fixed_event_names[]={ "INSTRUCTIONS_RETIRED", "UNHALTED_CORE_CYCLES ", "UNHALTED_REFERENCE_CYCLES " }; #define MAX_EVENT_NAMES (sizeof(fixed_event_names)/sizeof(char *)) static int pfm_gen_ia32_dispatch_counters_v23(pfmlib_input_param_t *inp, pfmlib_gen_ia32_input_param_t *param, pfmlib_output_param_t *outp) { #define HAS_OPTIONS(x) (cntrs && (cntrs[i].flags || cntrs[i].cnt_mask)) #define is_fixed_pmc(a) (a > 15) pfmlib_gen_ia32_counter_t *cntrs; pfm_gen_ia32_sel_reg_t reg; pfmlib_event_t *e; pfmlib_reg_t *pc, *pd; pfmlib_regmask_t *r_pmcs; uint64_t val; unsigned long plm; unsigned int fixed_ctr_mask; unsigned int npc = 0; unsigned int i, j, n, k, ucode; unsigned int assign[PMU_GEN_IA32_MAX_COUNTERS]; unsigned int next_gen, last_gen; e = inp->pfp_events; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; n = inp->pfp_event_count; r_pmcs = &inp->pfp_unavail_pmcs; cntrs = param ? param->pfp_gen_ia32_counters : NULL; if (n > gen_support->pmd_count) return PFMLIB_ERR_TOOMANY; /* * initilize to empty */ for(i=0; i < n; i++) assign[i] = -1; /* * error checking */ for(j=0; j < n; j++) { /* * only supports two priv levels for perf counters */ if (e[j].plm & (PFM_PLM1|PFM_PLM2)) return PFMLIB_ERR_INVAL; /* * check for valid flags */ if (cntrs && cntrs[j].flags & ~PFMLIB_GEN_IA32_ALL_FLAGS) return PFMLIB_ERR_INVAL; if (cntrs && pmu_version != 3 && (cntrs[j].flags & PFM_GEN_IA32_SEL_ANYTHR)) { DPRINT("event=%d anythread requires architectural perfmon v3", e[j].event); return PFMLIB_ERR_INVAL; } } next_gen = 0; /* first generic counter */ last_gen = num_gen_cnt - 1; /* last generic counter */ fixed_ctr_mask = (1 << num_fixed_cnt) - 1; /* * first constraint: fixed counters (try using them first) */ if (fixed_ctr_mask) { for(i=0; i < n; i++) { /* fixed counters do not support event options (filters) */ if (HAS_OPTIONS(i)) { if (pmu_version != 3) continue; if (cntrs[i].flags != PFM_GEN_IA32_SEL_ANYTHR) continue; /* ok for ANYTHR */ } for(j=0; j < num_fixed_cnt; j++) { if ((fixed_ctr_mask & (1<pfp_dfl_plm; if (plm & PFM_PLM0) val |= 1ULL; if (plm & PFM_PLM3) val |= 2ULL; /* only possible for v3 */ if (cntrs && cntrs[i].flags & PFM_GEN_IA32_SEL_ANYTHR) val |= 4ULL; val |= 1ULL << 3; /* force APIC int (kernel may force it anyway) */ reg.val |= val << ((assign[i]-FIXED_PMD_BASE)<<2); /* setup pd array */ pd[i].reg_num = assign[i]; pd[i].reg_addr = GEN_IA32_FIXED_CTR_BASE+assign[i]-FIXED_PMD_BASE; } if (reg.val) { pc[npc].reg_num = 16; pc[npc].reg_value = reg.val; pc[npc].reg_addr = 0x38D; __pfm_vbprintf("[FIXED_CTRL(pmc%u)=0x%"PRIx64, pc[npc].reg_num, reg.val); for(i=0; i < num_fixed_cnt; i++) { if (pmu_version != 3) __pfm_vbprintf(" pmi%d=1 en%d=0x%"PRIx64, i, i, (reg.val >> (i*4)) & 0x3ULL); else __pfm_vbprintf(" pmi%d=1 en%d=0x%"PRIx64 " any%d=%"PRId64, i, i, (reg.val >> (i*4)) & 0x3ULL, i, !!((reg.val >> (i*4)) & 0x4ULL)); } __pfm_vbprintf("] "); for(i=0; i < num_fixed_cnt; i++) { if ((fixed_ctr_mask & (0x1 << i)) == 0) { if (i < MAX_EVENT_NAMES) __pfm_vbprintf("%s ", fixed_event_names[i]); else __pfm_vbprintf("??? "); } } __pfm_vbprintf("\n"); npc++; for (i=0; i < n ; i++ ) { if (!is_fixed_pmc(assign[i])) continue; __pfm_vbprintf("[FIXED_CTR%u(pmd%u)]\n", pd[i].reg_num, pd[i].reg_num); } } for (i=0; i < n ; i++ ) { /* skip fixed counters */ if (is_fixed_pmc(assign[i])) continue; reg.val = 0; /* assume reserved bits are zerooed */ /* if plm is 0, then assume not specified per-event and use default */ plm = e[i].plm ? e[i].plm : inp->pfp_dfl_plm; val = gen_ia32_pe[e[i].event].pme_code; reg.sel_event_select = val & 0xff; ucode = (val >> 8) & 0xff; for(k=0; k < e[i].num_masks; k++) ucode |= gen_ia32_pe[e[i].event].pme_umasks[e[i].unit_masks[k]].pme_ucode; val |= ucode << 8; reg.sel_unit_mask = ucode; reg.sel_usr = plm & PFM_PLM3 ? 1 : 0; reg.sel_os = plm & PFM_PLM0 ? 1 : 0; reg.sel_en = 1; /* force enable bit to 1 */ reg.sel_int = 1; /* force APIC int to 1 */ reg.sel_cnt_mask = val >>24; reg.sel_inv = val >> 23; reg.sel_any = val >> 21;; reg.sel_edge = val >> 18; if (cntrs) { if (!reg.sel_cnt_mask) { /* * counter mask is 8-bit wide, do not silently * wrap-around */ if (cntrs[i].cnt_mask > 255) return PFMLIB_ERR_INVAL; reg.sel_cnt_mask = cntrs[i].cnt_mask; } if (!reg.sel_edge) reg.sel_edge = cntrs[i].flags & PFM_GEN_IA32_SEL_EDGE ? 1 : 0; if (!reg.sel_inv) reg.sel_inv = cntrs[i].flags & PFM_GEN_IA32_SEL_INV ? 1 : 0; if (!reg.sel_any) reg.sel_any = cntrs[i].flags & PFM_GEN_IA32_SEL_ANYTHR? 1 : 0; } pc[npc].reg_num = assign[i]; pc[npc].reg_value = reg.val; pc[npc].reg_addr = GEN_IA32_SEL_BASE+assign[i]; pd[i].reg_num = assign[i]; pd[i].reg_addr = GEN_IA32_CTR_BASE+assign[i]; if (pmu_version < 3) __pfm_vbprintf("[PERFEVTSEL%u(pmc%u)=0x%"PRIx64" event_sel=0x%x umask=0x%x os=%d usr=%d en=%d int=%d inv=%d edge=%d cnt_mask=%d] %s\n", pc[npc].reg_num, pc[npc].reg_num, reg.val, reg.sel_event_select, reg.sel_unit_mask, reg.sel_os, reg.sel_usr, reg.sel_en, reg.sel_int, reg.sel_inv, reg.sel_edge, reg.sel_cnt_mask, gen_ia32_pe[e[i].event].pme_name); else __pfm_vbprintf("[PERFEVTSEL%u(pmc%u)=0x%"PRIx64" event_sel=0x%x umask=0x%x os=%d usr=%d en=%d int=%d inv=%d edge=%d cnt_mask=%d anythr=%d] %s\n", pc[npc].reg_num, pc[npc].reg_num, reg.val, reg.sel_event_select, reg.sel_unit_mask, reg.sel_os, reg.sel_usr, reg.sel_en, reg.sel_int, reg.sel_inv, reg.sel_edge, reg.sel_cnt_mask, reg.sel_any, gen_ia32_pe[e[i].event].pme_name); __pfm_vbprintf("[PMC%u(pmd%u)]\n", pd[i].reg_num, pd[i].reg_num); npc++; } /* number of evtsel/ctr registers programmed */ outp->pfp_pmc_count = npc; outp->pfp_pmd_count = n; return PFMLIB_SUCCESS; } static int pfm_gen_ia32_dispatch_events(pfmlib_input_param_t *inp, void *model_in, pfmlib_output_param_t *outp, void *model_out) { pfmlib_gen_ia32_input_param_t *mod_in = model_in; if (inp->pfp_dfl_plm & (PFM_PLM1|PFM_PLM2)) { DPRINT("invalid plm=%x\n", inp->pfp_dfl_plm); return PFMLIB_ERR_INVAL; } /* simplfied v1 (no fixed counters */ if (pmu_version == 1) return pfm_gen_ia32_dispatch_counters_v1(inp, mod_in, outp); /* v2 or above */ return pfm_gen_ia32_dispatch_counters_v23(inp, mod_in, outp); } static int pfm_gen_ia32_get_event_code(unsigned int i, unsigned int cnt, int *code) { if (cnt != PFMLIB_CNT_FIRST && cnt > gen_support->pmc_count) return PFMLIB_ERR_INVAL; *code = gen_ia32_pe[i].pme_code; return PFMLIB_SUCCESS; } static void pfm_gen_ia32_get_event_counters(unsigned int j, pfmlib_regmask_t *counters) { unsigned int i; memset(counters, 0, sizeof(*counters)); for(i=0; i < num_gen_cnt; i++) pfm_regmask_set(counters, i); for(i=0; i < num_fixed_cnt; i++) { if (gen_ia32_pe[j].pme_fixed == (FIXED_PMD_BASE+i)) pfm_regmask_set(counters, FIXED_PMD_BASE+i); } } static void pfm_gen_ia32_get_impl_pmcs(pfmlib_regmask_t *impl_pmcs) { *impl_pmcs = gen_ia32_impl_pmcs; } static void pfm_gen_ia32_get_impl_pmds(pfmlib_regmask_t *impl_pmds) { *impl_pmds = gen_ia32_impl_pmds; } static void pfm_gen_ia32_get_impl_counters(pfmlib_regmask_t *impl_counters) { /* all pmds are counters */ *impl_counters = gen_ia32_impl_pmds; } static void pfm_gen_ia32_get_hw_counter_width(unsigned int *width) { /* * Even though, CPUID 0xa returns in eax the actual counter * width, the architecture specifies that writes are limited * to lower 32-bits. As such, only the lower 31 bits have full * degree of freedom. That is the "useable" counter width. */ *width = PMU_GEN_IA32_COUNTER_WIDTH; } static char * pfm_gen_ia32_get_event_name(unsigned int i) { return gen_ia32_pe[i].pme_name; } static int pfm_gen_ia32_get_event_description(unsigned int ev, char **str) { char *s; s = gen_ia32_pe[ev].pme_desc; if (s) { *str = strdup(s); } else { *str = NULL; } return PFMLIB_SUCCESS; } static char * pfm_gen_ia32_get_event_mask_name(unsigned int ev, unsigned int midx) { return gen_ia32_pe[ev].pme_umasks[midx].pme_uname; } static int pfm_gen_ia32_get_event_mask_desc(unsigned int ev, unsigned int midx, char **str) { char *s; s = gen_ia32_pe[ev].pme_umasks[midx].pme_udesc; if (s) { *str = strdup(s); } else { *str = NULL; } return PFMLIB_SUCCESS; } static unsigned int pfm_gen_ia32_get_num_event_masks(unsigned int ev) { return gen_ia32_pe[ev].pme_numasks; } static int pfm_gen_ia32_get_event_mask_code(unsigned int ev, unsigned int midx, unsigned int *code) { *code =gen_ia32_pe[ev].pme_umasks[midx].pme_ucode; return PFMLIB_SUCCESS; } static int pfm_gen_ia32_get_cycle_event(pfmlib_event_t *e) { if (gen_ia32_cycle_event == -1) return PFMLIB_ERR_NOTSUPP; e->event = gen_ia32_cycle_event; return PFMLIB_SUCCESS; } static int pfm_gen_ia32_get_inst_retired(pfmlib_event_t *e) { if (gen_ia32_inst_retired_event == -1) return PFMLIB_ERR_NOTSUPP; e->event = gen_ia32_inst_retired_event; return PFMLIB_SUCCESS; } /* architected PMU */ pfm_pmu_support_t gen_ia32_support={ .pmu_name = "Intel architectural PMU", .pmu_type = PFMLIB_GEN_IA32_PMU, .pme_count = 0, .pmc_count = 0, .pmd_count = 0, .num_cnt = 0, .get_event_code = pfm_gen_ia32_get_event_code, .get_event_name = pfm_gen_ia32_get_event_name, .get_event_counters = pfm_gen_ia32_get_event_counters, .dispatch_events = pfm_gen_ia32_dispatch_events, .pmu_detect = pfm_gen_ia32_detect, .pmu_init = pfm_gen_ia32_init, .get_impl_pmcs = pfm_gen_ia32_get_impl_pmcs, .get_impl_pmds = pfm_gen_ia32_get_impl_pmds, .get_impl_counters = pfm_gen_ia32_get_impl_counters, .get_hw_counter_width = pfm_gen_ia32_get_hw_counter_width, .get_event_desc = pfm_gen_ia32_get_event_description, .get_cycle_event = pfm_gen_ia32_get_cycle_event, .get_inst_retired_event = pfm_gen_ia32_get_inst_retired, .get_num_event_masks = pfm_gen_ia32_get_num_event_masks, .get_event_mask_name = pfm_gen_ia32_get_event_mask_name, .get_event_mask_code = pfm_gen_ia32_get_event_mask_code, .get_event_mask_desc = pfm_gen_ia32_get_event_mask_desc }; papi-5.5.1/src/libpfm-3.y/lib/power5+_events.h0000644000307100002310000140036713013651450020734 0ustar yarkhangraduate/****************************/ /* THIS IS OPEN SOURCE CODE */ /****************************/ #ifndef __POWER5p_EVENTS_H__ #define __POWER5p_EVENTS_H__ /* * File: power5+_events.h * CVS: * Author: Corey Ashford * cjashfor@us.ibm.com * Mods: * * * (C) Copyright IBM Corporation, 2007. All Rights Reserved. * Contributed by Corey Ashford * * Note: This code was automatically generated and should not be modified by * hand. * */ #define POWER5p_PME_PM_LSU_REJECT_RELOAD_CDF 0 #define POWER5p_PME_PM_FPU1_SINGLE 1 #define POWER5p_PME_PM_L3SB_REF 2 #define POWER5p_PME_PM_THRD_PRIO_DIFF_3or4_CYC 3 #define POWER5p_PME_PM_INST_FROM_L275_SHR 4 #define POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD 5 #define POWER5p_PME_PM_DTLB_MISS_4K 6 #define POWER5p_PME_PM_CLB_FULL_CYC 7 #define POWER5p_PME_PM_MRK_ST_CMPL 8 #define POWER5p_PME_PM_LSU_FLUSH_LRQ_FULL 9 #define POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR 10 #define POWER5p_PME_PM_1INST_CLB_CYC 11 #define POWER5p_PME_PM_MEM_SPEC_RD_CANCEL 12 #define POWER5p_PME_PM_MRK_DTLB_MISS_16M 13 #define POWER5p_PME_PM_FPU_FDIV 14 #define POWER5p_PME_PM_FPU_SINGLE 15 #define POWER5p_PME_PM_FPU0_FMA 16 #define POWER5p_PME_PM_SLB_MISS 17 #define POWER5p_PME_PM_LSU1_FLUSH_LRQ 18 #define POWER5p_PME_PM_L2SA_ST_HIT 19 #define POWER5p_PME_PM_DTLB_MISS 20 #define POWER5p_PME_PM_BR_PRED_TA 21 #define POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD_CYC 22 #define POWER5p_PME_PM_CMPLU_STALL_FXU 23 #define POWER5p_PME_PM_EXT_INT 24 #define POWER5p_PME_PM_MRK_LSU1_FLUSH_LRQ 25 #define POWER5p_PME_PM_MRK_ST_GPS 26 #define POWER5p_PME_PM_LSU1_LDF 27 #define POWER5p_PME_PM_FAB_CMD_ISSUED 28 #define POWER5p_PME_PM_LSU0_SRQ_STFWD 29 #define POWER5p_PME_PM_CR_MAP_FULL_CYC 30 #define POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL 31 #define POWER5p_PME_PM_MRK_LSU0_FLUSH_ULD 32 #define POWER5p_PME_PM_LSU_FLUSH_SRQ_FULL 33 #define POWER5p_PME_PM_MEM_RQ_DISP_Q16to19 34 #define POWER5p_PME_PM_FLUSH_IMBAL 35 #define POWER5p_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC 36 #define POWER5p_PME_PM_DATA_FROM_L35_MOD 37 #define POWER5p_PME_PM_MEM_HI_PRIO_WR_CMPL 38 #define POWER5p_PME_PM_FPU1_FDIV 39 #define POWER5p_PME_PM_MEM_RQ_DISP 40 #define POWER5p_PME_PM_FPU0_FRSP_FCONV 41 #define POWER5p_PME_PM_LWSYNC_HELD 42 #define POWER5p_PME_PM_FXU_FIN 43 #define POWER5p_PME_PM_DSLB_MISS 44 #define POWER5p_PME_PM_DATA_FROM_L275_SHR 45 #define POWER5p_PME_PM_FXLS1_FULL_CYC 46 #define POWER5p_PME_PM_THRD_SEL_T0 47 #define POWER5p_PME_PM_PTEG_RELOAD_VALID 48 #define POWER5p_PME_PM_MRK_STCX_FAIL 49 #define POWER5p_PME_PM_LSU_LMQ_LHR_MERGE 50 #define POWER5p_PME_PM_2INST_CLB_CYC 51 #define POWER5p_PME_PM_FAB_PNtoVN_DIRECT 52 #define POWER5p_PME_PM_PTEG_FROM_L2MISS 53 #define POWER5p_PME_PM_CMPLU_STALL_LSU 54 #define POWER5p_PME_PM_MRK_DSLB_MISS 55 #define POWER5p_PME_PM_LSU_FLUSH_ULD 56 #define POWER5p_PME_PM_PTEG_FROM_LMEM 57 #define POWER5p_PME_PM_MRK_BRU_FIN 58 #define POWER5p_PME_PM_MEM_WQ_DISP_WRITE 59 #define POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD_CYC 60 #define POWER5p_PME_PM_LSU1_NCLD 61 #define POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER 62 #define POWER5p_PME_PM_SNOOP_PW_RETRY_WQ_PWQ 63 #define POWER5p_PME_PM_FPU1_FULL_CYC 64 #define POWER5p_PME_PM_FPR_MAP_FULL_CYC 65 #define POWER5p_PME_PM_L3SA_ALL_BUSY 66 #define POWER5p_PME_PM_3INST_CLB_CYC 67 #define POWER5p_PME_PM_MEM_PWQ_DISP_Q2or3 68 #define POWER5p_PME_PM_L2SA_SHR_INV 69 #define POWER5p_PME_PM_THRESH_TIMEO 70 #define POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL 71 #define POWER5p_PME_PM_THRD_SEL_OVER_GCT_IMBAL 72 #define POWER5p_PME_PM_FPU_FSQRT 73 #define POWER5p_PME_PM_PMC1_OVERFLOW 74 #define POWER5p_PME_PM_MRK_LSU0_FLUSH_LRQ 75 #define POWER5p_PME_PM_L3SC_SNOOP_RETRY 76 #define POWER5p_PME_PM_DATA_TABLEWALK_CYC 77 #define POWER5p_PME_PM_THRD_PRIO_6_CYC 78 #define POWER5p_PME_PM_FPU_FEST 79 #define POWER5p_PME_PM_FAB_M1toP1_SIDECAR_EMPTY 80 #define POWER5p_PME_PM_MRK_DATA_FROM_RMEM 81 #define POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD_CYC 82 #define POWER5p_PME_PM_MEM_PWQ_DISP 83 #define POWER5p_PME_PM_FAB_P1toM1_SIDECAR_EMPTY 84 #define POWER5p_PME_PM_LD_MISS_L1_LSU0 85 #define POWER5p_PME_PM_SNOOP_PARTIAL_RTRY_QFULL 86 #define POWER5p_PME_PM_FPU1_STALL3 87 #define POWER5p_PME_PM_GCT_USAGE_80to99_CYC 88 #define POWER5p_PME_PM_WORK_HELD 89 #define POWER5p_PME_PM_INST_CMPL 90 #define POWER5p_PME_PM_LSU1_FLUSH_UST 91 #define POWER5p_PME_PM_FXU_IDLE 92 #define POWER5p_PME_PM_LSU0_FLUSH_ULD 93 #define POWER5p_PME_PM_LSU1_REJECT_LMQ_FULL 94 #define POWER5p_PME_PM_GRP_DISP_REJECT 95 #define POWER5p_PME_PM_PTEG_FROM_L25_SHR 96 #define POWER5p_PME_PM_L2SA_MOD_INV 97 #define POWER5p_PME_PM_FAB_CMD_RETRIED 98 #define POWER5p_PME_PM_L3SA_SHR_INV 99 #define POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL 100 #define POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_ADDR 101 #define POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_RC_FULL 102 #define POWER5p_PME_PM_PTEG_FROM_L375_MOD 103 #define POWER5p_PME_PM_MRK_LSU1_FLUSH_UST 104 #define POWER5p_PME_PM_BR_ISSUED 105 #define POWER5p_PME_PM_MRK_GRP_BR_REDIR 106 #define POWER5p_PME_PM_EE_OFF 107 #define POWER5p_PME_PM_IERAT_XLATE_WR_LP 108 #define POWER5p_PME_PM_DTLB_REF_64K 109 #define POWER5p_PME_PM_MEM_RQ_DISP_Q4to7 110 #define POWER5p_PME_PM_MEM_FAST_PATH_RD_DISP 111 #define POWER5p_PME_PM_INST_FROM_L3 112 #define POWER5p_PME_PM_ITLB_MISS 113 #define POWER5p_PME_PM_FXU1_BUSY_FXU0_IDLE 114 #define POWER5p_PME_PM_DTLB_REF_4K 115 #define POWER5p_PME_PM_FXLS_FULL_CYC 116 #define POWER5p_PME_PM_GRP_DISP_VALID 117 #define POWER5p_PME_PM_LSU_FLUSH_UST 118 #define POWER5p_PME_PM_FXU1_FIN 119 #define POWER5p_PME_PM_THRD_PRIO_4_CYC 120 #define POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD 121 #define POWER5p_PME_PM_4INST_CLB_CYC 122 #define POWER5p_PME_PM_MRK_DTLB_REF_16M 123 #define POWER5p_PME_PM_INST_FROM_L375_MOD 124 #define POWER5p_PME_PM_GRP_CMPL 125 #define POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_ADDR 126 #define POWER5p_PME_PM_FPU1_1FLOP 127 #define POWER5p_PME_PM_FPU_FRSP_FCONV 128 #define POWER5p_PME_PM_L3SC_REF 129 #define POWER5p_PME_PM_5INST_CLB_CYC 130 #define POWER5p_PME_PM_THRD_L2MISS_BOTH_CYC 131 #define POWER5p_PME_PM_MEM_PW_GATH 132 #define POWER5p_PME_PM_DTLB_REF_16G 133 #define POWER5p_PME_PM_FAB_DCLAIM_ISSUED 134 #define POWER5p_PME_PM_FAB_PNtoNN_SIDECAR 135 #define POWER5p_PME_PM_GRP_IC_MISS 136 #define POWER5p_PME_PM_INST_FROM_L35_SHR 137 #define POWER5p_PME_PM_LSU_LMQ_FULL_CYC 138 #define POWER5p_PME_PM_MRK_DATA_FROM_L2_CYC 139 #define POWER5p_PME_PM_LSU_SRQ_SYNC_CYC 140 #define POWER5p_PME_PM_LSU0_BUSY_REJECT 141 #define POWER5p_PME_PM_LSU_REJECT_ERAT_MISS 142 #define POWER5p_PME_PM_MRK_DATA_FROM_RMEM_CYC 143 #define POWER5p_PME_PM_DATA_FROM_L375_SHR 144 #define POWER5p_PME_PM_PTEG_FROM_L25_MOD 145 #define POWER5p_PME_PM_FPU0_FMOV_FEST 146 #define POWER5p_PME_PM_THRD_PRIO_7_CYC 147 #define POWER5p_PME_PM_LSU1_FLUSH_SRQ 148 #define POWER5p_PME_PM_LD_REF_L1_LSU0 149 #define POWER5p_PME_PM_L2SC_RCST_DISP 150 #define POWER5p_PME_PM_CMPLU_STALL_DIV 151 #define POWER5p_PME_PM_MEM_RQ_DISP_Q12to15 152 #define POWER5p_PME_PM_INST_FROM_L375_SHR 153 #define POWER5p_PME_PM_ST_REF_L1 154 #define POWER5p_PME_PM_L3SB_ALL_BUSY 155 #define POWER5p_PME_PM_FAB_P1toVNorNN_SIDECAR_EMPTY 156 #define POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR_CYC 157 #define POWER5p_PME_PM_FAB_HOLDtoNN_EMPTY 158 #define POWER5p_PME_PM_DATA_FROM_LMEM 159 #define POWER5p_PME_PM_RUN_CYC 160 #define POWER5p_PME_PM_PTEG_FROM_RMEM 161 #define POWER5p_PME_PM_L2SC_RCLD_DISP 162 #define POWER5p_PME_PM_LSU_LRQ_S0_VALID 163 #define POWER5p_PME_PM_LSU0_LDF 164 #define POWER5p_PME_PM_PMC3_OVERFLOW 165 #define POWER5p_PME_PM_MRK_IMR_RELOAD 166 #define POWER5p_PME_PM_MRK_GRP_TIMEO 167 #define POWER5p_PME_PM_ST_MISS_L1 168 #define POWER5p_PME_PM_STOP_COMPLETION 169 #define POWER5p_PME_PM_LSU_BUSY_REJECT 170 #define POWER5p_PME_PM_ISLB_MISS 171 #define POWER5p_PME_PM_CYC 172 #define POWER5p_PME_PM_THRD_ONE_RUN_CYC 173 #define POWER5p_PME_PM_GRP_BR_REDIR_NONSPEC 174 #define POWER5p_PME_PM_LSU1_SRQ_STFWD 175 #define POWER5p_PME_PM_L3SC_MOD_INV 176 #define POWER5p_PME_PM_L2_PREF 177 #define POWER5p_PME_PM_GCT_NOSLOT_BR_MPRED 178 #define POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD 179 #define POWER5p_PME_PM_L2SB_ST_REQ 180 #define POWER5p_PME_PM_L2SB_MOD_INV 181 #define POWER5p_PME_PM_MRK_L1_RELOAD_VALID 182 #define POWER5p_PME_PM_L3SB_HIT 183 #define POWER5p_PME_PM_L2SB_SHR_MOD 184 #define POWER5p_PME_PM_EE_OFF_EXT_INT 185 #define POWER5p_PME_PM_1PLUS_PPC_CMPL 186 #define POWER5p_PME_PM_L2SC_SHR_MOD 187 #define POWER5p_PME_PM_PMC6_OVERFLOW 188 #define POWER5p_PME_PM_IC_PREF_INSTALL 189 #define POWER5p_PME_PM_LSU_LRQ_FULL_CYC 190 #define POWER5p_PME_PM_TLB_MISS 191 #define POWER5p_PME_PM_GCT_FULL_CYC 192 #define POWER5p_PME_PM_FXU_BUSY 193 #define POWER5p_PME_PM_MRK_DATA_FROM_L3_CYC 194 #define POWER5p_PME_PM_LSU_REJECT_LMQ_FULL 195 #define POWER5p_PME_PM_LSU_SRQ_S0_ALLOC 196 #define POWER5p_PME_PM_GRP_MRK 197 #define POWER5p_PME_PM_INST_FROM_L25_SHR 198 #define POWER5p_PME_PM_DC_PREF_STREAM_ALLOC 199 #define POWER5p_PME_PM_FPU1_FIN 200 #define POWER5p_PME_PM_BR_MPRED_TA 201 #define POWER5p_PME_PM_MRK_DTLB_REF_64K 202 #define POWER5p_PME_PM_RUN_INST_CMPL 203 #define POWER5p_PME_PM_CRQ_FULL_CYC 204 #define POWER5p_PME_PM_L2SA_RCLD_DISP 205 #define POWER5p_PME_PM_SNOOP_WR_RETRY_QFULL 206 #define POWER5p_PME_PM_MRK_DTLB_REF_4K 207 #define POWER5p_PME_PM_LSU_SRQ_S0_VALID 208 #define POWER5p_PME_PM_LSU0_FLUSH_LRQ 209 #define POWER5p_PME_PM_INST_FROM_L275_MOD 210 #define POWER5p_PME_PM_GCT_EMPTY_CYC 211 #define POWER5p_PME_PM_LARX_LSU0 212 #define POWER5p_PME_PM_THRD_PRIO_DIFF_5or6_CYC 213 #define POWER5p_PME_PM_SNOOP_RETRY_1AHEAD 214 #define POWER5p_PME_PM_FPU1_FSQRT 215 #define POWER5p_PME_PM_MRK_LD_MISS_L1_LSU1 216 #define POWER5p_PME_PM_MRK_FPU_FIN 217 #define POWER5p_PME_PM_THRD_PRIO_5_CYC 218 #define POWER5p_PME_PM_MRK_DATA_FROM_LMEM 219 #define POWER5p_PME_PM_SNOOP_TLBIE 220 #define POWER5p_PME_PM_FPU1_FRSP_FCONV 221 #define POWER5p_PME_PM_DTLB_MISS_16G 222 #define POWER5p_PME_PM_L3SB_SNOOP_RETRY 223 #define POWER5p_PME_PM_FAB_VBYPASS_EMPTY 224 #define POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD 225 #define POWER5p_PME_PM_L2SB_RCST_DISP 226 #define POWER5p_PME_PM_6INST_CLB_CYC 227 #define POWER5p_PME_PM_FLUSH 228 #define POWER5p_PME_PM_L2SC_MOD_INV 229 #define POWER5p_PME_PM_FPU_DENORM 230 #define POWER5p_PME_PM_L3SC_HIT 231 #define POWER5p_PME_PM_SNOOP_WR_RETRY_RQ 232 #define POWER5p_PME_PM_LSU1_REJECT_SRQ 233 #define POWER5p_PME_PM_L3SC_ALL_BUSY 234 #define POWER5p_PME_PM_IC_PREF_REQ 235 #define POWER5p_PME_PM_MRK_GRP_IC_MISS 236 #define POWER5p_PME_PM_GCT_NOSLOT_IC_MISS 237 #define POWER5p_PME_PM_MRK_DATA_FROM_L3 238 #define POWER5p_PME_PM_GCT_NOSLOT_SRQ_FULL 239 #define POWER5p_PME_PM_CMPLU_STALL_DCACHE_MISS 240 #define POWER5p_PME_PM_THRD_SEL_OVER_ISU_HOLD 241 #define POWER5p_PME_PM_LSU_FLUSH_LRQ 242 #define POWER5p_PME_PM_THRD_PRIO_2_CYC 243 #define POWER5p_PME_PM_L3SA_MOD_INV 244 #define POWER5p_PME_PM_LSU_FLUSH_SRQ 245 #define POWER5p_PME_PM_MRK_LSU_SRQ_INST_VALID 246 #define POWER5p_PME_PM_L3SA_REF 247 #define POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL 248 #define POWER5p_PME_PM_FPU0_STALL3 249 #define POWER5p_PME_PM_TB_BIT_TRANS 250 #define POWER5p_PME_PM_GPR_MAP_FULL_CYC 251 #define POWER5p_PME_PM_MRK_LSU_FLUSH_LRQ 252 #define POWER5p_PME_PM_FPU0_STF 253 #define POWER5p_PME_PM_MRK_DTLB_MISS 254 #define POWER5p_PME_PM_FPU1_FMA 255 #define POWER5p_PME_PM_L2SA_MOD_TAG 256 #define POWER5p_PME_PM_LSU1_FLUSH_ULD 257 #define POWER5p_PME_PM_MRK_INST_FIN 258 #define POWER5p_PME_PM_MRK_LSU0_FLUSH_UST 259 #define POWER5p_PME_PM_FPU0_FULL_CYC 260 #define POWER5p_PME_PM_LSU_LRQ_S0_ALLOC 261 #define POWER5p_PME_PM_MRK_LSU1_FLUSH_ULD 262 #define POWER5p_PME_PM_MRK_DTLB_REF 263 #define POWER5p_PME_PM_BR_UNCOND 264 #define POWER5p_PME_PM_THRD_SEL_OVER_L2MISS 265 #define POWER5p_PME_PM_L2SB_SHR_INV 266 #define POWER5p_PME_PM_MEM_LO_PRIO_WR_CMPL 267 #define POWER5p_PME_PM_MRK_DTLB_MISS_64K 268 #define POWER5p_PME_PM_MRK_ST_MISS_L1 269 #define POWER5p_PME_PM_L3SC_MOD_TAG 270 #define POWER5p_PME_PM_GRP_DISP_SUCCESS 271 #define POWER5p_PME_PM_THRD_PRIO_DIFF_1or2_CYC 272 #define POWER5p_PME_PM_IC_DEMAND_L2_BHT_REDIRECT 273 #define POWER5p_PME_PM_LSU_DERAT_MISS 274 #define POWER5p_PME_PM_MEM_WQ_DISP_Q8to15 275 #define POWER5p_PME_PM_FPU0_SINGLE 276 #define POWER5p_PME_PM_THRD_PRIO_1_CYC 277 #define POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_OTHER 278 #define POWER5p_PME_PM_SNOOP_RD_RETRY_RQ 279 #define POWER5p_PME_PM_FAB_HOLDtoVN_EMPTY 280 #define POWER5p_PME_PM_FPU1_FEST 281 #define POWER5p_PME_PM_SNOOP_DCLAIM_RETRY_QFULL 282 #define POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR_CYC 283 #define POWER5p_PME_PM_MRK_ST_CMPL_INT 284 #define POWER5p_PME_PM_FLUSH_BR_MPRED 285 #define POWER5p_PME_PM_MRK_DTLB_MISS_16G 286 #define POWER5p_PME_PM_FPU_STF 287 #define POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR 288 #define POWER5p_PME_PM_CMPLU_STALL_FPU 289 #define POWER5p_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC 290 #define POWER5p_PME_PM_GCT_NOSLOT_CYC 291 #define POWER5p_PME_PM_FXU0_BUSY_FXU1_IDLE 292 #define POWER5p_PME_PM_PTEG_FROM_L35_SHR 293 #define POWER5p_PME_PM_MRK_DTLB_REF_16G 294 #define POWER5p_PME_PM_MRK_LSU_FLUSH_UST 295 #define POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR 296 #define POWER5p_PME_PM_L3SA_HIT 297 #define POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR 298 #define POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_ADDR 299 #define POWER5p_PME_PM_IERAT_XLATE_WR 300 #define POWER5p_PME_PM_L2SA_ST_REQ 301 #define POWER5p_PME_PM_INST_FROM_LMEM 302 #define POWER5p_PME_PM_THRD_SEL_T1 303 #define POWER5p_PME_PM_IC_DEMAND_L2_BR_REDIRECT 304 #define POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR_CYC 305 #define POWER5p_PME_PM_FPU0_1FLOP 306 #define POWER5p_PME_PM_PTEG_FROM_L2 307 #define POWER5p_PME_PM_MEM_PW_CMPL 308 #define POWER5p_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC 309 #define POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER 310 #define POWER5p_PME_PM_MRK_DTLB_MISS_4K 311 #define POWER5p_PME_PM_FPU0_FIN 312 #define POWER5p_PME_PM_L3SC_SHR_INV 313 #define POWER5p_PME_PM_GRP_BR_REDIR 314 #define POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL 315 #define POWER5p_PME_PM_MRK_LSU_FLUSH_SRQ 316 #define POWER5p_PME_PM_PTEG_FROM_L275_SHR 317 #define POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL 318 #define POWER5p_PME_PM_SNOOP_RD_RETRY_WQ 319 #define POWER5p_PME_PM_FAB_DCLAIM_RETRIED 320 #define POWER5p_PME_PM_LSU0_NCLD 321 #define POWER5p_PME_PM_LSU1_BUSY_REJECT 322 #define POWER5p_PME_PM_FXLS0_FULL_CYC 323 #define POWER5p_PME_PM_DTLB_REF_16M 324 #define POWER5p_PME_PM_FPU0_FEST 325 #define POWER5p_PME_PM_GCT_USAGE_60to79_CYC 326 #define POWER5p_PME_PM_DATA_FROM_L25_MOD 327 #define POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR 328 #define POWER5p_PME_PM_LSU0_REJECT_ERAT_MISS 329 #define POWER5p_PME_PM_DATA_FROM_L375_MOD 330 #define POWER5p_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 331 #define POWER5p_PME_PM_DTLB_MISS_64K 332 #define POWER5p_PME_PM_LSU0_REJECT_RELOAD_CDF 333 #define POWER5p_PME_PM_0INST_FETCH 334 #define POWER5p_PME_PM_LSU1_REJECT_RELOAD_CDF 335 #define POWER5p_PME_PM_MEM_WQ_DISP_Q0to7 336 #define POWER5p_PME_PM_L1_PREF 337 #define POWER5p_PME_PM_MRK_DATA_FROM_LMEM_CYC 338 #define POWER5p_PME_PM_BRQ_FULL_CYC 339 #define POWER5p_PME_PM_GRP_IC_MISS_NONSPEC 340 #define POWER5p_PME_PM_PTEG_FROM_L275_MOD 341 #define POWER5p_PME_PM_MRK_LD_MISS_L1_LSU0 342 #define POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR_CYC 343 #define POWER5p_PME_PM_DATA_FROM_L3 344 #define POWER5p_PME_PM_INST_FROM_L2 345 #define POWER5p_PME_PM_LSU_FLUSH 346 #define POWER5p_PME_PM_PMC2_OVERFLOW 347 #define POWER5p_PME_PM_FPU0_DENORM 348 #define POWER5p_PME_PM_FPU1_FMOV_FEST 349 #define POWER5p_PME_PM_INST_FETCH_CYC 350 #define POWER5p_PME_PM_INST_DISP 351 #define POWER5p_PME_PM_LSU_LDF 352 #define POWER5p_PME_PM_DATA_FROM_L25_SHR 353 #define POWER5p_PME_PM_L1_DCACHE_RELOAD_VALID 354 #define POWER5p_PME_PM_MEM_WQ_DISP_DCLAIM 355 #define POWER5p_PME_PM_MRK_GRP_ISSUED 356 #define POWER5p_PME_PM_FPU_FULL_CYC 357 #define POWER5p_PME_PM_INST_FROM_L35_MOD 358 #define POWER5p_PME_PM_FPU_FMA 359 #define POWER5p_PME_PM_THRD_PRIO_3_CYC 360 #define POWER5p_PME_PM_MRK_CRU_FIN 361 #define POWER5p_PME_PM_SNOOP_WR_RETRY_WQ 362 #define POWER5p_PME_PM_CMPLU_STALL_REJECT 363 #define POWER5p_PME_PM_MRK_FXU_FIN 364 #define POWER5p_PME_PM_LSU1_REJECT_ERAT_MISS 365 #define POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_OTHER 366 #define POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY 367 #define POWER5p_PME_PM_PMC4_OVERFLOW 368 #define POWER5p_PME_PM_L3SA_SNOOP_RETRY 369 #define POWER5p_PME_PM_PTEG_FROM_L35_MOD 370 #define POWER5p_PME_PM_INST_FROM_L25_MOD 371 #define POWER5p_PME_PM_THRD_SMT_HANG 372 #define POWER5p_PME_PM_CMPLU_STALL_ERAT_MISS 373 #define POWER5p_PME_PM_L3SA_MOD_TAG 374 #define POWER5p_PME_PM_INST_FROM_L2MISS 375 #define POWER5p_PME_PM_FLUSH_SYNC 376 #define POWER5p_PME_PM_MRK_GRP_DISP 377 #define POWER5p_PME_PM_MEM_RQ_DISP_Q8to11 378 #define POWER5p_PME_PM_L2SC_ST_HIT 379 #define POWER5p_PME_PM_L2SB_MOD_TAG 380 #define POWER5p_PME_PM_CLB_EMPTY_CYC 381 #define POWER5p_PME_PM_L2SB_ST_HIT 382 #define POWER5p_PME_PM_MEM_NONSPEC_RD_CANCEL 383 #define POWER5p_PME_PM_BR_PRED_CR_TA 384 #define POWER5p_PME_PM_MRK_LSU0_FLUSH_SRQ 385 #define POWER5p_PME_PM_MRK_LSU_FLUSH_ULD 386 #define POWER5p_PME_PM_INST_DISP_ATTEMPT 387 #define POWER5p_PME_PM_INST_FROM_RMEM 388 #define POWER5p_PME_PM_ST_REF_L1_LSU0 389 #define POWER5p_PME_PM_LSU0_DERAT_MISS 390 #define POWER5p_PME_PM_FPU_STALL3 391 #define POWER5p_PME_PM_L2SB_RCLD_DISP 392 #define POWER5p_PME_PM_BR_PRED_CR 393 #define POWER5p_PME_PM_MRK_DATA_FROM_L2 394 #define POWER5p_PME_PM_LSU0_FLUSH_SRQ 395 #define POWER5p_PME_PM_FAB_PNtoNN_DIRECT 396 #define POWER5p_PME_PM_IOPS_CMPL 397 #define POWER5p_PME_PM_L2SA_RCST_DISP 398 #define POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_OTHER 399 #define POWER5p_PME_PM_L2SC_SHR_INV 400 #define POWER5p_PME_PM_SNOOP_RETRY_AB_COLLISION 401 #define POWER5p_PME_PM_FAB_PNtoVN_SIDECAR 402 #define POWER5p_PME_PM_LSU0_REJECT_LMQ_FULL 403 #define POWER5p_PME_PM_LSU_LMQ_S0_ALLOC 404 #define POWER5p_PME_PM_SNOOP_PW_RETRY_RQ 405 #define POWER5p_PME_PM_DTLB_REF 406 #define POWER5p_PME_PM_PTEG_FROM_L3 407 #define POWER5p_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY 408 #define POWER5p_PME_PM_LSU_SRQ_EMPTY_CYC 409 #define POWER5p_PME_PM_FPU1_STF 410 #define POWER5p_PME_PM_LSU_LMQ_S0_VALID 411 #define POWER5p_PME_PM_GCT_USAGE_00to59_CYC 412 #define POWER5p_PME_PM_FPU_FMOV_FEST 413 #define POWER5p_PME_PM_DATA_FROM_L2MISS 414 #define POWER5p_PME_PM_XER_MAP_FULL_CYC 415 #define POWER5p_PME_PM_GRP_DISP_BLK_SB_CYC 416 #define POWER5p_PME_PM_FLUSH_SB 417 #define POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR 418 #define POWER5p_PME_PM_MRK_GRP_CMPL 419 #define POWER5p_PME_PM_SUSPENDED 420 #define POWER5p_PME_PM_SNOOP_RD_RETRY_QFULL 421 #define POWER5p_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC 422 #define POWER5p_PME_PM_DATA_FROM_L35_SHR 423 #define POWER5p_PME_PM_L3SB_MOD_INV 424 #define POWER5p_PME_PM_STCX_FAIL 425 #define POWER5p_PME_PM_LD_MISS_L1_LSU1 426 #define POWER5p_PME_PM_GRP_DISP 427 #define POWER5p_PME_PM_DC_PREF_DST 428 #define POWER5p_PME_PM_FPU1_DENORM 429 #define POWER5p_PME_PM_FPU0_FPSCR 430 #define POWER5p_PME_PM_DATA_FROM_L2 431 #define POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR 432 #define POWER5p_PME_PM_FPU_1FLOP 433 #define POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER 434 #define POWER5p_PME_PM_FPU0_FSQRT 435 #define POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL 436 #define POWER5p_PME_PM_LD_REF_L1 437 #define POWER5p_PME_PM_INST_FROM_L1 438 #define POWER5p_PME_PM_TLBIE_HELD 439 #define POWER5p_PME_PM_DC_PREF_OUT_OF_STREAMS 440 #define POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD_CYC 441 #define POWER5p_PME_PM_MRK_LSU1_FLUSH_SRQ 442 #define POWER5p_PME_PM_MEM_RQ_DISP_Q0to3 443 #define POWER5p_PME_PM_ST_REF_L1_LSU1 444 #define POWER5p_PME_PM_MRK_LD_MISS_L1 445 #define POWER5p_PME_PM_L1_WRITE_CYC 446 #define POWER5p_PME_PM_L2SC_ST_REQ 447 #define POWER5p_PME_PM_CMPLU_STALL_FDIV 448 #define POWER5p_PME_PM_THRD_SEL_OVER_CLB_EMPTY 449 #define POWER5p_PME_PM_BR_MPRED_CR 450 #define POWER5p_PME_PM_L3SB_MOD_TAG 451 #define POWER5p_PME_PM_MRK_DATA_FROM_L2MISS 452 #define POWER5p_PME_PM_LSU_REJECT_SRQ 453 #define POWER5p_PME_PM_LD_MISS_L1 454 #define POWER5p_PME_PM_INST_FROM_PREF 455 #define POWER5p_PME_PM_STCX_PASS 456 #define POWER5p_PME_PM_DC_INV_L2 457 #define POWER5p_PME_PM_LSU_SRQ_FULL_CYC 458 #define POWER5p_PME_PM_FPU_FIN 459 #define POWER5p_PME_PM_LSU_SRQ_STFWD 460 #define POWER5p_PME_PM_L2SA_SHR_MOD 461 #define POWER5p_PME_PM_0INST_CLB_CYC 462 #define POWER5p_PME_PM_FXU0_FIN 463 #define POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL 464 #define POWER5p_PME_PM_THRD_GRP_CMPL_BOTH_CYC 465 #define POWER5p_PME_PM_PMC5_OVERFLOW 466 #define POWER5p_PME_PM_FPU0_FDIV 467 #define POWER5p_PME_PM_PTEG_FROM_L375_SHR 468 #define POWER5p_PME_PM_HV_CYC 469 #define POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY 470 #define POWER5p_PME_PM_THRD_PRIO_DIFF_0_CYC 471 #define POWER5p_PME_PM_LR_CTR_MAP_FULL_CYC 472 #define POWER5p_PME_PM_L3SB_SHR_INV 473 #define POWER5p_PME_PM_DATA_FROM_RMEM 474 #define POWER5p_PME_PM_DATA_FROM_L275_MOD 475 #define POWER5p_PME_PM_LSU0_REJECT_SRQ 476 #define POWER5p_PME_PM_LSU1_DERAT_MISS 477 #define POWER5p_PME_PM_MRK_LSU_FIN 478 #define POWER5p_PME_PM_DTLB_MISS_16M 479 #define POWER5p_PME_PM_LSU0_FLUSH_UST 480 #define POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY 481 #define POWER5p_PME_PM_L2SC_MOD_TAG 482 static const int power5p_event_ids[][POWER5p_NUM_EVENT_COUNTERS] = { [ POWER5p_PME_PM_LSU_REJECT_RELOAD_CDF ] = { -1, 243, 240, -1, -1, -1 }, [ POWER5p_PME_PM_FPU1_SINGLE ] = { 82, 81, 81, 83, -1, -1 }, [ POWER5p_PME_PM_L3SB_REF ] = { 188, 185, 184, 183, -1, -1 }, [ POWER5p_PME_PM_THRD_PRIO_DIFF_3or4_CYC ] = { 343, 338, 336, 332, -1, -1 }, [ POWER5p_PME_PM_INST_FROM_L275_SHR ] = { -1, -1, 115, -1, -1, -1 }, [ POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD ] = { 274, -1, -1, 268, -1, -1 }, [ POWER5p_PME_PM_DTLB_MISS_4K ] = { 32, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_CLB_FULL_CYC ] = { 14, 13, 13, 14, -1, -1 }, [ POWER5p_PME_PM_MRK_ST_CMPL ] = { 299, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_LSU_FLUSH_LRQ_FULL ] = { 232, 231, 230, 227, -1, -1 }, [ POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR ] = { -1, -1, 265, -1, -1, -1 }, [ POWER5p_PME_PM_1INST_CLB_CYC ] = { 1, 1, 1, 2, -1, -1 }, [ POWER5p_PME_PM_MEM_SPEC_RD_CANCEL ] = { 264, 263, 259, 258, -1, -1 }, [ POWER5p_PME_PM_MRK_DTLB_MISS_16M ] = { -1, -1, 273, -1, -1, -1 }, [ POWER5p_PME_PM_FPU_FDIV ] = { 87, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_FPU_SINGLE ] = { 90, -1, -1, 90, -1, -1 }, [ POWER5p_PME_PM_FPU0_FMA ] = { 63, 62, 62, 64, -1, -1 }, [ POWER5p_PME_PM_SLB_MISS ] = { -1, 307, -1, -1, -1, -1 }, [ POWER5p_PME_PM_LSU1_FLUSH_LRQ ] = { 220, 216, 216, 215, -1, -1 }, [ POWER5p_PME_PM_L2SA_ST_HIT ] = { 142, 139, 138, 137, -1, -1 }, [ POWER5p_PME_PM_DTLB_MISS ] = { 31, 30, 30, 31, -1, -1 }, [ POWER5p_PME_PM_BR_PRED_TA ] = { 203, 11, 351, 348, -1, -1 }, [ POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD_CYC ] = { -1, -1, -1, 269, -1, -1 }, [ POWER5p_PME_PM_CMPLU_STALL_FXU ] = { -1, 16, -1, -1, -1, -1 }, [ POWER5p_PME_PM_EXT_INT ] = { -1, -1, -1, 37, -1, -1 }, [ POWER5p_PME_PM_MRK_LSU1_FLUSH_LRQ ] = { 292, 292, 286, 289, -1, -1 }, [ POWER5p_PME_PM_MRK_ST_GPS ] = { -1, 299, -1, -1, -1, -1 }, [ POWER5p_PME_PM_LSU1_LDF ] = { 224, 220, 220, 219, -1, -1 }, [ POWER5p_PME_PM_FAB_CMD_ISSUED ] = { 37, 36, 36, 38, -1, -1 }, [ POWER5p_PME_PM_LSU0_SRQ_STFWD ] = { 217, 213, 213, 212, -1, -1 }, [ POWER5p_PME_PM_CR_MAP_FULL_CYC ] = { 16, 19, 15, 20, -1, -1 }, [ POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL ] = { 137, 134, 133, 132, -1, -1 }, [ POWER5p_PME_PM_MRK_LSU0_FLUSH_ULD ] = { 290, 290, 284, 287, -1, -1 }, [ POWER5p_PME_PM_LSU_FLUSH_SRQ_FULL ] = { 234, 232, 231, 229, -1, -1 }, [ POWER5p_PME_PM_MEM_RQ_DISP_Q16to19 ] = { 360, 353, 352, 246, -1, -1 }, [ POWER5p_PME_PM_FLUSH_IMBAL ] = { 54, 53, 53, 55, -1, -1 }, [ POWER5p_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC ] = { 346, 341, 339, 335, -1, -1 }, [ POWER5p_PME_PM_DATA_FROM_L35_MOD ] = { -1, 22, 21, -1, -1, -1 }, [ POWER5p_PME_PM_MEM_HI_PRIO_WR_CMPL ] = { 253, 252, 248, 247, -1, -1 }, [ POWER5p_PME_PM_FPU1_FDIV ] = { 74, 73, 73, 75, -1, -1 }, [ POWER5p_PME_PM_MEM_RQ_DISP ] = { 261, 260, 256, 255, -1, -1 }, [ POWER5p_PME_PM_FPU0_FRSP_FCONV ] = { 66, 65, 65, 67, -1, -1 }, [ POWER5p_PME_PM_LWSYNC_HELD ] = { 250, 249, 245, 244, -1, -1 }, [ POWER5p_PME_PM_FXU_FIN ] = { -1, -1, 93, -1, -1, -1 }, [ POWER5p_PME_PM_DSLB_MISS ] = { 30, 29, 29, 30, -1, -1 }, [ POWER5p_PME_PM_DATA_FROM_L275_SHR ] = { -1, -1, 18, -1, -1, -1 }, [ POWER5p_PME_PM_FXLS1_FULL_CYC ] = { 92, 90, 89, 92, -1, -1 }, [ POWER5p_PME_PM_THRD_SEL_T0 ] = { 352, 347, 345, 341, -1, -1 }, [ POWER5p_PME_PM_PTEG_RELOAD_VALID ] = { 311, 306, 305, 303, -1, -1 }, [ POWER5p_PME_PM_MRK_STCX_FAIL ] = { 298, 298, 293, 297, -1, -1 }, [ POWER5p_PME_PM_LSU_LMQ_LHR_MERGE ] = { 238, 235, 233, 232, -1, -1 }, [ POWER5p_PME_PM_2INST_CLB_CYC ] = { 3, 2, 2, 3, -1, -1 }, [ POWER5p_PME_PM_FAB_PNtoVN_DIRECT ] = { 49, 48, 48, 50, -1, -1 }, [ POWER5p_PME_PM_PTEG_FROM_L2MISS ] = { -1, -1, 300, -1, -1, -1 }, [ POWER5p_PME_PM_CMPLU_STALL_LSU ] = { -1, 17, -1, -1, -1, -1 }, [ POWER5p_PME_PM_MRK_DSLB_MISS ] = { 276, 278, 271, 273, -1, -1 }, [ POWER5p_PME_PM_LSU_FLUSH_ULD ] = { 235, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_PTEG_FROM_LMEM ] = { -1, 305, 304, -1, -1, -1 }, [ POWER5p_PME_PM_MRK_BRU_FIN ] = { -1, 268, -1, -1, -1, -1 }, [ POWER5p_PME_PM_MEM_WQ_DISP_WRITE ] = { 268, 267, 263, 262, -1, -1 }, [ POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD_CYC ] = { -1, -1, -1, 266, -1, -1 }, [ POWER5p_PME_PM_LSU1_NCLD ] = { 225, 221, 221, 220, -1, -1 }, [ POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER ] = { 132, 129, 128, 127, -1, -1 }, [ POWER5p_PME_PM_SNOOP_PW_RETRY_WQ_PWQ ] = { 316, 311, 309, 307, -1, -1 }, [ POWER5p_PME_PM_FPU1_FULL_CYC ] = { 81, 80, 80, 82, -1, -1 }, [ POWER5p_PME_PM_FPR_MAP_FULL_CYC ] = { 57, 56, 56, 58, -1, -1 }, [ POWER5p_PME_PM_L3SA_ALL_BUSY ] = { 177, 174, 173, 172, -1, -1 }, [ POWER5p_PME_PM_3INST_CLB_CYC ] = { 4, 3, 3, 4, -1, -1 }, [ POWER5p_PME_PM_MEM_PWQ_DISP_Q2or3 ] = { 257, 250, 252, 251, -1, -1 }, [ POWER5p_PME_PM_L2SA_SHR_INV ] = { 140, 137, 136, 135, -1, -1 }, [ POWER5p_PME_PM_THRESH_TIMEO ] = { -1, -1, 348, -1, -1, -1 }, [ POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL ] = { 139, 136, 135, 134, -1, -1 }, [ POWER5p_PME_PM_THRD_SEL_OVER_GCT_IMBAL ] = { 349, 344, 342, 338, -1, -1 }, [ POWER5p_PME_PM_FPU_FSQRT ] = { -1, 86, 86, -1, -1, -1 }, [ POWER5p_PME_PM_PMC1_OVERFLOW ] = { -1, 301, -1, -1, -1, -1 }, [ POWER5p_PME_PM_MRK_LSU0_FLUSH_LRQ ] = { 288, 288, 282, 285, -1, -1 }, [ POWER5p_PME_PM_L3SC_SNOOP_RETRY ] = { 197, 194, 193, 192, -1, -1 }, [ POWER5p_PME_PM_DATA_TABLEWALK_CYC ] = { 25, 24, 24, 25, -1, -1 }, [ POWER5p_PME_PM_THRD_PRIO_6_CYC ] = { 339, 334, 332, 328, -1, -1 }, [ POWER5p_PME_PM_FPU_FEST ] = { 88, -1, -1, 87, -1, -1 }, [ POWER5p_PME_PM_FAB_M1toP1_SIDECAR_EMPTY ] = { 43, 42, 42, 44, -1, -1 }, [ POWER5p_PME_PM_MRK_DATA_FROM_RMEM ] = { 275, -1, -1, 271, -1, -1 }, [ POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD_CYC ] = { -1, -1, -1, 267, -1, -1 }, [ POWER5p_PME_PM_MEM_PWQ_DISP ] = { 256, 255, 251, 250, -1, -1 }, [ POWER5p_PME_PM_FAB_P1toM1_SIDECAR_EMPTY ] = { 45, 44, 44, 46, -1, -1 }, [ POWER5p_PME_PM_LD_MISS_L1_LSU0 ] = { 199, 196, 196, 194, -1, -1 }, [ POWER5p_PME_PM_SNOOP_PARTIAL_RTRY_QFULL ] = { 314, 309, 307, 305, -1, -1 }, [ POWER5p_PME_PM_FPU1_STALL3 ] = { 83, 82, 82, 84, -1, -1 }, [ POWER5p_PME_PM_GCT_USAGE_80to99_CYC ] = { -1, -1, 96, -1, -1, -1 }, [ POWER5p_PME_PM_WORK_HELD ] = { -1, -1, -1, 345, -1, -1 }, [ POWER5p_PME_PM_INST_CMPL ] = { 303, 302, -1, -1, -1, -1 }, [ POWER5p_PME_PM_LSU1_FLUSH_UST ] = { 223, 219, 219, 218, -1, -1 }, [ POWER5p_PME_PM_FXU_IDLE ] = { 96, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_LSU0_FLUSH_ULD ] = { 209, 205, 205, 204, -1, -1 }, [ POWER5p_PME_PM_LSU1_REJECT_LMQ_FULL ] = { 227, 223, 223, 222, -1, -1 }, [ POWER5p_PME_PM_GRP_DISP_REJECT ] = { 104, 104, 102, 103, -1, -1 }, [ POWER5p_PME_PM_PTEG_FROM_L25_SHR ] = { 305, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_L2SA_MOD_INV ] = { 128, 125, 124, 123, -1, -1 }, [ POWER5p_PME_PM_FAB_CMD_RETRIED ] = { 38, 37, 37, 39, -1, -1 }, [ POWER5p_PME_PM_L3SA_SHR_INV ] = { 182, 179, 178, 177, -1, -1 }, [ POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL ] = { 155, 152, 151, 150, -1, -1 }, [ POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_ADDR ] = { 135, 132, 131, 130, -1, -1 }, [ POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_RC_FULL ] = { 133, 130, 129, 128, -1, -1 }, [ POWER5p_PME_PM_PTEG_FROM_L375_MOD ] = { 309, -1, -1, 301, -1, -1 }, [ POWER5p_PME_PM_MRK_LSU1_FLUSH_UST ] = { 295, 295, 289, 292, -1, -1 }, [ POWER5p_PME_PM_BR_ISSUED ] = { 9, 8, 8, 9, -1, -1 }, [ POWER5p_PME_PM_MRK_GRP_BR_REDIR ] = { -1, 283, -1, -1, -1, -1 }, [ POWER5p_PME_PM_EE_OFF ] = { 35, 34, 34, 35, -1, -1 }, [ POWER5p_PME_PM_IERAT_XLATE_WR_LP ] = { 114, 112, 111, 111, -1, -1 }, [ POWER5p_PME_PM_DTLB_REF_64K ] = { -1, 33, -1, -1, -1, -1 }, [ POWER5p_PME_PM_MEM_RQ_DISP_Q4to7 ] = { 262, 259, 258, 257, -1, -1 }, [ POWER5p_PME_PM_MEM_FAST_PATH_RD_DISP ] = { 251, 354, 246, 245, -1, -1 }, [ POWER5p_PME_PM_INST_FROM_L3 ] = { 121, -1, 116, -1, -1, -1 }, [ POWER5p_PME_PM_ITLB_MISS ] = { 124, 121, 120, 119, -1, -1 }, [ POWER5p_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { -1, -1, -1, 95, -1, -1 }, [ POWER5p_PME_PM_DTLB_REF_4K ] = { 34, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_FXLS_FULL_CYC ] = { 93, -1, -1, 93, -1, -1 }, [ POWER5p_PME_PM_GRP_DISP_VALID ] = { 105, 105, 104, 104, -1, -1 }, [ POWER5p_PME_PM_LSU_FLUSH_UST ] = { -1, 233, -1, -1, -1, -1 }, [ POWER5p_PME_PM_FXU1_FIN ] = { 95, 92, 92, 96, -1, -1 }, [ POWER5p_PME_PM_THRD_PRIO_4_CYC ] = { 337, 332, 330, 326, -1, -1 }, [ POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD ] = { -1, 273, 268, -1, -1, -1 }, [ POWER5p_PME_PM_4INST_CLB_CYC ] = { 5, 4, 4, 5, -1, -1 }, [ POWER5p_PME_PM_MRK_DTLB_REF_16M ] = { -1, -1, 275, -1, -1, -1 }, [ POWER5p_PME_PM_INST_FROM_L375_MOD ] = { -1, -1, -1, 116, -1, -1 }, [ POWER5p_PME_PM_GRP_CMPL ] = { -1, -1, 100, -1, -1, -1 }, [ POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_ADDR ] = { 167, 164, 163, 162, -1, -1 }, [ POWER5p_PME_PM_FPU1_1FLOP ] = { 72, 71, 71, 73, -1, -1 }, [ POWER5p_PME_PM_FPU_FRSP_FCONV ] = { -1, 85, 85, -1, -1, -1 }, [ POWER5p_PME_PM_L3SC_REF ] = { 195, 192, 191, 190, -1, -1 }, [ POWER5p_PME_PM_5INST_CLB_CYC ] = { 6, 5, 5, 6, -1, -1 }, [ POWER5p_PME_PM_THRD_L2MISS_BOTH_CYC ] = { 332, 328, 326, 322, -1, -1 }, [ POWER5p_PME_PM_MEM_PW_GATH ] = { 259, 258, 254, 253, -1, -1 }, [ POWER5p_PME_PM_DTLB_REF_16G ] = { -1, -1, -1, 34, -1, -1 }, [ POWER5p_PME_PM_FAB_DCLAIM_ISSUED ] = { 39, 38, 38, 40, -1, -1 }, [ POWER5p_PME_PM_FAB_PNtoNN_SIDECAR ] = { 48, 47, 47, 49, -1, -1 }, [ POWER5p_PME_PM_GRP_IC_MISS ] = { 106, 106, 105, 105, -1, -1 }, [ POWER5p_PME_PM_INST_FROM_L35_SHR ] = { 122, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_LSU_LMQ_FULL_CYC ] = { 237, 234, 232, 231, -1, -1 }, [ POWER5p_PME_PM_MRK_DATA_FROM_L2_CYC ] = { -1, 272, -1, -1, -1, -1 }, [ POWER5p_PME_PM_LSU_SRQ_SYNC_CYC ] = { 249, 248, 244, 243, -1, -1 }, [ POWER5p_PME_PM_LSU0_BUSY_REJECT ] = { 205, 201, 201, 200, -1, -1 }, [ POWER5p_PME_PM_LSU_REJECT_ERAT_MISS ] = { 244, -1, -1, 238, -1, -1 }, [ POWER5p_PME_PM_MRK_DATA_FROM_RMEM_CYC ] = { -1, -1, -1, 272, -1, -1 }, [ POWER5p_PME_PM_DATA_FROM_L375_SHR ] = { -1, -1, 22, -1, -1, -1 }, [ POWER5p_PME_PM_PTEG_FROM_L25_MOD ] = { -1, 303, 298, -1, -1, -1 }, [ POWER5p_PME_PM_FPU0_FMOV_FEST ] = { 64, 63, 63, 65, -1, -1 }, [ POWER5p_PME_PM_THRD_PRIO_7_CYC ] = { 340, 335, 333, 329, -1, -1 }, [ POWER5p_PME_PM_LSU1_FLUSH_SRQ ] = { 221, 217, 217, 216, -1, -1 }, [ POWER5p_PME_PM_LD_REF_L1_LSU0 ] = { 202, 198, 198, 197, -1, -1 }, [ POWER5p_PME_PM_L2SC_RCST_DISP ] = { 166, 163, 162, 161, -1, -1 }, [ POWER5p_PME_PM_CMPLU_STALL_DIV ] = { -1, -1, -1, 15, -1, -1 }, [ POWER5p_PME_PM_MEM_RQ_DISP_Q12to15 ] = { 359, 262, 255, 248, -1, -1 }, [ POWER5p_PME_PM_INST_FROM_L375_SHR ] = { -1, -1, 117, -1, -1, -1 }, [ POWER5p_PME_PM_ST_REF_L1 ] = { -1, 323, 322, -1, -1, -1 }, [ POWER5p_PME_PM_L3SB_ALL_BUSY ] = { 184, 181, 180, 179, -1, -1 }, [ POWER5p_PME_PM_FAB_P1toVNorNN_SIDECAR_EMPTY ] = { 46, 45, 45, 47, -1, -1 }, [ POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR_CYC ] = { -1, 271, -1, -1, -1, -1 }, [ POWER5p_PME_PM_FAB_HOLDtoNN_EMPTY ] = { 41, 40, 40, 42, -1, -1 }, [ POWER5p_PME_PM_DATA_FROM_LMEM ] = { -1, 23, 23, -1, -1, -1 }, [ POWER5p_PME_PM_RUN_CYC ] = { 312, -1, -1, -1, -1, 0 }, [ POWER5p_PME_PM_PTEG_FROM_RMEM ] = { 310, -1, -1, 302, -1, -1 }, [ POWER5p_PME_PM_L2SC_RCLD_DISP ] = { 162, 159, 158, 157, -1, -1 }, [ POWER5p_PME_PM_LSU_LRQ_S0_VALID ] = { 243, 241, 239, 237, -1, -1 }, [ POWER5p_PME_PM_LSU0_LDF ] = { 211, 207, 207, 206, -1, -1 }, [ POWER5p_PME_PM_PMC3_OVERFLOW ] = { -1, -1, -1, 299, -1, -1 }, [ POWER5p_PME_PM_MRK_IMR_RELOAD ] = { 283, 284, 277, 281, -1, -1 }, [ POWER5p_PME_PM_MRK_GRP_TIMEO ] = { -1, -1, -1, 280, -1, -1 }, [ POWER5p_PME_PM_ST_MISS_L1 ] = { 327, 322, 321, 318, -1, -1 }, [ POWER5p_PME_PM_STOP_COMPLETION ] = { -1, -1, 320, -1, -1, -1 }, [ POWER5p_PME_PM_LSU_BUSY_REJECT ] = { -1, 227, -1, -1, -1, -1 }, [ POWER5p_PME_PM_ISLB_MISS ] = { 123, 120, 119, 118, -1, -1 }, [ POWER5p_PME_PM_CYC ] = { 17, 20, 16, 21, -1, -1 }, [ POWER5p_PME_PM_THRD_ONE_RUN_CYC ] = { 333, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_GRP_BR_REDIR_NONSPEC ] = { 102, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_LSU1_SRQ_STFWD ] = { 230, 226, 226, 225, -1, -1 }, [ POWER5p_PME_PM_L3SC_MOD_INV ] = { 193, 190, 189, 188, -1, -1 }, [ POWER5p_PME_PM_L2_PREF ] = { 176, 173, 172, 171, -1, -1 }, [ POWER5p_PME_PM_GCT_NOSLOT_BR_MPRED ] = { -1, -1, -1, 98, -1, -1 }, [ POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD ] = { -1, 269, 264, -1, -1, -1 }, [ POWER5p_PME_PM_L2SB_ST_REQ ] = { 159, 156, 155, 154, -1, -1 }, [ POWER5p_PME_PM_L2SB_MOD_INV ] = { 144, 141, 140, 139, -1, -1 }, [ POWER5p_PME_PM_MRK_L1_RELOAD_VALID ] = { 284, 285, 279, 282, -1, -1 }, [ POWER5p_PME_PM_L3SB_HIT ] = { 185, 182, 181, 180, -1, -1 }, [ POWER5p_PME_PM_L2SB_SHR_MOD ] = { 157, 154, 153, 152, -1, -1 }, [ POWER5p_PME_PM_EE_OFF_EXT_INT ] = { 36, 35, 35, 36, -1, -1 }, [ POWER5p_PME_PM_1PLUS_PPC_CMPL ] = { 2, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_L2SC_SHR_MOD ] = { 173, 170, 169, 168, -1, -1 }, [ POWER5p_PME_PM_PMC6_OVERFLOW ] = { -1, -1, 297, -1, -1, -1 }, [ POWER5p_PME_PM_IC_PREF_INSTALL ] = { 252, 251, 108, 108, -1, -1 }, [ POWER5p_PME_PM_LSU_LRQ_FULL_CYC ] = { 241, 239, 237, 235, -1, -1 }, [ POWER5p_PME_PM_TLB_MISS ] = { 356, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_GCT_FULL_CYC ] = { 97, 96, 94, 97, -1, -1 }, [ POWER5p_PME_PM_FXU_BUSY ] = { -1, 93, -1, -1, -1, -1 }, [ POWER5p_PME_PM_MRK_DATA_FROM_L3_CYC ] = { -1, 276, -1, -1, -1, -1 }, [ POWER5p_PME_PM_LSU_REJECT_LMQ_FULL ] = { -1, 242, -1, -1, -1, -1 }, [ POWER5p_PME_PM_LSU_SRQ_S0_ALLOC ] = { 247, 245, 242, 241, -1, -1 }, [ POWER5p_PME_PM_GRP_MRK ] = { 109, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_INST_FROM_L25_SHR ] = { 119, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_DC_PREF_STREAM_ALLOC ] = { 29, 28, 28, 29, -1, -1 }, [ POWER5p_PME_PM_FPU1_FIN ] = { 76, 75, 75, 77, -1, -1 }, [ POWER5p_PME_PM_BR_MPRED_TA ] = { 11, 10, 10, 11, -1, -1 }, [ POWER5p_PME_PM_MRK_DTLB_REF_64K ] = { -1, 282, -1, -1, -1, -1 }, [ POWER5p_PME_PM_RUN_INST_CMPL ] = { -1, -1, -1, -1, 0, -1 }, [ POWER5p_PME_PM_CRQ_FULL_CYC ] = { 15, 18, 14, 19, -1, -1 }, [ POWER5p_PME_PM_L2SA_RCLD_DISP ] = { 130, 127, 126, 125, -1, -1 }, [ POWER5p_PME_PM_SNOOP_WR_RETRY_QFULL ] = { 322, 317, 315, 313, -1, -1 }, [ POWER5p_PME_PM_MRK_DTLB_REF_4K ] = { 280, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_LSU_SRQ_S0_VALID ] = { 248, 246, 243, 242, -1, -1 }, [ POWER5p_PME_PM_LSU0_FLUSH_LRQ ] = { 207, 203, 203, 202, -1, -1 }, [ POWER5p_PME_PM_INST_FROM_L275_MOD ] = { -1, -1, -1, 115, -1, -1 }, [ POWER5p_PME_PM_GCT_EMPTY_CYC ] = { -1, 95, -1, -1, -1, -1 }, [ POWER5p_PME_PM_LARX_LSU0 ] = { 198, 195, 194, 193, -1, -1 }, [ POWER5p_PME_PM_THRD_PRIO_DIFF_5or6_CYC ] = { 344, 339, 337, 333, -1, -1 }, [ POWER5p_PME_PM_SNOOP_RETRY_1AHEAD ] = { 320, 315, 313, 311, -1, -1 }, [ POWER5p_PME_PM_FPU1_FSQRT ] = { 80, 79, 79, 81, -1, -1 }, [ POWER5p_PME_PM_MRK_LD_MISS_L1_LSU1 ] = { 287, 287, 281, 284, -1, -1 }, [ POWER5p_PME_PM_MRK_FPU_FIN ] = { -1, -1, 276, -1, -1, -1 }, [ POWER5p_PME_PM_THRD_PRIO_5_CYC ] = { 338, 333, 331, 327, -1, -1 }, [ POWER5p_PME_PM_MRK_DATA_FROM_LMEM ] = { -1, 277, 270, -1, -1, -1 }, [ POWER5p_PME_PM_SNOOP_TLBIE ] = { 321, 316, 314, 312, -1, -1 }, [ POWER5p_PME_PM_FPU1_FRSP_FCONV ] = { 79, 78, 78, 80, -1, -1 }, [ POWER5p_PME_PM_DTLB_MISS_16G ] = { -1, -1, -1, 32, -1, -1 }, [ POWER5p_PME_PM_L3SB_SNOOP_RETRY ] = { 190, 187, 186, 185, -1, -1 }, [ POWER5p_PME_PM_FAB_VBYPASS_EMPTY ] = { 51, 50, 50, 52, -1, -1 }, [ POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD ] = { 271, -1, -1, 265, -1, -1 }, [ POWER5p_PME_PM_L2SB_RCST_DISP ] = { 150, 147, 146, 145, -1, -1 }, [ POWER5p_PME_PM_6INST_CLB_CYC ] = { 7, 6, 6, 7, -1, -1 }, [ POWER5p_PME_PM_FLUSH ] = { 52, 51, 51, 53, -1, -1 }, [ POWER5p_PME_PM_L2SC_MOD_INV ] = { 160, 157, 156, 155, -1, -1 }, [ POWER5p_PME_PM_FPU_DENORM ] = { 86, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_L3SC_HIT ] = { 192, 189, 188, 187, -1, -1 }, [ POWER5p_PME_PM_SNOOP_WR_RETRY_RQ ] = { 323, 318, 316, 314, -1, -1 }, [ POWER5p_PME_PM_LSU1_REJECT_SRQ ] = { 229, 225, 225, 224, -1, -1 }, [ POWER5p_PME_PM_L3SC_ALL_BUSY ] = { 191, 188, 187, 186, -1, -1 }, [ POWER5p_PME_PM_IC_PREF_REQ ] = { 112, 110, 109, 109, -1, -1 }, [ POWER5p_PME_PM_MRK_GRP_IC_MISS ] = { -1, -1, -1, 279, -1, -1 }, [ POWER5p_PME_PM_GCT_NOSLOT_IC_MISS ] = { -1, 97, -1, -1, -1, -1 }, [ POWER5p_PME_PM_MRK_DATA_FROM_L3 ] = { 272, -1, 267, -1, -1, -1 }, [ POWER5p_PME_PM_GCT_NOSLOT_SRQ_FULL ] = { -1, -1, 95, -1, -1, -1 }, [ POWER5p_PME_PM_CMPLU_STALL_DCACHE_MISS ] = { -1, 14, -1, -1, -1, -1 }, [ POWER5p_PME_PM_THRD_SEL_OVER_ISU_HOLD ] = { 350, 345, 343, 339, -1, -1 }, [ POWER5p_PME_PM_LSU_FLUSH_LRQ ] = { -1, 230, 229, -1, -1, -1 }, [ POWER5p_PME_PM_THRD_PRIO_2_CYC ] = { 335, 330, 328, 324, -1, -1 }, [ POWER5p_PME_PM_L3SA_MOD_INV ] = { 179, 176, 175, 174, -1, -1 }, [ POWER5p_PME_PM_LSU_FLUSH_SRQ ] = { 233, -1, -1, 228, -1, -1 }, [ POWER5p_PME_PM_MRK_LSU_SRQ_INST_VALID ] = { 297, 297, 292, 296, -1, -1 }, [ POWER5p_PME_PM_L3SA_REF ] = { 181, 178, 177, 176, -1, -1 }, [ POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL ] = { 171, 168, 167, 166, -1, -1 }, [ POWER5p_PME_PM_FPU0_STALL3 ] = { 70, 69, 69, 71, -1, -1 }, [ POWER5p_PME_PM_TB_BIT_TRANS ] = { 331, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_GPR_MAP_FULL_CYC ] = { 100, 99, 97, 99, -1, -1 }, [ POWER5p_PME_PM_MRK_LSU_FLUSH_LRQ ] = { -1, -1, 290, -1, -1, -1 }, [ POWER5p_PME_PM_FPU0_STF ] = { 71, 70, 70, 72, -1, -1 }, [ POWER5p_PME_PM_MRK_DTLB_MISS ] = { 277, 279, 272, 274, -1, -1 }, [ POWER5p_PME_PM_FPU1_FMA ] = { 77, 76, 76, 78, -1, -1 }, [ POWER5p_PME_PM_L2SA_MOD_TAG ] = { 129, 126, 125, 124, -1, -1 }, [ POWER5p_PME_PM_LSU1_FLUSH_ULD ] = { 222, 218, 218, 217, -1, -1 }, [ POWER5p_PME_PM_MRK_INST_FIN ] = { -1, -1, 278, -1, -1, -1 }, [ POWER5p_PME_PM_MRK_LSU0_FLUSH_UST ] = { 291, 291, 285, 288, -1, -1 }, [ POWER5p_PME_PM_FPU0_FULL_CYC ] = { 68, 67, 67, 69, -1, -1 }, [ POWER5p_PME_PM_LSU_LRQ_S0_ALLOC ] = { 242, 240, 238, 236, -1, -1 }, [ POWER5p_PME_PM_MRK_LSU1_FLUSH_ULD ] = { 294, 294, 288, 291, -1, -1 }, [ POWER5p_PME_PM_MRK_DTLB_REF ] = { 279, 281, 274, 276, -1, -1 }, [ POWER5p_PME_PM_BR_UNCOND ] = { 12, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_THRD_SEL_OVER_L2MISS ] = { 351, 346, 344, 340, -1, -1 }, [ POWER5p_PME_PM_L2SB_SHR_INV ] = { 156, 153, 152, 151, -1, -1 }, [ POWER5p_PME_PM_MEM_LO_PRIO_WR_CMPL ] = { 255, 254, 250, 249, -1, -1 }, [ POWER5p_PME_PM_MRK_DTLB_MISS_64K ] = { -1, 280, -1, -1, -1, -1 }, [ POWER5p_PME_PM_MRK_ST_MISS_L1 ] = { 300, 300, 295, 298, -1, -1 }, [ POWER5p_PME_PM_L3SC_MOD_TAG ] = { 194, 191, 190, 189, -1, -1 }, [ POWER5p_PME_PM_GRP_DISP_SUCCESS ] = { -1, -1, 103, -1, -1, -1 }, [ POWER5p_PME_PM_THRD_PRIO_DIFF_1or2_CYC ] = { 342, 337, 335, 331, -1, -1 }, [ POWER5p_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = { 110, 108, 106, 106, -1, -1 }, [ POWER5p_PME_PM_LSU_DERAT_MISS ] = { -1, 228, 227, -1, -1, -1 }, [ POWER5p_PME_PM_MEM_WQ_DISP_Q8to15 ] = { 266, 265, 261, 260, -1, -1 }, [ POWER5p_PME_PM_FPU0_SINGLE ] = { 69, 68, 68, 70, -1, -1 }, [ POWER5p_PME_PM_THRD_PRIO_1_CYC ] = { 334, 329, 327, 323, -1, -1 }, [ POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_OTHER ] = { 168, 165, 164, 163, -1, -1 }, [ POWER5p_PME_PM_SNOOP_RD_RETRY_RQ ] = { 318, 313, 311, 309, -1, -1 }, [ POWER5p_PME_PM_FAB_HOLDtoVN_EMPTY ] = { 42, 41, 41, 43, -1, -1 }, [ POWER5p_PME_PM_FPU1_FEST ] = { 75, 74, 74, 76, -1, -1 }, [ POWER5p_PME_PM_SNOOP_DCLAIM_RETRY_QFULL ] = { 313, 308, 306, 304, -1, -1 }, [ POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR_CYC ] = { -1, 270, -1, -1, -1, -1 }, [ POWER5p_PME_PM_MRK_ST_CMPL_INT ] = { -1, -1, 294, -1, -1, -1 }, [ POWER5p_PME_PM_FLUSH_BR_MPRED ] = { 53, 52, 52, 54, -1, -1 }, [ POWER5p_PME_PM_MRK_DTLB_MISS_16G ] = { -1, -1, -1, 275, -1, -1 }, [ POWER5p_PME_PM_FPU_STF ] = { -1, 88, 87, -1, -1, -1 }, [ POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR ] = { 147, 144, 143, 142, -1, -1 }, [ POWER5p_PME_PM_CMPLU_STALL_FPU ] = { -1, -1, -1, 17, -1, -1 }, [ POWER5p_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC ] = { 345, 340, 338, 334, -1, -1 }, [ POWER5p_PME_PM_GCT_NOSLOT_CYC ] = { 98, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { -1, -1, 90, -1, -1, -1 }, [ POWER5p_PME_PM_PTEG_FROM_L35_SHR ] = { 308, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_MRK_DTLB_REF_16G ] = { -1, -1, -1, 277, -1, -1 }, [ POWER5p_PME_PM_MRK_LSU_FLUSH_UST ] = { -1, 296, 291, -1, -1, -1 }, [ POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR ] = { 270, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_L3SA_HIT ] = { 178, 175, 174, 173, -1, -1 }, [ POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR ] = { 273, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_ADDR ] = { 151, 148, 147, 146, -1, -1 }, [ POWER5p_PME_PM_IERAT_XLATE_WR ] = { 113, 111, 110, 110, -1, -1 }, [ POWER5p_PME_PM_L2SA_ST_REQ ] = { 143, 140, 139, 138, -1, -1 }, [ POWER5p_PME_PM_INST_FROM_LMEM ] = { -1, 119, -1, -1, -1, -1 }, [ POWER5p_PME_PM_THRD_SEL_T1 ] = { 353, 348, 346, 342, -1, -1 }, [ POWER5p_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = { 111, 109, 107, 107, -1, -1 }, [ POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR_CYC ] = { -1, 274, -1, -1, -1, -1 }, [ POWER5p_PME_PM_FPU0_1FLOP ] = { 58, 57, 57, 59, -1, -1 }, [ POWER5p_PME_PM_PTEG_FROM_L2 ] = { 304, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_MEM_PW_CMPL ] = { 258, 257, 253, 252, -1, -1 }, [ POWER5p_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC ] = { 347, 342, 340, 336, -1, -1 }, [ POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER ] = { 148, 145, 144, 143, -1, -1 }, [ POWER5p_PME_PM_MRK_DTLB_MISS_4K ] = { 278, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_FPU0_FIN ] = { 62, 61, 61, 63, -1, -1 }, [ POWER5p_PME_PM_L3SC_SHR_INV ] = { 196, 193, 192, 191, -1, -1 }, [ POWER5p_PME_PM_GRP_BR_REDIR ] = { 101, 100, 98, 100, -1, -1 }, [ POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL ] = { 165, 162, 161, 160, -1, -1 }, [ POWER5p_PME_PM_MRK_LSU_FLUSH_SRQ ] = { -1, -1, -1, 294, -1, -1 }, [ POWER5p_PME_PM_PTEG_FROM_L275_SHR ] = { -1, -1, 299, -1, -1, -1 }, [ POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL ] = { 149, 146, 145, 144, -1, -1 }, [ POWER5p_PME_PM_SNOOP_RD_RETRY_WQ ] = { 319, 314, 312, 310, -1, -1 }, [ POWER5p_PME_PM_FAB_DCLAIM_RETRIED ] = { 40, 39, 39, 41, -1, -1 }, [ POWER5p_PME_PM_LSU0_NCLD ] = { 212, 208, 208, 207, -1, -1 }, [ POWER5p_PME_PM_LSU1_BUSY_REJECT ] = { 218, 214, 214, 213, -1, -1 }, [ POWER5p_PME_PM_FXLS0_FULL_CYC ] = { 91, 89, 88, 91, -1, -1 }, [ POWER5p_PME_PM_DTLB_REF_16M ] = { -1, -1, 33, -1, -1, -1 }, [ POWER5p_PME_PM_FPU0_FEST ] = { 61, 60, 60, 62, -1, -1 }, [ POWER5p_PME_PM_GCT_USAGE_60to79_CYC ] = { -1, 98, -1, -1, -1, -1 }, [ POWER5p_PME_PM_DATA_FROM_L25_MOD ] = { -1, 21, 17, -1, -1, -1 }, [ POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR ] = { 163, 160, 159, 158, -1, -1 }, [ POWER5p_PME_PM_LSU0_REJECT_ERAT_MISS ] = { 213, 209, 209, 208, -1, -1 }, [ POWER5p_PME_PM_DATA_FROM_L375_MOD ] = { 23, -1, -1, 23, -1, -1 }, [ POWER5p_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { -1, 238, 236, -1, -1, -1 }, [ POWER5p_PME_PM_DTLB_MISS_64K ] = { -1, 31, -1, -1, -1, -1 }, [ POWER5p_PME_PM_LSU0_REJECT_RELOAD_CDF ] = { 215, 211, 211, 210, -1, -1 }, [ POWER5p_PME_PM_0INST_FETCH ] = { -1, -1, -1, 1, -1, -1 }, [ POWER5p_PME_PM_LSU1_REJECT_RELOAD_CDF ] = { 228, 224, 224, 223, -1, -1 }, [ POWER5p_PME_PM_MEM_WQ_DISP_Q0to7 ] = { 265, 264, 260, 259, -1, -1 }, [ POWER5p_PME_PM_L1_PREF ] = { 126, 123, 122, 121, -1, -1 }, [ POWER5p_PME_PM_MRK_DATA_FROM_LMEM_CYC ] = { -1, -1, -1, 270, -1, -1 }, [ POWER5p_PME_PM_BRQ_FULL_CYC ] = { 8, 7, 7, 8, -1, -1 }, [ POWER5p_PME_PM_GRP_IC_MISS_NONSPEC ] = { 108, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_PTEG_FROM_L275_MOD ] = { 306, -1, -1, 300, -1, -1 }, [ POWER5p_PME_PM_MRK_LD_MISS_L1_LSU0 ] = { 286, 286, 280, 283, -1, -1 }, [ POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR_CYC ] = { -1, 275, -1, -1, -1, -1 }, [ POWER5p_PME_PM_DATA_FROM_L3 ] = { 21, -1, 20, -1, -1, -1 }, [ POWER5p_PME_PM_INST_FROM_L2 ] = { 118, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_LSU_FLUSH ] = { 231, 229, 228, 226, -1, -1 }, [ POWER5p_PME_PM_PMC2_OVERFLOW ] = { -1, -1, 296, -1, -1, -1 }, [ POWER5p_PME_PM_FPU0_DENORM ] = { 59, 58, 58, 60, -1, -1 }, [ POWER5p_PME_PM_FPU1_FMOV_FEST ] = { 78, 77, 77, 79, -1, -1 }, [ POWER5p_PME_PM_INST_FETCH_CYC ] = { 117, 115, 114, 114, -1, -1 }, [ POWER5p_PME_PM_INST_DISP ] = { -1, -1, 113, 113, -1, -1 }, [ POWER5p_PME_PM_LSU_LDF ] = { 236, -1, -1, 230, -1, -1 }, [ POWER5p_PME_PM_DATA_FROM_L25_SHR ] = { 19, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_L1_DCACHE_RELOAD_VALID ] = { 125, 122, 121, 120, -1, -1 }, [ POWER5p_PME_PM_MEM_WQ_DISP_DCLAIM ] = { 267, 266, 262, 261, -1, -1 }, [ POWER5p_PME_PM_MRK_GRP_ISSUED ] = { 282, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_FPU_FULL_CYC ] = { 89, -1, -1, 89, -1, -1 }, [ POWER5p_PME_PM_INST_FROM_L35_MOD ] = { -1, 118, -1, -1, -1, -1 }, [ POWER5p_PME_PM_FPU_FMA ] = { -1, 84, -1, -1, -1, -1 }, [ POWER5p_PME_PM_THRD_PRIO_3_CYC ] = { 336, 331, 329, 325, -1, -1 }, [ POWER5p_PME_PM_MRK_CRU_FIN ] = { -1, -1, -1, 263, -1, -1 }, [ POWER5p_PME_PM_SNOOP_WR_RETRY_WQ ] = { 324, 319, 317, 315, -1, -1 }, [ POWER5p_PME_PM_CMPLU_STALL_REJECT ] = { -1, -1, -1, 18, -1, -1 }, [ POWER5p_PME_PM_MRK_FXU_FIN ] = { -1, 94, -1, -1, -1, -1 }, [ POWER5p_PME_PM_LSU1_REJECT_ERAT_MISS ] = { 226, 222, 222, 221, -1, -1 }, [ POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_OTHER ] = { 152, 149, 148, 147, -1, -1 }, [ POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY ] = { 170, 167, 166, 165, -1, -1 }, [ POWER5p_PME_PM_PMC4_OVERFLOW ] = { 301, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_L3SA_SNOOP_RETRY ] = { 183, 180, 179, 178, -1, -1 }, [ POWER5p_PME_PM_PTEG_FROM_L35_MOD ] = { -1, 304, 302, -1, -1, -1 }, [ POWER5p_PME_PM_INST_FROM_L25_MOD ] = { -1, 117, -1, -1, -1, -1 }, [ POWER5p_PME_PM_THRD_SMT_HANG ] = { 354, 349, 347, 343, -1, -1 }, [ POWER5p_PME_PM_CMPLU_STALL_ERAT_MISS ] = { -1, -1, -1, 16, -1, -1 }, [ POWER5p_PME_PM_L3SA_MOD_TAG ] = { 180, 177, 176, 175, -1, -1 }, [ POWER5p_PME_PM_INST_FROM_L2MISS ] = { 120, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_FLUSH_SYNC ] = { 56, 55, 55, 57, -1, -1 }, [ POWER5p_PME_PM_MRK_GRP_DISP ] = { 281, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_MEM_RQ_DISP_Q8to11 ] = { 263, 261, 247, 349, -1, -1 }, [ POWER5p_PME_PM_L2SC_ST_HIT ] = { 174, 171, 170, 169, -1, -1 }, [ POWER5p_PME_PM_L2SB_MOD_TAG ] = { 145, 142, 141, 140, -1, -1 }, [ POWER5p_PME_PM_CLB_EMPTY_CYC ] = { 13, 12, 12, 13, -1, -1 }, [ POWER5p_PME_PM_L2SB_ST_HIT ] = { 158, 155, 154, 153, -1, -1 }, [ POWER5p_PME_PM_MEM_NONSPEC_RD_CANCEL ] = { 254, 253, 249, 351, -1, -1 }, [ POWER5p_PME_PM_BR_PRED_CR_TA ] = { -1, -1, -1, 12, -1, -1 }, [ POWER5p_PME_PM_MRK_LSU0_FLUSH_SRQ ] = { 289, 289, 283, 286, -1, -1 }, [ POWER5p_PME_PM_MRK_LSU_FLUSH_ULD ] = { 296, -1, -1, 295, -1, -1 }, [ POWER5p_PME_PM_INST_DISP_ATTEMPT ] = { 116, 114, 354, 254, -1, -1 }, [ POWER5p_PME_PM_INST_FROM_RMEM ] = { -1, -1, -1, 117, -1, -1 }, [ POWER5p_PME_PM_ST_REF_L1_LSU0 ] = { 328, 324, 323, 319, -1, -1 }, [ POWER5p_PME_PM_LSU0_DERAT_MISS ] = { 206, 202, 202, 201, -1, -1 }, [ POWER5p_PME_PM_FPU_STALL3 ] = { -1, 87, -1, -1, -1, -1 }, [ POWER5p_PME_PM_L2SB_RCLD_DISP ] = { 146, 143, 142, 141, -1, -1 }, [ POWER5p_PME_PM_BR_PRED_CR ] = { 358, 352, 11, 347, -1, -1 }, [ POWER5p_PME_PM_MRK_DATA_FROM_L2 ] = { 269, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_LSU0_FLUSH_SRQ ] = { 208, 204, 204, 203, -1, -1 }, [ POWER5p_PME_PM_FAB_PNtoNN_DIRECT ] = { 47, 46, 46, 48, -1, -1 }, [ POWER5p_PME_PM_IOPS_CMPL ] = { 115, 113, 112, 112, -1, -1 }, [ POWER5p_PME_PM_L2SA_RCST_DISP ] = { 134, 131, 130, 129, -1, -1 }, [ POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_OTHER ] = { 136, 133, 132, 131, -1, -1 }, [ POWER5p_PME_PM_L2SC_SHR_INV ] = { 172, 169, 168, 167, -1, -1 }, [ POWER5p_PME_PM_SNOOP_RETRY_AB_COLLISION ] = { 361, 355, 353, 350, -1, -1 }, [ POWER5p_PME_PM_FAB_PNtoVN_SIDECAR ] = { 50, 49, 49, 51, -1, -1 }, [ POWER5p_PME_PM_LSU0_REJECT_LMQ_FULL ] = { 214, 210, 210, 209, -1, -1 }, [ POWER5p_PME_PM_LSU_LMQ_S0_ALLOC ] = { 239, 236, 234, 233, -1, -1 }, [ POWER5p_PME_PM_SNOOP_PW_RETRY_RQ ] = { 315, 310, 308, 306, -1, -1 }, [ POWER5p_PME_PM_DTLB_REF ] = { 33, 32, 32, 33, -1, -1 }, [ POWER5p_PME_PM_PTEG_FROM_L3 ] = { 307, -1, 301, -1, -1, -1 }, [ POWER5p_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY ] = { 44, 43, 43, 45, -1, -1 }, [ POWER5p_PME_PM_LSU_SRQ_EMPTY_CYC ] = { -1, -1, -1, 239, -1, -1 }, [ POWER5p_PME_PM_FPU1_STF ] = { 84, 83, 83, 85, -1, -1 }, [ POWER5p_PME_PM_LSU_LMQ_S0_VALID ] = { 240, 237, 235, 234, -1, -1 }, [ POWER5p_PME_PM_GCT_USAGE_00to59_CYC ] = { 99, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_FPU_FMOV_FEST ] = { -1, -1, 84, -1, -1, -1 }, [ POWER5p_PME_PM_DATA_FROM_L2MISS ] = { -1, -1, 19, -1, -1, -1 }, [ POWER5p_PME_PM_XER_MAP_FULL_CYC ] = { 357, 351, 350, 346, -1, -1 }, [ POWER5p_PME_PM_GRP_DISP_BLK_SB_CYC ] = { 103, 103, 101, 102, -1, -1 }, [ POWER5p_PME_PM_FLUSH_SB ] = { 55, 54, 54, 56, -1, -1 }, [ POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR ] = { -1, -1, 269, -1, -1, -1 }, [ POWER5p_PME_PM_MRK_GRP_CMPL ] = { -1, -1, -1, 278, -1, -1 }, [ POWER5p_PME_PM_SUSPENDED ] = { 330, 326, 325, 321, -1, -1 }, [ POWER5p_PME_PM_SNOOP_RD_RETRY_QFULL ] = { 317, 312, 310, 308, -1, -1 }, [ POWER5p_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC ] = { 107, 101, 99, 101, -1, -1 }, [ POWER5p_PME_PM_DATA_FROM_L35_SHR ] = { 22, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_L3SB_MOD_INV ] = { 186, 183, 182, 181, -1, -1 }, [ POWER5p_PME_PM_STCX_FAIL ] = { 325, 320, 318, 316, -1, -1 }, [ POWER5p_PME_PM_LD_MISS_L1_LSU1 ] = { 200, 199, 199, 198, -1, -1 }, [ POWER5p_PME_PM_GRP_DISP ] = { -1, 102, -1, -1, -1, -1 }, [ POWER5p_PME_PM_DC_PREF_DST ] = { 28, 27, 27, 28, -1, -1 }, [ POWER5p_PME_PM_FPU1_DENORM ] = { 73, 72, 72, 74, -1, -1 }, [ POWER5p_PME_PM_FPU0_FPSCR ] = { 65, 64, 64, 66, -1, -1 }, [ POWER5p_PME_PM_DATA_FROM_L2 ] = { 18, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR ] = { 131, 128, 127, 126, -1, -1 }, [ POWER5p_PME_PM_FPU_1FLOP ] = { 85, -1, -1, 86, -1, -1 }, [ POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER ] = { 164, 161, 160, 159, -1, -1 }, [ POWER5p_PME_PM_FPU0_FSQRT ] = { 67, 66, 66, 68, -1, -1 }, [ POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL ] = { 169, 166, 165, 164, -1, -1 }, [ POWER5p_PME_PM_LD_REF_L1 ] = { 201, -1, -1, 196, -1, -1 }, [ POWER5p_PME_PM_INST_FROM_L1 ] = { -1, 116, -1, -1, -1, -1 }, [ POWER5p_PME_PM_TLBIE_HELD ] = { 355, 350, 349, 344, -1, -1 }, [ POWER5p_PME_PM_DC_PREF_OUT_OF_STREAMS ] = { 27, 26, 26, 27, -1, -1 }, [ POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD_CYC ] = { -1, -1, -1, 264, -1, -1 }, [ POWER5p_PME_PM_MRK_LSU1_FLUSH_SRQ ] = { 293, 293, 287, 290, -1, -1 }, [ POWER5p_PME_PM_MEM_RQ_DISP_Q0to3 ] = { 260, 256, 257, 256, -1, -1 }, [ POWER5p_PME_PM_ST_REF_L1_LSU1 ] = { 329, 325, 324, 320, -1, -1 }, [ POWER5p_PME_PM_MRK_LD_MISS_L1 ] = { 285, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_L1_WRITE_CYC ] = { 127, 124, 123, 122, -1, -1 }, [ POWER5p_PME_PM_L2SC_ST_REQ ] = { 175, 172, 171, 170, -1, -1 }, [ POWER5p_PME_PM_CMPLU_STALL_FDIV ] = { -1, 15, -1, -1, -1, -1 }, [ POWER5p_PME_PM_THRD_SEL_OVER_CLB_EMPTY ] = { 348, 343, 341, 337, -1, -1 }, [ POWER5p_PME_PM_BR_MPRED_CR ] = { 10, 9, 9, 10, -1, -1 }, [ POWER5p_PME_PM_L3SB_MOD_TAG ] = { 187, 184, 183, 182, -1, -1 }, [ POWER5p_PME_PM_MRK_DATA_FROM_L2MISS ] = { -1, -1, 266, -1, -1, -1 }, [ POWER5p_PME_PM_LSU_REJECT_SRQ ] = { 245, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_LD_MISS_L1 ] = { -1, -1, 195, -1, -1, -1 }, [ POWER5p_PME_PM_INST_FROM_PREF ] = { -1, -1, 118, -1, -1, -1 }, [ POWER5p_PME_PM_STCX_PASS ] = { 326, 321, 319, 317, -1, -1 }, [ POWER5p_PME_PM_DC_INV_L2 ] = { 26, 25, 25, 26, -1, -1 }, [ POWER5p_PME_PM_LSU_SRQ_FULL_CYC ] = { 246, 244, 241, 240, -1, -1 }, [ POWER5p_PME_PM_FPU_FIN ] = { -1, -1, -1, 88, -1, -1 }, [ POWER5p_PME_PM_LSU_SRQ_STFWD ] = { -1, 247, -1, -1, -1, -1 }, [ POWER5p_PME_PM_L2SA_SHR_MOD ] = { 141, 138, 137, 136, -1, -1 }, [ POWER5p_PME_PM_0INST_CLB_CYC ] = { 0, 0, 0, 0, -1, -1 }, [ POWER5p_PME_PM_FXU0_FIN ] = { 94, 91, 91, 94, -1, -1 }, [ POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL ] = { 153, 150, 149, 148, -1, -1 }, [ POWER5p_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = { -1, 327, -1, -1, -1, -1 }, [ POWER5p_PME_PM_PMC5_OVERFLOW ] = { 302, -1, -1, -1, -1, -1 }, [ POWER5p_PME_PM_FPU0_FDIV ] = { 60, 59, 59, 61, -1, -1 }, [ POWER5p_PME_PM_PTEG_FROM_L375_SHR ] = { -1, -1, 303, -1, -1, -1 }, [ POWER5p_PME_PM_HV_CYC ] = { -1, 107, -1, -1, -1, -1 }, [ POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY ] = { 138, 135, 134, 133, -1, -1 }, [ POWER5p_PME_PM_THRD_PRIO_DIFF_0_CYC ] = { 341, 336, 334, 330, -1, -1 }, [ POWER5p_PME_PM_LR_CTR_MAP_FULL_CYC ] = { 204, 200, 200, 199, -1, -1 }, [ POWER5p_PME_PM_L3SB_SHR_INV ] = { 189, 186, 185, 184, -1, -1 }, [ POWER5p_PME_PM_DATA_FROM_RMEM ] = { 24, -1, -1, 24, -1, -1 }, [ POWER5p_PME_PM_DATA_FROM_L275_MOD ] = { 20, -1, -1, 22, -1, -1 }, [ POWER5p_PME_PM_LSU0_REJECT_SRQ ] = { 216, 212, 212, 211, -1, -1 }, [ POWER5p_PME_PM_LSU1_DERAT_MISS ] = { 219, 215, 215, 214, -1, -1 }, [ POWER5p_PME_PM_MRK_LSU_FIN ] = { -1, -1, -1, 293, -1, -1 }, [ POWER5p_PME_PM_DTLB_MISS_16M ] = { -1, -1, 31, -1, -1, -1 }, [ POWER5p_PME_PM_LSU0_FLUSH_UST ] = { 210, 206, 206, 205, -1, -1 }, [ POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY ] = { 154, 151, 150, 149, -1, -1 }, [ POWER5p_PME_PM_L2SC_MOD_TAG ] = { 161, 158, 157, 156, -1, -1 } }; static const unsigned long long power5p_group_vecs[][POWER5p_NUM_GROUP_VEC] = { [ POWER5p_PME_PM_LSU_REJECT_RELOAD_CDF ] = { 0x0000000000080000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPU1_SINGLE ] = { 0x0000000000000000ULL, 0x0000000002000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L3SB_REF ] = { 0x0000000000000000ULL, 0x0000000000008000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_THRD_PRIO_DIFF_3or4_CYC ] = { 0x0000000000000000ULL, 0x0000000200000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_INST_FROM_L275_SHR ] = { 0x0200000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD ] = { 0x0000000000000000ULL, 0x2000000000000000ULL, 0x0080000000000000ULL }, [ POWER5p_PME_PM_DTLB_MISS_4K ] = { 0x0001000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_CLB_FULL_CYC ] = { 0x0000000000001000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_ST_CMPL ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000100000000008ULL }, [ POWER5p_PME_PM_LSU_FLUSH_LRQ_FULL ] = { 0x0000000010000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR ] = { 0x0000000000000000ULL, 0x0400000000000000ULL, 0x0000000800000000ULL }, [ POWER5p_PME_PM_1INST_CLB_CYC ] = { 0x0000000000002000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MEM_SPEC_RD_CANCEL ] = { 0x0000000000000000ULL, 0x0001000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_DTLB_MISS_16M ] = { 0x0000000000000000ULL, 0x8000000000000000ULL, 0x0000028000000000ULL }, [ POWER5p_PME_PM_FPU_FDIV ] = { 0x0000000000000000ULL, 0x0000000000020000ULL, 0x0000000000410000ULL }, [ POWER5p_PME_PM_FPU_SINGLE ] = { 0x0000000000000000ULL, 0x0000000000100000ULL, 0x0000000000008000ULL }, [ POWER5p_PME_PM_FPU0_FMA ] = { 0x0000000000000000ULL, 0x0000000004000000ULL, 0x0000000000001000ULL }, [ POWER5p_PME_PM_SLB_MISS ] = { 0x0000020000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU1_FLUSH_LRQ ] = { 0x0000000000800000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SA_ST_HIT ] = { 0x0000000000000000ULL, 0x0000000000000002ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_DTLB_MISS ] = { 0x0002100000000000ULL, 0x0000000000000000ULL, 0x0000000004000080ULL }, [ POWER5p_PME_PM_BR_PRED_TA ] = { 0x0000040000000000ULL, 0x0000000000000000ULL, 0x0000000000000400ULL }, [ POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD_CYC ] = { 0x0000000000000000ULL, 0x2000000000000000ULL, 0x0000004000000000ULL }, [ POWER5p_PME_PM_CMPLU_STALL_FXU ] = { 0x0000000080000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_EXT_INT ] = { 0x0000000000000000ULL, 0x0002000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_LSU1_FLUSH_LRQ ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0020000000000000ULL }, [ POWER5p_PME_PM_MRK_ST_GPS ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000200000000010ULL }, [ POWER5p_PME_PM_LSU1_LDF ] = { 0x0000000000000000ULL, 0x0000000002000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FAB_CMD_ISSUED ] = { 0x0000000000000000ULL, 0x0000010000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU0_SRQ_STFWD ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_CR_MAP_FULL_CYC ] = { 0x0000000800000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL ] = { 0x0000000000000000ULL, 0x0000000000000001ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_LSU0_FLUSH_ULD ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0008000000000000ULL }, [ POWER5p_PME_PM_LSU_FLUSH_SRQ_FULL ] = { 0x0000000010000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MEM_RQ_DISP_Q16to19 ] = { 0x0000000000000000ULL, 0x0000800000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FLUSH_IMBAL ] = { 0x0000000000108000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC ] = { 0x0000000000000000ULL, 0x0000000400000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_DATA_FROM_L35_MOD ] = { 0x0040000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MEM_HI_PRIO_WR_CMPL ] = { 0x0000000000000000ULL, 0x0000400000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPU1_FDIV ] = { 0x0000000000000000ULL, 0x0000000000800000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MEM_RQ_DISP ] = { 0x0000000000000000ULL, 0x0001000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPU0_FRSP_FCONV ] = { 0x0000000000000000ULL, 0x0000000000800000ULL, 0x0000000000001000ULL }, [ POWER5p_PME_PM_LWSYNC_HELD ] = { 0x0000000000020000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FXU_FIN ] = { 0x0000000000000000ULL, 0x0000000040000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_DSLB_MISS ] = { 0x0000400000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_DATA_FROM_L275_SHR ] = { 0x0020000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FXLS1_FULL_CYC ] = { 0x0000000400000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_THRD_SEL_T0 ] = { 0x0000000000000000ULL, 0x0000002000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_PTEG_RELOAD_VALID ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_STCX_FAIL ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0020000000000010ULL }, [ POWER5p_PME_PM_LSU_LMQ_LHR_MERGE ] = { 0x0000000000000200ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_2INST_CLB_CYC ] = { 0x0000000000000008ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FAB_PNtoVN_DIRECT ] = { 0x0000000000000000ULL, 0x0000040000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_PTEG_FROM_L2MISS ] = { 0x2000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_CMPLU_STALL_LSU ] = { 0x0000000020000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_DSLB_MISS ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000040000000003ULL }, [ POWER5p_PME_PM_LSU_FLUSH_ULD ] = { 0x0000000002000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_PTEG_FROM_LMEM ] = { 0x2000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_BRU_FIN ] = { 0x0000000000000000ULL, 0x0040000000000000ULL, 0x0090000000000000ULL }, [ POWER5p_PME_PM_MEM_WQ_DISP_WRITE ] = { 0x0000000000000000ULL, 0x0004000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD_CYC ] = { 0x0000000000000000ULL, 0x1000000000000000ULL, 0x0000002000000000ULL }, [ POWER5p_PME_PM_LSU1_NCLD ] = { 0x0000002000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER ] = { 0x8000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_SNOOP_PW_RETRY_WQ_PWQ ] = { 0x0000000000000000ULL, 0x0000800000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPU1_FULL_CYC ] = { 0x0000000400000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPR_MAP_FULL_CYC ] = { 0x0000001000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L3SA_ALL_BUSY ] = { 0x0000000000000000ULL, 0x0000000000004000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_3INST_CLB_CYC ] = { 0x0000000000000000ULL, 0x0000000080000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MEM_PWQ_DISP_Q2or3 ] = { 0x0000000000000000ULL, 0x0008000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SA_SHR_INV ] = { 0x0000000000000000ULL, 0x0000000000000800ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_THRESH_TIMEO ] = { 0x0000000000000000ULL, 0x0010000000000000ULL, 0x0000000020000000ULL }, [ POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL ] = { 0x0000000000000000ULL, 0x0000000000000002ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_THRD_SEL_OVER_GCT_IMBAL ] = { 0x0000000000000000ULL, 0x0000004000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPU_FSQRT ] = { 0x0000000000000000ULL, 0x0000000000040000ULL, 0x0000000000410000ULL }, [ POWER5p_PME_PM_PMC1_OVERFLOW ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_LSU0_FLUSH_LRQ ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0010000000000000ULL }, [ POWER5p_PME_PM_L3SC_SNOOP_RETRY ] = { 0x0000000000000000ULL, 0x0000000000010000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_DATA_TABLEWALK_CYC ] = { 0x0000100000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_THRD_PRIO_6_CYC ] = { 0x0000000000000000ULL, 0x0000000200000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPU_FEST ] = { 0x0000000000000000ULL, 0x0000000000020000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FAB_M1toP1_SIDECAR_EMPTY ] = { 0x0000000000000000ULL, 0x0000080000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_DATA_FROM_RMEM ] = { 0x0000000000000000ULL, 0x0400000000000000ULL, 0x0000800000000000ULL }, [ POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD_CYC ] = { 0x0000000000000008ULL, 0x0200000000000000ULL, 0x0000000400000000ULL }, [ POWER5p_PME_PM_MEM_PWQ_DISP ] = { 0x0000000000000000ULL, 0x0008000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FAB_P1toM1_SIDECAR_EMPTY ] = { 0x0000000000000000ULL, 0x0000020000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LD_MISS_L1_LSU0 ] = { 0x0000400000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_SNOOP_PARTIAL_RTRY_QFULL ] = { 0x0000000000000000ULL, 0x0000100000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPU1_STALL3 ] = { 0x0000000000000000ULL, 0x0000000001000000ULL, 0x0000000000000800ULL }, [ POWER5p_PME_PM_GCT_USAGE_80to99_CYC ] = { 0x0000000000000040ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_WORK_HELD ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_INST_CMPL ] = { 0x0000000000000001ULL, 0x0000000000000000ULL, 0x0ffffffff9880000ULL }, [ POWER5p_PME_PM_LSU1_FLUSH_UST ] = { 0x0000000008000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FXU_IDLE ] = { 0x0000000000000000ULL, 0x0000000020000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU0_FLUSH_ULD ] = { 0x0000000004000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU1_REJECT_LMQ_FULL ] = { 0x0000000000040000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_GRP_DISP_REJECT ] = { 0x0000000000000004ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_PTEG_FROM_L25_SHR ] = { 0x0800000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SA_MOD_INV ] = { 0x0000000000000000ULL, 0x0000000000000800ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FAB_CMD_RETRIED ] = { 0x0000000000000000ULL, 0x0000010000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L3SA_SHR_INV ] = { 0x0000000000000000ULL, 0x0000000000000100ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL ] = { 0x0000000000000000ULL, 0x0000000000000010ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_ADDR ] = { 0x0000000000000000ULL, 0x0000000000000001ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_RC_FULL ] = { 0x8000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_PTEG_FROM_L375_MOD ] = { 0x1000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_LSU1_FLUSH_UST ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0004000000000000ULL }, [ POWER5p_PME_PM_BR_ISSUED ] = { 0x0000000002040000ULL, 0x0000000000000000ULL, 0x0000000000000400ULL }, [ POWER5p_PME_PM_MRK_GRP_BR_REDIR ] = { 0x0000000000000000ULL, 0x0000000040000000ULL, 0x0800000000000000ULL }, [ POWER5p_PME_PM_EE_OFF ] = { 0x0000000000000000ULL, 0x0000080000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_IERAT_XLATE_WR_LP ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_DTLB_REF_64K ] = { 0x0000800000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MEM_RQ_DISP_Q4to7 ] = { 0x0000000000000000ULL, 0x0002000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MEM_FAST_PATH_RD_DISP ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_INST_FROM_L3 ] = { 0x0080000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_ITLB_MISS ] = { 0x0000000000200000ULL, 0x0000000000000000ULL, 0x0000000000000080ULL }, [ POWER5p_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { 0x0000000000000000ULL, 0x0000000020000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_DTLB_REF_4K ] = { 0x0000800000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FXLS_FULL_CYC ] = { 0x0000000000000000ULL, 0x0000000040000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_GRP_DISP_VALID ] = { 0x0000000000000004ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU_FLUSH_UST ] = { 0x0000000002100000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FXU1_FIN ] = { 0x0000000000000000ULL, 0x0000000080000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_THRD_PRIO_4_CYC ] = { 0x0000000000000000ULL, 0x0000000100000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD ] = { 0x0000000000000000ULL, 0x0200000000000000ULL, 0x0000000400000000ULL }, [ POWER5p_PME_PM_4INST_CLB_CYC ] = { 0x0000000000000000ULL, 0x0000000080000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_DTLB_REF_16M ] = { 0x0000000000000000ULL, 0x4000000000000000ULL, 0x0000050000000002ULL }, [ POWER5p_PME_PM_INST_FROM_L375_MOD ] = { 0x0400000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_GRP_CMPL ] = { 0x0000000000000002ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_ADDR ] = { 0x0000000000000000ULL, 0x0000000000000040ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPU1_1FLOP ] = { 0x0000000000000000ULL, 0x0000000008000000ULL, 0x0000000000002000ULL }, [ POWER5p_PME_PM_FPU_FRSP_FCONV ] = { 0x0000000000000000ULL, 0x0000000000040000ULL, 0x0000000000010000ULL }, [ POWER5p_PME_PM_L3SC_REF ] = { 0x0000000000000000ULL, 0x0000000000010000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_5INST_CLB_CYC ] = { 0x0000000000000010ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_THRD_L2MISS_BOTH_CYC ] = { 0x0000000000000000ULL, 0x0000001000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MEM_PW_GATH ] = { 0x0000000000000000ULL, 0x0008000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_DTLB_REF_16G ] = { 0x0000800000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FAB_DCLAIM_ISSUED ] = { 0x0000000000000000ULL, 0x0000010000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FAB_PNtoNN_SIDECAR ] = { 0x0000000000000000ULL, 0x0000040000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_GRP_IC_MISS ] = { 0x0000010000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_INST_FROM_L35_SHR ] = { 0x0400000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU_LMQ_FULL_CYC ] = { 0x0000000200000400ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_DATA_FROM_L2_CYC ] = { 0x0000000000000000ULL, 0x0080000000000000ULL, 0x0008000000000000ULL }, [ POWER5p_PME_PM_LSU_SRQ_SYNC_CYC ] = { 0x0000000000000100ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU0_BUSY_REJECT ] = { 0x0000004000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU_REJECT_ERAT_MISS ] = { 0x0000000000008000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_DATA_FROM_RMEM_CYC ] = { 0x0000000000000000ULL, 0x0400000000000000ULL, 0x0000000800000000ULL }, [ POWER5p_PME_PM_DATA_FROM_L375_SHR ] = { 0x0040000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_PTEG_FROM_L25_MOD ] = { 0x0800000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPU0_FMOV_FEST ] = { 0x0000000000000000ULL, 0x0000000000400000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_THRD_PRIO_7_CYC ] = { 0x0000000000000000ULL, 0x0000000100000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU1_FLUSH_SRQ ] = { 0x0000000001000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LD_REF_L1_LSU0 ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SC_RCST_DISP ] = { 0x0000000000000000ULL, 0x0000000000000040ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_CMPLU_STALL_DIV ] = { 0x0000000080000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MEM_RQ_DISP_Q12to15 ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_INST_FROM_L375_SHR ] = { 0x0400000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_ST_REF_L1 ] = { 0x0004200000000000ULL, 0x0000000000000000ULL, 0x00000000092040e0ULL }, [ POWER5p_PME_PM_L3SB_ALL_BUSY ] = { 0x0000000000000000ULL, 0x0000000000004000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FAB_P1toVNorNN_SIDECAR_EMPTY ] = { 0x0000000000000000ULL, 0x0000020000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR_CYC ] = { 0x0000000000000000ULL, 0x1400000000000000ULL, 0x0000002800000000ULL }, [ POWER5p_PME_PM_FAB_HOLDtoNN_EMPTY ] = { 0x0000000000000000ULL, 0x0000080000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_DATA_FROM_LMEM ] = { 0x0018000000000000ULL, 0x0000000000000000ULL, 0x0000000010000140ULL }, [ POWER5p_PME_PM_RUN_CYC ] = { 0xffffffffffffffffULL, 0xffffffffffffffffULL, 0x0fffffffffffffffULL }, [ POWER5p_PME_PM_PTEG_FROM_RMEM ] = { 0x2000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SC_RCLD_DISP ] = { 0x0000000000000000ULL, 0x0000000000000020ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU_LRQ_S0_VALID ] = { 0x0000000000000080ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU0_LDF ] = { 0x0000000000000000ULL, 0x0000000012000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_PMC3_OVERFLOW ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_IMR_RELOAD ] = { 0x0000000000000000ULL, 0x0010000000000000ULL, 0x0000400200000000ULL }, [ POWER5p_PME_PM_MRK_GRP_TIMEO ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000200000000010ULL }, [ POWER5p_PME_PM_ST_MISS_L1 ] = { 0x0004200000000000ULL, 0x0000000000000000ULL, 0x0000000008100100ULL }, [ POWER5p_PME_PM_STOP_COMPLETION ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU_BUSY_REJECT ] = { 0x0000000000002000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_ISLB_MISS ] = { 0x0000400000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_CYC ] = { 0x0002000040000003ULL, 0x0000008000000000ULL, 0x000000001eb40201ULL }, [ POWER5p_PME_PM_THRD_ONE_RUN_CYC ] = { 0x0000000000000000ULL, 0x0000001000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_GRP_BR_REDIR_NONSPEC ] = { 0x0000080000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU1_SRQ_STFWD ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L3SC_MOD_INV ] = { 0x0000000000000000ULL, 0x0000000000000400ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2_PREF ] = { 0x0000000000006000ULL, 0x0000000000000000ULL, 0x0000000000000200ULL }, [ POWER5p_PME_PM_GCT_NOSLOT_BR_MPRED ] = { 0x0000000000000020ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD ] = { 0x0000000000000000ULL, 0x0080000000000000ULL, 0x0080000100000000ULL }, [ POWER5p_PME_PM_L2SB_ST_REQ ] = { 0x0000000000000000ULL, 0x0000000000000010ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SB_MOD_INV ] = { 0x0000000000000000ULL, 0x0000000000001000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_L1_RELOAD_VALID ] = { 0x0000000000000000ULL, 0x0040000000000000ULL, 0x0000000080000000ULL }, [ POWER5p_PME_PM_L3SB_HIT ] = { 0x0000000000000000ULL, 0x0000000000008000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SB_SHR_MOD ] = { 0x0000000000000000ULL, 0x0000000000001000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_EE_OFF_EXT_INT ] = { 0x0000000000000000ULL, 0x0001000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_1PLUS_PPC_CMPL ] = { 0x0000000000000002ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SC_SHR_MOD ] = { 0x0000000000000000ULL, 0x0000000000002000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_PMC6_OVERFLOW ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_IC_PREF_INSTALL ] = { 0x0000008000001000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU_LRQ_FULL_CYC ] = { 0x0000000200000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_TLB_MISS ] = { 0x0000020000000000ULL, 0x0000000000000000ULL, 0x0000000000200000ULL }, [ POWER5p_PME_PM_GCT_FULL_CYC ] = { 0x0000000000000040ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FXU_BUSY ] = { 0x0000000000000000ULL, 0x0000000020000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_DATA_FROM_L3_CYC ] = { 0x0000000000000000ULL, 0x0200000000000000ULL, 0x0000000400000000ULL }, [ POWER5p_PME_PM_LSU_REJECT_LMQ_FULL ] = { 0x0000000000008000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU_SRQ_S0_ALLOC ] = { 0x0000000000000100ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_GRP_MRK ] = { 0x0000000020000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_INST_FROM_L25_SHR ] = { 0x0200000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_DC_PREF_STREAM_ALLOC ] = { 0x0000000000000800ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPU1_FIN ] = { 0x0000000000000000ULL, 0x0000000000080000ULL, 0x000000000000a000ULL }, [ POWER5p_PME_PM_BR_MPRED_TA ] = { 0x0000020000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_DTLB_REF_64K ] = { 0x0000000000000000ULL, 0x4000000000000000ULL, 0x0000010000000000ULL }, [ POWER5p_PME_PM_RUN_INST_CMPL ] = { 0xffffffffffffffffULL, 0xffffffffffffffffULL, 0x0fffffffffffffffULL }, [ POWER5p_PME_PM_CRQ_FULL_CYC ] = { 0x0000000800000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SA_RCLD_DISP ] = { 0x8000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_SNOOP_WR_RETRY_QFULL ] = { 0x0000000000000000ULL, 0x0000100000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_DTLB_REF_4K ] = { 0x0000000000000000ULL, 0x4000000000000000ULL, 0x0002040000000002ULL }, [ POWER5p_PME_PM_LSU_SRQ_S0_VALID ] = { 0x0000000000000100ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU0_FLUSH_LRQ ] = { 0x0000000000800000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_INST_FROM_L275_MOD ] = { 0x0200000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_GCT_EMPTY_CYC ] = { 0x0000000000000002ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LARX_LSU0 ] = { 0x0000000200000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_THRD_PRIO_DIFF_5or6_CYC ] = { 0x0000000000000000ULL, 0x0000000200000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_SNOOP_RETRY_1AHEAD ] = { 0x0000000000000000ULL, 0x0000200000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPU1_FSQRT ] = { 0x0000000000000000ULL, 0x0000000000200000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_LD_MISS_L1_LSU1 ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0040000000000000ULL }, [ POWER5p_PME_PM_MRK_FPU_FIN ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0400200000000010ULL }, [ POWER5p_PME_PM_THRD_PRIO_5_CYC ] = { 0x0000000000000000ULL, 0x0000000400000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_DATA_FROM_LMEM ] = { 0x0000000000000000ULL, 0x0800000000000000ULL, 0x0000001000000000ULL }, [ POWER5p_PME_PM_SNOOP_TLBIE ] = { 0x0000000000000000ULL, 0x0000002000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPU1_FRSP_FCONV ] = { 0x0000000000000000ULL, 0x0000000004800000ULL, 0x0000000000001000ULL }, [ POWER5p_PME_PM_DTLB_MISS_16G ] = { 0x0001000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L3SB_SNOOP_RETRY ] = { 0x0000000000000000ULL, 0x0000000000004000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FAB_VBYPASS_EMPTY ] = { 0x0000000000000000ULL, 0x0000020000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD ] = { 0x0000000000000000ULL, 0x1000000000000000ULL, 0x0001000000000000ULL }, [ POWER5p_PME_PM_L2SB_RCST_DISP ] = { 0x0000000000000000ULL, 0x0000000000000008ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_6INST_CLB_CYC ] = { 0x0000000000000010ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FLUSH ] = { 0x0008000000080000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SC_MOD_INV ] = { 0x0000000000000000ULL, 0x0000000000002000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPU_DENORM ] = { 0x0000000000000000ULL, 0x0000000000080000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L3SC_HIT ] = { 0x0000000000000000ULL, 0x0000000000010000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_SNOOP_WR_RETRY_RQ ] = { 0x0000000000000000ULL, 0x0000400000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU1_REJECT_SRQ ] = { 0x0000000000004000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L3SC_ALL_BUSY ] = { 0x0000000000000000ULL, 0x0000000000010000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_IC_PREF_REQ ] = { 0x0000008000000000ULL, 0x0000000000000000ULL, 0x0000000000000200ULL }, [ POWER5p_PME_PM_MRK_GRP_IC_MISS ] = { 0x0000000000000000ULL, 0x0040000000000000ULL, 0x0000000080000000ULL }, [ POWER5p_PME_PM_GCT_NOSLOT_IC_MISS ] = { 0x0000000000000020ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_DATA_FROM_L3 ] = { 0x0000000000000000ULL, 0x0200000000000000ULL, 0x0000400000000000ULL }, [ POWER5p_PME_PM_GCT_NOSLOT_SRQ_FULL ] = { 0x0000000000000020ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_CMPLU_STALL_DCACHE_MISS ] = { 0x0000000040000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_THRD_SEL_OVER_ISU_HOLD ] = { 0x0000000000000000ULL, 0x0000008000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU_FLUSH_LRQ ] = { 0x0000000000400000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_THRD_PRIO_2_CYC ] = { 0x0000000000000000ULL, 0x0000000400000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L3SA_MOD_INV ] = { 0x0000000000000000ULL, 0x0000000000000100ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU_FLUSH_SRQ ] = { 0x0000000000400000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_LSU_SRQ_INST_VALID ] = { 0x0000000000000010ULL, 0x0000000000000000ULL, 0x0200000000000000ULL }, [ POWER5p_PME_PM_L3SA_REF ] = { 0x0000000000000000ULL, 0x0000000000008000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL ] = { 0x0000000000000000ULL, 0x0000000000000080ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPU0_STALL3 ] = { 0x0000000000000000ULL, 0x0000000001000000ULL, 0x0000000000000800ULL }, [ POWER5p_PME_PM_TB_BIT_TRANS ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_GPR_MAP_FULL_CYC ] = { 0x0000000800000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_LSU_FLUSH_LRQ ] = { 0x0000000010000000ULL, 0x0000000000000000ULL, 0x0100000000000000ULL }, [ POWER5p_PME_PM_FPU0_STF ] = { 0x0000000000000000ULL, 0x0000000010000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_DTLB_MISS ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000800000000001ULL }, [ POWER5p_PME_PM_FPU1_FMA ] = { 0x0000000000000000ULL, 0x0000000004000000ULL, 0x0000000000001000ULL }, [ POWER5p_PME_PM_L2SA_MOD_TAG ] = { 0x0000000000000000ULL, 0x0000000000000800ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU1_FLUSH_ULD ] = { 0x0000000004000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_INST_FIN ] = { 0x0000000000000000ULL, 0x0020000000000000ULL, 0x0800000040000000ULL }, [ POWER5p_PME_PM_MRK_LSU0_FLUSH_UST ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0008000000000000ULL }, [ POWER5p_PME_PM_FPU0_FULL_CYC ] = { 0x0000000400000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU_LRQ_S0_ALLOC ] = { 0x0000000000000080ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_LSU1_FLUSH_ULD ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0004000000000000ULL }, [ POWER5p_PME_PM_MRK_DTLB_REF ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0001000000000001ULL }, [ POWER5p_PME_PM_BR_UNCOND ] = { 0x0000040000000000ULL, 0x0000000000000000ULL, 0x0000000000000400ULL }, [ POWER5p_PME_PM_THRD_SEL_OVER_L2MISS ] = { 0x0000000000000000ULL, 0x0000008000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SB_SHR_INV ] = { 0x0000000000000000ULL, 0x0000000000001000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MEM_LO_PRIO_WR_CMPL ] = { 0x0000000000000000ULL, 0x0000400000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_DTLB_MISS_64K ] = { 0x0000000000000000ULL, 0x8000000000000000ULL, 0x0000028000000000ULL }, [ POWER5p_PME_PM_MRK_ST_MISS_L1 ] = { 0x0000000000000000ULL, 0x0020000000000000ULL, 0x0040000000000008ULL }, [ POWER5p_PME_PM_L3SC_MOD_TAG ] = { 0x0000000000000000ULL, 0x0000000000000400ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_GRP_DISP_SUCCESS ] = { 0x4000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_THRD_PRIO_DIFF_1or2_CYC ] = { 0x0000000000000000ULL, 0x0000000100000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = { 0x0000004000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU_DERAT_MISS ] = { 0x0000200000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MEM_WQ_DISP_Q8to15 ] = { 0x0000000000000000ULL, 0x0004000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPU0_SINGLE ] = { 0x0000000000000000ULL, 0x0000000002000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_THRD_PRIO_1_CYC ] = { 0x0000000000000000ULL, 0x0000000800000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_OTHER ] = { 0x0000000000000000ULL, 0x0000000000000040ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_SNOOP_RD_RETRY_RQ ] = { 0x0000000000000000ULL, 0x0000200000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FAB_HOLDtoVN_EMPTY ] = { 0x0000000000000000ULL, 0x0000020000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPU1_FEST ] = { 0x0000000000000000ULL, 0x0000000000200000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_SNOOP_DCLAIM_RETRY_QFULL ] = { 0x0000000000000000ULL, 0x0000100000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR_CYC ] = { 0x0000000000000000ULL, 0x0100000000000000ULL, 0x0000400000000000ULL }, [ POWER5p_PME_PM_MRK_ST_CMPL_INT ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000080000000004ULL }, [ POWER5p_PME_PM_FLUSH_BR_MPRED ] = { 0x0000080000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_DTLB_MISS_16G ] = { 0x0000000000000000ULL, 0x8000000000000000ULL, 0x0000028000000000ULL }, [ POWER5p_PME_PM_FPU_STF ] = { 0x0000000000000000ULL, 0x0000000000100000ULL, 0x00000000020a8000ULL }, [ POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR ] = { 0x0000000000000000ULL, 0x0000000000000004ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_CMPLU_STALL_FPU ] = { 0x0000000100000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC ] = { 0x0000000000000000ULL, 0x0000000400000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_GCT_NOSLOT_CYC ] = { 0x0000000000000020ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { 0x0000000000000000ULL, 0x0000000020000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_PTEG_FROM_L35_SHR ] = { 0x1000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_DTLB_REF_16G ] = { 0x0000000000000000ULL, 0x4000000000000000ULL, 0x0000010000000000ULL }, [ POWER5p_PME_PM_MRK_LSU_FLUSH_UST ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0100100000000008ULL }, [ POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR ] = { 0x0000000000000000ULL, 0x0100000000000000ULL, 0x0000000200000000ULL }, [ POWER5p_PME_PM_L3SA_HIT ] = { 0x0000000000000000ULL, 0x0000000000008000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR ] = { 0x0000000000000000ULL, 0x0800000000000000ULL, 0x0000001000000000ULL }, [ POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_ADDR ] = { 0x0000000000000000ULL, 0x0000000000000008ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_IERAT_XLATE_WR ] = { 0x0000008000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SA_ST_REQ ] = { 0x0000000000000000ULL, 0x0000000000000002ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_INST_FROM_LMEM ] = { 0x0100000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_THRD_SEL_T1 ] = { 0x0000000000000000ULL, 0x0000002000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = { 0x0000004000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR_CYC ] = { 0x0000000000000000ULL, 0x0800000000000000ULL, 0x0000800000000000ULL }, [ POWER5p_PME_PM_FPU0_1FLOP ] = { 0x0000000000000000ULL, 0x0000000008000000ULL, 0x0000000000002000ULL }, [ POWER5p_PME_PM_PTEG_FROM_L2 ] = { 0x2000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MEM_PW_CMPL ] = { 0x0000000000000000ULL, 0x0008000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC ] = { 0x0000000000000000ULL, 0x0000000800000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER ] = { 0x0000000000000000ULL, 0x0000000000000004ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_DTLB_MISS_4K ] = { 0x0000000000000000ULL, 0x8000000000000000ULL, 0x0005000000000000ULL }, [ POWER5p_PME_PM_FPU0_FIN ] = { 0x0000000000000000ULL, 0x0000000008080000ULL, 0x000000000000a800ULL }, [ POWER5p_PME_PM_L3SC_SHR_INV ] = { 0x0000000000000000ULL, 0x0000000000000400ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_GRP_BR_REDIR ] = { 0x0000080000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL ] = { 0x0000000000000000ULL, 0x0000000000000020ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_LSU_FLUSH_SRQ ] = { 0x0000000000008000ULL, 0x0000000000000000ULL, 0x0100000000000000ULL }, [ POWER5p_PME_PM_PTEG_FROM_L275_SHR ] = { 0x0800000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL ] = { 0x0000000000000000ULL, 0x0000000000000004ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_SNOOP_RD_RETRY_WQ ] = { 0x0000000000000000ULL, 0x0000200000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FAB_DCLAIM_RETRIED ] = { 0x0000000000000000ULL, 0x0000010000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU0_NCLD ] = { 0x0000002000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU1_BUSY_REJECT ] = { 0x0000004000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FXLS0_FULL_CYC ] = { 0x0000000400000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_DTLB_REF_16M ] = { 0x0000800000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPU0_FEST ] = { 0x0000000000000000ULL, 0x0000000000200000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_GCT_USAGE_60to79_CYC ] = { 0x0000000000000040ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_DATA_FROM_L25_MOD ] = { 0x0020000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR ] = { 0x0000000000000000ULL, 0x0000000000000020ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU0_REJECT_ERAT_MISS ] = { 0x0000000000020000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_DATA_FROM_L375_MOD ] = { 0x0040000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { 0x0000000000000600ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_DTLB_MISS_64K ] = { 0x0001000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU0_REJECT_RELOAD_CDF ] = { 0x0000000000010000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_0INST_FETCH ] = { 0x0100008000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU1_REJECT_RELOAD_CDF ] = { 0x0000000000010000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MEM_WQ_DISP_Q0to7 ] = { 0x0000000000000000ULL, 0x0004000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L1_PREF ] = { 0x0000000000001000ULL, 0x0000000000000000ULL, 0x0000000000000200ULL }, [ POWER5p_PME_PM_MRK_DATA_FROM_LMEM_CYC ] = { 0x0000000000000000ULL, 0x0800000000000000ULL, 0x0000001000000000ULL }, [ POWER5p_PME_PM_BRQ_FULL_CYC ] = { 0x0000000200000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_GRP_IC_MISS_NONSPEC ] = { 0x0000010000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_PTEG_FROM_L275_MOD ] = { 0x0800000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_LD_MISS_L1_LSU0 ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0040000000000000ULL }, [ POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR_CYC ] = { 0x0000000000000000ULL, 0x2000000000000000ULL, 0x0000004000000000ULL }, [ POWER5p_PME_PM_DATA_FROM_L3 ] = { 0x0018000000000000ULL, 0x0000000000000000ULL, 0x0000000000000140ULL }, [ POWER5p_PME_PM_INST_FROM_L2 ] = { 0x0100000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU_FLUSH ] = { 0x000000000dc80000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_PMC2_OVERFLOW ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPU0_DENORM ] = { 0x0000000000000000ULL, 0x0000000000400000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPU1_FMOV_FEST ] = { 0x0000000000000000ULL, 0x0000000000400000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_INST_FETCH_CYC ] = { 0x0000000000000800ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_INST_DISP ] = { 0x0000000000000005ULL, 0x0000000000000000ULL, 0x0000000001080000ULL }, [ POWER5p_PME_PM_LSU_LDF ] = { 0x0000000000000000ULL, 0x0000000000100000ULL, 0x0000000000080000ULL }, [ POWER5p_PME_PM_DATA_FROM_L25_SHR ] = { 0x0020000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L1_DCACHE_RELOAD_VALID ] = { 0x0000010000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MEM_WQ_DISP_DCLAIM ] = { 0x0000000000000000ULL, 0x0004000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_GRP_ISSUED ] = { 0x0000000000000000ULL, 0x0040000000000000ULL, 0x0000000080000000ULL }, [ POWER5p_PME_PM_FPU_FULL_CYC ] = { 0x0000000100000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_INST_FROM_L35_MOD ] = { 0x0400000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPU_FMA ] = { 0x0000000000000000ULL, 0x0000000000020000ULL, 0x0000000002424000ULL }, [ POWER5p_PME_PM_THRD_PRIO_3_CYC ] = { 0x0000000000000000ULL, 0x0000000200000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_CRU_FIN ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000080000000004ULL }, [ POWER5p_PME_PM_SNOOP_WR_RETRY_WQ ] = { 0x0000000000000000ULL, 0x0000400000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_CMPLU_STALL_REJECT ] = { 0x0000000020000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_FXU_FIN ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0400000000040000ULL }, [ POWER5p_PME_PM_LSU1_REJECT_ERAT_MISS ] = { 0x0000000000020000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_OTHER ] = { 0x0000000000000000ULL, 0x0000000000000008ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY ] = { 0x0000000000000000ULL, 0x0000000000000080ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_PMC4_OVERFLOW ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L3SA_SNOOP_RETRY ] = { 0x0000000000000000ULL, 0x0000000000004000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_PTEG_FROM_L35_MOD ] = { 0x1000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_INST_FROM_L25_MOD ] = { 0x0200000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_THRD_SMT_HANG ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_CMPLU_STALL_ERAT_MISS ] = { 0x0000000040000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L3SA_MOD_TAG ] = { 0x0000000000000000ULL, 0x0000000000000100ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_INST_FROM_L2MISS ] = { 0x0000000000000800ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FLUSH_SYNC ] = { 0x0000000000200000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_GRP_DISP ] = { 0x0000000000000000ULL, 0x0030000040000000ULL, 0x0000000060000000ULL }, [ POWER5p_PME_PM_MEM_RQ_DISP_Q8to11 ] = { 0x0000000000000000ULL, 0x0002000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SC_ST_HIT ] = { 0x0000000000000000ULL, 0x0000000000000080ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SB_MOD_TAG ] = { 0x0000000000000000ULL, 0x0000000000001000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_CLB_EMPTY_CYC ] = { 0x0000000000000008ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SB_ST_HIT ] = { 0x0000000000000000ULL, 0x0000000000000010ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MEM_NONSPEC_RD_CANCEL ] = { 0x0000000000000000ULL, 0x0001000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_BR_PRED_CR_TA ] = { 0x0000040000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_LSU0_FLUSH_SRQ ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0012000000000000ULL }, [ POWER5p_PME_PM_MRK_LSU_FLUSH_ULD ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000100000000008ULL }, [ POWER5p_PME_PM_INST_DISP_ATTEMPT ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000100000ULL }, [ POWER5p_PME_PM_INST_FROM_RMEM ] = { 0x0080000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_ST_REF_L1_LSU0 ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU0_DERAT_MISS ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPU_STALL3 ] = { 0x0000000000000000ULL, 0x0000000000080000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SB_RCLD_DISP ] = { 0x0000000000000000ULL, 0x0000000000000004ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_BR_PRED_CR ] = { 0x0000040000000000ULL, 0x0000000000000000ULL, 0x0000000000000400ULL }, [ POWER5p_PME_PM_MRK_DATA_FROM_L2 ] = { 0x0000000000000000ULL, 0x0080000000000000ULL, 0x0200000100000000ULL }, [ POWER5p_PME_PM_LSU0_FLUSH_SRQ ] = { 0x0000000001000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FAB_PNtoNN_DIRECT ] = { 0x0000000000000000ULL, 0x0000040000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_IOPS_CMPL ] = { 0x01080911fff53010ULL, 0x110020f81d100700ULL, 0x0002002000000006ULL }, [ POWER5p_PME_PM_L2SA_RCST_DISP ] = { 0x0000000000000000ULL, 0x0000000000000001ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_OTHER ] = { 0x0000000000000000ULL, 0x0000000000000001ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SC_SHR_INV ] = { 0x0000000000000000ULL, 0x0000000000002000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_SNOOP_RETRY_AB_COLLISION ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FAB_PNtoVN_SIDECAR ] = { 0x0000000000000000ULL, 0x0000040000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU0_REJECT_LMQ_FULL ] = { 0x0000000000040000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU_LMQ_S0_ALLOC ] = { 0x0000000000000080ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_SNOOP_PW_RETRY_RQ ] = { 0x0000000000000000ULL, 0x0000800000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_DTLB_REF ] = { 0x0002000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_PTEG_FROM_L3 ] = { 0x4000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY ] = { 0x0000000000000000ULL, 0x0000080000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU_SRQ_EMPTY_CYC ] = { 0x0000000000000600ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPU1_STF ] = { 0x0000000000000000ULL, 0x0000000010000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU_LMQ_S0_VALID ] = { 0x0000000000000080ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_GCT_USAGE_00to59_CYC ] = { 0x0000000000000040ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPU_FMOV_FEST ] = { 0x0000000000000000ULL, 0x0000000000020000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_DATA_FROM_L2MISS ] = { 0x0010000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_XER_MAP_FULL_CYC ] = { 0x0000001000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_GRP_DISP_BLK_SB_CYC ] = { 0x0000000000000004ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FLUSH_SB ] = { 0x0000000000200000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR ] = { 0x0000000000000000ULL, 0x2000000000000000ULL, 0x0000004000000000ULL }, [ POWER5p_PME_PM_MRK_GRP_CMPL ] = { 0x0000000000000000ULL, 0x0020000000000000ULL, 0x0800000040000000ULL }, [ POWER5p_PME_PM_SUSPENDED ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_SNOOP_RD_RETRY_QFULL ] = { 0x0000000000000000ULL, 0x0000100000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC ] = { 0x0000000080000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_DATA_FROM_L35_SHR ] = { 0x0040000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L3SB_MOD_INV ] = { 0x0000000000000000ULL, 0x0000000000000200ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_STCX_FAIL ] = { 0x0000002000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LD_MISS_L1_LSU1 ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_GRP_DISP ] = { 0x4000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_DC_PREF_DST ] = { 0x0000000000004000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPU1_DENORM ] = { 0x0000000000000000ULL, 0x0000000000400000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPU0_FPSCR ] = { 0x0000000000000000ULL, 0x0000000001000000ULL, 0x0000000000000800ULL }, [ POWER5p_PME_PM_DATA_FROM_L2 ] = { 0x0000200000000000ULL, 0x0000000000000000ULL, 0x0000000000000020ULL }, [ POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR ] = { 0x8000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPU_1FLOP ] = { 0x0000000000000000ULL, 0x0000000000040000ULL, 0x0000000000424000ULL }, [ POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER ] = { 0x0000000000000000ULL, 0x0000000000000020ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPU0_FSQRT ] = { 0x0000000000000000ULL, 0x0000000000200000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL ] = { 0x0000000000000000ULL, 0x0000000000000040ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LD_REF_L1 ] = { 0x0004100000000000ULL, 0x0000000000000000ULL, 0x00000000052040e0ULL }, [ POWER5p_PME_PM_INST_FROM_L1 ] = { 0x0080000000000000ULL, 0x0000000000000000ULL, 0x0000000000000020ULL }, [ POWER5p_PME_PM_TLBIE_HELD ] = { 0x0000000000020000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_DC_PREF_OUT_OF_STREAMS ] = { 0x0000000000000800ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD_CYC ] = { 0x0000000000000000ULL, 0x0080000000000000ULL, 0x0000000100000000ULL }, [ POWER5p_PME_PM_MRK_LSU1_FLUSH_SRQ ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0020000000000000ULL }, [ POWER5p_PME_PM_MEM_RQ_DISP_Q0to3 ] = { 0x0000000000000000ULL, 0x0002000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_ST_REF_L1_LSU1 ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_LD_MISS_L1 ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000080000000004ULL }, [ POWER5p_PME_PM_L1_WRITE_CYC ] = { 0x0000000000010000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SC_ST_REQ ] = { 0x0000000000000000ULL, 0x0000000000000080ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_CMPLU_STALL_FDIV ] = { 0x0000000100000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_THRD_SEL_OVER_CLB_EMPTY ] = { 0x0000000000000000ULL, 0x0000004000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_BR_MPRED_CR ] = { 0x0000020000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L3SB_MOD_TAG ] = { 0x0000000000000000ULL, 0x0000000000000200ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_DATA_FROM_L2MISS ] = { 0x0000001000000000ULL, 0x0000000000000000ULL, 0x0200000000000000ULL }, [ POWER5p_PME_PM_LSU_REJECT_SRQ ] = { 0x0000000000080000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LD_MISS_L1 ] = { 0x0004100000000000ULL, 0x0000000000000000ULL, 0x0000000004900100ULL }, [ POWER5p_PME_PM_INST_FROM_PREF ] = { 0x0080000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_STCX_PASS ] = { 0x0000002000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_DC_INV_L2 ] = { 0x4000000000100000ULL, 0x0000000000000000ULL, 0x0000000000800000ULL }, [ POWER5p_PME_PM_LSU_SRQ_FULL_CYC ] = { 0x0000000000000500ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPU_FIN ] = { 0x0000000000000000ULL, 0x0100000000040000ULL, 0x0000000202070000ULL }, [ POWER5p_PME_PM_LSU_SRQ_STFWD ] = { 0x0000000000000200ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SA_SHR_MOD ] = { 0x0000000000000000ULL, 0x0000000000000800ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_0INST_CLB_CYC ] = { 0x0000000000000008ULL, 0x0000004000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FXU0_FIN ] = { 0x0000000000000000ULL, 0x0000000080000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL ] = { 0x0000000000000000ULL, 0x0000000000000008ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = { 0x0000000000000000ULL, 0x0000001000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_PMC5_OVERFLOW ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_FPU0_FDIV ] = { 0x0000000000000000ULL, 0x0000000000800000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_PTEG_FROM_L375_SHR ] = { 0x1000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_HV_CYC ] = { 0x0000000000000000ULL, 0x0000000800000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY ] = { 0x0000000000000000ULL, 0x0000000000000002ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_THRD_PRIO_DIFF_0_CYC ] = { 0x0000000000000000ULL, 0x0000000100000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LR_CTR_MAP_FULL_CYC ] = { 0x0000000800000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L3SB_SHR_INV ] = { 0x0000000000000000ULL, 0x0000000000000200ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_DATA_FROM_RMEM ] = { 0x0010000000000000ULL, 0x0000000000000000ULL, 0x0000000010000000ULL }, [ POWER5p_PME_PM_DATA_FROM_L275_MOD ] = { 0x0020000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU0_REJECT_SRQ ] = { 0x0000000000004000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU1_DERAT_MISS ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_MRK_LSU_FIN ] = { 0x0000000000000000ULL, 0x0010000000000000ULL, 0x0400000020000000ULL }, [ POWER5p_PME_PM_DTLB_MISS_16M ] = { 0x0001000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_LSU0_FLUSH_UST ] = { 0x0000000008000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY ] = { 0x0000000000000000ULL, 0x0000000000000010ULL, 0x0000000000000000ULL }, [ POWER5p_PME_PM_L2SC_MOD_TAG ] = { 0x0000000000000000ULL, 0x0000000000002000ULL, 0x0000000000000000ULL } }; static const pme_power_entry_t power5p_pe[] = { [ POWER5p_PME_PM_LSU_REJECT_RELOAD_CDF ] = { .pme_name = "PM_LSU_REJECT_RELOAD_CDF", .pme_code = 0x2c4090, .pme_short_desc = "LSU reject due to reload CDF or tag update collision", .pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions because of Critical Data Forward. When critical data arrives from the storage system it is formatted and immediately forwarded, bypassing the data cache, to the destination register using the result bus. Any instruction the requires the result bus in the same cycle is rejected. Tag update rejects are caused when an instruction requires access to the Dcache directory or ERAT in the same system when they are being updated. Combined Unit 0 + 1.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_REJECT_RELOAD_CDF], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_REJECT_RELOAD_CDF] }, [ POWER5p_PME_PM_FPU1_SINGLE ] = { .pme_name = "PM_FPU1_SINGLE", .pme_code = 0x20e7, .pme_short_desc = "FPU1 executed single precision instruction", .pme_long_desc = "FPU1 has executed a single precision instruction.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU1_SINGLE], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU1_SINGLE] }, [ POWER5p_PME_PM_L3SB_REF ] = { .pme_name = "PM_L3SB_REF", .pme_code = 0x701c4, .pme_short_desc = "L3 slice B references", .pme_long_desc = "Number of attempts made by this chip cores to find data in the L3. Reported per L3 slice", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SB_REF], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SB_REF] }, [ POWER5p_PME_PM_THRD_PRIO_DIFF_3or4_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_3or4_CYC", .pme_code = 0x430e5, .pme_short_desc = "Cycles thread priority difference is 3 or 4", .pme_long_desc = "Cycles when this thread's priority is higher than the other thread's priority by 3 or 4.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_PRIO_DIFF_3or4_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_PRIO_DIFF_3or4_CYC] }, [ POWER5p_PME_PM_INST_FROM_L275_SHR ] = { .pme_name = "PM_INST_FROM_L275_SHR", .pme_code = 0x322096, .pme_short_desc = "Instruction fetched from L2.75 shared", .pme_long_desc = "An instruction fetch group was fetched with shared (T) data from the L2 on a different module than this processor is located. Fetch groups can contain up to 8 instructions", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_L275_SHR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_L275_SHR] }, [ POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L375_MOD", .pme_code = 0x1c70a7, .pme_short_desc = "Marked data loaded from L3.75 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L3 of a chip on a different module than this processor is located due to a marked load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD] }, [ POWER5p_PME_PM_DTLB_MISS_4K ] = { .pme_name = "PM_DTLB_MISS_4K", .pme_code = 0x1c208d, .pme_short_desc = "Data TLB miss for 4K page", .pme_long_desc = "Data TLB references to 4KB pages that missed the TLB. Page size is determined at TLB reload time.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DTLB_MISS_4K], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DTLB_MISS_4K] }, [ POWER5p_PME_PM_CLB_FULL_CYC ] = { .pme_name = "PM_CLB_FULL_CYC", .pme_code = 0x220e5, .pme_short_desc = "Cycles CLB full", .pme_long_desc = "Cycles when both thread's CLB is full.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_CLB_FULL_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_CLB_FULL_CYC] }, [ POWER5p_PME_PM_MRK_ST_CMPL ] = { .pme_name = "PM_MRK_ST_CMPL", .pme_code = 0x100003, .pme_short_desc = "Marked store instruction completed", .pme_long_desc = "A sampled store has completed (data home)", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_ST_CMPL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_ST_CMPL] }, [ POWER5p_PME_PM_LSU_FLUSH_LRQ_FULL ] = { .pme_name = "PM_LSU_FLUSH_LRQ_FULL", .pme_code = 0x320e7, .pme_short_desc = "Flush caused by LRQ full", .pme_long_desc = "This thread was flushed at dispatch because its Load Request Queue was full. This allows the other thread to have more machine resources for it to make progress while this thread is stalled.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_FLUSH_LRQ_FULL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_FLUSH_LRQ_FULL] }, [ POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L275_SHR", .pme_code = 0x3c7097, .pme_short_desc = "Marked data loaded from L2.75 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (T) data from the L2 on a different module than this processor is located due to a marked load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR] }, [ POWER5p_PME_PM_1INST_CLB_CYC ] = { .pme_name = "PM_1INST_CLB_CYC", .pme_code = 0x400c1, .pme_short_desc = "Cycles 1 instruction in CLB", .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_1INST_CLB_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_1INST_CLB_CYC] }, [ POWER5p_PME_PM_MEM_SPEC_RD_CANCEL ] = { .pme_name = "PM_MEM_SPEC_RD_CANCEL", .pme_code = 0x721e6, .pme_short_desc = "Speculative memory read cancelled", .pme_long_desc = "Speculative memory read cancelled (i.e. cresp = sourced by L2/L3)", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_SPEC_RD_CANCEL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_SPEC_RD_CANCEL] }, [ POWER5p_PME_PM_MRK_DTLB_MISS_16M ] = { .pme_name = "PM_MRK_DTLB_MISS_16M", .pme_code = 0x3c608d, .pme_short_desc = "Marked Data TLB misses for 16M page", .pme_long_desc = "Marked Data TLB misses for 16M page", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DTLB_MISS_16M], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DTLB_MISS_16M] }, [ POWER5p_PME_PM_FPU_FDIV ] = { .pme_name = "PM_FPU_FDIV", .pme_code = 0x100088, .pme_short_desc = "FPU executed FDIV instruction", .pme_long_desc = "The floating point unit has executed a divide instruction. This could be fdiv, fdivs, fdiv., fdivs.. Combined Unit 0 + Unit 1.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU_FDIV], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU_FDIV] }, [ POWER5p_PME_PM_FPU_SINGLE ] = { .pme_name = "PM_FPU_SINGLE", .pme_code = 0x102090, .pme_short_desc = "FPU executed single precision instruction", .pme_long_desc = "FPU is executing single precision instruction. Combined Unit 0 + Unit 1.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU_SINGLE], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU_SINGLE] }, [ POWER5p_PME_PM_FPU0_FMA ] = { .pme_name = "PM_FPU0_FMA", .pme_code = 0xc1, .pme_short_desc = "FPU0 executed multiply-add instruction", .pme_long_desc = "The floating point unit has executed a multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU0_FMA], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU0_FMA] }, [ POWER5p_PME_PM_SLB_MISS ] = { .pme_name = "PM_SLB_MISS", .pme_code = 0x280088, .pme_short_desc = "SLB misses", .pme_long_desc = "Total of all Segment Lookaside Buffer (SLB) misses, Instructions + Data.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SLB_MISS], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SLB_MISS] }, [ POWER5p_PME_PM_LSU1_FLUSH_LRQ ] = { .pme_name = "PM_LSU1_FLUSH_LRQ", .pme_code = 0xc00c6, .pme_short_desc = "LSU1 LRQ flushes", .pme_long_desc = "A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU1_FLUSH_LRQ], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU1_FLUSH_LRQ] }, [ POWER5p_PME_PM_L2SA_ST_HIT ] = { .pme_name = "PM_L2SA_ST_HIT", .pme_code = 0x733e0, .pme_short_desc = "L2 slice A store hits", .pme_long_desc = "A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A, B, and C.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_ST_HIT], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_ST_HIT] }, [ POWER5p_PME_PM_DTLB_MISS ] = { .pme_name = "PM_DTLB_MISS", .pme_code = 0x800c4, .pme_short_desc = "Data TLB misses", .pme_long_desc = "Data TLB misses, all page sizes.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DTLB_MISS], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DTLB_MISS] }, [ POWER5p_PME_PM_BR_PRED_TA ] = { .pme_name = "PM_BR_PRED_TA", .pme_code = 0x230e3, .pme_short_desc = "A conditional branch was predicted", .pme_long_desc = " target prediction", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_BR_PRED_TA], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_BR_PRED_TA] }, [ POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L375_MOD_CYC", .pme_code = 0x4c70a7, .pme_short_desc = "Marked load latency from L3.75 modified", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L375_MOD_CYC] }, [ POWER5p_PME_PM_CMPLU_STALL_FXU ] = { .pme_name = "PM_CMPLU_STALL_FXU", .pme_code = 0x211099, .pme_short_desc = "Completion stall caused by FXU instruction", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point instruction.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_CMPLU_STALL_FXU], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_CMPLU_STALL_FXU] }, [ POWER5p_PME_PM_EXT_INT ] = { .pme_name = "PM_EXT_INT", .pme_code = 0x400003, .pme_short_desc = "External interrupts", .pme_long_desc = "An interrupt due to an external exception occurred", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_EXT_INT], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_EXT_INT] }, [ POWER5p_PME_PM_MRK_LSU1_FLUSH_LRQ ] = { .pme_name = "PM_MRK_LSU1_FLUSH_LRQ", .pme_code = 0x810c6, .pme_short_desc = "LSU1 marked LRQ flushes", .pme_long_desc = "A marked load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LSU1_FLUSH_LRQ], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LSU1_FLUSH_LRQ] }, [ POWER5p_PME_PM_MRK_ST_GPS ] = { .pme_name = "PM_MRK_ST_GPS", .pme_code = 0x200003, .pme_short_desc = "Marked store sent to GPS", .pme_long_desc = "A sampled store has been sent to the memory subsystem", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_ST_GPS], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_ST_GPS] }, [ POWER5p_PME_PM_LSU1_LDF ] = { .pme_name = "PM_LSU1_LDF", .pme_code = 0xc50c4, .pme_short_desc = "LSU1 executed Floating Point load instruction", .pme_long_desc = "A floating point load was executed by LSU1", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU1_LDF], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU1_LDF] }, [ POWER5p_PME_PM_FAB_CMD_ISSUED ] = { .pme_name = "PM_FAB_CMD_ISSUED", .pme_code = 0x700c7, .pme_short_desc = "Fabric command issued", .pme_long_desc = "Incremented when a chip issues a command on its SnoopA address bus. Each of the two address busses (SnoopA and SnoopB) is capable of one transaction per fabric cycle (one fabric cycle = 2 cpu cycles in normal 2:1 mode), but each chip can only drive the SnoopA bus, and can only drive one transaction every two fabric cycles (i.e., every four cpu cycles). In MCM-based systems, two chips interleave their accesses to each of the two fabric busses (SnoopA, SnoopB) to reach a peak capability of one transaction per cpu clock cycle. The two chips that drive SnoopB are wired so that the chips refer to the bus as SnoopA but it is connected to the other two chips as SnoopB. Note that this event will only be recorded by the FBC on the chip that sourced the operation. The signal is delivered at FBC speed and the count must be scaled.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_CMD_ISSUED], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_CMD_ISSUED] }, [ POWER5p_PME_PM_LSU0_SRQ_STFWD ] = { .pme_name = "PM_LSU0_SRQ_STFWD", .pme_code = 0xc60e1, .pme_short_desc = "LSU0 SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load on unit 0. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU0_SRQ_STFWD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU0_SRQ_STFWD] }, [ POWER5p_PME_PM_CR_MAP_FULL_CYC ] = { .pme_name = "PM_CR_MAP_FULL_CYC", .pme_code = 0x100c4, .pme_short_desc = "Cycles CR logical operation mapper full", .pme_long_desc = "The Conditional Register mapper cannot accept any more groups. This condition will prevent dispatch groups from being dispatched. This event only indicates that the mapper was full, not that dispatch was prevented.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_CR_MAP_FULL_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_CR_MAP_FULL_CYC] }, [ POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL ] = { .pme_name = "PM_L2SA_RCST_DISP_FAIL_RC_FULL", .pme_code = 0x722e0, .pme_short_desc = "L2 slice A RC store dispatch attempt failed due to all RC full", .pme_long_desc = "A Read/Claim dispatch for a store failed because all RC machines are busy.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL] }, [ POWER5p_PME_PM_MRK_LSU0_FLUSH_ULD ] = { .pme_name = "PM_MRK_LSU0_FLUSH_ULD", .pme_code = 0x810c1, .pme_short_desc = "LSU0 marked unaligned load flushes", .pme_long_desc = "A marked load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LSU0_FLUSH_ULD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LSU0_FLUSH_ULD] }, [ POWER5p_PME_PM_LSU_FLUSH_SRQ_FULL ] = { .pme_name = "PM_LSU_FLUSH_SRQ_FULL", .pme_code = 0x330e0, .pme_short_desc = "Flush caused by SRQ full", .pme_long_desc = "This thread was flushed at dispatch because its Store Request Queue was full. This allows the other thread to have more machine resources for it to make progress while this thread is stalled.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_FLUSH_SRQ_FULL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_FLUSH_SRQ_FULL] }, [ POWER5p_PME_PM_MEM_RQ_DISP_Q16to19 ] = { .pme_name = "PM_MEM_RQ_DISP_Q16to19", .pme_code = 0x727e6, .pme_short_desc = "Memory read queue dispatched to queues 16-19", .pme_long_desc = "A memory operation was dispatched to read queue 16,17,18 or 19. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_RQ_DISP_Q16to19], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_RQ_DISP_Q16to19] }, [ POWER5p_PME_PM_FLUSH_IMBAL ] = { .pme_name = "PM_FLUSH_IMBAL", .pme_code = 0x330e3, .pme_short_desc = "Flush caused by thread GCT imbalance", .pme_long_desc = "This thread has been flushed at dispatch because it is stalled and a GCT imbalance exists. GCT thresholds are set in the TSCR register. This allows the other thread to have more machine resources for it to make progress while this thread is stalled.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FLUSH_IMBAL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FLUSH_IMBAL] }, [ POWER5p_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_minus3or4_CYC", .pme_code = 0x430e1, .pme_short_desc = "Cycles thread priority difference is -3 or -4", .pme_long_desc = "Cycles when this thread's priority is lower than the other thread's priority by 3 or 4.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC] }, [ POWER5p_PME_PM_DATA_FROM_L35_MOD ] = { .pme_name = "PM_DATA_FROM_L35_MOD", .pme_code = 0x2c309e, .pme_short_desc = "Data loaded from L3.5 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L3 of a chip on the same module as this processor is located due to a demand load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DATA_FROM_L35_MOD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DATA_FROM_L35_MOD] }, [ POWER5p_PME_PM_MEM_HI_PRIO_WR_CMPL ] = { .pme_name = "PM_MEM_HI_PRIO_WR_CMPL", .pme_code = 0x726e6, .pme_short_desc = "High priority write completed", .pme_long_desc = "A memory write, which was upgraded to high priority, completed. Writes can be upgraded to high priority to ensure that read traffic does not lock out writes. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_HI_PRIO_WR_CMPL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_HI_PRIO_WR_CMPL] }, [ POWER5p_PME_PM_FPU1_FDIV ] = { .pme_name = "PM_FPU1_FDIV", .pme_code = 0xc4, .pme_short_desc = "FPU1 executed FDIV instruction", .pme_long_desc = "FPU1 has executed a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU1_FDIV], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU1_FDIV] }, [ POWER5p_PME_PM_MEM_RQ_DISP ] = { .pme_name = "PM_MEM_RQ_DISP", .pme_code = 0x701c6, .pme_short_desc = "Memory read queue dispatched", .pme_long_desc = "A memory read was dispatched. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_RQ_DISP], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_RQ_DISP] }, [ POWER5p_PME_PM_FPU0_FRSP_FCONV ] = { .pme_name = "PM_FPU0_FRSP_FCONV", .pme_code = 0x10c1, .pme_short_desc = "FPU0 executed FRSP or FCONV instructions", .pme_long_desc = "FPU0 has executed a frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU0_FRSP_FCONV], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU0_FRSP_FCONV] }, [ POWER5p_PME_PM_LWSYNC_HELD ] = { .pme_name = "PM_LWSYNC_HELD", .pme_code = 0x130e0, .pme_short_desc = "LWSYNC held at dispatch", .pme_long_desc = "Cycles a LWSYNC instruction was held at dispatch. LWSYNC instructions are held at dispatch until all previous loads are done and all previous stores have issued. LWSYNC enters the Store Request Queue and is sent to the storage subsystem but does not wait for a response.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LWSYNC_HELD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LWSYNC_HELD] }, [ POWER5p_PME_PM_FXU_FIN ] = { .pme_name = "PM_FXU_FIN", .pme_code = 0x313088, .pme_short_desc = "FXU produced a result", .pme_long_desc = "The fixed point unit (Unit 0 + Unit 1) finished an instruction. Instructions that finish may not necessary complete.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FXU_FIN], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FXU_FIN] }, [ POWER5p_PME_PM_DSLB_MISS ] = { .pme_name = "PM_DSLB_MISS", .pme_code = 0x800c5, .pme_short_desc = "Data SLB misses", .pme_long_desc = "A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DSLB_MISS], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DSLB_MISS] }, [ POWER5p_PME_PM_DATA_FROM_L275_SHR ] = { .pme_name = "PM_DATA_FROM_L275_SHR", .pme_code = 0x3c3097, .pme_short_desc = "Data loaded from L2.75 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (T) data from the L2 on a different module than this processor is located due to a demand load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DATA_FROM_L275_SHR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DATA_FROM_L275_SHR] }, [ POWER5p_PME_PM_FXLS1_FULL_CYC ] = { .pme_name = "PM_FXLS1_FULL_CYC", .pme_code = 0x110c4, .pme_short_desc = "Cycles FXU1/LS1 queue full", .pme_long_desc = "The issue queue that feeds the Fixed Point unit 1 / Load Store Unit 1 is full. This condition will prevent dispatch groups from being dispatched. This event only indicates that the queue was full, not that dispatch was prevented.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FXLS1_FULL_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FXLS1_FULL_CYC] }, [ POWER5p_PME_PM_THRD_SEL_T0 ] = { .pme_name = "PM_THRD_SEL_T0", .pme_code = 0x410c0, .pme_short_desc = "Decode selected thread 0", .pme_long_desc = "Thread selection picked thread 0 for decode.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_SEL_T0], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_SEL_T0] }, [ POWER5p_PME_PM_PTEG_RELOAD_VALID ] = { .pme_name = "PM_PTEG_RELOAD_VALID", .pme_code = 0x830e4, .pme_short_desc = "PTEG reload valid", .pme_long_desc = "A Page Table Entry was loaded into the TLB.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PTEG_RELOAD_VALID], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PTEG_RELOAD_VALID] }, [ POWER5p_PME_PM_MRK_STCX_FAIL ] = { .pme_name = "PM_MRK_STCX_FAIL", .pme_code = 0x820e6, .pme_short_desc = "Marked STCX failed", .pme_long_desc = "A marked stcx (stwcx or stdcx) failed", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_STCX_FAIL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_STCX_FAIL] }, [ POWER5p_PME_PM_LSU_LMQ_LHR_MERGE ] = { .pme_name = "PM_LSU_LMQ_LHR_MERGE", .pme_code = 0xc70e5, .pme_short_desc = "LMQ LHR merges", .pme_long_desc = "A data cache miss occurred for the same real cache line address as an earlier request already in the Load Miss Queue and was merged into the LMQ entry.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_LMQ_LHR_MERGE], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_LMQ_LHR_MERGE] }, [ POWER5p_PME_PM_2INST_CLB_CYC ] = { .pme_name = "PM_2INST_CLB_CYC", .pme_code = 0x400c2, .pme_short_desc = "Cycles 2 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_2INST_CLB_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_2INST_CLB_CYC] }, [ POWER5p_PME_PM_FAB_PNtoVN_DIRECT ] = { .pme_name = "PM_FAB_PNtoVN_DIRECT", .pme_code = 0x723e7, .pme_short_desc = "PN to VN beat went straight to its destination", .pme_long_desc = "Fabric Data beats that the base chip takes the inbound PN data and passes it through to the outbound VN bus without going into a sidecar. The signal is delivered at FBC speed and the count must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_PNtoVN_DIRECT], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_PNtoVN_DIRECT] }, [ POWER5p_PME_PM_PTEG_FROM_L2MISS ] = { .pme_name = "PM_PTEG_FROM_L2MISS", .pme_code = 0x38309b, .pme_short_desc = "PTEG loaded from L2 miss", .pme_long_desc = "A Page Table Entry was loaded into the TLB but not from the local L2.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PTEG_FROM_L2MISS], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PTEG_FROM_L2MISS] }, [ POWER5p_PME_PM_CMPLU_STALL_LSU ] = { .pme_name = "PM_CMPLU_STALL_LSU", .pme_code = 0x211098, .pme_short_desc = "Completion stall caused by LSU instruction", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a load/store instruction.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_CMPLU_STALL_LSU], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_CMPLU_STALL_LSU] }, [ POWER5p_PME_PM_MRK_DSLB_MISS ] = { .pme_name = "PM_MRK_DSLB_MISS", .pme_code = 0xc50c7, .pme_short_desc = "Marked Data SLB misses", .pme_long_desc = "A Data SLB miss was caused by a marked instruction.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DSLB_MISS], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DSLB_MISS] }, [ POWER5p_PME_PM_LSU_FLUSH_ULD ] = { .pme_name = "PM_LSU_FLUSH_ULD", .pme_code = 0x1c0088, .pme_short_desc = "LRQ unaligned load flushes", .pme_long_desc = "A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1). Combined Unit 0 + 1.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_FLUSH_ULD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_FLUSH_ULD] }, [ POWER5p_PME_PM_PTEG_FROM_LMEM ] = { .pme_name = "PM_PTEG_FROM_LMEM", .pme_code = 0x283087, .pme_short_desc = "PTEG loaded from local memory", .pme_long_desc = "A Page Table Entry was loaded into the TLB from memory attached to the same module this proccessor is located on.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PTEG_FROM_LMEM], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PTEG_FROM_LMEM] }, [ POWER5p_PME_PM_MRK_BRU_FIN ] = { .pme_name = "PM_MRK_BRU_FIN", .pme_code = 0x200005, .pme_short_desc = "Marked instruction BRU processing finished", .pme_long_desc = "The branch unit finished a marked instruction. Instructions that finish may not necessary complete.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_BRU_FIN], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_BRU_FIN] }, [ POWER5p_PME_PM_MEM_WQ_DISP_WRITE ] = { .pme_name = "PM_MEM_WQ_DISP_WRITE", .pme_code = 0x703c6, .pme_short_desc = "Memory write queue dispatched due to write", .pme_long_desc = "A memory write was dispatched to a write queue. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_WQ_DISP_WRITE], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_WQ_DISP_WRITE] }, [ POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L275_MOD_CYC", .pme_code = 0x4c70a3, .pme_short_desc = "Marked load latency from L2.75 modified", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD_CYC] }, [ POWER5p_PME_PM_LSU1_NCLD ] = { .pme_name = "PM_LSU1_NCLD", .pme_code = 0xc50c5, .pme_short_desc = "LSU1 non-cacheable loads", .pme_long_desc = "A non-cacheable load was executed by Unit 0.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU1_NCLD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU1_NCLD] }, [ POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2SA_RCLD_DISP_FAIL_OTHER", .pme_code = 0x731e0, .pme_short_desc = "L2 slice A RC load dispatch attempt failed due to other reasons", .pme_long_desc = "A Read/Claim dispatch for a load failed for some reason other than Full or Collision conditions.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER] }, [ POWER5p_PME_PM_SNOOP_PW_RETRY_WQ_PWQ ] = { .pme_name = "PM_SNOOP_PW_RETRY_WQ_PWQ", .pme_code = 0x717c6, .pme_short_desc = "Snoop partial-write retry due to collision with active write or partial-write queue", .pme_long_desc = "A snoop request for a partial write to memory was retried because it matched the cache line of an active write or partial write. When this happens the snoop request is retried and the active write is changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SNOOP_PW_RETRY_WQ_PWQ], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SNOOP_PW_RETRY_WQ_PWQ] }, [ POWER5p_PME_PM_FPU1_FULL_CYC ] = { .pme_name = "PM_FPU1_FULL_CYC", .pme_code = 0x100c7, .pme_short_desc = "Cycles FPU1 issue queue full", .pme_long_desc = "The issue queue for FPU1 cannot accept any more instructions. Dispatch to this issue queue is stopped", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU1_FULL_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU1_FULL_CYC] }, [ POWER5p_PME_PM_FPR_MAP_FULL_CYC ] = { .pme_name = "PM_FPR_MAP_FULL_CYC", .pme_code = 0x100c1, .pme_short_desc = "Cycles FPR mapper full", .pme_long_desc = "The floating point unit has executed an add, mult, sub, compare, fsel, fneg, fabs, fnabs, fres, or frsqrte kind of instruction. These are single FLOP operations.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPR_MAP_FULL_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPR_MAP_FULL_CYC] }, [ POWER5p_PME_PM_L3SA_ALL_BUSY ] = { .pme_name = "PM_L3SA_ALL_BUSY", .pme_code = 0x721e3, .pme_short_desc = "L3 slice A active for every cycle all CI/CO machines busy", .pme_long_desc = "Cycles All Castin/Castout machines are busy.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SA_ALL_BUSY], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SA_ALL_BUSY] }, [ POWER5p_PME_PM_3INST_CLB_CYC ] = { .pme_name = "PM_3INST_CLB_CYC", .pme_code = 0x400c3, .pme_short_desc = "Cycles 3 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_3INST_CLB_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_3INST_CLB_CYC] }, [ POWER5p_PME_PM_MEM_PWQ_DISP_Q2or3 ] = { .pme_name = "PM_MEM_PWQ_DISP_Q2or3", .pme_code = 0x734e6, .pme_short_desc = "Memory partial-write queue dispatched to Write Queue 2 or 3", .pme_long_desc = "Memory partial-write queue dispatched to Write Queue 2 or 3. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_PWQ_DISP_Q2or3], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_PWQ_DISP_Q2or3] }, [ POWER5p_PME_PM_L2SA_SHR_INV ] = { .pme_name = "PM_L2SA_SHR_INV", .pme_code = 0x710c0, .pme_short_desc = "L2 slice A transition from shared to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A, B, and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_SHR_INV], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_SHR_INV] }, [ POWER5p_PME_PM_THRESH_TIMEO ] = { .pme_name = "PM_THRESH_TIMEO", .pme_code = 0x30000b, .pme_short_desc = "Threshold timeout", .pme_long_desc = "The threshold timer expired", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRESH_TIMEO], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRESH_TIMEO] }, [ POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL ] = { .pme_name = "PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL", .pme_code = 0x713c0, .pme_short_desc = "L2 slice A RC dispatch attempt failed due to all CO busy", .pme_long_desc = "A Read/Claim dispatch was rejected because all Castout machines were busy.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL] }, [ POWER5p_PME_PM_THRD_SEL_OVER_GCT_IMBAL ] = { .pme_name = "PM_THRD_SEL_OVER_GCT_IMBAL", .pme_code = 0x410c4, .pme_short_desc = "Thread selection overrides caused by GCT imbalance", .pme_long_desc = "Thread selection was overridden because of a GCT imbalance.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_SEL_OVER_GCT_IMBAL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_SEL_OVER_GCT_IMBAL] }, [ POWER5p_PME_PM_FPU_FSQRT ] = { .pme_name = "PM_FPU_FSQRT", .pme_code = 0x200090, .pme_short_desc = "FPU executed FSQRT instruction", .pme_long_desc = "The floating point unit has executed a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU_FSQRT], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU_FSQRT] }, [ POWER5p_PME_PM_PMC1_OVERFLOW ] = { .pme_name = "PM_PMC1_OVERFLOW", .pme_code = 0x20000a, .pme_short_desc = "PMC1 Overflow", .pme_long_desc = "Overflows from PMC1 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PMC1_OVERFLOW], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PMC1_OVERFLOW] }, [ POWER5p_PME_PM_MRK_LSU0_FLUSH_LRQ ] = { .pme_name = "PM_MRK_LSU0_FLUSH_LRQ", .pme_code = 0x810c2, .pme_short_desc = "LSU0 marked LRQ flushes", .pme_long_desc = "A marked load was flushed by unit 0 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LSU0_FLUSH_LRQ], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LSU0_FLUSH_LRQ] }, [ POWER5p_PME_PM_L3SC_SNOOP_RETRY ] = { .pme_name = "PM_L3SC_SNOOP_RETRY", .pme_code = 0x731e5, .pme_short_desc = "L3 slice C snoop retries", .pme_long_desc = "Number of times an L3 retried a snoop because it got two in at the same time (one on snp_a, one on snp_b)", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SC_SNOOP_RETRY], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SC_SNOOP_RETRY] }, [ POWER5p_PME_PM_DATA_TABLEWALK_CYC ] = { .pme_name = "PM_DATA_TABLEWALK_CYC", .pme_code = 0x800c7, .pme_short_desc = "Cycles doing data tablewalks", .pme_long_desc = "Cycles a translation tablewalk is active. While a tablewalk is active any request attempting to access the TLB will be rejected and retried.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DATA_TABLEWALK_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DATA_TABLEWALK_CYC] }, [ POWER5p_PME_PM_THRD_PRIO_6_CYC ] = { .pme_name = "PM_THRD_PRIO_6_CYC", .pme_code = 0x420e5, .pme_short_desc = "Cycles thread running at priority level 6", .pme_long_desc = "Cycles this thread was running at priority level 6.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_PRIO_6_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_PRIO_6_CYC] }, [ POWER5p_PME_PM_FPU_FEST ] = { .pme_name = "PM_FPU_FEST", .pme_code = 0x1010a8, .pme_short_desc = "FPU executed FEST instruction", .pme_long_desc = "The floating point unit has executed an estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. Combined Unit 0 + Unit 1.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU_FEST], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU_FEST] }, [ POWER5p_PME_PM_FAB_M1toP1_SIDECAR_EMPTY ] = { .pme_name = "PM_FAB_M1toP1_SIDECAR_EMPTY", .pme_code = 0x702c7, .pme_short_desc = "M1 to P1 sidecar empty", .pme_long_desc = "Fabric cycles when the Minus-1 hip/hop sidecars (sidecars for chip to chip data transfer) are empty. The signal is delivered at FBC speed and the count must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_M1toP1_SIDECAR_EMPTY], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_M1toP1_SIDECAR_EMPTY] }, [ POWER5p_PME_PM_MRK_DATA_FROM_RMEM ] = { .pme_name = "PM_MRK_DATA_FROM_RMEM", .pme_code = 0x1c70a1, .pme_short_desc = "Marked data loaded from remote memory", .pme_long_desc = "The processor's Data Cache was reloaded due to a marked load from memory attached to a different module than this proccessor is located on.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_RMEM], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_RMEM] }, [ POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L35_MOD_CYC", .pme_code = 0x4c70a6, .pme_short_desc = "Marked load latency from L3.5 modified", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD_CYC] }, [ POWER5p_PME_PM_MEM_PWQ_DISP ] = { .pme_name = "PM_MEM_PWQ_DISP", .pme_code = 0x704c6, .pme_short_desc = "Memory partial-write queue dispatched", .pme_long_desc = "Number of Partial Writes dispatched. The MC provides resources to gather partial cacheline writes (Partial line DMA writes & CI-stores) to up to four different cachelines at a time. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_PWQ_DISP], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_PWQ_DISP] }, [ POWER5p_PME_PM_FAB_P1toM1_SIDECAR_EMPTY ] = { .pme_name = "PM_FAB_P1toM1_SIDECAR_EMPTY", .pme_code = 0x701c7, .pme_short_desc = "P1 to M1 sidecar empty", .pme_long_desc = "Fabric cycles when the Plus-1 hip/hop sidecars (sidecars for chip to chip data transfer) are empty. The signal is delivered at FBC speed and the count must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_P1toM1_SIDECAR_EMPTY], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_P1toM1_SIDECAR_EMPTY] }, [ POWER5p_PME_PM_LD_MISS_L1_LSU0 ] = { .pme_name = "PM_LD_MISS_L1_LSU0", .pme_code = 0xc10c2, .pme_short_desc = "LSU0 L1 D cache load misses", .pme_long_desc = "Load references that miss the Level 1 Data cache, by unit 0.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LD_MISS_L1_LSU0], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LD_MISS_L1_LSU0] }, [ POWER5p_PME_PM_SNOOP_PARTIAL_RTRY_QFULL ] = { .pme_name = "PM_SNOOP_PARTIAL_RTRY_QFULL", .pme_code = 0x730e6, .pme_short_desc = "Snoop partial write retry due to partial-write queues full", .pme_long_desc = "A snoop request for a partial write to memory was retried because the write queues that handle partial writes were full. When this happens the active writes are changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SNOOP_PARTIAL_RTRY_QFULL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SNOOP_PARTIAL_RTRY_QFULL] }, [ POWER5p_PME_PM_FPU1_STALL3 ] = { .pme_name = "PM_FPU1_STALL3", .pme_code = 0x20e5, .pme_short_desc = "FPU1 stalled in pipe3", .pme_long_desc = "FPU1 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always).", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU1_STALL3], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU1_STALL3] }, [ POWER5p_PME_PM_GCT_USAGE_80to99_CYC ] = { .pme_name = "PM_GCT_USAGE_80to99_CYC", .pme_code = 0x30001f, .pme_short_desc = "Cycles GCT 80-99% full", .pme_long_desc = "Cycles when the Global Completion Table has between 80% and 99% of its slots used. The GCT has 20 entries shared between threads", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GCT_USAGE_80to99_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GCT_USAGE_80to99_CYC] }, [ POWER5p_PME_PM_WORK_HELD ] = { .pme_name = "PM_WORK_HELD", .pme_code = 0x40000c, .pme_short_desc = "Work held", .pme_long_desc = "RAS Unit has signaled completion to stop and there are groups waiting to complete", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_WORK_HELD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_WORK_HELD] }, [ POWER5p_PME_PM_INST_CMPL ] = { .pme_name = "PM_INST_CMPL", .pme_code = 0x100009, .pme_short_desc = "Instructions completed", .pme_long_desc = "Number of PowerPC instructions that completed.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_CMPL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_CMPL] }, [ POWER5p_PME_PM_LSU1_FLUSH_UST ] = { .pme_name = "PM_LSU1_FLUSH_UST", .pme_code = 0xc00c5, .pme_short_desc = "LSU1 unaligned store flushes", .pme_long_desc = "A store was flushed from unit 1 because it was unaligned (crossed a 4K boundary)", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU1_FLUSH_UST], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU1_FLUSH_UST] }, [ POWER5p_PME_PM_FXU_IDLE ] = { .pme_name = "PM_FXU_IDLE", .pme_code = 0x100012, .pme_short_desc = "FXU idle", .pme_long_desc = "FXU0 and FXU1 are both idle.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FXU_IDLE], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FXU_IDLE] }, [ POWER5p_PME_PM_LSU0_FLUSH_ULD ] = { .pme_name = "PM_LSU0_FLUSH_ULD", .pme_code = 0xc00c0, .pme_short_desc = "LSU0 unaligned load flushes", .pme_long_desc = "A load was flushed from unit 0 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1)", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU0_FLUSH_ULD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU0_FLUSH_ULD] }, [ POWER5p_PME_PM_LSU1_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU1_REJECT_LMQ_FULL", .pme_code = 0xc40c5, .pme_short_desc = "LSU1 reject due to LMQ full or missed data coming", .pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU1_REJECT_LMQ_FULL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU1_REJECT_LMQ_FULL] }, [ POWER5p_PME_PM_GRP_DISP_REJECT ] = { .pme_name = "PM_GRP_DISP_REJECT", .pme_code = 0x120e4, .pme_short_desc = "Group dispatch rejected", .pme_long_desc = "A group that previously attempted dispatch was rejected.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GRP_DISP_REJECT], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GRP_DISP_REJECT] }, [ POWER5p_PME_PM_PTEG_FROM_L25_SHR ] = { .pme_name = "PM_PTEG_FROM_L25_SHR", .pme_code = 0x183097, .pme_short_desc = "PTEG loaded from L2.5 shared", .pme_long_desc = "A Page Table Entry was loaded into the TLB with shared (T or SL) data from the L2 of a chip on the same module as this processor is located due to a demand load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PTEG_FROM_L25_SHR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PTEG_FROM_L25_SHR] }, [ POWER5p_PME_PM_L2SA_MOD_INV ] = { .pme_name = "PM_L2SA_MOD_INV", .pme_code = 0x730e0, .pme_short_desc = "L2 slice A transition from modified to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_MOD_INV], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_MOD_INV] }, [ POWER5p_PME_PM_FAB_CMD_RETRIED ] = { .pme_name = "PM_FAB_CMD_RETRIED", .pme_code = 0x710c7, .pme_short_desc = "Fabric command retried", .pme_long_desc = "Incremented when a command issued by a chip on its SnoopA address bus is retried for any reason. The overwhelming majority of retries are due to running out of memory controller queues but retries can also be caused by trying to reference addresses that are in a transient cache state -- e.g. a line is transient after issuing a DCLAIM instruction to a shared line but before the associated store completes. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_CMD_RETRIED], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_CMD_RETRIED] }, [ POWER5p_PME_PM_L3SA_SHR_INV ] = { .pme_name = "PM_L3SA_SHR_INV", .pme_code = 0x710c3, .pme_short_desc = "L3 slice A transition from shared to invalid", .pme_long_desc = "L3 snooper detects someone doing a store to a line that is Sx in this L3(i.e. invalidate hit SX and dispatched).", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SA_SHR_INV], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SA_SHR_INV] }, [ POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL ] = { .pme_name = "PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL", .pme_code = 0x713c1, .pme_short_desc = "L2 slice B RC dispatch attempt failed due to all CO busy", .pme_long_desc = "A Read/Claim dispatch was rejected because all Castout machines were busy.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL] }, [ POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2SA_RCST_DISP_FAIL_ADDR", .pme_code = 0x712c0, .pme_short_desc = "L2 slice A RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = "A Read/Claim dispatch for a store failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_ADDR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_ADDR] }, [ POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_RC_FULL ] = { .pme_name = "PM_L2SA_RCLD_DISP_FAIL_RC_FULL", .pme_code = 0x721e0, .pme_short_desc = "L2 slice A RC load dispatch attempt failed due to all RC full", .pme_long_desc = "A Read/Claim dispatch for a load failed because all RC machines are busy.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_RC_FULL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_RC_FULL] }, [ POWER5p_PME_PM_PTEG_FROM_L375_MOD ] = { .pme_name = "PM_PTEG_FROM_L375_MOD", .pme_code = 0x1830a7, .pme_short_desc = "PTEG loaded from L3.75 modified", .pme_long_desc = "A Page Table Entry was loaded into the TLB with modified (M) data from the L3 of a chip on a different module than this processor is located, due to a demand load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PTEG_FROM_L375_MOD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PTEG_FROM_L375_MOD] }, [ POWER5p_PME_PM_MRK_LSU1_FLUSH_UST ] = { .pme_name = "PM_MRK_LSU1_FLUSH_UST", .pme_code = 0x810c5, .pme_short_desc = "LSU1 marked unaligned store flushes", .pme_long_desc = "A marked store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LSU1_FLUSH_UST], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LSU1_FLUSH_UST] }, [ POWER5p_PME_PM_BR_ISSUED ] = { .pme_name = "PM_BR_ISSUED", .pme_code = 0x230e4, .pme_short_desc = "Branches issued", .pme_long_desc = "A branch instruction was issued to the branch unit. A branch that was incorrectly predicted may issue and execute multiple times.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_BR_ISSUED], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_BR_ISSUED] }, [ POWER5p_PME_PM_MRK_GRP_BR_REDIR ] = { .pme_name = "PM_MRK_GRP_BR_REDIR", .pme_code = 0x212091, .pme_short_desc = "Group experienced marked branch redirect", .pme_long_desc = "A group containing a marked (sampled) instruction experienced a branch redirect.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_GRP_BR_REDIR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_GRP_BR_REDIR] }, [ POWER5p_PME_PM_EE_OFF ] = { .pme_name = "PM_EE_OFF", .pme_code = 0x130e3, .pme_short_desc = "Cycles MSR(EE) bit off", .pme_long_desc = "Cycles MSR(EE) bit was off indicating that interrupts due to external exceptions were masked.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_EE_OFF], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_EE_OFF] }, [ POWER5p_PME_PM_IERAT_XLATE_WR_LP ] = { .pme_name = "PM_IERAT_XLATE_WR_LP", .pme_code = 0x210c6, .pme_short_desc = "Large page translation written to ierat", .pme_long_desc = "An entry was written into the IERAT as a result of an IERAT miss. This event can be used to count IERAT misses. An ERAT miss that are later ignored will not be counted unless the ERAT is written before the instruction stream is changed.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_IERAT_XLATE_WR_LP], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_IERAT_XLATE_WR_LP] }, [ POWER5p_PME_PM_DTLB_REF_64K ] = { .pme_name = "PM_DTLB_REF_64K", .pme_code = 0x2c2086, .pme_short_desc = "Data TLB reference for 64K page", .pme_long_desc = "Data TLB references for 64KB pages. Includes hits + misses.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DTLB_REF_64K], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DTLB_REF_64K] }, [ POWER5p_PME_PM_MEM_RQ_DISP_Q4to7 ] = { .pme_name = "PM_MEM_RQ_DISP_Q4to7", .pme_code = 0x712c6, .pme_short_desc = "Memory read queue dispatched to queues 4-7", .pme_long_desc = "A memory operation was dispatched to read queue 4,5,6 or 7. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_RQ_DISP_Q4to7], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_RQ_DISP_Q4to7] }, [ POWER5p_PME_PM_MEM_FAST_PATH_RD_DISP ] = { .pme_name = "PM_MEM_FAST_PATH_RD_DISP", .pme_code = 0x731e6, .pme_short_desc = "Fast path memory read dispatched", .pme_long_desc = "Fast path memory read dispatched", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_FAST_PATH_RD_DISP], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_FAST_PATH_RD_DISP] }, [ POWER5p_PME_PM_INST_FROM_L3 ] = { .pme_name = "PM_INST_FROM_L3", .pme_code = 0x12208d, .pme_short_desc = "Instruction fetched from L3", .pme_long_desc = "An instruction fetch group was fetched from the local L3. Fetch groups can contain up to 8 instructions", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_L3], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_L3] }, [ POWER5p_PME_PM_ITLB_MISS ] = { .pme_name = "PM_ITLB_MISS", .pme_code = 0x800c0, .pme_short_desc = "Instruction TLB misses", .pme_long_desc = "A TLB miss for an Instruction Fetch has occurred", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_ITLB_MISS], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_ITLB_MISS] }, [ POWER5p_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { .pme_name = "PM_FXU1_BUSY_FXU0_IDLE", .pme_code = 0x400012, .pme_short_desc = "FXU1 busy FXU0 idle", .pme_long_desc = "FXU0 was idle while FXU1 was busy.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FXU1_BUSY_FXU0_IDLE], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FXU1_BUSY_FXU0_IDLE] }, [ POWER5p_PME_PM_DTLB_REF_4K ] = { .pme_name = "PM_DTLB_REF_4K", .pme_code = 0x1c2086, .pme_short_desc = "Data TLB reference for 4K page", .pme_long_desc = "Data TLB references for 4KB pages. Includes hits + misses.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DTLB_REF_4K], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DTLB_REF_4K] }, [ POWER5p_PME_PM_FXLS_FULL_CYC ] = { .pme_name = "PM_FXLS_FULL_CYC", .pme_code = 0x1110a8, .pme_short_desc = "Cycles FXLS queue is full", .pme_long_desc = "Cycles when the issue queues for one or both FXU/LSU units is full. Use with caution since this is the sum of cycles when Unit 0 was full plus Unit 1 full. It does not indicate when both units were full.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FXLS_FULL_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FXLS_FULL_CYC] }, [ POWER5p_PME_PM_GRP_DISP_VALID ] = { .pme_name = "PM_GRP_DISP_VALID", .pme_code = 0x120e3, .pme_short_desc = "Group dispatch valid", .pme_long_desc = "A group is available for dispatch. This does not mean it was successfully dispatched.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GRP_DISP_VALID], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GRP_DISP_VALID] }, [ POWER5p_PME_PM_LSU_FLUSH_UST ] = { .pme_name = "PM_LSU_FLUSH_UST", .pme_code = 0x2c0088, .pme_short_desc = "SRQ unaligned store flushes", .pme_long_desc = "A store was flushed because it was unaligned (crossed a 4K boundary). Combined Unit 0 + 1.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_FLUSH_UST], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_FLUSH_UST] }, [ POWER5p_PME_PM_FXU1_FIN ] = { .pme_name = "PM_FXU1_FIN", .pme_code = 0x130e6, .pme_short_desc = "FXU1 produced a result", .pme_long_desc = "The Fixed Point unit 1 finished an instruction and produced a result. Instructions that finish may not necessary complete.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FXU1_FIN], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FXU1_FIN] }, [ POWER5p_PME_PM_THRD_PRIO_4_CYC ] = { .pme_name = "PM_THRD_PRIO_4_CYC", .pme_code = 0x420e3, .pme_short_desc = "Cycles thread running at priority level 4", .pme_long_desc = "Cycles this thread was running at priority level 4.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_PRIO_4_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_PRIO_4_CYC] }, [ POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L35_MOD", .pme_code = 0x2c709e, .pme_short_desc = "Marked data loaded from L3.5 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L3 of a chip on the same module as this processor is located due to a marked load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L35_MOD] }, [ POWER5p_PME_PM_4INST_CLB_CYC ] = { .pme_name = "PM_4INST_CLB_CYC", .pme_code = 0x400c4, .pme_short_desc = "Cycles 4 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_4INST_CLB_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_4INST_CLB_CYC] }, [ POWER5p_PME_PM_MRK_DTLB_REF_16M ] = { .pme_name = "PM_MRK_DTLB_REF_16M", .pme_code = 0x3c6086, .pme_short_desc = "Marked Data TLB reference for 16M page", .pme_long_desc = "Data TLB references by a marked instruction for 16MB pages.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DTLB_REF_16M], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DTLB_REF_16M] }, [ POWER5p_PME_PM_INST_FROM_L375_MOD ] = { .pme_name = "PM_INST_FROM_L375_MOD", .pme_code = 0x42209d, .pme_short_desc = "Instruction fetched from L3.75 modified", .pme_long_desc = "An instruction fetch group was fetched with modified (M) data from the L3 of a chip on a different module than this processor is located. Fetch groups can contain up to 8 instructions", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_L375_MOD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_L375_MOD] }, [ POWER5p_PME_PM_GRP_CMPL ] = { .pme_name = "PM_GRP_CMPL", .pme_code = 0x300013, .pme_short_desc = "Group completed", .pme_long_desc = "A group completed. Microcoded instructions that span multiple groups will generate this event once per group.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GRP_CMPL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GRP_CMPL] }, [ POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2SC_RCST_DISP_FAIL_ADDR", .pme_code = 0x712c2, .pme_short_desc = "L2 slice C RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = "A Read/Claim dispatch for a store failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_ADDR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_ADDR] }, [ POWER5p_PME_PM_FPU1_1FLOP ] = { .pme_name = "PM_FPU1_1FLOP", .pme_code = 0xc7, .pme_short_desc = "FPU1 executed add", .pme_long_desc = " mult", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU1_1FLOP], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU1_1FLOP] }, [ POWER5p_PME_PM_FPU_FRSP_FCONV ] = { .pme_name = "PM_FPU_FRSP_FCONV", .pme_code = 0x2010a8, .pme_short_desc = "FPU executed FRSP or FCONV instructions", .pme_long_desc = "The floating point unit has executed a frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU_FRSP_FCONV], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU_FRSP_FCONV] }, [ POWER5p_PME_PM_L3SC_REF ] = { .pme_name = "PM_L3SC_REF", .pme_code = 0x701c5, .pme_short_desc = "L3 slice C references", .pme_long_desc = "Number of attempts made by this chip cores to find data in the L3. Reported per L3 slice.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SC_REF], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SC_REF] }, [ POWER5p_PME_PM_5INST_CLB_CYC ] = { .pme_name = "PM_5INST_CLB_CYC", .pme_code = 0x400c5, .pme_short_desc = "Cycles 5 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_5INST_CLB_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_5INST_CLB_CYC] }, [ POWER5p_PME_PM_THRD_L2MISS_BOTH_CYC ] = { .pme_name = "PM_THRD_L2MISS_BOTH_CYC", .pme_code = 0x410c7, .pme_short_desc = "Cycles both threads in L2 misses", .pme_long_desc = "Cycles that both threads have L2 miss pending. If only one thread has a L2 miss pending the other thread is given priority at decode. If both threads have L2 miss pending decode priority is determined by the number of GCT entries used.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_L2MISS_BOTH_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_L2MISS_BOTH_CYC] }, [ POWER5p_PME_PM_MEM_PW_GATH ] = { .pme_name = "PM_MEM_PW_GATH", .pme_code = 0x714c6, .pme_short_desc = "Memory partial-write gathered", .pme_long_desc = "Two or more partial-writes have been merged into a single memory write. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_PW_GATH], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_PW_GATH] }, [ POWER5p_PME_PM_DTLB_REF_16G ] = { .pme_name = "PM_DTLB_REF_16G", .pme_code = 0x4c2086, .pme_short_desc = "Data TLB reference for 16G page", .pme_long_desc = "Data TLB references for 16GB pages. Includes hits + misses.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DTLB_REF_16G], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DTLB_REF_16G] }, [ POWER5p_PME_PM_FAB_DCLAIM_ISSUED ] = { .pme_name = "PM_FAB_DCLAIM_ISSUED", .pme_code = 0x720e7, .pme_short_desc = "dclaim issued", .pme_long_desc = "A DCLAIM command was issued. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_DCLAIM_ISSUED], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_DCLAIM_ISSUED] }, [ POWER5p_PME_PM_FAB_PNtoNN_SIDECAR ] = { .pme_name = "PM_FAB_PNtoNN_SIDECAR", .pme_code = 0x713c7, .pme_short_desc = "PN to NN beat went to sidecar first", .pme_long_desc = "Fabric Data beats that the base chip takes the inbound PN data and forwards it on to the outbound NN data bus after going into a sidecar first. The signal is delivered at FBC speed and the count must be scaled.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_PNtoNN_SIDECAR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_PNtoNN_SIDECAR] }, [ POWER5p_PME_PM_GRP_IC_MISS ] = { .pme_name = "PM_GRP_IC_MISS", .pme_code = 0x120e7, .pme_short_desc = "Group experienced I cache miss", .pme_long_desc = "Number of groups, counted at dispatch, that have encountered an icache miss redirect. Every group constructed from a fetch group that missed the instruction cache will count.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GRP_IC_MISS], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GRP_IC_MISS] }, [ POWER5p_PME_PM_INST_FROM_L35_SHR ] = { .pme_name = "PM_INST_FROM_L35_SHR", .pme_code = 0x12209d, .pme_short_desc = "Instruction fetched from L3.5 shared", .pme_long_desc = "An instruction fetch group was fetched with shared (S) data from the L3 of a chip on the same module as this processor is located. Fetch groups can contain up to 8 instructions", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_L35_SHR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_L35_SHR] }, [ POWER5p_PME_PM_LSU_LMQ_FULL_CYC ] = { .pme_name = "PM_LSU_LMQ_FULL_CYC", .pme_code = 0xc30e7, .pme_short_desc = "Cycles LMQ full", .pme_long_desc = "The Load Miss Queue was full.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_LMQ_FULL_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_LMQ_FULL_CYC] }, [ POWER5p_PME_PM_MRK_DATA_FROM_L2_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L2_CYC", .pme_code = 0x2c70a0, .pme_short_desc = "Marked load latency from L2", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L2_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L2_CYC] }, [ POWER5p_PME_PM_LSU_SRQ_SYNC_CYC ] = { .pme_name = "PM_LSU_SRQ_SYNC_CYC", .pme_code = 0x830e5, .pme_short_desc = "SRQ sync duration", .pme_long_desc = "Cycles that a sync instruction is active in the Store Request Queue.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_SRQ_SYNC_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_SRQ_SYNC_CYC] }, [ POWER5p_PME_PM_LSU0_BUSY_REJECT ] = { .pme_name = "PM_LSU0_BUSY_REJECT", .pme_code = 0xc20e1, .pme_short_desc = "LSU0 busy due to reject", .pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU0_BUSY_REJECT], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU0_BUSY_REJECT] }, [ POWER5p_PME_PM_LSU_REJECT_ERAT_MISS ] = { .pme_name = "PM_LSU_REJECT_ERAT_MISS", .pme_code = 0x1c4090, .pme_short_desc = "LSU reject due to ERAT miss", .pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions due to an ERAT miss. Combined unit 0 + 1. Requests that miss the Derat are rejected and retried until the request hits in the Erat.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_REJECT_ERAT_MISS], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_REJECT_ERAT_MISS] }, [ POWER5p_PME_PM_MRK_DATA_FROM_RMEM_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_RMEM_CYC", .pme_code = 0x4c70a1, .pme_short_desc = "Marked load latency from remote memory", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_RMEM_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_RMEM_CYC] }, [ POWER5p_PME_PM_DATA_FROM_L375_SHR ] = { .pme_name = "PM_DATA_FROM_L375_SHR", .pme_code = 0x3c309e, .pme_short_desc = "Data loaded from L3.75 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (S) data from the L3 of a chip on a different module than this processor is located due to a demand load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DATA_FROM_L375_SHR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DATA_FROM_L375_SHR] }, [ POWER5p_PME_PM_PTEG_FROM_L25_MOD ] = { .pme_name = "PM_PTEG_FROM_L25_MOD", .pme_code = 0x283097, .pme_short_desc = "PTEG loaded from L2.5 modified", .pme_long_desc = "A Page Table Entry was loaded into the TLB with modified (M) data from the L2 of a chip on the same module as this processor is located due to a demand load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PTEG_FROM_L25_MOD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PTEG_FROM_L25_MOD] }, [ POWER5p_PME_PM_FPU0_FMOV_FEST ] = { .pme_name = "PM_FPU0_FMOV_FEST", .pme_code = 0x10c0, .pme_short_desc = "FPU0 executed FMOV or FEST instructions", .pme_long_desc = "FPU0 has executed a move kind of instruction or one of the estimate instructions. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU0_FMOV_FEST], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU0_FMOV_FEST] }, [ POWER5p_PME_PM_THRD_PRIO_7_CYC ] = { .pme_name = "PM_THRD_PRIO_7_CYC", .pme_code = 0x420e6, .pme_short_desc = "Cycles thread running at priority level 7", .pme_long_desc = "Cycles this thread was running at priority level 7.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_PRIO_7_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_PRIO_7_CYC] }, [ POWER5p_PME_PM_LSU1_FLUSH_SRQ ] = { .pme_name = "PM_LSU1_FLUSH_SRQ", .pme_code = 0xc00c7, .pme_short_desc = "LSU1 SRQ lhs flushes", .pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU1_FLUSH_SRQ], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU1_FLUSH_SRQ] }, [ POWER5p_PME_PM_LD_REF_L1_LSU0 ] = { .pme_name = "PM_LD_REF_L1_LSU0", .pme_code = 0xc10c0, .pme_short_desc = "LSU0 L1 D cache load references", .pme_long_desc = "Load references to Level 1 Data Cache, by unit 0.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LD_REF_L1_LSU0], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LD_REF_L1_LSU0] }, [ POWER5p_PME_PM_L2SC_RCST_DISP ] = { .pme_name = "PM_L2SC_RCST_DISP", .pme_code = 0x702c2, .pme_short_desc = "L2 slice C RC store dispatch attempt", .pme_long_desc = "A Read/Claim dispatch for a Store was attempted.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_RCST_DISP], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_RCST_DISP] }, [ POWER5p_PME_PM_CMPLU_STALL_DIV ] = { .pme_name = "PM_CMPLU_STALL_DIV", .pme_code = 0x411099, .pme_short_desc = "Completion stall caused by DIV instruction", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point divide instruction. This is a subset of PM_CMPLU_STALL_FXU.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_CMPLU_STALL_DIV], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_CMPLU_STALL_DIV] }, [ POWER5p_PME_PM_MEM_RQ_DISP_Q12to15 ] = { .pme_name = "PM_MEM_RQ_DISP_Q12to15", .pme_code = 0x732e6, .pme_short_desc = "Memory read queue dispatched to queues 12-15", .pme_long_desc = "A memory operation was dispatched to read queue 12,13,14 or 15. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_RQ_DISP_Q12to15], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_RQ_DISP_Q12to15] }, [ POWER5p_PME_PM_INST_FROM_L375_SHR ] = { .pme_name = "PM_INST_FROM_L375_SHR", .pme_code = 0x32209d, .pme_short_desc = "Instruction fetched from L3.75 shared", .pme_long_desc = "An instruction fetch group was fetched with shared (S) data from the L3 of a chip on a different module than this processor is located. Fetch groups can contain up to 8 instructions", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_L375_SHR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_L375_SHR] }, [ POWER5p_PME_PM_ST_REF_L1 ] = { .pme_name = "PM_ST_REF_L1", .pme_code = 0x2c10a8, .pme_short_desc = "L1 D cache store references", .pme_long_desc = "Store references to the Data Cache. Combined Unit 0 + 1.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_ST_REF_L1], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_ST_REF_L1] }, [ POWER5p_PME_PM_L3SB_ALL_BUSY ] = { .pme_name = "PM_L3SB_ALL_BUSY", .pme_code = 0x721e4, .pme_short_desc = "L3 slice B active for every cycle all CI/CO machines busy", .pme_long_desc = "Cycles All Castin/Castout machines are busy.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SB_ALL_BUSY], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SB_ALL_BUSY] }, [ POWER5p_PME_PM_FAB_P1toVNorNN_SIDECAR_EMPTY ] = { .pme_name = "PM_FAB_P1toVNorNN_SIDECAR_EMPTY", .pme_code = 0x711c7, .pme_short_desc = "P1 to VN/NN sidecar empty", .pme_long_desc = "Fabric cycles when the Plus-1 jump sidecar (sidecars for mcm to mcm data transfer) is empty. The signal is delivered at FBC speed and the count must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_P1toVNorNN_SIDECAR_EMPTY], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_P1toVNorNN_SIDECAR_EMPTY] }, [ POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L275_SHR_CYC", .pme_code = 0x2c70a3, .pme_short_desc = "Marked load latency from L2.75 shared", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L275_SHR_CYC] }, [ POWER5p_PME_PM_FAB_HOLDtoNN_EMPTY ] = { .pme_name = "PM_FAB_HOLDtoNN_EMPTY", .pme_code = 0x722e7, .pme_short_desc = "Hold buffer to NN empty", .pme_long_desc = "Fabric cyles when the Next Node out hold-buffers are emtpy. The signal is delivered at FBC speed and the count must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_HOLDtoNN_EMPTY], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_HOLDtoNN_EMPTY] }, [ POWER5p_PME_PM_DATA_FROM_LMEM ] = { .pme_name = "PM_DATA_FROM_LMEM", .pme_code = 0x2c3087, .pme_short_desc = "Data loaded from local memory", .pme_long_desc = "The processor's Data Cache was reloaded from memory attached to the same module this proccessor is located on.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DATA_FROM_LMEM], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DATA_FROM_LMEM] }, [ POWER5p_PME_PM_RUN_CYC ] = { .pme_name = "PM_RUN_CYC", .pme_code = 0x100005, .pme_short_desc = "Run cycles", .pme_long_desc = "Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_RUN_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_RUN_CYC] }, [ POWER5p_PME_PM_PTEG_FROM_RMEM ] = { .pme_name = "PM_PTEG_FROM_RMEM", .pme_code = 0x1830a1, .pme_short_desc = "PTEG loaded from remote memory", .pme_long_desc = "A Page Table Entry was loaded into the TLB from memory attached to a different module than this proccessor is located on.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PTEG_FROM_RMEM], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PTEG_FROM_RMEM] }, [ POWER5p_PME_PM_L2SC_RCLD_DISP ] = { .pme_name = "PM_L2SC_RCLD_DISP", .pme_code = 0x701c2, .pme_short_desc = "L2 slice C RC load dispatch attempt", .pme_long_desc = "A Read/Claim dispatch for a Load was attempted", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_RCLD_DISP], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_RCLD_DISP] }, [ POWER5p_PME_PM_LSU_LRQ_S0_VALID ] = { .pme_name = "PM_LSU_LRQ_S0_VALID", .pme_code = 0xc60e6, .pme_short_desc = "LRQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the LRQ is split between the two threads (16 entries each).", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_LRQ_S0_VALID], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_LRQ_S0_VALID] }, [ POWER5p_PME_PM_LSU0_LDF ] = { .pme_name = "PM_LSU0_LDF", .pme_code = 0xc50c0, .pme_short_desc = "LSU0 executed Floating Point load instruction", .pme_long_desc = "A floating point load was executed by LSU0", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU0_LDF], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU0_LDF] }, [ POWER5p_PME_PM_PMC3_OVERFLOW ] = { .pme_name = "PM_PMC3_OVERFLOW", .pme_code = 0x40000a, .pme_short_desc = "PMC3 Overflow", .pme_long_desc = "Overflows from PMC3 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PMC3_OVERFLOW], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PMC3_OVERFLOW] }, [ POWER5p_PME_PM_MRK_IMR_RELOAD ] = { .pme_name = "PM_MRK_IMR_RELOAD", .pme_code = 0x820e2, .pme_short_desc = "Marked IMR reloaded", .pme_long_desc = "A DL1 reload occurred due to marked load", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_IMR_RELOAD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_IMR_RELOAD] }, [ POWER5p_PME_PM_MRK_GRP_TIMEO ] = { .pme_name = "PM_MRK_GRP_TIMEO", .pme_code = 0x40000b, .pme_short_desc = "Marked group completion timeout", .pme_long_desc = "The sampling timeout expired indicating that the previously sampled instruction is no longer in the processor", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_GRP_TIMEO], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_GRP_TIMEO] }, [ POWER5p_PME_PM_ST_MISS_L1 ] = { .pme_name = "PM_ST_MISS_L1", .pme_code = 0xc10c3, .pme_short_desc = "L1 D cache store misses", .pme_long_desc = "A store missed the dcache. Combined Unit 0 + 1.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_ST_MISS_L1], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_ST_MISS_L1] }, [ POWER5p_PME_PM_STOP_COMPLETION ] = { .pme_name = "PM_STOP_COMPLETION", .pme_code = 0x300018, .pme_short_desc = "Completion stopped", .pme_long_desc = "RAS Unit has signaled completion to stop", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_STOP_COMPLETION], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_STOP_COMPLETION] }, [ POWER5p_PME_PM_LSU_BUSY_REJECT ] = { .pme_name = "PM_LSU_BUSY_REJECT", .pme_code = 0x2c2088, .pme_short_desc = "LSU busy due to reject", .pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions. Combined unit 0 + 1.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_BUSY_REJECT], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_BUSY_REJECT] }, [ POWER5p_PME_PM_ISLB_MISS ] = { .pme_name = "PM_ISLB_MISS", .pme_code = 0x800c1, .pme_short_desc = "Instruction SLB misses", .pme_long_desc = "A SLB miss for an instruction fetch as occurred", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_ISLB_MISS], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_ISLB_MISS] }, [ POWER5p_PME_PM_CYC ] = { .pme_name = "PM_CYC", .pme_code = 0xf, .pme_short_desc = "Processor cycles", .pme_long_desc = "Processor cycles", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_CYC] }, [ POWER5p_PME_PM_THRD_ONE_RUN_CYC ] = { .pme_name = "PM_THRD_ONE_RUN_CYC", .pme_code = 0x10000b, .pme_short_desc = "One of the threads in run cycles", .pme_long_desc = "At least one thread has set its run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. This event does not respect FCWAIT.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_ONE_RUN_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_ONE_RUN_CYC] }, [ POWER5p_PME_PM_GRP_BR_REDIR_NONSPEC ] = { .pme_name = "PM_GRP_BR_REDIR_NONSPEC", .pme_code = 0x112091, .pme_short_desc = "Group experienced non-speculative branch redirect", .pme_long_desc = "Number of groups, counted at completion, that have encountered a branch redirect.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GRP_BR_REDIR_NONSPEC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GRP_BR_REDIR_NONSPEC] }, [ POWER5p_PME_PM_LSU1_SRQ_STFWD ] = { .pme_name = "PM_LSU1_SRQ_STFWD", .pme_code = 0xc60e5, .pme_short_desc = "LSU1 SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load on unit 1. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU1_SRQ_STFWD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU1_SRQ_STFWD] }, [ POWER5p_PME_PM_L3SC_MOD_INV ] = { .pme_name = "PM_L3SC_MOD_INV", .pme_code = 0x730e5, .pme_short_desc = "L3 slice C transition from modified to invalid", .pme_long_desc = "L3 snooper detects someone doing a store to a line that is truly M in this L3 (i.e. L3 going M=>I) Mu|Me are not included since they are formed due to a previous read op Tx is not included since it is considered shared at this point.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SC_MOD_INV], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SC_MOD_INV] }, [ POWER5p_PME_PM_L2_PREF ] = { .pme_name = "PM_L2_PREF", .pme_code = 0xc50c3, .pme_short_desc = "L2 cache prefetches", .pme_long_desc = "A request to prefetch data into L2 was made", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2_PREF], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2_PREF] }, [ POWER5p_PME_PM_GCT_NOSLOT_BR_MPRED ] = { .pme_name = "PM_GCT_NOSLOT_BR_MPRED", .pme_code = 0x41009c, .pme_short_desc = "No slot in GCT caused by branch mispredict", .pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread because of a branch misprediction.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GCT_NOSLOT_BR_MPRED], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GCT_NOSLOT_BR_MPRED] }, [ POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L25_MOD", .pme_code = 0x2c7097, .pme_short_desc = "Marked data loaded from L2.5 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L2 of a chip on the same module as this processor is located due to a marked load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD] }, [ POWER5p_PME_PM_L2SB_ST_REQ ] = { .pme_name = "PM_L2SB_ST_REQ", .pme_code = 0x723e1, .pme_short_desc = "L2 slice B store requests", .pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A, B, and C.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_ST_REQ], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_ST_REQ] }, [ POWER5p_PME_PM_L2SB_MOD_INV ] = { .pme_name = "PM_L2SB_MOD_INV", .pme_code = 0x730e1, .pme_short_desc = "L2 slice B transition from modified to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_MOD_INV], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_MOD_INV] }, [ POWER5p_PME_PM_MRK_L1_RELOAD_VALID ] = { .pme_name = "PM_MRK_L1_RELOAD_VALID", .pme_code = 0xc70e4, .pme_short_desc = "Marked L1 reload data source valid", .pme_long_desc = "The source information is valid and is for a marked load", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_L1_RELOAD_VALID], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_L1_RELOAD_VALID] }, [ POWER5p_PME_PM_L3SB_HIT ] = { .pme_name = "PM_L3SB_HIT", .pme_code = 0x711c4, .pme_short_desc = "L3 slice B hits", .pme_long_desc = "Number of attempts made by this chip cores that resulted in an L3 hit. Reported per L3 slice", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SB_HIT], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SB_HIT] }, [ POWER5p_PME_PM_L2SB_SHR_MOD ] = { .pme_name = "PM_L2SB_SHR_MOD", .pme_code = 0x700c1, .pme_short_desc = "L2 slice B transition from shared to modified", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A, B, and C.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_SHR_MOD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_SHR_MOD] }, [ POWER5p_PME_PM_EE_OFF_EXT_INT ] = { .pme_name = "PM_EE_OFF_EXT_INT", .pme_code = 0x130e7, .pme_short_desc = "Cycles MSR(EE) bit off and external interrupt pending", .pme_long_desc = "Cycles when an interrupt due to an external exception is pending but external exceptions were masked.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_EE_OFF_EXT_INT], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_EE_OFF_EXT_INT] }, [ POWER5p_PME_PM_1PLUS_PPC_CMPL ] = { .pme_name = "PM_1PLUS_PPC_CMPL", .pme_code = 0x100013, .pme_short_desc = "One or more PPC instruction completed", .pme_long_desc = "A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_1PLUS_PPC_CMPL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_1PLUS_PPC_CMPL] }, [ POWER5p_PME_PM_L2SC_SHR_MOD ] = { .pme_name = "PM_L2SC_SHR_MOD", .pme_code = 0x700c2, .pme_short_desc = "L2 slice C transition from shared to modified", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A, B, and C.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_SHR_MOD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_SHR_MOD] }, [ POWER5p_PME_PM_PMC6_OVERFLOW ] = { .pme_name = "PM_PMC6_OVERFLOW", .pme_code = 0x30001a, .pme_short_desc = "PMC6 Overflow", .pme_long_desc = "Overflows from PMC6 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PMC6_OVERFLOW], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PMC6_OVERFLOW] }, [ POWER5p_PME_PM_IC_PREF_INSTALL ] = { .pme_name = "PM_IC_PREF_INSTALL", .pme_code = 0x210c7, .pme_short_desc = "Instruction prefetched installed in prefetch buffer", .pme_long_desc = "A prefetch buffer entry (line) is allocated but the request is not a demand fetch.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_IC_PREF_INSTALL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_IC_PREF_INSTALL] }, [ POWER5p_PME_PM_LSU_LRQ_FULL_CYC ] = { .pme_name = "PM_LSU_LRQ_FULL_CYC", .pme_code = 0x110c2, .pme_short_desc = "Cycles LRQ full", .pme_long_desc = "Cycles when the LRQ is full.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_LRQ_FULL_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_LRQ_FULL_CYC] }, [ POWER5p_PME_PM_TLB_MISS ] = { .pme_name = "PM_TLB_MISS", .pme_code = 0x180088, .pme_short_desc = "TLB misses", .pme_long_desc = "Total of Data TLB mises + Instruction TLB misses", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_TLB_MISS], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_TLB_MISS] }, [ POWER5p_PME_PM_GCT_FULL_CYC ] = { .pme_name = "PM_GCT_FULL_CYC", .pme_code = 0x100c0, .pme_short_desc = "Cycles GCT full", .pme_long_desc = "The Global Completion Table is completely full.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GCT_FULL_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GCT_FULL_CYC] }, [ POWER5p_PME_PM_FXU_BUSY ] = { .pme_name = "PM_FXU_BUSY", .pme_code = 0x200012, .pme_short_desc = "FXU busy", .pme_long_desc = "Cycles when both FXU0 and FXU1 are busy.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FXU_BUSY], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FXU_BUSY] }, [ POWER5p_PME_PM_MRK_DATA_FROM_L3_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L3_CYC", .pme_code = 0x2c70a4, .pme_short_desc = "Marked load latency from L3", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L3_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L3_CYC] }, [ POWER5p_PME_PM_LSU_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU_REJECT_LMQ_FULL", .pme_code = 0x2c4088, .pme_short_desc = "LSU reject due to LMQ full or missed data coming", .pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all the eight entries are full, subsequent load instructions are rejected. Combined unit 0 + 1.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_REJECT_LMQ_FULL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_REJECT_LMQ_FULL] }, [ POWER5p_PME_PM_LSU_SRQ_S0_ALLOC ] = { .pme_name = "PM_LSU_SRQ_S0_ALLOC", .pme_code = 0xc20e7, .pme_short_desc = "SRQ slot 0 allocated", .pme_long_desc = "SRQ Slot zero was allocated", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_SRQ_S0_ALLOC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_SRQ_S0_ALLOC] }, [ POWER5p_PME_PM_GRP_MRK ] = { .pme_name = "PM_GRP_MRK", .pme_code = 0x100014, .pme_short_desc = "Group marked in IDU", .pme_long_desc = "A group was sampled (marked). The group is called a marked group. One instruction within the group is tagged for detailed monitoring. The sampled instruction is called a marked instructions. Events associated with the marked instruction are annotated with the marked term.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GRP_MRK], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GRP_MRK] }, [ POWER5p_PME_PM_INST_FROM_L25_SHR ] = { .pme_name = "PM_INST_FROM_L25_SHR", .pme_code = 0x122096, .pme_short_desc = "Instruction fetched from L2.5 shared", .pme_long_desc = "An instruction fetch group was fetched with shared (T or SL) data from the L2 of a chip on the same module as this processor is located. Fetch groups can contain up to 8 instructions.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_L25_SHR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_L25_SHR] }, [ POWER5p_PME_PM_DC_PREF_STREAM_ALLOC ] = { .pme_name = "PM_DC_PREF_STREAM_ALLOC", .pme_code = 0x830e7, .pme_short_desc = "D cache new prefetch stream allocated", .pme_long_desc = "A new Prefetch Stream was allocated.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DC_PREF_STREAM_ALLOC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DC_PREF_STREAM_ALLOC] }, [ POWER5p_PME_PM_FPU1_FIN ] = { .pme_name = "PM_FPU1_FIN", .pme_code = 0x10c7, .pme_short_desc = "FPU1 produced a result", .pme_long_desc = "FPU1 finished, produced a result. This only indicates finish, not completion. Floating Point Stores are included in this count but not Floating Point Loads., ,", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU1_FIN], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU1_FIN] }, [ POWER5p_PME_PM_BR_MPRED_TA ] = { .pme_name = "PM_BR_MPRED_TA", .pme_code = 0x230e6, .pme_short_desc = "Branch mispredictions due to target address", .pme_long_desc = "A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_BR_MPRED_TA], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_BR_MPRED_TA] }, [ POWER5p_PME_PM_MRK_DTLB_REF_64K ] = { .pme_name = "PM_MRK_DTLB_REF_64K", .pme_code = 0x2c6086, .pme_short_desc = "Marked Data TLB reference for 64K page", .pme_long_desc = "Data TLB references by a marked instruction for 64KB pages.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DTLB_REF_64K], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DTLB_REF_64K] }, [ POWER5p_PME_PM_RUN_INST_CMPL ] = { .pme_name = "PM_RUN_INST_CMPL", .pme_code = 0x500009, .pme_short_desc = "Run instructions completed", .pme_long_desc = "Number of run instructions completed.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_RUN_INST_CMPL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_RUN_INST_CMPL] }, [ POWER5p_PME_PM_CRQ_FULL_CYC ] = { .pme_name = "PM_CRQ_FULL_CYC", .pme_code = 0x110c1, .pme_short_desc = "Cycles CR issue queue full", .pme_long_desc = "The issue queue that feeds the Conditional Register unit is full. This condition will prevent dispatch groups from being dispatched. This event only indicates that the queue was full, not that dispatch was prevented.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_CRQ_FULL_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_CRQ_FULL_CYC] }, [ POWER5p_PME_PM_L2SA_RCLD_DISP ] = { .pme_name = "PM_L2SA_RCLD_DISP", .pme_code = 0x701c0, .pme_short_desc = "L2 slice A RC load dispatch attempt", .pme_long_desc = "A Read/Claim dispatch for a Load was attempted", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_RCLD_DISP], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_RCLD_DISP] }, [ POWER5p_PME_PM_SNOOP_WR_RETRY_QFULL ] = { .pme_name = "PM_SNOOP_WR_RETRY_QFULL", .pme_code = 0x710c6, .pme_short_desc = "Snoop read retry due to read queue full", .pme_long_desc = "A snoop request for a write to memory was retried because the write queues were full. When this happens the snoop request is retried and the writes in the write reorder queue are changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SNOOP_WR_RETRY_QFULL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SNOOP_WR_RETRY_QFULL] }, [ POWER5p_PME_PM_MRK_DTLB_REF_4K ] = { .pme_name = "PM_MRK_DTLB_REF_4K", .pme_code = 0x1c6086, .pme_short_desc = "Marked Data TLB reference for 4K page", .pme_long_desc = "Data TLB references by a marked instruction for 4KB pages.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DTLB_REF_4K], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DTLB_REF_4K] }, [ POWER5p_PME_PM_LSU_SRQ_S0_VALID ] = { .pme_name = "PM_LSU_SRQ_S0_VALID", .pme_code = 0xc20e6, .pme_short_desc = "SRQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the SRQ is split between the two threads (16 entries each).", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_SRQ_S0_VALID], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_SRQ_S0_VALID] }, [ POWER5p_PME_PM_LSU0_FLUSH_LRQ ] = { .pme_name = "PM_LSU0_FLUSH_LRQ", .pme_code = 0xc00c2, .pme_short_desc = "LSU0 LRQ flushes", .pme_long_desc = "A load was flushed by unit 0 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU0_FLUSH_LRQ], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU0_FLUSH_LRQ] }, [ POWER5p_PME_PM_INST_FROM_L275_MOD ] = { .pme_name = "PM_INST_FROM_L275_MOD", .pme_code = 0x422096, .pme_short_desc = "Instruction fetched from L2.75 modified", .pme_long_desc = "An instruction fetch group was fetched with modified (M) data from the L2 on a different module than this processor is located. Fetch groups can contain up to 8 instructions", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_L275_MOD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_L275_MOD] }, [ POWER5p_PME_PM_GCT_EMPTY_CYC ] = { .pme_name = "PM_GCT_EMPTY_CYC", .pme_code = 0x200004, .pme_short_desc = "Cycles GCT empty", .pme_long_desc = "The Global Completion Table is completely empty", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GCT_EMPTY_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GCT_EMPTY_CYC] }, [ POWER5p_PME_PM_LARX_LSU0 ] = { .pme_name = "PM_LARX_LSU0", .pme_code = 0x820e7, .pme_short_desc = "Larx executed on LSU0", .pme_long_desc = "A larx (lwarx or ldarx) was executed on side 0 (there is no corresponding unit 1 event since larx instructions can only execute on unit 0)", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LARX_LSU0], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LARX_LSU0] }, [ POWER5p_PME_PM_THRD_PRIO_DIFF_5or6_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_5or6_CYC", .pme_code = 0x430e6, .pme_short_desc = "Cycles thread priority difference is 5 or 6", .pme_long_desc = "Cycles when this thread's priority is higher than the other thread's priority by 5 or 6.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_PRIO_DIFF_5or6_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_PRIO_DIFF_5or6_CYC] }, [ POWER5p_PME_PM_SNOOP_RETRY_1AHEAD ] = { .pme_name = "PM_SNOOP_RETRY_1AHEAD", .pme_code = 0x725e6, .pme_short_desc = "Snoop retry due to one ahead collision", .pme_long_desc = "Snoop retry due to one ahead collision", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SNOOP_RETRY_1AHEAD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SNOOP_RETRY_1AHEAD] }, [ POWER5p_PME_PM_FPU1_FSQRT ] = { .pme_name = "PM_FPU1_FSQRT", .pme_code = 0xc6, .pme_short_desc = "FPU1 executed FSQRT instruction", .pme_long_desc = "FPU1 has executed a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU1_FSQRT], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU1_FSQRT] }, [ POWER5p_PME_PM_MRK_LD_MISS_L1_LSU1 ] = { .pme_name = "PM_MRK_LD_MISS_L1_LSU1", .pme_code = 0x820e4, .pme_short_desc = "LSU1 marked L1 D cache load misses", .pme_long_desc = "Load references that miss the Level 1 Data cache, by LSU1.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LD_MISS_L1_LSU1], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LD_MISS_L1_LSU1] }, [ POWER5p_PME_PM_MRK_FPU_FIN ] = { .pme_name = "PM_MRK_FPU_FIN", .pme_code = 0x300014, .pme_short_desc = "Marked instruction FPU processing finished", .pme_long_desc = "One of the Floating Point Units finished a marked instruction. Instructions that finish may not necessary complete", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_FPU_FIN], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_FPU_FIN] }, [ POWER5p_PME_PM_THRD_PRIO_5_CYC ] = { .pme_name = "PM_THRD_PRIO_5_CYC", .pme_code = 0x420e4, .pme_short_desc = "Cycles thread running at priority level 5", .pme_long_desc = "Cycles this thread was running at priority level 5.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_PRIO_5_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_PRIO_5_CYC] }, [ POWER5p_PME_PM_MRK_DATA_FROM_LMEM ] = { .pme_name = "PM_MRK_DATA_FROM_LMEM", .pme_code = 0x2c7087, .pme_short_desc = "Marked data loaded from local memory", .pme_long_desc = "The processor's Data Cache was reloaded due to a marked load from memory attached to the same module this proccessor is located on.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_LMEM], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_LMEM] }, [ POWER5p_PME_PM_SNOOP_TLBIE ] = { .pme_name = "PM_SNOOP_TLBIE", .pme_code = 0x800c3, .pme_short_desc = "Snoop TLBIE", .pme_long_desc = "A tlbie was snooped from another processor.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SNOOP_TLBIE], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SNOOP_TLBIE] }, [ POWER5p_PME_PM_FPU1_FRSP_FCONV ] = { .pme_name = "PM_FPU1_FRSP_FCONV", .pme_code = 0x10c5, .pme_short_desc = "FPU1 executed FRSP or FCONV instructions", .pme_long_desc = "FPU1 has executed a frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU1_FRSP_FCONV], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU1_FRSP_FCONV] }, [ POWER5p_PME_PM_DTLB_MISS_16G ] = { .pme_name = "PM_DTLB_MISS_16G", .pme_code = 0x4c208d, .pme_short_desc = "Data TLB miss for 16G page", .pme_long_desc = "Data TLB references to 16GB pages that missed the TLB. Page size is determined at TLB reload time.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DTLB_MISS_16G], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DTLB_MISS_16G] }, [ POWER5p_PME_PM_L3SB_SNOOP_RETRY ] = { .pme_name = "PM_L3SB_SNOOP_RETRY", .pme_code = 0x731e4, .pme_short_desc = "L3 slice B snoop retries", .pme_long_desc = "Number of times an L3 retried a snoop because it got two in at the same time (one on snp_a, one on snp_b)", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SB_SNOOP_RETRY], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SB_SNOOP_RETRY] }, [ POWER5p_PME_PM_FAB_VBYPASS_EMPTY ] = { .pme_name = "PM_FAB_VBYPASS_EMPTY", .pme_code = 0x731e7, .pme_short_desc = "Vertical bypass buffer empty", .pme_long_desc = "Fabric cycles when the Middle Bypass sidecar is empty. The signal is delivered at FBC speed and the count must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_VBYPASS_EMPTY], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_VBYPASS_EMPTY] }, [ POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L275_MOD", .pme_code = 0x1c70a3, .pme_short_desc = "Marked data loaded from L2.75 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L2 on a different module than this processor is located due to a marked load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L275_MOD] }, [ POWER5p_PME_PM_L2SB_RCST_DISP ] = { .pme_name = "PM_L2SB_RCST_DISP", .pme_code = 0x702c1, .pme_short_desc = "L2 slice B RC store dispatch attempt", .pme_long_desc = "A Read/Claim dispatch for a Store was attempted.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_RCST_DISP], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_RCST_DISP] }, [ POWER5p_PME_PM_6INST_CLB_CYC ] = { .pme_name = "PM_6INST_CLB_CYC", .pme_code = 0x400c6, .pme_short_desc = "Cycles 6 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_6INST_CLB_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_6INST_CLB_CYC] }, [ POWER5p_PME_PM_FLUSH ] = { .pme_name = "PM_FLUSH", .pme_code = 0x110c7, .pme_short_desc = "Flushes", .pme_long_desc = "Flushes occurred including LSU and Branch flushes.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FLUSH], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FLUSH] }, [ POWER5p_PME_PM_L2SC_MOD_INV ] = { .pme_name = "PM_L2SC_MOD_INV", .pme_code = 0x730e2, .pme_short_desc = "L2 slice C transition from modified to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_MOD_INV], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_MOD_INV] }, [ POWER5p_PME_PM_FPU_DENORM ] = { .pme_name = "PM_FPU_DENORM", .pme_code = 0x102088, .pme_short_desc = "FPU received denormalized data", .pme_long_desc = "The floating point unit has encountered a denormalized operand. Combined Unit 0 + Unit 1.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU_DENORM], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU_DENORM] }, [ POWER5p_PME_PM_L3SC_HIT ] = { .pme_name = "PM_L3SC_HIT", .pme_code = 0x711c5, .pme_short_desc = "L3 slice C hits", .pme_long_desc = "Number of attempts made by this chip cores that resulted in an L3 hit. Reported per L3 Slice", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SC_HIT], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SC_HIT] }, [ POWER5p_PME_PM_SNOOP_WR_RETRY_RQ ] = { .pme_name = "PM_SNOOP_WR_RETRY_RQ", .pme_code = 0x706c6, .pme_short_desc = "Snoop write/dclaim retry due to collision with active read queue", .pme_long_desc = "A snoop request for a write or dclaim to memory was retried because it matched the cacheline of an active read. This event is sent from the Memory Controller clock domain and must be scaled accordingly", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SNOOP_WR_RETRY_RQ], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SNOOP_WR_RETRY_RQ] }, [ POWER5p_PME_PM_LSU1_REJECT_SRQ ] = { .pme_name = "PM_LSU1_REJECT_SRQ", .pme_code = 0xc40c4, .pme_short_desc = "LSU1 SRQ lhs rejects", .pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions because of Load Hit Store conditions. Loads are rejected when data is needed from a previous store instruction but store forwarding is not possible because the data is not fully contained in the Store Data Queue or is not yet available in the Store Data Queue.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU1_REJECT_SRQ], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU1_REJECT_SRQ] }, [ POWER5p_PME_PM_L3SC_ALL_BUSY ] = { .pme_name = "PM_L3SC_ALL_BUSY", .pme_code = 0x721e5, .pme_short_desc = "L3 slice C active for every cycle all CI/CO machines busy", .pme_long_desc = "Cycles All Castin/Castout machines are busy.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SC_ALL_BUSY], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SC_ALL_BUSY] }, [ POWER5p_PME_PM_IC_PREF_REQ ] = { .pme_name = "PM_IC_PREF_REQ", .pme_code = 0x220e6, .pme_short_desc = "Instruction prefetch requests", .pme_long_desc = "An instruction prefetch request has been made.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_IC_PREF_REQ], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_IC_PREF_REQ] }, [ POWER5p_PME_PM_MRK_GRP_IC_MISS ] = { .pme_name = "PM_MRK_GRP_IC_MISS", .pme_code = 0x412091, .pme_short_desc = "Group experienced marked I cache miss", .pme_long_desc = "A group containing a marked (sampled) instruction experienced an instruction cache miss.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_GRP_IC_MISS], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_GRP_IC_MISS] }, [ POWER5p_PME_PM_GCT_NOSLOT_IC_MISS ] = { .pme_name = "PM_GCT_NOSLOT_IC_MISS", .pme_code = 0x21009c, .pme_short_desc = "No slot in GCT caused by I cache miss", .pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread because of an Instruction Cache miss.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GCT_NOSLOT_IC_MISS], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GCT_NOSLOT_IC_MISS] }, [ POWER5p_PME_PM_MRK_DATA_FROM_L3 ] = { .pme_name = "PM_MRK_DATA_FROM_L3", .pme_code = 0x1c708e, .pme_short_desc = "Marked data loaded from L3", .pme_long_desc = "The processor's Data Cache was reloaded from the local L3 due to a marked load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L3], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L3] }, [ POWER5p_PME_PM_GCT_NOSLOT_SRQ_FULL ] = { .pme_name = "PM_GCT_NOSLOT_SRQ_FULL", .pme_code = 0x310084, .pme_short_desc = "No slot in GCT caused by SRQ full", .pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread because the Store Request Queue (SRQ) is full. This happens when the storage subsystem can not process the stores in the SRQ. Groups can not be dispatched until a SRQ entry is available.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GCT_NOSLOT_SRQ_FULL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GCT_NOSLOT_SRQ_FULL] }, [ POWER5p_PME_PM_CMPLU_STALL_DCACHE_MISS ] = { .pme_name = "PM_CMPLU_STALL_DCACHE_MISS", .pme_code = 0x21109a, .pme_short_desc = "Completion stall caused by D cache miss", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a Data Cache Miss. Data Cache Miss has higher priority than any other Load/Store delay, so if an instruction encounters multiple delays only the Data Cache Miss will be reported and the entire delay period will be charged to Data Cache Miss. This is a subset of PM_CMPLU_STALL_LSU.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_CMPLU_STALL_DCACHE_MISS], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_CMPLU_STALL_DCACHE_MISS] }, [ POWER5p_PME_PM_THRD_SEL_OVER_ISU_HOLD ] = { .pme_name = "PM_THRD_SEL_OVER_ISU_HOLD", .pme_code = 0x410c5, .pme_short_desc = "Thread selection overrides caused by ISU holds", .pme_long_desc = "Thread selection was overridden because of an ISU hold.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_SEL_OVER_ISU_HOLD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_SEL_OVER_ISU_HOLD] }, [ POWER5p_PME_PM_LSU_FLUSH_LRQ ] = { .pme_name = "PM_LSU_FLUSH_LRQ", .pme_code = 0x2c0090, .pme_short_desc = "LRQ flushes", .pme_long_desc = "A load was flushed because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. Combined Units 0 and 1.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_FLUSH_LRQ], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_FLUSH_LRQ] }, [ POWER5p_PME_PM_THRD_PRIO_2_CYC ] = { .pme_name = "PM_THRD_PRIO_2_CYC", .pme_code = 0x420e1, .pme_short_desc = "Cycles thread running at priority level 2", .pme_long_desc = "Cycles this thread was running at priority level 2.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_PRIO_2_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_PRIO_2_CYC] }, [ POWER5p_PME_PM_L3SA_MOD_INV ] = { .pme_name = "PM_L3SA_MOD_INV", .pme_code = 0x730e3, .pme_short_desc = "L3 slice A transition from modified to invalid", .pme_long_desc = "L3 snooper detects someone doing a store to a line that is truly M in this L3 (i.e. L3 going M=>I) Mu|Me are not included since they are formed due to a prev read op. Tx is not included since it is considered shared at this point.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SA_MOD_INV], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SA_MOD_INV] }, [ POWER5p_PME_PM_LSU_FLUSH_SRQ ] = { .pme_name = "PM_LSU_FLUSH_SRQ", .pme_code = 0x1c0090, .pme_short_desc = "SRQ flushes", .pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group. Combined Unit 0 + 1.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_FLUSH_SRQ], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_FLUSH_SRQ] }, [ POWER5p_PME_PM_MRK_LSU_SRQ_INST_VALID ] = { .pme_name = "PM_MRK_LSU_SRQ_INST_VALID", .pme_code = 0xc70e6, .pme_short_desc = "Marked instruction valid in SRQ", .pme_long_desc = "This signal is asserted every cycle when a marked request is resident in the Store Request Queue", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LSU_SRQ_INST_VALID], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LSU_SRQ_INST_VALID] }, [ POWER5p_PME_PM_L3SA_REF ] = { .pme_name = "PM_L3SA_REF", .pme_code = 0x701c3, .pme_short_desc = "L3 slice A references", .pme_long_desc = "Number of attempts made by this chip cores to find data in the L3. Reported per L3 slice", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SA_REF], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SA_REF] }, [ POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL ] = { .pme_name = "PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL", .pme_code = 0x713c2, .pme_short_desc = "L2 slice C RC dispatch attempt failed due to all CO busy", .pme_long_desc = "A Read/Claim dispatch was rejected because all Castout machines were busy.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL] }, [ POWER5p_PME_PM_FPU0_STALL3 ] = { .pme_name = "PM_FPU0_STALL3", .pme_code = 0x20e1, .pme_short_desc = "FPU0 stalled in pipe3", .pme_long_desc = "FPU0 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always).", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU0_STALL3], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU0_STALL3] }, [ POWER5p_PME_PM_TB_BIT_TRANS ] = { .pme_name = "PM_TB_BIT_TRANS", .pme_code = 0x100018, .pme_short_desc = "Time Base bit transition", .pme_long_desc = "When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_TB_BIT_TRANS], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_TB_BIT_TRANS] }, [ POWER5p_PME_PM_GPR_MAP_FULL_CYC ] = { .pme_name = "PM_GPR_MAP_FULL_CYC", .pme_code = 0x130e5, .pme_short_desc = "Cycles GPR mapper full", .pme_long_desc = "The General Purpose Register mapper cannot accept any more groups. This condition will prevent dispatch groups from being dispatched. This event only indicates that the mapper was full, not that dispatch was prevented.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GPR_MAP_FULL_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GPR_MAP_FULL_CYC] }, [ POWER5p_PME_PM_MRK_LSU_FLUSH_LRQ ] = { .pme_name = "PM_MRK_LSU_FLUSH_LRQ", .pme_code = 0x381088, .pme_short_desc = "Marked LRQ flushes", .pme_long_desc = "A marked load was flushed because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LSU_FLUSH_LRQ], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LSU_FLUSH_LRQ] }, [ POWER5p_PME_PM_FPU0_STF ] = { .pme_name = "PM_FPU0_STF", .pme_code = 0x20e2, .pme_short_desc = "FPU0 executed store instruction", .pme_long_desc = "FPU0 has executed a Floating Point Store instruction.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU0_STF], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU0_STF] }, [ POWER5p_PME_PM_MRK_DTLB_MISS ] = { .pme_name = "PM_MRK_DTLB_MISS", .pme_code = 0xc50c6, .pme_short_desc = "Marked Data TLB misses", .pme_long_desc = "Data TLB references by a marked instruction that missed the TLB (all page sizes).", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DTLB_MISS], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DTLB_MISS] }, [ POWER5p_PME_PM_FPU1_FMA ] = { .pme_name = "PM_FPU1_FMA", .pme_code = 0xc5, .pme_short_desc = "FPU1 executed multiply-add instruction", .pme_long_desc = "The floating point unit has executed a multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU1_FMA], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU1_FMA] }, [ POWER5p_PME_PM_L2SA_MOD_TAG ] = { .pme_name = "PM_L2SA_MOD_TAG", .pme_code = 0x720e0, .pme_short_desc = "L2 slice A transition from modified to tagged", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_MOD_TAG], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_MOD_TAG] }, [ POWER5p_PME_PM_LSU1_FLUSH_ULD ] = { .pme_name = "PM_LSU1_FLUSH_ULD", .pme_code = 0xc00c4, .pme_short_desc = "LSU1 unaligned load flushes", .pme_long_desc = "A load was flushed from unit 1 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1).", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU1_FLUSH_ULD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU1_FLUSH_ULD] }, [ POWER5p_PME_PM_MRK_INST_FIN ] = { .pme_name = "PM_MRK_INST_FIN", .pme_code = 0x300005, .pme_short_desc = "Marked instruction finished", .pme_long_desc = "One of the execution units finished a marked instruction. Instructions that finish may not necessary complete", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_INST_FIN], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_INST_FIN] }, [ POWER5p_PME_PM_MRK_LSU0_FLUSH_UST ] = { .pme_name = "PM_MRK_LSU0_FLUSH_UST", .pme_code = 0x810c0, .pme_short_desc = "LSU0 marked unaligned store flushes", .pme_long_desc = "A marked store was flushed from unit 0 because it was unaligned", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LSU0_FLUSH_UST], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LSU0_FLUSH_UST] }, [ POWER5p_PME_PM_FPU0_FULL_CYC ] = { .pme_name = "PM_FPU0_FULL_CYC", .pme_code = 0x100c3, .pme_short_desc = "Cycles FPU0 issue queue full", .pme_long_desc = "The issue queue for FPU0 cannot accept any more instruction. Dispatch to this issue queue is stopped.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU0_FULL_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU0_FULL_CYC] }, [ POWER5p_PME_PM_LSU_LRQ_S0_ALLOC ] = { .pme_name = "PM_LSU_LRQ_S0_ALLOC", .pme_code = 0xc60e7, .pme_short_desc = "LRQ slot 0 allocated", .pme_long_desc = "LRQ slot zero was allocated", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_LRQ_S0_ALLOC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_LRQ_S0_ALLOC] }, [ POWER5p_PME_PM_MRK_LSU1_FLUSH_ULD ] = { .pme_name = "PM_MRK_LSU1_FLUSH_ULD", .pme_code = 0x810c4, .pme_short_desc = "LSU1 marked unaligned load flushes", .pme_long_desc = "A marked load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LSU1_FLUSH_ULD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LSU1_FLUSH_ULD] }, [ POWER5p_PME_PM_MRK_DTLB_REF ] = { .pme_name = "PM_MRK_DTLB_REF", .pme_code = 0xc60e4, .pme_short_desc = "Marked Data TLB reference", .pme_long_desc = "Total number of Data TLB references by a marked instruction for all page sizes. Page size is determined at TLB reload time.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DTLB_REF], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DTLB_REF] }, [ POWER5p_PME_PM_BR_UNCOND ] = { .pme_name = "PM_BR_UNCOND", .pme_code = 0x123087, .pme_short_desc = "Unconditional branch", .pme_long_desc = "An unconditional branch was executed.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_BR_UNCOND], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_BR_UNCOND] }, [ POWER5p_PME_PM_THRD_SEL_OVER_L2MISS ] = { .pme_name = "PM_THRD_SEL_OVER_L2MISS", .pme_code = 0x410c3, .pme_short_desc = "Thread selection overrides caused by L2 misses", .pme_long_desc = "Thread selection was overridden because one thread was had a L2 miss pending.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_SEL_OVER_L2MISS], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_SEL_OVER_L2MISS] }, [ POWER5p_PME_PM_L2SB_SHR_INV ] = { .pme_name = "PM_L2SB_SHR_INV", .pme_code = 0x710c1, .pme_short_desc = "L2 slice B transition from shared to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A, B, and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_SHR_INV], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_SHR_INV] }, [ POWER5p_PME_PM_MEM_LO_PRIO_WR_CMPL ] = { .pme_name = "PM_MEM_LO_PRIO_WR_CMPL", .pme_code = 0x736e6, .pme_short_desc = "Low priority write completed", .pme_long_desc = "A memory write, which was not upgraded to high priority, completed. This event is sent from the Memory Controller clock domain and must be scaled accordingly", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_LO_PRIO_WR_CMPL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_LO_PRIO_WR_CMPL] }, [ POWER5p_PME_PM_MRK_DTLB_MISS_64K ] = { .pme_name = "PM_MRK_DTLB_MISS_64K", .pme_code = 0x2c608d, .pme_short_desc = "Marked Data TLB misses for 64K page", .pme_long_desc = "Data TLB references to 64KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DTLB_MISS_64K], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DTLB_MISS_64K] }, [ POWER5p_PME_PM_MRK_ST_MISS_L1 ] = { .pme_name = "PM_MRK_ST_MISS_L1", .pme_code = 0x820e3, .pme_short_desc = "Marked L1 D cache store misses", .pme_long_desc = "A marked store missed the dcache", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_ST_MISS_L1], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_ST_MISS_L1] }, [ POWER5p_PME_PM_L3SC_MOD_TAG ] = { .pme_name = "PM_L3SC_MOD_TAG", .pme_code = 0x720e5, .pme_short_desc = "L3 slice C transition from modified to TAG", .pme_long_desc = "L3 snooper detects someone doing a read to a line that is truly M in this L3(i.e. L3 going M->T or M->I(go_Mu case); Mu|Me are not included since they are formed due to a prev read op). Tx is not included since it is considered shared at this point.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SC_MOD_TAG], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SC_MOD_TAG] }, [ POWER5p_PME_PM_GRP_DISP_SUCCESS ] = { .pme_name = "PM_GRP_DISP_SUCCESS", .pme_code = 0x300002, .pme_short_desc = "Group dispatch success", .pme_long_desc = "Number of groups sucessfully dispatched (not rejected)", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GRP_DISP_SUCCESS], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GRP_DISP_SUCCESS] }, [ POWER5p_PME_PM_THRD_PRIO_DIFF_1or2_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_1or2_CYC", .pme_code = 0x430e4, .pme_short_desc = "Cycles thread priority difference is 1 or 2", .pme_long_desc = "Cycles when this thread's priority is higher than the other thread's priority by 1 or 2.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_PRIO_DIFF_1or2_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_PRIO_DIFF_1or2_CYC] }, [ POWER5p_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = { .pme_name = "PM_IC_DEMAND_L2_BHT_REDIRECT", .pme_code = 0x230e0, .pme_short_desc = "L2 I cache demand request due to BHT redirect", .pme_long_desc = "A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (CR mispredict).", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_IC_DEMAND_L2_BHT_REDIRECT], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_IC_DEMAND_L2_BHT_REDIRECT] }, [ POWER5p_PME_PM_LSU_DERAT_MISS ] = { .pme_name = "PM_LSU_DERAT_MISS", .pme_code = 0x280090, .pme_short_desc = "DERAT misses", .pme_long_desc = "Total D-ERAT Misses. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction. Combined Unit 0 + 1.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_DERAT_MISS], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_DERAT_MISS] }, [ POWER5p_PME_PM_MEM_WQ_DISP_Q8to15 ] = { .pme_name = "PM_MEM_WQ_DISP_Q8to15", .pme_code = 0x733e6, .pme_short_desc = "Memory write queue dispatched to queues 8-15", .pme_long_desc = "A memory operation was dispatched to a write queue in the range between 8 and 15. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_WQ_DISP_Q8to15], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_WQ_DISP_Q8to15] }, [ POWER5p_PME_PM_FPU0_SINGLE ] = { .pme_name = "PM_FPU0_SINGLE", .pme_code = 0x20e3, .pme_short_desc = "FPU0 executed single precision instruction", .pme_long_desc = "FPU0 has executed a single precision instruction.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU0_SINGLE], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU0_SINGLE] }, [ POWER5p_PME_PM_THRD_PRIO_1_CYC ] = { .pme_name = "PM_THRD_PRIO_1_CYC", .pme_code = 0x420e0, .pme_short_desc = "Cycles thread running at priority level 1", .pme_long_desc = "Cycles this thread was running at priority level 1. Priority level 1 is the lowest and indicates the thread is sleeping.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_PRIO_1_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_PRIO_1_CYC] }, [ POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2SC_RCST_DISP_FAIL_OTHER", .pme_code = 0x732e2, .pme_short_desc = "L2 slice C RC store dispatch attempt failed due to other reasons", .pme_long_desc = "A Read/Claim dispatch for a store failed for some reason other than Full or Collision conditions. Rejected dispatches do not count because they have not yet been attempted.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_OTHER], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_OTHER] }, [ POWER5p_PME_PM_SNOOP_RD_RETRY_RQ ] = { .pme_name = "PM_SNOOP_RD_RETRY_RQ", .pme_code = 0x705c6, .pme_short_desc = "Snoop read retry due to collision with active read queue", .pme_long_desc = "A snoop request for a read from memory was retried because it matched the cache line of an active read. The snoop request is retried because the L2 may be able to source data via intervention for the 2nd read faster than the MC. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SNOOP_RD_RETRY_RQ], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SNOOP_RD_RETRY_RQ] }, [ POWER5p_PME_PM_FAB_HOLDtoVN_EMPTY ] = { .pme_name = "PM_FAB_HOLDtoVN_EMPTY", .pme_code = 0x721e7, .pme_short_desc = "Hold buffer to VN empty", .pme_long_desc = "Fabric cycles when the Vertical Node out hold-buffers are emtpy. The signal is delivered at FBC speed and the count must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_HOLDtoVN_EMPTY], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_HOLDtoVN_EMPTY] }, [ POWER5p_PME_PM_FPU1_FEST ] = { .pme_name = "PM_FPU1_FEST", .pme_code = 0x10c6, .pme_short_desc = "FPU1 executed FEST instruction", .pme_long_desc = "FPU1 has executed an estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU1_FEST], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU1_FEST] }, [ POWER5p_PME_PM_SNOOP_DCLAIM_RETRY_QFULL ] = { .pme_name = "PM_SNOOP_DCLAIM_RETRY_QFULL", .pme_code = 0x720e6, .pme_short_desc = "Snoop dclaim/flush retry due to write/dclaim queues full", .pme_long_desc = "The memory controller A memory write was dispatched to a write queue. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SNOOP_DCLAIM_RETRY_QFULL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SNOOP_DCLAIM_RETRY_QFULL] }, [ POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L25_SHR_CYC", .pme_code = 0x2c70a2, .pme_short_desc = "Marked load latency from L2.5 shared", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR_CYC] }, [ POWER5p_PME_PM_MRK_ST_CMPL_INT ] = { .pme_name = "PM_MRK_ST_CMPL_INT", .pme_code = 0x300003, .pme_short_desc = "Marked store completed with intervention", .pme_long_desc = "A marked store previously sent to the memory subsystem completed (data home) after requiring intervention", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_ST_CMPL_INT], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_ST_CMPL_INT] }, [ POWER5p_PME_PM_FLUSH_BR_MPRED ] = { .pme_name = "PM_FLUSH_BR_MPRED", .pme_code = 0x110c6, .pme_short_desc = "Flush caused by branch mispredict", .pme_long_desc = "A flush was caused by a branch mispredict.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FLUSH_BR_MPRED], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FLUSH_BR_MPRED] }, [ POWER5p_PME_PM_MRK_DTLB_MISS_16G ] = { .pme_name = "PM_MRK_DTLB_MISS_16G", .pme_code = 0x4c608d, .pme_short_desc = "Marked Data TLB misses for 16G page", .pme_long_desc = "Data TLB references to 16GB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DTLB_MISS_16G], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DTLB_MISS_16G] }, [ POWER5p_PME_PM_FPU_STF ] = { .pme_name = "PM_FPU_STF", .pme_code = 0x202090, .pme_short_desc = "FPU executed store instruction", .pme_long_desc = "FPU has executed a store instruction. Combined Unit 0 + Unit 1.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU_STF], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU_STF] }, [ POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2SB_RCLD_DISP_FAIL_ADDR", .pme_code = 0x711c1, .pme_short_desc = "L2 slice B RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = "A Read/Claim dispatch for a load failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR] }, [ POWER5p_PME_PM_CMPLU_STALL_FPU ] = { .pme_name = "PM_CMPLU_STALL_FPU", .pme_code = 0x411098, .pme_short_desc = "Completion stall caused by FPU instruction", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a floating point instruction.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_CMPLU_STALL_FPU], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_CMPLU_STALL_FPU] }, [ POWER5p_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_minus1or2_CYC", .pme_code = 0x430e2, .pme_short_desc = "Cycles thread priority difference is -1 or -2", .pme_long_desc = "Cycles when this thread's priority is lower than the other thread's priority by 1 or 2.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC] }, [ POWER5p_PME_PM_GCT_NOSLOT_CYC ] = { .pme_name = "PM_GCT_NOSLOT_CYC", .pme_code = 0x100004, .pme_short_desc = "Cycles no GCT slot allocated", .pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GCT_NOSLOT_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GCT_NOSLOT_CYC] }, [ POWER5p_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { .pme_name = "PM_FXU0_BUSY_FXU1_IDLE", .pme_code = 0x300012, .pme_short_desc = "FXU0 busy FXU1 idle", .pme_long_desc = "FXU0 is busy while FXU1 was idle", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FXU0_BUSY_FXU1_IDLE], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FXU0_BUSY_FXU1_IDLE] }, [ POWER5p_PME_PM_PTEG_FROM_L35_SHR ] = { .pme_name = "PM_PTEG_FROM_L35_SHR", .pme_code = 0x18309e, .pme_short_desc = "PTEG loaded from L3.5 shared", .pme_long_desc = "A Page Table Entry was loaded into the TLB with shared (S) data from the L3 of a chip on the same module as this processor is located, due to a demand load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PTEG_FROM_L35_SHR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PTEG_FROM_L35_SHR] }, [ POWER5p_PME_PM_MRK_DTLB_REF_16G ] = { .pme_name = "PM_MRK_DTLB_REF_16G", .pme_code = 0x4c6086, .pme_short_desc = "Marked Data TLB reference for 16G page", .pme_long_desc = "Data TLB references by a marked instruction for 16GB pages.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DTLB_REF_16G], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DTLB_REF_16G] }, [ POWER5p_PME_PM_MRK_LSU_FLUSH_UST ] = { .pme_name = "PM_MRK_LSU_FLUSH_UST", .pme_code = 0x2810a8, .pme_short_desc = "Marked unaligned store flushes", .pme_long_desc = "A marked store was flushed because it was unaligned", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LSU_FLUSH_UST], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LSU_FLUSH_UST] }, [ POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L25_SHR", .pme_code = 0x1c7097, .pme_short_desc = "Marked data loaded from L2.5 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (T or SL) data from the L2 of a chip on the same module as this processor is located due to a marked load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L25_SHR] }, [ POWER5p_PME_PM_L3SA_HIT ] = { .pme_name = "PM_L3SA_HIT", .pme_code = 0x711c3, .pme_short_desc = "L3 slice A hits", .pme_long_desc = "Number of attempts made by this chip cores that resulted in an L3 hit. Reported per L3 slice", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SA_HIT], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SA_HIT] }, [ POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L35_SHR", .pme_code = 0x1c709e, .pme_short_desc = "Marked data loaded from L3.5 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (S) data from the L3 of a chip on the same module as this processor is located due to a marked load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR] }, [ POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2SB_RCST_DISP_FAIL_ADDR", .pme_code = 0x712c1, .pme_short_desc = "L2 slice B RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = "A Read/Claim dispatch for a store failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_ADDR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_ADDR] }, [ POWER5p_PME_PM_IERAT_XLATE_WR ] = { .pme_name = "PM_IERAT_XLATE_WR", .pme_code = 0x220e7, .pme_short_desc = "Translation written to ierat", .pme_long_desc = "An entry was written into the IERAT as a result of an IERAT miss. This event can be used to count IERAT misses. An ERAT miss that are later ignored will not be counted unless the ERAT is written before the instruction stream is changed.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_IERAT_XLATE_WR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_IERAT_XLATE_WR] }, [ POWER5p_PME_PM_L2SA_ST_REQ ] = { .pme_name = "PM_L2SA_ST_REQ", .pme_code = 0x723e0, .pme_short_desc = "L2 slice A store requests", .pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A, B, and C.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_ST_REQ], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_ST_REQ] }, [ POWER5p_PME_PM_INST_FROM_LMEM ] = { .pme_name = "PM_INST_FROM_LMEM", .pme_code = 0x222086, .pme_short_desc = "Instruction fetched from local memory", .pme_long_desc = "An instruction fetch group was fetched from memory attached to the same module this proccessor is located on. Fetch groups can contain up to 8 instructions", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_LMEM], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_LMEM] }, [ POWER5p_PME_PM_THRD_SEL_T1 ] = { .pme_name = "PM_THRD_SEL_T1", .pme_code = 0x410c1, .pme_short_desc = "Decode selected thread 1", .pme_long_desc = "Thread selection picked thread 1 for decode.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_SEL_T1], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_SEL_T1] }, [ POWER5p_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = { .pme_name = "PM_IC_DEMAND_L2_BR_REDIRECT", .pme_code = 0x230e1, .pme_short_desc = "L2 I cache demand request due to branch redirect", .pme_long_desc = "A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (either ALL mispredicted or Target).", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_IC_DEMAND_L2_BR_REDIRECT], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_IC_DEMAND_L2_BR_REDIRECT] }, [ POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L35_SHR_CYC", .pme_code = 0x2c70a6, .pme_short_desc = "Marked load latency from L3.5 shared", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L35_SHR_CYC] }, [ POWER5p_PME_PM_FPU0_1FLOP ] = { .pme_name = "PM_FPU0_1FLOP", .pme_code = 0xc3, .pme_short_desc = "FPU0 executed add", .pme_long_desc = " mult", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU0_1FLOP], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU0_1FLOP] }, [ POWER5p_PME_PM_PTEG_FROM_L2 ] = { .pme_name = "PM_PTEG_FROM_L2", .pme_code = 0x183087, .pme_short_desc = "PTEG loaded from L2", .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local L2 due to a demand load", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PTEG_FROM_L2], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PTEG_FROM_L2] }, [ POWER5p_PME_PM_MEM_PW_CMPL ] = { .pme_name = "PM_MEM_PW_CMPL", .pme_code = 0x724e6, .pme_short_desc = "Memory partial-write completed", .pme_long_desc = "Number of Partial Writes completed. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_PW_CMPL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_PW_CMPL] }, [ POWER5p_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_minus5or6_CYC", .pme_code = 0x430e0, .pme_short_desc = "Cycles thread priority difference is -5 or -6", .pme_long_desc = "Cycles when this thread's priority is lower than the other thread's priority by 5 or 6.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC] }, [ POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2SB_RCLD_DISP_FAIL_OTHER", .pme_code = 0x731e1, .pme_short_desc = "L2 slice B RC load dispatch attempt failed due to other reasons", .pme_long_desc = "A Read/Claim dispatch for a load failed for some reason other than Full or Collision conditions.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER] }, [ POWER5p_PME_PM_MRK_DTLB_MISS_4K ] = { .pme_name = "PM_MRK_DTLB_MISS_4K", .pme_code = 0x1c608d, .pme_short_desc = "Marked Data TLB misses for 4K page", .pme_long_desc = "Data TLB references to 4KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DTLB_MISS_4K], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DTLB_MISS_4K] }, [ POWER5p_PME_PM_FPU0_FIN ] = { .pme_name = "PM_FPU0_FIN", .pme_code = 0x10c3, .pme_short_desc = "FPU0 produced a result", .pme_long_desc = "FPU0 finished, produced a result. This only indicates finish, not completion. Floating Point Stores are included in this count but not Floating Point Loads.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU0_FIN], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU0_FIN] }, [ POWER5p_PME_PM_L3SC_SHR_INV ] = { .pme_name = "PM_L3SC_SHR_INV", .pme_code = 0x710c5, .pme_short_desc = "L3 slice C transition from shared to invalid", .pme_long_desc = "L3 snooper detects someone doing a store to a line that is Sx in this L3(i.e. invalidate hit SX and dispatched).", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SC_SHR_INV], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SC_SHR_INV] }, [ POWER5p_PME_PM_GRP_BR_REDIR ] = { .pme_name = "PM_GRP_BR_REDIR", .pme_code = 0x120e6, .pme_short_desc = "Group experienced branch redirect", .pme_long_desc = "Number of groups, counted at dispatch, that have encountered a branch redirect. Every group constructed from a fetch group that has been redirected will count.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GRP_BR_REDIR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GRP_BR_REDIR] }, [ POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL ] = { .pme_name = "PM_L2SC_RCLD_DISP_FAIL_RC_FULL", .pme_code = 0x721e2, .pme_short_desc = "L2 slice C RC load dispatch attempt failed due to all RC full", .pme_long_desc = "A Read/Claim dispatch for a load failed because all RC machines are busy.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL] }, [ POWER5p_PME_PM_MRK_LSU_FLUSH_SRQ ] = { .pme_name = "PM_MRK_LSU_FLUSH_SRQ", .pme_code = 0x481088, .pme_short_desc = "Marked SRQ lhs flushes", .pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LSU_FLUSH_SRQ], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LSU_FLUSH_SRQ] }, [ POWER5p_PME_PM_PTEG_FROM_L275_SHR ] = { .pme_name = "PM_PTEG_FROM_L275_SHR", .pme_code = 0x383097, .pme_short_desc = "PTEG loaded from L2.75 shared", .pme_long_desc = "A Page Table Entry was loaded into the TLB with shared (T) data from the L2 on a different module than this processor is located due to a demand load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PTEG_FROM_L275_SHR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PTEG_FROM_L275_SHR] }, [ POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL ] = { .pme_name = "PM_L2SB_RCLD_DISP_FAIL_RC_FULL", .pme_code = 0x721e1, .pme_short_desc = "L2 slice B RC load dispatch attempt failed due to all RC full", .pme_long_desc = "A Read/Claim dispatch for a load failed because all RC machines are busy.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL] }, [ POWER5p_PME_PM_SNOOP_RD_RETRY_WQ ] = { .pme_name = "PM_SNOOP_RD_RETRY_WQ", .pme_code = 0x715c6, .pme_short_desc = "Snoop read retry due to collision with active write queue", .pme_long_desc = "A snoop request for a read from memory was retried because it matched the cache line of an active write. The snoop request is retried and the active write is changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SNOOP_RD_RETRY_WQ], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SNOOP_RD_RETRY_WQ] }, [ POWER5p_PME_PM_FAB_DCLAIM_RETRIED ] = { .pme_name = "PM_FAB_DCLAIM_RETRIED", .pme_code = 0x730e7, .pme_short_desc = "dclaim retried", .pme_long_desc = "A DCLAIM command was retried. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_DCLAIM_RETRIED], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_DCLAIM_RETRIED] }, [ POWER5p_PME_PM_LSU0_NCLD ] = { .pme_name = "PM_LSU0_NCLD", .pme_code = 0xc50c1, .pme_short_desc = "LSU0 non-cacheable loads", .pme_long_desc = "A non-cacheable load was executed by unit 0.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU0_NCLD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU0_NCLD] }, [ POWER5p_PME_PM_LSU1_BUSY_REJECT ] = { .pme_name = "PM_LSU1_BUSY_REJECT", .pme_code = 0xc20e5, .pme_short_desc = "LSU1 busy due to reject", .pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU1_BUSY_REJECT], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU1_BUSY_REJECT] }, [ POWER5p_PME_PM_FXLS0_FULL_CYC ] = { .pme_name = "PM_FXLS0_FULL_CYC", .pme_code = 0x110c0, .pme_short_desc = "Cycles FXU0/LS0 queue full", .pme_long_desc = "The issue queue that feeds the Fixed Point unit 0 / Load Store Unit 0 is full. This condition will prevent dispatch groups from being dispatched. This event only indicates that the queue was full, not that dispatch was prevented.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FXLS0_FULL_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FXLS0_FULL_CYC] }, [ POWER5p_PME_PM_DTLB_REF_16M ] = { .pme_name = "PM_DTLB_REF_16M", .pme_code = 0x3c2086, .pme_short_desc = "Data TLB reference for 16M page", .pme_long_desc = "Data TLB references for 16MB pages. Includes hits + misses.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DTLB_REF_16M], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DTLB_REF_16M] }, [ POWER5p_PME_PM_FPU0_FEST ] = { .pme_name = "PM_FPU0_FEST", .pme_code = 0x10c2, .pme_short_desc = "FPU0 executed FEST instruction", .pme_long_desc = "FPU0 has executed an estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU0_FEST], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU0_FEST] }, [ POWER5p_PME_PM_GCT_USAGE_60to79_CYC ] = { .pme_name = "PM_GCT_USAGE_60to79_CYC", .pme_code = 0x20001f, .pme_short_desc = "Cycles GCT 60-79% full", .pme_long_desc = "Cycles when the Global Completion Table has between 60% and 70% of its slots used. The GCT has 20 entries shared between threads.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GCT_USAGE_60to79_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GCT_USAGE_60to79_CYC] }, [ POWER5p_PME_PM_DATA_FROM_L25_MOD ] = { .pme_name = "PM_DATA_FROM_L25_MOD", .pme_code = 0x2c3097, .pme_short_desc = "Data loaded from L2.5 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L2 of a chip on the same module as this processor is located due to a demand load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DATA_FROM_L25_MOD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DATA_FROM_L25_MOD] }, [ POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2SC_RCLD_DISP_FAIL_ADDR", .pme_code = 0x711c2, .pme_short_desc = "L2 slice C RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = "A Read/Claim dispatch for a load failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR] }, [ POWER5p_PME_PM_LSU0_REJECT_ERAT_MISS ] = { .pme_name = "PM_LSU0_REJECT_ERAT_MISS", .pme_code = 0xc40c3, .pme_short_desc = "LSU0 reject due to ERAT miss", .pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions due to an ERAT miss. Requests that miss the Derat are rejected and retried until the request hits in the Erat.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU0_REJECT_ERAT_MISS], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU0_REJECT_ERAT_MISS] }, [ POWER5p_PME_PM_DATA_FROM_L375_MOD ] = { .pme_name = "PM_DATA_FROM_L375_MOD", .pme_code = 0x1c30a7, .pme_short_desc = "Data loaded from L3.75 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L3 of a chip on the same module as this processor is located due to a demand load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DATA_FROM_L375_MOD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DATA_FROM_L375_MOD] }, [ POWER5p_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_LMQ_SRQ_EMPTY_CYC", .pme_code = 0x200015, .pme_short_desc = "Cycles LMQ and SRQ empty", .pme_long_desc = "Cycles when both the LMQ and SRQ are empty (LSU is idle)", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC] }, [ POWER5p_PME_PM_DTLB_MISS_64K ] = { .pme_name = "PM_DTLB_MISS_64K", .pme_code = 0x2c208d, .pme_short_desc = "Data TLB miss for 64K page", .pme_long_desc = "Data TLB references to 64KB pages that missed the TLB. Page size is determined at TLB reload time.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DTLB_MISS_64K], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DTLB_MISS_64K] }, [ POWER5p_PME_PM_LSU0_REJECT_RELOAD_CDF ] = { .pme_name = "PM_LSU0_REJECT_RELOAD_CDF", .pme_code = 0xc40c2, .pme_short_desc = "LSU0 reject due to reload CDF or tag update collision", .pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions because of Critical Data Forward. When critical data arrives from the storage system it is formatted and immediately forwarded, bypassing the data cache, to the destination register using the result bus. Any instruction the requires the result bus in the same cycle is rejected. Tag update rejects are caused when an instruction requires access to the Dcache directory or ERAT in the same system when they are being updated.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU0_REJECT_RELOAD_CDF], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU0_REJECT_RELOAD_CDF] }, [ POWER5p_PME_PM_0INST_FETCH ] = { .pme_name = "PM_0INST_FETCH", .pme_code = 0x42208d, .pme_short_desc = "No instructions fetched", .pme_long_desc = "No instructions were fetched this cycles (due to IFU hold, redirect, or icache miss)", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_0INST_FETCH], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_0INST_FETCH] }, [ POWER5p_PME_PM_LSU1_REJECT_RELOAD_CDF ] = { .pme_name = "PM_LSU1_REJECT_RELOAD_CDF", .pme_code = 0xc40c6, .pme_short_desc = "LSU1 reject due to reload CDF or tag update collision", .pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions because of Critical Data Forward. When critical data arrives from the storage system it is formatted and immediately forwarded, bypassing the data cache, to the destination register using the result bus. Any instruction the requires the result bus in the same cycle is rejected. Tag update rejects are caused when an instruction requires access to the Dcache directory or ERAT in the same system when they are being updated.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU1_REJECT_RELOAD_CDF], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU1_REJECT_RELOAD_CDF] }, [ POWER5p_PME_PM_MEM_WQ_DISP_Q0to7 ] = { .pme_name = "PM_MEM_WQ_DISP_Q0to7", .pme_code = 0x723e6, .pme_short_desc = "Memory write queue dispatched to queues 0-7", .pme_long_desc = "A memory operation was dispatched to a write queue in the range between 0 and 7. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_WQ_DISP_Q0to7], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_WQ_DISP_Q0to7] }, [ POWER5p_PME_PM_L1_PREF ] = { .pme_name = "PM_L1_PREF", .pme_code = 0xc70e7, .pme_short_desc = "L1 cache data prefetches", .pme_long_desc = "A request to prefetch data into the L1 was made", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L1_PREF], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L1_PREF] }, [ POWER5p_PME_PM_MRK_DATA_FROM_LMEM_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_LMEM_CYC", .pme_code = 0x4c70a0, .pme_short_desc = "Marked load latency from local memory", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_LMEM_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_LMEM_CYC] }, [ POWER5p_PME_PM_BRQ_FULL_CYC ] = { .pme_name = "PM_BRQ_FULL_CYC", .pme_code = 0x100c5, .pme_short_desc = "Cycles branch queue full", .pme_long_desc = "Cycles when the issue queue that feeds the branch unit is full. This condition will prevent dispatch groups from being dispatched. This event only indicates that the queue was full, not that dispatch was prevented.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_BRQ_FULL_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_BRQ_FULL_CYC] }, [ POWER5p_PME_PM_GRP_IC_MISS_NONSPEC ] = { .pme_name = "PM_GRP_IC_MISS_NONSPEC", .pme_code = 0x112099, .pme_short_desc = "Group experienced non-speculative I cache miss", .pme_long_desc = "Number of groups, counted at completion, that have encountered an instruction cache miss.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GRP_IC_MISS_NONSPEC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GRP_IC_MISS_NONSPEC] }, [ POWER5p_PME_PM_PTEG_FROM_L275_MOD ] = { .pme_name = "PM_PTEG_FROM_L275_MOD", .pme_code = 0x1830a3, .pme_short_desc = "PTEG loaded from L2.75 modified", .pme_long_desc = "A Page Table Entry was loaded into the TLB with modified (M) data from the L2 on a different module than this processor is located due to a demand load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PTEG_FROM_L275_MOD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PTEG_FROM_L275_MOD] }, [ POWER5p_PME_PM_MRK_LD_MISS_L1_LSU0 ] = { .pme_name = "PM_MRK_LD_MISS_L1_LSU0", .pme_code = 0x820e0, .pme_short_desc = "LSU0 marked L1 D cache load misses", .pme_long_desc = "Load references that miss the Level 1 Data cache, by LSU0.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LD_MISS_L1_LSU0], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LD_MISS_L1_LSU0] }, [ POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L375_SHR_CYC", .pme_code = 0x2c70a7, .pme_short_desc = "Marked load latency from L3.75 shared", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR_CYC] }, [ POWER5p_PME_PM_DATA_FROM_L3 ] = { .pme_name = "PM_DATA_FROM_L3", .pme_code = 0x1c308e, .pme_short_desc = "Data loaded from L3", .pme_long_desc = "The processor's Data Cache was reloaded from the local L3 due to a demand load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DATA_FROM_L3], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DATA_FROM_L3] }, [ POWER5p_PME_PM_INST_FROM_L2 ] = { .pme_name = "PM_INST_FROM_L2", .pme_code = 0x122086, .pme_short_desc = "Instruction fetched from L2", .pme_long_desc = "An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_L2], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_L2] }, [ POWER5p_PME_PM_LSU_FLUSH ] = { .pme_name = "PM_LSU_FLUSH", .pme_code = 0x110c5, .pme_short_desc = "Flush initiated by LSU", .pme_long_desc = "A flush was initiated by the Load Store Unit", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_FLUSH], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_FLUSH] }, [ POWER5p_PME_PM_PMC2_OVERFLOW ] = { .pme_name = "PM_PMC2_OVERFLOW", .pme_code = 0x30000a, .pme_short_desc = "PMC2 Overflow", .pme_long_desc = "Overflows from PMC2 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PMC2_OVERFLOW], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PMC2_OVERFLOW] }, [ POWER5p_PME_PM_FPU0_DENORM ] = { .pme_name = "PM_FPU0_DENORM", .pme_code = 0x20e0, .pme_short_desc = "FPU0 received denormalized data", .pme_long_desc = "FPU0 has encountered a denormalized operand.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU0_DENORM], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU0_DENORM] }, [ POWER5p_PME_PM_FPU1_FMOV_FEST ] = { .pme_name = "PM_FPU1_FMOV_FEST", .pme_code = 0x10c4, .pme_short_desc = "FPU1 executed FMOV or FEST instructions", .pme_long_desc = "FPU1 has executed a move kind of instruction or one of the estimate instructions. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU1_FMOV_FEST], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU1_FMOV_FEST] }, [ POWER5p_PME_PM_INST_FETCH_CYC ] = { .pme_name = "PM_INST_FETCH_CYC", .pme_code = 0x220e4, .pme_short_desc = "Cycles at least 1 instruction fetched", .pme_long_desc = "Cycles when at least one instruction was sent from the fetch unit to the decode unit.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FETCH_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FETCH_CYC] }, [ POWER5p_PME_PM_INST_DISP ] = { .pme_name = "PM_INST_DISP", .pme_code = 0x300009, .pme_short_desc = "Instructions dispatched", .pme_long_desc = "Number of PowerPC instructions successfully dispatched.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_DISP], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_DISP] }, [ POWER5p_PME_PM_LSU_LDF ] = { .pme_name = "PM_LSU_LDF", .pme_code = 0x1c50a8, .pme_short_desc = "LSU executed Floating Point load instruction", .pme_long_desc = "LSU executed Floating Point load instruction. Combined Unit 0 + 1.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_LDF], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_LDF] }, [ POWER5p_PME_PM_DATA_FROM_L25_SHR ] = { .pme_name = "PM_DATA_FROM_L25_SHR", .pme_code = 0x1c3097, .pme_short_desc = "Data loaded from L2.5 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (T or SL) data from the L2 of a chip on the same module as this processor is located due to a demand load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DATA_FROM_L25_SHR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DATA_FROM_L25_SHR] }, [ POWER5p_PME_PM_L1_DCACHE_RELOAD_VALID ] = { .pme_name = "PM_L1_DCACHE_RELOAD_VALID", .pme_code = 0xc30e4, .pme_short_desc = "L1 reload data source valid", .pme_long_desc = "The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L1_DCACHE_RELOAD_VALID], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L1_DCACHE_RELOAD_VALID] }, [ POWER5p_PME_PM_MEM_WQ_DISP_DCLAIM ] = { .pme_name = "PM_MEM_WQ_DISP_DCLAIM", .pme_code = 0x713c6, .pme_short_desc = "Memory write queue dispatched due to dclaim/flush", .pme_long_desc = "A memory dclaim or flush operation was dispatched to a write queue. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_WQ_DISP_DCLAIM], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_WQ_DISP_DCLAIM] }, [ POWER5p_PME_PM_MRK_GRP_ISSUED ] = { .pme_name = "PM_MRK_GRP_ISSUED", .pme_code = 0x100015, .pme_short_desc = "Marked group issued", .pme_long_desc = "A sampled instruction was issued.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_GRP_ISSUED], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_GRP_ISSUED] }, [ POWER5p_PME_PM_FPU_FULL_CYC ] = { .pme_name = "PM_FPU_FULL_CYC", .pme_code = 0x110090, .pme_short_desc = "Cycles FPU issue queue full", .pme_long_desc = "Cycles when one or both FPU issue queues are full. Combined Unit 0 + 1. Use with caution since this is the sum of cycles when Unit 0 was full plus Unit 1 full. It does not indicate when both units were full.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU_FULL_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU_FULL_CYC] }, [ POWER5p_PME_PM_INST_FROM_L35_MOD ] = { .pme_name = "PM_INST_FROM_L35_MOD", .pme_code = 0x22209d, .pme_short_desc = "Instruction fetched from L3.5 modified", .pme_long_desc = "An instruction fetch group was fetched with modified (M) data from the L3 of a chip on the same module as this processor is located. Fetch groups can contain up to 8 instructions", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_L35_MOD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_L35_MOD] }, [ POWER5p_PME_PM_FPU_FMA ] = { .pme_name = "PM_FPU_FMA", .pme_code = 0x200088, .pme_short_desc = "FPU executed multiply-add instruction", .pme_long_desc = "This signal is active for one cycle when FPU is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU_FMA], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU_FMA] }, [ POWER5p_PME_PM_THRD_PRIO_3_CYC ] = { .pme_name = "PM_THRD_PRIO_3_CYC", .pme_code = 0x420e2, .pme_short_desc = "Cycles thread running at priority level 3", .pme_long_desc = "Cycles this thread was running at priority level 3.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_PRIO_3_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_PRIO_3_CYC] }, [ POWER5p_PME_PM_MRK_CRU_FIN ] = { .pme_name = "PM_MRK_CRU_FIN", .pme_code = 0x400005, .pme_short_desc = "Marked instruction CRU processing finished", .pme_long_desc = "The Condition Register Unit finished a marked instruction. Instructions that finish may not necessary complete.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_CRU_FIN], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_CRU_FIN] }, [ POWER5p_PME_PM_SNOOP_WR_RETRY_WQ ] = { .pme_name = "PM_SNOOP_WR_RETRY_WQ", .pme_code = 0x716c6, .pme_short_desc = "Snoop write/dclaim retry due to collision with active write queue", .pme_long_desc = "A snoop request for a write or dclaim to memory was retried because it matched the cache line of an active write. The snoop request is retried and the active write is changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SNOOP_WR_RETRY_WQ], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SNOOP_WR_RETRY_WQ] }, [ POWER5p_PME_PM_CMPLU_STALL_REJECT ] = { .pme_name = "PM_CMPLU_STALL_REJECT", .pme_code = 0x41109a, .pme_short_desc = "Completion stall caused by reject", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a load/store reject. This is a subset of PM_CMPLU_STALL_LSU.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_CMPLU_STALL_REJECT], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_CMPLU_STALL_REJECT] }, [ POWER5p_PME_PM_MRK_FXU_FIN ] = { .pme_name = "PM_MRK_FXU_FIN", .pme_code = 0x200014, .pme_short_desc = "Marked instruction FXU processing finished", .pme_long_desc = "One of the Fixed Point Units finished a marked instruction. Instructions that finish may not necessary complete.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_FXU_FIN], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_FXU_FIN] }, [ POWER5p_PME_PM_LSU1_REJECT_ERAT_MISS ] = { .pme_name = "PM_LSU1_REJECT_ERAT_MISS", .pme_code = 0xc40c7, .pme_short_desc = "LSU1 reject due to ERAT miss", .pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions due to an ERAT miss. Requests that miss the Derat are rejected and retried until the request hits in the Erat.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU1_REJECT_ERAT_MISS], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU1_REJECT_ERAT_MISS] }, [ POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2SB_RCST_DISP_FAIL_OTHER", .pme_code = 0x732e1, .pme_short_desc = "L2 slice B RC store dispatch attempt failed due to other reasons", .pme_long_desc = "A Read/Claim dispatch for a store failed for some reason other than Full or Collision conditions. Rejected dispatches do not count because they have not yet been attempted.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_OTHER], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_OTHER] }, [ POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY ] = { .pme_name = "PM_L2SC_RC_DISP_FAIL_CO_BUSY", .pme_code = 0x703c2, .pme_short_desc = "L2 slice C RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy", .pme_long_desc = "A Read/Claim Dispatch was rejected at dispatch because the Castout Machine was busy. In the case of an RC starting up on a miss and the victim is valid, the CO machine must be available for the RC to process the access. If the CO is still busy working on an old castout, then the RC must not-ack the access if it is a miss(re-issued by the CIU). If it is a miss and the CO is available to process the castout, the RC will accept the access. Once the RC has finished, it can restart and process new accesses that result in a hit (or miss that doesn't need a CO) even though the CO is still processing a castout from a previous access.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY] }, [ POWER5p_PME_PM_PMC4_OVERFLOW ] = { .pme_name = "PM_PMC4_OVERFLOW", .pme_code = 0x10000a, .pme_short_desc = "PMC4 Overflow", .pme_long_desc = "Overflows from PMC4 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PMC4_OVERFLOW], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PMC4_OVERFLOW] }, [ POWER5p_PME_PM_L3SA_SNOOP_RETRY ] = { .pme_name = "PM_L3SA_SNOOP_RETRY", .pme_code = 0x731e3, .pme_short_desc = "L3 slice A snoop retries", .pme_long_desc = "Number of times an L3 retried a snoop because it got two in at the same time (one on snp_a, one on snp_b)", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SA_SNOOP_RETRY], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SA_SNOOP_RETRY] }, [ POWER5p_PME_PM_PTEG_FROM_L35_MOD ] = { .pme_name = "PM_PTEG_FROM_L35_MOD", .pme_code = 0x28309e, .pme_short_desc = "PTEG loaded from L3.5 modified", .pme_long_desc = "A Page Table Entry was loaded into the TLB with modified (M) data from the L3 of a chip on the same module as this processor is located, due to a demand load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PTEG_FROM_L35_MOD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PTEG_FROM_L35_MOD] }, [ POWER5p_PME_PM_INST_FROM_L25_MOD ] = { .pme_name = "PM_INST_FROM_L25_MOD", .pme_code = 0x222096, .pme_short_desc = "Instruction fetched from L2.5 modified", .pme_long_desc = "An instruction fetch group was fetched with modified (M) data from the L2 of a chip on the same module as this processor is located. Fetch groups can contain up to 8 instructions.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_L25_MOD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_L25_MOD] }, [ POWER5p_PME_PM_THRD_SMT_HANG ] = { .pme_name = "PM_THRD_SMT_HANG", .pme_code = 0x330e7, .pme_short_desc = "SMT hang detected", .pme_long_desc = "A hung thread was detected", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_SMT_HANG], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_SMT_HANG] }, [ POWER5p_PME_PM_CMPLU_STALL_ERAT_MISS ] = { .pme_name = "PM_CMPLU_STALL_ERAT_MISS", .pme_code = 0x41109b, .pme_short_desc = "Completion stall caused by ERAT miss", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered an ERAT miss. This is a subset of PM_CMPLU_STALL_REJECT.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_CMPLU_STALL_ERAT_MISS], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_CMPLU_STALL_ERAT_MISS] }, [ POWER5p_PME_PM_L3SA_MOD_TAG ] = { .pme_name = "PM_L3SA_MOD_TAG", .pme_code = 0x720e3, .pme_short_desc = "L3 slice A transition from modified to TAG", .pme_long_desc = "L3 snooper detects someone doing a read to a line that is truly M in this L3(i.e. L3 going M->T or M->I(go_Mu case) Mu|Me are not included since they are formed due to a prev read op). Tx is not included since it is considered shared at this point.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SA_MOD_TAG], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SA_MOD_TAG] }, [ POWER5p_PME_PM_INST_FROM_L2MISS ] = { .pme_name = "PM_INST_FROM_L2MISS", .pme_code = 0x12209b, .pme_short_desc = "Instruction fetched missed L2", .pme_long_desc = "An instruction fetch group was fetched from beyond the local L2.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_L2MISS], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_L2MISS] }, [ POWER5p_PME_PM_FLUSH_SYNC ] = { .pme_name = "PM_FLUSH_SYNC", .pme_code = 0x330e1, .pme_short_desc = "Flush caused by sync", .pme_long_desc = "This thread has been flushed at dispatch due to a sync, lwsync, ptesync, or tlbsync instruction. This allows the other thread to have more machine resources for it to make progress until the sync finishes.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FLUSH_SYNC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FLUSH_SYNC] }, [ POWER5p_PME_PM_MRK_GRP_DISP ] = { .pme_name = "PM_MRK_GRP_DISP", .pme_code = 0x100002, .pme_short_desc = "Marked group dispatched", .pme_long_desc = "A group containing a sampled instruction was dispatched", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_GRP_DISP], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_GRP_DISP] }, [ POWER5p_PME_PM_MEM_RQ_DISP_Q8to11 ] = { .pme_name = "PM_MEM_RQ_DISP_Q8to11", .pme_code = 0x722e6, .pme_short_desc = "Memory read queue dispatched to queues 8-11", .pme_long_desc = "A memory operation was dispatched to read queue 8,9,10 or 11. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_RQ_DISP_Q8to11], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_RQ_DISP_Q8to11] }, [ POWER5p_PME_PM_L2SC_ST_HIT ] = { .pme_name = "PM_L2SC_ST_HIT", .pme_code = 0x733e2, .pme_short_desc = "L2 slice C store hits", .pme_long_desc = "A store request made from the core hit in the L2 directory. The event is provided on each of the three slices A, B, and C.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_ST_HIT], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_ST_HIT] }, [ POWER5p_PME_PM_L2SB_MOD_TAG ] = { .pme_name = "PM_L2SB_MOD_TAG", .pme_code = 0x720e1, .pme_short_desc = "L2 slice B transition from modified to tagged", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_MOD_TAG], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_MOD_TAG] }, [ POWER5p_PME_PM_CLB_EMPTY_CYC ] = { .pme_name = "PM_CLB_EMPTY_CYC", .pme_code = 0x410c6, .pme_short_desc = "Cycles CLB empty", .pme_long_desc = "Cycles when both thread's CLB is completely empty.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_CLB_EMPTY_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_CLB_EMPTY_CYC] }, [ POWER5p_PME_PM_L2SB_ST_HIT ] = { .pme_name = "PM_L2SB_ST_HIT", .pme_code = 0x733e1, .pme_short_desc = "L2 slice B store hits", .pme_long_desc = "A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A, B and C.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_ST_HIT], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_ST_HIT] }, [ POWER5p_PME_PM_MEM_NONSPEC_RD_CANCEL ] = { .pme_name = "PM_MEM_NONSPEC_RD_CANCEL", .pme_code = 0x711c6, .pme_short_desc = "Non speculative memory read cancelled", .pme_long_desc = "A non-speculative read was cancelled because the combined response indicated it was sourced from aother L2 or L3. This event is sent from the Memory Controller clock domain and must be scaled accordingly", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_NONSPEC_RD_CANCEL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_NONSPEC_RD_CANCEL] }, [ POWER5p_PME_PM_BR_PRED_CR_TA ] = { .pme_name = "PM_BR_PRED_CR_TA", .pme_code = 0x423087, .pme_short_desc = "A conditional branch was predicted", .pme_long_desc = " CR and target prediction", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_BR_PRED_CR_TA], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_BR_PRED_CR_TA] }, [ POWER5p_PME_PM_MRK_LSU0_FLUSH_SRQ ] = { .pme_name = "PM_MRK_LSU0_FLUSH_SRQ", .pme_code = 0x810c3, .pme_short_desc = "LSU0 marked SRQ lhs flushes", .pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LSU0_FLUSH_SRQ], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LSU0_FLUSH_SRQ] }, [ POWER5p_PME_PM_MRK_LSU_FLUSH_ULD ] = { .pme_name = "PM_MRK_LSU_FLUSH_ULD", .pme_code = 0x1810a8, .pme_short_desc = "Marked unaligned load flushes", .pme_long_desc = "A marked load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LSU_FLUSH_ULD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LSU_FLUSH_ULD] }, [ POWER5p_PME_PM_INST_DISP_ATTEMPT ] = { .pme_name = "PM_INST_DISP_ATTEMPT", .pme_code = 0x120e1, .pme_short_desc = "Instructions dispatch attempted", .pme_long_desc = "Number of PowerPC Instructions dispatched (attempted, not filtered by success.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_DISP_ATTEMPT], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_DISP_ATTEMPT] }, [ POWER5p_PME_PM_INST_FROM_RMEM ] = { .pme_name = "PM_INST_FROM_RMEM", .pme_code = 0x422086, .pme_short_desc = "Instruction fetched from remote memory", .pme_long_desc = "An instruction fetch group was fetched from memory attached to a different module than this proccessor is located on. Fetch groups can contain up to 8 instructions", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_RMEM], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_RMEM] }, [ POWER5p_PME_PM_ST_REF_L1_LSU0 ] = { .pme_name = "PM_ST_REF_L1_LSU0", .pme_code = 0xc10c1, .pme_short_desc = "LSU0 L1 D cache store references", .pme_long_desc = "Store references to the Data Cache by LSU0.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_ST_REF_L1_LSU0], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_ST_REF_L1_LSU0] }, [ POWER5p_PME_PM_LSU0_DERAT_MISS ] = { .pme_name = "PM_LSU0_DERAT_MISS", .pme_code = 0x800c2, .pme_short_desc = "LSU0 DERAT misses", .pme_long_desc = "Total D-ERAT Misses by LSU0. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU0_DERAT_MISS], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU0_DERAT_MISS] }, [ POWER5p_PME_PM_FPU_STALL3 ] = { .pme_name = "PM_FPU_STALL3", .pme_code = 0x202088, .pme_short_desc = "FPU stalled in pipe3", .pme_long_desc = "FPU has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. Combined Unit 0 + Unit 1.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU_STALL3], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU_STALL3] }, [ POWER5p_PME_PM_L2SB_RCLD_DISP ] = { .pme_name = "PM_L2SB_RCLD_DISP", .pme_code = 0x701c1, .pme_short_desc = "L2 slice B RC load dispatch attempt", .pme_long_desc = "A Read/Claim dispatch for a Load was attempted", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_RCLD_DISP], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_RCLD_DISP] }, [ POWER5p_PME_PM_BR_PRED_CR ] = { .pme_name = "PM_BR_PRED_CR", .pme_code = 0x230e2, .pme_short_desc = "A conditional branch was predicted", .pme_long_desc = " CR prediction", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_BR_PRED_CR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_BR_PRED_CR] }, [ POWER5p_PME_PM_MRK_DATA_FROM_L2 ] = { .pme_name = "PM_MRK_DATA_FROM_L2", .pme_code = 0x1c7087, .pme_short_desc = "Marked data loaded from L2", .pme_long_desc = "The processor's Data Cache was reloaded from the local L2 due to a marked load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L2], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L2] }, [ POWER5p_PME_PM_LSU0_FLUSH_SRQ ] = { .pme_name = "PM_LSU0_FLUSH_SRQ", .pme_code = 0xc00c3, .pme_short_desc = "LSU0 SRQ lhs flushes", .pme_long_desc = "A store was flushed by unit 0 because younger load hits and older store that is already in the SRQ or in the same group.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU0_FLUSH_SRQ], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU0_FLUSH_SRQ] }, [ POWER5p_PME_PM_FAB_PNtoNN_DIRECT ] = { .pme_name = "PM_FAB_PNtoNN_DIRECT", .pme_code = 0x703c7, .pme_short_desc = "PN to NN beat went straight to its destination", .pme_long_desc = "Fabric Data beats that the base chip takes the inbound PN data and passes it through to the outbound NN bus without going into a sidecar. The signal is delivered at FBC speed and the count must be scaled.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_PNtoNN_DIRECT], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_PNtoNN_DIRECT] }, [ POWER5p_PME_PM_IOPS_CMPL ] = { .pme_name = "PM_IOPS_CMPL", .pme_code = 0x1, .pme_short_desc = "Internal operations completed", .pme_long_desc = "Number of internal operations that completed.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_IOPS_CMPL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_IOPS_CMPL] }, [ POWER5p_PME_PM_L2SA_RCST_DISP ] = { .pme_name = "PM_L2SA_RCST_DISP", .pme_code = 0x702c0, .pme_short_desc = "L2 slice A RC store dispatch attempt", .pme_long_desc = "A Read/Claim dispatch for a Store was attempted.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_RCST_DISP], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_RCST_DISP] }, [ POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2SA_RCST_DISP_FAIL_OTHER", .pme_code = 0x732e0, .pme_short_desc = "L2 slice A RC store dispatch attempt failed due to other reasons", .pme_long_desc = "A Read/Claim dispatch for a store failed for some reason other than Full or Collision conditions. Rejected dispatches do not count because they have not yet been attempted.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_OTHER], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_RCST_DISP_FAIL_OTHER] }, [ POWER5p_PME_PM_L2SC_SHR_INV ] = { .pme_name = "PM_L2SC_SHR_INV", .pme_code = 0x710c2, .pme_short_desc = "L2 slice C transition from shared to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A, B, and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_SHR_INV], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_SHR_INV] }, [ POWER5p_PME_PM_SNOOP_RETRY_AB_COLLISION ] = { .pme_name = "PM_SNOOP_RETRY_AB_COLLISION", .pme_code = 0x735e6, .pme_short_desc = "Snoop retry due to a b collision", .pme_long_desc = "Snoop retry due to a b collision", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SNOOP_RETRY_AB_COLLISION], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SNOOP_RETRY_AB_COLLISION] }, [ POWER5p_PME_PM_FAB_PNtoVN_SIDECAR ] = { .pme_name = "PM_FAB_PNtoVN_SIDECAR", .pme_code = 0x733e7, .pme_short_desc = "PN to VN beat went to sidecar first", .pme_long_desc = "Fabric data beats that the base chip takes the inbound PN data and forwards it on to the outbound VN data bus after going into a sidecar first. The signal is delivered at FBC speed and the count must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_PNtoVN_SIDECAR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_PNtoVN_SIDECAR] }, [ POWER5p_PME_PM_LSU0_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU0_REJECT_LMQ_FULL", .pme_code = 0xc40c1, .pme_short_desc = "LSU0 reject due to LMQ full or missed data coming", .pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU0_REJECT_LMQ_FULL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU0_REJECT_LMQ_FULL] }, [ POWER5p_PME_PM_LSU_LMQ_S0_ALLOC ] = { .pme_name = "PM_LSU_LMQ_S0_ALLOC", .pme_code = 0xc30e6, .pme_short_desc = "LMQ slot 0 allocated", .pme_long_desc = "The first entry in the LMQ was allocated.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_LMQ_S0_ALLOC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_LMQ_S0_ALLOC] }, [ POWER5p_PME_PM_SNOOP_PW_RETRY_RQ ] = { .pme_name = "PM_SNOOP_PW_RETRY_RQ", .pme_code = 0x707c6, .pme_short_desc = "Snoop partial-write retry due to collision with active read queue", .pme_long_desc = "A snoop request for a partial write to memory was retried because it matched the cache line of an active read. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SNOOP_PW_RETRY_RQ], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SNOOP_PW_RETRY_RQ] }, [ POWER5p_PME_PM_DTLB_REF ] = { .pme_name = "PM_DTLB_REF", .pme_code = 0xc20e4, .pme_short_desc = "Data TLB references", .pme_long_desc = "Total number of Data TLB references for all page sizes. Page size is determined at TLB reload time.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DTLB_REF], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DTLB_REF] }, [ POWER5p_PME_PM_PTEG_FROM_L3 ] = { .pme_name = "PM_PTEG_FROM_L3", .pme_code = 0x18308e, .pme_short_desc = "PTEG loaded from L3", .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local L3 due to a demand load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PTEG_FROM_L3], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PTEG_FROM_L3] }, [ POWER5p_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY ] = { .pme_name = "PM_FAB_M1toVNorNN_SIDECAR_EMPTY", .pme_code = 0x712c7, .pme_short_desc = "M1 to VN/NN sidecar empty", .pme_long_desc = "Fabric cycles when the Minus-1 jump sidecar (sidecars for mcm to mcm data transfer) is empty. The signal is delivered at FBC speed and the count must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY] }, [ POWER5p_PME_PM_LSU_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_SRQ_EMPTY_CYC", .pme_code = 0x400015, .pme_short_desc = "Cycles SRQ empty", .pme_long_desc = "Cycles the Store Request Queue is empty", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_SRQ_EMPTY_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_SRQ_EMPTY_CYC] }, [ POWER5p_PME_PM_FPU1_STF ] = { .pme_name = "PM_FPU1_STF", .pme_code = 0x20e6, .pme_short_desc = "FPU1 executed store instruction", .pme_long_desc = "FPU1 has executed a Floating Point Store instruction.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU1_STF], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU1_STF] }, [ POWER5p_PME_PM_LSU_LMQ_S0_VALID ] = { .pme_name = "PM_LSU_LMQ_S0_VALID", .pme_code = 0xc30e5, .pme_short_desc = "LMQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle when the first entry in the LMQ is valid. The LMQ had eight entries that are allocated FIFO", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_LMQ_S0_VALID], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_LMQ_S0_VALID] }, [ POWER5p_PME_PM_GCT_USAGE_00to59_CYC ] = { .pme_name = "PM_GCT_USAGE_00to59_CYC", .pme_code = 0x10001f, .pme_short_desc = "Cycles GCT less than 60% full", .pme_long_desc = "Cycles when the Global Completion Table has fewer than 60% of its slots used. The GCT has 20 entries shared between threads.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GCT_USAGE_00to59_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GCT_USAGE_00to59_CYC] }, [ POWER5p_PME_PM_FPU_FMOV_FEST ] = { .pme_name = "PM_FPU_FMOV_FEST", .pme_code = 0x301088, .pme_short_desc = "FPU executed FMOV or FEST instructions", .pme_long_desc = "The floating point unit has executed a move kind of instruction or one of the estimate instructions. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ.. Combined Unit 0 + Unit 1.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU_FMOV_FEST], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU_FMOV_FEST] }, [ POWER5p_PME_PM_DATA_FROM_L2MISS ] = { .pme_name = "PM_DATA_FROM_L2MISS", .pme_code = 0x3c309b, .pme_short_desc = "Data loaded missed L2", .pme_long_desc = "The processor's Data Cache was reloaded but not from the local L2.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DATA_FROM_L2MISS], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DATA_FROM_L2MISS] }, [ POWER5p_PME_PM_XER_MAP_FULL_CYC ] = { .pme_name = "PM_XER_MAP_FULL_CYC", .pme_code = 0x100c2, .pme_short_desc = "Cycles XER mapper full", .pme_long_desc = "The XER mapper cannot accept any more groups. This condition will prevent dispatch groups from being dispatched. This event only indicates that the mapper was full, not that dispatch was prevented.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_XER_MAP_FULL_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_XER_MAP_FULL_CYC] }, [ POWER5p_PME_PM_GRP_DISP_BLK_SB_CYC ] = { .pme_name = "PM_GRP_DISP_BLK_SB_CYC", .pme_code = 0x130e1, .pme_short_desc = "Cycles group dispatch blocked by scoreboard", .pme_long_desc = "A scoreboard operation on a non-renamed resource has blocked dispatch.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GRP_DISP_BLK_SB_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GRP_DISP_BLK_SB_CYC] }, [ POWER5p_PME_PM_FLUSH_SB ] = { .pme_name = "PM_FLUSH_SB", .pme_code = 0x330e2, .pme_short_desc = "Flush caused by scoreboard operation", .pme_long_desc = "This thread has been flushed at dispatch because its scoreboard bit is set indicating that a non-renamed resource is being updated. This allows the other thread to have more machine resources for it to make progress while this thread is stalled.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FLUSH_SB], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FLUSH_SB] }, [ POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L375_SHR", .pme_code = 0x3c709e, .pme_short_desc = "Marked data loaded from L3.75 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (S) data from the L3 of a chip on a different module than this processor is located due to a marked load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L375_SHR] }, [ POWER5p_PME_PM_MRK_GRP_CMPL ] = { .pme_name = "PM_MRK_GRP_CMPL", .pme_code = 0x400013, .pme_short_desc = "Marked group completed", .pme_long_desc = "A group containing a sampled instruction completed. Microcoded instructions that span multiple groups will generate this event once per group.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_GRP_CMPL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_GRP_CMPL] }, [ POWER5p_PME_PM_SUSPENDED ] = { .pme_name = "PM_SUSPENDED", .pme_code = 0x0, .pme_short_desc = "Suspended", .pme_long_desc = "The counter is suspended (does not count).", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SUSPENDED], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SUSPENDED] }, [ POWER5p_PME_PM_SNOOP_RD_RETRY_QFULL ] = { .pme_name = "PM_SNOOP_RD_RETRY_QFULL", .pme_code = 0x700c6, .pme_short_desc = "Snoop read retry due to read queue full", .pme_long_desc = "A snoop request for a read from memory was retried because the read queues were full. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_SNOOP_RD_RETRY_QFULL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_SNOOP_RD_RETRY_QFULL] }, [ POWER5p_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC ] = { .pme_name = "PM_GRP_IC_MISS_BR_REDIR_NONSPEC", .pme_code = 0x120e5, .pme_short_desc = "Group experienced non-speculative I cache miss or branch redirect", .pme_long_desc = "Group experienced non-speculative I cache miss or branch redirect", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC] }, [ POWER5p_PME_PM_DATA_FROM_L35_SHR ] = { .pme_name = "PM_DATA_FROM_L35_SHR", .pme_code = 0x1c309e, .pme_short_desc = "Data loaded from L3.5 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (S) data from the L3 of a chip on the same module as this processor is located due to a demand load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DATA_FROM_L35_SHR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DATA_FROM_L35_SHR] }, [ POWER5p_PME_PM_L3SB_MOD_INV ] = { .pme_name = "PM_L3SB_MOD_INV", .pme_code = 0x730e4, .pme_short_desc = "L3 slice B transition from modified to invalid", .pme_long_desc = "L3 snooper detects someone doing a store to a line that is truly M in this L3 (i.e. L3 going M=>I). Mu|Me are not included since they are formed due to a prev read op. Tx is not included since it is considered shared at this point.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SB_MOD_INV], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SB_MOD_INV] }, [ POWER5p_PME_PM_STCX_FAIL ] = { .pme_name = "PM_STCX_FAIL", .pme_code = 0x820e1, .pme_short_desc = "STCX failed", .pme_long_desc = "A stcx (stwcx or stdcx) failed", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_STCX_FAIL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_STCX_FAIL] }, [ POWER5p_PME_PM_LD_MISS_L1_LSU1 ] = { .pme_name = "PM_LD_MISS_L1_LSU1", .pme_code = 0xc10c5, .pme_short_desc = "LSU1 L1 D cache load misses", .pme_long_desc = "Load references that miss the Level 1 Data cache, by unit 1.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LD_MISS_L1_LSU1], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LD_MISS_L1_LSU1] }, [ POWER5p_PME_PM_GRP_DISP ] = { .pme_name = "PM_GRP_DISP", .pme_code = 0x200002, .pme_short_desc = "Group dispatches", .pme_long_desc = "A group was dispatched", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_GRP_DISP], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_GRP_DISP] }, [ POWER5p_PME_PM_DC_PREF_DST ] = { .pme_name = "PM_DC_PREF_DST", .pme_code = 0x830e6, .pme_short_desc = "DST (Data Stream Touch) stream start", .pme_long_desc = "A prefetch stream was started using the DST instruction.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DC_PREF_DST], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DC_PREF_DST] }, [ POWER5p_PME_PM_FPU1_DENORM ] = { .pme_name = "PM_FPU1_DENORM", .pme_code = 0x20e4, .pme_short_desc = "FPU1 received denormalized data", .pme_long_desc = "FPU1 has encountered a denormalized operand.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU1_DENORM], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU1_DENORM] }, [ POWER5p_PME_PM_FPU0_FPSCR ] = { .pme_name = "PM_FPU0_FPSCR", .pme_code = 0x30e0, .pme_short_desc = "FPU0 executed FPSCR instruction", .pme_long_desc = "FPU0 has executed FPSCR move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*, mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU0_FPSCR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU0_FPSCR] }, [ POWER5p_PME_PM_DATA_FROM_L2 ] = { .pme_name = "PM_DATA_FROM_L2", .pme_code = 0x1c3087, .pme_short_desc = "Data loaded from L2", .pme_long_desc = "The processor's Data Cache was reloaded from the local L2 due to a demand load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DATA_FROM_L2], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DATA_FROM_L2] }, [ POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2SA_RCLD_DISP_FAIL_ADDR", .pme_code = 0x711c0, .pme_short_desc = "L2 slice A RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = "A Read/Claim dispatch for a load failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR] }, [ POWER5p_PME_PM_FPU_1FLOP ] = { .pme_name = "PM_FPU_1FLOP", .pme_code = 0x100090, .pme_short_desc = "FPU executed one flop instruction", .pme_long_desc = "The floating point unit has executed an add, mult, sub, compare, fsel, fneg, fabs, fnabs, fres, or frsqrte kind of instruction. These are single FLOP operations.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU_1FLOP], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU_1FLOP] }, [ POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2SC_RCLD_DISP_FAIL_OTHER", .pme_code = 0x731e2, .pme_short_desc = "L2 slice C RC load dispatch attempt failed due to other reasons", .pme_long_desc = "A Read/Claim dispatch for a load failed for some reason other than Full or Collision conditions.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER] }, [ POWER5p_PME_PM_FPU0_FSQRT ] = { .pme_name = "PM_FPU0_FSQRT", .pme_code = 0xc2, .pme_short_desc = "FPU0 executed FSQRT instruction", .pme_long_desc = "FPU0 has executed a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU0_FSQRT], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU0_FSQRT] }, [ POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL ] = { .pme_name = "PM_L2SC_RCST_DISP_FAIL_RC_FULL", .pme_code = 0x722e1, .pme_short_desc = "L2 slice C RC store dispatch attempt failed due to all RC full", .pme_long_desc = "A Read/Claim dispatch for a store failed because all RC machines are busy.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL] }, [ POWER5p_PME_PM_LD_REF_L1 ] = { .pme_name = "PM_LD_REF_L1", .pme_code = 0x1c10a8, .pme_short_desc = "L1 D cache load references", .pme_long_desc = "Load references to the Level 1 Data Cache. Combined unit 0 + 1.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LD_REF_L1], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LD_REF_L1] }, [ POWER5p_PME_PM_INST_FROM_L1 ] = { .pme_name = "PM_INST_FROM_L1", .pme_code = 0x22208d, .pme_short_desc = "Instruction fetched from L1", .pme_long_desc = "An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_L1], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_L1] }, [ POWER5p_PME_PM_TLBIE_HELD ] = { .pme_name = "PM_TLBIE_HELD", .pme_code = 0x130e4, .pme_short_desc = "TLBIE held at dispatch", .pme_long_desc = "Cycles a TLBIE instruction was held at dispatch.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_TLBIE_HELD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_TLBIE_HELD] }, [ POWER5p_PME_PM_DC_PREF_OUT_OF_STREAMS ] = { .pme_name = "PM_DC_PREF_OUT_OF_STREAMS", .pme_code = 0xc50c2, .pme_short_desc = "D cache out of prefetch streams", .pme_long_desc = "A new prefetch stream was detected but no more stream entries were available.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DC_PREF_OUT_OF_STREAMS], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DC_PREF_OUT_OF_STREAMS] }, [ POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L25_MOD_CYC", .pme_code = 0x4c70a2, .pme_short_desc = "Marked load latency from L2.5 modified", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L25_MOD_CYC] }, [ POWER5p_PME_PM_MRK_LSU1_FLUSH_SRQ ] = { .pme_name = "PM_MRK_LSU1_FLUSH_SRQ", .pme_code = 0x810c7, .pme_short_desc = "LSU1 marked SRQ lhs flushes", .pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LSU1_FLUSH_SRQ], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LSU1_FLUSH_SRQ] }, [ POWER5p_PME_PM_MEM_RQ_DISP_Q0to3 ] = { .pme_name = "PM_MEM_RQ_DISP_Q0to3", .pme_code = 0x702c6, .pme_short_desc = "Memory read queue dispatched to queues 0-3", .pme_long_desc = "A memory operation was dispatched to read queue 0,1,2, or 3. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MEM_RQ_DISP_Q0to3], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MEM_RQ_DISP_Q0to3] }, [ POWER5p_PME_PM_ST_REF_L1_LSU1 ] = { .pme_name = "PM_ST_REF_L1_LSU1", .pme_code = 0xc10c4, .pme_short_desc = "LSU1 L1 D cache store references", .pme_long_desc = "Store references to the Data Cache by LSU1.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_ST_REF_L1_LSU1], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_ST_REF_L1_LSU1] }, [ POWER5p_PME_PM_MRK_LD_MISS_L1 ] = { .pme_name = "PM_MRK_LD_MISS_L1", .pme_code = 0x182088, .pme_short_desc = "Marked L1 D cache load misses", .pme_long_desc = "Marked L1 D cache load misses", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LD_MISS_L1], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LD_MISS_L1] }, [ POWER5p_PME_PM_L1_WRITE_CYC ] = { .pme_name = "PM_L1_WRITE_CYC", .pme_code = 0x230e7, .pme_short_desc = "Cycles writing to instruction L1", .pme_long_desc = "Cycles that a cache line was written to the instruction cache.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L1_WRITE_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L1_WRITE_CYC] }, [ POWER5p_PME_PM_L2SC_ST_REQ ] = { .pme_name = "PM_L2SC_ST_REQ", .pme_code = 0x723e2, .pme_short_desc = "L2 slice C store requests", .pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A, B, and C.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_ST_REQ], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_ST_REQ] }, [ POWER5p_PME_PM_CMPLU_STALL_FDIV ] = { .pme_name = "PM_CMPLU_STALL_FDIV", .pme_code = 0x21109b, .pme_short_desc = "Completion stall caused by FDIV or FQRT instruction", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a floating point divide or square root instruction. This is a subset of PM_CMPLU_STALL_FPU.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_CMPLU_STALL_FDIV], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_CMPLU_STALL_FDIV] }, [ POWER5p_PME_PM_THRD_SEL_OVER_CLB_EMPTY ] = { .pme_name = "PM_THRD_SEL_OVER_CLB_EMPTY", .pme_code = 0x410c2, .pme_short_desc = "Thread selection overrides caused by CLB empty", .pme_long_desc = "Thread selection was overridden because one thread's CLB was empty.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_SEL_OVER_CLB_EMPTY], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_SEL_OVER_CLB_EMPTY] }, [ POWER5p_PME_PM_BR_MPRED_CR ] = { .pme_name = "PM_BR_MPRED_CR", .pme_code = 0x230e5, .pme_short_desc = "Branch mispredictions due to CR bit setting", .pme_long_desc = "A conditional branch instruction was incorrectly predicted as taken or not taken. The branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_BR_MPRED_CR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_BR_MPRED_CR] }, [ POWER5p_PME_PM_L3SB_MOD_TAG ] = { .pme_name = "PM_L3SB_MOD_TAG", .pme_code = 0x720e4, .pme_short_desc = "L3 slice B transition from modified to TAG", .pme_long_desc = "L3 snooper detects someone doing a read to a line that is truly M in this L3(i.e. L3 going M->T or M->I(go_Mu case); Mu|Me are not included since they are formed due to a prev read op). Tx is not included since it is considered shared at this point.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SB_MOD_TAG], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SB_MOD_TAG] }, [ POWER5p_PME_PM_MRK_DATA_FROM_L2MISS ] = { .pme_name = "PM_MRK_DATA_FROM_L2MISS", .pme_code = 0x3c709b, .pme_short_desc = "Marked data loaded missed L2", .pme_long_desc = "DL1 was reloaded from beyond L2 due to a marked demand load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_DATA_FROM_L2MISS], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_DATA_FROM_L2MISS] }, [ POWER5p_PME_PM_LSU_REJECT_SRQ ] = { .pme_name = "PM_LSU_REJECT_SRQ", .pme_code = 0x1c4088, .pme_short_desc = "LSU SRQ lhs rejects", .pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions because of Load Hit Store conditions. Loads are rejected when data is needed from a previous store instruction but store forwarding is not possible because the data is not fully contained in the Store Data Queue or is not yet available in the Store Data Queue. Combined Unit 0 + 1.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_REJECT_SRQ], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_REJECT_SRQ] }, [ POWER5p_PME_PM_LD_MISS_L1 ] = { .pme_name = "PM_LD_MISS_L1", .pme_code = 0x3c1088, .pme_short_desc = "L1 D cache load misses", .pme_long_desc = "Load references that miss the Level 1 Data cache. Combined unit 0 + 1.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LD_MISS_L1], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LD_MISS_L1] }, [ POWER5p_PME_PM_INST_FROM_PREF ] = { .pme_name = "PM_INST_FROM_PREF", .pme_code = 0x32208d, .pme_short_desc = "Instruction fetched from prefetch", .pme_long_desc = "An instruction fetch group was fetched from the prefetch buffer. Fetch groups can contain up to 8 instructions", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_INST_FROM_PREF], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_INST_FROM_PREF] }, [ POWER5p_PME_PM_STCX_PASS ] = { .pme_name = "PM_STCX_PASS", .pme_code = 0x820e5, .pme_short_desc = "Stcx passes", .pme_long_desc = "A stcx (stwcx or stdcx) instruction was successful", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_STCX_PASS], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_STCX_PASS] }, [ POWER5p_PME_PM_DC_INV_L2 ] = { .pme_name = "PM_DC_INV_L2", .pme_code = 0xc10c7, .pme_short_desc = "L1 D cache entries invalidated from L2", .pme_long_desc = "A dcache invalidated was received from the L2 because a line in L2 was castout.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DC_INV_L2], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DC_INV_L2] }, [ POWER5p_PME_PM_LSU_SRQ_FULL_CYC ] = { .pme_name = "PM_LSU_SRQ_FULL_CYC", .pme_code = 0x110c3, .pme_short_desc = "Cycles SRQ full", .pme_long_desc = "Cycles the Store Request Queue is full.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_SRQ_FULL_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_SRQ_FULL_CYC] }, [ POWER5p_PME_PM_FPU_FIN ] = { .pme_name = "PM_FPU_FIN", .pme_code = 0x401088, .pme_short_desc = "FPU produced a result", .pme_long_desc = "FPU finished, produced a result. This only indicates finish, not completion. Combined Unit 0 + Unit 1. Floating Point Stores are included in this count but not Floating Point Loads., , , XYZs", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU_FIN], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU_FIN] }, [ POWER5p_PME_PM_LSU_SRQ_STFWD ] = { .pme_name = "PM_LSU_SRQ_STFWD", .pme_code = 0x2c6088, .pme_short_desc = "SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. Combined Unit 0 + 1.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU_SRQ_STFWD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU_SRQ_STFWD] }, [ POWER5p_PME_PM_L2SA_SHR_MOD ] = { .pme_name = "PM_L2SA_SHR_MOD", .pme_code = 0x700c0, .pme_short_desc = "L2 slice A transition from shared to modified", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A, B, and C.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_SHR_MOD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_SHR_MOD] }, [ POWER5p_PME_PM_0INST_CLB_CYC ] = { .pme_name = "PM_0INST_CLB_CYC", .pme_code = 0x400c0, .pme_short_desc = "Cycles no instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_0INST_CLB_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_0INST_CLB_CYC] }, [ POWER5p_PME_PM_FXU0_FIN ] = { .pme_name = "PM_FXU0_FIN", .pme_code = 0x130e2, .pme_short_desc = "FXU0 produced a result", .pme_long_desc = "The Fixed Point unit 0 finished an instruction and produced a result. Instructions that finish may not necessary complete.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FXU0_FIN], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FXU0_FIN] }, [ POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL ] = { .pme_name = "PM_L2SB_RCST_DISP_FAIL_RC_FULL", .pme_code = 0x722e2, .pme_short_desc = "L2 slice B RC store dispatch attempt failed due to all RC full", .pme_long_desc = "A Read/Claim dispatch for a store failed because all RC machines are busy.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL] }, [ POWER5p_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = { .pme_name = "PM_THRD_GRP_CMPL_BOTH_CYC", .pme_code = 0x200013, .pme_short_desc = "Cycles group completed by both threads", .pme_long_desc = "Cycles that both threads completed.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_GRP_CMPL_BOTH_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_GRP_CMPL_BOTH_CYC] }, [ POWER5p_PME_PM_PMC5_OVERFLOW ] = { .pme_name = "PM_PMC5_OVERFLOW", .pme_code = 0x10001a, .pme_short_desc = "PMC5 Overflow", .pme_long_desc = "Overflows from PMC5 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PMC5_OVERFLOW], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PMC5_OVERFLOW] }, [ POWER5p_PME_PM_FPU0_FDIV ] = { .pme_name = "PM_FPU0_FDIV", .pme_code = 0xc0, .pme_short_desc = "FPU0 executed FDIV instruction", .pme_long_desc = "FPU0 has executed a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_FPU0_FDIV], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_FPU0_FDIV] }, [ POWER5p_PME_PM_PTEG_FROM_L375_SHR ] = { .pme_name = "PM_PTEG_FROM_L375_SHR", .pme_code = 0x38309e, .pme_short_desc = "PTEG loaded from L3.75 shared", .pme_long_desc = "A Page Table Entry was loaded into the TLB with shared (S) data from the L3 of a chip on a different module than this processor is located, due to a demand load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_PTEG_FROM_L375_SHR], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_PTEG_FROM_L375_SHR] }, [ POWER5p_PME_PM_HV_CYC ] = { .pme_name = "PM_HV_CYC", .pme_code = 0x20000b, .pme_short_desc = "Hypervisor Cycles", .pme_long_desc = "Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0)", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_HV_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_HV_CYC] }, [ POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY ] = { .pme_name = "PM_L2SA_RC_DISP_FAIL_CO_BUSY", .pme_code = 0x703c0, .pme_short_desc = "L2 slice A RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy", .pme_long_desc = "A Read/Claim Dispatch was rejected at dispatch because the Castout Machine was busy. In the case of an RC starting up on a miss and the victim is valid, the CO machine must be available for the RC to process the access. If the CO is still busy working on an old castout, then the RC must not-ack the access if it is a miss(re-issued by the CIU). If it is a miss and the CO is available to process the castout, the RC will accept the access. Once the RC has finished, it can restart and process new accesses that result in a hit (or miss that doesn't need a CO) even though the CO is still processing a castout from a previous access.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY] }, [ POWER5p_PME_PM_THRD_PRIO_DIFF_0_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_0_CYC", .pme_code = 0x430e3, .pme_short_desc = "Cycles no thread priority difference", .pme_long_desc = "Cycles when this thread's priority is equal to the other thread's priority.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_THRD_PRIO_DIFF_0_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_THRD_PRIO_DIFF_0_CYC] }, [ POWER5p_PME_PM_LR_CTR_MAP_FULL_CYC ] = { .pme_name = "PM_LR_CTR_MAP_FULL_CYC", .pme_code = 0x100c6, .pme_short_desc = "Cycles LR/CTR mapper full", .pme_long_desc = "The LR/CTR mapper cannot accept any more groups. This condition will prevent dispatch groups from being dispatched. This event only indicates that the mapper was full, not that dispatch was prevented.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LR_CTR_MAP_FULL_CYC], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LR_CTR_MAP_FULL_CYC] }, [ POWER5p_PME_PM_L3SB_SHR_INV ] = { .pme_name = "PM_L3SB_SHR_INV", .pme_code = 0x710c4, .pme_short_desc = "L3 slice B transition from shared to invalid", .pme_long_desc = "L3 snooper detects someone doing a store to a line that is Sx in this L3(i.e. invalidate hit SX and dispatched).", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L3SB_SHR_INV], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L3SB_SHR_INV] }, [ POWER5p_PME_PM_DATA_FROM_RMEM ] = { .pme_name = "PM_DATA_FROM_RMEM", .pme_code = 0x1c30a1, .pme_short_desc = "Data loaded from remote memory", .pme_long_desc = "The processor's Data Cache was reloaded from memory attached to a different module than this proccessor is located on.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DATA_FROM_RMEM], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DATA_FROM_RMEM] }, [ POWER5p_PME_PM_DATA_FROM_L275_MOD ] = { .pme_name = "PM_DATA_FROM_L275_MOD", .pme_code = 0x1c30a3, .pme_short_desc = "Data loaded from L2.75 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L2 on a different module than this processor is located due to a demand load.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DATA_FROM_L275_MOD], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DATA_FROM_L275_MOD] }, [ POWER5p_PME_PM_LSU0_REJECT_SRQ ] = { .pme_name = "PM_LSU0_REJECT_SRQ", .pme_code = 0xc40c0, .pme_short_desc = "LSU0 SRQ lhs rejects", .pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions because of Load Hit Store conditions. Loads are rejected when data is needed from a previous store instruction but store forwarding is not possible because the data is not fully contained in the Store Data Queue or is not yet available in the Store Data Queue.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU0_REJECT_SRQ], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU0_REJECT_SRQ] }, [ POWER5p_PME_PM_LSU1_DERAT_MISS ] = { .pme_name = "PM_LSU1_DERAT_MISS", .pme_code = 0x800c6, .pme_short_desc = "LSU1 DERAT misses", .pme_long_desc = "A data request (load or store) from LSU Unit 1 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU1_DERAT_MISS], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU1_DERAT_MISS] }, [ POWER5p_PME_PM_MRK_LSU_FIN ] = { .pme_name = "PM_MRK_LSU_FIN", .pme_code = 0x400014, .pme_short_desc = "Marked instruction LSU processing finished", .pme_long_desc = "One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_MRK_LSU_FIN], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_MRK_LSU_FIN] }, [ POWER5p_PME_PM_DTLB_MISS_16M ] = { .pme_name = "PM_DTLB_MISS_16M", .pme_code = 0x3c208d, .pme_short_desc = "Data TLB miss for 16M page", .pme_long_desc = "Data TLB references to 16MB pages that missed the TLB. Page size is determined at TLB reload time.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_DTLB_MISS_16M], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_DTLB_MISS_16M] }, [ POWER5p_PME_PM_LSU0_FLUSH_UST ] = { .pme_name = "PM_LSU0_FLUSH_UST", .pme_code = 0xc00c1, .pme_short_desc = "LSU0 unaligned store flushes", .pme_long_desc = "A store was flushed from unit 0 because it was unaligned (crossed a 4K boundary).", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_LSU0_FLUSH_UST], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_LSU0_FLUSH_UST] }, [ POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY ] = { .pme_name = "PM_L2SB_RC_DISP_FAIL_CO_BUSY", .pme_code = 0x703c1, .pme_short_desc = "L2 slice B RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy", .pme_long_desc = "A Read/Claim Dispatch was rejected at dispatch because the Castout Machine was busy. In the case of an RC starting up on a miss and the victim is valid, the CO machine must be available for the RC to process the access. If the CO is still busy working on an old castout, then the RC must not-ack the access if it is a miss(re-issued by the CIU). If it is a miss and the CO is available to process the castout, the RC will accept the access. Once the RC has finished, it can restart and process new accesses that result in a hit (or miss that doesn't need a CO) even though the CO is still processing a castout from a previous access.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY] }, [ POWER5p_PME_PM_L2SC_MOD_TAG ] = { .pme_name = "PM_L2SC_MOD_TAG", .pme_code = 0x720e2, .pme_short_desc = "L2 slice C transition from modified to tagged", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.", .pme_event_ids = power5p_event_ids[POWER5p_PME_PM_L2SC_MOD_TAG], .pme_group_vector = power5p_group_vecs[POWER5p_PME_PM_L2SC_MOD_TAG] } }; #define POWER5p_PME_EVENT_COUNT 483 static const int power5p_group_event_ids[][POWER5p_NUM_EVENT_COUNTERS] = { [ 0 ] = { 312, 302, 113, 21, 0, 0 }, [ 1 ] = { 2, 95, 100, 21, 0, 0 }, [ 2 ] = { 105, 104, 101, 113, 0, 0 }, [ 3 ] = { 0, 2, 12, 267, 0, 0 }, [ 4 ] = { 6, 6, 292, 112, 0, 0 }, [ 5 ] = { 98, 97, 95, 98, 0, 0 }, [ 6 ] = { 99, 98, 96, 97, 0, 0 }, [ 7 ] = { 242, 241, 234, 234, 0, 0 }, [ 8 ] = { 247, 246, 244, 240, 0, 0 }, [ 9 ] = { 238, 247, 236, 239, 0, 0 }, [ 10 ] = { 237, 244, 236, 239, 0, 0 }, [ 11 ] = { 120, 115, 26, 29, 0, 0 }, [ 12 ] = { 115, 13, 122, 108, 0, 0 }, [ 13 ] = { 1, 227, 172, 112, 0, 0 }, [ 14 ] = { 216, 225, 27, 171, 0, 0 }, [ 15 ] = { 244, 242, 53, 294, 0, 0 }, [ 16 ] = { 215, 224, 112, 122, 0, 0 }, [ 17 ] = { 213, 222, 245, 344, 0, 0 }, [ 18 ] = { 214, 223, 112, 9, 0, 0 }, [ 19 ] = { 245, 243, 228, 53, 0, 0 }, [ 20 ] = { 115, 233, 53, 26, 0, 0 }, [ 21 ] = { 124, 113, 54, 57, 0, 0 }, [ 22 ] = { 233, 230, 112, 226, 0, 0 }, [ 23 ] = { 207, 216, 228, 112, 0, 0 }, [ 24 ] = { 208, 217, 112, 226, 0, 0 }, [ 25 ] = { 235, 233, 8, 112, 0, 0 }, [ 26 ] = { 209, 218, 228, 112, 0, 0 }, [ 27 ] = { 210, 219, 112, 226, 0, 0 }, [ 28 ] = { 232, 113, 290, 229, 0, 0 }, [ 29 ] = { 109, 17, 112, 18, 0, 0 }, [ 30 ] = { 115, 14, 16, 16, 0, 0 }, [ 31 ] = { 107, 16, 112, 15, 0, 0 }, [ 32 ] = { 89, 15, 112, 17, 0, 0 }, [ 33 ] = { 198, 7, 237, 231, 0, 0 }, [ 34 ] = { 68, 80, 88, 92, 0, 0 }, [ 35 ] = { 16, 200, 97, 19, 0, 0 }, [ 36 ] = { 57, 351, 266, 112, 0, 0 }, [ 37 ] = { 325, 321, 208, 220, 0, 0 }, [ 38 ] = { 205, 214, 106, 107, 0, 0 }, [ 39 ] = { 113, 110, 108, 1, 0, 0 }, [ 40 ] = { 108, 106, 121, 112, 0, 0 }, [ 41 ] = { 356, 307, 9, 11, 0, 0 }, [ 42 ] = { 12, 11, 11, 12, 0, 0 }, [ 43 ] = { 102, 100, 52, 112, 0, 0 }, [ 44 ] = { 25, 30, 195, 196, 0, 0 }, [ 45 ] = { 18, 228, 322, 318, 0, 0 }, [ 46 ] = { 30, 120, 196, 195, 0, 0 }, [ 47 ] = { 34, 33, 33, 34, 0, 0 }, [ 48 ] = { 32, 31, 31, 32, 0, 0 }, [ 49 ] = { 33, 30, 16, 21, 0, 0 }, [ 50 ] = { 201, 323, 195, 318, 0, 0 }, [ 51 ] = { 21, 23, 51, 112, 0, 0 }, [ 52 ] = { 21, 23, 19, 24, 0, 0 }, [ 53 ] = { 19, 21, 18, 22, 0, 0 }, [ 54 ] = { 22, 22, 22, 23, 0, 0 }, [ 55 ] = { 121, 116, 118, 117, 0, 0 }, [ 56 ] = { 118, 119, 112, 1, 0, 0 }, [ 57 ] = { 119, 117, 115, 115, 0, 0 }, [ 58 ] = { 122, 118, 117, 116, 0, 0 }, [ 59 ] = { 305, 303, 299, 300, 0, 0 }, [ 60 ] = { 308, 304, 303, 301, 0, 0 }, [ 61 ] = { 304, 305, 300, 302, 0, 0 }, [ 62 ] = { 307, 102, 103, 26, 0, 0 }, [ 63 ] = { 130, 130, 127, 127, 0, 0 }, [ 64 ] = { 134, 134, 131, 131, 0, 0 }, [ 65 ] = { 138, 140, 135, 137, 0, 0 }, [ 66 ] = { 146, 146, 143, 143, 0, 0 }, [ 67 ] = { 150, 150, 147, 147, 0, 0 }, [ 68 ] = { 154, 156, 151, 153, 0, 0 }, [ 69 ] = { 162, 162, 159, 159, 0, 0 }, [ 70 ] = { 166, 166, 163, 163, 0, 0 }, [ 71 ] = { 170, 172, 167, 169, 0, 0 }, [ 72 ] = { 180, 113, 175, 177, 0, 0 }, [ 73 ] = { 115, 184, 182, 184, 0, 0 }, [ 74 ] = { 115, 191, 189, 191, 0, 0 }, [ 75 ] = { 129, 138, 124, 135, 0, 0 }, [ 76 ] = { 145, 154, 140, 151, 0, 0 }, [ 77 ] = { 161, 170, 156, 167, 0, 0 }, [ 78 ] = { 177, 181, 179, 185, 0, 0 }, [ 79 ] = { 181, 185, 174, 180, 0, 0 }, [ 80 ] = { 191, 192, 193, 187, 0, 0 }, [ 81 ] = { 87, 84, 84, 87, 0, 0 }, [ 82 ] = { 85, 86, 85, 88, 0, 0 }, [ 83 ] = { 86, 87, 61, 77, 0, 0 }, [ 84 ] = { 90, 88, 112, 230, 0, 0 }, [ 85 ] = { 67, 79, 60, 76, 0, 0 }, [ 86 ] = { 59, 72, 63, 79, 0, 0 }, [ 87 ] = { 60, 73, 65, 80, 0, 0 }, [ 88 ] = { 70, 82, 112, 66, 0, 0 }, [ 89 ] = { 69, 81, 207, 219, 0, 0 }, [ 90 ] = { 63, 76, 112, 80, 0, 0 }, [ 91 ] = { 58, 71, 61, 112, 0, 0 }, [ 92 ] = { 71, 83, 207, 112, 0, 0 }, [ 93 ] = { 96, 93, 90, 95, 0, 0 }, [ 94 ] = { 281, 283, 93, 93, 0, 0 }, [ 95 ] = { 4, 4, 91, 96, 0, 0 }, [ 96 ] = { 337, 335, 334, 331, 0, 0 }, [ 97 ] = { 336, 334, 336, 333, 0, 0 }, [ 98 ] = { 335, 333, 338, 335, 0, 0 }, [ 99 ] = { 334, 107, 340, 112, 0, 0 }, [ 100 ] = { 333, 327, 112, 322, 0, 0 }, [ 101 ] = { 321, 113, 345, 342, 0, 0 }, [ 102 ] = { 115, 0, 341, 338, 0, 0 }, [ 103 ] = { 115, 20, 343, 340, 0, 0 }, [ 104 ] = { 37, 38, 37, 41, 0, 0 }, [ 105 ] = { 45, 41, 45, 52, 0, 0 }, [ 106 ] = { 47, 48, 47, 51, 0, 0 }, [ 107 ] = { 43, 40, 34, 45, 0, 0 }, [ 108 ] = { 317, 308, 315, 305, 0, 0 }, [ 109 ] = { 318, 315, 312, 112, 0, 0 }, [ 110 ] = { 323, 252, 317, 249, 0, 0 }, [ 111 ] = { 315, 353, 309, 306, 0, 0 }, [ 112 ] = { 261, 263, 249, 36, 0, 0 }, [ 113 ] = { 260, 261, 258, 37, 0, 0 }, [ 114 ] = { 268, 264, 262, 260, 0, 0 }, [ 115 ] = { 256, 257, 254, 251, 0, 0 }, [ 116 ] = { 281, 284, 348, 293, 0, 0 }, [ 117 ] = { 281, 300, 278, 278, 0, 0 }, [ 118 ] = { 282, 268, 279, 279, 0, 0 }, [ 119 ] = { 269, 272, 264, 264, 0, 0 }, [ 120 ] = { 270, 270, 112, 88, 0, 0 }, [ 121 ] = { 272, 276, 268, 267, 0, 0 }, [ 122 ] = { 275, 271, 265, 272, 0, 0 }, [ 123 ] = { 273, 274, 270, 270, 0, 0 }, [ 124 ] = { 271, 271, 112, 266, 0, 0 }, [ 125 ] = { 274, 275, 269, 269, 0, 0 }, [ 126 ] = { 280, 282, 275, 277, 0, 0 }, [ 127 ] = { 278, 280, 273, 275, 0, 0 }, [ 128 ] = { 279, 279, 271, 21, 0, 0 }, [ 129 ] = { 280, 113, 275, 273, 0, 0 }, [ 130 ] = { 285, 113, 294, 263, 0, 0 }, [ 131 ] = { 299, 300, 291, 295, 0, 0 }, [ 132 ] = { 298, 299, 276, 280, 0, 0 }, [ 133 ] = { 18, 116, 322, 196, 0, 0 }, [ 134 ] = { 21, 23, 322, 196, 0, 0 }, [ 135 ] = { 124, 30, 322, 196, 0, 0 }, [ 136 ] = { 21, 23, 195, 318, 0, 0 }, [ 137 ] = { 17, 110, 122, 171, 0, 0 }, [ 138 ] = { 12, 11, 11, 9, 0, 0 }, [ 139 ] = { 70, 82, 61, 66, 0, 0 }, [ 140 ] = { 63, 76, 65, 80, 0, 0 }, [ 141 ] = { 58, 71, 61, 77, 0, 0 }, [ 142 ] = { 85, 84, 322, 196, 0, 0 }, [ 143 ] = { 90, 88, 61, 77, 0, 0 }, [ 144 ] = { 87, 86, 85, 88, 0, 0 }, [ 145 ] = { 85, 84, 87, 88, 0, 0 }, [ 146 ] = { 17, 94, 16, 88, 0, 0 }, [ 147 ] = { 303, 88, 113, 230, 0, 0 }, [ 148 ] = { 17, 114, 195, 318, 0, 0 }, [ 149 ] = { 356, 20, 322, 196, 0, 0 }, [ 150 ] = { 87, 84, 86, 86, 0, 0 }, [ 151 ] = { 303, 20, 195, 26, 0, 0 }, [ 152 ] = { 303, 323, 113, 196, 0, 0 }, [ 153 ] = { 17, 84, 87, 88, 0, 0 }, [ 154 ] = { 17, 30, 195, 196, 0, 0 }, [ 155 ] = { 17, 302, 322, 318, 0, 0 }, [ 156 ] = { 303, 23, 16, 24, 0, 0 }, [ 157 ] = { 281, 302, 348, 293, 0, 0 }, [ 158 ] = { 281, 302, 278, 278, 0, 0 }, [ 159 ] = { 282, 302, 279, 279, 0, 0 }, [ 160 ] = { 269, 302, 264, 264, 0, 0 }, [ 161 ] = { 270, 302, 277, 88, 0, 0 }, [ 162 ] = { 303, 276, 268, 267, 0, 0 }, [ 163 ] = { 303, 271, 265, 272, 0, 0 }, [ 164 ] = { 273, 302, 270, 270, 0, 0 }, [ 165 ] = { 303, 271, 112, 266, 0, 0 }, [ 166 ] = { 303, 275, 269, 269, 0, 0 }, [ 167 ] = { 303, 280, 273, 275, 0, 0 }, [ 168 ] = { 303, 282, 275, 277, 0, 0 }, [ 169 ] = { 303, 280, 273, 275, 0, 0 }, [ 170 ] = { 280, 302, 275, 273, 0, 0 }, [ 171 ] = { 285, 302, 294, 263, 0, 0 }, [ 172 ] = { 299, 302, 291, 295, 0, 0 }, [ 173 ] = { 303, 299, 276, 280, 0, 0 }, [ 174 ] = { 303, 270, 267, 281, 0, 0 }, [ 175 ] = { 303, 274, 272, 271, 0, 0 }, [ 176 ] = { 278, 302, 274, 265, 0, 0 }, [ 177 ] = { 280, 302, 112, 286, 0, 0 }, [ 178 ] = { 278, 302, 288, 292, 0, 0 }, [ 179 ] = { 303, 272, 284, 288, 0, 0 }, [ 180 ] = { 303, 268, 282, 286, 0, 0 }, [ 181 ] = { 303, 292, 287, 297, 0, 0 }, [ 182 ] = { 303, 286, 281, 298, 0, 0 }, [ 183 ] = { 303, 268, 264, 268, 0, 0 }, [ 184 ] = { 303, 296, 290, 294, 0, 0 }, [ 185 ] = { 269, 302, 266, 296, 0, 0 }, [ 186 ] = { 303, 94, 276, 293, 0, 0 }, [ 187 ] = { 303, 283, 278, 278, 0, 0 } }; static const pmg_power_group_t power5p_groups[] = { [ 0 ] = { .pmg_name = "pm_utilization", .pmg_desc = "CPI and utilization data", .pmg_event_ids = power5p_group_event_ids[0], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000000a12121eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 1 ] = { .pmg_name = "pm_completion", .pmg_desc = "Completion and cycle counts", .pmg_event_ids = power5p_group_event_ids[1], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000002608261eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 2 ] = { .pmg_name = "pm_group_dispatch", .pmg_desc = "Group dispatch events", .pmg_event_ids = power5p_group_event_ids[2], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4000000ec6c8c212ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 3 ] = { .pmg_name = "pm_clb1", .pmg_desc = "CLB fullness", .pmg_event_ids = power5p_group_event_ids[3], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x015b000180848c4cULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 4 ] = { .pmg_name = "pm_clb2", .pmg_desc = "CLB fullness", .pmg_event_ids = power5p_group_event_ids[4], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x014300028a8ccc02ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 5 ] = { .pmg_name = "pm_gct_empty", .pmg_desc = "GCT empty reasons", .pmg_event_ids = power5p_group_event_ids[5], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4000000008380838ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 6 ] = { .pmg_name = "pm_gct_usage", .pmg_desc = "GCT Usage", .pmg_event_ids = power5p_group_event_ids[6], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000003e3e3e3eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 7 ] = { .pmg_name = "pm_lsu1", .pmg_desc = "LSU LRQ and LMQ events", .pmg_event_ids = power5p_group_event_ids[7], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x020f000fcecccccaULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 8 ] = { .pmg_name = "pm_lsu2", .pmg_desc = "LSU SRQ events", .pmg_event_ids = power5p_group_event_ids[8], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x400e000ececcca86ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 9 ] = { .pmg_name = "pm_lsu3", .pmg_desc = "LSU SRQ and LMQ events", .pmg_event_ids = power5p_group_event_ids[9], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x030f0004ea102a2aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 10 ] = { .pmg_name = "pm_lsu4", .pmg_desc = "LSU SRQ and LMQ events", .pmg_event_ids = power5p_group_event_ids[10], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x40030000eea62a2aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 11 ] = { .pmg_name = "pm_prefetch1", .pmg_desc = "Prefetch stream allocation", .pmg_event_ids = power5p_group_event_ids[11], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x8432000d36c884ceULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 12 ] = { .pmg_name = "pm_prefetch2", .pmg_desc = "Prefetch events", .pmg_event_ids = power5p_group_event_ids[12], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x8103000602cace8eULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 13 ] = { .pmg_name = "pm_prefetch3", .pmg_desc = "L2 prefetch and misc events", .pmg_event_ids = power5p_group_event_ids[13], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x047c000482108602ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 14 ] = { .pmg_name = "pm_prefetch4", .pmg_desc = "Misc prefetch and reject events", .pmg_event_ids = power5p_group_event_ids[14], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0cf200028088cc86ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 15 ] = { .pmg_name = "pm_lsu_reject1", .pmg_desc = "LSU reject events", .pmg_event_ids = power5p_group_event_ids[15], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xc8e000022010c610ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 16 ] = { .pmg_name = "pm_lsu_reject2", .pmg_desc = "LSU rejects due to reload CDF or tag update collision", .pmg_event_ids = power5p_group_event_ids[16], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x88c00001848c02ceULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 17 ] = { .pmg_name = "LSU rejects due to ERAT", .pmg_desc = " held instuctions", .pmg_event_ids = power5p_group_event_ids[17], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x48c00003868ec0c8ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 18 ] = { .pmg_name = "pm_lsu_reject4", .pmg_desc = "LSU0/1 reject LMQ full", .pmg_event_ids = power5p_group_event_ids[18], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x88c00001828a02c8ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 19 ] = { .pmg_name = "pm_lsu_reject5", .pmg_desc = "LSU misc reject and flush events", .pmg_event_ids = power5p_group_event_ids[19], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x48c0000010208a8eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 20 ] = { .pmg_name = "pm_flush1", .pmg_desc = "Misc flush events", .pmg_event_ids = power5p_group_event_ids[20], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xc0f000020210c68eULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 21 ] = { .pmg_name = "pm_flush2", .pmg_desc = "Flushes due to scoreboard and sync", .pmg_event_ids = power5p_group_event_ids[21], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xc08000038002c4c2ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 22 ] = { .pmg_name = "pm_lsu_flush_srq_lrq", .pmg_desc = "LSU flush by SRQ and LRQ events", .pmg_event_ids = power5p_group_event_ids[22], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x40c000002020028aULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 23 ] = { .pmg_name = "pm_lsu_flush_lrq", .pmg_desc = "LSU0/1 flush due to LRQ", .pmg_event_ids = power5p_group_event_ids[23], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x40c00000848c8a02ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 24 ] = { .pmg_name = "pm_lsu_flush_srq", .pmg_desc = "LSU0/1 flush due to SRQ", .pmg_event_ids = power5p_group_event_ids[24], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x40c00000868e028aULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 25 ] = { .pmg_name = "pm_lsu_flush_unaligned", .pmg_desc = "LSU flush due to unaligned data", .pmg_event_ids = power5p_group_event_ids[25], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x80c000021010c802ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 26 ] = { .pmg_name = "pm_lsu_flush_uld", .pmg_desc = "LSU0/1 flush due to unaligned load", .pmg_event_ids = power5p_group_event_ids[26], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x40c0000080888a02ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 27 ] = { .pmg_name = "pm_lsu_flush_ust", .pmg_desc = "LSU0/1 flush due to unaligned store", .pmg_event_ids = power5p_group_event_ids[27], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x40c00000828a028aULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 28 ] = { .pmg_name = "pm_lsu_flush_full", .pmg_desc = "LSU flush due to LRQ/SRQ full", .pmg_event_ids = power5p_group_event_ids[28], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xc0200009ce0210c0ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 29 ] = { .pmg_name = "pm_lsu_stall1", .pmg_desc = "LSU Stalls", .pmg_event_ids = power5p_group_event_ids[29], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4000000028300234ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 30 ] = { .pmg_name = "pm_lsu_stall2", .pmg_desc = "LSU Stalls", .pmg_event_ids = power5p_group_event_ids[30], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4000000002341e36ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 31 ] = { .pmg_name = "pm_fxu_stall", .pmg_desc = "FXU Stalls", .pmg_event_ids = power5p_group_event_ids[31], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x40000008ca320232ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 32 ] = { .pmg_name = "pm_fpu_stall", .pmg_desc = "FPU Stalls", .pmg_event_ids = power5p_group_event_ids[32], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4000000020360230ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 33 ] = { .pmg_name = "pm_queue_full", .pmg_desc = "BRQ LRQ LMQ queue full", .pmg_event_ids = power5p_group_event_ids[33], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x400b0009ce8a84ceULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 34 ] = { .pmg_name = "pm_issueq_full", .pmg_desc = "FPU FX full", .pmg_event_ids = power5p_group_event_ids[34], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x40000000868e8088ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 35 ] = { .pmg_name = "pm_mapper_full1", .pmg_desc = "CR CTR GPR mapper full", .pmg_event_ids = power5p_group_event_ids[35], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x40000002888cca82ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 36 ] = { .pmg_name = "pm_mapper_full2", .pmg_desc = "FPR XER mapper full", .pmg_event_ids = power5p_group_event_ids[36], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4103000282843602ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 37 ] = { .pmg_name = "pm_misc_load", .pmg_desc = "Non-cachable loads and stcx events", .pmg_event_ids = power5p_group_event_ids[37], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0438000cc2ca828aULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 38 ] = { .pmg_name = "pm_ic_demand", .pmg_desc = "ICache demand from BR redirect", .pmg_event_ids = power5p_group_event_ids[38], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x800c000fc2cac0c2ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 39 ] = { .pmg_name = "pm_ic_pref", .pmg_desc = "ICache prefetch", .pmg_event_ids = power5p_group_event_ids[39], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x8000000dcecc8e1aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 40 ] = { .pmg_name = "pm_ic_miss", .pmg_desc = "ICache misses", .pmg_event_ids = power5p_group_event_ids[40], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4003000e32cec802ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 41 ] = { .pmg_name = "Branch mispredict", .pmg_desc = " TLB and SLB misses", .pmg_event_ids = power5p_group_event_ids[41], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x808000031010caccULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 42 ] = { .pmg_name = "pm_branch1", .pmg_desc = "Branch operations", .pmg_event_ids = power5p_group_event_ids[42], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x8000000f0e0e0e0eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 43 ] = { .pmg_name = "pm_branch2", .pmg_desc = "Branch operations", .pmg_event_ids = power5p_group_event_ids[43], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4000000c22cc8c02ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 44 ] = { .pmg_name = "pm_L1_tlbmiss", .pmg_desc = "L1 load and TLB misses", .pmg_event_ids = power5p_group_event_ids[44], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00b000008e881020ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 45 ] = { .pmg_name = "pm_L1_DERAT_miss", .pmg_desc = "L1 store and DERAT misses", .pmg_event_ids = power5p_group_event_ids[45], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00b300080e202086ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 46 ] = { .pmg_name = "pm_L1_slbmiss", .pmg_desc = "L1 load and SLB misses", .pmg_event_ids = power5p_group_event_ids[46], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00b000008a82848cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 47 ] = { .pmg_name = "pm_dtlbref", .pmg_desc = "Data TLB references", .pmg_event_ids = power5p_group_event_ids[47], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000c000f0c0c0c0cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 48 ] = { .pmg_name = "pm_dtlbmiss", .pmg_desc = "Data TLB misses", .pmg_event_ids = power5p_group_event_ids[48], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000c000f1a1a1a1aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 49 ] = { .pmg_name = "pm_dtlb", .pmg_desc = "Data TLB references and misses", .pmg_event_ids = power5p_group_event_ids[49], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x008c0008c8881e1eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 50 ] = { .pmg_name = "pm_L1_refmiss", .pmg_desc = "L1 load references and misses and store references and misses", .pmg_event_ids = power5p_group_event_ids[50], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0030000050501086ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 51 ] = { .pmg_name = "pm_dsource1", .pmg_desc = "L3 cache and memory data access", .pmg_event_ids = power5p_group_event_ids[51], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4003000c1c0e8e02ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 52 ] = { .pmg_name = "pm_dsource2", .pmg_desc = "L3 cache and memory data access", .pmg_event_ids = power5p_group_event_ids[52], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0003000f1c0e360eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 53 ] = { .pmg_name = "pm_dsource_L2", .pmg_desc = "L2 cache data access", .pmg_event_ids = power5p_group_event_ids[53], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0003000f2e2e2e2eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 54 ] = { .pmg_name = "pm_dsource_L3", .pmg_desc = "L3 cache data access", .pmg_event_ids = power5p_group_event_ids[54], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0003000f3c3c3c3cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 55 ] = { .pmg_name = "pm_isource1", .pmg_desc = "Instruction source information", .pmg_event_ids = power5p_group_event_ids[55], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x8000000f1a1a1a0cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 56 ] = { .pmg_name = "pm_isource2", .pmg_desc = "Instruction source information", .pmg_event_ids = power5p_group_event_ids[56], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x8000000d0c0c021aULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 57 ] = { .pmg_name = "pm_isource_L2", .pmg_desc = "L2 instruction source information", .pmg_event_ids = power5p_group_event_ids[57], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x8000000f2c2c2c2cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 58 ] = { .pmg_name = "pm_isource_L3", .pmg_desc = "L3 instruction source information", .pmg_event_ids = power5p_group_event_ids[58], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x8000000f3a3a3a3aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 59 ] = { .pmg_name = "pm_pteg_source1", .pmg_desc = "PTEG source information", .pmg_event_ids = power5p_group_event_ids[59], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0002000f2e2e2e2eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 60 ] = { .pmg_name = "pm_pteg_source2", .pmg_desc = "PTEG source information", .pmg_event_ids = power5p_group_event_ids[60], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0002000f3c3c3c3cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 61 ] = { .pmg_name = "pm_pteg_source3", .pmg_desc = "PTEG source information", .pmg_event_ids = power5p_group_event_ids[61], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0002000f0e0e360eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 62 ] = { .pmg_name = "pm_pteg_source4", .pmg_desc = "L3 PTEG and group disptach events", .pmg_event_ids = power5p_group_event_ids[62], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x003200081c04048eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 63 ] = { .pmg_name = "pm_L2SA_ld", .pmg_desc = "L2 slice A load events", .pmg_event_ids = power5p_group_event_ids[63], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3055400580c080c0ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 64 ] = { .pmg_name = "pm_L2SA_st", .pmg_desc = "L2 slice A store events", .pmg_event_ids = power5p_group_event_ids[64], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3055800580c080c0ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 65 ] = { .pmg_name = "pm_L2SA_st2", .pmg_desc = "L2 slice A store events", .pmg_event_ids = power5p_group_event_ids[65], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3055c00580c080c0ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 66 ] = { .pmg_name = "pm_L2SB_ld", .pmg_desc = "L2 slice B load events", .pmg_event_ids = power5p_group_event_ids[66], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3055400582c282c2ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 67 ] = { .pmg_name = "pm_L2SB_st", .pmg_desc = "L2 slice B store events", .pmg_event_ids = power5p_group_event_ids[67], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3055800582c482c2ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 68 ] = { .pmg_name = "pm_L2SB_st2", .pmg_desc = "L2 slice B store events", .pmg_event_ids = power5p_group_event_ids[68], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3055c00582c282c2ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 69 ] = { .pmg_name = "pm_L2SC_ld", .pmg_desc = "L2 slice C load events", .pmg_event_ids = power5p_group_event_ids[69], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3055400584c484c4ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 70 ] = { .pmg_name = "pm_L2SC_st", .pmg_desc = "L2 slice C store events", .pmg_event_ids = power5p_group_event_ids[70], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3055800584c284c4ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 71 ] = { .pmg_name = "pm_L2SC_st2", .pmg_desc = "L2 slice C store events", .pmg_event_ids = power5p_group_event_ids[71], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3055c00584c484c4ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 72 ] = { .pmg_name = "pm_L3SA_trans", .pmg_desc = "L3 slice A state transistions", .pmg_event_ids = power5p_group_event_ids[72], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3015000ac602c686ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 73 ] = { .pmg_name = "pm_L3SB_trans", .pmg_desc = "L3 slice B state transistions", .pmg_event_ids = power5p_group_event_ids[73], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3015000602c8c888ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 74 ] = { .pmg_name = "pm_L3SC_trans", .pmg_desc = "L3 slice C state transistions", .pmg_event_ids = power5p_group_event_ids[74], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3015000602caca8aULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 75 ] = { .pmg_name = "pm_L2SA_trans", .pmg_desc = "L2 slice A state transistions", .pmg_event_ids = power5p_group_event_ids[75], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3055000ac080c080ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 76 ] = { .pmg_name = "pm_L2SB_trans", .pmg_desc = "L2 slice B state transistions", .pmg_event_ids = power5p_group_event_ids[76], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3055000ac282c282ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 77 ] = { .pmg_name = "pm_L2SC_trans", .pmg_desc = "L2 slice C state transistions", .pmg_event_ids = power5p_group_event_ids[77], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3055000ac484c484ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 78 ] = { .pmg_name = "pm_L3SAB_retry", .pmg_desc = "L3 slice A/B snoop retry and all CI/CO busy", .pmg_event_ids = power5p_group_event_ids[78], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3005100fc6c8c6c8ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 79 ] = { .pmg_name = "pm_L3SAB_hit", .pmg_desc = "L3 slice A/B hit and reference", .pmg_event_ids = power5p_group_event_ids[79], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3050100086888688ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 80 ] = { .pmg_name = "pm_L3SC_retry_hit", .pmg_desc = "L3 slice C hit & snoop retry", .pmg_event_ids = power5p_group_event_ids[80], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3055100aca8aca8aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 81 ] = { .pmg_name = "pm_fpu1", .pmg_desc = "Floating Point events", .pmg_event_ids = power5p_group_event_ids[81], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000010101020ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 82 ] = { .pmg_name = "pm_fpu2", .pmg_desc = "Floating Point events", .pmg_event_ids = power5p_group_event_ids[82], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000020202010ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 83 ] = { .pmg_name = "pm_fpu3", .pmg_desc = "Floating point events", .pmg_event_ids = power5p_group_event_ids[83], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000c1010868eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 84 ] = { .pmg_name = "pm_fpu4", .pmg_desc = "Floating point events", .pmg_event_ids = power5p_group_event_ids[84], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0430000c20200220ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 85 ] = { .pmg_name = "pm_fpu5", .pmg_desc = "Floating point events by unit", .pmg_event_ids = power5p_group_event_ids[85], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000848c848cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 86 ] = { .pmg_name = "pm_fpu6", .pmg_desc = "Floating point events by unit", .pmg_event_ids = power5p_group_event_ids[86], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000cc0c88088ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 87 ] = { .pmg_name = "pm_fpu7", .pmg_desc = "Floating point events by unit", .pmg_event_ids = power5p_group_event_ids[87], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000008088828aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 88 ] = { .pmg_name = "pm_fpu8", .pmg_desc = "Floating point events by unit", .pmg_event_ids = power5p_group_event_ids[88], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000dc2ca02c0ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 89 ] = { .pmg_name = "pm_fpu9", .pmg_desc = "Floating point events by unit", .pmg_event_ids = power5p_group_event_ids[89], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0430000cc6ce8088ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 90 ] = { .pmg_name = "pm_fpu10", .pmg_desc = "Floating point events by unit", .pmg_event_ids = power5p_group_event_ids[90], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000828a028aULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 91 ] = { .pmg_name = "pm_fpu11", .pmg_desc = "Floating point events by unit", .pmg_event_ids = power5p_group_event_ids[91], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000868e8602ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 92 ] = { .pmg_name = "pm_fpu12", .pmg_desc = "Floating point events by unit", .pmg_event_ids = power5p_group_event_ids[92], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0430000cc4cc8002ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 93 ] = { .pmg_name = "pm_fxu1", .pmg_desc = "Fixed Point events", .pmg_event_ids = power5p_group_event_ids[93], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000024242424ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 94 ] = { .pmg_name = "pm_fxu2", .pmg_desc = "Fixed Point events", .pmg_event_ids = power5p_group_event_ids[94], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4000000604221020ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 95 ] = { .pmg_name = "pm_fxu3", .pmg_desc = "Fixed Point events", .pmg_event_ids = power5p_group_event_ids[95], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x404000038688c4ccULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 96 ] = { .pmg_name = "pm_smt_priorities1", .pmg_desc = "Thread priority events", .pmg_event_ids = power5p_group_event_ids[96], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0005000fc6ccc6c8ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 97 ] = { .pmg_name = "pm_smt_priorities2", .pmg_desc = "Thread priority events", .pmg_event_ids = power5p_group_event_ids[97], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0005000fc4cacaccULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 98 ] = { .pmg_name = "pm_smt_priorities3", .pmg_desc = "Thread priority events", .pmg_event_ids = power5p_group_event_ids[98], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0005000fc2c8c4c2ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 99 ] = { .pmg_name = "pm_smt_priorities4", .pmg_desc = "Thread priority events", .pmg_event_ids = power5p_group_event_ids[99], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0005000ac016c002ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 100 ] = { .pmg_name = "pm_smt_both", .pmg_desc = "Thread common events", .pmg_event_ids = power5p_group_event_ids[100], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0010000016260208ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 101 ] = { .pmg_name = "pm_smt_selection", .pmg_desc = "Thread selection", .pmg_event_ids = power5p_group_event_ids[101], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0090000086028082ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 102 ] = { .pmg_name = "pm_smt_selectover1", .pmg_desc = "Thread selection overide", .pmg_event_ids = power5p_group_event_ids[102], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0050000002808488ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 103 ] = { .pmg_name = "pm_smt_selectover2", .pmg_desc = "Thread selection overide", .pmg_event_ids = power5p_group_event_ids[103], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00100000021e8a86ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 104 ] = { .pmg_name = "pm_fabric1", .pmg_desc = "Fabric events", .pmg_event_ids = power5p_group_event_ids[104], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x305500058ece8eceULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 105 ] = { .pmg_name = "pm_fabric2", .pmg_desc = "Fabric data movement", .pmg_event_ids = power5p_group_event_ids[105], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x305500858ece8eceULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 106 ] = { .pmg_name = "pm_fabric3", .pmg_desc = "Fabric data movement", .pmg_event_ids = power5p_group_event_ids[106], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x305501858ece8eceULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 107 ] = { .pmg_name = "pm_fabric4", .pmg_desc = "Fabric data movement", .pmg_event_ids = power5p_group_event_ids[107], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x705401068ecec68eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 108 ] = { .pmg_name = "pm_snoop1", .pmg_desc = "Snoop retry", .pmg_event_ids = power5p_group_event_ids[108], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x305500058ccc8cccULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 109 ] = { .pmg_name = "pm_snoop2", .pmg_desc = "Snoop read retry", .pmg_event_ids = power5p_group_event_ids[109], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x30540a048ccc8c02ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 110 ] = { .pmg_name = "pm_snoop3", .pmg_desc = "Snoop write retry", .pmg_event_ids = power5p_group_event_ids[110], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x30550c058ccc8cccULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 111 ] = { .pmg_name = "pm_snoop4", .pmg_desc = "Snoop partial write retry", .pmg_event_ids = power5p_group_event_ids[111], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x30540e048ccc8cacULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 112 ] = { .pmg_name = "pm_mem_rq", .pmg_desc = "Memory read queue dispatch", .pmg_event_ids = power5p_group_event_ids[112], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x705402058ccc8cceULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 113 ] = { .pmg_name = "pm_mem_read", .pmg_desc = "Memory read complete and cancel", .pmg_event_ids = power5p_group_event_ids[113], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x305404048ccc8c06ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 114 ] = { .pmg_name = "pm_mem_wq", .pmg_desc = "Memory write queue dispatch", .pmg_event_ids = power5p_group_event_ids[114], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x305506058ccc8cccULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 115 ] = { .pmg_name = "pm_mem_pwq", .pmg_desc = "Memory partial write queue", .pmg_event_ids = power5p_group_event_ids[115], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x305508058ccc8cccULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 116 ] = { .pmg_name = "pm_threshold", .pmg_desc = "Thresholding", .pmg_event_ids = power5p_group_event_ids[116], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0008000404c41628ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 117 ] = { .pmg_name = "pm_mrk_grp1", .pmg_desc = "Marked group events", .pmg_event_ids = power5p_group_event_ids[117], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0008000404c60a26ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 118 ] = { .pmg_name = "pm_mrk_grp2", .pmg_desc = "Marked group events", .pmg_event_ids = power5p_group_event_ids[118], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x410300032a0ac822ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 119 ] = { .pmg_name = "pm_mrk_dsource1", .pmg_desc = "Marked data from", .pmg_event_ids = power5p_group_event_ids[119], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x010b000f0e404444ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 120 ] = { .pmg_name = "pm_mrk_dsource2", .pmg_desc = "Marked data from", .pmg_event_ids = power5p_group_event_ids[120], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x010b000c2e440210ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 121 ] = { .pmg_name = "pm_mrk_dsource3", .pmg_desc = "Marked data from", .pmg_event_ids = power5p_group_event_ids[121], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x010b000f1c484c4cULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 122 ] = { .pmg_name = "pm_mrk_dsource4", .pmg_desc = "Marked data from", .pmg_event_ids = power5p_group_event_ids[122], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x010b000f42462e42ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 123 ] = { .pmg_name = "pm_mrk_dsource5", .pmg_desc = "Marked data from", .pmg_event_ids = power5p_group_event_ids[123], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x010b000f3c4c4040ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 124 ] = { .pmg_name = "pm_mrk_dsource6", .pmg_desc = "Marked data from", .pmg_event_ids = power5p_group_event_ids[124], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x010b000d46460246ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 125 ] = { .pmg_name = "pm_mrk_dsource7", .pmg_desc = "Marked data from", .pmg_event_ids = power5p_group_event_ids[125], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x010b000f4e4e3c4eULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 126 ] = { .pmg_name = "pm_mrk_dtlbref", .pmg_desc = "Marked data TLB references", .pmg_event_ids = power5p_group_event_ids[126], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x020c000f0c0c0c0cULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 127 ] = { .pmg_name = "pm_mrk_dtlbmiss", .pmg_desc = "Marked data TLB misses", .pmg_event_ids = power5p_group_event_ids[127], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x020c000f1a1a1a1aULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 128 ] = { .pmg_name = "pm_mrk_dtlb_dslb", .pmg_desc = "Marked data TLB references and misses and marked data SLB misses", .pmg_event_ids = power5p_group_event_ids[128], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x063c0008c8ac8e1eULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 129 ] = { .pmg_name = "pm_mrk_lbref", .pmg_desc = "Marked TLB and SLB references", .pmg_event_ids = power5p_group_event_ids[129], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x063c000a0c020c8eULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 130 ] = { .pmg_name = "pm_mrk_lsmiss", .pmg_desc = "Marked load and store miss", .pmg_event_ids = power5p_group_event_ids[130], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000800081002060aULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 131 ] = { .pmg_name = "pm_mrk_ulsflush", .pmg_desc = "Mark unaligned load and store flushes", .pmg_event_ids = power5p_group_event_ids[131], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0028000406c62020ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 132 ] = { .pmg_name = "pm_mrk_misc", .pmg_desc = "Misc marked instructions", .pmg_event_ids = power5p_group_event_ids[132], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00080008cc062816ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 133 ] = { .pmg_name = "pm_lsref_L1", .pmg_desc = "Load/Store operations and L1 activity", .pmg_event_ids = power5p_group_event_ids[133], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x8033000c0e1a2020ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 134 ] = { .pmg_name = "Load/Store operations and L2", .pmg_desc = " L3 activity", .pmg_event_ids = power5p_group_event_ids[134], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0033000c1c0e2020ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 135 ] = { .pmg_name = "pm_lsref_tlbmiss", .pmg_desc = "Load/Store operations and TLB misses", .pmg_event_ids = power5p_group_event_ids[135], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00b0000080882020ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 136 ] = { .pmg_name = "pm_Dmiss", .pmg_desc = "Data cache misses", .pmg_event_ids = power5p_group_event_ids[136], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0033000c1c0e1086ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 137 ] = { .pmg_name = "pm_prefetchX", .pmg_desc = "Prefetch events", .pmg_event_ids = power5p_group_event_ids[137], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x853300061eccce86ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 138 ] = { .pmg_name = "pm_branchX", .pmg_desc = "Branch operations", .pmg_event_ids = power5p_group_event_ids[138], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x8000000f0e0e0ec8ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 139 ] = { .pmg_name = "pm_fpuX1", .pmg_desc = "Floating point events by unit", .pmg_event_ids = power5p_group_event_ids[139], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000dc2ca86c0ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 140 ] = { .pmg_name = "pm_fpuX2", .pmg_desc = "Floating point events by unit", .pmg_event_ids = power5p_group_event_ids[140], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000828a828aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 141 ] = { .pmg_name = "pm_fpuX3", .pmg_desc = "Floating point events by unit", .pmg_event_ids = power5p_group_event_ids[141], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000868e868eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 142 ] = { .pmg_name = "pm_fpuX4", .pmg_desc = "Floating point and L1 events", .pmg_event_ids = power5p_group_event_ids[142], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0030000020102020ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 143 ] = { .pmg_name = "pm_fpuX5", .pmg_desc = "Floating point events", .pmg_event_ids = power5p_group_event_ids[143], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000c2020868eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 144 ] = { .pmg_name = "pm_fpuX6", .pmg_desc = "Floating point events", .pmg_event_ids = power5p_group_event_ids[144], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000010202010ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 145 ] = { .pmg_name = "pm_fpuX7", .pmg_desc = "Floating point events", .pmg_event_ids = power5p_group_event_ids[145], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000220105010ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 146 ] = { .pmg_name = "pm_hpmcount8", .pmg_desc = "HPM group for set 9", .pmg_event_ids = power5p_group_event_ids[146], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000001e281e10ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 147 ] = { .pmg_name = "pm_hpmcount2", .pmg_desc = "HPM group for set 2", .pmg_event_ids = power5p_group_event_ids[147], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0430000412201220ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 148 ] = { .pmg_name = "pm_hpmcount3", .pmg_desc = "HPM group for set 3", .pmg_event_ids = power5p_group_event_ids[148], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x403000041ec21086ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 149 ] = { .pmg_name = "pm_hpmcount4", .pmg_desc = "HPM group for set 7", .pmg_event_ids = power5p_group_event_ids[149], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00b00000101e2020ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 150 ] = { .pmg_name = "pm_flop", .pmg_desc = "Floating point operations", .pmg_event_ids = power5p_group_event_ids[150], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000010105050ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 151 ] = { .pmg_name = "pm_eprof1", .pmg_desc = "Group for use with eprof", .pmg_event_ids = power5p_group_event_ids[151], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00300000121e108eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 152 ] = { .pmg_name = "pm_eprof2", .pmg_desc = "Group for use with eprof", .pmg_event_ids = power5p_group_event_ids[152], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0030000012501220ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 153 ] = { .pmg_name = "pm_flip", .pmg_desc = "Group for flips", .pmg_event_ids = power5p_group_event_ids[153], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000021e105010ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 154 ] = { .pmg_name = "pm_hpmcount5", .pmg_desc = "HPM group for set 5", .pmg_event_ids = power5p_group_event_ids[154], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00b000001e881020ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 155 ] = { .pmg_name = "pm_hpmcount6", .pmg_desc = "HPM group for set 6", .pmg_event_ids = power5p_group_event_ids[155], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x003000001e122086ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 156 ] = { .pmg_name = "pm_hpmcount7", .pmg_desc = "HPM group for set 8", .pmg_event_ids = power5p_group_event_ids[156], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00030005120e1e0eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 157 ] = { .pmg_name = "pm_ep_threshold", .pmg_desc = "Thresholding", .pmg_event_ids = power5p_group_event_ids[157], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000004121628ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 158 ] = { .pmg_name = "pm_ep_mrk_grp1", .pmg_desc = "Marked group events", .pmg_event_ids = power5p_group_event_ids[158], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000004120a26ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 159 ] = { .pmg_name = "pm_ep_mrk_grp2", .pmg_desc = "Marked group events", .pmg_event_ids = power5p_group_event_ids[159], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x410300032a12c822ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 160 ] = { .pmg_name = "pm_ep_mrk_dsource1", .pmg_desc = "Marked data from", .pmg_event_ids = power5p_group_event_ids[160], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x010b000b0e124444ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 161 ] = { .pmg_name = "pm_ep_mrk_dsource2", .pmg_desc = "Marked data from", .pmg_event_ids = power5p_group_event_ids[161], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x010b00082e12e410ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 162 ] = { .pmg_name = "pm_ep_mrk_dsource3", .pmg_desc = "Marked data from", .pmg_event_ids = power5p_group_event_ids[162], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x010b000712484c4cULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 163 ] = { .pmg_name = "pm_ep_mrk_dsource4", .pmg_desc = "Marked data from", .pmg_event_ids = power5p_group_event_ids[163], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x010b000712462e42ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 164 ] = { .pmg_name = "pm_ep_mrk_dsource5", .pmg_desc = "Marked data from", .pmg_event_ids = power5p_group_event_ids[164], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x010b000b3c124040ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 165 ] = { .pmg_name = "pm_ep_mrk_dsource6", .pmg_desc = "Marked data from", .pmg_event_ids = power5p_group_event_ids[165], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x010b000512460246ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 166 ] = { .pmg_name = "pm_ep_mrk_dsource7", .pmg_desc = "Marked data from", .pmg_event_ids = power5p_group_event_ids[166], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x010b0007124e3c4eULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 167 ] = { .pmg_name = "pm_ep_mrk_lbmiss", .pmg_desc = "Marked TLB and SLB misses", .pmg_event_ids = power5p_group_event_ids[167], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x020c0007121a1a1aULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 168 ] = { .pmg_name = "pm_ep_mrk_dtlbref", .pmg_desc = "Marked data TLB references", .pmg_event_ids = power5p_group_event_ids[168], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x020c0007120c0c0cULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 169 ] = { .pmg_name = "pm_ep_mrk_dtlbmiss", .pmg_desc = "Marked data TLB misses", .pmg_event_ids = power5p_group_event_ids[169], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x020c0007121a1a1aULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 170 ] = { .pmg_name = "pm_ep_mrk_lbref", .pmg_desc = "Marked TLB and SLB references", .pmg_event_ids = power5p_group_event_ids[170], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x063c000a0c120c8eULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 171 ] = { .pmg_name = "pm_ep_mrk_lsmiss", .pmg_desc = "Marked load and store miss", .pmg_event_ids = power5p_group_event_ids[171], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000800081012060aULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 172 ] = { .pmg_name = "pm_ep_mrk_ulsflush", .pmg_desc = "Mark unaligned load and store flushes", .pmg_event_ids = power5p_group_event_ids[172], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0020000006122020ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 173 ] = { .pmg_name = "pm_ep_mrk_misc1", .pmg_desc = "Misc marked instructions", .pmg_event_ids = power5p_group_event_ids[173], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000012062816ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 174 ] = { .pmg_name = "pm_ep_mrk_misc2", .pmg_desc = "Misc marked instructions", .pmg_event_ids = power5p_group_event_ids[174], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x010b000612445ee4ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 175 ] = { .pmg_name = "pm_ep_mrk_misc3", .pmg_desc = "Misc marked instructions", .pmg_event_ids = power5p_group_event_ids[175], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x053b0005124c8c0eULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 176 ] = { .pmg_name = "pm_ep_mrk_misc4", .pmg_desc = "Misc marked instructions", .pmg_event_ids = power5p_group_event_ids[176], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x030f00091a12e82eULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 177 ] = { .pmg_name = "pm_ep_mrk_misc5", .pmg_desc = "Misc marked instructions", .pmg_event_ids = power5p_group_event_ids[177], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x022c00080c120286ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 178 ] = { .pmg_name = "pm_ep_mrk_misc6", .pmg_desc = "Misc marked instructions", .pmg_event_ids = power5p_group_event_ids[178], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x022c00081a12888aULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 179 ] = { .pmg_name = "pm_ep_mrk_misc7", .pmg_desc = "Misc marked instructions", .pmg_event_ids = power5p_group_event_ids[179], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x012b000412408280ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 180 ] = { .pmg_name = "pm_ep_mrk_misc8", .pmg_desc = "Misc marked instructions", .pmg_event_ids = power5p_group_event_ids[180], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00200000120a8486ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 181 ] = { .pmg_name = "pm_ep_mrk_misc9", .pmg_desc = "Misc marked instructions", .pmg_event_ids = power5p_group_event_ids[181], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0028000012ac8eecULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 182 ] = { .pmg_name = "pm_ep_mrk_misc10", .pmg_desc = "Misc marked instructions", .pmg_event_ids = power5p_group_event_ids[182], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0008000412c0e8e6ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 183 ] = { .pmg_name = "pm_ep_mrk_misc11", .pmg_desc = "Misc marked instructions", .pmg_event_ids = power5p_group_event_ids[183], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x01030003120a443cULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 184 ] = { .pmg_name = "pm_ep_mrk_misc12", .pmg_desc = "Misc marked instructions", .pmg_event_ids = power5p_group_event_ids[184], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0020000012501010ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 185 ] = { .pmg_name = "pm_ep_mrk_misc13", .pmg_desc = "Misc marked instructions", .pmg_event_ids = power5p_group_event_ids[185], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0103000b0e1236ccULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 186 ] = { .pmg_name = "pm_ep_mrk_misc14", .pmg_desc = "Misc marked instructions", .pmg_event_ids = power5p_group_event_ids[186], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000012282828ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 187 ] = { .pmg_name = "pm_ep_mrk_misc15", .pmg_desc = "Misc marked instructions", .pmg_event_ids = power5p_group_event_ids[187], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4000000412220a26ULL, .pmg_mmcra = 0x0000000000000001ULL } }; #endif papi-5.5.1/src/libpfm-3.y/lib/pfmlib_power4_priv.h0000644000307100002310000000117313013651450021654 0ustar yarkhangraduate/****************************/ /* THIS IS OPEN SOURCE CODE */ /****************************/ #ifndef __PFMLIB_POWER4_PRIV_H__ #define __PFMLIB_POWER4_PRIV_H__ /* * File: pfmlib_power4_priv.h * CVS: * Author: Corey Ashford * cjashfor@us.ibm.com * Mods: * * * (C) Copyright IBM Corporation, 2007. All Rights Reserved. * Contributed by Corey Ashford * * Note: This code was automatically generated and should not be modified by * hand. * */ #define POWER4_NUM_EVENT_COUNTERS 8 #define POWER4_NUM_GROUP_VEC 1 #define POWER4_NUM_CONTROL_REGS 3 #endif papi-5.5.1/src/libpfm-3.y/lib/pfmlib_itanium.c0000644000307100002310000010161313013651450021035 0ustar yarkhangraduate/* * pfmlib_itanium.c : support for Itanium-family PMU * * Copyright (c) 2001-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include /* public headers */ #include /* private headers */ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_priv_ia64.h" /* architecture private */ #include "pfmlib_itanium_priv.h" /* PMU private */ #include "itanium_events.h" /* PMU private */ #define is_ear(i) event_is_ear(itanium_pe+(i)) #define is_ear_tlb(i) event_is_tlb_ear(itanium_pe+(i)) #define is_iear(i) event_is_iear(itanium_pe+(i)) #define is_dear(i) event_is_dear(itanium_pe+(i)) #define is_btb(i) event_is_btb(itanium_pe+(i)) #define has_opcm(i) event_opcm_ok(itanium_pe+(i)) #define has_iarr(i) event_iarr_ok(itanium_pe+(i)) #define has_darr(i) event_darr_ok(itanium_pe+(i)) #define evt_use_opcm(e) ((e)->pfp_ita_pmc8.opcm_used != 0 || (e)->pfp_ita_pmc9.opcm_used !=0) #define evt_use_irange(e) ((e)->pfp_ita_irange.rr_used) #define evt_use_drange(e) ((e)->pfp_ita_drange.rr_used) #define evt_umask(e) itanium_pe[(e)].pme_umask /* let's define some handy shortcuts! */ #define pmc_plm pmc_ita_count_reg.pmc_plm #define pmc_ev pmc_ita_count_reg.pmc_ev #define pmc_oi pmc_ita_count_reg.pmc_oi #define pmc_pm pmc_ita_count_reg.pmc_pm #define pmc_es pmc_ita_count_reg.pmc_es #define pmc_umask pmc_ita_count_reg.pmc_umask #define pmc_thres pmc_ita_count_reg.pmc_thres #define pmc_ism pmc_ita_count_reg.pmc_ism /* * Description of the PMC register mappings use by * this module (as reported in pfmlib_reg_t.reg_num): * * 0 -> PMC0 * 1 -> PMC1 * n -> PMCn * * The following are in the model specific rr_br[]: * IBR0 -> 0 * IBR1 -> 1 * ... * IBR7 -> 7 * DBR0 -> 0 * DBR1 -> 1 * ... * DBR7 -> 7 * * We do not use a mapping table, instead we make up the * values on the fly given the base. */ #define PFMLIB_ITA_PMC_BASE 0 static int pfm_ita_detect(void) { int ret = PFMLIB_ERR_NOTSUPP; /* * we support all chips (there is only one!) in the Itanium family */ if (pfm_ia64_get_cpu_family() == 0x07) ret = PFMLIB_SUCCESS; return ret; } /* * Part of the following code will eventually go into a perfmon library */ static int valid_assign(unsigned int *as, pfmlib_regmask_t *r_pmcs, unsigned int cnt) { unsigned int i; for(i=0; i < cnt; i++) { if (as[i]==0) return PFMLIB_ERR_NOASSIGN; /* * take care of restricted PMC registers */ if (pfm_regmask_isset(r_pmcs, as[i])) return PFMLIB_ERR_NOASSIGN; } return PFMLIB_SUCCESS; } /* * Automatically dispatch events to corresponding counters following constraints. */ static int pfm_ita_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_ita_input_param_t *mod_in, pfmlib_output_param_t *outp) { #define has_counter(e,b) (itanium_pe[e].pme_counters & (1 << (b)) ? (b) : 0) pfmlib_ita_input_param_t *param = mod_in; pfm_ita_pmc_reg_t reg; pfmlib_event_t *e; pfmlib_reg_t *pc, *pd; pfmlib_regmask_t *r_pmcs; unsigned int i,j,k,l, m; unsigned int max_l0, max_l1, max_l2, max_l3; unsigned int assign[PMU_ITA_NUM_COUNTERS]; unsigned int cnt; e = inp->pfp_events; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; cnt = inp->pfp_event_count; r_pmcs = &inp->pfp_unavail_pmcs; if (PFMLIB_DEBUG()) { for (m=0; m < cnt; m++) { DPRINT("ev[%d]=%s counters=0x%lx\n", m, itanium_pe[e[m].event].pme_name, itanium_pe[e[m].event].pme_counters); } } if (cnt > PMU_ITA_NUM_COUNTERS) return PFMLIB_ERR_TOOMANY; max_l0 = PMU_ITA_FIRST_COUNTER + PMU_ITA_NUM_COUNTERS; max_l1 = PMU_ITA_FIRST_COUNTER + PMU_ITA_NUM_COUNTERS*(cnt>1); max_l2 = PMU_ITA_FIRST_COUNTER + PMU_ITA_NUM_COUNTERS*(cnt>2); max_l3 = PMU_ITA_FIRST_COUNTER + PMU_ITA_NUM_COUNTERS*(cnt>3); DPRINT("max_l0=%u max_l1=%u max_l2=%u max_l3=%u\n", max_l0, max_l1, max_l2, max_l3); /* * This code needs fixing. It is not very pretty and * won't handle more than 4 counters if more become * available ! * For now, worst case in the loop nest: 4! (factorial) */ for (i=PMU_ITA_FIRST_COUNTER; i < max_l0; i++) { assign[0]= has_counter(e[0].event,i); if (max_l1 == PMU_ITA_FIRST_COUNTER && valid_assign(assign, r_pmcs, cnt) == PFMLIB_SUCCESS) goto done; for (j=PMU_ITA_FIRST_COUNTER; j < max_l1; j++) { if (j == i) continue; assign[1] = has_counter(e[1].event,j); if (max_l2 == PMU_ITA_FIRST_COUNTER && valid_assign(assign, r_pmcs, cnt) == PFMLIB_SUCCESS) goto done; for (k=PMU_ITA_FIRST_COUNTER; k < max_l2; k++) { if(k == i || k == j) continue; assign[2] = has_counter(e[2].event,k); if (max_l3 == PMU_ITA_FIRST_COUNTER && valid_assign(assign, r_pmcs, cnt) == PFMLIB_SUCCESS) goto done; for (l=PMU_ITA_FIRST_COUNTER; l < max_l3; l++) { if(l == i || l == j || l == k) continue; assign[3] = has_counter(e[3].event,l); if (valid_assign(assign, r_pmcs, cnt) == PFMLIB_SUCCESS) goto done; } } } } /* we cannot satisfy the constraints */ return PFMLIB_ERR_NOASSIGN; done: for (j=0; j < cnt ; j++ ) { reg.pmc_val = 0; /* clear all */ /* if plm is 0, then assume not specified per-event and use default */ reg.pmc_plm = e[j].plm ? e[j].plm : inp->pfp_dfl_plm; reg.pmc_oi = 1; /* overflow interrupt */ reg.pmc_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc_thres = param ? param->pfp_ita_counters[j].thres: 0; reg.pmc_ism = param ? param->pfp_ita_counters[j].ism : PFMLIB_ITA_ISM_BOTH; reg.pmc_umask = is_ear(e[j].event) ? 0x0 : evt_umask(e[j].event); reg.pmc_es = itanium_pe[e[j].event].pme_code; pc[j].reg_num = assign[j]; pc[j].reg_value = reg.pmc_val; pc[j].reg_addr = assign[j]; pc[j].reg_alt_addr= assign[j]; pd[j].reg_num = assign[j]; pd[j].reg_addr = assign[j]; pd[j].reg_alt_addr = assign[j]; __pfm_vbprintf("[PMC%u(pmc%u)=0x%06lx thres=%d es=0x%02x plm=%d umask=0x%x pm=%d ism=0x%x oi=%d] %s\n", assign[j], assign[j], reg.pmc_val, reg.pmc_thres, reg.pmc_es,reg.pmc_plm, reg.pmc_umask, reg.pmc_pm, reg.pmc_ism, reg.pmc_oi, itanium_pe[e[j].event].pme_name); __pfm_vbprintf("[PMD%u(pmd%u)]\n", pd[j].reg_num, pd[j].reg_num); } /* number of PMC registers programmed */ outp->pfp_pmc_count = cnt; outp->pfp_pmd_count = cnt; return PFMLIB_SUCCESS; } static int pfm_dispatch_iear(pfmlib_input_param_t *inp, pfmlib_ita_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfm_ita_pmc_reg_t reg; pfmlib_ita_input_param_t *param = mod_in; pfmlib_ita_input_param_t fake_param; pfmlib_reg_t *pc, *pd; unsigned int pos1, pos2; int iear_idx = -1; unsigned int i, count; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; pos1 = outp->pfp_pmc_count; pos2 = outp->pfp_pmd_count; count = inp->pfp_event_count; for (i=0; i < count; i++) { if (is_iear(inp->pfp_events[i].event)) iear_idx = i; } if (param == NULL || mod_in->pfp_ita_iear.ear_used == 0) { /* * case 3: no I-EAR event, no (or nothing) in param->pfp_ita2_iear.ear_used */ if (iear_idx == -1) return PFMLIB_SUCCESS; memset(&fake_param, 0, sizeof(fake_param)); param = &fake_param; pfm_ita_get_ear_mode(inp->pfp_events[iear_idx].event, ¶m->pfp_ita_iear.ear_mode); param->pfp_ita_iear.ear_umask = evt_umask(inp->pfp_events[iear_idx].event); param->pfp_ita_iear.ear_ism = PFMLIB_ITA_ISM_BOTH; /* force both instruction sets */ DPRINT("I-EAR event with no info\n"); } /* sanity check on the mode */ if (param->pfp_ita_iear.ear_mode < 0 || param->pfp_ita_iear.ear_mode > 2) return PFMLIB_ERR_INVAL; /* * case 2: ear_used=1, event is defined, we use the param info as it is more precise * case 4: ear_used=1, no event (free running I-EAR), use param info */ reg.pmc_val = 0; /* if plm is 0, then assume not specified per-event and use default */ reg.pmc10_ita_reg.iear_plm = param->pfp_ita_iear.ear_plm ? param->pfp_ita_iear.ear_plm : inp->pfp_dfl_plm; reg.pmc10_ita_reg.iear_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc10_ita_reg.iear_tlb = param->pfp_ita_iear.ear_mode; reg.pmc10_ita_reg.iear_umask = param->pfp_ita_iear.ear_umask; reg.pmc10_ita_reg.iear_ism = param->pfp_ita_iear.ear_ism; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 10)) return PFMLIB_ERR_NOASSIGN; pc[pos1].reg_num = 10; /* PMC10 is I-EAR config register */ pc[pos1].reg_value = reg.pmc_val; pc[pos1].reg_addr = 10; pc[pos1].reg_alt_addr= 10; pos1++; pd[pos2].reg_num = 0; pd[pos2].reg_addr = 0; pd[pos2].reg_alt_addr = 0; pos2++; pd[pos2].reg_num = 1; pd[pos2].reg_addr = 1; pd[pos2].reg_alt_addr = 1; pos2++; __pfm_vbprintf("[PMC10(pmc10)=0x%lx tlb=%s plm=%d pm=%d ism=0x%x umask=0x%x]\n", reg.pmc_val, reg.pmc10_ita_reg.iear_tlb ? "Yes" : "No", reg.pmc10_ita_reg.iear_plm, reg.pmc10_ita_reg.iear_pm, reg.pmc10_ita_reg.iear_ism, reg.pmc10_ita_reg.iear_umask); __pfm_vbprintf("[PMD0(pmd0)]\n[PMD1(pmd1)\n"); /* update final number of entries used */ outp->pfp_pmc_count = pos1; outp->pfp_pmd_count = pos2; return PFMLIB_SUCCESS; } static int pfm_dispatch_dear(pfmlib_input_param_t *inp, pfmlib_ita_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfm_ita_pmc_reg_t reg; pfmlib_ita_input_param_t *param = mod_in; pfmlib_ita_input_param_t fake_param; pfmlib_reg_t *pc, *pd; unsigned int pos1, pos2; int dear_idx = -1; unsigned int i, count; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; pos1 = outp->pfp_pmc_count; pos2 = outp->pfp_pmd_count; count = inp->pfp_event_count; for (i=0; i < count; i++) { if (is_dear(inp->pfp_events[i].event)) dear_idx = i; } if (param == NULL || param->pfp_ita_dear.ear_used == 0) { /* * case 3: no D-EAR event, no (or nothing) in param->pfp_ita2_dear.ear_used */ if (dear_idx == -1) return PFMLIB_SUCCESS; memset(&fake_param, 0, sizeof(fake_param)); param = &fake_param; pfm_ita_get_ear_mode(inp->pfp_events[dear_idx].event, ¶m->pfp_ita_dear.ear_mode); param->pfp_ita_dear.ear_umask = evt_umask(inp->pfp_events[dear_idx].event); param->pfp_ita_dear.ear_ism = PFMLIB_ITA_ISM_BOTH; /* force both instruction sets */ DPRINT("D-EAR event with no info\n"); } /* sanity check on the mode */ if (param->pfp_ita_dear.ear_mode > 2) return PFMLIB_ERR_INVAL; /* * case 2: ear_used=1, event is defined, we use the param info as it is more precise * case 4: ear_used=1, no event (free running D-EAR), use param info */ reg.pmc_val = 0; /* if plm is 0, then assume not specified per-event and use default */ reg.pmc11_ita_reg.dear_plm = param->pfp_ita_dear.ear_plm ? param->pfp_ita_dear.ear_plm : inp->pfp_dfl_plm; reg.pmc11_ita_reg.dear_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc11_ita_reg.dear_tlb = param->pfp_ita_dear.ear_mode; reg.pmc11_ita_reg.dear_ism = param->pfp_ita_dear.ear_ism; reg.pmc11_ita_reg.dear_umask = param->pfp_ita_dear.ear_umask; reg.pmc11_ita_reg.dear_pt = param->pfp_ita_drange.rr_used ? 0: 1; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 11)) return PFMLIB_ERR_NOASSIGN; pc[pos1].reg_num = 11; /* PMC11 is D-EAR config register */ pc[pos1].reg_value = reg.pmc_val; pc[pos1].reg_addr = 11; pos1++; pd[pos2].reg_num = 2; pd[pos2].reg_addr = 2; pd[pos2].reg_alt_addr = 2; pos2++; pd[pos2].reg_num = 3; pd[pos2].reg_addr = 3; pd[pos2].reg_alt_addr = 3; pos2++; pd[pos2].reg_num = 17; pd[pos2].reg_addr = 17; pd[pos2].reg_alt_addr = 17; pos2++; __pfm_vbprintf("[PMC11(pmc11)=0x%lx tlb=%s plm=%d pm=%d ism=0x%x umask=0x%x pt=%d]\n", reg.pmc_val, reg.pmc11_ita_reg.dear_tlb ? "Yes" : "No", reg.pmc11_ita_reg.dear_plm, reg.pmc11_ita_reg.dear_pm, reg.pmc11_ita_reg.dear_ism, reg.pmc11_ita_reg.dear_umask, reg.pmc11_ita_reg.dear_pt); __pfm_vbprintf("[PMD2(pmd2)]\n[PMD3(pmd3)\nPMD17(pmd17)\n"); /* update final number of entries used */ outp->pfp_pmc_count = pos1; outp->pfp_pmd_count = pos2; return PFMLIB_SUCCESS; } static int pfm_dispatch_opcm(pfmlib_input_param_t *inp, pfmlib_ita_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfmlib_ita_input_param_t *param = mod_in; pfm_ita_pmc_reg_t reg; pfmlib_reg_t *pc = outp->pfp_pmcs; int pos = outp->pfp_pmc_count; if (param == NULL) return PFMLIB_SUCCESS; if (param->pfp_ita_pmc8.opcm_used) { reg.pmc_val = param->pfp_ita_pmc8.pmc_val; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 8)) return PFMLIB_ERR_NOASSIGN; pc[pos].reg_num = 8; pc[pos].reg_value = reg.pmc_val; pc[pos].reg_addr = 8; pc[pos].reg_alt_addr = 8; pos++; __pfm_vbprintf("[PMC8(pmc8)=0x%lx m=%d i=%d f=%d b=%d match=0x%x mask=0x%x]\n", reg.pmc_val, reg.pmc8_9_ita_reg.m, reg.pmc8_9_ita_reg.i, reg.pmc8_9_ita_reg.f, reg.pmc8_9_ita_reg.b, reg.pmc8_9_ita_reg.match, reg.pmc8_9_ita_reg.mask); } if (param->pfp_ita_pmc9.opcm_used) { reg.pmc_val = param->pfp_ita_pmc9.pmc_val; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 9)) return PFMLIB_ERR_NOASSIGN; pc[pos].reg_num = 9; pc[pos].reg_value = reg.pmc_val; pc[pos].reg_addr = 9; pc[pos].reg_alt_addr = 9; pos++; __pfm_vbprintf("[PMC9(pmc9)=0x%lx m=%d i=%d f=%d b=%d match=0x%x mask=0x%x]\n", reg.pmc_val, reg.pmc8_9_ita_reg.m, reg.pmc8_9_ita_reg.i, reg.pmc8_9_ita_reg.f, reg.pmc8_9_ita_reg.b, reg.pmc8_9_ita_reg.match, reg.pmc8_9_ita_reg.mask); } outp->pfp_pmc_count = pos; return PFMLIB_SUCCESS; } static int pfm_dispatch_btb(pfmlib_input_param_t *inp, pfmlib_ita_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfm_ita_pmc_reg_t reg; pfmlib_ita_input_param_t *param = mod_in; pfmlib_ita_input_param_t fake_param; pfmlib_reg_t *pc, *pd; int found_btb=0; unsigned int i, count; unsigned int pos1, pos2; reg.pmc_val = 0; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; pos1 = outp->pfp_pmc_count; pos2 = outp->pfp_pmd_count; count = inp->pfp_event_count; for (i=0; i < count; i++) { if (is_btb(inp->pfp_events[i].event)) found_btb = 1; } if (param == NULL || param->pfp_ita_btb.btb_used == 0) { /* * case 3: no BTB event, no param */ if (found_btb == 0) return PFMLIB_SUCCESS; /* * case 1: BTB event, no param, capture all branches */ memset(&fake_param, 0, sizeof(fake_param)); param = &fake_param; param->pfp_ita_btb.btb_tar = 0x1; /* capture TAR */ param->pfp_ita_btb.btb_tm = 0x3; /* all branches */ param->pfp_ita_btb.btb_ptm = 0x3; /* all branches */ param->pfp_ita_btb.btb_ppm = 0x3; /* all branches */ param->pfp_ita_btb.btb_tac = 0x1; /* capture TAC */ param->pfp_ita_btb.btb_bac = 0x1; /* capture BAC */ DPRINT("BTB event with no info\n"); } /* * case 2: BTB event, param * case 4: no BTB event, param (free running mode) */ /* if plm is 0, then assume not specified per-event and use default */ reg.pmc12_ita_reg.btbc_plm = param->pfp_ita_btb.btb_plm ? param->pfp_ita_btb.btb_plm : inp->pfp_dfl_plm; reg.pmc12_ita_reg.btbc_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc12_ita_reg.btbc_tar = param->pfp_ita_btb.btb_tar & 0x1; reg.pmc12_ita_reg.btbc_tm = param->pfp_ita_btb.btb_tm & 0x3; reg.pmc12_ita_reg.btbc_ptm = param->pfp_ita_btb.btb_ptm & 0x3; reg.pmc12_ita_reg.btbc_ppm = param->pfp_ita_btb.btb_ppm & 0x3; reg.pmc12_ita_reg.btbc_bpt = param->pfp_ita_btb.btb_tac & 0x1; reg.pmc12_ita_reg.btbc_bac = param->pfp_ita_btb.btb_bac & 0x1; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 12)) return PFMLIB_ERR_NOASSIGN; pc[pos1].reg_num = 12; pc[pos1].reg_value = reg.pmc_val; pc[pos1].reg_value = 12; pos1++; __pfm_vbprintf("[PMC12(pmc12)=0x%lx plm=%d pm=%d tar=%d tm=%d ptm=%d ppm=%d bpt=%d bac=%d]\n", reg.pmc_val, reg.pmc12_ita_reg.btbc_plm, reg.pmc12_ita_reg.btbc_pm, reg.pmc12_ita_reg.btbc_tar, reg.pmc12_ita_reg.btbc_tm, reg.pmc12_ita_reg.btbc_ptm, reg.pmc12_ita_reg.btbc_ppm, reg.pmc12_ita_reg.btbc_bpt, reg.pmc12_ita_reg.btbc_bac); /* * PMD16 is included in list of used PMD */ for(i=8; i < 17; i++, pos2++) { pd[pos2].reg_num = i; pd[pos2].reg_addr = i; pd[pos2].reg_alt_addr = i; __pfm_vbprintf("[PMD%u(pmd%u)]\n", pd[pos2].reg_num, pd[pos2].reg_num); } /* update final number of entries used */ outp->pfp_pmc_count = pos1; outp->pfp_pmd_count = pos2; return PFMLIB_SUCCESS; } /* * mode = 0 -> check code (enforce bundle alignment) * mode = 1 -> check data */ static int check_intervals(pfmlib_ita_input_rr_t *irr, int mode, int *n_intervals) { int i; pfmlib_ita_input_rr_desc_t *lim = irr->rr_limits; for(i=0; i < 4; i++) { /* end marker */ if (lim[i].rr_start == 0 && lim[i].rr_end == 0) break; /* invalid entry */ if (lim[i].rr_start >= lim[i].rr_end) return PFMLIB_ERR_IRRINVAL; if (mode == 0 && (lim[i].rr_start & 0xf || lim[i].rr_end & 0xf)) return PFMLIB_ERR_IRRALIGN; } *n_intervals = i; return PFMLIB_SUCCESS; } static void do_normal_rr(unsigned long start, unsigned long end, pfmlib_reg_t *br, int nbr, int dir, int *idx, int *reg_idx, int plm) { unsigned long size, l_addr, c; unsigned long l_offs = 0, r_offs = 0; unsigned long l_size, r_size; dbreg_t db; int p2; if (nbr < 1 || end <= start) return; size = end - start; DPRINT("start=0x%016lx end=0x%016lx size=0x%lx bytes (%lu bundles) nbr=%d dir=%d\n", start, end, size, size >> 4, nbr, dir); p2 = pfm_ia64_fls(size); c = ALIGN_DOWN(end, p2); DPRINT("largest power of two possible: 2^%d=0x%lx, crossing=0x%016lx\n", p2, 1UL << p2, c); if ((c - (1UL<= start) { l_addr = c - (1UL << p2); } else { p2--; if ((c + (1UL<>l_offs: 0x%lx\n", l_offs); } } else if (dir == 1 && r_size != 0 && nbr == 1) { p2++; l_addr = start; if (PFMLIB_DEBUG()) { r_offs = l_addr+(1UL<>r_offs: 0x%lx\n", r_offs); } } l_size = l_addr - start; r_size = end - l_addr-(1UL<>largest chunk: 2^%d @0x%016lx-0x%016lx\n", p2, l_addr, l_addr+(1UL<>before: 0x%016lx-0x%016lx\n", start, l_addr); if (r_size && !r_offs) DPRINT(">>after : 0x%016lx-0x%016lx\n", l_addr+(1UL<>1; if (nbr & 0x1) { /* * our simple heuristic is: * we assign the largest number of registers to the largest * of the two chunks */ if (l_size > r_size) { l_nbr++; } else { r_nbr++; } } do_normal_rr(start, l_addr, br, l_nbr, 0, idx, reg_idx, plm); do_normal_rr(l_addr+(1UL<rr_start, in_rr->rr_end, n_pairs); __pfm_vbprintf("start offset: -0x%lx end_offset: +0x%lx\n", out_rr->rr_soff, out_rr->rr_eoff); for (j=0; j < n_pairs; j++, base_idx += 2) { d.val = dbr[base_idx+1].reg_value; r_end = dbr[base_idx].reg_value+((~(d.db.db_mask)) & ~(0xffUL << 56)); __pfm_vbprintf("brp%u: db%u: 0x%016lx db%u: plm=0x%x mask=0x%016lx end=0x%016lx\n", dbr[base_idx].reg_num>>1, dbr[base_idx].reg_num, dbr[base_idx].reg_value, dbr[base_idx+1].reg_num, d.db.db_plm, (unsigned long) d.db.db_mask, r_end); } } static int compute_normal_rr(pfmlib_ita_input_rr_t *irr, int dfl_plm, int n, int *base_idx, pfmlib_ita_output_rr_t *orr) { pfmlib_ita_input_rr_desc_t *in_rr; pfmlib_ita_output_rr_desc_t *out_rr; unsigned long r_end; pfmlib_reg_t *br; dbreg_t d; int i, j, br_index, reg_idx, prev_index; in_rr = irr->rr_limits; out_rr = orr->rr_infos; br = orr->rr_br; reg_idx = *base_idx; br_index = 0; for (i=0; i < n; i++, in_rr++, out_rr++) { /* * running out of registers */ if (br_index == 8) break; prev_index = br_index; do_normal_rr( in_rr->rr_start, in_rr->rr_end, br, 4 - (reg_idx>>1), /* how many pairs available */ 0, &br_index, ®_idx, in_rr->rr_plm ? in_rr->rr_plm : dfl_plm); DPRINT("br_index=%d reg_idx=%d\n", br_index, reg_idx); /* * compute offsets */ out_rr->rr_soff = out_rr->rr_eoff = 0; for(j=prev_index; j < br_index; j+=2) { d.val = br[j+1].reg_value; r_end = br[j].reg_value+((~(d.db.db_mask)+1) & ~(0xffUL << 56)); if (br[j].reg_value <= in_rr->rr_start) out_rr->rr_soff = in_rr->rr_start - br[j].reg_value; if (r_end >= in_rr->rr_end) out_rr->rr_eoff = r_end - in_rr->rr_end; } if (PFMLIB_VERBOSE()) print_one_range(in_rr, out_rr, br, prev_index, (br_index-prev_index)>>1); } /* do not have enough registers to cover all the ranges */ if (br_index == 8 && i < n) return PFMLIB_ERR_TOOMANY; orr->rr_nbr_used = br_index; return PFMLIB_SUCCESS; } static int pfm_dispatch_irange(pfmlib_input_param_t *inp, pfmlib_ita_input_param_t *mod_in, pfmlib_output_param_t *outp, pfmlib_ita_output_param_t *mod_out) { pfm_ita_pmc_reg_t reg; pfmlib_ita_input_param_t *param = mod_in; pfmlib_reg_t *pc = outp->pfp_pmcs; pfmlib_ita_input_rr_t *irr; pfmlib_ita_output_rr_t *orr; int pos = outp->pfp_pmc_count; int ret, base_idx = 0; int n_intervals; if (param == NULL || param->pfp_ita_irange.rr_used == 0) return PFMLIB_SUCCESS; if (mod_out == NULL) return PFMLIB_ERR_INVAL; irr = ¶m->pfp_ita_irange; orr = &mod_out->pfp_ita_irange; ret = check_intervals(irr, 0, &n_intervals); if (ret != PFMLIB_SUCCESS) return ret; if (n_intervals < 1) return PFMLIB_ERR_IRRINVAL; DPRINT("n_intervals=%d\n", n_intervals); ret = compute_normal_rr(irr, inp->pfp_dfl_plm, n_intervals, &base_idx, orr); if (ret != PFMLIB_SUCCESS) { return ret == PFMLIB_ERR_TOOMANY ? PFMLIB_ERR_IRRTOOMANY : ret; } reg.pmc_val = 0; reg.pmc13_ita_reg.irange_ta = 0x0; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 13)) return PFMLIB_ERR_NOASSIGN; pc[pos].reg_num = 13; pc[pos].reg_value = reg.pmc_val; pc[pos].reg_addr = 13; pc[pos].reg_alt_addr= 13; pos++; __pfm_vbprintf("[PMC13(pmc13)=0x%lx ta=%d]\n", reg.pmc_val, reg.pmc13_ita_reg.irange_ta); outp->pfp_pmc_count = pos; return PFMLIB_SUCCESS; } static int pfm_dispatch_drange(pfmlib_input_param_t *inp, pfmlib_ita_input_param_t *mod_in, pfmlib_output_param_t *outp, pfmlib_ita_output_param_t *mod_out) { pfmlib_ita_input_param_t *param = mod_in; pfmlib_event_t *e = inp->pfp_events; pfmlib_reg_t *pc = outp->pfp_pmcs; pfmlib_ita_input_rr_t *irr; pfmlib_ita_output_rr_t *orr; pfm_ita_pmc_reg_t reg; unsigned int i, count; int pos = outp->pfp_pmc_count; int ret, base_idx = 0; int n_intervals; if (param == NULL || param->pfp_ita_drange.rr_used == 0) return PFMLIB_SUCCESS; if (mod_out == NULL) return PFMLIB_ERR_INVAL; irr = ¶m->pfp_ita_drange; orr = &mod_out->pfp_ita_drange; ret = check_intervals(irr, 1 , &n_intervals); if (ret != PFMLIB_SUCCESS) return ret; if (n_intervals < 1) return PFMLIB_ERR_DRRINVAL; DPRINT("n_intervals=%d\n", n_intervals); ret = compute_normal_rr(irr, inp->pfp_dfl_plm, n_intervals, &base_idx, orr); if (ret != PFMLIB_SUCCESS) { return ret == PFMLIB_ERR_TOOMANY ? PFMLIB_ERR_DRRTOOMANY : ret; } count = inp->pfp_event_count; for (i=0; i < count; i++) { if (is_dear(e[i].event)) return PFMLIB_SUCCESS; /* will be done there */ } reg.pmc_val = 0UL; /* * here we have no other choice but to use the default priv level as there is no * specific D-EAR event provided */ reg.pmc11_ita_reg.dear_plm = inp->pfp_dfl_plm; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 11)) return PFMLIB_ERR_NOASSIGN; pc[pos].reg_num = 11; pc[pos].reg_value = reg.pmc_val; pc[pos].reg_addr = 11; pc[pos].reg_alt_addr= 11; pos++; __pfm_vbprintf("[PMC11(pmc11)=0x%lx tlb=%s plm=%d pm=%d ism=0x%x umask=0x%x pt=%d]\n", reg.pmc_val, reg.pmc11_ita_reg.dear_tlb ? "Yes" : "No", reg.pmc11_ita_reg.dear_plm, reg.pmc11_ita_reg.dear_pm, reg.pmc11_ita_reg.dear_ism, reg.pmc11_ita_reg.dear_umask, reg.pmc11_ita_reg.dear_pt); outp->pfp_pmc_count = pos; return PFMLIB_SUCCESS; } static int check_qualifier_constraints(pfmlib_input_param_t *inp, pfmlib_ita_input_param_t *mod_in) { pfmlib_event_t *e = inp->pfp_events; unsigned int i, count; count = inp->pfp_event_count; for(i=0; i < count; i++) { /* * skip check for counter which requested it. Use at your own risk. * No all counters have necessarily been validated for use with * qualifiers. Typically the event is counted as if no constraint * existed. */ if (mod_in->pfp_ita_counters[i].flags & PFMLIB_ITA_FL_EVT_NO_QUALCHECK) continue; if (evt_use_irange(mod_in) && has_iarr(e[i].event) == 0) return PFMLIB_ERR_FEATCOMB; if (evt_use_drange(mod_in) && has_darr(e[i].event) == 0) return PFMLIB_ERR_FEATCOMB; if (evt_use_opcm(mod_in) && has_opcm(e[i].event) == 0) return PFMLIB_ERR_FEATCOMB; } return PFMLIB_SUCCESS; } static int check_range_plm(pfmlib_input_param_t *inp, pfmlib_ita_input_param_t *mod_in) { unsigned int i, count; if (mod_in->pfp_ita_drange.rr_used == 0 && mod_in->pfp_ita_irange.rr_used == 0) return PFMLIB_SUCCESS; /* * range restriction applies to all events, therefore we must have a consistent * set of plm and they must match the pfp_dfl_plm which is used to setup the debug * registers */ count = inp->pfp_event_count; for(i=0; i < count; i++) { if (inp->pfp_events[i].plm && inp->pfp_events[i].plm != inp->pfp_dfl_plm) return PFMLIB_ERR_FEATCOMB; } return PFMLIB_SUCCESS; } static int pfm_ita_dispatch_events(pfmlib_input_param_t *inp, void *model_in, pfmlib_output_param_t *outp, void *model_out) { int ret; pfmlib_ita_input_param_t *mod_in = (pfmlib_ita_input_param_t *)model_in; pfmlib_ita_output_param_t *mod_out = (pfmlib_ita_output_param_t *)model_out; /* * nothing will come out of this combination */ if (mod_out && mod_in == NULL) return PFMLIB_ERR_INVAL; /* check opcode match, range restriction qualifiers */ if (mod_in && check_qualifier_constraints(inp, mod_in) != PFMLIB_SUCCESS) return PFMLIB_ERR_FEATCOMB; /* check for problems with raneg restriction and per-event plm */ if (mod_in && check_range_plm(inp, mod_in) != PFMLIB_SUCCESS) return PFMLIB_ERR_FEATCOMB; ret = pfm_ita_dispatch_counters(inp, mod_in, outp); if (ret != PFMLIB_SUCCESS) return ret; /* now check for I-EAR */ ret = pfm_dispatch_iear(inp, mod_in, outp); if (ret != PFMLIB_SUCCESS) return ret; /* now check for D-EAR */ ret = pfm_dispatch_dear(inp, mod_in, outp); if (ret != PFMLIB_SUCCESS) return ret; /* now check for Opcode matchers */ ret = pfm_dispatch_opcm(inp, mod_in, outp); if (ret != PFMLIB_SUCCESS) return ret; ret = pfm_dispatch_btb(inp, mod_in, outp); if (ret != PFMLIB_SUCCESS) return ret; ret = pfm_dispatch_irange(inp, mod_in, outp, mod_out);; if (ret != PFMLIB_SUCCESS) return ret; ret = pfm_dispatch_drange(inp, mod_in, outp, mod_out);; return ret; } /* XXX: return value is also error code */ int pfm_ita_get_event_maxincr(unsigned int i, unsigned int *maxincr) { if (i >= PME_ITA_EVENT_COUNT || maxincr == NULL) return PFMLIB_ERR_INVAL; *maxincr = itanium_pe[i].pme_maxincr; return PFMLIB_SUCCESS; } int pfm_ita_is_ear(unsigned int i) { return i >= PME_ITA_EVENT_COUNT || ! is_ear(i) ? 0 : 1; } int pfm_ita_is_dear(unsigned int i) { return i >= PME_ITA_EVENT_COUNT || ! is_dear(i) ? 0 : 1; } int pfm_ita_is_dear_tlb(unsigned int i) { return i >= PME_ITA_EVENT_COUNT || ! (is_dear(i) && is_ear_tlb(i)) ? 0 : 1; } int pfm_ita_is_dear_cache(unsigned int i) { return i >= PME_ITA_EVENT_COUNT || ! (is_dear(i) && !is_ear_tlb(i)) ? 0 : 1; } int pfm_ita_is_iear(unsigned int i) { return i >= PME_ITA_EVENT_COUNT || ! is_iear(i) ? 0 : 1; } int pfm_ita_is_iear_tlb(unsigned int i) { return i >= PME_ITA_EVENT_COUNT || ! (is_iear(i) && is_ear_tlb(i)) ? 0 : 1; } int pfm_ita_is_iear_cache(unsigned int i) { return i >= PME_ITA_EVENT_COUNT || ! (is_iear(i) && !is_ear_tlb(i)) ? 0 : 1; } int pfm_ita_is_btb(unsigned int i) { return i >= PME_ITA_EVENT_COUNT || ! is_btb(i) ? 0 : 1; } int pfm_ita_support_iarr(unsigned int i) { return i >= PME_ITA_EVENT_COUNT || ! has_iarr(i) ? 0 : 1; } int pfm_ita_support_darr(unsigned int i) { return i >= PME_ITA_EVENT_COUNT || ! has_darr(i) ? 0 : 1; } int pfm_ita_support_opcm(unsigned int i) { return i >= PME_ITA_EVENT_COUNT || ! has_opcm(i) ? 0 : 1; } int pfm_ita_get_ear_mode(unsigned int i, pfmlib_ita_ear_mode_t *m) { if (!is_ear(i) || m == NULL) return PFMLIB_ERR_INVAL; *m = is_ear_tlb(i) ? PFMLIB_ITA_EAR_TLB_MODE : PFMLIB_ITA_EAR_CACHE_MODE; return PFMLIB_SUCCESS; } static int pfm_ita_get_event_code(unsigned int i, unsigned int cnt, int *code) { if (cnt != PFMLIB_CNT_FIRST && (cnt < 4 || cnt > 7)) return PFMLIB_ERR_INVAL; *code = (int)itanium_pe[i].pme_code; return PFMLIB_SUCCESS; } /* * This function is accessible directly to the user */ int pfm_ita_get_event_umask(unsigned int i, unsigned long *umask) { if (i >= PME_ITA_EVENT_COUNT || umask == NULL) return PFMLIB_ERR_INVAL; *umask = evt_umask(i); return PFMLIB_SUCCESS; } static char * pfm_ita_get_event_name(unsigned int i) { return itanium_pe[i].pme_name; } static void pfm_ita_get_event_counters(unsigned int j, pfmlib_regmask_t *counters) { unsigned int i; unsigned long m; memset(counters, 0, sizeof(*counters)); m =itanium_pe[j].pme_counters; for(i=0; m ; i++, m>>=1) { if (m & 0x1) pfm_regmask_set(counters, i); } } static void pfm_ita_get_impl_pmcs(pfmlib_regmask_t *impl_pmcs) { unsigned int i = 0; /* all pmcs are contiguous */ for(i=0; i < PMU_ITA_NUM_PMCS; i++) pfm_regmask_set(impl_pmcs, i); } static void pfm_ita_get_impl_pmds(pfmlib_regmask_t *impl_pmds) { unsigned int i = 0; /* all pmds are contiguous */ for(i=0; i < PMU_ITA_NUM_PMDS; i++) pfm_regmask_set(impl_pmds, i); } static void pfm_ita_get_impl_counters(pfmlib_regmask_t *impl_counters) { unsigned int i = 0; /* counting pmds are contiguous */ for(i=4; i < 8; i++) pfm_regmask_set(impl_counters, i); } static void pfm_ita_get_hw_counter_width(unsigned int *width) { *width = PMU_ITA_COUNTER_WIDTH; } static int pfm_ita_get_cycle_event(pfmlib_event_t *e) { e->event = PME_ITA_CPU_CYCLES; return PFMLIB_SUCCESS; } static int pfm_ita_get_inst_retired(pfmlib_event_t *e) { e->event = PME_ITA_IA64_INST_RETIRED; return PFMLIB_SUCCESS; } pfm_pmu_support_t itanium_support={ .pmu_name = "itanium", .pmu_type = PFMLIB_ITANIUM_PMU, .pme_count = PME_ITA_EVENT_COUNT, .pmc_count = PMU_ITA_NUM_PMCS, .pmd_count = PMU_ITA_NUM_PMDS, .num_cnt = PMU_ITA_NUM_COUNTERS, .get_event_code = pfm_ita_get_event_code, .get_event_name = pfm_ita_get_event_name, .get_event_counters = pfm_ita_get_event_counters, .dispatch_events = pfm_ita_dispatch_events, .pmu_detect = pfm_ita_detect, .get_impl_pmcs = pfm_ita_get_impl_pmcs, .get_impl_pmds = pfm_ita_get_impl_pmds, .get_impl_counters = pfm_ita_get_impl_counters, .get_hw_counter_width = pfm_ita_get_hw_counter_width, .get_cycle_event = pfm_ita_get_cycle_event, .get_inst_retired_event = pfm_ita_get_inst_retired /* no event description available for Itanium */ }; papi-5.5.1/src/libpfm-3.y/lib/amd64_events_fam15h.h0000644000307100002310000020031013013651450021475 0ustar yarkhangraduate/* * Copyright (c) 2010 Advanced Micro Devices, Inc. * Contributed by Robert Richter * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ /* * Family 15h Microarchitecture performance monitor events * * History: * * Apr 29 2011 -- Robert Richter, robert.richter@amd.com: * Source: BKDG for AMD Family 15h Models 00h-0Fh Processors, * 42301, Rev 1.15, April 18, 2011 * * Dec 09 2010 -- Robert Richter, robert.richter@amd.com: * Source: BIOS and Kernel Developer's Guide for the AMD Family 15h * Processors, Rev 0.90, May 18, 2010 */ static pme_amd64_entry_t amd64_fam15h_pe[]={ /* Family 15h */ /* 0 */{.pme_name = "DISPATCHED_FPU_OPS", .pme_code = 0x00, .pme_desc = "FPU Pipe Assignment", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "OPS_PIPE0", .pme_udesc = "Total number uops assigned to Pipe 0", .pme_ucode = 1 << 0, }, { .pme_uname = "OPS_PIPE1", .pme_udesc = "Total number uops assigned to Pipe 1", .pme_ucode = 1 << 1, }, { .pme_uname = "OPS_PIPE2", .pme_udesc = "Total number uops assigned to Pipe 2", .pme_ucode = 1 << 2, }, { .pme_uname = "OPS_PIPE3", .pme_udesc = "Total number uops assigned to Pipe 3", .pme_ucode = 1 << 3, }, { .pme_uname = "OPS_DUAL_PIPE0", .pme_udesc = "Total number dual-pipe uops assigned to Pipe 0", .pme_ucode = 1 << 4, }, { .pme_uname = "OPS_DUAL_PIPE1", .pme_udesc = "Total number dual-pipe uops assigned to Pipe 1", .pme_ucode = 1 << 5, }, { .pme_uname = "OPS_DUAL_PIPE2", .pme_udesc = "Total number dual-pipe uops assigned to Pipe 2", .pme_ucode = 1 << 6, }, { .pme_uname = "OPS_DUAL_PIPE3", .pme_udesc = "Total number dual-pipe uops assigned to Pipe 3", .pme_ucode = 1 << 7, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 1 */{.pme_name = "CYCLES_FPU_EMPTY", .pme_code = 0x01, .pme_desc = "FP Scheduler Empty", }, /* 2 */{.pme_name = "RETIRED_SSE_OPS", .pme_code = 0x03, .pme_desc = "Retired SSE/BNI Ops", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "SINGLE_ADD_SUB_OPS", .pme_udesc = "Single-precision add/subtract FLOPS", .pme_ucode = 1 << 0, }, { .pme_uname = "SINGLE_MUL_OPS", .pme_udesc = "Single-precision multiply FLOPS", .pme_ucode = 1 << 1, }, { .pme_uname = "SINGLE_DIV_OPS", .pme_udesc = "Single-precision divide/square root FLOPS", .pme_ucode = 1 << 2, }, { .pme_uname = "SINGLE_MUL_ADD_OPS", .pme_udesc = "Single precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS", .pme_ucode = 1 << 3, }, { .pme_uname = "DOUBLE_ADD_SUB_OPS", .pme_udesc = "Double precision add/subtract FLOPS", .pme_ucode = 1 << 4, }, { .pme_uname = "DOUBLE_MUL_OPS", .pme_udesc = "Double precision multiply FLOPS", .pme_ucode = 1 << 5, }, { .pme_uname = "DOUBLE_DIV_OPS", .pme_udesc = "Double precision divide/square root FLOPS", .pme_ucode = 1 << 6, }, { .pme_uname = "DOUBLE_MUL_ADD_OPS", .pme_udesc = "Double precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS", .pme_ucode = 1 << 7, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 3 */{.pme_name = "MOVE_SCALAR_OPTIMIZATION", .pme_code = 0x04, .pme_desc = "Number of Move Elimination and Scalar Op Optimization", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 5, .pme_umasks = { { .pme_uname = "SSE_MOVE_OPS", .pme_udesc = "Number of SSE Move Ops", .pme_ucode = 1 << 0, }, { .pme_uname = "SSE_MOVE_OPS_ELIM", .pme_udesc = "Number of SSE Move Ops eliminated", .pme_ucode = 1 << 1, }, { .pme_uname = "OPT_CAND", .pme_udesc = "Number of Ops that are candidates for optimization (Z-bit set or pass)", .pme_ucode = 1 << 2, }, { .pme_uname = "SCALAR_OPS_OPTIMIZED", .pme_udesc = "Number of Scalar ops optimized", .pme_ucode = 1 << 3, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x0F, }, }, }, /* 4 */{.pme_name = "RETIRED_SERIALIZING_OPS", .pme_code = 0x05, .pme_desc = "Retired Serializing Ops", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 5, .pme_umasks = { { .pme_uname = "SSE_RETIRED", .pme_udesc = "SSE bottom-executing uops retired", .pme_ucode = 1 << 0, }, { .pme_uname = "SSE_MISPREDICTED", .pme_udesc = "SSE control word mispredict traps due to mispredictions", .pme_ucode = 1 << 1, }, { .pme_uname = "X87_RETIRED", .pme_udesc = "x87 bottom-executing uops retired", .pme_ucode = 1 << 2, }, { .pme_uname = "X87_MISPREDICTED", .pme_udesc = "x87 control word mispredict traps due to mispredictions", .pme_ucode = 1 << 3, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x0F, }, }, }, /* 5 */{.pme_name = "BOTTOM_EXECUTE_OP", .pme_code = 0x06, .pme_desc = "Number of Cycles that a Bottom-Execute uop is in the FP Scheduler", }, /* 6 */{.pme_name = "SEGMENT_REGISTER_LOADS", .pme_code = 0x20, .pme_desc = "Segment Register Loads", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 8, .pme_umasks = { { .pme_uname = "ES", .pme_udesc = "ES", .pme_ucode = 1 << 0, }, { .pme_uname = "CS", .pme_udesc = "CS", .pme_ucode = 1 << 1, }, { .pme_uname = "SS", .pme_udesc = "SS", .pme_ucode = 1 << 2, }, { .pme_uname = "DS", .pme_udesc = "DS", .pme_ucode = 1 << 3, }, { .pme_uname = "FS", .pme_udesc = "FS", .pme_ucode = 1 << 4, }, { .pme_uname = "GS", .pme_udesc = "GS", .pme_ucode = 1 << 5, }, { .pme_uname = "HS", .pme_udesc = "HS", .pme_ucode = 1 << 6, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x7F, }, }, }, /* 7 */{.pme_name = "PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE", .pme_code = 0x21, .pme_desc = "Pipeline Restart Due to Self-Modifying Code", }, /* 8 */{.pme_name = "PIPELINE_RESTART_DUE_TO_PROBE_HIT", .pme_code = 0x22, .pme_desc = "Pipeline Restart Due to Probe Hit", }, /* 9 */{.pme_name = "LOAD_Q_STORE_Q_FULL", .pme_code = 0x23, .pme_desc = "Load Queue/Store Queue Full", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 3, .pme_umasks = { { .pme_uname = "LOAD_QUEUE", .pme_udesc = "The number of cycles that the load buffer is full", .pme_ucode = 1 << 0, }, { .pme_uname = "STORE_QUEUE", .pme_udesc = "The number of cycles that the store buffer is full", .pme_ucode = 1 << 1, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x03, }, }, }, /* 10 */{.pme_name = "LOCKED_OPS", .pme_code = 0x24, .pme_desc = "Locked Operations", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 4, .pme_umasks = { { .pme_uname = "EXECUTED", .pme_udesc = "Number of locked instructions executed", .pme_ucode = 1 << 0, }, { .pme_uname = "CYCLES_NON_SPECULATIVE_PHASE", .pme_udesc = "Number of cycles spent in non-speculative phase, excluding cache miss penalty", .pme_ucode = 1 << 2, }, { .pme_uname = "CYCLES_WAITING", .pme_udesc = "Number of cycles spent in non-speculative phase, including the cache miss penalty", .pme_ucode = 1 << 3, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x0D, }, }, }, /* 11 */{.pme_name = "RETIRED_CLFLUSH_INSTRUCTIONS", .pme_code = 0x26, .pme_desc = "Retired CLFLUSH Instructions", }, /* 12 */{.pme_name = "RETIRED_CPUID_INSTRUCTIONS", .pme_code = 0x27, .pme_desc = "Retired CPUID Instructions", }, /* 13 */{.pme_name = "CANCELLED_STORE_TO_LOAD", .pme_code = 0x2A, .pme_desc = "Canceled Store to Load Forward Operations", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 2, .pme_umasks = { { .pme_uname = "SIZE_ADDRESS_MISMATCHES", .pme_udesc = "Store is smaller than load or different starting byte but partial overlap", .pme_ucode = 1 << 0, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x01, }, }, }, /* 14 */{.pme_name = "SMIS_RECEIVED", .pme_code = 0x2B, .pme_desc = "SMIs Received", }, /* 15 */{.pme_name = "DATA_CACHE_ACCESSES", .pme_code = 0x40, .pme_desc = "Data Cache Accesses", }, /* 16 */{.pme_name = "DATA_CACHE_MISSES", .pme_code = 0x41, .pme_desc = "Data Cache Misses", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 3, .pme_umasks = { { .pme_uname = "DC_MISS_STREAMING_STORE", .pme_udesc = "First data cache miss or streaming store to a 64B cache line", .pme_ucode = 1 << 0, }, { .pme_uname = "STREAMING_STORE", .pme_udesc = "First streaming store to a 64B cache line", .pme_ucode = 1 << 1, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x03, }, }, }, /* 17 */{.pme_name = "DATA_CACHE_REFILLS_FROM_L2_OR_NORTHBRIDGE", .pme_code = 0x42, .pme_desc = "Data Cache Refills from L2 or System", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 5, .pme_umasks = { { .pme_uname = "GOOD", .pme_udesc = "Fill with good data. (Final valid status is valid)", .pme_ucode = 1 << 0, }, { .pme_uname = "INVALID", .pme_udesc = "Early valid status turned out to be invalid", .pme_ucode = 1 << 1, }, { .pme_uname = "POISON", .pme_udesc = "Fill with poison data", .pme_ucode = 1 << 2, }, { .pme_uname = "READ_ERROR", .pme_udesc = "Fill with read data error", .pme_ucode = 1 << 3, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x0F, }, }, }, /* 18 */{.pme_name = "DATA_CACHE_REFILLS_FROM_NORTHBRIDGE", .pme_code = 0x43, .pme_desc = "Data Cache Refills from System", }, /* 19 */{.pme_name = "UNIFIED_TLB_HIT", .pme_code = 0x45, .pme_desc = "Unified TLB Hit", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 7, .pme_umasks = { { .pme_uname = "4K_DATA", .pme_udesc = "4 KB unified TLB hit for data", .pme_ucode = 1 << 0, }, { .pme_uname = "2M_DATA", .pme_udesc = "2 MB unified TLB hit for data", .pme_ucode = 1 << 1, }, { .pme_uname = "1G_DATA", .pme_udesc = "1 GB unified TLB hit for data", .pme_ucode = 1 << 2, }, { .pme_uname = "4K_INST", .pme_udesc = "4 KB unified TLB hit for instruction", .pme_ucode = 1 << 4, }, { .pme_uname = "2M_INST", .pme_udesc = "2 MB unified TLB hit for instruction", .pme_ucode = 1 << 5, }, { .pme_uname = "1G_INST", .pme_udesc = "1 GB unified TLB hit for instruction", .pme_ucode = 1 << 6, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x77, }, }, }, /* 20 */{.pme_name = "UNIFIED_TLB_MISS", .pme_code = 0x46, .pme_desc = "Unified TLB Miss", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 7, .pme_umasks = { { .pme_uname = "4K_DATA", .pme_udesc = "4 KB unified TLB miss for data", .pme_ucode = 1 << 0, }, { .pme_uname = "2M_DATA", .pme_udesc = "2 MB unified TLB miss for data", .pme_ucode = 1 << 1, }, { .pme_uname = "1GB_DATA", .pme_udesc = "1 GB unified TLB miss for data", .pme_ucode = 1 << 2, }, { .pme_uname = "4K_INST", .pme_udesc = "4 KB unified TLB miss for instruction", .pme_ucode = 1 << 4, }, { .pme_uname = "2M_INST", .pme_udesc = "2 MB unified TLB miss for instruction", .pme_ucode = 1 << 5, }, { .pme_uname = "1G_INST", .pme_udesc = "1 GB unified TLB miss for instruction", .pme_ucode = 1 << 6, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x77, }, }, }, /* 21 */{.pme_name = "MISALIGNED_ACCESSES", .pme_code = 0x47, .pme_desc = "Misaligned Accesses", }, /* 22 */{.pme_name = "PREFETCH_INSTRUCTIONS_DISPATCHED", .pme_code = 0x4B, .pme_desc = "Prefetch Instructions Dispatched", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 4, .pme_umasks = { { .pme_uname = "LOAD", .pme_udesc = "Load (Prefetch, PrefetchT0/T1/T2)", .pme_ucode = 1 << 0, }, { .pme_uname = "STORE", .pme_udesc = "Store (PrefetchW)", .pme_ucode = 1 << 1, }, { .pme_uname = "NTA", .pme_udesc = "NTA (PrefetchNTA)", .pme_ucode = 1 << 2, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x07, }, }, }, /* 23 */{.pme_name = "INEFFECTIVE_SW_PREFETCHES", .pme_code = 0x52, .pme_desc = "Ineffective Software Prefetches", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 3, .pme_umasks = { { .pme_uname = "SW_PREFETCH_HIT_IN_L1", .pme_udesc = "Software prefetch hit in the L1", .pme_ucode = 1 << 0, }, { .pme_uname = "SW_PREFETCH_HIT_IN_L2", .pme_udesc = "Software prefetch hit in the L2", .pme_ucode = 1 << 3, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x09, }, }, }, /* 24 */{.pme_name = "MEMORY_REQUESTS", .pme_code = 0x65, .pme_desc = "Memory Requests by Type", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 4, .pme_umasks = { { .pme_uname = "NON_CACHEABLE", .pme_udesc = "Requests to non-cacheable (UC) memory", .pme_ucode = 1 << 0, }, { .pme_uname = "WRITE_COMBINING", .pme_udesc = "Requests to non-cacheable (WC, but not WC+/SS) memory", .pme_ucode = 1 << 1, }, { .pme_uname = "STREAMING_STORE", .pme_udesc = "Requests to non-cacheable (WC+/SS, but not WC) memory", .pme_ucode = 1 << 7, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x83, }, }, }, /* 25 */{.pme_name = "DATA_PREFETCHER", .pme_code = 0x67, .pme_desc = "Data Prefetcher", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 2, .pme_umasks = { { .pme_uname = "ATTEMPTED", .pme_udesc = "Prefetch attempts", .pme_ucode = 1 << 1, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x02, }, }, }, /* 26 */{.pme_name = "MAB_REQS", .pme_code = 0x68, .pme_desc = "MAB Requests", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "BUFFER_BIT_0", .pme_udesc = "Buffer entry index bit 0", .pme_ucode = 1 << 0, }, { .pme_uname = "BUFFER_BIT_1", .pme_udesc = "Buffer entry index bit 1", .pme_ucode = 1 << 1, }, { .pme_uname = "BUFFER_BIT_2", .pme_udesc = "Buffer entry index bit 2", .pme_ucode = 1 << 2, }, { .pme_uname = "BUFFER_BIT_3", .pme_udesc = "Buffer entry index bit 3", .pme_ucode = 1 << 3, }, { .pme_uname = "BUFFER_BIT_4", .pme_udesc = "Buffer entry index bit 4", .pme_ucode = 1 << 4, }, { .pme_uname = "BUFFER_BIT_5", .pme_udesc = "Buffer entry index bit 5", .pme_ucode = 1 << 5, }, { .pme_uname = "BUFFER_BIT_6", .pme_udesc = "Buffer entry index bit 6", .pme_ucode = 1 << 6, }, { .pme_uname = "BUFFER_BIT_7", .pme_udesc = "Buffer entry index bit 7", .pme_ucode = 1 << 7, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 27 */{.pme_name = "MAB_WAIT", .pme_code = 0x69, .pme_desc = "MAB Wait Cycles", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "BUFFER_BIT_0", .pme_udesc = "Buffer entry index bit 0", .pme_ucode = 1 << 0, }, { .pme_uname = "BUFFER_BIT_1", .pme_udesc = "Buffer entry index bit 1", .pme_ucode = 1 << 1, }, { .pme_uname = "BUFFER_BIT_2", .pme_udesc = "Buffer entry index bit 2", .pme_ucode = 1 << 2, }, { .pme_uname = "BUFFER_BIT_3", .pme_udesc = "Buffer entry index bit 3", .pme_ucode = 1 << 3, }, { .pme_uname = "BUFFER_BIT_4", .pme_udesc = "Buffer entry index bit 4", .pme_ucode = 1 << 4, }, { .pme_uname = "BUFFER_BIT_5", .pme_udesc = "Buffer entry index bit 5", .pme_ucode = 1 << 5, }, { .pme_uname = "BUFFER_BIT_6", .pme_udesc = "Buffer entry index bit 6", .pme_ucode = 1 << 6, }, { .pme_uname = "BUFFER_BIT_7", .pme_udesc = "Buffer entry index bit 7", .pme_ucode = 1 << 7, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 28 */{.pme_name = "SYSTEM_READ_RESPONSES", .pme_code = 0x6C, .pme_desc = "Response From System on Cache Refills", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 7, .pme_umasks = { { .pme_uname = "EXCLUSIVE", .pme_udesc = "Exclusive", .pme_ucode = 1 << 0, }, { .pme_uname = "MODIFIED", .pme_udesc = "Modified (D18F0x68[ATMModeEn]==0), Modified written (D18F0x68[ATMModeEn]==1)", .pme_ucode = 1 << 1, }, { .pme_uname = "SHARED", .pme_udesc = "Shared", .pme_ucode = 1 << 2, }, { .pme_uname = "OWNED", .pme_udesc = "Owned", .pme_ucode = 1 << 3, }, { .pme_uname = "DATA_ERROR", .pme_udesc = "Data Error", .pme_ucode = 1 << 4, }, { .pme_uname = "MODIFIED_UNWRITTEN", .pme_udesc = "Modified unwritten", .pme_ucode = 1 << 5, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x3F, }, }, }, /* 29 */{.pme_name = "OCTWORD_WRITE_TRANSFERS", .pme_code = 0x6D, .pme_desc = "Octwords Written to System", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 2, .pme_umasks = { { .pme_uname = "OCTWORD_WRITE_TRANSFER", .pme_udesc = "OW write transfer", .pme_ucode = 1 << 0, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x01, }, }, }, /* 30 */{.pme_name = "CPU_CLK_UNHALTED", .pme_code = 0x76, .pme_desc = "CPU Clocks not Halted", }, /* 31 */{.pme_name = "REQUESTS_TO_L2", .pme_code = 0x7D, .pme_desc = "Requests to L2 Cache", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 7, .pme_umasks = { { .pme_uname = "INSTRUCTIONS", .pme_udesc = "IC fill", .pme_ucode = 1 << 0, }, { .pme_uname = "DATA", .pme_udesc = "DC fill", .pme_ucode = 1 << 1, }, { .pme_uname = "TLB_WALK", .pme_udesc = "TLB fill (page table walks)", .pme_ucode = 1 << 2, }, { .pme_uname = "SNOOP", .pme_udesc = "NB probe request", .pme_ucode = 1 << 3, }, { .pme_uname = "CANCELLED", .pme_udesc = "Canceled request", .pme_ucode = 1 << 4, }, { .pme_uname = "PREFETCHER", .pme_udesc = "L2 cache prefetcher request", .pme_ucode = 1 << 6, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x5F, }, }, }, /* 32 */{.pme_name = "L2_CACHE_MISS", .pme_code = 0x7E, .pme_desc = "L2 Cache Misses", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 5, .pme_umasks = { { .pme_uname = "INSTRUCTIONS", .pme_udesc = "IC fill", .pme_ucode = 1 << 0, }, { .pme_uname = "DATA", .pme_udesc = "DC fill (includes possible replays, whereas PMCx041 does not)", .pme_ucode = 1 << 1, }, { .pme_uname = "TLB_WALK", .pme_udesc = "TLB page table walk", .pme_ucode = 1 << 2, }, { .pme_uname = "PREFETCHER", .pme_udesc = "L2 Cache Prefetcher request", .pme_ucode = 1 << 4, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x17, }, }, }, /* 33 */{.pme_name = "L2_CACHE_FILL_WRITEBACK", .pme_code = 0x7F, .pme_desc = "L2 Fill/Writeback", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 4, .pme_umasks = { { .pme_uname = "L2_FILLS", .pme_udesc = "L2 fills from system", .pme_ucode = 1 << 0, }, { .pme_uname = "L2_WRITEBACKS", .pme_udesc = "L2 Writebacks to system (Clean and Dirty)", .pme_ucode = 1 << 1, }, { .pme_uname = "L2_WRITEBACKS_CLEAN", .pme_udesc = "L2 Clean Writebacks to system", .pme_ucode = 1 << 2, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x07, }, }, }, /* 34 */{.pme_name = "PAGE_SPLINTERING", .pme_code = 0x165, .pme_desc = "Page Splintering", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 4, .pme_umasks = { { .pme_uname = "GUEST_LARGER", .pme_udesc = "Guest page size is larger than host page size when nested paging is enabled", .pme_ucode = 1 << 0, }, { .pme_uname = "MTRR_MISMATCH", .pme_udesc = "Splintering due to MTRRs, IORRs, APIC, TOMs or other special address region", .pme_ucode = 1 << 1, }, { .pme_uname = "HOST_LARGER", .pme_udesc = "Host page size is larger than the guest page size", .pme_ucode = 1 << 2, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x07, }, }, }, /* 35 */{.pme_name = "INSTRUCTION_CACHE_FETCHES", .pme_code = 0x80, .pme_desc = "Instruction Cache Fetches", }, /* 36 */{.pme_name = "INSTRUCTION_CACHE_MISSES", .pme_code = 0x81, .pme_desc = "Instruction Cache Misses", }, /* 37 */{.pme_name = "INSTRUCTION_CACHE_REFILLS_FROM_L2", .pme_code = 0x82, .pme_desc = "Instruction Cache Refills from L2", }, /* 38 */{.pme_name = "INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM", .pme_code = 0x83, .pme_desc = "Instruction Cache Refills from System", }, /* 39 */{.pme_name = "L1_ITLB_MISS_AND_L2_ITLB_HIT", .pme_code = 0x84, .pme_desc = "L1 ITLB Miss, L2 ITLB Hit", }, /* 40 */{.pme_name = "L1_ITLB_MISS_AND_L2_ITLB_MISS", .pme_code = 0x85, .pme_desc = "L1 ITLB Miss, L2 ITLB Miss", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 4, .pme_umasks = { { .pme_uname = "4K_PAGE_FETCHES", .pme_udesc = "Instruction fetches to a 4 KB page", .pme_ucode = 1 << 0, }, { .pme_uname = "2M_PAGE_FETCHES", .pme_udesc = "Instruction fetches to a 2 MB page", .pme_ucode = 1 << 1, }, { .pme_uname = "1G_PAGE_FETCHES", .pme_udesc = "Instruction fetches to a 1 GB page", .pme_ucode = 1 << 2, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x07, }, }, }, /* 41 */{.pme_name = "PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE", .pme_code = 0x86, .pme_desc = "Pipeline Restart Due to Instruction Stream Probe", }, /* 42 */{.pme_name = "INSTRUCTION_FETCH_STALL", .pme_code = 0x87, .pme_desc = "Instruction Fetch Stall", }, /* 43 */{.pme_name = "RETURN_STACK_HITS", .pme_code = 0x88, .pme_desc = "Return Stack Hits", }, /* 44 */{.pme_name = "RETURN_STACK_OVERFLOWS", .pme_code = 0x89, .pme_desc = "Return Stack Overflows", }, /* 45 */{.pme_name = "INSTRUCTION_CACHE_VICTIMS", .pme_code = 0x8B, .pme_desc = "Instruction Cache Victims", }, /* 46 */{.pme_name = "INSTRUCTION_CACHE_INVALIDATED", .pme_code = 0x8C, .pme_desc = "Instruction Cache Lines Invalidated", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 5, .pme_umasks = { { .pme_uname = "NON_SMC_PROBE_MISS", .pme_udesc = "Non-SMC invalidating probe that missed on in-flight instructions", .pme_ucode = 1 << 0, }, { .pme_uname = "NON_SMC_PROBE_HIT", .pme_udesc = "Non-SMC invalidating probe that hit on in-flight instructions", .pme_ucode = 1 << 1, }, { .pme_uname = "SMC_PROBE_MISS", .pme_udesc = "SMC invalidating probe that missed on in-flight instructions", .pme_ucode = 1 << 2, }, { .pme_uname = "SMC_PROBE_HIT", .pme_udesc = "SMC invalidating probe that hit on in-flight instructions", .pme_ucode = 1 << 3, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x0F, }, }, }, /* 47 */{.pme_name = "ITLB_RELOADS", .pme_code = 0x99, .pme_desc = "ITLB Reloads", }, /* 48 */{.pme_name = "ITLB_RELOADS_ABORTED", .pme_code = 0x9A, .pme_desc = "ITLB Reloads Aborted", }, /* 49 */{.pme_name = "RETIRED_INSTRUCTIONS", .pme_code = 0xC0, .pme_desc = "Retired Instructions", }, /* 50 */{.pme_name = "RETIRED_UOPS", .pme_code = 0xC1, .pme_desc = "Retired uops", }, /* 51 */{.pme_name = "RETIRED_BRANCH_INSTRUCTIONS", .pme_code = 0xC2, .pme_desc = "Retired Branch Instructions", }, /* 52 */{.pme_name = "RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS", .pme_code = 0xC3, .pme_desc = "Retired Mispredicted Branch Instructions", }, /* 53 */{.pme_name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS", .pme_code = 0xC4, .pme_desc = "Retired Taken Branch Instructions", }, /* 54 */{.pme_name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED", .pme_code = 0xC5, .pme_desc = "Retired Taken Branch Instructions Mispredicted", }, /* 55 */{.pme_name = "RETIRED_FAR_CONTROL_TRANSFERS", .pme_code = 0xC6, .pme_desc = "Retired Far Control Transfers", }, /* 56 */{.pme_name = "RETIRED_BRANCH_RESYNCS", .pme_code = 0xC7, .pme_desc = "Retired Branch Resyncs", }, /* 57 */{.pme_name = "RETIRED_NEAR_RETURNS", .pme_code = 0xC8, .pme_desc = "Retired Near Returns", }, /* 58 */{.pme_name = "RETIRED_NEAR_RETURNS_MISPREDICTED", .pme_code = 0xC9, .pme_desc = "Retired Near Returns Mispredicted", }, /* 59 */{.pme_name = "RETIRED_INDIRECT_BRANCHES_MISPREDICTED", .pme_code = 0xCA, .pme_desc = "Retired Indirect Branches Mispredicted", }, /* 60 */{.pme_name = "RETIRED_MMX_FP_INSTRUCTIONS", .pme_code = 0xCB, .pme_desc = "Retired MMX/FP Instructions", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 4, .pme_umasks = { { .pme_uname = "X87", .pme_udesc = "x87 instructions", .pme_ucode = 1 << 0, }, { .pme_uname = "MMX", .pme_udesc = "MMX(tm) instructions", .pme_ucode = 1 << 1, }, { .pme_uname = "SSE", .pme_udesc = "SSE instructions (SSE,SSE2,SSE3,SSSE3,SSE4A,SSE4.1,SSE4.2,AVX,XOP,FMA4)", .pme_ucode = 1 << 2, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x07, }, }, }, /* 61 */{.pme_name = "INTERRUPTS_MASKED_CYCLES", .pme_code = 0xCD, .pme_desc = "Interrupts-Masked Cycles", }, /* 62 */{.pme_name = "INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING", .pme_code = 0xCE, .pme_desc = "Interrupts-Masked Cycles with Interrupt Pending", }, /* 63 */{.pme_name = "INTERRUPTS_TAKEN", .pme_code = 0xCF, .pme_desc = "Interrupts Taken", }, /* 64 */{.pme_name = "DECODER_EMPTY", .pme_code = 0xD0, .pme_desc = "Decoder Empty", }, /* 65 */{.pme_name = "DISPATCH_STALLS", .pme_code = 0xD1, .pme_desc = "Dispatch Stalls", }, /* 66 */{.pme_name = "DISPATCH_STALL_FOR_SERIALIZATION", .pme_code = 0xD3, .pme_desc = "Microsequencer Stall due to Serialization", }, /* 67 */{.pme_name = "DISPATCH_STALL_FOR_RETIRE_QUEUE_FULL", .pme_code = 0xD5, .pme_desc = "Dispatch Stall for Instruction Retire Q Full", }, /* 68 */{.pme_name = "DISPATCH_STALL_FOR_INT_SCHED_QUEUE_FULL", .pme_code = 0xD6, .pme_desc = "Dispatch Stall for Integer Scheduler Queue Full", }, /* 69 */{.pme_name = "DISPATCH_STALL_FOR_FPU_FULL", .pme_code = 0xD7, .pme_desc = "Dispatch Stall for FP Scheduler Queue Full", }, /* 70 */{.pme_name = "DISPATCH_STALL_FOR_LDQ_FULL", .pme_code = 0xD8, .pme_desc = "Dispatch Stall for LDQ Full", }, /* 71 */{.pme_name = "MICROSEQ_STALL_WAITING_FOR_ALL_QUIET", .pme_code = 0xD9, .pme_desc = "Microsequencer Stall Waiting for All Quiet", }, /* 72 */{.pme_name = "FPU_EXCEPTIONS", .pme_code = 0xDB, .pme_desc = "FPU Exceptions", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 6, .pme_umasks = { { .pme_uname = "TOTAL_FAULTS", .pme_udesc = "Total microfaults", .pme_ucode = 1 << 0, }, { .pme_uname = "TOTAL_TRAPS", .pme_udesc = "Total microtraps", .pme_ucode = 1 << 1, }, { .pme_uname = "INT2EXT_FAULTS", .pme_udesc = "Int2Ext faults", .pme_ucode = 1 << 2, }, { .pme_uname = "EXT2INT_FAULTS", .pme_udesc = "Ext2Int faults", .pme_ucode = 1 << 3, }, { .pme_uname = "BYPASS_FAULTS", .pme_udesc = "Bypass faults", .pme_ucode = 1 << 4, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x1F, }, }, }, /* 73 */{.pme_name = "DR0_BREAKPOINTS", .pme_code = 0xDC, .pme_desc = "DR0 Breakpoint Match", }, /* 74 */{.pme_name = "DR1_BREAKPOINTS", .pme_code = 0xDD, .pme_desc = "DR1 Breakpoint Match", }, /* 75 */{.pme_name = "DR2_BREAKPOINTS", .pme_code = 0xDE, .pme_desc = "DR2 Breakpoint Match", }, /* 76 */{.pme_name = "DR3_BREAKPOINTS", .pme_code = 0xDF, .pme_desc = "DR3 Breakpoint Match", }, /* 77 */{.pme_name = "IBS_OPS_TAGGED", .pme_code = 0x1CF, .pme_desc = "Tagged IBS Ops", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 4, .pme_umasks = { { .pme_uname = "TAGGED", .pme_udesc = "Number of ops tagged by IBS", .pme_ucode = 1 << 0, }, { .pme_uname = "RETIRED", .pme_udesc = "Number of ops tagged by IBS that retired", .pme_ucode = 1 << 1, }, { .pme_uname = "IGNORED", .pme_udesc = "Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired", .pme_ucode = 1 << 2, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x07, }, }, }, /* Northbridge events (.pme_code & 0x0E0) not yet supported by the kernel */ #if 0 /* 78 */{.pme_name = "DRAM_ACCESSES", .pme_code = 0xE0, .pme_desc = "DRAM Accesses", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 7, .pme_umasks = { { .pme_uname = "HIT", .pme_udesc = "DCT0 Page hit", .pme_ucode = 1 << 0, }, { .pme_uname = "MISS", .pme_udesc = "DCT0 Page Miss", .pme_ucode = 1 << 1, }, { .pme_uname = "CONFLICT", .pme_udesc = "DCT0 Page Conflict", .pme_ucode = 1 << 2, }, { .pme_uname = "DCT1_PAGE_HIT", .pme_udesc = "DCT1 Page hit", .pme_ucode = 1 << 3, }, { .pme_uname = "DCT1_PAGE_MISS", .pme_udesc = "DCT1 Page Miss", .pme_ucode = 1 << 4, }, { .pme_uname = "DCT1_PAGE_CONFLICT", .pme_udesc = "DCT1 Page Conflict", .pme_ucode = 1 << 5, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x3F, }, }, }, /* 79 */{.pme_name = "MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOWS", .pme_code = 0xE1, .pme_desc = "DRAM Controller Page Table Overflows", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 3, .pme_umasks = { { .pme_uname = "DCT0_PAGE_TABLE_OVERFLOW", .pme_udesc = "DCT0 Page Table Overflow", .pme_ucode = 1 << 0, }, { .pme_uname = "DCT1_PAGE_TABLE_OVERFLOW", .pme_udesc = "DCT1 Page Table Overflow", .pme_ucode = 1 << 1, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x03, }, }, }, /* 80 */{.pme_name = "MEMORY_CONTROLLER_SLOT_MISSED", .pme_code = 0xE2, .pme_desc = "Memory Controller DRAM Command Slots Missed", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 3, .pme_umasks = { { .pme_uname = "DCT0_COMMAND_SLOTS_MISSED", .pme_udesc = "DCT0 Command Slots Missed (in MemClks)", .pme_ucode = 1 << 0, }, { .pme_uname = "DCT1_COMMAND_SLOTS_MISSED", .pme_udesc = "DCT1 Command Slots Missed (in MemClks)", .pme_ucode = 1 << 1, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x03, }, }, }, /* 81 */{.pme_name = "MEMORY_CONTROLLER_TURNAROUNDS", .pme_code = 0xE3, .pme_desc = "Memory Controller Turnarounds", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 7, .pme_umasks = { { .pme_uname = "CHIP_SELECT", .pme_udesc = "DCT0 DIMM (chip select) turnaround", .pme_ucode = 1 << 0, }, { .pme_uname = "READ_TO_WRITE", .pme_udesc = "DCT0 Read to write turnaround", .pme_ucode = 1 << 1, }, { .pme_uname = "WRITE_TO_READ", .pme_udesc = "DCT0 Write to read turnaround", .pme_ucode = 1 << 2, }, { .pme_uname = "DCT1_DIMM", .pme_udesc = "DCT1 DIMM (chip select) turnaround", .pme_ucode = 1 << 3, }, { .pme_uname = "DCT1_READ_TO_WRITE_TURNAROUND", .pme_udesc = "DCT1 Read to write turnaround", .pme_ucode = 1 << 4, }, { .pme_uname = "DCT1_WRITE_TO_READ_TURNAROUND", .pme_udesc = "DCT1 Write to read turnaround", .pme_ucode = 1 << 5, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x3F, }, }, }, /* 82 */{.pme_name = "MEMORY_CONTROLLER_BYPASS_COUNTER_SATURATION", .pme_code = 0xE4, .pme_desc = "Memory Controller Bypass Counter Saturation", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 5, .pme_umasks = { { .pme_uname = "HIGH_PRIORITY", .pme_udesc = "Memory controller high priority bypass", .pme_ucode = 1 << 0, }, { .pme_uname = "MEDIUM_PRIORITY", .pme_udesc = "Memory controller medium priority bypass", .pme_ucode = 1 << 1, }, { .pme_uname = "DCT0_DCQ", .pme_udesc = "DCT0 DCQ bypass", .pme_ucode = 1 << 2, }, { .pme_uname = "DCT1_DCQ", .pme_udesc = "DCT1 DCQ bypass", .pme_ucode = 1 << 3, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x0F, }, }, }, /* 83 */{.pme_name = "THERMAL_STATUS", .pme_code = 0xE8, .pme_desc = "Thermal Status", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 4, .pme_umasks = { { .pme_uname = "CLKS_DIE_TEMP_TOO_HIGH", .pme_udesc = "Number of times the HTC trip point is crossed", .pme_ucode = 1 << 2, }, { .pme_uname = "CLOCKS_HTC_P_STATE_INACTIVE", .pme_udesc = "Number of clocks HTC P-state is inactive", .pme_ucode = 1 << 5, }, { .pme_uname = "CLOCKS_HTC_P_STATE_ACTIVE", .pme_udesc = "Number of clocks HTC P-state is active", .pme_ucode = 1 << 6, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x64, }, }, }, /* 84 */{.pme_name = "CPU_IO_REQUESTS_TO_MEMORY_IO", .pme_code = 0xE9, .pme_desc = "CPU/IO Requests to Memory/IO", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "I_O_TO_I_O", .pme_udesc = "IO to IO", .pme_ucode = 1 << 0, }, { .pme_uname = "I_O_TO_MEM", .pme_udesc = "IO to Mem", .pme_ucode = 1 << 1, }, { .pme_uname = "CPU_TO_I_O", .pme_udesc = "CPU to IO", .pme_ucode = 1 << 2, }, { .pme_uname = "CPU_TO_MEM", .pme_udesc = "CPU to Mem", .pme_ucode = 1 << 3, }, { .pme_uname = "TO_REMOTE_NODE", .pme_udesc = "To remote node", .pme_ucode = 1 << 4, }, { .pme_uname = "TO_LOCAL_NODE", .pme_udesc = "To local node", .pme_ucode = 1 << 5, }, { .pme_uname = "FROM_REMOTE_NODE", .pme_udesc = "From remote node", .pme_ucode = 1 << 6, }, { .pme_uname = "FROM_LOCAL_NODE", .pme_udesc = "From local node", .pme_ucode = 1 << 7, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 85 */{.pme_name = "CACHE_BLOCK_COMMANDS", .pme_code = 0xEA, .pme_desc = "Cache Block Commands", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 6, .pme_umasks = { { .pme_uname = "VICTIM_WRITEBACK", .pme_udesc = "Victim Block (Writeback)", .pme_ucode = 1 << 0, }, { .pme_uname = "DCACHE_LOAD_MISS", .pme_udesc = "Read Block (Dcache load miss refill)", .pme_ucode = 1 << 2, }, { .pme_uname = "SHARED_ICACHE_REFILL", .pme_udesc = "Read Block Shared (Icache refill)", .pme_ucode = 1 << 3, }, { .pme_uname = "READ_BLOCK_MODIFIED", .pme_udesc = "Read Block Modified (Dcache store miss refill)", .pme_ucode = 1 << 4, }, { .pme_uname = "CHANGE_TO_DIRTY", .pme_udesc = "Change-to-Dirty (first store to clean block already in cache)", .pme_ucode = 1 << 5, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x3D, }, }, }, /* 86 */{.pme_name = "SIZED_COMMANDS", .pme_code = 0xEB, .pme_desc = "Sized Commands", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 7, .pme_umasks = { { .pme_uname = "NON_POSTED_WRITE_BYTE", .pme_udesc = "Non-Posted SzWr Byte (1-32 bytes)", .pme_ucode = 1 << 0, }, { .pme_uname = "NON_POSTED_WRITE_DWORD", .pme_udesc = "Non-Posted SzWr DW (1-16 dwords)", .pme_ucode = 1 << 1, }, { .pme_uname = "POSTED_WRITE_BYTE", .pme_udesc = "Posted SzWr Byte (1-32 bytes)", .pme_ucode = 1 << 2, }, { .pme_uname = "POSTED_WRITE_DWORD", .pme_udesc = "Posted SzWr DW (1-16 dwords)", .pme_ucode = 1 << 3, }, { .pme_uname = "READ_BYTE", .pme_udesc = "SzRd Byte (4 bytes)", .pme_ucode = 1 << 4, }, { .pme_uname = "READ_DWORD", .pme_udesc = "SzRd DW (1-16 dwords)", .pme_ucode = 1 << 5, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x3F, }, }, }, /* 87 */{.pme_name = "PROBE_RESPONSES_AND_UPSTREAM_REQUESTS", .pme_code = 0xEC, .pme_desc = "Probe Responses and Upstream Requests", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "MISS", .pme_udesc = "Probe miss", .pme_ucode = 1 << 0, }, { .pme_uname = "HIT_CLEAN", .pme_udesc = "Probe hit clean", .pme_ucode = 1 << 1, }, { .pme_uname = "HIT_DIRTY_NO_MEMORY_CANCEL", .pme_udesc = "Probe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)", .pme_ucode = 1 << 2, }, { .pme_uname = "HIT_DIRTY_WITH_MEMORY_CANCEL", .pme_udesc = "Probe hit dirty with memory cancel (probed by DMA read/cache refill request)", .pme_ucode = 1 << 3, }, { .pme_uname = "UPSTREAM_DISPLAY_REFRESH_READS", .pme_udesc = "Upstream display refresh/ISOC reads", .pme_ucode = 1 << 4, }, { .pme_uname = "UPSTREAM_NON_DISPLAY_REFRESH_READS", .pme_udesc = "Upstream non-display refresh reads", .pme_ucode = 1 << 5, }, { .pme_uname = "UPSTREAM_WRITES", .pme_udesc = "Upstream ISOC writes", .pme_ucode = 1 << 6, }, { .pme_uname = "UPSTREAM_NON_ISOC_WRITES", .pme_udesc = "Upstream non-ISOC writes", .pme_ucode = 1 << 7, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 88 */{.pme_name = "GART_EVENTS", .pme_code = 0xEE, .pme_desc = "GART Events", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 6, .pme_umasks = { { .pme_uname = "CPU_HIT", .pme_udesc = "GART aperture hit on access from CPU", .pme_ucode = 1 << 0, }, { .pme_uname = "IO_HIT", .pme_udesc = "GART aperture hit on access from IO", .pme_ucode = 1 << 1, }, { .pme_uname = "MISS", .pme_udesc = "GART miss", .pme_ucode = 1 << 2, }, { .pme_uname = "TABLE_WALK", .pme_udesc = "GART Request hit table walk in progress", .pme_ucode = 1 << 3, }, { .pme_uname = "MULTIPLE_TABLE_WALK", .pme_udesc = "GART multiple table walk in progress", .pme_ucode = 1 << 7, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x8F, }, }, }, /* 89 */{.pme_name = "HYPERTRANSPORT_LINK0_TRANSMIT_BANDWIDTH", .pme_code = 0xF6, .pme_desc = "HyperTransport(tm) Link 0 Transmit Bandwidth", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 8, .pme_umasks = { { .pme_uname = "COMMAND_DWORD_SENT", .pme_udesc = "Command DWORD sent", .pme_ucode = 1 << 0, }, { .pme_uname = "DATA_DWORD_SENT", .pme_udesc = "Data DWORD sent", .pme_ucode = 1 << 1, }, { .pme_uname = "BUFFER_RELEASE_DWORD_SENT", .pme_udesc = "Buffer release DWORD sent", .pme_ucode = 1 << 2, }, { .pme_uname = "NOP_DWORD_SENT", .pme_udesc = "Nop DW sent (idle)", .pme_ucode = 1 << 3, }, { .pme_uname = "ADDRESS_EXT_DWORD_SENT", .pme_udesc = "Address DWORD sent", .pme_ucode = 1 << 4, }, { .pme_uname = "PER_PACKET_CRC_SENT", .pme_udesc = "Per packet CRC sent", .pme_ucode = 1 << 5, }, { .pme_uname = "SUBLINK_MASK", .pme_udesc = "SubLink Mask", .pme_ucode = 1 << 7, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xBF, }, }, }, /* 90 */{.pme_name = "HYPERTRANSPORT_LINK1_TRANSMIT_BANDWIDTH", .pme_code = 0xF7, .pme_desc = "HyperTransport(tm) Link 1 Transmit Bandwidth", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 8, .pme_umasks = { { .pme_uname = "COMMAND_DWORD_SENT", .pme_udesc = "Command DWORD sent", .pme_ucode = 1 << 0, }, { .pme_uname = "DATA_DWORD_SENT", .pme_udesc = "Data DWORD sent", .pme_ucode = 1 << 1, }, { .pme_uname = "BUFFER_RELEASE_DWORD_SENT", .pme_udesc = "Buffer release DWORD sent", .pme_ucode = 1 << 2, }, { .pme_uname = "NOP_DWORD_SENT", .pme_udesc = "Nop DW sent (idle)", .pme_ucode = 1 << 3, }, { .pme_uname = "ADDRESS_EXT_DWORD_SENT", .pme_udesc = "Address DWORD sent", .pme_ucode = 1 << 4, }, { .pme_uname = "PER_PACKET_CRC_SENT", .pme_udesc = "Per packet CRC sent", .pme_ucode = 1 << 5, }, { .pme_uname = "SUBLINK_MASK", .pme_udesc = "SubLink Mask", .pme_ucode = 1 << 7, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xBF, }, }, }, /* 91 */{.pme_name = "HYPERTRANSPORT_LINK2_TRANSMIT_BANDWIDTH", .pme_code = 0xF8, .pme_desc = "HyperTransport(tm) Link 2 Transmit Bandwidth", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 8, .pme_umasks = { { .pme_uname = "COMMAND_DWORD_SENT", .pme_udesc = "Command DWORD sent", .pme_ucode = 1 << 0, }, { .pme_uname = "DATA_DWORD_SENT", .pme_udesc = "Data DWORD sent", .pme_ucode = 1 << 1, }, { .pme_uname = "BUFFER_RELEASE_DWORD_SENT", .pme_udesc = "Buffer release DWORD sent", .pme_ucode = 1 << 2, }, { .pme_uname = "NOP_DWORD_SENT", .pme_udesc = "Nop DW sent (idle)", .pme_ucode = 1 << 3, }, { .pme_uname = "ADDRESS_EXT_DWORD_SENT", .pme_udesc = "Address DWORD sent", .pme_ucode = 1 << 4, }, { .pme_uname = "PER_PACKET_CRC_SENT", .pme_udesc = "Per packet CRC sent", .pme_ucode = 1 << 5, }, { .pme_uname = "SUBLINK_MASK", .pme_udesc = "SubLink Mask", .pme_ucode = 1 << 7, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xBF, }, }, }, /* 92 */{.pme_name = "HYPERTRANSPORT_LINK3_TRANSMIT_BANDWIDTH", .pme_code = 0x1F9, .pme_desc = "HyperTransport(tm) Link 3 Transmit Bandwidth", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 8, .pme_umasks = { { .pme_uname = "COMMAND_DWORD_SENT", .pme_udesc = "Command DWORD sent", .pme_ucode = 1 << 0, }, { .pme_uname = "DATA_DWORD_SENT", .pme_udesc = "Data DWORD sent", .pme_ucode = 1 << 1, }, { .pme_uname = "BUFFER_RELEASE_DWORD_SENT", .pme_udesc = "Buffer release DWORD sent", .pme_ucode = 1 << 2, }, { .pme_uname = "NOP_DWORD_SENT", .pme_udesc = "Nop DW sent (idle)", .pme_ucode = 1 << 3, }, { .pme_uname = "ADDRESS_EXT_DWORD_SENT", .pme_udesc = "Address DWORD sent", .pme_ucode = 1 << 4, }, { .pme_uname = "PER_PACKET_CRC_SENT", .pme_udesc = "Per packet CRC sent", .pme_ucode = 1 << 5, }, { .pme_uname = "SUBLINK_MASK", .pme_udesc = "SubLink Mask", .pme_ucode = 1 << 7, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xBF, }, }, }, /* 93 */{.pme_name = "CPU_DRAM_REQUEST_TO_NODE", .pme_code = 0x1E0, .pme_desc = "CPU to DRAM Requests to Target Node", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "LOCAL_TO_0", .pme_udesc = "From Local node to Node 0", .pme_ucode = 1 << 0, }, { .pme_uname = "LOCAL_TO_1", .pme_udesc = "From Local node to Node 1", .pme_ucode = 1 << 1, }, { .pme_uname = "LOCAL_TO_2", .pme_udesc = "From Local node to Node 2", .pme_ucode = 1 << 2, }, { .pme_uname = "LOCAL_TO_3", .pme_udesc = "From Local node to Node 3", .pme_ucode = 1 << 3, }, { .pme_uname = "LOCAL_TO_4", .pme_udesc = "From Local node to Node 4", .pme_ucode = 1 << 4, }, { .pme_uname = "LOCAL_TO_5", .pme_udesc = "From Local node to Node 5", .pme_ucode = 1 << 5, }, { .pme_uname = "LOCAL_TO_6", .pme_udesc = "From Local node to Node 6", .pme_ucode = 1 << 6, }, { .pme_uname = "LOCAL_TO_7", .pme_udesc = "From Local node to Node 7", .pme_ucode = 1 << 7, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 94 */{.pme_name = "IO_DRAM_REQUEST_TO_NODE", .pme_code = 0x1E1, .pme_desc = "IO to DRAM Requests to Target Node", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "LOCAL_TO_0", .pme_udesc = "From Local node to Node 0", .pme_ucode = 1 << 0, }, { .pme_uname = "LOCAL_TO_1", .pme_udesc = "From Local node to Node 1", .pme_ucode = 1 << 1, }, { .pme_uname = "LOCAL_TO_2", .pme_udesc = "From Local node to Node 2", .pme_ucode = 1 << 2, }, { .pme_uname = "LOCAL_TO_3", .pme_udesc = "From Local node to Node 3", .pme_ucode = 1 << 3, }, { .pme_uname = "LOCAL_TO_4", .pme_udesc = "From Local node to Node 4", .pme_ucode = 1 << 4, }, { .pme_uname = "LOCAL_TO_5", .pme_udesc = "From Local node to Node 5", .pme_ucode = 1 << 5, }, { .pme_uname = "LOCAL_TO_6", .pme_udesc = "From Local node to Node 6", .pme_ucode = 1 << 6, }, { .pme_uname = "LOCAL_TO_7", .pme_udesc = "From Local node to Node 7", .pme_ucode = 1 << 7, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 95 */{.pme_name = "CPU_READ_COMMAND_LATENCY_NODE_0_3", .pme_code = 0x1E2, .pme_desc = "CPU Read Command Latency to Target Node 0-3", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "READ_BLOCK", .pme_udesc = "Read block", .pme_ucode = 1 << 0, }, { .pme_uname = "READ_BLOCK_SHARED", .pme_udesc = "Read block shared", .pme_ucode = 1 << 1, }, { .pme_uname = "READ_BLOCK_MODIFIED", .pme_udesc = "Read block modified", .pme_ucode = 1 << 2, }, { .pme_uname = "CHANGE_TO_DIRTY", .pme_udesc = "Change-to-Dirty", .pme_ucode = 1 << 3, }, { .pme_uname = "LOCAL_TO_0", .pme_udesc = "From Local node to Node 0", .pme_ucode = 1 << 4, }, { .pme_uname = "LOCAL_TO_1", .pme_udesc = "From Local node to Node 1", .pme_ucode = 1 << 5, }, { .pme_uname = "LOCAL_TO_2", .pme_udesc = "From Local node to Node 2", .pme_ucode = 1 << 6, }, { .pme_uname = "LOCAL_TO_3", .pme_udesc = "From Local node to Node 3", .pme_ucode = 1 << 7, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 96 */{.pme_name = "CPU_READ_COMMAND_REQUEST_NODE_0_3", .pme_code = 0x1E3, .pme_desc = "CPU Read Command Requests to Target Node 0-3", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "READ_BLOCK", .pme_udesc = "Read block", .pme_ucode = 1 << 0, }, { .pme_uname = "READ_BLOCK_SHARED", .pme_udesc = "Read block shared", .pme_ucode = 1 << 1, }, { .pme_uname = "READ_BLOCK_MODIFIED", .pme_udesc = "Read block modified", .pme_ucode = 1 << 2, }, { .pme_uname = "CHANGE_TO_DIRTY", .pme_udesc = "Change-to-Dirty", .pme_ucode = 1 << 3, }, { .pme_uname = "LOCAL_TO_0", .pme_udesc = "From Local node to Node 0", .pme_ucode = 1 << 4, }, { .pme_uname = "LOCAL_TO_1", .pme_udesc = "From Local node to Node 1", .pme_ucode = 1 << 5, }, { .pme_uname = "LOCAL_TO_2", .pme_udesc = "From Local node to Node 2", .pme_ucode = 1 << 6, }, { .pme_uname = "LOCAL_TO_3", .pme_udesc = "From Local node to Node 3", .pme_ucode = 1 << 7, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 97 */{.pme_name = "CPU_READ_COMMAND_LATENCY_NODE_4_7", .pme_code = 0x1E4, .pme_desc = "CPU Read Command Latency to Target Node 4-7", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "READ_BLOCK", .pme_udesc = "Read block", .pme_ucode = 1 << 0, }, { .pme_uname = "READ_BLOCK_SHARED", .pme_udesc = "Read block shared", .pme_ucode = 1 << 1, }, { .pme_uname = "READ_BLOCK_MODIFIED", .pme_udesc = "Read block modified", .pme_ucode = 1 << 2, }, { .pme_uname = "CHANGE_TO_DIRTY", .pme_udesc = "Change-to-Dirty", .pme_ucode = 1 << 3, }, { .pme_uname = "LOCAL_TO_4", .pme_udesc = "From Local node to Node 4", .pme_ucode = 1 << 4, }, { .pme_uname = "LOCAL_TO_5", .pme_udesc = "From Local node to Node 5", .pme_ucode = 1 << 5, }, { .pme_uname = "LOCAL_TO_6", .pme_udesc = "From Local node to Node 6", .pme_ucode = 1 << 6, }, { .pme_uname = "LOCAL_TO_7", .pme_udesc = "From Local node to Node 7", .pme_ucode = 1 << 7, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 98 */{.pme_name = "CPU_READ_COMMAND_REQUEST_NODE_4_7", .pme_code = 0x1E5, .pme_desc = "CPU Read Command Requests to Target Node 4-7", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "READ_BLOCK", .pme_udesc = "Read block", .pme_ucode = 1 << 0, }, { .pme_uname = "READ_BLOCK_SHARED", .pme_udesc = "Read block shared", .pme_ucode = 1 << 1, }, { .pme_uname = "READ_BLOCK_MODIFIED", .pme_udesc = "Read block modified", .pme_ucode = 1 << 2, }, { .pme_uname = "CHANGE_TO_DIRTY", .pme_udesc = "Change-to-Dirty", .pme_ucode = 1 << 3, }, { .pme_uname = "LOCAL_TO_4", .pme_udesc = "From Local node to Node 4", .pme_ucode = 1 << 4, }, { .pme_uname = "LOCAL_TO_5", .pme_udesc = "From Local node to Node 5", .pme_ucode = 1 << 5, }, { .pme_uname = "LOCAL_TO_6", .pme_udesc = "From Local node to Node 6", .pme_ucode = 1 << 6, }, { .pme_uname = "LOCAL_TO_7", .pme_udesc = "From Local node to Node 7", .pme_ucode = 1 << 7, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 99 */{.pme_name = "CPU_COMMAND_LATENCY_TARGET", .pme_code = 0x1E6, .pme_desc = "CPU Command Latency to Target Node 0-3/4-7", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "READ_SIZED", .pme_udesc = "Read Sized", .pme_ucode = 1 << 0, }, { .pme_uname = "WRITE_SIZED", .pme_udesc = "Write Sized", .pme_ucode = 1 << 1, }, { .pme_uname = "VICTIM_BLOCK", .pme_udesc = "Victim Block", .pme_ucode = 1 << 2, }, { .pme_uname = "NODE_GROUP_SELECT", .pme_udesc = "Node Group Select: 0=Nodes 0-3, 1= Nodes 4-7", .pme_ucode = 1 << 3, }, { .pme_uname = "LOCAL_TO_0_4", .pme_udesc = "From Local node to Node 0/4", .pme_ucode = 1 << 4, }, { .pme_uname = "LOCAL_TO_1_5", .pme_udesc = "From Local node to Node 1/5", .pme_ucode = 1 << 5, }, { .pme_uname = "LOCAL_TO_2_6", .pme_udesc = "From Local node to Node 2/6", .pme_ucode = 1 << 6, }, { .pme_uname = "LOCAL_TO_3_7", .pme_udesc = "From Local node to Node 3/7", .pme_ucode = 1 << 7, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 100 */{.pme_name = "CPU_REQUEST_TARGET", .pme_code = 0x1E7, .pme_desc = "CPU Requests to Target Node 0-3/4-7", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "READ_SIZED", .pme_udesc = "Read Sized", .pme_ucode = 1 << 0, }, { .pme_uname = "WRITE_SIZED", .pme_udesc = "Write Sized", .pme_ucode = 1 << 1, }, { .pme_uname = "VICTIM_BLOCK", .pme_udesc = "Victim Block", .pme_ucode = 1 << 2, }, { .pme_uname = "NODE_GROUP_SELECT", .pme_udesc = "Node Group Select: 0=Nodes 0-3, 1= Nodes 4-7", .pme_ucode = 1 << 3, }, { .pme_uname = "LOCAL_TO_0_4", .pme_udesc = "From Local node to Node 0/4", .pme_ucode = 1 << 4, }, { .pme_uname = "LOCAL_TO_1_5", .pme_udesc = "From Local node to Node 1/5", .pme_ucode = 1 << 5, }, { .pme_uname = "LOCAL_TO_2_6", .pme_udesc = "From Local node to Node 2/6", .pme_ucode = 1 << 6, }, { .pme_uname = "LOCAL_TO_3_7", .pme_udesc = "From Local node to Node 3/7", .pme_ucode = 1 << 7, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 101 */{.pme_name = "MEMORY_CONTROLLER_REQUESTS", .pme_code = 0x1F0, .pme_desc = "Memory Controller Requests", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "WRITE_REQUESTS", .pme_udesc = "Write requests sent to the DCT", .pme_ucode = 1 << 0, }, { .pme_uname = "READ_REQUESTS", .pme_udesc = "Read requests (including prefetch requests) sent to the DCT", .pme_ucode = 1 << 1, }, { .pme_uname = "PREFETCH_REQUESTS", .pme_udesc = "Prefetch requests sent to the DCT", .pme_ucode = 1 << 2, }, { .pme_uname = "32_BYTES_WRITES", .pme_udesc = "32 Bytes Sized Writes", .pme_ucode = 1 << 3, }, { .pme_uname = "64_BYTES_WRITES", .pme_udesc = "64 Bytes Sized Writes", .pme_ucode = 1 << 4, }, { .pme_uname = "32_BYTES_READS", .pme_udesc = "32 Bytes Sized Reads", .pme_ucode = 1 << 5, }, { .pme_uname = "64_BYTES_READS", .pme_udesc = "64 Byte Sized Reads", .pme_ucode = 1 << 6, }, { .pme_uname = "READ_REQUESTS_WHILE_WRITES_REQUESTS", .pme_udesc = "Read requests sent to the DCT while writes requests are pending in the DCT", .pme_ucode = 1 << 7, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 102 */{.pme_name = "READ_REQUEST_L3_CACHE", .pme_code = 0x4E0, .pme_desc = "Read Request to L3 Cache", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 13, .pme_umasks = { { .pme_uname = "READ_BLOCK_EXCLUSIVE", .pme_udesc = "Read Block Exclusive (Data cache read)", .pme_ucode = 1 << 0, }, { .pme_uname = "READ_BLOCK_SHARED", .pme_udesc = "Read Block Shared (Instruction cache read)", .pme_ucode = 1 << 1, }, { .pme_uname = "READ_BLOCK_MODIFY", .pme_udesc = "Read Block Modify", .pme_ucode = 1 << 2, }, { .pme_uname = "PREFETCH_ONLY", .pme_udesc = "1=Count prefetch only, 0=Count prefetch and non-prefetch", .pme_ucode = 1 << 3, }, { .pme_uname = "CORE_0_SELECT", .pme_udesc = "Core 0 Select", .pme_ucode = 0x00, }, { .pme_uname = "CORE_1_SELECT", .pme_udesc = "Core 1 Select", .pme_ucode = 0x10, }, { .pme_uname = "CORE_2_SELECT", .pme_udesc = "Core 2 Select", .pme_ucode = 0x20, }, { .pme_uname = "CORE_3_SELECT", .pme_udesc = "Core 3 Select", .pme_ucode = 0x30, }, { .pme_uname = "CORE_4_SELECT", .pme_udesc = "Core 4 Select", .pme_ucode = 0x40, }, { .pme_uname = "CORE_5_SELECT", .pme_udesc = "Core 5 Select", .pme_ucode = 0x50, }, { .pme_uname = "CORE_6_SELECT", .pme_udesc = "Core 6 Select", .pme_ucode = 0x60, }, { .pme_uname = "CORE_7_SELECT", .pme_udesc = "Core 7 Select", .pme_ucode = 0x70, }, { .pme_uname = "ALL_CORES", .pme_udesc = "All cores", .pme_ucode = 0xF0, }, }, }, /* 103 */{.pme_name = "L3_CACHE_MISSES", .pme_code = 0x4E1, .pme_desc = "L3 Cache Misses", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 13, .pme_umasks = { { .pme_uname = "READ_BLOCK_EXCLUSIVE", .pme_udesc = "Read Block Exclusive (Data cache read)", .pme_ucode = 1 << 0, }, { .pme_uname = "READ_BLOCK_SHARED", .pme_udesc = "Read Block Shared (Instruction cache read)", .pme_ucode = 1 << 1, }, { .pme_uname = "READ_BLOCK_MODIFY", .pme_udesc = "Read Block Modify", .pme_ucode = 1 << 2, }, { .pme_uname = "PREFETCH_ONLY", .pme_udesc = "1=Count prefetch only, 0=Count prefetch and non-prefetch", .pme_ucode = 1 << 3, }, { .pme_uname = "CORE_0_SELECT", .pme_udesc = "Core 0 Select", .pme_ucode = 0x00, }, { .pme_uname = "CORE_1_SELECT", .pme_udesc = "Core 1 Select", .pme_ucode = 0x10, }, { .pme_uname = "CORE_2_SELECT", .pme_udesc = "Core 2 Select", .pme_ucode = 0x20, }, { .pme_uname = "CORE_3_SELECT", .pme_udesc = "Core 3 Select", .pme_ucode = 0x30, }, { .pme_uname = "CORE_4_SELECT", .pme_udesc = "Core 4 Select", .pme_ucode = 0x40, }, { .pme_uname = "CORE_5_SELECT", .pme_udesc = "Core 5 Select", .pme_ucode = 0x50, }, { .pme_uname = "CORE_6_SELECT", .pme_udesc = "Core 6 Select", .pme_ucode = 0x60, }, { .pme_uname = "CORE_7_SELECT", .pme_udesc = "Core 7 Select", .pme_ucode = 0x70, }, { .pme_uname = "ALL_CORES", .pme_udesc = "All cores", .pme_ucode = 0xF0, }, }, }, /* 104 */{.pme_name = "L3_FILLS_CAUSED_BY_L2_EVICTIONS", .pme_code = 0x4E2, .pme_desc = "L3 Fills caused by L2 Evictions", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 13, .pme_umasks = { { .pme_uname = "SHARED", .pme_udesc = "Shared", .pme_ucode = 1 << 0, }, { .pme_uname = "EXCLUSIVE", .pme_udesc = "Exclusive", .pme_ucode = 1 << 1, }, { .pme_uname = "OWNED", .pme_udesc = "Owned", .pme_ucode = 1 << 2, }, { .pme_uname = "MODIFIED", .pme_udesc = "Modified", .pme_ucode = 1 << 3, }, { .pme_uname = "CORE_0_SELECT", .pme_udesc = "Core 0 Select", .pme_ucode = 0x00, }, { .pme_uname = "CORE_1_SELECT", .pme_udesc = "Core 1 Select", .pme_ucode = 0x10, }, { .pme_uname = "CORE_2_SELECT", .pme_udesc = "Core 2 Select", .pme_ucode = 0x20, }, { .pme_uname = "CORE_3_SELECT", .pme_udesc = "Core 3 Select", .pme_ucode = 0x30, }, { .pme_uname = "CORE_4_SELECT", .pme_udesc = "Core 4 Select", .pme_ucode = 0x40, }, { .pme_uname = "CORE_5_SELECT", .pme_udesc = "Core 5 Select", .pme_ucode = 0x50, }, { .pme_uname = "CORE_6_SELECT", .pme_udesc = "Core 6 Select", .pme_ucode = 0x60, }, { .pme_uname = "CORE_7_SELECT", .pme_udesc = "Core 7 Select", .pme_ucode = 0x70, }, { .pme_uname = "ALL_CORES", .pme_udesc = "All cores", .pme_ucode = 0xF0, }, }, }, /* 105 */{.pme_name = "L3_EVICTIONS", .pme_code = 0x4E3, .pme_desc = "L3 Evictions", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 5, .pme_umasks = { { .pme_uname = "SHARED", .pme_udesc = "Shared", .pme_ucode = 1 << 0, }, { .pme_uname = "EXCLUSIVE", .pme_udesc = "Exclusive", .pme_ucode = 1 << 1, }, { .pme_uname = "OWNED", .pme_udesc = "Owned", .pme_ucode = 1 << 2, }, { .pme_uname = "MODIFIED", .pme_udesc = "Modified", .pme_ucode = 1 << 3, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x0F, }, }, }, /* 106 */{.pme_name = "NON_CANCELLED_L3_READ_REQUESTS", .pme_code = 0x4ED, .pme_desc = "Non-canceled L3 Read Requests", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 13, .pme_umasks = { { .pme_uname = "RDBLK", .pme_udesc = "RdBlk", .pme_ucode = 1 << 0, }, { .pme_uname = "RDBLKS", .pme_udesc = "RdBlkS", .pme_ucode = 1 << 1, }, { .pme_uname = "RDBLKM", .pme_udesc = "RdBlkM", .pme_ucode = 1 << 2, }, { .pme_uname = "PREFETCH_ONLY", .pme_udesc = "1=Count prefetch only; 0=Count prefetch and non-prefetch", .pme_ucode = 1 << 3, }, { .pme_uname = "CORE_0_SELECT", .pme_udesc = "Core 0 Select", .pme_ucode = 0x00, }, { .pme_uname = "CORE_1_SELECT", .pme_udesc = "Core 1 Select", .pme_ucode = 0x10, }, { .pme_uname = "CORE_2_SELECT", .pme_udesc = "Core 2 Select", .pme_ucode = 0x20, }, { .pme_uname = "CORE_3_SELECT", .pme_udesc = "Core 3 Select", .pme_ucode = 0x30, }, { .pme_uname = "CORE_4_SELECT", .pme_udesc = "Core 4 Select", .pme_ucode = 0x40, }, { .pme_uname = "CORE_5_SELECT", .pme_udesc = "Core 5 Select", .pme_ucode = 0x50, }, { .pme_uname = "CORE_6_SELECT", .pme_udesc = "Core 6 Select", .pme_ucode = 0x60, }, { .pme_uname = "CORE_7_SELECT", .pme_udesc = "Core 7 Select", .pme_ucode = 0x70, }, { .pme_uname = "ALL_CORES", .pme_udesc = "All cores", .pme_ucode = 0xF0, }, }, }, #endif /* 107 */{.pme_name = "LS_DISPATCH", .pme_code = 0x29, .pme_desc = "LS Dispatch", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 4, .pme_umasks = { { .pme_uname = "LOADS", .pme_udesc = "Loads", .pme_ucode = 1 << 0, }, { .pme_uname = "STORES", .pme_udesc = "Stores", .pme_ucode = 1 << 1, }, { .pme_uname = "LOAD_OP_STORES", .pme_udesc = "Load-op-Stores", .pme_ucode = 1 << 2, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x07, }, }, }, /* 108 */{.pme_name = "EXECUTED_CLFLUSH_INSTRUCTIONS", .pme_code = 0x30, .pme_desc = "Executed CLFLUSH Instructions", }, /* 109 */{.pme_name = "L2_PREFETCHER_TRIGGER_EVENTS", .pme_code = 0x16C, .pme_desc = "L2 Prefetcher Trigger Events", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 3, .pme_umasks = { { .pme_uname = "LOAD_L1_MISS_SEEN_BY_PREFETCHER", .pme_udesc = "Load L1 miss seen by prefetcher", .pme_ucode = 1 << 0, }, { .pme_uname = "STORE_L1_MISS_SEEN_BY_PREFETCHER", .pme_udesc = "Store L1 miss seen by prefetcher", .pme_ucode = 1 << 1, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x03, }, }, }, /* 110 */{.pme_name = "DISPATCH_STALL_FOR_STQ_FULL", .pme_code = 0x1D8, .pme_desc = "Dispatch Stall for STQ Full", }, /* Northbridge events (.pme_code & 0x0E0) not yet supported by the kernel */ #if 0 /* 111 */{.pme_name = "REQUEST_CACHE_STATUS_0", .pme_code = 0x1EA, .pme_desc = "Request Cache Status 0", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "PROBE_HIT_S", .pme_udesc = "Probe Hit S", .pme_ucode = 1 << 0, }, { .pme_uname = "PROBE_HIT_E", .pme_udesc = "Probe Hit E", .pme_ucode = 1 << 1, }, { .pme_uname = "PROBE_HIT_MUW_OR_O", .pme_udesc = "Probe Hit MuW or O", .pme_ucode = 1 << 2, }, { .pme_uname = "PROBE_HIT_M", .pme_udesc = "Probe Hit M", .pme_ucode = 1 << 3, }, { .pme_uname = "PROBE_MISS", .pme_udesc = "Probe Miss", .pme_ucode = 1 << 4, }, { .pme_uname = "DIRECTED_PROBE", .pme_udesc = "Directed Probe", .pme_ucode = 1 << 5, }, { .pme_uname = "TRACK_CACHE_STAT_FOR_RDBLK", .pme_udesc = "Track Cache Stat for RdBlk", .pme_ucode = 1 << 6, }, { .pme_uname = "TRACK_CACHE_STAT_FOR_RDBLKS", .pme_udesc = "Track Cache Stat for RdBlkS", .pme_ucode = 1 << 7, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 112 */{.pme_name = "REQUEST_CACHE_STATUS_1", .pme_code = 0x1EB, .pme_desc = "Request Cache Status 1", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "PROBE_HIT_S", .pme_udesc = "Probe Hit S", .pme_ucode = 1 << 0, }, { .pme_uname = "PROBE_HIT_E", .pme_udesc = "Probe Hit E", .pme_ucode = 1 << 1, }, { .pme_uname = "PROBE_HIT_MUW_OR_O", .pme_udesc = "Probe Hit MuW or O", .pme_ucode = 1 << 2, }, { .pme_uname = "PROBE_HIT_M", .pme_udesc = "Probe Hit M", .pme_ucode = 1 << 3, }, { .pme_uname = "PROBE_MISS", .pme_udesc = "Probe Miss", .pme_ucode = 1 << 4, }, { .pme_uname = "DIRECTED_PROBE", .pme_udesc = "Directed Probe", .pme_ucode = 1 << 5, }, { .pme_uname = "TRACK_CACHE_STAT_FOR_CHGTODIRTY", .pme_udesc = "Track Cache Stat for ChgToDirty", .pme_ucode = 1 << 6, }, { .pme_uname = "TRACK_CACHE_STAT_FOR_RDBLKM", .pme_udesc = "Track Cache Stat for RdBlkM", .pme_ucode = 1 << 7, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 113 */{.pme_name = "L3_LATENCY", .pme_code = 0x4EF, .pme_desc = "L3 Latency", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 3, .pme_umasks = { { .pme_uname = "L3CYCCOUNT", .pme_udesc = "L3CycCount. L3 Request cycle count", .pme_ucode = 1 << 0, }, { .pme_uname = "L3REQCOUNT", .pme_udesc = "L3ReqCount. L3 request count", .pme_ucode = 1 << 1, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x03, }, }, }, #endif }; #define PME_AMD64_FAM15H_EVENT_COUNT (sizeof(amd64_fam15h_pe)/sizeof(pme_amd64_entry_t)) #define PME_AMD64_FAM15H_CPU_CLK_UNHALTED 30 #define PME_AMD64_FAM15H_RETIRED_INSTRUCTIONS 49 papi-5.5.1/src/libpfm-3.y/lib/pfmlib_amd64_priv.h0000644000307100002310000001107213013651450021346 0ustar yarkhangraduate/* * Copyright (c) 2004-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #ifndef __PFMLIB_AMD64_PRIV_H__ #define __PFMLIB_AMD64_PRIV_H__ /* * PERFSEL/PERFCTR include IBS registers: * * PMCs PMDs * * PERFCTRS 6 6 * IBS FETCH 1 3 * IBS OP 1 7 * * total 8 16 */ #define PMU_AMD64_NUM_PERFSEL 8 /* number of PMCs defined */ #define PMU_AMD64_NUM_PERFCTR 16 /* number of PMDs defined */ #define PMU_AMD64_NUM_COUNTERS 4 /* number of EvtSel/EvtCtr */ #define PMU_AMD64_NUM_COUNTERS_F15H 6 /* number of EvtSel/EvtCtr */ #define PMU_AMD64_COUNTER_WIDTH 48 /* hw counter bit width */ #define PMU_AMD64_CNT_MASK_MAX 4 /* max cnt_mask value */ #define PMU_AMD64_IBSFETCHCTL_PMC 6 /* IBS: fetch PMC base */ #define PMU_AMD64_IBSFETCHCTL_PMD 6 /* IBS: fetch PMD base */ #define PMU_AMD64_IBSOPCTL_PMC 7 /* IBS: op PMC base */ #define PMU_AMD64_IBSOPCTL_PMD 9 /* IBS: op PMD base */ #define PFMLIB_AMD64_MAX_UMASK 13 typedef struct { char *pme_uname; /* unit mask name */ char *pme_udesc; /* event/umask description */ unsigned int pme_ucode; /* unit mask code */ unsigned int pme_uflags; /* unit mask flags */ } pme_amd64_umask_t; typedef struct { char *pme_name; /* event name */ char *pme_desc; /* event description */ pme_amd64_umask_t pme_umasks[PFMLIB_AMD64_MAX_UMASK]; /* umask desc */ unsigned int pme_code; /* event code */ unsigned int pme_numasks; /* number of umasks */ unsigned int pme_flags; /* flags */ } pme_amd64_entry_t; typedef enum { AMD64_CPU_UN, AMD64_K7, AMD64_K8_REV_B, AMD64_K8_REV_C, AMD64_K8_REV_D, AMD64_K8_REV_E, AMD64_K8_REV_F, AMD64_K8_REV_G, AMD64_FAM10H_REV_B, AMD64_FAM10H_REV_C, AMD64_FAM10H_REV_D, AMD64_FAM10H_REV_E, AMD64_FAM15H_REV_B, } amd64_rev_t; static const char *amd64_rev_strs[]= { "?", "?", /* K8 */ "B", "C", "D", "E", "F", "G", /* Family 10h */ "B", "C", "D", "E", /* Family 15h */ "B", }; static const char *amd64_cpu_strs[] = { "AMD64 (unknown model)", "AMD64 (K7)", "AMD64 (K8 RevB)", "AMD64 (K8 RevC)", "AMD64 (K8 RevD)", "AMD64 (K8 RevE)", "AMD64 (K8 RevF)", "AMD64 (K8 RevG)", "AMD64 (Family 10h RevB, Barcelona)", "AMD64 (Family 10h RevC, Shanghai)", "AMD64 (Family 10h RevD, Istanbul)", "AMD64 (Family 10h RevE)", "AMD64 (Family 15h RevB)", }; /* * pme_flags values */ #define PFMLIB_AMD64_UMASK_COMBO 0x1 /* unit mask can be combined */ #define PFMLIB_AMD64_FROM_REV(rev) ((rev)<<8) #define PFMLIB_AMD64_TILL_REV(rev) ((rev)<<16) #define PFMLIB_AMD64_NOT_SUPP 0x1ff00 #define PFMLIB_AMD64_TILL_K8_REV_C PFMLIB_AMD64_TILL_REV(AMD64_K8_REV_C) #define PFMLIB_AMD64_K8_REV_D PFMLIB_AMD64_FROM_REV(AMD64_K8_REV_D) #define PFMLIB_AMD64_K8_REV_E PFMLIB_AMD64_FROM_REV(AMD64_K8_REV_E) #define PFMLIB_AMD64_TILL_K8_REV_E PFMLIB_AMD64_TILL_REV(AMD64_K8_REV_E) #define PFMLIB_AMD64_K8_REV_F PFMLIB_AMD64_FROM_REV(AMD64_K8_REV_F) #define PFMLIB_AMD64_TILL_FAM10H_REV_B PFMLIB_AMD64_TILL_REV(AMD64_FAM10H_REV_B) #define PFMLIB_AMD64_FAM10H_REV_C PFMLIB_AMD64_FROM_REV(AMD64_FAM10H_REV_C) #define PFMLIB_AMD64_TILL_FAM10H_REV_C PFMLIB_AMD64_TILL_REV(AMD64_FAM10H_REV_C) #define PFMLIB_AMD64_FAM10H_REV_D PFMLIB_AMD64_FROM_REV(AMD64_FAM10H_REV_D) static inline int from_revision(unsigned int flags) { return ((flags) >> 8) & 0xff; } static inline int till_revision(unsigned int flags) { int till = (((flags)>>16) & 0xff); if (!till) return 0xff; return till; } #endif /* __PFMLIB_AMD64_PRIV_H__ */ papi-5.5.1/src/libpfm-3.y/lib/pfmlib_itanium2.c0000644000307100002310000017353213013651450021130 0ustar yarkhangraduate/* * pfmlib_itanium2.c : support for the Itanium2 PMU family * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include /* public headers */ #include /* private headers */ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_priv_ia64.h" /* architecture private */ #include "pfmlib_itanium2_priv.h" /* PMU private */ #include "itanium2_events.h" /* PMU private */ #define is_ear(i) event_is_ear(itanium2_pe+(i)) #define is_ear_tlb(i) event_is_ear_tlb(itanium2_pe+(i)) #define is_ear_alat(i) event_is_ear_alat(itanium2_pe+(i)) #define is_ear_cache(i) event_is_ear_cache(itanium2_pe+(i)) #define is_iear(i) event_is_iear(itanium2_pe+(i)) #define is_dear(i) event_is_dear(itanium2_pe+(i)) #define is_btb(i) event_is_btb(itanium2_pe+(i)) #define has_opcm(i) event_opcm_ok(itanium2_pe+(i)) #define has_iarr(i) event_iarr_ok(itanium2_pe+(i)) #define has_darr(i) event_darr_ok(itanium2_pe+(i)) #define evt_use_opcm(e) ((e)->pfp_ita2_pmc8.opcm_used != 0 || (e)->pfp_ita2_pmc9.opcm_used !=0) #define evt_use_irange(e) ((e)->pfp_ita2_irange.rr_used) #define evt_use_drange(e) ((e)->pfp_ita2_drange.rr_used) #define evt_grp(e) (int)itanium2_pe[e].pme_qualifiers.pme_qual.pme_group #define evt_set(e) (int)itanium2_pe[e].pme_qualifiers.pme_qual.pme_set #define evt_umask(e) itanium2_pe[e].pme_umask #define FINE_MODE_BOUNDARY_BITS 12 #define FINE_MODE_MASK ~((1U<<12)-1) /* let's define some handy shortcuts! */ #define pmc_plm pmc_ita2_counter_reg.pmc_plm #define pmc_ev pmc_ita2_counter_reg.pmc_ev #define pmc_oi pmc_ita2_counter_reg.pmc_oi #define pmc_pm pmc_ita2_counter_reg.pmc_pm #define pmc_es pmc_ita2_counter_reg.pmc_es #define pmc_umask pmc_ita2_counter_reg.pmc_umask #define pmc_thres pmc_ita2_counter_reg.pmc_thres #define pmc_ism pmc_ita2_counter_reg.pmc_ism static char * pfm_ita2_get_event_name(unsigned int i); /* * Description of the PMC register mappings use by * this module (as reported in pfmlib_reg_t.reg_num): * * 0 -> PMC0 * 1 -> PMC1 * n -> PMCn * * The following are in the model specific rr_br[]: * IBR0 -> 0 * IBR1 -> 1 * ... * IBR7 -> 7 * DBR0 -> 0 * DBR1 -> 1 * ... * DBR7 -> 7 * * We do not use a mapping table, instead we make up the * values on the fly given the base. */ /* * The Itanium2 PMU has a bug in the fine mode implementation. * It only sees ranges with a granularity of two bundles. * So we prepare for the day they fix it. */ static int has_fine_mode_bug; static int pfm_ita2_detect(void) { int tmp; int ret = PFMLIB_ERR_NOTSUPP; tmp = pfm_ia64_get_cpu_family(); if (tmp == 0x1f) { has_fine_mode_bug = 1; ret = PFMLIB_SUCCESS; } return ret; } /* * Check the event for incompatibilities. This is useful * for L1 and L2 related events. Due to wire limitations, * some caches events are separated into sets. There * are 5 sets for the L1D cache group and 6 sets for L2 group. * It is NOT possible to simultaneously measure events from * differents sets within a group. For instance, you cannot * measure events from set0 and set1 in L1D cache group. However * it is possible to measure set0 in L1D and set1 in L2 at the same * time. * * This function verifies that the set constraint are respected. */ static int check_cross_groups_and_umasks(pfmlib_input_param_t *inp) { unsigned long ref_umask, umask; int g, s; unsigned int cnt = inp->pfp_event_count; pfmlib_event_t *e = inp->pfp_events; unsigned int i, j; /* * XXX: could possibly be optimized */ for (i=0; i < cnt; i++) { g = evt_grp(e[i].event); s = evt_set(e[i].event); if (g == PFMLIB_ITA2_EVT_NO_GRP) continue; ref_umask = evt_umask(e[i].event); for (j=i+1; j < cnt; j++) { if (evt_grp(e[j].event) != g) continue; if (evt_set(e[j].event) != s) return PFMLIB_ERR_EVTSET; /* only care about L2 cache group */ if (g != PFMLIB_ITA2_EVT_L2_CACHE_GRP || (s == 1 || s == 2)) continue; umask = evt_umask(e[j].event); /* * there is no assignement possible if the event in PMC4 * has a umask (ref_umask) and an event (from the same * set) also has a umask AND it is different. For some * sets, the umasks are shared, therefore the value * programmed into PMC4 determines the umask for all * the other events (with umask) from the set. */ if (umask && ref_umask != umask) return PFMLIB_ERR_NOASSIGN; } } return PFMLIB_SUCCESS; } /* * Certain prefetch events must be treated specially when instruction range restriction * is in use because they can only be constrained by IBRP1 in fine-mode. Other events * will use IBRP0 if tagged as a demand fetch OR IBPR1 if tagged as a prefetch match. * From the library's point of view there is no way of distinguishing this, so we leave * it up to the user to interpret the results. * * Events which can be qualified by the two pairs depending on their tag: * - IBP_BUNPAIRS_IN * - L1I_FETCH_RAB_HIT * - L1I_FETCH_ISB_HIT * - L1I_FILLS * * This function returns the number of qualifying prefetch events found * * XXX: not clear which events do qualify as prefetch events. */ static int prefetch_events[]={ PME_ITA2_L1I_PREFETCHES, PME_ITA2_L1I_STRM_PREFETCHES, PME_ITA2_L2_INST_PREFETCHES }; #define NPREFETCH_EVENTS sizeof(prefetch_events)/sizeof(int) static int check_prefetch_events(pfmlib_input_param_t *inp) { int code; int prefetch_codes[NPREFETCH_EVENTS]; unsigned int i, j, count; int c; int found = 0; for(i=0; i < NPREFETCH_EVENTS; i++) { pfm_get_event_code(prefetch_events[i], &code); prefetch_codes[i] = code; } count = inp->pfp_event_count; for(i=0; i < count; i++) { pfm_get_event_code(inp->pfp_events[i].event, &c); for(j=0; j < NPREFETCH_EVENTS; j++) { if (c == prefetch_codes[j]) found++; } } return found; } /* * IA64_INST_RETIRED (and subevents) is the only event which can be measured on all * 4 IBR when non-fine mode is not possible. * * This function returns: * - the number of events matching the IA64_INST_RETIRED code * - in retired_mask the bottom 4 bits indicates which of the 4 INST_RETIRED event * is present */ static unsigned int check_inst_retired_events(pfmlib_input_param_t *inp, unsigned long *retired_mask) { int code; int c, ret; unsigned int i, count, found = 0; unsigned long umask, mask; pfm_get_event_code(PME_ITA2_IA64_INST_RETIRED_THIS, &code); count = inp->pfp_event_count; mask = 0; for(i=0; i < count; i++) { ret = pfm_get_event_code(inp->pfp_events[i].event, &c); if (c == code) { ret = pfm_ita2_get_event_umask(inp->pfp_events[i].event, &umask); if (ret != PFMLIB_SUCCESS) break; switch(umask) { case 0: mask |= 1; break; case 1: mask |= 2; break; case 2: mask |= 4; break; case 3: mask |= 8; break; } found++; } } if (retired_mask) *retired_mask = mask; return found; } static int check_fine_mode_possible(pfmlib_ita2_input_rr_t *rr, int n) { pfmlib_ita2_input_rr_desc_t *lim = rr->rr_limits; int i; for(i=0; i < n; i++) { if ((lim[i].rr_start & FINE_MODE_MASK) != (lim[i].rr_end & FINE_MODE_MASK)) return 0; } return 1; } /* * mode = 0 -> check code (enforce bundle alignment) * mode = 1 -> check data */ static int check_intervals(pfmlib_ita2_input_rr_t *irr, int mode, unsigned int *n_intervals) { unsigned int i; pfmlib_ita2_input_rr_desc_t *lim = irr->rr_limits; for(i=0; i < 4; i++) { /* end marker */ if (lim[i].rr_start == 0 && lim[i].rr_end == 0) break; /* invalid entry */ if (lim[i].rr_start >= lim[i].rr_end) return PFMLIB_ERR_IRRINVAL; if (mode == 0 && (lim[i].rr_start & 0xf || lim[i].rr_end & 0xf)) return PFMLIB_ERR_IRRALIGN; } *n_intervals = i; return PFMLIB_SUCCESS; } static int valid_assign(pfmlib_event_t *e, unsigned int *as, pfmlib_regmask_t *r_pmcs, unsigned int cnt) { unsigned long pmc4_umask = 0, umask; char *name; int l1_grp_present = 0, l2_grp_present = 0; unsigned int i; int c, failure; int need_pmc5, need_pmc4; int pmc5_evt = -1, pmc4_evt = -1; if (PFMLIB_DEBUG()) { unsigned int j; for(j=0;jpfp_event_count; for(i=0; i < count; i++) { for (j=0; j < NCANCEL_EVENTS; j++) { pfm_get_event_code(inp->pfp_events[i].event, &code); if (code == cancel_codes[j]) { if (idx != -1) { return PFMLIB_ERR_INVAL; } idx = inp->pfp_events[i].event; } } } return PFMLIB_SUCCESS; } /* * Automatically dispatch events to corresponding counters following constraints. * Upon return the pfarg_regt structure is ready to be submitted to kernel */ static int pfm_ita2_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t *mod_in, pfmlib_output_param_t *outp) { #define has_counter(e,b) (itanium2_pe[e].pme_counters & (1 << (b)) ? (b) : 0) pfmlib_ita2_input_param_t *param = mod_in; pfm_ita2_pmc_reg_t reg; pfmlib_event_t *e; pfmlib_reg_t *pc, *pd; pfmlib_regmask_t *r_pmcs; unsigned int i,j,k,l; int ret; unsigned int max_l0, max_l1, max_l2, max_l3; unsigned int assign[PMU_ITA2_NUM_COUNTERS]; unsigned int m, cnt; e = inp->pfp_events; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; cnt = inp->pfp_event_count; r_pmcs = &inp->pfp_unavail_pmcs; if (PFMLIB_DEBUG()) for (m=0; m < cnt; m++) { DPRINT("ev[%d]=%s counters=0x%lx\n", m, itanium2_pe[e[m].event].pme_name, itanium2_pe[e[m].event].pme_counters); } if (cnt > PMU_ITA2_NUM_COUNTERS) return PFMLIB_ERR_TOOMANY; ret = check_cross_groups_and_umasks(inp); if (ret != PFMLIB_SUCCESS) return ret; ret = check_cancel_events(inp); if (ret != PFMLIB_SUCCESS) return ret; max_l0 = PMU_ITA2_FIRST_COUNTER + PMU_ITA2_NUM_COUNTERS; max_l1 = PMU_ITA2_FIRST_COUNTER + PMU_ITA2_NUM_COUNTERS*(cnt>1); max_l2 = PMU_ITA2_FIRST_COUNTER + PMU_ITA2_NUM_COUNTERS*(cnt>2); max_l3 = PMU_ITA2_FIRST_COUNTER + PMU_ITA2_NUM_COUNTERS*(cnt>3); DPRINT("max_l0=%u max_l1=%u max_l2=%u max_l3=%u\n", max_l0, max_l1, max_l2, max_l3); /* * For now, worst case in the loop nest: 4! (factorial) */ for (i=PMU_ITA2_FIRST_COUNTER; i < max_l0; i++) { assign[0] = has_counter(e[0].event,i); if (max_l1 == PMU_ITA2_FIRST_COUNTER && valid_assign(e, assign, r_pmcs, cnt) == PFMLIB_SUCCESS) goto done; for (j=PMU_ITA2_FIRST_COUNTER; j < max_l1; j++) { if (j == i) continue; assign[1] = has_counter(e[1].event,j); if (max_l2 == PMU_ITA2_FIRST_COUNTER && valid_assign(e, assign, r_pmcs, cnt) == PFMLIB_SUCCESS) goto done; for (k=PMU_ITA2_FIRST_COUNTER; k < max_l2; k++) { if(k == i || k == j) continue; assign[2] = has_counter(e[2].event,k); if (max_l3 == PMU_ITA2_FIRST_COUNTER && valid_assign(e, assign, r_pmcs, cnt) == PFMLIB_SUCCESS) goto done; for (l=PMU_ITA2_FIRST_COUNTER; l < max_l3; l++) { if(l == i || l == j || l == k) continue; assign[3] = has_counter(e[3].event,l); if (valid_assign(e, assign, r_pmcs, cnt) == PFMLIB_SUCCESS) goto done; } } } } /* we cannot satisfy the constraints */ return PFMLIB_ERR_NOASSIGN; done: for (j=0; j < cnt ; j++ ) { reg.pmc_val = 0; /* clear all, bits 26-27 must be zero for proper operations */ /* if plm is 0, then assume not specified per-event and use default */ reg.pmc_plm = inp->pfp_events[j].plm ? inp->pfp_events[j].plm : inp->pfp_dfl_plm; reg.pmc_oi = 1; /* overflow interrupt */ reg.pmc_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc_thres = param ? param->pfp_ita2_counters[j].thres: 0; reg.pmc_ism = param ? param->pfp_ita2_counters[j].ism : PFMLIB_ITA2_ISM_BOTH; reg.pmc_umask = is_ear(e[j].event) ? 0x0 : itanium2_pe[e[j].event].pme_umask; reg.pmc_es = itanium2_pe[e[j].event].pme_code; /* * Note that we don't force PMC4.pmc_ena = 1 because the kernel takes care of this for us. * This way we don't have to program something in PMC4 even when we don't use it */ pc[j].reg_num = assign[j]; pc[j].reg_value = reg.pmc_val; pc[j].reg_addr = pc[j].reg_alt_addr = assign[j]; pd[j].reg_num = assign[j]; pd[j].reg_addr = pd[j].reg_alt_addr = assign[j]; __pfm_vbprintf("[PMC%u(pmc%u)=0x%06lx thres=%d es=0x%02x plm=%d umask=0x%x pm=%d ism=0x%x oi=%d] %s\n", assign[j], assign[j], reg.pmc_val, reg.pmc_thres, reg.pmc_es,reg.pmc_plm, reg.pmc_umask, reg.pmc_pm, reg.pmc_ism, reg.pmc_oi, itanium2_pe[e[j].event].pme_name); __pfm_vbprintf("[PMD%u(pmd%u)]\n", pd[j].reg_num, pd[j].reg_num); } /* number of PMC registers programmed */ outp->pfp_pmc_count = cnt; outp->pfp_pmd_count = cnt; return PFMLIB_SUCCESS; } static int pfm_dispatch_iear(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfm_ita2_pmc_reg_t reg; pfmlib_ita2_input_param_t *param = mod_in; pfmlib_reg_t *pc, *pd; pfmlib_ita2_input_param_t fake_param; unsigned int pos1, pos2; unsigned int i, count; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; pos1 = outp->pfp_pmc_count; pos2 = outp->pfp_pmd_count; count = inp->pfp_event_count; for (i=0; i < count; i++) { if (is_iear(inp->pfp_events[i].event)) break; } if (param == NULL || param->pfp_ita2_iear.ear_used == 0) { /* * case 3: no I-EAR event, no (or nothing) in param->pfp_ita2_iear.ear_used */ if (i == count) return PFMLIB_SUCCESS; memset(&fake_param, 0, sizeof(fake_param)); param = &fake_param; /* * case 1: extract all information for event (name) */ pfm_ita2_get_ear_mode(inp->pfp_events[i].event, ¶m->pfp_ita2_iear.ear_mode); param->pfp_ita2_iear.ear_umask = evt_umask(inp->pfp_events[i].event); param->pfp_ita2_iear.ear_ism = PFMLIB_ITA2_ISM_BOTH; /* force both instruction sets */ DPRINT("I-EAR event with no info\n"); } /* * case 2: ear_used=1, event is defined, we use the param info as it is more precise * case 4: ear_used=1, no event (free running I-EAR), use param info */ reg.pmc_val = 0; if (param->pfp_ita2_iear.ear_mode == PFMLIB_ITA2_EAR_TLB_MODE) { /* if plm is 0, then assume not specified per-event and use default */ reg.pmc10_ita2_tlb_reg.iear_plm = param->pfp_ita2_iear.ear_plm ? param->pfp_ita2_iear.ear_plm : inp->pfp_dfl_plm; reg.pmc10_ita2_tlb_reg.iear_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc10_ita2_tlb_reg.iear_ct = 0x0; reg.pmc10_ita2_tlb_reg.iear_umask = param->pfp_ita2_iear.ear_umask; reg.pmc10_ita2_tlb_reg.iear_ism = param->pfp_ita2_iear.ear_ism; } else if (param->pfp_ita2_iear.ear_mode == PFMLIB_ITA2_EAR_CACHE_MODE) { /* if plm is 0, then assume not specified per-event and use default */ reg.pmc10_ita2_cache_reg.iear_plm = param->pfp_ita2_iear.ear_plm ? param->pfp_ita2_iear.ear_plm : inp->pfp_dfl_plm; reg.pmc10_ita2_cache_reg.iear_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc10_ita2_cache_reg.iear_ct = 0x1; reg.pmc10_ita2_cache_reg.iear_umask = param->pfp_ita2_iear.ear_umask; reg.pmc10_ita2_cache_reg.iear_ism = param->pfp_ita2_iear.ear_ism; } else { DPRINT("ALAT mode not supported in I-EAR mode\n"); return PFMLIB_ERR_INVAL; } if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 10)) return PFMLIB_ERR_NOASSIGN; pc[pos1].reg_num = 10; /* PMC10 is I-EAR config register */ pc[pos1].reg_value = reg.pmc_val; pc[pos1].reg_addr = pc[pos1].reg_alt_addr = 10; pos1++; pd[pos2].reg_num = 0; pd[pos2].reg_addr = pd[pos2].reg_alt_addr= 0; pos2++; pd[pos2].reg_num = 1; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 1; pos2++; if (param->pfp_ita2_iear.ear_mode == PFMLIB_ITA2_EAR_TLB_MODE) { __pfm_vbprintf("[PMC10(pmc10)=0x%lx ctb=tlb plm=%d pm=%d ism=0x%x umask=0x%x]\n", reg.pmc_val, reg.pmc10_ita2_tlb_reg.iear_plm, reg.pmc10_ita2_tlb_reg.iear_pm, reg.pmc10_ita2_tlb_reg.iear_ism, reg.pmc10_ita2_tlb_reg.iear_umask); } else { __pfm_vbprintf("[PMC10(pmc10)=0x%lx ctb=cache plm=%d pm=%d ism=0x%x umask=0x%x]\n", reg.pmc_val, reg.pmc10_ita2_cache_reg.iear_plm, reg.pmc10_ita2_cache_reg.iear_pm, reg.pmc10_ita2_cache_reg.iear_ism, reg.pmc10_ita2_cache_reg.iear_umask); } __pfm_vbprintf("[PMD0(pmd0)]\n[PMD1(pmd1)\n"); /* update final number of entries used */ outp->pfp_pmc_count = pos1; outp->pfp_pmd_count = pos2; return PFMLIB_SUCCESS; } static int pfm_dispatch_dear(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfm_ita2_pmc_reg_t reg; pfmlib_ita2_input_param_t *param = mod_in; pfmlib_reg_t *pc, *pd; pfmlib_ita2_input_param_t fake_param; unsigned int pos1, pos2; unsigned int i, count; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; pos1 = outp->pfp_pmc_count; pos2 = outp->pfp_pmd_count; count = inp->pfp_event_count; for (i=0; i < count; i++) { if (is_dear(inp->pfp_events[i].event)) break; } if (param == NULL || param->pfp_ita2_dear.ear_used == 0) { /* * case 3: no D-EAR event, no (or nothing) in param->pfp_ita2_dear.ear_used */ if (i == count) return PFMLIB_SUCCESS; memset(&fake_param, 0, sizeof(fake_param)); param = &fake_param; /* * case 1: extract all information for event (name) */ pfm_ita2_get_ear_mode(inp->pfp_events[i].event, ¶m->pfp_ita2_dear.ear_mode); param->pfp_ita2_dear.ear_umask = evt_umask(inp->pfp_events[i].event); param->pfp_ita2_dear.ear_ism = PFMLIB_ITA2_ISM_BOTH; /* force both instruction sets */ DPRINT("D-EAR event with no info\n"); } /* sanity check on the mode */ if ( param->pfp_ita2_dear.ear_mode != PFMLIB_ITA2_EAR_CACHE_MODE && param->pfp_ita2_dear.ear_mode != PFMLIB_ITA2_EAR_TLB_MODE && param->pfp_ita2_dear.ear_mode != PFMLIB_ITA2_EAR_ALAT_MODE) return PFMLIB_ERR_INVAL; /* * case 2: ear_used=1, event is defined, we use the param info as it is more precise * case 4: ear_used=1, no event (free running D-EAR), use param info */ reg.pmc_val = 0; /* if plm is 0, then assume not specified per-event and use default */ reg.pmc11_ita2_reg.dear_plm = param->pfp_ita2_dear.ear_plm ? param->pfp_ita2_dear.ear_plm : inp->pfp_dfl_plm; reg.pmc11_ita2_reg.dear_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc11_ita2_reg.dear_mode = param->pfp_ita2_dear.ear_mode; reg.pmc11_ita2_reg.dear_umask = param->pfp_ita2_dear.ear_umask; reg.pmc11_ita2_reg.dear_ism = param->pfp_ita2_dear.ear_ism; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 11)) return PFMLIB_ERR_NOASSIGN; pc[pos1].reg_num = 11; /* PMC11 is D-EAR config register */ pc[pos1].reg_value = reg.pmc_val; pc[pos1].reg_addr = pc[pos1].reg_alt_addr = 11; pos1++; pd[pos2].reg_num = 2; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 2; pos2++; pd[pos2].reg_num = 3; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 3; pos2++; pd[pos2].reg_num = 17; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 17; pos2++; __pfm_vbprintf("[PMC11(pmc11)=0x%lx mode=%s plm=%d pm=%d ism=0x%x umask=0x%x]\n", reg.pmc_val, reg.pmc11_ita2_reg.dear_mode == 0 ? "L1D" : (reg.pmc11_ita2_reg.dear_mode == 1 ? "L1DTLB" : "ALAT"), reg.pmc11_ita2_reg.dear_plm, reg.pmc11_ita2_reg.dear_pm, reg.pmc11_ita2_reg.dear_ism, reg.pmc11_ita2_reg.dear_umask); __pfm_vbprintf("[PMD2(pmd2)]\n[PMD3(pmd3)\nPMD17(pmd17)\n"); /* update final number of entries used */ outp->pfp_pmc_count = pos1; outp->pfp_pmd_count = pos2; return PFMLIB_SUCCESS; } static int pfm_dispatch_opcm(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t *mod_in, pfmlib_output_param_t *outp, pfmlib_ita2_output_param_t *mod_out) { pfmlib_ita2_input_param_t *param = mod_in; pfmlib_reg_t *pc = outp->pfp_pmcs; pfm_ita2_pmc_reg_t reg, pmc15; unsigned int i, has_1st_pair, has_2nd_pair, count; unsigned int pos = outp->pfp_pmc_count; if (param == NULL) return PFMLIB_SUCCESS; /* not constrained by PMC8 nor PMC9 */ pmc15.pmc_val = 0xffffffff; /* XXX: use PAL instead. PAL value is 0xfffffff0 */ if (param->pfp_ita2_irange.rr_used && mod_out == NULL) return PFMLIB_ERR_INVAL; if (param->pfp_ita2_pmc8.opcm_used || (param->pfp_ita2_irange.rr_used && mod_out->pfp_ita2_irange.rr_nbr_used!=0) ) { reg.pmc_val = param->pfp_ita2_pmc8.opcm_used ? param->pfp_ita2_pmc8.pmc_val : 0xffffffff3fffffff; if (param->pfp_ita2_irange.rr_used) { reg.pmc8_9_ita2_reg.opcm_ig_ad = 0; reg.pmc8_9_ita2_reg.opcm_inv = param->pfp_ita2_irange.rr_flags & PFMLIB_ITA2_RR_INV ? 1 : 0; } else { /* clear range restriction fields when none is used */ reg.pmc8_9_ita2_reg.opcm_ig_ad = 1; reg.pmc8_9_ita2_reg.opcm_inv = 0; } /* force bit 2 to 1 */ reg.pmc8_9_ita2_reg.opcm_bit2 = 1; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 8)) return PFMLIB_ERR_NOASSIGN; pc[pos].reg_num = 8; pc[pos].reg_value = reg.pmc_val; pc[pos].reg_addr = pc[pos].reg_alt_addr = 8; pos++; /* * will be constrained by PMC8 */ if (param->pfp_ita2_pmc8.opcm_used) { has_1st_pair = has_2nd_pair = 0; count = inp->pfp_event_count; for(i=0; i < count; i++) { if (inp->pfp_events[i].event == PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP0_PMC8) has_1st_pair=1; if (inp->pfp_events[i].event == PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP2_PMC8) has_2nd_pair=1; } if (has_1st_pair || has_2nd_pair == 0) pmc15.pmc15_ita2_reg.opcmc_ibrp0_pmc8 = 0; if (has_2nd_pair || has_1st_pair == 0) pmc15.pmc15_ita2_reg.opcmc_ibrp2_pmc8 = 0; } __pfm_vbprintf("[PMC8(pmc8)=0x%lx m=%d i=%d f=%d b=%d match=0x%x mask=0x%x inv=%d ig_ad=%d]\n", reg.pmc_val, reg.pmc8_9_ita2_reg.opcm_m, reg.pmc8_9_ita2_reg.opcm_i, reg.pmc8_9_ita2_reg.opcm_f, reg.pmc8_9_ita2_reg.opcm_b, reg.pmc8_9_ita2_reg.opcm_match, reg.pmc8_9_ita2_reg.opcm_mask, reg.pmc8_9_ita2_reg.opcm_inv, reg.pmc8_9_ita2_reg.opcm_ig_ad); } if (param->pfp_ita2_pmc9.opcm_used) { /* * PMC9 can only be used to qualify IA64_INST_RETIRED_* events */ if (check_inst_retired_events(inp, NULL) != inp->pfp_event_count) return PFMLIB_ERR_FEATCOMB; reg.pmc_val = param->pfp_ita2_pmc9.pmc_val; /* ig_ad, inv are ignored for PMC9, to avoid confusion we force default values */ reg.pmc8_9_ita2_reg.opcm_ig_ad = 1; reg.pmc8_9_ita2_reg.opcm_inv = 0; /* force bit 2 to 1 */ reg.pmc8_9_ita2_reg.opcm_bit2 = 1; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 9)) return PFMLIB_ERR_NOASSIGN; pc[pos].reg_num = 9; pc[pos].reg_value = reg.pmc_val; pc[pos].reg_addr = pc[pos].reg_alt_addr = 9; pos++; /* * will be constrained by PMC9 */ has_1st_pair = has_2nd_pair = 0; count = inp->pfp_event_count; for(i=0; i < count; i++) { if (inp->pfp_events[i].event == PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP1_PMC9) has_1st_pair=1; if (inp->pfp_events[i].event == PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP3_PMC9) has_2nd_pair=1; } if (has_1st_pair || has_2nd_pair == 0) pmc15.pmc15_ita2_reg.opcmc_ibrp1_pmc9 = 0; if (has_2nd_pair || has_1st_pair == 0) pmc15.pmc15_ita2_reg.opcmc_ibrp3_pmc9 = 0; __pfm_vbprintf("[PMC9(pmc9)=0x%lx m=%d i=%d f=%d b=%d match=0x%x mask=0x%x]\n", reg.pmc_val, reg.pmc8_9_ita2_reg.opcm_m, reg.pmc8_9_ita2_reg.opcm_i, reg.pmc8_9_ita2_reg.opcm_f, reg.pmc8_9_ita2_reg.opcm_b, reg.pmc8_9_ita2_reg.opcm_match, reg.pmc8_9_ita2_reg.opcm_mask); } if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 15)) return PFMLIB_ERR_NOASSIGN; pc[pos].reg_num = 15; pc[pos].reg_value = pmc15.pmc_val; pc[pos].reg_addr = pc[pos].reg_alt_addr = 15; pos++; __pfm_vbprintf("[PMC15(pmc15)=0x%lx ibrp0_pmc8=%d ibrp1_pmc9=%d ibrp2_pmc8=%d ibrp3_pmc9=%d]\n", pmc15.pmc_val, pmc15.pmc15_ita2_reg.opcmc_ibrp0_pmc8, pmc15.pmc15_ita2_reg.opcmc_ibrp1_pmc9, pmc15.pmc15_ita2_reg.opcmc_ibrp2_pmc8, pmc15.pmc15_ita2_reg.opcmc_ibrp3_pmc9); outp->pfp_pmc_count = pos; return PFMLIB_SUCCESS; } static int pfm_dispatch_btb(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfmlib_event_t *e= inp->pfp_events; pfm_ita2_pmc_reg_t reg; pfmlib_ita2_input_param_t *param = mod_in; pfmlib_reg_t *pc, *pd; pfmlib_ita2_input_param_t fake_param; int found_btb = 0, found_bad_dear = 0; int has_btb_param; unsigned int i, pos1, pos2; unsigned int count; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; pos1 = outp->pfp_pmc_count; pos2 = outp->pfp_pmd_count; /* * explicit BTB settings */ has_btb_param = param && param->pfp_ita2_btb.btb_used; reg.pmc_val = 0UL; /* * we need to scan all events looking for DEAR ALAT/TLB due to incompatibility */ count = inp->pfp_event_count; for (i=0; i < count; i++) { if (is_btb(e[i].event)) found_btb = 1; /* * keep track of the first BTB event */ /* look only for DEAR TLB */ if (is_dear(e[i].event) && (is_ear_tlb(e[i].event) || is_ear_alat(e[i].event))) { found_bad_dear = 1; } } DPRINT("found_btb=%d found_bar_dear=%d\n", found_btb, found_bad_dear); /* * did not find D-EAR TLB/ALAT event, need to check param structure */ if (found_bad_dear == 0 && param && param->pfp_ita2_dear.ear_used == 1) { if ( param->pfp_ita2_dear.ear_mode == PFMLIB_ITA2_EAR_TLB_MODE || param->pfp_ita2_dear.ear_mode == PFMLIB_ITA2_EAR_ALAT_MODE) found_bad_dear = 1; } /* * no explicit BTB event and no special case to deal with (cover part of case 3) */ if (found_btb == 0 && has_btb_param == 0 && found_bad_dear == 0) return PFMLIB_SUCCESS; if (has_btb_param == 0) { /* * case 3: no BTB event, btb_used=0 but found_bad_dear=1, need to cleanup PMC12 */ if (found_btb == 0) goto assign_zero; /* * case 1: we have a BTB event but no param, default setting is to capture * all branches. */ memset(&fake_param, 0, sizeof(fake_param)); param = &fake_param; param->pfp_ita2_btb.btb_ds = 0; /* capture branch targets */ param->pfp_ita2_btb.btb_tm = 0x3; /* all branches */ param->pfp_ita2_btb.btb_ptm = 0x3; /* all branches */ param->pfp_ita2_btb.btb_ppm = 0x3; /* all branches */ param->pfp_ita2_btb.btb_brt = 0x0; /* all branches */ DPRINT("BTB event with no info\n"); } /* * case 2: BTB event in the list, param provided * case 4: no BTB event, param provided (free running mode) */ reg.pmc12_ita2_reg.btbc_plm = param->pfp_ita2_btb.btb_plm ? param->pfp_ita2_btb.btb_plm : inp->pfp_dfl_plm; reg.pmc12_ita2_reg.btbc_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc12_ita2_reg.btbc_ds = param->pfp_ita2_btb.btb_ds & 0x1; reg.pmc12_ita2_reg.btbc_tm = param->pfp_ita2_btb.btb_tm & 0x3; reg.pmc12_ita2_reg.btbc_ptm = param->pfp_ita2_btb.btb_ptm & 0x3; reg.pmc12_ita2_reg.btbc_ppm = param->pfp_ita2_btb.btb_ppm & 0x3; reg.pmc12_ita2_reg.btbc_brt = param->pfp_ita2_btb.btb_brt & 0x3; /* * if DEAR-ALAT or DEAR-TLB is set then PMC12 must be set to zero (see documentation p. 87) * * D-EAR ALAT/TLB and BTB cannot be used at the same time. * From documentation: PMC12 must be zero in this mode; else the wrong IP for misses * coming right after a mispredicted branch. * * D-EAR cache is fine. */ assign_zero: if (found_bad_dear && reg.pmc_val != 0UL) return PFMLIB_ERR_EVTINCOMP; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 12)) return PFMLIB_ERR_NOASSIGN; memset(pc+pos1, 0, sizeof(pfmlib_reg_t)); pc[pos1].reg_num = 12; pc[pos1].reg_value = reg.pmc_val; pc[pos1].reg_addr = pc[pos1].reg_alt_addr = 12; pos1++; __pfm_vbprintf("[PMC12(pmc12)=0x%lx plm=%d pm=%d ds=%d tm=%d ptm=%d ppm=%d brt=%d]\n", reg.pmc_val, reg.pmc12_ita2_reg.btbc_plm, reg.pmc12_ita2_reg.btbc_pm, reg.pmc12_ita2_reg.btbc_ds, reg.pmc12_ita2_reg.btbc_tm, reg.pmc12_ita2_reg.btbc_ptm, reg.pmc12_ita2_reg.btbc_ppm, reg.pmc12_ita2_reg.btbc_brt); /* * only add BTB PMD when actually using BTB. * Not needed when dealing with D-EAR TLB and DEAR-ALAT * PMC12 restriction */ if (found_btb || has_btb_param) { /* * PMD16 is included in list of used PMD */ for(i=8; i < 17; i++, pos2++) { pd[pos2].reg_num = i; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = i; __pfm_vbprintf("[PMD%u(pmd%u)]\n", pd[pos2].reg_num, pd[pos2].reg_num); } } /* update final number of entries used */ outp->pfp_pmc_count = pos1; outp->pfp_pmd_count = pos2; return PFMLIB_SUCCESS; } static void do_normal_rr(unsigned long start, unsigned long end, pfmlib_reg_t *br, int nbr, int dir, int *idx, int *reg_idx, int plm) { unsigned long size, l_addr, c; unsigned long l_offs = 0, r_offs = 0; unsigned long l_size, r_size; dbreg_t db; int p2; if (nbr < 1 || end <= start) return; size = end - start; DPRINT("start=0x%016lx end=0x%016lx size=0x%lx bytes (%lu bundles) nbr=%d dir=%d\n", start, end, size, size >> 4, nbr, dir); p2 = pfm_ia64_fls(size); c = ALIGN_DOWN(end, p2); DPRINT("largest power of two possible: 2^%d=0x%lx, crossing=0x%016lx\n", p2, 1UL << p2, c); if ((c - (1UL<= start) { l_addr = c - (1UL << p2); } else { p2--; if ((c + (1UL<>l_offs: 0x%lx\n", l_offs); } } else if (dir == 1 && r_size != 0 && nbr == 1) { p2++; l_addr = start; if (PFMLIB_DEBUG()) { r_offs = l_addr+(1UL<>r_offs: 0x%lx\n", r_offs); } } l_size = l_addr - start; r_size = end - l_addr-(1UL<>largest chunk: 2^%d @0x%016lx-0x%016lx\n", p2, l_addr, l_addr+(1UL<>before: 0x%016lx-0x%016lx\n", start, l_addr); if (r_size && !r_offs) printf(">>after : 0x%016lx-0x%016lx\n", l_addr+(1UL<>1; if (nbr & 0x1) { /* * our simple heuristic is: * we assign the largest number of registers to the largest * of the two chunks */ if (l_size > r_size) { l_nbr++; } else { r_nbr++; } } do_normal_rr(start, l_addr, br, l_nbr, 0, idx, reg_idx, plm); do_normal_rr(l_addr+(1UL<rr_start, in_rr->rr_end, n_pairs, fine_mode ? ", fine_mode" : "", rr_flags & PFMLIB_ITA2_RR_INV ? ", inversed" : ""); __pfm_vbprintf("start offset: -0x%lx end_offset: +0x%lx\n", out_rr->rr_soff, out_rr->rr_eoff); for (j=0; j < n_pairs; j++, base_idx+=2) { d.val = dbr[base_idx+1].reg_value; r_end = dbr[base_idx].reg_value+((~(d.db.db_mask)) & ~(0xffUL << 56)); if (fine_mode) __pfm_vbprintf("brp%u: db%u: 0x%016lx db%u: plm=0x%x mask=0x%016lx\n", dbr[base_idx].reg_num>>1, dbr[base_idx].reg_num, dbr[base_idx].reg_value, dbr[base_idx+1].reg_num, d.db.db_plm, d.db.db_mask); else __pfm_vbprintf("brp%u: db%u: 0x%016lx db%u: plm=0x%x mask=0x%016lx end=0x%016lx\n", dbr[base_idx].reg_num>>1, dbr[base_idx].reg_num, dbr[base_idx].reg_value, dbr[base_idx+1].reg_num, d.db.db_plm, d.db.db_mask, r_end); } } /* * base_idx = base register index to use (for IBRP1, base_idx = 2) */ static int compute_fine_rr(pfmlib_ita2_input_rr_t *irr, int dfl_plm, int n, int *base_idx, pfmlib_ita2_output_rr_t *orr) { int i; pfmlib_reg_t *br; pfmlib_ita2_input_rr_desc_t *in_rr; pfmlib_ita2_output_rr_desc_t *out_rr; unsigned long addr; int reg_idx; dbreg_t db; in_rr = irr->rr_limits; out_rr = orr->rr_infos; br = orr->rr_br+orr->rr_nbr_used; reg_idx = *base_idx; db.val = 0; db.db.db_mask = FINE_MODE_MASK; if (n > 2) return PFMLIB_ERR_IRRTOOMANY; for (i=0; i < n; i++, reg_idx += 2, in_rr++, br+= 4) { /* * setup lower limit pair * * because of the PMU bug, we must align down to the closest bundle-pair * aligned address. 5 => 32-byte aligned address */ addr = has_fine_mode_bug ? ALIGN_DOWN(in_rr->rr_start, 5) : in_rr->rr_start; out_rr->rr_soff = in_rr->rr_start - addr; /* * adjust plm for each range */ db.db.db_plm = in_rr->rr_plm ? in_rr->rr_plm : (unsigned long)dfl_plm; br[0].reg_num = reg_idx; br[0].reg_value = addr; br[0].reg_addr = br[0].reg_alt_addr = reg_idx; br[1].reg_num = reg_idx+1; br[1].reg_value = db.val; br[1].reg_addr = br[1].reg_alt_addr = reg_idx+1; /* * setup upper limit pair * * * In fine mode, the bundle address stored in the upper limit debug * registers is included in the count, so we substract 0x10 to exclude it. * * because of the PMU bug, we align the (corrected) end to the nearest * 32-byte aligned address + 0x10. With this correction and depending * on the correction, we may count one * * */ addr = in_rr->rr_end - 0x10; if (has_fine_mode_bug && (addr & 0x1f) == 0) addr += 0x10; out_rr->rr_eoff = addr - in_rr->rr_end + 0x10; br[2].reg_num = reg_idx+4; br[2].reg_value = addr; br[2].reg_addr = br[2].reg_alt_addr = reg_idx+4; br[3].reg_num = reg_idx+5; br[3].reg_value = db.val; br[3].reg_addr = br[3].reg_alt_addr = reg_idx+5; if (PFMLIB_VERBOSE()) print_one_range(in_rr, out_rr, br, 0, 2, 1, irr->rr_flags); } orr->rr_nbr_used += i<<2; /* update base_idx, for subsequent calls */ *base_idx = reg_idx; return PFMLIB_SUCCESS; } /* * base_idx = base register index to use (for IBRP1, base_idx = 2) */ static int compute_single_rr(pfmlib_ita2_input_rr_t *irr, int dfl_plm, int *base_idx, pfmlib_ita2_output_rr_t *orr) { unsigned long size, end, start; unsigned long p_start, p_end; pfmlib_ita2_input_rr_desc_t *in_rr; pfmlib_ita2_output_rr_desc_t *out_rr; pfmlib_reg_t *br; dbreg_t db; int reg_idx; int l, m; in_rr = irr->rr_limits; out_rr = orr->rr_infos; br = orr->rr_br+orr->rr_nbr_used; start = in_rr->rr_start; end = in_rr->rr_end; size = end - start; reg_idx = *base_idx; l = pfm_ia64_fls(size); m = l; if (size & ((1UL << l)-1)) { if (l>62) { printf("range: [0x%lx-0x%lx] too big\n", start, end); return PFMLIB_ERR_IRRTOOBIG; } m++; } DPRINT("size=%ld, l=%d m=%d, internal: 0x%lx full: 0x%lx\n", size, l, m, 1UL << l, 1UL << m); for (; m < 64; m++) { p_start = ALIGN_DOWN(start, m); p_end = p_start+(1UL<= end) goto found; } return PFMLIB_ERR_IRRINVAL; found: DPRINT("m=%d p_start=0x%lx p_end=0x%lx\n", m, p_start,p_end); /* when the event is not IA64_INST_RETIRED, then we MUST use ibrp0 */ br[0].reg_num = reg_idx; br[0].reg_value = p_start; br[0].reg_addr = br[0].reg_alt_addr = reg_idx; db.val = 0; db.db.db_mask = ~((1UL << m)-1); db.db.db_plm = in_rr->rr_plm ? in_rr->rr_plm : (unsigned long)dfl_plm; br[1].reg_num = reg_idx + 1; br[1].reg_value = db.val; br[1].reg_addr = br[1].reg_alt_addr = reg_idx + 1; out_rr->rr_soff = start - p_start; out_rr->rr_eoff = p_end - end; if (PFMLIB_VERBOSE()) print_one_range(in_rr, out_rr, br, 0, 1, 0, irr->rr_flags); orr->rr_nbr_used += 2; /* update base_idx, for subsequent calls */ *base_idx = reg_idx; return PFMLIB_SUCCESS; } static int compute_normal_rr(pfmlib_ita2_input_rr_t *irr, int dfl_plm, int n, int *base_idx, pfmlib_ita2_output_rr_t *orr) { pfmlib_ita2_input_rr_desc_t *in_rr; pfmlib_ita2_output_rr_desc_t *out_rr; unsigned long r_end; pfmlib_reg_t *br; dbreg_t d; int i, j; int br_index, reg_idx, prev_index; in_rr = irr->rr_limits; out_rr = orr->rr_infos; br = orr->rr_br+orr->rr_nbr_used; reg_idx = *base_idx; br_index = 0; for (i=0; i < n; i++, in_rr++, out_rr++) { /* * running out of registers */ if (br_index == 8) break; prev_index = br_index; do_normal_rr( in_rr->rr_start, in_rr->rr_end, br, 4 - (reg_idx>>1), /* how many pairs available */ 0, &br_index, ®_idx, in_rr->rr_plm ? in_rr->rr_plm : dfl_plm); DPRINT("br_index=%d reg_idx=%d\n", br_index, reg_idx); /* * compute offsets */ out_rr->rr_soff = out_rr->rr_eoff = 0; for(j=prev_index; j < br_index; j+=2) { d.val = br[j+1].reg_value; r_end = br[j].reg_value+((~(d.db.db_mask)+1) & ~(0xffUL << 56)); if (br[j].reg_value <= in_rr->rr_start) out_rr->rr_soff = in_rr->rr_start - br[j].reg_value; if (r_end >= in_rr->rr_end) out_rr->rr_eoff = r_end - in_rr->rr_end; } if (PFMLIB_VERBOSE()) print_one_range(in_rr, out_rr, br, prev_index, (br_index-prev_index)>>1, 0, irr->rr_flags); } /* do not have enough registers to cover all the ranges */ if (br_index == 8 && i < n) return PFMLIB_ERR_TOOMANY; orr->rr_nbr_used += br_index; /* update base_idx, for subsequent calls */ *base_idx = reg_idx; return PFMLIB_SUCCESS; } static int pfm_dispatch_irange(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t *mod_in, pfmlib_output_param_t *outp, pfmlib_ita2_output_param_t *mod_out) { pfm_ita2_pmc_reg_t reg; pfmlib_ita2_input_param_t *param = mod_in; pfmlib_ita2_input_rr_t *irr; pfmlib_ita2_output_rr_t *orr; pfmlib_reg_t *pc = outp->pfp_pmcs; unsigned int i, pos = outp->pfp_pmc_count, count; int ret; unsigned int retired_only, retired_count, fine_mode, prefetch_count; unsigned int n_intervals; int base_idx = 0; unsigned long retired_mask; if (param == NULL) return PFMLIB_SUCCESS; if (param->pfp_ita2_irange.rr_used == 0) return PFMLIB_SUCCESS; if (mod_out == NULL) return PFMLIB_ERR_INVAL; irr = ¶m->pfp_ita2_irange; orr = &mod_out->pfp_ita2_irange; ret = check_intervals(irr, 0, &n_intervals); if (ret != PFMLIB_SUCCESS) return ret; if (n_intervals < 1) return PFMLIB_ERR_IRRINVAL; retired_count = check_inst_retired_events(inp, &retired_mask); retired_only = retired_count == inp->pfp_event_count; prefetch_count = check_prefetch_events(inp); fine_mode = irr->rr_flags & PFMLIB_ITA2_RR_NO_FINE_MODE ? 0 : check_fine_mode_possible(irr, n_intervals); DPRINT("n_intervals=%d retired_only=%d retired_count=%d prefetch_count=%d fine_mode=%d\n", n_intervals, retired_only, retired_count, prefetch_count, fine_mode); /* * On Itanium2, there are more constraints on what can be measured with irange. * * - The fine mode is the best because you directly set the lower and upper limits of * the range. This uses 2 ibr pairs for range (ibrp0/ibrp2 and ibp1/ibrp3). Therefore * at most 2 fine mode ranges can be defined. There is a limit on the size and alignment * of the range to allow fine mode: the range must be less than 4KB in size AND the lower * and upper limits must NOT cross a 4KB page boundary. The fine mode works will all events. * * - if the fine mode fails, then for all events, except IA64_TAGGED_INST_RETIRED_*, only * the first pair of ibr is available: ibrp0. This imposes some severe restrictions on the * size and alignement of the range. It can be bigger than 4KB and must be properly aligned * on its size. The library relaxes these constraints by allowing the covered areas to be * larger than the expected range. It may start before and end after. You can determine how * far off the range is in either direction for each range by looking at the rr_soff (start * offset) and rr_eoff (end offset). * * - if the events include certain prefetch events then only IBRP1 can be used in fine mode * See 10.3.5.1 Exception 1. * * - Finally, when the events are ONLY IA64_TAGGED_INST_RETIRED_* then all IBR pairs can be used * to cover the range giving us more flexibility to approximate the range when it is not * properly aligned on its size (see 10.3.5.2 Exception 2). */ if (fine_mode == 0 && retired_only == 0 && n_intervals > 1) return PFMLIB_ERR_IRRTOOMANY; /* we do not default to non-fine mode to support more ranges */ if (n_intervals > 2 && fine_mode == 1) return PFMLIB_ERR_IRRTOOMANY; if (fine_mode == 0) { if (retired_only) { ret = compute_normal_rr(irr, inp->pfp_dfl_plm, n_intervals, &base_idx, orr); } else { /* unless we have only prefetch and instruction retired events, * we cannot satisfy the request because the other events cannot * be measured on anything but IBRP0. */ if (prefetch_count && (prefetch_count+retired_count) != inp->pfp_event_count) return PFMLIB_ERR_FEATCOMB; base_idx = prefetch_count ? 2 : 0; ret = compute_single_rr(irr, inp->pfp_dfl_plm, &base_idx, orr); } } else { if (prefetch_count && n_intervals != 1) return PFMLIB_ERR_IRRTOOMANY; base_idx = prefetch_count ? 2 : 0; ret = compute_fine_rr(irr, inp->pfp_dfl_plm, n_intervals, &base_idx, orr); } if (ret != PFMLIB_SUCCESS) { return ret == PFMLIB_ERR_TOOMANY ? PFMLIB_ERR_IRRTOOMANY : ret; } reg.pmc_val = 0xdb6; /* default value */ count = orr->rr_nbr_used; for (i=0; i < count; i++) { switch(orr->rr_br[i].reg_num) { case 0: reg.pmc14_ita2_reg.iarc_ibrp0 = 0; break; case 2: reg.pmc14_ita2_reg.iarc_ibrp1 = 0; break; case 4: reg.pmc14_ita2_reg.iarc_ibrp2 = 0; break; case 6: reg.pmc14_ita2_reg.iarc_ibrp3 = 0; break; } } if (retired_only && (param->pfp_ita2_pmc8.opcm_used ||param->pfp_ita2_pmc9.opcm_used)) { /* * PMC8 + IA64_INST_RETIRED only works if irange on IBRP0 and/or IBRP2 * PMC9 + IA64_INST_RETIRED only works if irange on IBRP1 and/or IBRP3 */ count = orr->rr_nbr_used; for (i=0; i < count; i++) { if (orr->rr_br[i].reg_num == 0 && param->pfp_ita2_pmc9.opcm_used) return PFMLIB_ERR_FEATCOMB; if (orr->rr_br[i].reg_num == 2 && param->pfp_ita2_pmc8.opcm_used) return PFMLIB_ERR_FEATCOMB; if (orr->rr_br[i].reg_num == 4 && param->pfp_ita2_pmc9.opcm_used) return PFMLIB_ERR_FEATCOMB; if (orr->rr_br[i].reg_num == 6 && param->pfp_ita2_pmc8.opcm_used) return PFMLIB_ERR_FEATCOMB; } } if (fine_mode) { reg.pmc14_ita2_reg.iarc_fine = 1; } else if (retired_only) { /* * we need to check that the user provided all the events needed to cover * all the ibr pairs used to cover the range */ if ((retired_mask & 0x1) == 0 && reg.pmc14_ita2_reg.iarc_ibrp0 == 0) return PFMLIB_ERR_IRRINVAL; if ((retired_mask & 0x2) == 0 && reg.pmc14_ita2_reg.iarc_ibrp1 == 0) return PFMLIB_ERR_IRRINVAL; if ((retired_mask & 0x4) == 0 && reg.pmc14_ita2_reg.iarc_ibrp2 == 0) return PFMLIB_ERR_IRRINVAL; if ((retired_mask & 0x8) == 0 && reg.pmc14_ita2_reg.iarc_ibrp3 == 0) return PFMLIB_ERR_IRRINVAL; } /* initialize pmc request slot */ memset(pc+pos, 0, sizeof(pfmlib_reg_t)); if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 14)) return PFMLIB_ERR_NOASSIGN; pc[pos].reg_num = 14; pc[pos].reg_value = reg.pmc_val; pc[pos].reg_addr = pc[pos].reg_alt_addr = 14; pos++; __pfm_vbprintf("[PMC14(pmc14)=0x%lx ibrp0=%d ibrp1=%d ibrp2=%d ibrp3=%d fine=%d]\n", reg.pmc_val, reg.pmc14_ita2_reg.iarc_ibrp0, reg.pmc14_ita2_reg.iarc_ibrp1, reg.pmc14_ita2_reg.iarc_ibrp2, reg.pmc14_ita2_reg.iarc_ibrp3, reg.pmc14_ita2_reg.iarc_fine); outp->pfp_pmc_count = pos; return PFMLIB_SUCCESS; } static const unsigned long iod_tab[8]={ /* --- */ 3, /* --D */ 2, /* -O- */ 3, /* should not be used */ /* -OD */ 0, /* =IOD safe because default IBR is harmless */ /* I-- */ 1, /* =IO safe because by defaut OPC is turned off */ /* I-D */ 0, /* =IOD safe because by default opc is turned off */ /* IO- */ 1, /* IOD */ 0 }; /* * IMPORTANT: MUST BE CALLED *AFTER* pfm_dispatch_irange() to make sure we see * the irange programming to adjust pmc13. */ static int pfm_dispatch_drange(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t *mod_in, pfmlib_output_param_t *outp, pfmlib_ita2_output_param_t *mod_out) { pfmlib_ita2_input_param_t *param = mod_in; pfmlib_reg_t *pc = outp->pfp_pmcs; pfmlib_ita2_input_rr_t *irr; pfmlib_ita2_output_rr_t *orr, *orr2; pfm_ita2_pmc_reg_t pmc13; pfm_ita2_pmc_reg_t pmc14; unsigned int i, pos = outp->pfp_pmc_count; int iod_codes[4], dfl_val_pmc8, dfl_val_pmc9; unsigned int n_intervals; int ret; int base_idx = 0; int fine_mode = 0; #define DR_USED 0x1 /* data range is used */ #define OP_USED 0x2 /* opcode matching is used */ #define IR_USED 0x4 /* code range is used */ if (param == NULL) return PFMLIB_SUCCESS; /* * if only pmc8/pmc9 opcode matching is used, we do not need to change * the default value of pmc13 regardless of the events being measured. */ if ( param->pfp_ita2_drange.rr_used == 0 && param->pfp_ita2_irange.rr_used == 0) return PFMLIB_SUCCESS; /* * it seems like the ignored bits need to have special values * otherwise this does not work. */ pmc13.pmc_val = 0x2078fefefefe; /* * initialize iod codes */ iod_codes[0] = iod_codes[1] = iod_codes[2] = iod_codes[3] = 0; /* * setup default iod value, we need to separate because * if drange is used we do not know in advance which DBR will be used * therefore we need to apply dfl_val later */ dfl_val_pmc8 = param->pfp_ita2_pmc8.opcm_used ? OP_USED : 0; dfl_val_pmc9 = param->pfp_ita2_pmc9.opcm_used ? OP_USED : 0; if (param->pfp_ita2_drange.rr_used == 1) { if (mod_out == NULL) return PFMLIB_ERR_INVAL; irr = ¶m->pfp_ita2_drange; orr = &mod_out->pfp_ita2_drange; ret = check_intervals(irr, 1, &n_intervals); if (ret != PFMLIB_SUCCESS) return ret; if (n_intervals < 1) return PFMLIB_ERR_DRRINVAL; ret = compute_normal_rr(irr, inp->pfp_dfl_plm, n_intervals, &base_idx, orr); if (ret != PFMLIB_SUCCESS) { return ret == PFMLIB_ERR_TOOMANY ? PFMLIB_ERR_DRRTOOMANY : ret; } /* * Update iod_codes to reflect the use of the DBR constraint. */ for (i=0; i < orr->rr_nbr_used; i++) { if (orr->rr_br[i].reg_num == 0) iod_codes[0] |= DR_USED | dfl_val_pmc8; if (orr->rr_br[i].reg_num == 2) iod_codes[1] |= DR_USED | dfl_val_pmc9; if (orr->rr_br[i].reg_num == 4) iod_codes[2] |= DR_USED | dfl_val_pmc8; if (orr->rr_br[i].reg_num == 6) iod_codes[3] |= DR_USED | dfl_val_pmc9; } } /* * XXX: assume dispatch_irange executed before calling this function */ if (param->pfp_ita2_irange.rr_used == 1) { orr2 = &mod_out->pfp_ita2_irange; if (mod_out == NULL) return PFMLIB_ERR_INVAL; /* * we need to find out whether or not the irange is using * fine mode. If this is the case, then we only need to * program pmc13 for the ibr pairs which designate the lower * bounds of a range. For instance, if IBRP0/IBRP2 are used, * then we only need to program pmc13.cfg_dbrp0 and pmc13.ena_dbrp0, * the PMU will automatically use IBRP2, even though pmc13.ena_dbrp2=0. */ for(i=0; i <= pos; i++) { if (pc[i].reg_num == 14) { pmc14.pmc_val = pc[i].reg_value; if (pmc14.pmc14_ita2_reg.iarc_fine == 1) fine_mode = 1; break; } } /* * Update to reflect the use of the IBR constraint */ for (i=0; i < orr2->rr_nbr_used; i++) { if (orr2->rr_br[i].reg_num == 0) iod_codes[0] |= IR_USED | dfl_val_pmc8; if (orr2->rr_br[i].reg_num == 2) iod_codes[1] |= IR_USED | dfl_val_pmc9; if (fine_mode == 0 && orr2->rr_br[i].reg_num == 4) iod_codes[2] |= IR_USED | dfl_val_pmc8; if (fine_mode == 0 && orr2->rr_br[i].reg_num == 6) iod_codes[3] |= IR_USED | dfl_val_pmc9; } } if (param->pfp_ita2_irange.rr_used == 0 && param->pfp_ita2_drange.rr_used ==0) { iod_codes[0] = iod_codes[2] = dfl_val_pmc8; iod_codes[1] = iod_codes[3] = dfl_val_pmc9; } /* * update the cfg dbrpX field. If we put a constraint on a cfg dbrp, then * we must enable it in the corresponding ena_dbrpX */ pmc13.pmc13_ita2_reg.darc_ena_dbrp0 = iod_codes[0] ? 1 : 0; pmc13.pmc13_ita2_reg.darc_cfg_dbrp0 = iod_tab[iod_codes[0]]; pmc13.pmc13_ita2_reg.darc_ena_dbrp1 = iod_codes[1] ? 1 : 0; pmc13.pmc13_ita2_reg.darc_cfg_dbrp1 = iod_tab[iod_codes[1]]; pmc13.pmc13_ita2_reg.darc_ena_dbrp2 = iod_codes[2] ? 1 : 0; pmc13.pmc13_ita2_reg.darc_cfg_dbrp2 = iod_tab[iod_codes[2]]; pmc13.pmc13_ita2_reg.darc_ena_dbrp3 = iod_codes[3] ? 1 : 0; pmc13.pmc13_ita2_reg.darc_cfg_dbrp3 = iod_tab[iod_codes[3]]; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 13)) return PFMLIB_ERR_NOASSIGN; pc[pos].reg_num = 13; pc[pos].reg_value = pmc13.pmc_val; pc[pos].reg_addr = pc[pos].reg_alt_addr = 13; pos++; __pfm_vbprintf("[PMC13(pmc13)=0x%lx cfg_dbrp0=%d cfg_dbrp1=%d cfg_dbrp2=%d cfg_dbrp3=%d ena_dbrp0=%d ena_dbrp1=%d ena_dbrp2=%d ena_dbrp3=%d]\n", pmc13.pmc_val, pmc13.pmc13_ita2_reg.darc_cfg_dbrp0, pmc13.pmc13_ita2_reg.darc_cfg_dbrp1, pmc13.pmc13_ita2_reg.darc_cfg_dbrp2, pmc13.pmc13_ita2_reg.darc_cfg_dbrp3, pmc13.pmc13_ita2_reg.darc_ena_dbrp0, pmc13.pmc13_ita2_reg.darc_ena_dbrp1, pmc13.pmc13_ita2_reg.darc_ena_dbrp2, pmc13.pmc13_ita2_reg.darc_ena_dbrp3); outp->pfp_pmc_count = pos; return PFMLIB_SUCCESS; } static int check_qualifier_constraints(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t *mod_in) { pfmlib_ita2_input_param_t *param = mod_in; pfmlib_event_t *e = inp->pfp_events; unsigned int i, count; count = inp->pfp_event_count; for(i=0; i < count; i++) { /* * skip check for counter which requested it. Use at your own risk. * No all counters have necessarily been validated for use with * qualifiers. Typically the event is counted as if no constraint * existed. */ if (param->pfp_ita2_counters[i].flags & PFMLIB_ITA2_FL_EVT_NO_QUALCHECK) continue; if (evt_use_irange(param) && has_iarr(e[i].event) == 0) return PFMLIB_ERR_FEATCOMB; if (evt_use_drange(param) && has_darr(e[i].event) == 0) return PFMLIB_ERR_FEATCOMB; if (evt_use_opcm(param) && has_opcm(e[i].event) == 0) return PFMLIB_ERR_FEATCOMB; } return PFMLIB_SUCCESS; } static int check_range_plm(pfmlib_input_param_t *inp, pfmlib_ita2_input_param_t *mod_in) { pfmlib_ita2_input_param_t *param = mod_in; unsigned int i, count; if (param->pfp_ita2_drange.rr_used == 0 && param->pfp_ita2_irange.rr_used == 0) return PFMLIB_SUCCESS; /* * range restriction applies to all events, therefore we must have a consistent * set of plm and they must match the pfp_dfl_plm which is used to setup the debug * registers */ count = inp->pfp_event_count; for(i=0; i < count; i++) { if (inp->pfp_events[i].plm && inp->pfp_events[i].plm != inp->pfp_dfl_plm) return PFMLIB_ERR_FEATCOMB; } return PFMLIB_SUCCESS; } static int pfm_ita2_dispatch_events(pfmlib_input_param_t *inp, void *model_in, pfmlib_output_param_t *outp, void *model_out) { int ret; pfmlib_ita2_input_param_t *mod_in = (pfmlib_ita2_input_param_t *)model_in; pfmlib_ita2_output_param_t *mod_out = (pfmlib_ita2_output_param_t *)model_out; /* * nothing will come out of this combination */ if (mod_out && mod_in == NULL) return PFMLIB_ERR_INVAL; /* check opcode match, range restriction qualifiers */ if (mod_in && check_qualifier_constraints(inp, mod_in) != PFMLIB_SUCCESS) return PFMLIB_ERR_FEATCOMB; /* check for problems with raneg restriction and per-event plm */ if (mod_in && check_range_plm(inp, mod_in) != PFMLIB_SUCCESS) return PFMLIB_ERR_FEATCOMB; ret = pfm_ita2_dispatch_counters(inp, mod_in, outp); if (ret != PFMLIB_SUCCESS) return ret; /* now check for I-EAR */ ret = pfm_dispatch_iear(inp, mod_in, outp); if (ret != PFMLIB_SUCCESS) return ret; /* now check for D-EAR */ ret = pfm_dispatch_dear(inp, mod_in, outp); if (ret != PFMLIB_SUCCESS) return ret; /* XXX: must be done before dispatch_opcm() and dispatch_drange() */ ret = pfm_dispatch_irange(inp, mod_in, outp, mod_out);; if (ret != PFMLIB_SUCCESS) return ret; ret = pfm_dispatch_drange(inp, mod_in, outp, mod_out);; if (ret != PFMLIB_SUCCESS) return ret; /* now check for Opcode matchers */ ret = pfm_dispatch_opcm(inp, mod_in, outp, mod_out); if (ret != PFMLIB_SUCCESS) return ret; ret = pfm_dispatch_btb(inp, mod_in, outp); return ret; } /* XXX: return value is also error code */ int pfm_ita2_get_event_maxincr(unsigned int i, unsigned int *maxincr) { if (i >= PME_ITA2_EVENT_COUNT || maxincr == NULL) return PFMLIB_ERR_INVAL; *maxincr = itanium2_pe[i].pme_maxincr; return PFMLIB_SUCCESS; } int pfm_ita2_is_ear(unsigned int i) { return i < PME_ITA2_EVENT_COUNT && is_ear(i); } int pfm_ita2_is_dear(unsigned int i) { return i < PME_ITA2_EVENT_COUNT && is_dear(i); } int pfm_ita2_is_dear_tlb(unsigned int i) { return i < PME_ITA2_EVENT_COUNT && is_dear(i) && is_ear_tlb(i); } int pfm_ita2_is_dear_cache(unsigned int i) { return i < PME_ITA2_EVENT_COUNT && is_dear(i) && is_ear_cache(i); } int pfm_ita2_is_dear_alat(unsigned int i) { return i < PME_ITA2_EVENT_COUNT && is_ear_alat(i); } int pfm_ita2_is_iear(unsigned int i) { return i < PME_ITA2_EVENT_COUNT && is_iear(i); } int pfm_ita2_is_iear_tlb(unsigned int i) { return i < PME_ITA2_EVENT_COUNT && is_iear(i) && is_ear_tlb(i); } int pfm_ita2_is_iear_cache(unsigned int i) { return i < PME_ITA2_EVENT_COUNT && is_iear(i) && is_ear_cache(i); } int pfm_ita2_is_btb(unsigned int i) { return i < PME_ITA2_EVENT_COUNT && is_btb(i); } int pfm_ita2_support_iarr(unsigned int i) { return i < PME_ITA2_EVENT_COUNT && has_iarr(i); } int pfm_ita2_support_darr(unsigned int i) { return i < PME_ITA2_EVENT_COUNT && has_darr(i); } int pfm_ita2_support_opcm(unsigned int i) { return i < PME_ITA2_EVENT_COUNT && has_opcm(i); } int pfm_ita2_get_ear_mode(unsigned int i, pfmlib_ita2_ear_mode_t *m) { pfmlib_ita2_ear_mode_t r; if (!is_ear(i) || m == NULL) return PFMLIB_ERR_INVAL; r = PFMLIB_ITA2_EAR_TLB_MODE; if (is_ear_tlb(i)) goto done; r = PFMLIB_ITA2_EAR_CACHE_MODE; if (is_ear_cache(i)) goto done; r = PFMLIB_ITA2_EAR_ALAT_MODE; if (is_ear_alat(i)) goto done; return PFMLIB_ERR_INVAL; done: *m = r; return PFMLIB_SUCCESS; } static int pfm_ita2_get_event_code(unsigned int i, unsigned int cnt, int *code) { if (cnt != PFMLIB_CNT_FIRST && (cnt < 4 || cnt > 7)) return PFMLIB_ERR_INVAL; *code = (int)itanium2_pe[i].pme_code; return PFMLIB_SUCCESS; } /* * This function is accessible directly to the user */ int pfm_ita2_get_event_umask(unsigned int i, unsigned long *umask) { if (i >= PME_ITA2_EVENT_COUNT || umask == NULL) return PFMLIB_ERR_INVAL; *umask = evt_umask(i); return PFMLIB_SUCCESS; } int pfm_ita2_get_event_group(unsigned int i, int *grp) { if (i >= PME_ITA2_EVENT_COUNT || grp == NULL) return PFMLIB_ERR_INVAL; *grp = evt_grp(i); return PFMLIB_SUCCESS; } int pfm_ita2_get_event_set(unsigned int i, int *set) { if (i >= PME_ITA2_EVENT_COUNT || set == NULL) return PFMLIB_ERR_INVAL; *set = evt_set(i) == 0xf ? PFMLIB_ITA2_EVT_NO_SET : evt_set(i); return PFMLIB_SUCCESS; } /* external interface */ int pfm_ita2_irange_is_fine(pfmlib_output_param_t *outp, pfmlib_ita2_output_param_t *mod_out) { pfmlib_ita2_output_param_t *param = mod_out; pfm_ita2_pmc_reg_t reg; unsigned int i, count; /* some sanity checks */ if (outp == NULL || param == NULL) return 0; if (outp->pfp_pmc_count >= PFMLIB_MAX_PMCS) return 0; if (param->pfp_ita2_irange.rr_nbr_used == 0) return 0; /* * we look for pmc14 as it contains the bit indicating if fine mode is used */ count = outp->pfp_pmc_count; for(i=0; i < count; i++) { if (outp->pfp_pmcs[i].reg_num == 14) goto found; } return 0; found: reg.pmc_val = outp->pfp_pmcs[i].reg_value; return reg.pmc14_ita2_reg.iarc_fine ? 1 : 0; } static char * pfm_ita2_get_event_name(unsigned int i) { return itanium2_pe[i].pme_name; } static void pfm_ita2_get_event_counters(unsigned int j, pfmlib_regmask_t *counters) { unsigned int i; unsigned long m; memset(counters, 0, sizeof(*counters)); m =itanium2_pe[j].pme_counters; for(i=0; m ; i++, m>>=1) { if (m & 0x1) pfm_regmask_set(counters, i); } } static void pfm_ita2_get_impl_pmcs(pfmlib_regmask_t *impl_pmcs) { unsigned int i = 0; /* all pmcs are contiguous */ for(i=0; i < PMU_ITA2_NUM_PMCS; i++) pfm_regmask_set(impl_pmcs, i); } static void pfm_ita2_get_impl_pmds(pfmlib_regmask_t *impl_pmds) { unsigned int i = 0; /* all pmds are contiguous */ for(i=0; i < PMU_ITA2_NUM_PMDS; i++) pfm_regmask_set(impl_pmds, i); } static void pfm_ita2_get_impl_counters(pfmlib_regmask_t *impl_counters) { unsigned int i = 0; /* counting pmds are contiguous */ for(i=4; i < 8; i++) pfm_regmask_set(impl_counters, i); } static void pfm_ita2_get_hw_counter_width(unsigned int *width) { *width = PMU_ITA2_COUNTER_WIDTH; } static int pfm_ita2_get_event_description(unsigned int ev, char **str) { char *s; s = itanium2_pe[ev].pme_desc; if (s) { *str = strdup(s); } else { *str = NULL; } return PFMLIB_SUCCESS; } static int pfm_ita2_get_cycle_event(pfmlib_event_t *e) { e->event = PME_ITA2_CPU_CYCLES; return PFMLIB_SUCCESS; } static int pfm_ita2_get_inst_retired(pfmlib_event_t *e) { e->event = PME_ITA2_IA64_INST_RETIRED; return PFMLIB_SUCCESS; } pfm_pmu_support_t itanium2_support={ .pmu_name = "itanium2", .pmu_type = PFMLIB_ITANIUM2_PMU, .pme_count = PME_ITA2_EVENT_COUNT, .pmc_count = PMU_ITA2_NUM_PMCS, .pmd_count = PMU_ITA2_NUM_PMDS, .num_cnt = PMU_ITA2_NUM_COUNTERS, .get_event_code = pfm_ita2_get_event_code, .get_event_name = pfm_ita2_get_event_name, .get_event_counters = pfm_ita2_get_event_counters, .dispatch_events = pfm_ita2_dispatch_events, .pmu_detect = pfm_ita2_detect, .get_impl_pmcs = pfm_ita2_get_impl_pmcs, .get_impl_pmds = pfm_ita2_get_impl_pmds, .get_impl_counters = pfm_ita2_get_impl_counters, .get_hw_counter_width = pfm_ita2_get_hw_counter_width, .get_event_desc = pfm_ita2_get_event_description, .get_cycle_event = pfm_ita2_get_cycle_event, .get_inst_retired_event = pfm_ita2_get_inst_retired }; papi-5.5.1/src/libpfm-3.y/lib/pfmlib_itanium_priv.h0000644000307100002310000000714713013651450022111 0ustar yarkhangraduate/* * Copyright (c) 2001-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #ifndef __PFMLIB_ITANIUM_PRIV_H__ #define __PFMLIB_ITANIUM_PRIV_H__ /* * Itanium encoding structure * (code must be first 8 bits) */ typedef struct { unsigned long pme_code:8; /* major event code */ unsigned long pme_ear:1; /* is EAR event */ unsigned long pme_dear:1; /* 1=Data 0=Instr */ unsigned long pme_tlb:1; /* 1=TLB 0=Cache */ unsigned long pme_btb:1; /* 1=BTB */ unsigned long pme_ig1:4; /* ignored */ unsigned long pme_umask:16; /* unit mask*/ unsigned long pme_ig:32; /* ignored */ } pme_ita_entry_code_t; #define PME_UMASK_NONE 0x0 typedef union { unsigned long pme_vcode; pme_ita_entry_code_t pme_ita_code; /* must not be larger than vcode */ } pme_ita_code_t; typedef union { unsigned long qual; /* generic qualifier */ struct { unsigned long pme_iar:1; /* instruction address range supported */ unsigned long pme_opm:1; /* opcode match supported */ unsigned long pme_dar:1; /* data address range supported */ unsigned long pme_reserved:61; /* not used */ } pme_qual; } pme_ita_qualifiers_t; typedef struct { char *pme_name; pme_ita_code_t pme_entry_code; unsigned long pme_counters; /* supported counters */ unsigned int pme_maxincr; pme_ita_qualifiers_t pme_qualifiers; char *pme_desc; } pme_ita_entry_t; /* * We embed the umask value into the event code. Because it really is * like a subevent. * pme_code: * - lower 16 bits: major event code * - upper 16 bits: unit mask */ #define pme_code pme_entry_code.pme_ita_code.pme_code #define pme_ear pme_entry_code.pme_ita_code.pme_ear #define pme_dear pme_entry_code.pme_ita_code.pme_dear #define pme_tlb pme_entry_code.pme_ita_code.pme_tlb #define pme_btb pme_entry_code.pme_ita_code.pme_btb #define pme_umask pme_entry_code.pme_ita_code.pme_umask #define pme_used pme_qualifiers.pme_qual_struct.pme_used #define event_is_ear(e) ((e)->pme_ear == 1) #define event_is_iear(e) ((e)->pme_ear == 1 && (e)->pme_dear==0) #define event_is_dear(e) ((e)->pme_ear == 1 && (e)->pme_dear==1) #define event_is_tlb_ear(e) ((e)->pme_ear == 1 && (e)->pme_tlb==1) #define event_is_btb(e) ((e)->pme_btb) #define event_opcm_ok(e) ((e)->pme_qualifiers.pme_qual.pme_opm==1) #define event_iarr_ok(e) ((e)->pme_qualifiers.pme_qual.pme_iar==1) #define event_darr_ok(e) ((e)->pme_qualifiers.pme_qual.pme_dar==1) #endif /* __PFMLIB_ITANIUM_PRIV_H__ */ papi-5.5.1/src/libpfm-3.y/lib/coreduo_events.h0000644000307100002310000006412513013651450021075 0ustar yarkhangraduate/* * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * Contributions by James Ralph * * Based on: * Copyright (c) 2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #define INTEL_COREDUO_MESI_UMASKS \ { .pme_uname = "MESI",\ .pme_udesc = "Any cacheline access",\ .pme_ucode = 0xf\ },\ { .pme_uname = "I_STATE",\ .pme_udesc = "Invalid cacheline",\ .pme_ucode = 0x1\ },\ { .pme_uname = "S_STATE",\ .pme_udesc = "Shared cacheline",\ .pme_ucode = 0x2\ },\ { .pme_uname = "E_STATE",\ .pme_udesc = "Exclusive cacheline",\ .pme_ucode = 0x4\ },\ { .pme_uname = "M_STATE",\ .pme_udesc = "Modified cacheline",\ .pme_ucode = 0x8\ } #define INTEL_COREDUO_SPECIFICITY_UMASKS \ { .pme_uname = "SELF",\ .pme_udesc = "This core",\ .pme_ucode = 0x40\ },\ { .pme_uname = "BOTH_CORES",\ .pme_udesc = "Both cores",\ .pme_ucode = 0xc0\ } #define INTEL_COREDUO_HW_PREFETCH_UMASKS \ { .pme_uname = "ANY",\ .pme_udesc = "All inclusive",\ .pme_ucode = 0x30\ },\ { .pme_uname = "PREFETCH",\ .pme_udesc = "Hardware prefetch only",\ .pme_ucode = 0x10\ } #define INTEL_COREDUO_AGENT_UMASKS \ { .pme_uname = "THIS_AGENT",\ .pme_udesc = "This agent",\ .pme_ucode = 0x00\ },\ { .pme_uname = "ALL_AGENTS",\ .pme_udesc = "Any agent on the bus",\ .pme_ucode = 0x20\ } static pme_coreduo_entry_t coreduo_pe[]={ /* * BEGIN architectural perfmon events */ /* 0 */{ .pme_name = "UNHALTED_CORE_CYCLES", .pme_code = 0x003c, .pme_desc = "Unhalted core cycles", }, /* 1 */{ .pme_name = "UNHALTED_REFERENCE_CYCLES", .pme_code = 0x013c, .pme_desc = "Unhalted reference cycles. Measures bus cycles" }, /* 2 */{ .pme_name = "INSTRUCTIONS_RETIRED", .pme_code = 0xc0, .pme_desc = "Instructions retired" }, /* 3 */{ .pme_name = "LAST_LEVEL_CACHE_REFERENCES", .pme_code = 0x4f2e, .pme_desc = "Last level of cache references" }, /* 4 */{ .pme_name = "LAST_LEVEL_CACHE_MISSES", .pme_code = 0x412e, .pme_desc = "Last level of cache misses", }, /* 5 */{ .pme_name = "BRANCH_INSTRUCTIONS_RETIRED", .pme_code = 0xc4, .pme_desc = "Branch instructions retired" }, /* 6 */{ .pme_name = "MISPREDICTED_BRANCH_RETIRED", .pme_code = 0xc5, .pme_desc = "Mispredicted branch instruction retired" }, /* * BEGIN non architectural events */ { .pme_code = 0x3, .pme_name = "LD_BLOCKS", .pme_desc = "Load operations delayed due to store buffer blocks. The preceding store may be blocked due to unknown address, unknown data, or conflict due to partial overlap between the load and store.", }, { .pme_code = 0x4, .pme_name = "SD_DRAINS", .pme_desc = "Cycles while draining store buffers", }, { .pme_code = 0x5, .pme_name = "MISALIGN_MEM_REF", .pme_desc = "Misaligned data memory references (MOB splits of loads and stores).", }, { .pme_code = 0x6, .pme_name = "SEG_REG_LOADS", .pme_desc = "Segment register loads", }, { .pme_code = 0x7, .pme_name = "SSE_PREFETCH", .pme_flags = 0, .pme_desc = "Streaming SIMD Extensions (SSE) Prefetch instructions executed", .pme_umasks = { { .pme_uname = "NTA", .pme_udesc = "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed", .pme_ucode = 0x0 }, { .pme_uname = "T1", .pme_udesc = "SSE software prefetch instruction PREFE0xTCT1 retired", .pme_ucode = 0x01 }, { .pme_uname = "T2", .pme_udesc = "SSE software prefetch instruction PREFE0xTCT2 retired", .pme_ucode = 0x02 }, }, .pme_numasks = 3 }, { .pme_name = "SSE_NTSTORES_RET", .pme_desc = "SSE streaming store instruction retired", .pme_code = 0x0307 }, { .pme_code = 0x10, .pme_name = "FP_COMPS_OP_EXE", .pme_desc = "FP computational Instruction executed. FADD, FSUB, FCOM, FMULs, MUL, IMUL, FDIVs, DIV, IDIV, FPREMs, FSQRT are included; but exclude FADD or FMUL used in the middle of a transcendental instruction.", }, { .pme_code = 0x11, .pme_name = "FP_ASSIST", .pme_desc = "FP exceptions experienced microcode assists", .pme_flags = PFMLIB_COREDUO_PMC1 }, { .pme_code = 0x12, .pme_name = "MUL", .pme_desc = "Multiply operations (a speculative count, including FP and integer multiplies).", .pme_flags = PFMLIB_COREDUO_PMC1 }, { .pme_code = 0x13, .pme_name = "DIV", .pme_desc = "Divide operations (a speculative count, including FP and integer multiplies). ", .pme_flags = PFMLIB_COREDUO_PMC1 }, { .pme_code = 0x14, .pme_name = "CYCLES_DIV_BUSY", .pme_desc = "Cycles the divider is busy ", .pme_flags = PFMLIB_COREDUO_PMC0 }, { .pme_code = 0x21, .pme_name = "L2_ADS", .pme_flags = PFMLIB_COREDUO_CSPEC, .pme_desc = "L2 Address strobes ", .pme_umasks = { INTEL_COREDUO_SPECIFICITY_UMASKS }, .pme_numasks = 2 }, { .pme_code = 0x22, .pme_name = "DBUS_BUSY", .pme_flags = PFMLIB_COREDUO_CSPEC, .pme_desc = "Core cycle during which data buswas busy (increments by 4)", .pme_umasks = { INTEL_COREDUO_SPECIFICITY_UMASKS }, .pme_numasks = 2 }, { .pme_code = 0x23, .pme_name = "DBUS_BUSY_RD", .pme_flags = PFMLIB_COREDUO_CSPEC, .pme_desc = "Cycles data bus is busy transferring data to a core (increments by 4) ", .pme_umasks = { INTEL_COREDUO_SPECIFICITY_UMASKS }, .pme_numasks = 2 }, { .pme_code = 0x24, .pme_name = "L2_LINES_IN", .pme_flags = PFMLIB_COREDUO_CSPEC, .pme_desc = "L2 cache lines allocated", .pme_umasks = { INTEL_COREDUO_SPECIFICITY_UMASKS, INTEL_COREDUO_HW_PREFETCH_UMASKS }, .pme_numasks = 4 }, { .pme_code = 0x25, .pme_name = "L2_M_LINES_IN", .pme_flags = PFMLIB_COREDUO_CSPEC, .pme_desc = "L2 Modified-state cache lines allocated", .pme_umasks = { INTEL_COREDUO_SPECIFICITY_UMASKS }, .pme_numasks = 2 }, { .pme_code = 0x26, .pme_name = "L2_LINES_OUT", .pme_flags = PFMLIB_COREDUO_CSPEC, .pme_desc = "L2 cache lines evicted ", .pme_umasks = { INTEL_COREDUO_SPECIFICITY_UMASKS, INTEL_COREDUO_HW_PREFETCH_UMASKS }, .pme_numasks = 4 }, { .pme_code = 0x27, .pme_name = "L2_M_LINES_OUT", .pme_flags = PFMLIB_COREDUO_CSPEC, .pme_desc = "L2 Modified-state cache lines evicted ", .pme_umasks = { INTEL_COREDUO_SPECIFICITY_UMASKS, INTEL_COREDUO_HW_PREFETCH_UMASKS }, .pme_numasks = 4 }, { .pme_code = 0x28, .pme_name = "L2_IFETCH", .pme_flags = PFMLIB_COREDUO_CSPEC|PFMLIB_COREDUO_MESI, .pme_desc = "L2 instruction fetches from nstruction fetch unit (includes speculative fetches) ", .pme_umasks = { INTEL_COREDUO_MESI_UMASKS, INTEL_COREDUO_SPECIFICITY_UMASKS }, .pme_numasks = 7 }, { .pme_code = 0x29, .pme_name = "L2_LD", .pme_desc = "L2 cache reads (includes speculation) ", .pme_flags = PFMLIB_COREDUO_CSPEC|PFMLIB_COREDUO_MESI, .pme_umasks = { INTEL_COREDUO_MESI_UMASKS, INTEL_COREDUO_SPECIFICITY_UMASKS }, .pme_numasks = 7 }, { .pme_code = 0x2A, .pme_name = "L2_ST", .pme_flags = PFMLIB_COREDUO_CSPEC|PFMLIB_COREDUO_MESI, .pme_desc = "L2 cache writes (includes speculation)", .pme_umasks = { INTEL_COREDUO_MESI_UMASKS, INTEL_COREDUO_SPECIFICITY_UMASKS }, .pme_numasks = 7 }, { .pme_code = 0x2E, .pme_name = "L2_RQSTS", .pme_flags = PFMLIB_COREDUO_CSPEC|PFMLIB_COREDUO_MESI, .pme_desc = "L2 cache reference requests ", .pme_umasks = { INTEL_COREDUO_MESI_UMASKS, INTEL_COREDUO_SPECIFICITY_UMASKS, INTEL_COREDUO_HW_PREFETCH_UMASKS }, .pme_numasks = 9 }, { .pme_code = 0x30, .pme_name = "L2_REJECT_CYCLES", .pme_flags = PFMLIB_COREDUO_CSPEC|PFMLIB_COREDUO_MESI, .pme_desc = "Cycles L2 is busy and rejecting new requests.", .pme_umasks = { INTEL_COREDUO_MESI_UMASKS, INTEL_COREDUO_SPECIFICITY_UMASKS, INTEL_COREDUO_HW_PREFETCH_UMASKS }, .pme_numasks = 9 }, { .pme_code = 0x32, .pme_name = "L2_NO_REQUEST_CYCLES", .pme_flags = PFMLIB_COREDUO_CSPEC|PFMLIB_COREDUO_MESI, .pme_desc = "Cycles there is no request to access L2.", .pme_umasks = { INTEL_COREDUO_MESI_UMASKS, INTEL_COREDUO_SPECIFICITY_UMASKS, INTEL_COREDUO_HW_PREFETCH_UMASKS }, .pme_numasks = 9 }, { .pme_code = 0x3A, .pme_name = "EST_TRANS_ALL", .pme_desc = "Any Intel Enhanced SpeedStep(R) Technology transitions", }, { .pme_code = 0x103A, .pme_name = "EST_TRANS_ALL", .pme_desc = "Intel Enhanced SpeedStep Technology frequency transitions", }, { .pme_code = 0x3B, .pme_name = "THERMAL_TRIP", .pme_desc = "Duration in a thermal trip based on the current core clock ", .pme_umasks = { { .pme_uname = "CYCLES", .pme_udesc = "Duration in a thermal trip based on the current core clock", .pme_ucode = 0xC0 }, { .pme_uname = "TRIPS", .pme_udesc = "Number of thermal trips", .pme_ucode = 0xC0 | (1<<10) /* Edge detect pin (Figure 18-13) */ } }, .pme_numasks = 2 }, { .pme_name = "CPU_CLK_UNHALTED", .pme_code = 0x3c, .pme_desc = "Core cycles when core is not halted", .pme_umasks = { { .pme_uname = "NONHLT_REF_CYCLES", .pme_udesc = "Non-halted bus cycles", .pme_ucode = 0x01 }, { .pme_uname = "SERIAL_EXECUTION_CYCLES", .pme_udesc ="Non-halted bus cycles of this core executing code while the other core is halted", .pme_ucode = 0x02 } }, .pme_numasks = 2 }, { .pme_code = 0x40, .pme_name = "DCACHE_CACHE_LD", .pme_desc = "L1 cacheable data read operations", .pme_umasks = { INTEL_COREDUO_MESI_UMASKS }, .pme_numasks = 5 }, { .pme_code = 0x41, .pme_name = "DCACHE_CACHE_ST", .pme_desc = "L1 cacheable data write operations", .pme_umasks = { INTEL_COREDUO_MESI_UMASKS }, .pme_numasks = 5 }, { .pme_code = 0x42, .pme_name = "DCACHE_CACHE_LOCK", .pme_desc = "L1 cacheable lock read operations to invalid state", .pme_umasks = { INTEL_COREDUO_MESI_UMASKS }, .pme_numasks = 5 }, { .pme_code = 0x0143, .pme_name = "DATA_MEM_REF", .pme_desc = "L1 data read and writes of cacheable and non-cacheable types", }, { .pme_code = 0x0244, .pme_name = "DATA_MEM_CACHE_REF", .pme_desc = "L1 data cacheable read and write operations.", }, { .pme_code = 0x0f45, .pme_name = "DCACHE_REPL", .pme_desc = "L1 data cache line replacements", }, { .pme_code = 0x46, .pme_name = "DCACHE_M_REPL", .pme_desc = "L1 data M-state cache line allocated", }, { .pme_code = 0x47, .pme_name = "DCACHE_M_EVICT", .pme_desc = "L1 data M-state cache line evicted", }, { .pme_code = 0x48, .pme_name = "DCACHE_PEND_MISS", .pme_desc = "Weighted cycles of L1 miss outstanding", }, { .pme_code = 0x49, .pme_name = "DTLB_MISS", .pme_desc = "Data references that missed TLB", }, { .pme_code = 0x4B, .pme_name = "SSE_PRE_MISS", .pme_flags = 0, .pme_desc = "Streaming SIMD Extensions (SSE) instructions missing all cache levels", .pme_umasks = { { .pme_uname = "NTA_MISS", .pme_udesc = "PREFETCHNTA missed all caches", .pme_ucode = 0x00 }, { .pme_uname = "T1_MISS", .pme_udesc = "PREFETCHT1 missed all caches", .pme_ucode = 0x01 }, { .pme_uname = "T2_MISS", .pme_udesc = "PREFETCHT2 missed all caches", .pme_ucode = 0x02 }, { .pme_uname = "STORES_MISS", .pme_udesc = "SSE streaming store instruction missed all caches", .pme_ucode = 0x03 } }, .pme_numasks = 4 }, { .pme_code = 0x4F, .pme_name = "L1_PREF_REQ", .pme_desc = "L1 prefetch requests due to DCU cache misses", }, { .pme_code = 0x60, .pme_name = "BUS_REQ_OUTSTANDING", .pme_flags = PFMLIB_COREDUO_CSPEC, .pme_desc = "Weighted cycles of cacheable bus data read requests. This event counts full-line read request from DCU or HW prefetcher, but not RFO, write, instruction fetches, or others.", .pme_umasks = { INTEL_COREDUO_SPECIFICITY_UMASKS, INTEL_COREDUO_AGENT_UMASKS }, .pme_numasks = 4 /* TODO: umasks bit 12 to include HWP or exclude HWP separately. */, }, { .pme_code = 0x61, .pme_name = "BUS_BNR_CLOCKS", .pme_desc = "External bus cycles while BNR asserted", }, { .pme_code = 0x62, .pme_name = "BUS_DRDY_CLOCKS", .pme_desc = "External bus cycles while DRDY asserted", .pme_umasks = { INTEL_COREDUO_AGENT_UMASKS }, .pme_numasks = 2 }, { .pme_code = 0x63, .pme_name = "BUS_LOCKS_CLOCKS", .pme_flags = PFMLIB_COREDUO_CSPEC, .pme_desc = "External bus cycles while bus lock signal asserted", .pme_umasks = { INTEL_COREDUO_SPECIFICITY_UMASKS, }, .pme_numasks = 2 }, { .pme_code = 0x4064, .pme_name = "BUS_DATA_RCV", .pme_desc = "External bus cycles while bus lock signal asserted", }, { .pme_code = 0x65, .pme_name = "BUS_TRANS_BRD", .pme_flags = PFMLIB_COREDUO_CSPEC, .pme_desc = "Burst read bus transactions (data or code)", .pme_umasks = { INTEL_COREDUO_SPECIFICITY_UMASKS, }, .pme_numasks = 2 }, { .pme_code = 0x66, .pme_name = "BUS_TRANS_RFO", .pme_flags = PFMLIB_COREDUO_CSPEC, .pme_desc = "Completed read for ownership ", .pme_umasks = { INTEL_COREDUO_SPECIFICITY_UMASKS, INTEL_COREDUO_AGENT_UMASKS }, .pme_numasks = 4 }, { .pme_code = 0x68, .pme_name = "BUS_TRANS_IFETCH", .pme_flags = PFMLIB_COREDUO_CSPEC, .pme_desc = "Completed instruction fetch transactions", .pme_umasks = { INTEL_COREDUO_SPECIFICITY_UMASKS, INTEL_COREDUO_AGENT_UMASKS }, .pme_numasks = 4 }, { .pme_code = 0x69, .pme_flags = PFMLIB_COREDUO_CSPEC, .pme_name = "BUS_TRANS_INVAL", .pme_desc = "Completed invalidate transactions", .pme_umasks = { INTEL_COREDUO_SPECIFICITY_UMASKS, INTEL_COREDUO_AGENT_UMASKS }, .pme_numasks = 4 }, { .pme_code = 0x6A, .pme_name = "BUS_TRANS_PWR", .pme_flags = PFMLIB_COREDUO_CSPEC, .pme_desc = "Completed partial write transactions", .pme_umasks = { INTEL_COREDUO_SPECIFICITY_UMASKS, INTEL_COREDUO_AGENT_UMASKS }, .pme_numasks = 4 }, { .pme_code = 0x6B, .pme_name = "BUS_TRANS_P", .pme_flags = PFMLIB_COREDUO_CSPEC, .pme_desc = "Completed partial transactions (include partial read + partial write + line write)", .pme_umasks = { INTEL_COREDUO_SPECIFICITY_UMASKS, INTEL_COREDUO_AGENT_UMASKS }, .pme_numasks = 4 }, { .pme_code = 0x6C, .pme_name = "BUS_TRANS_IO", .pme_flags = PFMLIB_COREDUO_CSPEC, .pme_desc = "Completed I/O transactions (read and write)", .pme_umasks = { INTEL_COREDUO_SPECIFICITY_UMASKS, INTEL_COREDUO_AGENT_UMASKS }, .pme_numasks = 4 }, { .pme_code = 0x206D, .pme_name = "BUS_TRANS_DEF", .pme_flags = PFMLIB_COREDUO_CSPEC, .pme_desc = "Completed defer transactions ", .pme_umasks = { INTEL_COREDUO_SPECIFICITY_UMASKS }, .pme_numasks = 2 }, { .pme_code = 0xc067, .pme_name = "BUS_TRANS_WB", .pme_desc = "Completed writeback transactions from DCU (does not include L2 writebacks)", .pme_umasks = { INTEL_COREDUO_AGENT_UMASKS }, .pme_numasks = 2 }, { .pme_code = 0xc06E, .pme_name = "BUS_TRANS_BURST", .pme_desc = "Completed burst transactions (full line transactions include reads, write, RFO, and writebacks) ", /* TODO .pme_umasks = 0xC0, */ .pme_umasks = { INTEL_COREDUO_AGENT_UMASKS }, .pme_numasks = 2 }, { .pme_code = 0xc06F, .pme_name = "BUS_TRANS_MEM", .pme_flags = PFMLIB_COREDUO_CSPEC, .pme_desc = "Completed memory transactions. This includes Bus_Trans_Burst + Bus_Trans_P + Bus_Trans_Inval.", .pme_umasks = { INTEL_COREDUO_AGENT_UMASKS }, .pme_numasks = 2 }, { .pme_code = 0xc070, .pme_name = "BUS_TRANS_ANY", .pme_desc = "Any completed bus transactions", .pme_umasks = { INTEL_COREDUO_AGENT_UMASKS }, .pme_numasks = 2 }, { .pme_code = 0x77, .pme_name = "BUS_SNOOPS", .pme_desc = "External bus cycles while bus lock signal asserted", .pme_flags = PFMLIB_COREDUO_MESI, .pme_umasks = { INTEL_COREDUO_MESI_UMASKS, INTEL_COREDUO_AGENT_UMASKS }, .pme_numasks = 7 }, { .pme_code = 0x0178, .pme_name = "DCU_SNOOP_TO_SHARE", .pme_desc = "DCU snoops to share-state L1 cache line due to L1 misses ", .pme_flags = PFMLIB_COREDUO_CSPEC, .pme_umasks = { INTEL_COREDUO_SPECIFICITY_UMASKS }, .pme_numasks = 2 }, { .pme_code = 0x7D, .pme_name = "BUS_NOT_IN_USE", .pme_flags = PFMLIB_COREDUO_CSPEC, .pme_desc = "Number of cycles there is no transaction from the core", .pme_umasks = { INTEL_COREDUO_SPECIFICITY_UMASKS }, .pme_numasks = 2 }, { .pme_code = 0x7E, .pme_name = "BUS_SNOOP_STALL", .pme_desc = "Number of bus cycles while bus snoop is stalled" }, { .pme_code = 0x80, .pme_name = "ICACHE_READS", .pme_desc = "Number of instruction fetches from ICache, streaming buffers (both cacheable and uncacheable fetches)" }, { .pme_code = 0x81, .pme_name = "ICACHE_MISSES", .pme_desc = "Number of instruction fetch misses from ICache, streaming buffers." }, { .pme_code = 0x85, .pme_name = "ITLB_MISSES", .pme_desc = "Number of iITLB misses" }, { .pme_code = 0x86, .pme_name = "IFU_MEM_STALL", .pme_desc = "Cycles IFU is stalled while waiting for data from memory" }, { .pme_code = 0x87, .pme_name = "ILD_STALL", .pme_desc = "Number of instruction length decoder stalls (Counts number of LCP stalls)" }, { .pme_code = 0x88, .pme_name = "BR_INST_EXEC", .pme_desc = "Branch instruction executed (includes speculation)." }, { .pme_code = 0x89, .pme_name = "BR_MISSP_EXEC", .pme_desc = "Branch instructions executed and mispredicted at execution (includes branches that do not have prediction or mispredicted)" }, { .pme_code = 0x8A, .pme_name = "BR_BAC_MISSP_EXEC", .pme_desc = "Branch instructions executed that were mispredicted at front end" }, { .pme_code = 0x8B, .pme_name = "BR_CND_EXEC", .pme_desc = "Conditional branch instructions executed" }, { .pme_code = 0x8C, .pme_name = "BR_CND_MISSP_EXEC", .pme_desc = "Conditional branch instructions executed that were mispredicted" }, { .pme_code = 0x8D, .pme_name = "BR_IND_EXEC", .pme_desc = "Indirect branch instructions executed" }, { .pme_code = 0x8E, .pme_name = "BR_IND_MISSP_EXEC", .pme_desc = "Indirect branch instructions executed that were mispredicted" }, { .pme_code = 0x8F, .pme_name = "BR_RET_EXEC", .pme_desc = "Return branch instructions executed" }, { .pme_code = 0x90, .pme_name = "BR_RET_MISSP_EXEC", .pme_desc = "Return branch instructions executed that were mispredicted" }, { .pme_code = 0x91, .pme_name = "BR_RET_BAC_MISSP_EXEC", .pme_desc = "Return branch instructions executed that were mispredicted at the front end" }, { .pme_code = 0x92, .pme_name = "BR_CALL_EXEC", .pme_desc = "Return call instructions executed" }, { .pme_code = 0x93, .pme_name = "BR_CALL_MISSP_EXEC", .pme_desc = "Return call instructions executed that were mispredicted" }, { .pme_code = 0x94, .pme_name = "BR_IND_CALL_EXEC", .pme_desc = "Indirect call branch instructions executed" }, { .pme_code = 0xA2, .pme_name = "RESOURCE_STALL", .pme_desc = "Cycles while there is a resource related stall (renaming, buffer entries) as seen by allocator" }, { .pme_code = 0xB0, .pme_name = "MMX_INSTR_EXEC", .pme_desc = "Number of MMX instructions executed (does not include MOVQ and MOVD stores)" }, { .pme_code = 0xB1, .pme_name = "SIMD_INT_SAT_EXEC", .pme_desc = "Number of SIMD Integer saturating instructions executed" }, { .pme_code = 0xB3, .pme_name = "SIMD_INT_INSTRUCTIONS", .pme_desc = "Number of SIMD Integer instructions executed", .pme_umasks = { { .pme_uname = "MUL", .pme_udesc = "Number of SIMD Integer packed multiply instructions executed", .pme_ucode = 0x01 }, { .pme_uname = "SHIFT", .pme_udesc = "Number of SIMD Integer packed shift instructions executed", .pme_ucode = 0x02 }, { .pme_uname = "PACK", .pme_udesc = "Number of SIMD Integer pack operations instruction executed", .pme_ucode = 0x04 }, { .pme_uname = "UNPACK", .pme_udesc = "Number of SIMD Integer unpack instructions executed", .pme_ucode = 0x08 }, { .pme_uname = "LOGICAL", .pme_udesc = "Number of SIMD Integer packed logical instructions executed", .pme_ucode = 0x10 }, { .pme_uname = "ARITHMETIC", .pme_udesc = "Number of SIMD Integer packed arithmetic instructions executed", .pme_ucode = 0x20 } }, .pme_numasks = 6 }, { .pme_code = 0xC0, .pme_name = "INSTR_RET", .pme_desc = "Number of instruction retired (Macro fused instruction count as 2)" }, { .pme_code = 0xC1, .pme_name = "FP_COMP_INSTR_RET", .pme_desc = "Number of FP compute instructions retired (X87 instruction or instruction that contain X87 operations)", .pme_flags = PFMLIB_COREDUO_PMC0 }, { .pme_code = 0xC2, .pme_name = "UOPS_RET", .pme_desc = "Number of micro-ops retired (include fused uops)" }, { .pme_code = 0xC3, .pme_name = "SMC_DETECTED", .pme_desc = "Number of times self-modifying code condition detected" }, { .pme_code = 0xC4, .pme_name = "BR_INSTR_RET", .pme_desc = "Number of branch instructions retired" }, { .pme_code = 0xC5, .pme_name = "BR_MISPRED_RET", .pme_desc = "Number of mispredicted branch instructions retired" }, { .pme_code = 0xC6, .pme_name = "CYCLES_INT_MASKED", .pme_desc = "Cycles while interrupt is disabled" }, { .pme_code = 0xC7, .pme_name = "CYCLES_INT_PEDNING_MASKED", .pme_desc = "Cycles while interrupt is disabled and interrupts are pending" }, { .pme_code = 0xC8, .pme_name = "HW_INT_RX", .pme_desc = "Number of hardware interrupts received" }, { .pme_code = 0xC9, .pme_name = "BR_TAKEN_RET", .pme_desc = "Number of taken branch instruction retired" }, { .pme_code = 0xCA, .pme_name = "BR_MISPRED_TAKEN_RET", .pme_desc = "Number of taken and mispredicted branch instructions retired" }, { .pme_code = 0xCC, .pme_name = "FP_MMX_TRANS", .pme_name = "MMX_FP_TRANS", .pme_desc = "Transitions from MMX (TM) Instructions to Floating Point Instructions", .pme_umasks = { { .pme_uname = "TO_FP", .pme_udesc = "Number of transitions from MMX to X87", .pme_ucode = 0x00 }, { .pme_uname = "TO_MMX", .pme_udesc = "Number of transitions from X87 to MMX", .pme_ucode = 0x01 } }, .pme_numasks = 2 }, { .pme_code = 0xCD, .pme_name = "MMX_ASSIST", .pme_desc = "Number of EMMS executed" }, { .pme_code = 0xCE, .pme_name = "MMX_INSTR_RET", .pme_desc = "Number of MMX instruction retired" }, { .pme_code = 0xD0, .pme_name = "INSTR_DECODED", .pme_desc = "Number of instruction decoded" }, { .pme_code = 0xD7, .pme_name = "ESP_UOPS", .pme_desc = "Number of ESP folding instruction decoded" }, { .pme_code = 0xD8, .pme_name = "SSE_INSTRUCTIONS_RETIRED", .pme_desc = "Number of SSE/SSE2 instructions retired (packed and scalar)", .pme_umasks = { { .pme_uname = "SINGLE", .pme_udesc = "Number of SSE/SSE2 single precision instructions retired (packed and scalar)", .pme_ucode = 0x00 }, { .pme_uname = "SCALAR_SINGLE", .pme_udesc = "Number of SSE/SSE2 scalar single precision instructions retired", .pme_ucode = 0x01, }, { .pme_uname = "PACKED_DOUBLE", .pme_udesc = "Number of SSE/SSE2 packed double percision instructions retired", .pme_ucode = 0x02, }, { .pme_uname = "DOUBLE", .pme_udesc = "Number of SSE/SSE2 scalar double percision instructions retired", .pme_ucode = 0x03, }, { .pme_uname = "INT_128", .pme_udesc = "Number of SSE2 128 bit integer instructions retired", .pme_ucode = 0x04, }, }, .pme_numasks = 5 }, { .pme_code = 0xD9, .pme_name = "SSE_COMP_INSTRUCTIONS_RETIRED", .pme_desc = "Number of computational SSE/SSE2 instructions retired (does not include AND, OR, XOR)", .pme_umasks = { { .pme_uname = "PACKED_SINGLE", .pme_udesc = "Number of SSE/SSE2 packed single precision compute instructions retired (does not include AND, OR, XOR)", .pme_ucode = 0x00 }, { .pme_uname = "SCALAR_SINGLE", .pme_udesc = "Number of SSE/SSE2 scalar single precision compute instructions retired (does not include AND, OR, XOR)", .pme_ucode = 0x01 }, { .pme_uname = "PACKED_DOUBLE", .pme_udesc = "Number of SSE/SSE2 packed double precision compute instructions retired (does not include AND, OR, XOR)", .pme_ucode = 0x02 }, { .pme_uname = "SCALAR_DOUBLE", .pme_udesc = "Number of SSE/SSE2 scalar double precision compute instructions retired (does not include AND, OR, XOR)", .pme_ucode = 0x03 } }, .pme_numasks = 4 }, { .pme_code = 0xDA, .pme_name = "FUSED_UOPS", .pme_desc = "fused uops retired", .pme_umasks = { { .pme_uname = "ALL", .pme_udesc = "All fused uops retired", .pme_ucode = 0x00 }, { .pme_uname = "LOADS", .pme_udesc = "Fused load uops retired", .pme_ucode = 0x01 }, { .pme_uname = "STORES", .pme_udesc = "Fused load uops retired", .pme_ucode = 0x02 }, }, .pme_numasks = 3 }, { .pme_code = 0xDB, .pme_name = "UNFUSION", .pme_desc = "Number of unfusion events in the ROB (due to exception)" }, { .pme_code = 0xE0, .pme_name = "BR_INSTR_DECODED", .pme_desc = "Branch instructions decoded" }, { .pme_code = 0xE2, .pme_name = "BTB_MISSES", .pme_desc = "Number of branches the BTB did not produce a prediction" }, { .pme_code = 0xE4, .pme_name = "BR_BOGUS", .pme_desc = "Number of bogus branches" }, { .pme_code = 0xE6, .pme_name = "BACLEARS", .pme_desc = "Number of BAClears asserted" }, { .pme_code = 0xF0, .pme_name = "PREF_RQSTS_UP", .pme_desc = "Number of hardware prefetch requests issued in forward streams" }, { .pme_code = 0xF8, .pme_name = "PREF_RQSTS_DN", .pme_desc = "Number of hardware prefetch requests issued in backward streams" } }; #define PME_COREDUO_UNHALTED_CORE_CYCLES 0 #define PME_COREDUO_INSTRUCTIONS_RETIRED 2 #define PME_COREDUO_EVENT_COUNT (sizeof(coreduo_pe)/sizeof(pme_coreduo_entry_t)) papi-5.5.1/src/libpfm-3.y/lib/intel_corei7_events.h0000644000307100002310000017675713013651450022037 0ustar yarkhangraduate/* * Copyright (c) 2008 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ static pme_nhm_entry_t corei7_pe[]={ /* * BEGIN architected events */ {.pme_name = "UNHALTED_CORE_CYCLES", .pme_code = 0x003c, .pme_cntmsk = 0x2000f, .pme_flags = PFMLIB_NHM_FIXED1, .pme_desc = "count core clock cycles whenever the clock signal on the specific core is running (not halted). Alias to event CPU_CLK_UNHALTED:THREAD" }, {.pme_name = "INSTRUCTION_RETIRED", .pme_code = 0x00c0, .pme_cntmsk = 0x1000f, .pme_flags = PFMLIB_NHM_FIXED0|PFMLIB_NHM_PEBS, .pme_desc = "count the number of instructions at retirement. Alias to event INST_RETIRED:ANY_P", }, {.pme_name = "INSTRUCTIONS_RETIRED", .pme_code = 0x00c0, .pme_cntmsk = 0x1000f, .pme_flags = PFMLIB_NHM_FIXED0|PFMLIB_NHM_PEBS, .pme_desc = "This is an alias for INSTRUCTION_RETIRED", }, {.pme_name = "UNHALTED_REFERENCE_CYCLES", .pme_code = 0x013c, .pme_cntmsk = 0x40000, .pme_flags = PFMLIB_NHM_FIXED2_ONLY, .pme_desc = "Unhalted reference cycles", }, {.pme_name = "LLC_REFERENCES", .pme_code = 0x4f2e, .pme_cntmsk = 0xf, .pme_desc = "count each request originating from the core to reference a cache line in the last level cache. The count may include speculation, but excludes cache line fills due to hardware prefetch. Alias to L2_RQSTS:SELF_DEMAND_MESI", }, {.pme_name = "LAST_LEVEL_CACHE_REFERENCES", .pme_code = 0x4f2e, .pme_cntmsk = 0xf, .pme_desc = "This is an alias for LLC_REFERENCES", }, {.pme_name = "LLC_MISSES", .pme_code = 0x412e, .pme_cntmsk = 0xf, .pme_desc = "count each cache miss condition for references to the last level cache. The event count may include speculation, but excludes cache line fills due to hardware prefetch. Alias to event L2_RQSTS:SELF_DEMAND_I_STATE", }, {.pme_name = "LAST_LEVEL_CACHE_MISSES", .pme_code = 0x412e, .pme_cntmsk = 0xf, .pme_desc = "This is an alias for LLC_MISSES", }, {.pme_name = "BRANCH_INSTRUCTIONS_RETIRED", .pme_code = 0x00c4, .pme_cntmsk = 0xf, .pme_desc = "count branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instruction. Alias to event BR_INST_RETIRED:ANY", }, /* * BEGIN core specific events */ { .pme_name = "ARITH", .pme_desc = "Counts arithmetic multiply and divide operations", .pme_code = 0x14, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "CYCLES_DIV_BUSY", .pme_udesc = "Counts the number of cycles the divider is busy executing divide or square root operations. The divide can be integer, X87 or Streaming SIMD Extensions (SSE). The square root operation can be either X87 or SSE.", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "DIV", .pme_udesc = "Counts the number of divide or square root operations. The divide can be integer, X87 or Streaming SIMD Extensions (SSE). The square root operation can be either X87 or SSE.", .pme_ucode = 0x01 | (1<<16) | (1<<15) | (1<<10), /* cmask=1  invert=1  edge=1 */ .pme_uflags = 0, }, { .pme_uname = "MUL", .pme_udesc = "Counts the number of multiply operations executed. This includes integer as well as floating point multiply operations but excludes DPPS mul and MPSAD.", .pme_ucode = 0x02, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "BACLEAR", .pme_desc = "Branch address calculator", .pme_code = 0xE6, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "BAD_TARGET", .pme_udesc = "BACLEAR asserted with bad target address", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "CLEAR", .pme_udesc = "BACLEAR asserted, regardless of cause", .pme_ucode = 0x01, .pme_uflags = 0, }, }, .pme_numasks = 2 }, { .pme_name = "BACLEAR_FORCE_IQ", .pme_desc = "Instruction queue forced BACLEAR", .pme_code = 0x01A7, .pme_flags = 0, }, { .pme_name = "BOGUS_BR", .pme_desc = "Counts the number of bogus branches.", .pme_code = 0x01E4, .pme_flags = 0, }, { .pme_name = "BPU_CLEARS", .pme_desc = "Branch prediction Unit clears", .pme_code = 0xE8, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "EARLY", .pme_udesc = "Early Branch Prediciton Unit clears", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "LATE", .pme_udesc = "Late Branch Prediction Unit clears", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "ANY", .pme_udesc = "count any Branch Prediction Unit clears", .pme_ucode = 0x03, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "BPU_MISSED_CALL_RET", .pme_desc = "Branch prediction unit missed call or return", .pme_code = 0x01E5, .pme_flags = 0, }, { .pme_name = "BR_INST_DECODED", .pme_desc = "Branch instructions decoded", .pme_code = 0x01E0, .pme_flags = 0, }, { .pme_name = "BR_INST_EXEC", .pme_desc = "Branch instructions executed", .pme_code = 0x88, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "Branch instructions executed", .pme_ucode = 0x7F, .pme_uflags = 0, }, { .pme_uname = "COND", .pme_udesc = "Conditional branch instructions executed", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "DIRECT", .pme_udesc = "Unconditional branches executed", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "DIRECT_NEAR_CALL", .pme_udesc = "Unconditional call branches executed", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "INDIRECT_NEAR_CALL", .pme_udesc = "Indirect call branches executed", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "INDIRECT_NON_CALL", .pme_udesc = "Indirect non call branches executed", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "NEAR_CALLS", .pme_udesc = "Call branches executed", .pme_ucode = 0x30, .pme_uflags = 0, }, { .pme_uname = "NON_CALLS", .pme_udesc = "All non call branches executed", .pme_ucode = 0x07, .pme_uflags = 0, }, { .pme_uname = "RETURN_NEAR", .pme_udesc = "Indirect return branches executed", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "TAKEN", .pme_udesc = "Taken branches executed", .pme_ucode = 0x40, .pme_uflags = 0, }, }, .pme_numasks = 10 }, { .pme_name = "BR_INST_RETIRED", .pme_desc = "Retired branch instructions", .pme_code = 0xC4, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ALL_BRANCHES", .pme_udesc = "Retired branch instructions (Precise Event)", .pme_ucode = 0x04, .pme_uflags = PFMLIB_NHM_PEBS, }, { .pme_uname = "CONDITIONAL", .pme_udesc = "Retired conditional branch instructions (Precise Event)", .pme_ucode = 0x01, .pme_uflags = PFMLIB_NHM_PEBS, }, { .pme_uname = "NEAR_CALL", .pme_udesc = "Retired near call instructions (Precise Event)", .pme_ucode = 0x02, .pme_uflags = PFMLIB_NHM_PEBS, }, }, .pme_numasks = 3 }, { .pme_name = "BR_MISP_EXEC", .pme_desc = "Mispredicted branches executed", .pme_code = 0x89, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "Mispredicted branches executed", .pme_ucode = 0x7F, .pme_uflags = 0, }, { .pme_uname = "COND", .pme_udesc = "Mispredicted conditional branches executed", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "DIRECT", .pme_udesc = "Mispredicted unconditional branches executed", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "DIRECT_NEAR_CALL", .pme_udesc = "Mispredicted non call branches executed", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "INDIRECT_NEAR_CALL", .pme_udesc = "Mispredicted indirect call branches executed", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "INDIRECT_NON_CALL", .pme_udesc = "Mispredicted indirect non call branches executed", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "NEAR_CALLS", .pme_udesc = "Mispredicted call branches executed", .pme_ucode = 0x30, .pme_uflags = 0, }, { .pme_uname = "NON_CALLS", .pme_udesc = "Mispredicted non call branches executed", .pme_ucode = 0x07, .pme_uflags = 0, }, { .pme_uname = "RETURN_NEAR", .pme_udesc = "Mispredicted return branches executed", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "TAKEN", .pme_udesc = "Mispredicted taken branches executed", .pme_ucode = 0x40, .pme_uflags = 0, }, }, .pme_numasks = 10 }, { .pme_name = "BR_MISP_RETIRED", .pme_desc = "Count Mispredicted Branch Activity", .pme_code = 0xC5, .pme_flags = 0, .pme_umasks = { { .pme_uname = "NEAR_CALL", .pme_udesc = "Counts mispredicted direct and indirect near unconditional retired calls", .pme_ucode = 0x02, .pme_uflags = 0, }, }, .pme_numasks = 1 }, { .pme_name = "CACHE_LOCK_CYCLES", .pme_desc = "Cache lock cycles", .pme_code = 0x63, .pme_flags = PFMLIB_NHM_PMC01, .pme_umasks = { { .pme_uname = "L1D", .pme_udesc = "Cycles L1D locked", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "L1D_L2", .pme_udesc = "Cycles L1D and L2 locked", .pme_ucode = 0x01, .pme_uflags = 0, }, }, .pme_numasks = 2 }, { .pme_name = "CPU_CLK_UNHALTED", .pme_desc = "Cycles when processor is not in halted state", .pme_code = 0x3C, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "THREAD_P", .pme_udesc = "Cycles when thread is not halted (programmable counter)", .pme_ucode = 0x00, .pme_uflags = 0, }, { .pme_uname = "REF_P", .pme_udesc = "Reference base clock (133 Mhz) cycles when thread is not halted", .pme_ucode = 0x01, .pme_uflags = 0, }, }, .pme_numasks = 2 }, { .pme_name = "DTLB_LOAD_MISSES", .pme_desc = "Data TLB load misses", .pme_code = 0x08, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "DTLB load misses", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "PDE_MISS", .pme_udesc = "DTLB load miss caused by low part of address", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "WALK_COMPLETED", .pme_udesc = "DTLB load miss page walks complete", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "STLB_HIT", .pme_udesc = "DTLB second level hit", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "PDP_MISS", .pme_udesc = "Number of DTLB cache load misses where the high part of the linear to physical address translation was missed", .pme_ucode = 0x40, .pme_uflags = 0, }, { .pme_uname = "LARGE_WALK_COMPLETED", .pme_udesc = "Counts number of completed large page walks due to load miss in the STLB", .pme_ucode = 0x80, .pme_uflags = 0, }, }, .pme_numasks = 6 }, { .pme_name = "DTLB_MISSES", .pme_desc = "Data TLB misses", .pme_code = 0x49, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "DTLB misses", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "STLB_HIT", .pme_udesc = "DTLB first level misses but second level hit", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "WALK_COMPLETED", .pme_udesc = "DTLB miss page walks", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "PDE_MISS", .pme_udesc = "Number of DTLB cache misses where the low part of the linear to physical address translation was missed", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "PDP_MISS", .pme_udesc = "Number of DTLB misses where the high part of the linear to physical address translation was missed", .pme_ucode = 0x40, .pme_uflags = 0, }, { .pme_uname = "LARGE_WALK_COMPLETED", .pme_udesc = "Counts number of completed large page walks due to misses in the STLB", .pme_ucode = 0x80, .pme_uflags = 0, }, }, .pme_numasks = 6 }, { .pme_name = "EPT", .pme_desc = "Extended Page Directory", .pme_code = 0x4F, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "EPDE_MISS", .pme_udesc = "Extended Page Directory Entry miss", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "EPDPE_MISS", .pme_udesc = "Extended Page Directory Pointer miss", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "EPDPE_HIT", .pme_udesc = "Extended Page Directory Pointer hit", .pme_ucode = 0x04, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "ES_REG_RENAMES", .pme_desc = "ES segment renames", .pme_code = 0x01D5, .pme_flags = 0, }, { .pme_name = "FP_ASSIST", .pme_desc = "Floating point assists", .pme_code = 0xF7, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ALL", .pme_udesc = "Floating point assists (Precise Event)", .pme_ucode = 0x01, .pme_uflags = PFMLIB_NHM_PEBS, }, { .pme_uname = "INPUT", .pme_udesc = "Floating poiint assists for invalid input value (Precise Event)", .pme_ucode = 0x04, .pme_uflags = PFMLIB_NHM_PEBS, }, { .pme_uname = "OUTPUT", .pme_udesc = "Floating point assists for invalid output value (Precise Event)", .pme_ucode = 0x02, .pme_uflags = PFMLIB_NHM_PEBS, }, }, .pme_numasks = 3 }, { .pme_name = "FP_COMP_OPS_EXE", .pme_desc = "Floating point computational micro-ops", .pme_code = 0x10, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "MMX", .pme_udesc = "MMX Uops", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "SSE_DOUBLE_PRECISION", .pme_udesc = "SSE* FP double precision Uops", .pme_ucode = 0x80, .pme_uflags = 0, }, { .pme_uname = "SSE_FP", .pme_udesc = "SSE and SSE2 FP Uops", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "SSE_FP_PACKED", .pme_udesc = "SSE FP packed Uops", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "SSE_FP_SCALAR", .pme_udesc = "SSE FP scalar Uops", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "SSE_SINGLE_PRECISION", .pme_udesc = "SSE* FP single precision Uops", .pme_ucode = 0x40, .pme_uflags = 0, }, { .pme_uname = "SSE2_INTEGER", .pme_udesc = "SSE2 integer Uops", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "X87", .pme_udesc = "Computational floating-point operations executed", .pme_ucode = 0x01, .pme_uflags = 0, }, }, .pme_numasks = 8 }, { .pme_name = "FP_MMX_TRANS", .pme_desc = "Floating Point to and from MMX transitions", .pme_code = 0xCC, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "All Floating Point to and from MMX transitions", .pme_ucode = 0x03, .pme_uflags = 0, }, { .pme_uname = "TO_FP", .pme_udesc = "Transitions from MMX to Floating Point instructions", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "TO_MMX", .pme_udesc = "Transitions from Floating Point to MMX instructions", .pme_ucode = 0x02, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "HW_INT", .pme_desc = "Hardware interrupts", .pme_code = 0x1D, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "RCV", .pme_udesc = "Number of interrupt received", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "CYCLES_MASKED", .pme_udesc = "Number of cycles interrupt are masked", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "CYCLES_PENDING_AND_MASKED", .pme_udesc = "Number of cycles interrupts are pending and masked", .pme_ucode = 0x04, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "IFU_IVC", .pme_desc = "Instruction Fetch unit victim cache", .pme_code = 0x81, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "FULL", .pme_udesc = "Instruction Fetche unit victim cache full", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "L1I_EVICTION", .pme_udesc = "L1 Instruction cache evictions", .pme_ucode = 0x02, .pme_uflags = 0, }, }, .pme_numasks = 2 }, { .pme_name = "ILD_STALL", .pme_desc = "Instruction Length Decoder stalls", .pme_code = 0x87, .pme_flags = 0, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "Any Instruction Length Decoder stall cycles", .pme_ucode = 0x0F, .pme_uflags = 0, }, { .pme_uname = "IQ_FULL", .pme_udesc = "Instruction Queue full stall cycles", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "LCP", .pme_udesc = "Length Change Prefix stall cycles", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "MRU", .pme_udesc = "Stall cycles due to BPU MRU bypass", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "REGEN", .pme_udesc = "Regen stall cycles", .pme_ucode = 0x08, .pme_uflags = 0, }, }, .pme_numasks = 5 }, { .pme_name = "INST_DECODED", .pme_desc = "Instructions decoded", .pme_code = 0x18, .pme_flags = 0, .pme_umasks = { { .pme_uname = "DEC0", .pme_udesc = "Instructions that must be decoded by decoder 0", .pme_ucode = 0x01, .pme_uflags = 0, }, }, .pme_numasks = 1 }, { .pme_name = "INST_QUEUE_WRITES", .pme_desc = "Instructions written to instruction queue.", .pme_code = 0x0117, .pme_flags = 0, }, { .pme_name = "INST_QUEUE_WRITE_CYCLES", .pme_desc = "Cycles instructions are written to the instruction queue", .pme_code = 0x011E, .pme_flags = 0, }, { .pme_name = "INST_RETIRED", .pme_desc = "Instructions retired", .pme_code = 0xC0, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY_P", .pme_udesc = "Instructions Retired (Precise Event)", .pme_ucode = 0x00, .pme_uflags = PFMLIB_NHM_PEBS, }, { .pme_uname = "X87", .pme_udesc = "Retired floating-point operations (Precise Event)", .pme_ucode = 0x02, .pme_uflags = PFMLIB_NHM_PEBS, }, }, .pme_numasks = 2 }, { .pme_name = "IO_TRANSACTIONS", .pme_desc = "I/O transactions", .pme_code = 0x016C, .pme_flags = 0, }, { .pme_name = "ITLB_FLUSH", .pme_desc = "Counts the number of ITLB flushes", .pme_code = 0x01AE, .pme_flags = 0, }, { .pme_name = "ITLB_MISSES", .pme_desc = "Instruction TLB misses", .pme_code = 0x85, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "ITLB miss", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "WALK_COMPLETED", .pme_udesc = "ITLB miss page walks", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "STLB_HIT", .pme_udesc = "Counts the number of ITLB misses that hit in the second level TLB", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "PDE_MISS", .pme_udesc = "Number of ITLB misses where the low part of the linear to physical address translation was missed", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "PDP_MISS", .pme_udesc = "Number of ITLB misses where the high part of the linear to physical address translation was missed", .pme_ucode = 0x40, .pme_uflags = 0, }, { .pme_uname = "LARGE_WALK_COMPLETED", .pme_udesc = "Counts number of completed large page walks due to misses in the STLB", .pme_ucode = 0x80, .pme_uflags = 0, }, }, .pme_numasks = 6 }, { .pme_name = "ITLB_MISS_RETIRED", .pme_desc = "Retired instructions that missed the ITLB (Precise Event)", .pme_code = 0x20C8, .pme_flags = PFMLIB_NHM_PEBS, }, { .pme_name = "L1D", .pme_desc = "L1D cache", .pme_code = 0x51, .pme_flags = PFMLIB_NHM_PMC01|PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "M_EVICT", .pme_udesc = "L1D cache lines replaced in M state", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "M_REPL", .pme_udesc = "L1D cache lines allocated in the M state", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "M_SNOOP_EVICT", .pme_udesc = "L1D snoop eviction of cache lines in M state", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "REPL", .pme_udesc = "L1 data cache lines allocated", .pme_ucode = 0x01, .pme_uflags = 0, }, }, .pme_numasks = 4 }, { .pme_name = "L1D_ALL_REF", .pme_desc = "L1D references", .pme_code = 0x43, .pme_flags = PFMLIB_NHM_PMC01|PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "All references to the L1 data cache", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "CACHEABLE", .pme_udesc = "L1 data cacheable reads and writes", .pme_ucode = 0x02, .pme_uflags = 0, }, }, .pme_numasks = 2 }, { .pme_name = "L1D_CACHE_LD", .pme_desc = "L1D cacheable loads. WARNING: event may overcount loads", .pme_code = 0x40, .pme_flags = PFMLIB_NHM_PMC01|PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "E_STATE", .pme_udesc = "L1 data cache read in E state", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "I_STATE", .pme_udesc = "L1 data cache read in I state (misses)", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "M_STATE", .pme_udesc = "L1 data cache read in M state", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "MESI", .pme_udesc = "L1 data cache reads", .pme_ucode = 0x0F, .pme_uflags = 0, }, { .pme_uname = "S_STATE", .pme_udesc = "L1 data cache read in S state", .pme_ucode = 0x02, .pme_uflags = 0, }, }, .pme_numasks = 5 }, { .pme_name = "L1D_CACHE_LOCK", .pme_desc = "L1 data cache load lock", .pme_code = 0x42, .pme_flags = PFMLIB_NHM_PMC01|PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "E_STATE", .pme_udesc = "L1 data cache load locks in E state", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "HIT", .pme_udesc = "L1 data cache load lock hits. WARNING: overcounts by 3x", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "M_STATE", .pme_udesc = "L1 data cache load locks in M state. WARNING: overcounts by 3x", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "S_STATE", .pme_udesc = "L1 data cache load locks in S state", .pme_ucode = 0x02, .pme_uflags = 0, }, }, .pme_numasks = 4 }, { .pme_name = "L1D_CACHE_LOCK_FB_HIT", .pme_desc = "L1D load lock accepted in fill buffer", .pme_code = 0x0153, .pme_flags = PFMLIB_NHM_PMC01, }, { .pme_name = "L1D_CACHE_PREFETCH_LOCK_FB_HIT", .pme_desc = "L1D prefetch load lock accepted in fill buffer", .pme_code = 0x0152, .pme_flags = PFMLIB_NHM_PMC01, }, { .pme_name = "L1D_CACHE_ST", .pme_desc = "L1 data cache stores", .pme_code = 0x41, .pme_flags = PFMLIB_NHM_PMC01|PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "E_STATE", .pme_udesc = "L1 data cache stores in E state", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "I_STATE", .pme_udesc = "L1 data cache store in the I state", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "M_STATE", .pme_udesc = "L1 data cache stores in M state", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "S_STATE", .pme_udesc = "L1 data cache stores in S state", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "MESI", .pme_udesc = "L1 data cache store in all states", .pme_ucode = 0x0F, .pme_uflags = 0, }, }, .pme_numasks = 5 }, { .pme_name = "L1D_PREFETCH", .pme_desc = "L1D hardware prefetch", .pme_code = 0x4E, .pme_flags = PFMLIB_NHM_PMC01|PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "MISS", .pme_udesc = "L1D hardware prefetch misses", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "REQUESTS", .pme_udesc = "L1D hardware prefetch requests", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "TRIGGERS", .pme_udesc = "L1D hardware prefetch requests triggered", .pme_ucode = 0x04, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "L1D_WB_L2", .pme_desc = "L1 writebacks to L2", .pme_code = 0x28, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "E_STATE", .pme_udesc = "L1 writebacks to L2 in E state", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "I_STATE", .pme_udesc = "L1 writebacks to L2 in I state (misses)", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "M_STATE", .pme_udesc = "L1 writebacks to L2 in M state", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "S_STATE", .pme_udesc = "L1 writebacks to L2 in S state", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "MESI", .pme_udesc = "All L1 writebacks to L2", .pme_ucode = 0x0F, .pme_uflags = 0, }, }, .pme_numasks = 5 }, { .pme_name = "L1I", .pme_desc = "L1I instruction fetches", .pme_code = 0x80, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "CYCLES_STALLED", .pme_udesc = "L1I instruction fetch stall cycles", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "HITS", .pme_udesc = "L1I instruction fetch hits", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "MISSES", .pme_udesc = "L1I instruction fetch misses", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "READS", .pme_udesc = "L1I Instruction fetches", .pme_ucode = 0x03, .pme_uflags = 0, }, }, .pme_numasks = 4 }, { .pme_name = "L1I_OPPORTUNISTIC_HITS", .pme_desc = "Opportunistic hits in streaming", .pme_code = 0x0183, .pme_flags = 0, }, { .pme_name = "L2_DATA_RQSTS", .pme_desc = "L2 data requests", .pme_code = 0x26, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "All L2 data requests", .pme_ucode = 0xFF, .pme_uflags = 0, }, { .pme_uname = "DEMAND_E_STATE", .pme_udesc = "L2 data demand loads in E state", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "DEMAND_I_STATE", .pme_udesc = "L2 data demand loads in I state (misses)", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "DEMAND_M_STATE", .pme_udesc = "L2 data demand loads in M state", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "DEMAND_MESI", .pme_udesc = "L2 data demand requests", .pme_ucode = 0x0F, .pme_uflags = 0, }, { .pme_uname = "DEMAND_S_STATE", .pme_udesc = "L2 data demand loads in S state", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "PREFETCH_E_STATE", .pme_udesc = "L2 data prefetches in E state", .pme_ucode = 0x40, .pme_uflags = 0, }, { .pme_uname = "PREFETCH_I_STATE", .pme_udesc = "L2 data prefetches in the I state (misses)", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "PREFETCH_M_STATE", .pme_udesc = "L2 data prefetches in M state", .pme_ucode = 0x80, .pme_uflags = 0, }, { .pme_uname = "PREFETCH_MESI", .pme_udesc = "All L2 data prefetches", .pme_ucode = 0xF0, .pme_uflags = 0, }, { .pme_uname = "PREFETCH_S_STATE", .pme_udesc = "L2 data prefetches in the S state", .pme_ucode = 0x20, .pme_uflags = 0, }, }, .pme_numasks = 11 }, { .pme_name = "L2_HW_PREFETCH", .pme_desc = "L2 HW prefetches", .pme_code = 0xF3, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "HIT", .pme_udesc = "Count L2 HW prefetcher detector hits", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "ALLOC", .pme_udesc = "Count L2 HW prefetcher allocations", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "DATA_TRIGGER", .pme_udesc = "Count L2 HW data prefetcher triggered", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "CODE_TRIGGER", .pme_udesc = "Count L2 HW code prefetcher triggered", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "DCA_TRIGGER", .pme_udesc = "Count L2 HW DCA prefetcher triggered", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "KICK_START", .pme_udesc = "Count L2 HW prefetcher kick started", .pme_ucode = 0x20, .pme_uflags = 0, }, }, .pme_numasks = 6 }, { .pme_name = "L2_LINES_IN", .pme_desc = "L2 lines allocated", .pme_code = 0xF1, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "any L2 lines allocated", .pme_ucode = 0x07, .pme_uflags = 0, }, { .pme_uname = "E_STATE", .pme_udesc = "L2 lines allocated in the E state", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "S_STATE", .pme_udesc = "L2 lines allocated in the S state", .pme_ucode = 0x02, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "L2_LINES_OUT", .pme_desc = "L2 lines evicted", .pme_code = 0xF2, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "L2 lines evicted", .pme_ucode = 0x0F, .pme_uflags = 0, }, { .pme_uname = "DEMAND_CLEAN", .pme_udesc = "L2 lines evicted by a demand request", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "DEMAND_DIRTY", .pme_udesc = "L2 modified lines evicted by a demand request", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "PREFETCH_CLEAN", .pme_udesc = "L2 lines evicted by a prefetch request", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "PREFETCH_DIRTY", .pme_udesc = "L2 modified lines evicted by a prefetch request", .pme_ucode = 0x08, .pme_uflags = 0, }, }, .pme_numasks = 5 }, { .pme_name = "L2_RQSTS", .pme_desc = "L2 requests", .pme_code = 0x24, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "MISS", .pme_udesc = "All L2 misses", .pme_ucode = 0xAA, .pme_uflags = 0, }, { .pme_uname = "REFERENCES", .pme_udesc = "All L2 requests", .pme_ucode = 0xFF, .pme_uflags = 0, }, { .pme_uname = "IFETCH_HIT", .pme_udesc = "L2 instruction fetch hits", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "IFETCH_MISS", .pme_udesc = "L2 instruction fetch misses", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "IFETCHES", .pme_udesc = "L2 instruction fetches", .pme_ucode = 0x30, .pme_uflags = 0, }, { .pme_uname = "LD_HIT", .pme_udesc = "L2 load hits", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "LD_MISS", .pme_udesc = "L2 load misses", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "LOADS", .pme_udesc = "L2 requests", .pme_ucode = 0x03, .pme_uflags = 0, }, { .pme_uname = "PREFETCH_HIT", .pme_udesc = "L2 prefetch hits", .pme_ucode = 0x40, .pme_uflags = 0, }, { .pme_uname = "PREFETCH_MISS", .pme_udesc = "L2 prefetch misses", .pme_ucode = 0x80, .pme_uflags = 0, }, { .pme_uname = "PREFETCHES", .pme_udesc = "All L2 prefetches", .pme_ucode = 0xC0, .pme_uflags = 0, }, { .pme_uname = "RFO_HIT", .pme_udesc = "L2 RFO hits", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "RFO_MISS", .pme_udesc = "L2 RFO misses", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "RFOS", .pme_udesc = "L2 RFO requests", .pme_ucode = 0x0C, .pme_uflags = 0, }, }, .pme_numasks = 14 }, { .pme_name = "L2_TRANSACTIONS", .pme_desc = "L2 transactions", .pme_code = 0xF0, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "All L2 transactions", .pme_ucode = 0x80, .pme_uflags = 0, }, { .pme_uname = "FILL", .pme_udesc = "L2 fill transactions", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "IFETCH", .pme_udesc = "L2 instruction fetch transactions", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "L1D_WB", .pme_udesc = "L1D writeback to L2 transactions", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "LOAD", .pme_udesc = "L2 Load transactions", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "PREFETCH", .pme_udesc = "L2 prefetch transactions", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "RFO", .pme_udesc = "L2 RFO transactions", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "WB", .pme_udesc = "L2 writeback to LLC transactions", .pme_ucode = 0x40, .pme_uflags = 0, }, }, .pme_numasks = 8 }, { .pme_name = "L2_WRITE", .pme_desc = "L2 demand lock/store RFO", .pme_code = 0x27, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "LOCK_E_STATE", .pme_udesc = "L2 demand lock RFOs in E state", .pme_ucode = 0x40, .pme_uflags = 0, }, { .pme_uname = "LOCK_I_STATE", .pme_udesc = "L2 demand lock RFOs in I state (misses)", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "LOCK_S_STATE", .pme_udesc = "L2 demand lock RFOs in S state", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "LOCK_HIT", .pme_udesc = "All demand L2 lock RFOs that hit the cache", .pme_ucode = 0xE0, .pme_uflags = 0, }, { .pme_uname = "LOCK_M_STATE", .pme_udesc = "L2 demand lock RFOs in M state", .pme_ucode = 0x80, .pme_uflags = 0, }, { .pme_uname = "LOCK_MESI", .pme_udesc = "All demand L2 lock RFOs", .pme_ucode = 0xF0, .pme_uflags = 0, }, { .pme_uname = "RFO_HIT", .pme_udesc = "All L2 demand store RFOs that hit the cache", .pme_ucode = 0x0E, .pme_uflags = 0, }, { .pme_uname = "RFO_E_STATE", .pme_udesc = "L2 demand store RFOs in the E state (exclusive)", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "RFO_I_STATE", .pme_udesc = "L2 demand store RFOs in I state (misses)", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "RFO_M_STATE", .pme_udesc = "L2 demand store RFOs in M state", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "RFO_MESI", .pme_udesc = "All L2 demand store RFOs", .pme_ucode = 0x0F, .pme_uflags = 0, }, { .pme_uname = "RFO_S_STATE", .pme_udesc = "L2 demand store RFOs in S state", .pme_ucode = 0x02, .pme_uflags = 0, }, }, .pme_numasks = 12 }, { .pme_name = "LARGE_ITLB", .pme_desc = "Large instruction TLB", .pme_code = 0x82, .pme_flags = 0, .pme_umasks = { { .pme_uname = "HIT", .pme_udesc = "Large ITLB hit", .pme_ucode = 0x01, .pme_uflags = 0, }, }, .pme_numasks = 1 }, { .pme_name = "LOAD_DISPATCH", .pme_desc = "Loads dispatched", .pme_code = 0x13, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "All loads dispatched", .pme_ucode = 0x07, .pme_uflags = 0, }, { .pme_uname = "MOB", .pme_udesc = "Loads dispatched from the MOB", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "RS", .pme_udesc = "Loads dispatched that bypass the MOB", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "RS_DELAYED", .pme_udesc = "Loads dispatched from stage 305", .pme_ucode = 0x02, .pme_uflags = 0, }, }, .pme_numasks = 4 }, { .pme_name = "LOAD_HIT_PRE", .pme_desc = "Load operations conflicting with software prefetches", .pme_code = 0x014C, .pme_flags = PFMLIB_NHM_PMC01, }, { .pme_name = "LONGEST_LAT_CACHE", .pme_desc = "Longest latency cache reference", .pme_code = 0x2E, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "REFERENCE", .pme_udesc = "Longest latency cache reference", .pme_ucode = 0x4F, .pme_uflags = 0, }, { .pme_uname = "MISS", .pme_udesc = "Longest latency cache miss", .pme_ucode = 0x41, .pme_uflags = 0, }, }, .pme_numasks = 2 }, { .pme_name = "LSD", .pme_desc = "Loop stream detector", .pme_code = 0xA8, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ACTIVE", .pme_udesc = "Cycles when uops were delivered by the LSD", .pme_ucode = 0x01 | (1<<16), .pme_uflags = 0, }, { .pme_uname = "INACTIVE", .pme_udesc = "Cycles no uops were delivered by the LSD", .pme_ucode = 0x01 | (1<<16)|(1<<15), .pme_uflags = 0, }, }, .pme_numasks = 2 }, { .pme_name = "MACHINE_CLEARS", .pme_desc = "Machine Clear", .pme_code = 0xC3, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "SMC", .pme_udesc = "Self-Modifying Code detected", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "CYCLES", .pme_udesc = "Cycles machine clear asserted", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "MEM_ORDER", .pme_udesc = "Execution pipeline restart due to Memory ordering conflicts", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "FUSION_ASSIST", .pme_udesc = "Counts the number of macro-fusion assists", .pme_ucode = 0x10, .pme_uflags = 0, }, }, .pme_numasks = 4 }, { .pme_name = "MACRO_INSTS", .pme_desc = "Macro-fused instructions", .pme_code = 0xD0, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "DECODED", .pme_udesc = "Instructions decoded", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "FUSIONS_DECODED", .pme_udesc = "Macro-fused instructions decoded", .pme_ucode = 0x01, .pme_uflags = 0, }, }, .pme_numasks = 2 }, { .pme_name = "MEMORY_DISAMBIGUATION", .pme_desc = "Memory Disambiguation Activity", .pme_code = 0x09, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "RESET", .pme_udesc = "Counts memory disambiguation reset cycles", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "WATCHDOG", .pme_udesc = "Counts the number of times the memory disambiguation watchdog kicked in", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "WATCH_CYCLES", .pme_udesc = "Counts the cycles that the memory disambiguation watchdog is active", .pme_ucode = 0x08, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "MEM_INST_RETIRED", .pme_desc = "Memory instructions retired", .pme_code = 0x0B, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "LATENCY_ABOVE_THRESHOLD", .pme_udesc = "Memory instructions retired above programmed clocks, minimum value threhold is 4, requires PEBS", .pme_ucode = 0x10, .pme_uflags = PFMLIB_NHM_PEBS, }, { .pme_uname = "LOADS", .pme_udesc = "Instructions retired which contains a load (Precise Event)", .pme_ucode = 0x01, .pme_uflags = PFMLIB_NHM_PEBS, }, { .pme_uname = "STORES", .pme_udesc = "Instructions retired which contains a store (Precise Event)", .pme_ucode = 0x02, .pme_uflags = PFMLIB_NHM_PEBS, }, }, .pme_numasks = 3 }, { .pme_name = "MEM_LOAD_RETIRED", .pme_desc = "Retired loads", .pme_code = 0xCB, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "DTLB_MISS", .pme_udesc = "Retired loads that miss the DTLB (Precise Event)", .pme_ucode = 0x80, .pme_uflags = PFMLIB_NHM_PEBS, }, { .pme_uname = "HIT_LFB", .pme_udesc = "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)", .pme_ucode = 0x40, .pme_uflags = PFMLIB_NHM_PEBS, }, { .pme_uname = "L1D_HIT", .pme_udesc = "Retired loads that hit the L1 data cache (Precise Event)", .pme_ucode = 0x01, .pme_uflags = PFMLIB_NHM_PEBS, }, { .pme_uname = "L2_HIT", .pme_udesc = "Retired loads that hit the L2 cache (Precise Event)", .pme_ucode = 0x02, .pme_uflags = PFMLIB_NHM_PEBS, }, { .pme_uname = "L3_MISS", .pme_udesc = "Retired loads that miss the LLC cache (Precise Event)", .pme_ucode = 0x10, .pme_uflags = PFMLIB_NHM_PEBS, }, { .pme_uname = "LLC_MISS", .pme_udesc = "This is an alias for L3_MISS", .pme_ucode = 0x10, .pme_uflags = PFMLIB_NHM_PEBS, }, { .pme_uname = "L3_UNSHARED_HIT", .pme_udesc = "Retired loads that hit valid versions in the LLC cache (Precise Event)", .pme_ucode = 0x04, .pme_uflags = PFMLIB_NHM_PEBS, }, { .pme_uname = "LLC_UNSHARED_HIT", .pme_udesc = "This is an alias for L3_UNSHARED_HIT", .pme_ucode = 0x04, .pme_uflags = PFMLIB_NHM_PEBS, }, { .pme_uname = "OTHER_CORE_L2_HIT_HITM", .pme_udesc = "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)", .pme_ucode = 0x08, .pme_uflags = PFMLIB_NHM_PEBS, }, }, .pme_numasks = 9 }, { .pme_name = "MEM_STORE_RETIRED", .pme_desc = "Retired stores", .pme_code = 0x0C, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "DTLB_MISS", .pme_udesc = "Retired stores that miss the DTLB (Precise Event)", .pme_ucode = 0x01, .pme_uflags = PFMLIB_NHM_PEBS, }, }, .pme_numasks = 1 }, { .pme_name = "MEM_UNCORE_RETIRED", .pme_desc = "Load instructions retired which hit offcore", .pme_code = 0x0F, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "OTHER_CORE_L2_HITM", .pme_udesc = "Load instructions retired that HIT modified data in sibling core (Precise Event)", .pme_ucode = 0x02, .pme_uflags = PFMLIB_NHM_PEBS, }, { .pme_uname = "REMOTE_CACHE_LOCAL_HOME_HIT", .pme_udesc = "Load instructions retired remote cache HIT data source (Precise Event)", .pme_ucode = 0x08, .pme_uflags = PFMLIB_NHM_PEBS, }, { .pme_uname = "REMOTE_DRAM", .pme_udesc = "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)", .pme_ucode = 0x10, .pme_uflags = PFMLIB_NHM_PEBS, }, { .pme_uname = "LOCAL_DRAM", .pme_udesc = "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)", .pme_ucode = 0x20, .pme_uflags = PFMLIB_NHM_PEBS, }, /* Model 46 only (must be after common umasks) */ { .pme_uname = "L3_DATA_MISS_UNKNOWN", .pme_udesc = "Load instructions retired where the memory reference missed L3 and data source is unknown (Model 46 only, Precise Event)", .pme_ucode = 0x01, .pme_umodel = 46, .pme_uflags = PFMLIB_NHM_PEBS, }, /* Model 46 only (must be after common umasks) */ { .pme_uname = "UNCACHEABLE", .pme_udesc = "Load instructions retired where the memory reference missed L1, L2, L3 caches and to perform I/O (Model 46 only, Precise Event)", .pme_ucode = 0x80, .pme_umodel = 46, .pme_uflags = PFMLIB_NHM_PEBS, }, }, .pme_numasks = 6 /* patched at runtime for model 46 */ }, { .pme_name = "OFFCORE_REQUESTS", .pme_desc = "Offcore memory requests", .pme_code = 0xB0, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "All offcore requests", .pme_ucode = 0x80, .pme_uflags = 0, }, { .pme_uname = "ANY_READ", .pme_udesc = "Offcore read requests", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "ANY_RFO", .pme_udesc = "Offcore RFO requests", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "DEMAND_READ_CODE", .pme_udesc = "Counts number of offcore demand code read requests. Does not count L2 prefetch requests.", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "DEMAND_READ_DATA", .pme_udesc = "Offcore demand data read requests", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "DEMAND_RFO", .pme_udesc = "Offcore demand RFO requests", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "L1D_WRITEBACK", .pme_udesc = "Offcore L1 data cache writebacks", .pme_ucode = 0x40, .pme_uflags = 0, }, { .pme_uname = "UNCACHED_MEM", .pme_udesc = "Counts number of offcore uncached memory requests", .pme_ucode = 0x20, .pme_uflags = 0, }, }, .pme_numasks = 8 }, { .pme_name = "OFFCORE_REQUESTS_SQ_FULL", .pme_desc = "Counts cycles the Offcore Request buffer or Super Queue is full.", .pme_code = 0x01B2, .pme_flags = 0, }, { .pme_name = "PARTIAL_ADDRESS_ALIAS", .pme_desc = "False dependencies due to partial address aliasing", .pme_code = 0x0107, .pme_flags = 0, }, { .pme_name = "PIC_ACCESSES", .pme_desc = "Programmable interrupt controller", .pme_code = 0xBA, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "TPR_READS", .pme_udesc = "Counts number of TPR reads", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "TPR_WRITES", .pme_udesc = "Counts number of TPR writes", .pme_ucode = 0x02, .pme_uflags = 0, }, }, .pme_numasks = 2 }, { .pme_name = "RAT_STALLS", .pme_desc = "Register allocation table stalls", .pme_code = 0xD2, .pme_flags = 0, .pme_umasks = { { .pme_uname = "FLAGS", .pme_udesc = "Flag stall cycles", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "REGISTERS", .pme_udesc = "Partial register stall cycles", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "ROB_READ_PORT", .pme_udesc = "ROB read port stalls cycles", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "SCOREBOARD", .pme_udesc = "Scoreboard stall cycles", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "ANY", .pme_udesc = "All RAT stall cycles", .pme_ucode = 0x0F, .pme_uflags = 0, }, }, .pme_numasks = 5 }, { .pme_name = "RESOURCE_STALLS", .pme_desc = "Processor stalls", .pme_code = 0xA2, .pme_flags = 0, .pme_umasks = { { .pme_uname = "FPCW", .pme_udesc = "FPU control word write stall cycles", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "LOAD", .pme_udesc = "Load buffer stall cycles", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "MXCSR", .pme_udesc = "MXCSR rename stall cycles", .pme_ucode = 0x40, .pme_uflags = 0, }, { .pme_uname = "RS_FULL", .pme_udesc = "Reservation Station full stall cycles", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "STORE", .pme_udesc = "Store buffer stall cycles", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "OTHER", .pme_udesc = "Other Resource related stall cycles", .pme_ucode = 0x80, .pme_uflags = 0, }, { .pme_uname = "ROB_FULL", .pme_udesc = "ROB full stall cycles", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "ANY", .pme_udesc = "Resource related stall cycles", .pme_ucode = 0x01, .pme_uflags = 0, }, }, .pme_numasks = 8 }, { .pme_name = "SEG_RENAME_STALLS", .pme_desc = "Segment rename stall cycles", .pme_code = 0x01D4, .pme_flags = 0, }, { .pme_name = "SEGMENT_REG_LOADS", .pme_desc = "Counts number of segment register loads", .pme_code = 0x01F8, .pme_flags = 0, }, { .pme_name = "SIMD_INT_128", .pme_desc = "128 bit SIMD integer operations", .pme_code = 0x12, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "PACK", .pme_udesc = "128 bit SIMD integer pack operations", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "PACKED_ARITH", .pme_udesc = "128 bit SIMD integer arithmetic operations", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "PACKED_LOGICAL", .pme_udesc = "128 bit SIMD integer logical operations", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "PACKED_MPY", .pme_udesc = "128 bit SIMD integer multiply operations", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "PACKED_SHIFT", .pme_udesc = "128 bit SIMD integer shift operations", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "SHUFFLE_MOVE", .pme_udesc = "128 bit SIMD integer shuffle/move operations", .pme_ucode = 0x40, .pme_uflags = 0, }, { .pme_uname = "UNPACK", .pme_udesc = "128 bit SIMD integer unpack operations", .pme_ucode = 0x08, .pme_uflags = 0, }, }, .pme_numasks = 7 }, { .pme_name = "SIMD_INT_64", .pme_desc = "64 bit SIMD integer operations", .pme_code = 0xFD, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "PACK", .pme_udesc = "SIMD integer 64 bit pack operations", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "PACKED_ARITH", .pme_udesc = "SIMD integer 64 bit arithmetic operations", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "PACKED_LOGICAL", .pme_udesc = "SIMD integer 64 bit logical operations", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "PACKED_MPY", .pme_udesc = "SIMD integer 64 bit packed multiply operations", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "PACKED_SHIFT", .pme_udesc = "SIMD integer 64 bit shift operations", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "SHUFFLE_MOVE", .pme_udesc = "SIMD integer 64 bit shuffle/move operations", .pme_ucode = 0x40, .pme_uflags = 0, }, { .pme_uname = "UNPACK", .pme_udesc = "SIMD integer 64 bit unpack operations", .pme_ucode = 0x08, .pme_uflags = 0, }, }, .pme_numasks = 7 }, { .pme_name = "SNOOP_RESPONSE", .pme_desc = "Snoop", .pme_code = 0xB8, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "HIT", .pme_udesc = "Thread responded HIT to snoop", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "HITE", .pme_udesc = "Thread responded HITE to snoop", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "HITM", .pme_udesc = "Thread responded HITM to snoop", .pme_ucode = 0x04, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "SQ_FULL_STALL_CYCLES", .pme_desc = "Counts cycles the Offcore Request buffer or Super Queue is full and request(s) are outstanding.", .pme_code = 0x01F6, .pme_flags = 0, }, { .pme_name = "SQ_MISC", .pme_desc = "Super Queue Activity Related to L2 Cache Access", .pme_code = 0xF4, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "PROMOTION", .pme_udesc = "Counts the number of L2 secondary misses that hit the Super Queue", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "PROMOTION_POST_GO", .pme_udesc = "Counts the number of L2 secondary misses during the Super Queue filling L2", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "LRU_HINTS", .pme_udesc = "Counts number of Super Queue LRU hints sent to L3", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "FILL_DROPPED", .pme_udesc = "Counts the number of SQ L2 fills dropped due to L2 busy", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "SPLIT_LOCK", .pme_udesc = "Super Queue lock splits across a cache line", .pme_ucode = 0x10, .pme_uflags = 0, }, }, .pme_numasks = 5 }, { .pme_name = "SSE_MEM_EXEC", .pme_desc = "Streaming SIMD executed", .pme_code = 0x4B, .pme_flags = 0, .pme_umasks = { { .pme_uname = "NTA", .pme_udesc = "Streaming SIMD L1D NTA prefetch miss", .pme_ucode = 0x01, .pme_uflags = 0, }, }, .pme_numasks = 1 }, { .pme_name = "SSEX_UOPS_RETIRED", .pme_desc = "SIMD micro-ops retired", .pme_code = 0xC7, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "PACKED_DOUBLE", .pme_udesc = "SIMD Packed-Double Uops retired (Precise Event)", .pme_ucode = 0x04, .pme_uflags = PFMLIB_NHM_PEBS, }, { .pme_uname = "PACKED_SINGLE", .pme_udesc = "SIMD Packed-Single Uops retired (Precise Event)", .pme_ucode = 0x01, .pme_uflags = PFMLIB_NHM_PEBS, }, { .pme_uname = "SCALAR_DOUBLE", .pme_udesc = "SIMD Scalar-Double Uops retired (Precise Event)", .pme_ucode = 0x08, .pme_uflags = PFMLIB_NHM_PEBS, }, { .pme_uname = "SCALAR_SINGLE", .pme_udesc = "SIMD Scalar-Single Uops retired (Precise Event)", .pme_ucode = 0x02, .pme_uflags = PFMLIB_NHM_PEBS, }, { .pme_uname = "VECTOR_INTEGER", .pme_udesc = "SIMD Vector Integer Uops retired (Precise Event)", .pme_ucode = 0x10, .pme_uflags = PFMLIB_NHM_PEBS, }, }, .pme_numasks = 5 }, { .pme_name = "STORE_BLOCKS", .pme_desc = "Delayed loads", .pme_code = 0x06, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "AT_RET", .pme_udesc = "Loads delayed with at-Retirement block code", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "L1D_BLOCK", .pme_udesc = "Cacheable loads delayed with L1D block code", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "NOT_STA", .pme_udesc = "Loads delayed due to a store blocked for unknown data", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "STA", .pme_udesc = "Loads delayed due to a store blocked for an unknown address", .pme_ucode = 0x02, .pme_uflags = 0, }, }, .pme_numasks = 4 }, { .pme_name = "TWO_UOP_INSTS_DECODED", .pme_desc = "Two micro-ops instructions decoded", .pme_code = 0x0119, .pme_flags = 0, }, { .pme_name = "UOPS_DECODED_DEC0", .pme_desc = "Micro-ops decoded by decoder 0", .pme_code = 0x013D, .pme_flags = 0, }, { .pme_name = "UOPS_DECODED", .pme_desc = "Micro-ops decoded", .pme_code = 0xD1, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ESP_FOLDING", .pme_udesc = "Stack pointer instructions decoded", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "ESP_SYNC", .pme_udesc = "Stack pointer sync operations", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "MS", .pme_udesc = "Uops decoded by Microcode Sequencer", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "MS_CYCLES_ACTIVE", .pme_udesc = "cycles in which at least one uop is decoded by Microcode Sequencer", .pme_ucode = 0x2 | (1<< 16), /* counter-mask = 1 */ }, }, .pme_numasks = 4 }, { .pme_name = "UOPS_EXECUTED", .pme_desc = "Micro-ops executed", .pme_code = 0xB1, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "PORT0", .pme_udesc = "Uops executed on port 0", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "PORT1", .pme_udesc = "Uops executed on port 1", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "PORT2_CORE", .pme_udesc = "Uops executed on port 2 (core count only)", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "PORT3_CORE", .pme_udesc = "Uops executed on port 3 (core count only)", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "PORT4_CORE", .pme_udesc = "Uops executed on port 4 (core count only)", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "PORT5", .pme_udesc = "Uops executed on port 5", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "PORT015", .pme_udesc = "Uops issued on ports 0, 1 or 5", .pme_ucode = 0x40, .pme_uflags = 0, }, { .pme_uname = "PORT234_CORE", .pme_udesc = "Uops issued on ports 2, 3 or 4 (core count only)", .pme_ucode = 0x80, .pme_uflags = 0, }, { .pme_uname = "PORT015_STALL_CYCLES", .pme_udesc = "Cycles no Uops issued on ports 0, 1 or 5", .pme_ucode = 0x40 | (1<<16) | (1<<15), /* counter-mask=1, inv=1 */ .pme_uflags = 0, }, }, .pme_numasks = 9 }, { .pme_name = "UOPS_ISSUED", .pme_desc = "Micro-ops issued", .pme_code = 0x0E, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "Uops issued", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "STALLED_CYCLES", .pme_udesc = "Cycles stalled no issued uops", .pme_ucode = 0x01 | (1<<16) | (1<<15), /* counter-mask=1, inv=1 */ .pme_uflags = 0, }, { .pme_uname = "FUSED", .pme_udesc = "Fused Uops issued", .pme_ucode = 0x02, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "UOPS_RETIRED", .pme_desc = "Micro-ops retired", .pme_code = 0xC2, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "Uops retired (Precise Event)", .pme_ucode = 0x01, .pme_uflags = PFMLIB_NHM_PEBS, }, { .pme_uname = "RETIRE_SLOTS", .pme_udesc = "Retirement slots used (Precise Event)", .pme_ucode = 0x02, .pme_uflags = PFMLIB_NHM_PEBS, }, { .pme_uname = "ACTIVE_CYCLES", .pme_udesc = "Cycles Uops are being retired (Precise Event)", .pme_ucode = 0x01 | (1<< 16), /* counter mask = 1 */ .pme_uflags = PFMLIB_NHM_PEBS, }, { .pme_uname = "STALL_CYCLES", .pme_udesc = "Cycles No Uops retired (Precise Event)", .pme_ucode = 0x01 | (1<<16) | (1<<15), /* counter-mask=1, inv=1 */ .pme_uflags = PFMLIB_NHM_PEBS, }, { .pme_uname = "MACRO_FUSED", .pme_udesc = "Macro-fused Uops retired (Precise Event)", .pme_ucode = 0x04, .pme_uflags = PFMLIB_NHM_PEBS, }, }, .pme_numasks = 5 }, { .pme_name = "UOP_UNFUSION", .pme_desc = "Micro-ops unfusions due to FP exceptions", .pme_code = 0x01DB, .pme_flags = 0, }, /* * BEGIN OFFCORE_RESPONSE */ { .pme_name = "OFFCORE_RESPONSE_0", .pme_desc = "Offcore response", .pme_code = 0x01B7, .pme_flags = PFMLIB_NHM_OFFCORE_RSP0, .pme_umasks = { { .pme_uname = "DMND_DATA_RD", .pme_udesc = "Request. Counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "DMND_RFO", .pme_udesc = "Request. Counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "DMND_IFETCH", .pme_udesc = "Request. Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "WB", .pme_udesc = "Request. Counts the number of writeback (modified to exclusive) transactions", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "PF_DATA_RD", .pme_udesc = "Request. Counts the number of data cacheline reads generated by L2 prefetchers", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "PF_RFO", .pme_udesc = "Request. Counts the number of RFO requests generated by L2 prefetchers", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "PF_IFETCH", .pme_udesc = "Request. Counts the number of code reads generated by L2 prefetchers", .pme_ucode = 0x40, .pme_uflags = 0, }, { .pme_uname = "OTHER", .pme_udesc = "Request. Counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lock", .pme_ucode = 0x80, .pme_uflags = 0, }, { .pme_uname = "ANY_REQUEST", .pme_udesc = "Request. Counts any request type", .pme_ucode = 0xff, .pme_uflags = 0, }, { .pme_uname = "UNCORE_HIT", .pme_udesc = "Response. Counts L3 Hit: local or remote home requests that hit L3 cache in the uncore with no coherency actions required (snooping)", .pme_ucode = 0x100, .pme_uflags = 0, }, { .pme_uname = "OTHER_CORE_HIT_SNP", .pme_udesc = "Response. Counts L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where no modified copies were found (clean)", .pme_ucode = 0x200, .pme_uflags = 0, }, { .pme_uname = "OTHER_CORE_HITM", .pme_udesc = "Response. Counts L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where modified copies were found (HITM)", .pme_ucode = 0x400, .pme_uflags = 0, }, { .pme_uname = "REMOTE_CACHE_FWD", .pme_udesc = "Response. Counts L3 Miss: local homed requests that missed the L3 cache and was serviced by forwarded data following a cross package snoop where no modified copies found. (Remote home requests are not counted)", .pme_ucode = 0x1000, .pme_uflags = 0, }, { .pme_uname = "REMOTE_DRAM", .pme_udesc = "Response. Counts L3 Miss: remote home requests that missed the L3 cache and were serviced by remote DRAM", .pme_ucode = 0x2000, .pme_uflags = 0, }, { .pme_uname = "LOCAL_DRAM", .pme_udesc = "Response. Counts L3 Miss: local home requests that missed the L3 cache and were serviced by local DRAM", .pme_ucode = 0x4000, .pme_uflags = 0, }, { .pme_uname = "NON_DRAM", .pme_udesc = "Response. Non-DRAM requests that were serviced by IOH", .pme_ucode = 0x8000, .pme_uflags = 0, }, { .pme_uname = "ANY_RESPONSE", .pme_udesc = "Response. Counts any response type", .pme_ucode = 0xf700, .pme_uflags = 0, }, }, .pme_numasks = 17 } }; #define PME_COREI7_UNHALTED_CORE_CYCLES 0 #define PME_COREI7_INSTRUCTIONS_RETIRED 1 #define PME_COREI7_EVENT_COUNT (sizeof(corei7_pe)/sizeof(pme_nhm_entry_t)) papi-5.5.1/src/libpfm-3.y/lib/pfmlib_i386_p6_priv.h0000644000307100002310000000426513013651450021537 0ustar yarkhangraduate/* * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #ifndef __PFMLIB_I386_P6_PRIV_H__ #define __PFMLIB_I386_P6_PRIV_H__ #define PFMLIB_I386_P6_MAX_UMASK 16 typedef struct { char *pme_uname; /* unit mask name */ char *pme_udesc; /* event/umask description */ unsigned int pme_ucode; /* unit mask code */ } pme_i386_p6_umask_t; typedef struct { char *pme_name; /* event name */ char *pme_desc; /* event description */ pme_i386_p6_umask_t pme_umasks[PFMLIB_I386_P6_MAX_UMASK]; /* umask desc */ unsigned int pme_code; /* event code */ unsigned int pme_numasks; /* number of umasks */ unsigned int pme_flags; /* flags */ } pme_i386_p6_entry_t; /* * pme_flags values */ #define PFMLIB_I386_P6_UMASK_COMBO 0x01 /* unit mask can be combined */ #define PFMLIB_I386_P6_CTR0_ONLY 0x02 /* event can only be counted on counter 0 */ #define PFMLIB_I386_P6_CTR1_ONLY 0x04 /* event can only be counted on counter 1 */ #endif /* __PFMLIB_I386_P6_PRIV_H__ */ papi-5.5.1/src/libpfm-3.y/lib/amd64_events_fam10h.h0000644000307100002310000021252113013651450021477 0ustar yarkhangraduate/* * Copyright (c) 2007 Advanced Micro Devices, Inc. * Contributed by Robert Richter * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ /* History * * Feb 06 2009 -- Robert Richter, robert.richter@amd.com: * * Update for Family 10h RevD (Istanbul) from: BIOS and Kernel * Developer's Guide (BKDG) For AMD Family 10h Processors, 31116 Rev * 3.20 - February 04, 2009 * * Update for Family 10h RevC (Shanghai) from: BIOS and Kernel * Developer's Guide (BKDG) For AMD Family 10h Processors, 31116 Rev * 3.20 - February 04, 2009 * * * Dec 12 2007 -- Robert Richter, robert.richter@amd.com: * * Created from: BIOS and Kernel Developer's Guide (BKDG) For AMD * Family 10h Processors, 31116 Rev 3.00 - September 07, 2007 */ static pme_amd64_entry_t amd64_fam10h_pe[]={ /* Family 10h RevB, Barcelona */ /* 0 */{.pme_name = "DISPATCHED_FPU", .pme_code = 0x00, .pme_desc = "Dispatched FPU Operations", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 7, .pme_umasks = { { .pme_uname = "OPS_ADD", .pme_udesc = "Add pipe ops excluding load ops and SSE move ops", .pme_ucode = 0x01, }, { .pme_uname = "OPS_MULTIPLY", .pme_udesc = "Multiply pipe ops excluding load ops and SSE move ops", .pme_ucode = 0x02, }, { .pme_uname = "OPS_STORE", .pme_udesc = "Store pipe ops excluding load ops and SSE move ops", .pme_ucode = 0x04, }, { .pme_uname = "OPS_ADD_PIPE_LOAD_OPS", .pme_udesc = "Add pipe load ops and SSE move ops", .pme_ucode = 0x08, }, { .pme_uname = "OPS_MULTIPLY_PIPE_LOAD_OPS", .pme_udesc = "Multiply pipe load ops and SSE move ops", .pme_ucode = 0x10, }, { .pme_uname = "OPS_STORE_PIPE_LOAD_OPS", .pme_udesc = "Store pipe load ops and SSE move ops", .pme_ucode = 0x20, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x3F, }, }, }, /* 1 */{.pme_name = "CYCLES_NO_FPU_OPS_RETIRED", .pme_code = 0x01, .pme_desc = "Cycles in which the FPU is Empty", }, /* 2 */{.pme_name = "DISPATCHED_FPU_OPS_FAST_FLAG", .pme_code = 0x02, .pme_desc = "Dispatched Fast Flag FPU Operations", }, /* 3 */{.pme_name = "RETIRED_SSE_OPERATIONS", .pme_code = 0x03, .pme_desc = "Retired SSE Operations", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 8, .pme_umasks = { { .pme_uname = "SINGLE_ADD_SUB_OPS", .pme_udesc = "Single precision add/subtract ops", .pme_ucode = 0x01, }, { .pme_uname = "SINGLE_MUL_OPS", .pme_udesc = "Single precision multiply ops", .pme_ucode = 0x02, }, { .pme_uname = "SINGLE_DIV_OPS", .pme_udesc = "Single precision divide/square root ops", .pme_ucode = 0x04, }, { .pme_uname = "DOUBLE_ADD_SUB_OPS", .pme_udesc = "Double precision add/subtract ops", .pme_ucode = 0x08, }, { .pme_uname = "DOUBLE_MUL_OPS", .pme_udesc = "Double precision multiply ops", .pme_ucode = 0x10, }, { .pme_uname = "DOUBLE_DIV_OPS", .pme_udesc = "Double precision divide/square root ops", .pme_ucode = 0x20, }, { .pme_uname = "OP_TYPE", .pme_udesc = "Op type: 0=uops. 1=FLOPS", .pme_ucode = 0x40, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x7F, }, }, }, /* 4 */{.pme_name = "RETIRED_MOVE_OPS", .pme_code = 0x04, .pme_desc = "Retired Move Ops", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 5, .pme_umasks = { { .pme_uname = "LOW_QW_MOVE_UOPS", .pme_udesc = "Merging low quadword move uops", .pme_ucode = 0x01, }, { .pme_uname = "HIGH_QW_MOVE_UOPS", .pme_udesc = "Merging high quadword move uops", .pme_ucode = 0x02, }, { .pme_uname = "ALL_OTHER_MERGING_MOVE_UOPS", .pme_udesc = "All other merging move uops", .pme_ucode = 0x04, }, { .pme_uname = "ALL_OTHER_MOVE_UOPS", .pme_udesc = "All other move uops", .pme_ucode = 0x08, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x0F, }, }, }, /* 5 */{.pme_name = "RETIRED_SERIALIZING_OPS", .pme_code = 0x05, .pme_desc = "Retired Serializing Ops", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 5, .pme_umasks = { { .pme_uname = "SSE_BOTTOM_EXECUTING_UOPS", .pme_udesc = "SSE bottom-executing uops retired", .pme_ucode = 0x01, }, { .pme_uname = "SSE_BOTTOM_SERIALIZING_UOPS", .pme_udesc = "SSE bottom-serializing uops retired", .pme_ucode = 0x02, }, { .pme_uname = "X87_BOTTOM_EXECUTING_UOPS", .pme_udesc = "x87 bottom-executing uops retired", .pme_ucode = 0x04, }, { .pme_uname = "X87_BOTTOM_SERIALIZING_UOPS", .pme_udesc = "x87 bottom-serializing uops retired", .pme_ucode = 0x08, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x0F, }, }, }, /* 6 */{.pme_name = "FP_SCHEDULER_CYCLES", .pme_code = 0x06, .pme_desc = "Number of Cycles that a Serializing uop is in the FP Scheduler", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 3, .pme_umasks = { { .pme_uname = "BOTTOM_EXECUTE_CYCLES", .pme_udesc = "Number of cycles a bottom-execute uop is in the FP scheduler", .pme_ucode = 0x01, }, { .pme_uname = "BOTTOM_SERIALIZING_CYCLES", .pme_udesc = "Number of cycles a bottom-serializing uop is in the FP scheduler", .pme_ucode = 0x02, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x03, }, }, }, /* 7 */{.pme_name = "SEGMENT_REGISTER_LOADS", .pme_code = 0x20, .pme_desc = "Segment Register Loads", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 8, .pme_umasks = { { .pme_uname = "ES", .pme_udesc = "ES", .pme_ucode = 0x01, }, { .pme_uname = "CS", .pme_udesc = "CS", .pme_ucode = 0x02, }, { .pme_uname = "SS", .pme_udesc = "SS", .pme_ucode = 0x04, }, { .pme_uname = "DS", .pme_udesc = "DS", .pme_ucode = 0x08, }, { .pme_uname = "FS", .pme_udesc = "FS", .pme_ucode = 0x10, }, { .pme_uname = "GS", .pme_udesc = "GS", .pme_ucode = 0x20, }, { .pme_uname = "HS", .pme_udesc = "HS", .pme_ucode = 0x40, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x7F, }, }, }, /* 8 */{.pme_name = "PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE", .pme_code = 0x21, .pme_desc = "Pipeline Restart Due to Self-Modifying Code", }, /* 9 */{.pme_name = "PIPELINE_RESTART_DUE_TO_PROBE_HIT", .pme_code = 0x22, .pme_desc = "Pipeline Restart Due to Probe Hit", }, /* 10 */{.pme_name = "LS_BUFFER_2_FULL_CYCLES", .pme_code = 0x23, .pme_desc = "LS Buffer 2 Full", }, /* 11 */{.pme_name = "LOCKED_OPS", .pme_code = 0x24, .pme_desc = "Locked Operations", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 5, .pme_umasks = { { .pme_uname = "EXECUTED", .pme_udesc = "The number of locked instructions executed", .pme_ucode = 0x01, }, { .pme_uname = "CYCLES_SPECULATIVE_PHASE", .pme_udesc = "The number of cycles spent in speculative phase", .pme_ucode = 0x02, }, { .pme_uname = "CYCLES_NON_SPECULATIVE_PHASE", .pme_udesc = "The number of cycles spent in non-speculative phase (including cache miss penalty)", .pme_ucode = 0x04, }, { .pme_uname = "CYCLES_WAITING", .pme_udesc = "The number of cycles waiting for a cache hit (cache miss penalty).", .pme_ucode = 0x08, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x0F, }, }, }, /* 12 */{.pme_name = "RETIRED_CLFLUSH_INSTRUCTIONS", .pme_code = 0x26, .pme_desc = "Retired CLFLUSH Instructions", }, /* 13 */{.pme_name = "RETIRED_CPUID_INSTRUCTIONS", .pme_code = 0x27, .pme_desc = "Retired CPUID Instructions", }, /* 14 */{.pme_name = "CANCELLED_STORE_TO_LOAD_FORWARD_OPERATIONS", .pme_code = 0x2A, .pme_desc = "Cancelled Store to Load Forward Operations", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 4, .pme_umasks = { { .pme_uname = "ADDRESS_MISMATCHES", .pme_udesc = "Address mismatches (starting byte not the same).", .pme_ucode = 0x01, }, { .pme_uname = "STORE_IS_SMALLER_THAN_LOAD", .pme_udesc = "Store is smaller than load.", .pme_ucode = 0x02, }, { .pme_uname = "MISALIGNED", .pme_udesc = "Misaligned.", .pme_ucode = 0x04, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x07, }, }, }, /* 15 */{.pme_name = "SMIS_RECEIVED", .pme_code = 0x2B, .pme_desc = "SMIs Received", }, /* 16 */{.pme_name = "DATA_CACHE_ACCESSES", .pme_code = 0x40, .pme_desc = "Data Cache Accesses", }, /* 17 */{.pme_name = "DATA_CACHE_MISSES", .pme_code = 0x41, .pme_desc = "Data Cache Misses", }, /* 18 */{.pme_name = "DATA_CACHE_REFILLS", .pme_code = 0x42, .pme_desc = "Data Cache Refills from L2 or Northbridge", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 6, .pme_umasks = { { .pme_uname = "SYSTEM", .pme_udesc = "Refill from the Northbridge", .pme_ucode = 0x01, }, { .pme_uname = "L2_SHARED", .pme_udesc = "Shared-state line from L2", .pme_ucode = 0x02, }, { .pme_uname = "L2_EXCLUSIVE", .pme_udesc = "Exclusive-state line from L2", .pme_ucode = 0x04, }, { .pme_uname = "L2_OWNED", .pme_udesc = "Owned-state line from L2", .pme_ucode = 0x08, }, { .pme_uname = "L2_MODIFIED", .pme_udesc = "Modified-state line from L2", .pme_ucode = 0x10, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x1F, }, }, }, /* 19 */{.pme_name = "DATA_CACHE_REFILLS_FROM_SYSTEM", .pme_code = 0x43, .pme_desc = "Data Cache Refills from the Northbridge", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 6, .pme_umasks = { { .pme_uname = "INVALID", .pme_udesc = "Invalid", .pme_ucode = 0x01, }, { .pme_uname = "SHARED", .pme_udesc = "Shared", .pme_ucode = 0x02, }, { .pme_uname = "EXCLUSIVE", .pme_udesc = "Exclusive", .pme_ucode = 0x04, }, { .pme_uname = "OWNED", .pme_udesc = "Owned", .pme_ucode = 0x08, }, { .pme_uname = "MODIFIED", .pme_udesc = "Modified", .pme_ucode = 0x10, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x1F, }, }, }, /* 20 */{.pme_name = "DATA_CACHE_LINES_EVICTED", .pme_code = 0x44, .pme_desc = "Data Cache Lines Evicted", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 8, .pme_umasks = { { .pme_uname = "INVALID", .pme_udesc = "Invalid", .pme_ucode = 0x01, }, { .pme_uname = "SHARED", .pme_udesc = "Shared", .pme_ucode = 0x02, }, { .pme_uname = "EXCLUSIVE", .pme_udesc = "Exclusive", .pme_ucode = 0x04, }, { .pme_uname = "OWNED", .pme_udesc = "Owned", .pme_ucode = 0x08, }, { .pme_uname = "MODIFIED", .pme_udesc = "Modified", .pme_ucode = 0x10, }, { .pme_uname = "BY_PREFETCHNTA", .pme_udesc = "Cache line evicted was brought into the cache with by a PrefetchNTA instruction.", .pme_ucode = 0x20, }, { .pme_uname = "NOT_BY_PREFETCHNTA", .pme_udesc = "Cache line evicted was not brought into the cache with by a PrefetchNTA instruction.", .pme_ucode = 0x40, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x7F, }, }, }, /* 21 */{.pme_name = "L1_DTLB_MISS_AND_L2_DTLB_HIT", .pme_code = 0x45, .pme_desc = "L1 DTLB Miss and L2 DTLB Hit", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 5, .pme_umasks = { { .pme_uname = "L2_4K_TLB_HIT", .pme_udesc = "L2 4K TLB hit", .pme_ucode = 0x01, }, { .pme_uname = "L2_2M_TLB_HIT", .pme_udesc = "L2 2M TLB hit", .pme_ucode = 0x02, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x03, .pme_uflags = PFMLIB_AMD64_TILL_FAM10H_REV_B, }, { .pme_uname = "L2_1G_TLB_HIT", .pme_udesc = "L2 1G TLB hit", .pme_ucode = 0x04, .pme_uflags = PFMLIB_AMD64_FAM10H_REV_C, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x07, .pme_uflags = PFMLIB_AMD64_FAM10H_REV_C, }, }, }, /* 22 */{.pme_name = "L1_DTLB_AND_L2_DTLB_MISS", .pme_code = 0x46, .pme_desc = "L1 DTLB and L2 DTLB Miss", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 4, .pme_umasks = { { .pme_uname = "4K_TLB_RELOAD", .pme_udesc = "4K TLB reload", .pme_ucode = 0x01, }, { .pme_uname = "2M_TLB_RELOAD", .pme_udesc = "2M TLB reload", .pme_ucode = 0x02, }, { .pme_uname = "1G_TLB_RELOAD", .pme_udesc = "1G TLB reload", .pme_ucode = 0x04, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x07, }, }, }, /* 23 */{.pme_name = "MISALIGNED_ACCESSES", .pme_code = 0x47, .pme_desc = "Misaligned Accesses", }, /* 24 */{.pme_name = "MICROARCHITECTURAL_LATE_CANCEL_OF_AN_ACCESS", .pme_code = 0x48, .pme_desc = "Microarchitectural Late Cancel of an Access", }, /* 25 */{.pme_name = "MICROARCHITECTURAL_EARLY_CANCEL_OF_AN_ACCESS", .pme_code = 0x49, .pme_desc = "Microarchitectural Early Cancel of an Access", }, /* 26 */{.pme_name = "SCRUBBER_SINGLE_BIT_ECC_ERRORS", .pme_code = 0x4A, .pme_desc = "Single-bit ECC Errors Recorded by Scrubber", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 5, .pme_umasks = { { .pme_uname = "SCRUBBER_ERROR", .pme_udesc = "Scrubber error", .pme_ucode = 0x01, }, { .pme_uname = "PIGGYBACK_ERROR", .pme_udesc = "Piggyback scrubber errors", .pme_ucode = 0x02, }, { .pme_uname = "LOAD_PIPE_ERROR", .pme_udesc = "Load pipe error", .pme_ucode = 0x04, }, { .pme_uname = "STORE_WRITE_PIPE_ERROR", .pme_udesc = "Store write pipe error", .pme_ucode = 0x08, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x0F, }, }, }, /* 27 */{.pme_name = "PREFETCH_INSTRUCTIONS_DISPATCHED", .pme_code = 0x4B, .pme_desc = "Prefetch Instructions Dispatched", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 4, .pme_umasks = { { .pme_uname = "LOAD", .pme_udesc = "Load (Prefetch, PrefetchT0/T1/T2)", .pme_ucode = 0x01, }, { .pme_uname = "STORE", .pme_udesc = "Store (PrefetchW)", .pme_ucode = 0x02, }, { .pme_uname = "NTA", .pme_udesc = "NTA (PrefetchNTA)", .pme_ucode = 0x04, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x07, }, }, }, /* 28 */{.pme_name = "DCACHE_MISSES_BY_LOCKED_INSTRUCTIONS", .pme_code = 0x4C, .pme_desc = "DCACHE Misses by Locked Instructions", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 2, .pme_umasks = { { .pme_uname = "DATA_CACHE_MISSES_BY_LOCKED_INSTRUCTIONS", .pme_udesc = "Data cache misses by locked instructions", .pme_ucode = 0x02, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x02, }, }, }, /* 29 */{.pme_name = "L1_DTLB_HIT", .pme_code = 0x4D, .pme_desc = "L1 DTLB Hit", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 4, .pme_umasks = { { .pme_uname = "L1_4K_TLB_HIT", .pme_udesc = "L1 4K TLB hit", .pme_ucode = 0x01, }, { .pme_uname = "L1_2M_TLB_HIT", .pme_udesc = "L1 2M TLB hit", .pme_ucode = 0x02, }, { .pme_uname = "L1_1G_TLB_HIT", .pme_udesc = "L1 1G TLB hit", .pme_ucode = 0x04, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x07, }, }, }, /* 30 */{.pme_name = "INEFFECTIVE_SW_PREFETCHES", .pme_code = 0x52, .pme_desc = "Ineffective Software Prefetches", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 3, .pme_umasks = { { .pme_uname = "SW_PREFETCH_HIT_IN_L1", .pme_udesc = "Software prefetch hit in the L1.", .pme_ucode = 0x01, }, { .pme_uname = "SW_PREFETCH_HIT_IN_L2", .pme_udesc = "Software prefetch hit in L2.", .pme_ucode = 0x08, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x09, }, }, }, /* 31 */{.pme_name = "GLOBAL_TLB_FLUSHES", .pme_code = 0x54, .pme_desc = "Global TLB Flushes", }, /* 32 */{.pme_name = "MEMORY_REQUESTS", .pme_code = 0x65, .pme_desc = "Memory Requests by Type", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 4, .pme_umasks = { { .pme_uname = "NON_CACHEABLE", .pme_udesc = "Requests to non-cacheable (UC) memory", .pme_ucode = 0x01, }, { .pme_uname = "WRITE_COMBINING", .pme_udesc = "Requests to write-combining (WC) memory or WC buffer flushes to WB memory", .pme_ucode = 0x02, }, { .pme_uname = "STREAMING_STORE", .pme_udesc = "Streaming store (SS) requests", .pme_ucode = 0x80, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x83, }, }, }, /* 33 */{.pme_name = "DATA_PREFETCHES", .pme_code = 0x67, .pme_desc = "Data Prefetcher", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 3, .pme_umasks = { { .pme_uname = "CANCELLED", .pme_udesc = "Cancelled prefetches", .pme_ucode = 0x01, }, { .pme_uname = "ATTEMPTED", .pme_udesc = "Prefetch attempts", .pme_ucode = 0x02, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x03, }, }, }, /* 34 */{.pme_name = "SYSTEM_READ_RESPONSES", .pme_code = 0x6C, .pme_desc = "Northbridge Read Responses by Coherency State", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 6, .pme_umasks = { { .pme_uname = "EXCLUSIVE", .pme_udesc = "Exclusive", .pme_ucode = 0x01, }, { .pme_uname = "MODIFIED", .pme_udesc = "Modified", .pme_ucode = 0x02, }, { .pme_uname = "SHARED", .pme_udesc = "Shared", .pme_ucode = 0x04, }, { .pme_uname = "OWNED", .pme_udesc = "Owned", .pme_ucode = 0x08, }, { .pme_uname = "DATA_ERROR", .pme_udesc = "Data Error", .pme_ucode = 0x10, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x1F, }, }, }, /* 35 */{.pme_name = "QUADWORDS_WRITTEN_TO_SYSTEM", .pme_code = 0x6D, .pme_desc = "Octwords Written to System", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 2, .pme_umasks = { { .pme_uname = "QUADWORD_WRITE_TRANSFER", .pme_udesc = "Octword write transfer", .pme_ucode = 0x01, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x01, }, }, }, /* 36 */{.pme_name = "CPU_CLK_UNHALTED", .pme_code = 0x76, .pme_desc = "CPU Clocks not Halted", }, /* 37 */{.pme_name = "REQUESTS_TO_L2", .pme_code = 0x7D, .pme_desc = "Requests to L2 Cache", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 7, .pme_umasks = { { .pme_uname = "INSTRUCTIONS", .pme_udesc = "IC fill", .pme_ucode = 0x01, }, { .pme_uname = "DATA", .pme_udesc = "DC fill", .pme_ucode = 0x02, }, { .pme_uname = "TLB_WALK", .pme_udesc = "TLB fill (page table walks)", .pme_ucode = 0x04, }, { .pme_uname = "SNOOP", .pme_udesc = "Tag snoop request", .pme_ucode = 0x08, }, { .pme_uname = "CANCELLED", .pme_udesc = "Cancelled request", .pme_ucode = 0x10, }, { .pme_uname = "HW_PREFETCH_FROM_DC", .pme_udesc = "Hardware prefetch from DC", .pme_ucode = 0x20, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x3F, }, }, }, /* 38 */{.pme_name = "L2_CACHE_MISS", .pme_code = 0x7E, .pme_desc = "L2 Cache Misses", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 5, .pme_umasks = { { .pme_uname = "INSTRUCTIONS", .pme_udesc = "IC fill", .pme_ucode = 0x01, }, { .pme_uname = "DATA", .pme_udesc = "DC fill (includes possible replays, whereas EventSelect 041h does not)", .pme_ucode = 0x02, }, { .pme_uname = "TLB_WALK", .pme_udesc = "TLB page table walk", .pme_ucode = 0x04, }, { .pme_uname = "HW_PREFETCH_FROM_DC", .pme_udesc = "Hardware prefetch from DC", .pme_ucode = 0x08, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x0F, }, }, }, /* 39 */{.pme_name = "L2_FILL_WRITEBACK", .pme_code = 0x7F, .pme_desc = "L2 Fill/Writeback", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 3, .pme_umasks = { { .pme_uname = "L2_FILLS", .pme_udesc = "L2 fills (victims from L1 caches, TLB page table walks and data prefetches)", .pme_ucode = 0x01, }, { .pme_uname = "L2_WRITEBACKS", .pme_udesc = "L2 Writebacks to system.", .pme_ucode = 0x02, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x03, }, }, }, /* 40 */{.pme_name = "INSTRUCTION_CACHE_FETCHES", .pme_code = 0x80, .pme_desc = "Instruction Cache Fetches", }, /* 41 */{.pme_name = "INSTRUCTION_CACHE_MISSES", .pme_code = 0x81, .pme_desc = "Instruction Cache Misses", }, /* 42 */{.pme_name = "INSTRUCTION_CACHE_REFILLS_FROM_L2", .pme_code = 0x82, .pme_desc = "Instruction Cache Refills from L2", }, /* 43 */{.pme_name = "INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM", .pme_code = 0x83, .pme_desc = "Instruction Cache Refills from System", }, /* 44 */{.pme_name = "L1_ITLB_MISS_AND_L2_ITLB_HIT", .pme_code = 0x84, .pme_desc = "L1 ITLB Miss and L2 ITLB Hit", }, /* 45 */{.pme_name = "L1_ITLB_MISS_AND_L2_ITLB_MISS", .pme_code = 0x85, .pme_desc = "L1 ITLB Miss and L2 ITLB Miss", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 3, .pme_umasks = { { .pme_uname = "4K_PAGE_FETCHES", .pme_udesc = "Instruction fetches to a 4K page.", .pme_ucode = 0x01, }, { .pme_uname = "2M_PAGE_FETCHES", .pme_udesc = "Instruction fetches to a 2M page.", .pme_ucode = 0x02, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x03, }, }, }, /* 46 */{.pme_name = "PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE", .pme_code = 0x86, .pme_desc = "Pipeline Restart Due to Instruction Stream Probe", }, /* 47 */{.pme_name = "INSTRUCTION_FETCH_STALL", .pme_code = 0x87, .pme_desc = "Instruction Fetch Stall", }, /* 48 */{.pme_name = "RETURN_STACK_HITS", .pme_code = 0x88, .pme_desc = "Return Stack Hits", }, /* 49 */{.pme_name = "RETURN_STACK_OVERFLOWS", .pme_code = 0x89, .pme_desc = "Return Stack Overflows", }, /* 50 */{.pme_name = "INSTRUCTION_CACHE_VICTIMS", .pme_code = 0x8B, .pme_desc = "Instruction Cache Victims", }, /* 51 */{.pme_name = "INSTRUCTION_CACHE_LINES_INVALIDATED", .pme_code = 0x8C, .pme_desc = "Instruction Cache Lines Invalidated", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 3, .pme_umasks = { { .pme_uname = "INVALIDATING_PROBE_NO_IN_FLIGHT", .pme_udesc = "Invalidating probe that did not hit any in-flight instructions.", .pme_ucode = 0x01, }, { .pme_uname = "INVALIDATING_PROBE_ONE_OR_MORE_IN_FLIGHT", .pme_udesc = "Invalidating probe that hit one or more in-flight instructions.", .pme_ucode = 0x02, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x03, }, }, }, /* 52 */{.pme_name = "ITLB_RELOADS", .pme_code = 0x99, .pme_desc = "ITLB Reloads", }, /* 53 */{.pme_name = "ITLB_RELOADS_ABORTED", .pme_code = 0x9A, .pme_desc = "ITLB Reloads Aborted", }, /* 54 */{.pme_name = "RETIRED_INSTRUCTIONS", .pme_code = 0xC0, .pme_desc = "Retired Instructions", }, /* 55 */{.pme_name = "RETIRED_UOPS", .pme_code = 0xC1, .pme_desc = "Retired uops", }, /* 56 */{.pme_name = "RETIRED_BRANCH_INSTRUCTIONS", .pme_code = 0xC2, .pme_desc = "Retired Branch Instructions", }, /* 57 */{.pme_name = "RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS", .pme_code = 0xC3, .pme_desc = "Retired Mispredicted Branch Instructions", }, /* 58 */{.pme_name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS", .pme_code = 0xC4, .pme_desc = "Retired Taken Branch Instructions", }, /* 59 */{.pme_name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED", .pme_code = 0xC5, .pme_desc = "Retired Taken Branch Instructions Mispredicted", }, /* 60 */{.pme_name = "RETIRED_FAR_CONTROL_TRANSFERS", .pme_code = 0xC6, .pme_desc = "Retired Far Control Transfers", }, /* 61 */{.pme_name = "RETIRED_BRANCH_RESYNCS", .pme_code = 0xC7, .pme_desc = "Retired Branch Resyncs", }, /* 62 */{.pme_name = "RETIRED_NEAR_RETURNS", .pme_code = 0xC8, .pme_desc = "Retired Near Returns", }, /* 63 */{.pme_name = "RETIRED_NEAR_RETURNS_MISPREDICTED", .pme_code = 0xC9, .pme_desc = "Retired Near Returns Mispredicted", }, /* 64 */{.pme_name = "RETIRED_INDIRECT_BRANCHES_MISPREDICTED", .pme_code = 0xCA, .pme_desc = "Retired Indirect Branches Mispredicted", }, /* 65 */{.pme_name = "RETIRED_MMX_AND_FP_INSTRUCTIONS", .pme_code = 0xCB, .pme_desc = "Retired MMX/FP Instructions", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 4, .pme_umasks = { { .pme_uname = "X87", .pme_udesc = "x87 instructions", .pme_ucode = 0x01, }, { .pme_uname = "MMX_AND_3DNOW", .pme_udesc = "MMX and 3DNow! instructions", .pme_ucode = 0x02, }, { .pme_uname = "PACKED_SSE_AND_SSE2", .pme_udesc = "SSE instructions (SSE, SSE2, SSE3, and SSE4A)", .pme_ucode = 0x04, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x07, }, }, }, /* 66 */{.pme_name = "RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS", .pme_code = 0xCC, .pme_desc = "Retired Fastpath Double Op Instructions", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 4, .pme_umasks = { { .pme_uname = "POSITION_0", .pme_udesc = "With low op in position 0", .pme_ucode = 0x01, }, { .pme_uname = "POSITION_1", .pme_udesc = "With low op in position 1", .pme_ucode = 0x02, }, { .pme_uname = "POSITION_2", .pme_udesc = "With low op in position 2", .pme_ucode = 0x04, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x07, }, }, }, /* 67 */{.pme_name = "INTERRUPTS_MASKED_CYCLES", .pme_code = 0xCD, .pme_desc = "Interrupts-Masked Cycles", }, /* 68 */{.pme_name = "INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING", .pme_code = 0xCE, .pme_desc = "Interrupts-Masked Cycles with Interrupt Pending", }, /* 69 */{.pme_name = "INTERRUPTS_TAKEN", .pme_code = 0xCF, .pme_desc = "Interrupts Taken", }, /* 70 */{.pme_name = "DECODER_EMPTY", .pme_code = 0xD0, .pme_desc = "Decoder Empty", }, /* 71 */{.pme_name = "DISPATCH_STALLS", .pme_code = 0xD1, .pme_desc = "Dispatch Stalls", }, /* 72 */{.pme_name = "DISPATCH_STALL_FOR_BRANCH_ABORT", .pme_code = 0xD2, .pme_desc = "Dispatch Stall for Branch Abort to Retire", }, /* 73 */{.pme_name = "DISPATCH_STALL_FOR_SERIALIZATION", .pme_code = 0xD3, .pme_desc = "Dispatch Stall for Serialization", }, /* 74 */{.pme_name = "DISPATCH_STALL_FOR_SEGMENT_LOAD", .pme_code = 0xD4, .pme_desc = "Dispatch Stall for Segment Load", }, /* 75 */{.pme_name = "DISPATCH_STALL_FOR_REORDER_BUFFER_FULL", .pme_code = 0xD5, .pme_desc = "Dispatch Stall for Reorder Buffer Full", }, /* 76 */{.pme_name = "DISPATCH_STALL_FOR_RESERVATION_STATION_FULL", .pme_code = 0xD6, .pme_desc = "Dispatch Stall for Reservation Station Full", }, /* 77 */{.pme_name = "DISPATCH_STALL_FOR_FPU_FULL", .pme_code = 0xD7, .pme_desc = "Dispatch Stall for FPU Full", }, /* 78 */{.pme_name = "DISPATCH_STALL_FOR_LS_FULL", .pme_code = 0xD8, .pme_desc = "Dispatch Stall for LS Full", }, /* 79 */{.pme_name = "DISPATCH_STALL_WAITING_FOR_ALL_QUIET", .pme_code = 0xD9, .pme_desc = "Dispatch Stall Waiting for All Quiet", }, /* 80 */{.pme_name = "DISPATCH_STALL_FOR_FAR_TRANSFER_OR_RSYNC", .pme_code = 0xDA, .pme_desc = "Dispatch Stall for Far Transfer or Resync to Retire", }, /* 81 */{.pme_name = "FPU_EXCEPTIONS", .pme_code = 0xDB, .pme_desc = "FPU Exceptions", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 5, .pme_umasks = { { .pme_uname = "X87_RECLASS_MICROFAULTS", .pme_udesc = "x87 reclass microfaults", .pme_ucode = 0x01, }, { .pme_uname = "SSE_RETYPE_MICROFAULTS", .pme_udesc = "SSE retype microfaults", .pme_ucode = 0x02, }, { .pme_uname = "SSE_RECLASS_MICROFAULTS", .pme_udesc = "SSE reclass microfaults", .pme_ucode = 0x04, }, { .pme_uname = "SSE_AND_X87_MICROTRAPS", .pme_udesc = "SSE and x87 microtraps", .pme_ucode = 0x08, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x0F, }, }, }, /* 82 */{.pme_name = "DR0_BREAKPOINT_MATCHES", .pme_code = 0xDC, .pme_desc = "DR0 Breakpoint Matches", }, /* 83 */{.pme_name = "DR1_BREAKPOINT_MATCHES", .pme_code = 0xDD, .pme_desc = "DR1 Breakpoint Matches", }, /* 84 */{.pme_name = "DR2_BREAKPOINT_MATCHES", .pme_code = 0xDE, .pme_desc = "DR2 Breakpoint Matches", }, /* 85 */{.pme_name = "DR3_BREAKPOINT_MATCHES", .pme_code = 0xDF, .pme_desc = "DR3 Breakpoint Matches", }, /* 86 */{.pme_name = "DRAM_ACCESSES_PAGE", .pme_code = 0xE0, .pme_desc = "DRAM Accesses", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 7, .pme_umasks = { { .pme_uname = "HIT", .pme_udesc = "DCT0 Page hit", .pme_ucode = 0x01, }, { .pme_uname = "MISS", .pme_udesc = "DCT0 Page Miss", .pme_ucode = 0x02, }, { .pme_uname = "CONFLICT", .pme_udesc = "DCT0 Page Conflict", .pme_ucode = 0x04, }, { .pme_uname = "DCT1_PAGE_HIT", .pme_udesc = "DCT1 Page hit", .pme_ucode = 0x08, }, { .pme_uname = "DCT1_PAGE_MISS", .pme_udesc = "DCT1 Page Miss", .pme_ucode = 0x10, }, { .pme_uname = "DCT1_PAGE_CONFLICT", .pme_udesc = "DCT1 Page Conflict", .pme_ucode = 0x20, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x3F, }, }, }, /* 87 */{.pme_name = "MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOWS", .pme_code = 0xE1, .pme_desc = "DRAM Controller Page Table Overflows", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 3, .pme_umasks = { { .pme_uname = "DCT0_PAGE_TABLE_OVERFLOW", .pme_udesc = "DCT0 Page Table Overflow", .pme_ucode = 0x01, }, { .pme_uname = "DCT1_PAGE_TABLE_OVERFLOW", .pme_udesc = "DCT1 Page Table Overflow", .pme_ucode = 0x02, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x03, }, }, }, /* 88 */{.pme_name = "MEMORY_CONTROLLER_SLOT_MISSES", .pme_code = 0xE2, .pme_desc = "Memory Controller DRAM Command Slots Missed", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 3, .pme_umasks = { { .pme_uname = "DCT0_COMMAND_SLOTS_MISSED", .pme_udesc = "DCT0 Command Slots Missed", .pme_ucode = 0x01, }, { .pme_uname = "DCT1_COMMAND_SLOTS_MISSED", .pme_udesc = "DCT1 Command Slots Missed", .pme_ucode = 0x02, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x03, }, }, }, /* 89 */{.pme_name = "MEMORY_CONTROLLER_TURNAROUNDS", .pme_code = 0xE3, .pme_desc = "Memory Controller Turnarounds", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 7, .pme_umasks = { { .pme_uname = "CHIP_SELECT", .pme_udesc = "DCT0 DIMM (chip select) turnaround", .pme_ucode = 0x01, }, { .pme_uname = "READ_TO_WRITE", .pme_udesc = "DCT0 Read to write turnaround", .pme_ucode = 0x02, }, { .pme_uname = "WRITE_TO_READ", .pme_udesc = "DCT0 Write to read turnaround", .pme_ucode = 0x04, }, { .pme_uname = "DCT1_DIMM", .pme_udesc = "DCT1 DIMM (chip select) turnaround", .pme_ucode = 0x08, }, { .pme_uname = "DCT1_READ_TO_WRITE_TURNAROUND", .pme_udesc = "DCT1 Read to write turnaround", .pme_ucode = 0x10, }, { .pme_uname = "DCT1_WRITE_TO_READ_TURNAROUND", .pme_udesc = "DCT1 Write to read turnaround", .pme_ucode = 0x20, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x3F, }, }, }, /* 90 */{.pme_name = "MEMORY_CONTROLLER_BYPASS", .pme_code = 0xE4, .pme_desc = "Memory Controller Bypass Counter Saturation", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 5, .pme_umasks = { { .pme_uname = "HIGH_PRIORITY", .pme_udesc = "Memory controller high priority bypass", .pme_ucode = 0x01, }, { .pme_uname = "LOW_PRIORITY", .pme_udesc = "Memory controller medium priority bypass", .pme_ucode = 0x02, }, { .pme_uname = "DRAM_INTERFACE", .pme_udesc = "DCT0 DCQ bypass", .pme_ucode = 0x04, }, { .pme_uname = "DRAM_QUEUE", .pme_udesc = "DCT1 DCQ bypass", .pme_ucode = 0x08, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x0F, }, }, }, /* 91 */{.pme_name = "THERMAL_STATUS_AND_ECC_ERRORS", .pme_code = 0xE8, .pme_desc = "Thermal Status", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 6, .pme_umasks = { { .pme_uname = "CLKS_DIE_TEMP_TOO_HIGH", .pme_udesc = "Number of times the HTC trip point is crossed", .pme_ucode = 0x04, }, { .pme_uname = "CLKS_TEMP_THRESHOLD_EXCEEDED", .pme_udesc = "Number of clocks when STC trip point active", .pme_ucode = 0x08, }, { .pme_uname = "STC_TRIP_POINTS_CROSSED", .pme_udesc = "Number of times the STC trip point is crossed", .pme_ucode = 0x10, }, { .pme_uname = "CLOCKS_HTC_P_STATE_INACTIVE", .pme_udesc = "Number of clocks HTC P-state is inactive.", .pme_ucode = 0x20, }, { .pme_uname = "CLOCKS_HTC_P_STATE_ACTIVE", .pme_udesc = "Number of clocks HTC P-state is active", .pme_ucode = 0x40, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x7C, }, }, }, /* 92 */{.pme_name = "CPU_IO_REQUESTS_TO_MEMORY_IO", .pme_code = 0xE9, .pme_desc = "CPU/IO Requests to Memory/IO", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "I_O_TO_I_O", .pme_udesc = "IO to IO", .pme_ucode = 0x01, }, { .pme_uname = "I_O_TO_MEM", .pme_udesc = "IO to Mem", .pme_ucode = 0x02, }, { .pme_uname = "CPU_TO_I_O", .pme_udesc = "CPU to IO", .pme_ucode = 0x04, }, { .pme_uname = "CPU_TO_MEM", .pme_udesc = "CPU to Mem", .pme_ucode = 0x08, }, { .pme_uname = "TO_REMOTE_NODE", .pme_udesc = "To remote node", .pme_ucode = 0x10, }, { .pme_uname = "TO_LOCAL_NODE", .pme_udesc = "To local node", .pme_ucode = 0x20, }, { .pme_uname = "FROM_REMOTE_NODE", .pme_udesc = "From remote node", .pme_ucode = 0x40, }, { .pme_uname = "FROM_LOCAL_NODE", .pme_udesc = "From local node", .pme_ucode = 0x80, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 93 */{.pme_name = "CACHE_BLOCK", .pme_code = 0xEA, .pme_desc = "Cache Block Commands", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 6, .pme_umasks = { { .pme_uname = "VICTIM_WRITEBACK", .pme_udesc = "Victim Block (Writeback)", .pme_ucode = 0x01, }, { .pme_uname = "DCACHE_LOAD_MISS", .pme_udesc = "Read Block (Dcache load miss refill)", .pme_ucode = 0x04, }, { .pme_uname = "SHARED_ICACHE_REFILL", .pme_udesc = "Read Block Shared (Icache refill)", .pme_ucode = 0x08, }, { .pme_uname = "READ_BLOCK_MODIFIED", .pme_udesc = "Read Block Modified (Dcache store miss refill)", .pme_ucode = 0x10, }, { .pme_uname = "READ_TO_DIRTY", .pme_udesc = "Change-to-Dirty (first store to clean block already in cache)", .pme_ucode = 0x20, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x3D, }, }, }, /* 94 */{.pme_name = "SIZED_COMMANDS", .pme_code = 0xEB, .pme_desc = "Sized Commands", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 7, .pme_umasks = { { .pme_uname = "NON_POSTED_WRITE_BYTE", .pme_udesc = "Non-Posted SzWr Byte (1-32 bytes) Legacy or mapped IO, typically 1-4 bytes", .pme_ucode = 0x01, }, { .pme_uname = "NON_POSTED_WRITE_DWORD", .pme_udesc = "Non-Posted SzWr DW (1-16 dwords) Legacy or mapped IO, typically 1 DWORD", .pme_ucode = 0x02, }, { .pme_uname = "POSTED_WRITE_BYTE", .pme_udesc = "Posted SzWr Byte (1-32 bytes) Sub-cache-line DMA writes, size varies; also flushes of partially-filled Write Combining buffer", .pme_ucode = 0x04, }, { .pme_uname = "POSTED_WRITE_DWORD", .pme_udesc = "Posted SzWr DW (1-16 dwords) Block-oriented DMA writes, often cache-line sized; also processor Write Combining buffer flushes", .pme_ucode = 0x08, }, { .pme_uname = "READ_BYTE_4_BYTES", .pme_udesc = "SzRd Byte (4 bytes) Legacy or mapped IO", .pme_ucode = 0x10, }, { .pme_uname = "READ_DWORD_1_16_DWORDS", .pme_udesc = "SzRd DW (1-16 dwords) Block-oriented DMA reads, typically cache-line size", .pme_ucode = 0x20, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x3F, }, }, }, /* 95 */{.pme_name = "PROBE", .pme_code = 0xEC, .pme_desc = "Probe Responses and Upstream Requests", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "MISS", .pme_udesc = "Probe miss", .pme_ucode = 0x01, }, { .pme_uname = "HIT_CLEAN", .pme_udesc = "Probe hit clean", .pme_ucode = 0x02, }, { .pme_uname = "HIT_DIRTY_NO_MEMORY_CANCEL", .pme_udesc = "Probe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)", .pme_ucode = 0x04, }, { .pme_uname = "HIT_DIRTY_WITH_MEMORY_CANCEL", .pme_udesc = "Probe hit dirty with memory cancel (probed by DMA read or cache refill request)", .pme_ucode = 0x08, }, { .pme_uname = "UPSTREAM_DISPLAY_REFRESH_READS", .pme_udesc = "Upstream display refresh/ISOC reads", .pme_ucode = 0x10, }, { .pme_uname = "UPSTREAM_NON_DISPLAY_REFRESH_READS", .pme_udesc = "Upstream non-display refresh reads", .pme_ucode = 0x20, }, { .pme_uname = "UPSTREAM_WRITES", .pme_udesc = "Upstream ISOC writes", .pme_ucode = 0x40, }, { .pme_uname = "UPSTREAM_NON_ISOC_WRITES", .pme_udesc = "Upstream non-ISOC writes", .pme_ucode = 0x80, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 96 */{.pme_name = "GART", .pme_code = 0xEE, .pme_desc = "GART Events", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "APERTURE_HIT_FROM_CPU", .pme_udesc = "GART aperture hit on access from CPU", .pme_ucode = 0x01, }, { .pme_uname = "APERTURE_HIT_FROM_IO", .pme_udesc = "GART aperture hit on access from IO", .pme_ucode = 0x02, }, { .pme_uname = "MISS", .pme_udesc = "GART miss", .pme_ucode = 0x04, }, { .pme_uname = "REQUEST_HIT_TABLE_WALK", .pme_udesc = "GART/DEV Request hit table walk in progress", .pme_ucode = 0x08, }, { .pme_uname = "DEV_HIT", .pme_udesc = "DEV hit", .pme_ucode = 0x10, }, { .pme_uname = "DEV_MISS", .pme_udesc = "DEV miss", .pme_ucode = 0x20, }, { .pme_uname = "DEV_ERROR", .pme_udesc = "DEV error", .pme_ucode = 0x40, }, { .pme_uname = "MULTIPLE_TABLE_WALK", .pme_udesc = "GART/DEV multiple table walk in progress", .pme_ucode = 0x80, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 97 */{.pme_name = "MEMORY_CONTROLLER_REQUESTS", .pme_code = 0x1F0, .pme_desc = "Memory Controller Requests", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "WRITE_REQUESTS", .pme_udesc = "Write requests sent to the DCT", .pme_ucode = 0x01, }, { .pme_uname = "READ_REQUESTS", .pme_udesc = "Read requests (including prefetch requests) sent to the DCT", .pme_ucode = 0x02, }, { .pme_uname = "PREFETCH_REQUESTS", .pme_udesc = "Prefetch requests sent to the DCT", .pme_ucode = 0x04, }, { .pme_uname = "32_BYTES_WRITES", .pme_udesc = "32 Bytes Sized Writes", .pme_ucode = 0x08, }, { .pme_uname = "64_BYTES_WRITES", .pme_udesc = "64 Bytes Sized Writes", .pme_ucode = 0x10, }, { .pme_uname = "32_BYTES_READS", .pme_udesc = "32 Bytes Sized Reads", .pme_ucode = 0x20, }, { .pme_uname = "64_BYTES_READS", .pme_udesc = "64 Byte Sized Reads", .pme_ucode = 0x40, }, { .pme_uname = "READ_REQUESTS_WHILE_WRITES_REQUESTS", .pme_udesc = "Read requests sent to the DCT while writes requests are pending in the DCT", .pme_ucode = 0x80, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 98 */{.pme_name = "CPU_TO_DRAM_REQUESTS_TO_TARGET_NODE", .pme_code = 0x1E0, .pme_desc = "CPU to DRAM Requests to Target Node", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "LOCAL_TO_0", .pme_udesc = "From Local node to Node 0", .pme_ucode = 0x01, }, { .pme_uname = "LOCAL_TO_1", .pme_udesc = "From Local node to Node 1", .pme_ucode = 0x02, }, { .pme_uname = "LOCAL_TO_2", .pme_udesc = "From Local node to Node 2", .pme_ucode = 0x04, }, { .pme_uname = "LOCAL_TO_3", .pme_udesc = "From Local node to Node 3", .pme_ucode = 0x08, }, { .pme_uname = "LOCAL_TO_4", .pme_udesc = "From Local node to Node 4", .pme_ucode = 0x10, }, { .pme_uname = "LOCAL_TO_5", .pme_udesc = "From Local node to Node 5", .pme_ucode = 0x20, }, { .pme_uname = "LOCAL_TO_6", .pme_udesc = "From Local node to Node 6", .pme_ucode = 0x40, }, { .pme_uname = "LOCAL_TO_7", .pme_udesc = "From Local node to Node 7", .pme_ucode = 0x80, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 99 */{.pme_name = "IO_TO_DRAM_REQUESTS_TO_TARGET_NODE", .pme_code = 0x1E1, .pme_desc = "IO to DRAM Requests to Target Node", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "LOCAL_TO_0", .pme_udesc = "From Local node to Node 0", .pme_ucode = 0x01, }, { .pme_uname = "LOCAL_TO_1", .pme_udesc = "From Local node to Node 1", .pme_ucode = 0x02, }, { .pme_uname = "LOCAL_TO_2", .pme_udesc = "From Local node to Node 2", .pme_ucode = 0x04, }, { .pme_uname = "LOCAL_TO_3", .pme_udesc = "From Local node to Node 3", .pme_ucode = 0x08, }, { .pme_uname = "LOCAL_TO_4", .pme_udesc = "From Local node to Node 4", .pme_ucode = 0x10, }, { .pme_uname = "LOCAL_TO_5", .pme_udesc = "From Local node to Node 5", .pme_ucode = 0x20, }, { .pme_uname = "LOCAL_TO_6", .pme_udesc = "From Local node to Node 6", .pme_ucode = 0x40, }, { .pme_uname = "LOCAL_TO_7", .pme_udesc = "From Local node to Node 7", .pme_ucode = 0x80, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 100 */{.pme_name = "CPU_READ_COMMAND_LATENCY_TO_TARGET_NODE_0_3", .pme_code = 0x1E2, .pme_desc = "CPU Read Command Latency to Target Node 0-3", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "READ_BLOCK", .pme_udesc = "Read block", .pme_ucode = 0x01, }, { .pme_uname = "READ_BLOCK_SHARED", .pme_udesc = "Read block shared", .pme_ucode = 0x02, }, { .pme_uname = "READ_BLOCK_MODIFIED", .pme_udesc = "Read block modified", .pme_ucode = 0x04, }, { .pme_uname = "CHANGE_TO_DIRTY", .pme_udesc = "Change-to-Dirty", .pme_ucode = 0x08, }, { .pme_uname = "LOCAL_TO_0", .pme_udesc = "From Local node to Node 0", .pme_ucode = 0x10, }, { .pme_uname = "LOCAL_TO_1", .pme_udesc = "From Local node to Node 1", .pme_ucode = 0x20, }, { .pme_uname = "LOCAL_TO_2", .pme_udesc = "From Local node to Node 2", .pme_ucode = 0x40, }, { .pme_uname = "LOCAL_TO_3", .pme_udesc = "From Local node to Node 3", .pme_ucode = 0x80, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 101 */{.pme_name = "CPU_READ_COMMAND_REQUESTS_TO_TARGET_NODE_0_3", .pme_code = 0x1E3, .pme_desc = "CPU Read Command Requests to Target Node 0-3", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "READ_BLOCK", .pme_udesc = "Read block", .pme_ucode = 0x01, }, { .pme_uname = "READ_BLOCK_SHARED", .pme_udesc = "Read block shared", .pme_ucode = 0x02, }, { .pme_uname = "READ_BLOCK_MODIFIED", .pme_udesc = "Read block modified", .pme_ucode = 0x04, }, { .pme_uname = "CHANGE_TO_DIRTY", .pme_udesc = "Change-to-Dirty", .pme_ucode = 0x08, }, { .pme_uname = "LOCAL_TO_0", .pme_udesc = "From Local node to Node 0", .pme_ucode = 0x10, }, { .pme_uname = "LOCAL_TO_1", .pme_udesc = "From Local node to Node 1", .pme_ucode = 0x20, }, { .pme_uname = "LOCAL_TO_2", .pme_udesc = "From Local node to Node 2", .pme_ucode = 0x40, }, { .pme_uname = "LOCAL_TO_3", .pme_udesc = "From Local node to Node 3", .pme_ucode = 0x80, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 102 */{.pme_name = "CPU_READ_COMMAND_LATENCY_TO_TARGET_NODE_4_7", .pme_code = 0x1E4, .pme_desc = "CPU Read Command Latency to Target Node 4-7", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "READ_BLOCK", .pme_udesc = "Read block", .pme_ucode = 0x01, }, { .pme_uname = "READ_BLOCK_SHARED", .pme_udesc = "Read block shared", .pme_ucode = 0x02, }, { .pme_uname = "READ_BLOCK_MODIFIED", .pme_udesc = "Read block modified", .pme_ucode = 0x04, }, { .pme_uname = "CHANGE_TO_DIRTY", .pme_udesc = "Change-to-Dirty", .pme_ucode = 0x08, }, { .pme_uname = "LOCAL_TO_4", .pme_udesc = "From Local node to Node 4", .pme_ucode = 0x10, }, { .pme_uname = "LOCAL_TO_5", .pme_udesc = "From Local node to Node 5", .pme_ucode = 0x20, }, { .pme_uname = "LOCAL_TO_6", .pme_udesc = "From Local node to Node 6", .pme_ucode = 0x40, }, { .pme_uname = "LOCAL_TO_7", .pme_udesc = "From Local node to Node 7", .pme_ucode = 0x80, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 103 */{.pme_name = "CPU_READ_COMMAND_REQUESTS_TO_TARGET_NODE_4_7", .pme_code = 0x1E5, .pme_desc = "CPU Read Command Requests to Target Node 4-7", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "READ_BLOCK", .pme_udesc = "Read block", .pme_ucode = 0x01, }, { .pme_uname = "READ_BLOCK_SHARED", .pme_udesc = "Read block shared", .pme_ucode = 0x02, }, { .pme_uname = "READ_BLOCK_MODIFIED", .pme_udesc = "Read block modified", .pme_ucode = 0x04, }, { .pme_uname = "CHANGE_TO_DIRTY", .pme_udesc = "Change-to-Dirty", .pme_ucode = 0x08, }, { .pme_uname = "LOCAL_TO_4", .pme_udesc = "From Local node to Node 4", .pme_ucode = 0x10, }, { .pme_uname = "LOCAL_TO_5", .pme_udesc = "From Local node to Node 5", .pme_ucode = 0x20, }, { .pme_uname = "LOCAL_TO_6", .pme_udesc = "From Local node to Node 6", .pme_ucode = 0x40, }, { .pme_uname = "LOCAL_TO_7", .pme_udesc = "From Local node to Node 7", .pme_ucode = 0x80, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 104 */{.pme_name = "CPU_COMMAND_LATENCY_TO_TARGET_NODE_0_3_4_7", .pme_code = 0x1E6, .pme_desc = "CPU Command Latency to Target Node 0-3/4-7", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "READ_SIZED", .pme_udesc = "Read Sized", .pme_ucode = 0x01, }, { .pme_uname = "WRITE_SIZED", .pme_udesc = "Write Sized", .pme_ucode = 0x02, }, { .pme_uname = "VICTIM_BLOCK", .pme_udesc = "Victim Block", .pme_ucode = 0x04, }, { .pme_uname = "NODE_GROUP_SELECT", .pme_udesc = "Node Group Select. 0=Nodes 0-3. 1= Nodes 4-7.", .pme_ucode = 0x08, }, { .pme_uname = "LOCAL_TO_0_4", .pme_udesc = "From Local node to Node 0/4", .pme_ucode = 0x10, }, { .pme_uname = "LOCAL_TO_1_5", .pme_udesc = "From Local node to Node 1/5", .pme_ucode = 0x20, }, { .pme_uname = "LOCAL_TO_2_6", .pme_udesc = "From Local node to Node 2/6", .pme_ucode = 0x40, }, { .pme_uname = "LOCAL_TO_3_7", .pme_udesc = "From Local node to Node 3/7", .pme_ucode = 0x80, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 105 */{.pme_name = "CPU_REQUESTS_TO_TARGET_NODE_0_3_4_7", .pme_code = 0x1E7, .pme_desc = "CPU Requests to Target Node 0-3/4-7", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "READ_SIZED", .pme_udesc = "Read Sized", .pme_ucode = 0x01, }, { .pme_uname = "WRITE_SIZED", .pme_udesc = "Write Sized", .pme_ucode = 0x02, }, { .pme_uname = "VICTIM_BLOCK", .pme_udesc = "Victim Block", .pme_ucode = 0x04, }, { .pme_uname = "NODE_GROUP_SELECT", .pme_udesc = "Node Group Select. 0=Nodes 0-3. 1= Nodes 4-7.", .pme_ucode = 0x08, }, { .pme_uname = "LOCAL_TO_0_4", .pme_udesc = "From Local node to Node 0/4", .pme_ucode = 0x10, }, { .pme_uname = "LOCAL_TO_1_5", .pme_udesc = "From Local node to Node 1/5", .pme_ucode = 0x20, }, { .pme_uname = "LOCAL_TO_2_6", .pme_udesc = "From Local node to Node 2/6", .pme_ucode = 0x40, }, { .pme_uname = "LOCAL_TO_3_7", .pme_udesc = "From Local node to Node 3/7", .pme_ucode = 0x80, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 106 */{.pme_name = "HYPERTRANSPORT_LINK0", .pme_code = 0xF6, .pme_desc = "HyperTransport Link 0 Transmit Bandwidth", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 8, .pme_umasks = { { .pme_uname = "COMMAND_DWORD_SENT", .pme_udesc = "Command DWORD sent", .pme_ucode = 0x01, }, { .pme_uname = "DATA_DWORD_SENT", .pme_udesc = "Data DWORD sent", .pme_ucode = 0x02, }, { .pme_uname = "BUFFER_RELEASE_DWORD_SENT", .pme_udesc = "Buffer release DWORD sent", .pme_ucode = 0x04, }, { .pme_uname = "NOP_DWORD_SENT", .pme_udesc = "Nop DW sent (idle)", .pme_ucode = 0x08, }, { .pme_uname = "ADDRESS_EXT_DWORD_SENT", .pme_udesc = "Address extension DWORD sent", .pme_ucode = 0x10, }, { .pme_uname = "PER_PACKET_CRC_SENT", .pme_udesc = "Per packet CRC sent", .pme_ucode = 0x20, }, { .pme_uname = "SUBLINK_MASK", .pme_udesc = "SubLink Mask", .pme_ucode = 0x80, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xBF, }, }, }, /* 107 */{.pme_name = "HYPERTRANSPORT_LINK1", .pme_code = 0xF7, .pme_desc = "HyperTransport Link 1 Transmit Bandwidth", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 8, .pme_umasks = { { .pme_uname = "COMMAND_DWORD_SENT", .pme_udesc = "Command DWORD sent", .pme_ucode = 0x01, }, { .pme_uname = "DATA_DWORD_SENT", .pme_udesc = "Data DWORD sent", .pme_ucode = 0x02, }, { .pme_uname = "BUFFER_RELEASE_DWORD_SENT", .pme_udesc = "Buffer release DWORD sent", .pme_ucode = 0x04, }, { .pme_uname = "NOP_DWORD_SENT", .pme_udesc = "Nop DW sent (idle)", .pme_ucode = 0x08, }, { .pme_uname = "ADDRESS_EXT_DWORD_SENT", .pme_udesc = "Address extension DWORD sent", .pme_ucode = 0x10, }, { .pme_uname = "PER_PACKET_CRC_SENT", .pme_udesc = "Per packet CRC sent", .pme_ucode = 0x20, }, { .pme_uname = "SUBLINK_MASK", .pme_udesc = "SubLink Mask", .pme_ucode = 0x80, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xBF, }, }, }, /* 108 */{.pme_name = "HYPERTRANSPORT_LINK2", .pme_code = 0xF8, .pme_desc = "HyperTransport Link 2 Transmit Bandwidth", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 8, .pme_umasks = { { .pme_uname = "COMMAND_DWORD_SENT", .pme_udesc = "Command DWORD sent", .pme_ucode = 0x01, }, { .pme_uname = "DATA_DWORD_SENT", .pme_udesc = "Data DWORD sent", .pme_ucode = 0x02, }, { .pme_uname = "BUFFER_RELEASE_DWORD_SENT", .pme_udesc = "Buffer release DWORD sent", .pme_ucode = 0x04, }, { .pme_uname = "NOP_DWORD_SENT", .pme_udesc = "Nop DW sent (idle)", .pme_ucode = 0x08, }, { .pme_uname = "ADDRESS_EXT_DWORD_SENT", .pme_udesc = "Address extension DWORD sent", .pme_ucode = 0x10, }, { .pme_uname = "PER_PACKET_CRC_SENT", .pme_udesc = "Per packet CRC sent", .pme_ucode = 0x20, }, { .pme_uname = "SUBLINK_MASK", .pme_udesc = "SubLink Mask", .pme_ucode = 0x80, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xBF, }, }, }, /* 109 */{.pme_name = "HYPERTRANSPORT_LINK3", .pme_code = 0x1F9, .pme_desc = "HyperTransport Link 3 Transmit Bandwidth", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 8, .pme_umasks = { { .pme_uname = "COMMAND_DWORD_SENT", .pme_udesc = "Command DWORD sent", .pme_ucode = 0x01, }, { .pme_uname = "DATA_DWORD_SENT", .pme_udesc = "Data DWORD sent", .pme_ucode = 0x02, }, { .pme_uname = "BUFFER_RELEASE_DWORD_SENT", .pme_udesc = "Buffer release DWORD sent", .pme_ucode = 0x04, }, { .pme_uname = "NOP_DWORD_SENT", .pme_udesc = "Nop DW sent (idle)", .pme_ucode = 0x08, }, { .pme_uname = "ADDRESS_EXT_DWORD_SENT", .pme_udesc = "Address DWORD sent", .pme_ucode = 0x10, }, { .pme_uname = "PER_PACKET_CRC_SENT", .pme_udesc = "Per packet CRC sent", .pme_ucode = 0x20, }, { .pme_uname = "SUBLINK_MASK", .pme_udesc = "SubLink Mask", .pme_ucode = 0x80, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xBF, }, }, }, /* 110 */{.pme_name = "READ_REQUEST_TO_L3_CACHE", .pme_code = 0x4E0, .pme_desc = "Read Request to L3 Cache", .pme_flags = PFMLIB_AMD64_UMASK_COMBO|PFMLIB_AMD64_TILL_FAM10H_REV_C, .pme_numasks = 5, .pme_umasks = { { .pme_uname = "READ_BLOCK_EXCLUSIVE", .pme_udesc = "Read Block Exclusive (Data cache read)", .pme_ucode = 0x01, }, { .pme_uname = "READ_BLOCK_SHARED", .pme_udesc = "Read Block Shared (Instruction cache read)", .pme_ucode = 0x02, }, { .pme_uname = "READ_BLOCK_MODIFY", .pme_udesc = "Read Block Modify", .pme_ucode = 0x04, }, { .pme_uname = "ANY_READ", .pme_udesc = "any read modes (exclusive, shared, modify)", .pme_ucode = 0x07, }, #if 0 /* * http://support.amd.com/us/Processor_TechDocs/41322.pdf * * Issue number 437 on page 131. * */ { .pme_uname = "CORE_0_SELECT", .pme_udesc = "Core 0 Select", .pme_ucode = 0x10, }, { .pme_uname = "CORE_1_SELECT", .pme_udesc = "Core 1 Select", .pme_ucode = 0x20, }, { .pme_uname = "CORE_2_SELECT", .pme_udesc = "Core 2 Select", .pme_ucode = 0x40, }, { .pme_uname = "CORE_3_SELECT", .pme_udesc = "Core 3 Select", .pme_ucode = 0x80, }, #endif { .pme_uname = "ALL_CORES", .pme_udesc = "All cores", .pme_ucode = 0xF0, }, }, }, /* 111 */{.pme_name = "L3_CACHE_MISSES", .pme_code = 0x4E1, .pme_desc = "L3 Cache Misses", .pme_flags = PFMLIB_AMD64_UMASK_COMBO|PFMLIB_AMD64_TILL_FAM10H_REV_C, .pme_numasks = 5, .pme_umasks = { { .pme_uname = "READ_BLOCK_EXCLUSIVE", .pme_udesc = "Read Block Exclusive (Data cache read)", .pme_ucode = 0x01, }, { .pme_uname = "READ_BLOCK_SHARED", .pme_udesc = "Read Block Shared (Instruction cache read)", .pme_ucode = 0x02, }, { .pme_uname = "READ_BLOCK_MODIFY", .pme_udesc = "Read Block Modify", .pme_ucode = 0x04, }, { .pme_uname = "ANY_READ", .pme_udesc = "any read modes (exclusive, shared, modify)", .pme_ucode = 0x07, }, #if 0 /* * http://support.amd.com/us/Processor_TechDocs/41322.pdf * * Issue number 437 on page 131. * */ { .pme_uname = "CORE_0_SELECT", .pme_udesc = "Core 0 Select", .pme_ucode = 0x10, }, { .pme_uname = "CORE_1_SELECT", .pme_udesc = "Core 1 Select", .pme_ucode = 0x20, }, { .pme_uname = "CORE_2_SELECT", .pme_udesc = "Core 2 Select", .pme_ucode = 0x40, }, { .pme_uname = "CORE_3_SELECT", .pme_udesc = "Core 3 Select", .pme_ucode = 0x80, }, #endif { .pme_uname = "ALL_CORES", .pme_udesc = "All cores", .pme_ucode = 0xF0, }, }, }, /* 112 */{.pme_name = "L3_FILLS_CAUSED_BY_L2_EVICTIONS", .pme_code = 0x4E2, .pme_desc = "L3 Fills caused by L2 Evictions", .pme_flags = PFMLIB_AMD64_UMASK_COMBO|PFMLIB_AMD64_TILL_FAM10H_REV_C, .pme_numasks = 6, .pme_umasks = { { .pme_uname = "SHARED", .pme_udesc = "Shared", .pme_ucode = 0x01, }, { .pme_uname = "EXCLUSIVE", .pme_udesc = "Exclusive", .pme_ucode = 0x02, }, { .pme_uname = "OWNED", .pme_udesc = "Owned", .pme_ucode = 0x04, }, { .pme_uname = "MODIFIED", .pme_udesc = "Modified", .pme_ucode = 0x08, }, { .pme_uname = "ANY_STATE", .pme_udesc = "any line state (shared, owned, exclusive, modified)", .pme_ucode = 0x0F, }, #if 0 /* * http://support.amd.com/us/Processor_TechDocs/41322.pdf * * Issue number 437 on page 131. * */ { .pme_uname = "CORE_0_SELECT", .pme_udesc = "Core 0 Select", .pme_ucode = 0x10, }, { .pme_uname = "CORE_1_SELECT", .pme_udesc = "Core 1 Select", .pme_ucode = 0x20, }, { .pme_uname = "CORE_2_SELECT", .pme_udesc = "Core 2 Select", .pme_ucode = 0x40, }, { .pme_uname = "CORE_3_SELECT", .pme_udesc = "Core 3 Select", .pme_ucode = 0x80, }, #endif { .pme_uname = "ALL_CORES", .pme_udesc = "All cores", .pme_ucode = 0xF0, }, }, }, /* 113 */{.pme_name = "L3_EVICTIONS", .pme_code = 0x4E3, .pme_desc = "L3 Evictions", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 5, .pme_umasks = { { .pme_uname = "SHARED", .pme_udesc = "Shared", .pme_ucode = 0x01, }, { .pme_uname = "EXCLUSIVE", .pme_udesc = "Exclusive", .pme_ucode = 0x02, }, { .pme_uname = "OWNED", .pme_udesc = "Owned", .pme_ucode = 0x04, }, { .pme_uname = "MODIFIED", .pme_udesc = "Modified", .pme_ucode = 0x08, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x0F, }, }, }, /* Family 10h RevC, Shanghai */ /* 114 */{.pme_name = "PAGE_SIZE_MISMATCHES", .pme_code = 0x165, .pme_desc = "Page Size Mismatches", .pme_flags = PFMLIB_AMD64_UMASK_COMBO|PFMLIB_AMD64_FAM10H_REV_C, .pme_numasks = 4, .pme_umasks = { { .pme_uname = "GUEST_LARGER", .pme_udesc = "Guest page size is larger than the host page size.", .pme_ucode = 0x01, }, { .pme_uname = "MTRR_MISMATCH", .pme_udesc = "MTRR mismatch.", .pme_ucode = 0x02, }, { .pme_uname = "HOST_LARGER", .pme_udesc = "Host page size is larger than the guest page size.", .pme_ucode = 0x04, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x07, }, }, }, /* 115 */{.pme_name = "RETIRED_X87_OPS", .pme_code = 0x1C0, .pme_desc = "Retired x87 Floating Point Operations", .pme_flags = PFMLIB_AMD64_UMASK_COMBO|PFMLIB_AMD64_FAM10H_REV_C, .pme_numasks = 4, .pme_umasks = { { .pme_uname = "ADD_SUB_OPS", .pme_udesc = "Add/subtract ops", .pme_ucode = 0x01, }, { .pme_uname = "MUL_OPS", .pme_udesc = "Multiply ops", .pme_ucode = 0x02, }, { .pme_uname = "DIV_OPS", .pme_udesc = "Divide ops", .pme_ucode = 0x04, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x07, }, }, }, /* 116 */{.pme_name = "IBS_OPS_TAGGED", .pme_code = 0x1CF, .pme_desc = "IBS Ops Tagged", .pme_flags = PFMLIB_AMD64_FAM10H_REV_C, }, /* 117 */{.pme_name = "LFENCE_INST_RETIRED", .pme_code = 0x1D3, .pme_desc = "LFENCE Instructions Retired", .pme_flags = PFMLIB_AMD64_FAM10H_REV_C, }, /* 118 */{.pme_name = "SFENCE_INST_RETIRED", .pme_code = 0x1D4, .pme_desc = "SFENCE Instructions Retired", .pme_flags = PFMLIB_AMD64_FAM10H_REV_C, }, /* 119 */{.pme_name = "MFENCE_INST_RETIRED", .pme_code = 0x1D5, .pme_desc = "MFENCE Instructions Retired", .pme_flags = PFMLIB_AMD64_FAM10H_REV_C, }, /* Family 10h RevD, Istanbul */ /* 120 */{.pme_name = "READ_REQUEST_TO_L3_CACHE", .pme_code = 0x4E0, .pme_desc = "Read Request to L3 Cache", .pme_flags = PFMLIB_AMD64_UMASK_COMBO|PFMLIB_AMD64_FAM10H_REV_D, .pme_numasks = 5, .pme_umasks = { { .pme_uname = "READ_BLOCK_EXCLUSIVE", .pme_udesc = "Read Block Exclusive (Data cache read)", .pme_ucode = 0x01, }, { .pme_uname = "READ_BLOCK_SHARED", .pme_udesc = "Read Block Shared (Instruction cache read)", .pme_ucode = 0x02, }, { .pme_uname = "READ_BLOCK_MODIFY", .pme_udesc = "Read Block Modify", .pme_ucode = 0x04, }, { .pme_uname = "ANY_READ", .pme_udesc = "any read modes (exclusive, shared, modify)", .pme_ucode = 0x07, }, #if 0 /* * http://support.amd.com/us/Processor_TechDocs/41322.pdf * * Issue number 437 on page 131. * */ { .pme_uname = "CORE_0_SELECT", .pme_udesc = "Core 0 Select", .pme_ucode = 0x00, }, { .pme_uname = "CORE_1_SELECT", .pme_udesc = "Core 1 Select", .pme_ucode = 0x10, }, { .pme_uname = "CORE_2_SELECT", .pme_udesc = "Core 2 Select", .pme_ucode = 0x20, }, { .pme_uname = "CORE_3_SELECT", .pme_udesc = "Core 3 Select", .pme_ucode = 0x30, }, { .pme_uname = "CORE_4_SELECT", .pme_udesc = "Core 4 Select", .pme_ucode = 0x40, }, { .pme_uname = "CORE_5_SELECT", .pme_udesc = "Core 5 Select", .pme_ucode = 0x50, }, { .pme_uname = "ANY_CORE", .pme_udesc = "Any core", .pme_ucode = 0xF0, }, #endif { .pme_uname = "ALL_CORES", .pme_udesc = "All cores", .pme_ucode = 0xF0, }, }, }, /* 121 */{.pme_name = "L3_CACHE_MISSES", .pme_code = 0x4E1, .pme_desc = "L3 Cache Misses", .pme_flags = PFMLIB_AMD64_UMASK_COMBO|PFMLIB_AMD64_FAM10H_REV_D, .pme_numasks = 5, .pme_umasks = { { .pme_uname = "READ_BLOCK_EXCLUSIVE", .pme_udesc = "Read Block Exclusive (Data cache read)", .pme_ucode = 0x01, }, { .pme_uname = "READ_BLOCK_SHARED", .pme_udesc = "Read Block Shared (Instruction cache read)", .pme_ucode = 0x02, }, { .pme_uname = "READ_BLOCK_MODIFY", .pme_udesc = "Read Block Modify", .pme_ucode = 0x04, }, { .pme_uname = "ANY_READ", .pme_udesc = "any read modes (exclusive, shared, modify)", .pme_ucode = 0x07, }, #if 0 /* * http://support.amd.com/us/Processor_TechDocs/41322.pdf * * Issue number 437 on page 131. * */ { .pme_uname = "CORE_0_SELECT", .pme_udesc = "Core 0 Select", .pme_ucode = 0x00, }, { .pme_uname = "CORE_1_SELECT", .pme_udesc = "Core 1 Select", .pme_ucode = 0x10, }, { .pme_uname = "CORE_2_SELECT", .pme_udesc = "Core 2 Select", .pme_ucode = 0x20, }, { .pme_uname = "CORE_3_SELECT", .pme_udesc = "Core 3 Select", .pme_ucode = 0x30, }, { .pme_uname = "CORE_4_SELECT", .pme_udesc = "Core 4 Select", .pme_ucode = 0x40, }, { .pme_uname = "CORE_5_SELECT", .pme_udesc = "Core 5 Select", .pme_ucode = 0x50, }, { .pme_uname = "ANY_CORE", .pme_udesc = "Any core", .pme_ucode = 0xF0, }, #endif { .pme_uname = "ALL_CORES", .pme_udesc = "All cores", .pme_ucode = 0xF0, }, }, }, /* 122 */{.pme_name = "L3_FILLS_CAUSED_BY_L2_EVICTIONS", .pme_code = 0x4E2, .pme_desc = "L3 Fills caused by L2 Evictions", .pme_flags = PFMLIB_AMD64_UMASK_COMBO|PFMLIB_AMD64_FAM10H_REV_D, .pme_numasks = 6, .pme_umasks = { { .pme_uname = "SHARED", .pme_udesc = "Shared", .pme_ucode = 0x01, }, { .pme_uname = "EXCLUSIVE", .pme_udesc = "Exclusive", .pme_ucode = 0x02, }, { .pme_uname = "OWNED", .pme_udesc = "Owned", .pme_ucode = 0x04, }, { .pme_uname = "MODIFIED", .pme_udesc = "Modified", .pme_ucode = 0x08, }, { .pme_uname = "ANY_STATE", .pme_udesc = "any line state (shared, owned, exclusive, modified)", .pme_ucode = 0x0F, }, #if 0 /* * http://support.amd.com/us/Processor_TechDocs/41322.pdf * * Issue number 437 on page 131. * */ { .pme_uname = "CORE_0_SELECT", .pme_udesc = "Core 0 Select", .pme_ucode = 0x00, }, { .pme_uname = "CORE_1_SELECT", .pme_udesc = "Core 1 Select", .pme_ucode = 0x10, }, { .pme_uname = "CORE_2_SELECT", .pme_udesc = "Core 2 Select", .pme_ucode = 0x20, }, { .pme_uname = "CORE_3_SELECT", .pme_udesc = "Core 3 Select", .pme_ucode = 0x30, }, { .pme_uname = "CORE_4_SELECT", .pme_udesc = "Core 4 Select", .pme_ucode = 0x40, }, { .pme_uname = "CORE_5_SELECT", .pme_udesc = "Core 5 Select", .pme_ucode = 0x50, }, { .pme_uname = "ANY_CORE", .pme_udesc = "Any core", .pme_ucode = 0xF0, }, #endif { .pme_uname = "ALL_CORES", .pme_udesc = "All cores", .pme_ucode = 0xF0, }, }, }, /* 123 */{.pme_name = "IBSOP_EVENT", .pme_code = 0xFF, .pme_desc = "Enable IBS OP mode (pseudo event)", .pme_flags = 0, .pme_numasks = 2, .pme_umasks = { { .pme_uname = "CYCLES", .pme_udesc = "sample cycles", .pme_ucode = 0x01, }, { .pme_uname = "UOPS", .pme_udesc = "sample dispatched uops (Rev C and later)", .pme_ucode = 0x02, }, }, }, /* 124 */{.pme_name = "IBSFETCH_EVENT", .pme_code = 0xFF, .pme_desc = "Enable IBS Fetch mode (pseudo event)", .pme_flags = 0, .pme_numasks = 2, .pme_umasks = { { .pme_uname = "RANDOM", .pme_udesc = "randomize period", .pme_ucode = 0x01, }, { .pme_uname = "NO_RANDOM", .pme_udesc = "do not randomize period", .pme_ucode = 0x00, }, }, }, /* 125 */{.pme_name = "MAB_REQUESTS", .pme_code = 0x68, .pme_desc = "Average L1 refill latency for Icache and Dcache misses (request count for cache refills)", .pme_numasks = 10, .pme_umasks = { { .pme_uname = "BUFFER_0", .pme_udesc = "Buffer 0", .pme_ucode = 0x00, }, { .pme_uname = "BUFFER_1", .pme_udesc = "Buffer 1", .pme_ucode = 0x01, }, { .pme_uname = "BUFFER_2", .pme_udesc = "Buffer 2", .pme_ucode = 0x02, }, { .pme_uname = "BUFFER_3", .pme_udesc = "Buffer 3", .pme_ucode = 0x03, }, { .pme_uname = "BUFFER_4", .pme_udesc = "Buffer 4", .pme_ucode = 0x04, }, { .pme_uname = "BUFFER_5", .pme_udesc = "Buffer 5", .pme_ucode = 0x05, }, { .pme_uname = "BUFFER_6", .pme_udesc = "Buffer 6", .pme_ucode = 0x06, }, { .pme_uname = "BUFFER_7", .pme_udesc = "Buffer 7", .pme_ucode = 0x07, }, { .pme_uname = "BUFFER_8", .pme_udesc = "Buffer 8", .pme_ucode = 0x08, }, { .pme_uname = "BUFFER_9", .pme_udesc = "Buffer 9", .pme_ucode = 0x09, }, }, }, /* 126 */{.pme_name = "MAB_WAIT_CYCLES", .pme_code = 0x69, .pme_desc = "Average L1 refill latency for Icache and Dcache misses (cycles that requests spent waiting for the refills)", .pme_numasks = 10, .pme_umasks = { { .pme_uname = "BUFFER_0", .pme_udesc = "Buffer 0", .pme_ucode = 0x00, }, { .pme_uname = "BUFFER_1", .pme_udesc = "Buffer 1", .pme_ucode = 0x01, }, { .pme_uname = "BUFFER_2", .pme_udesc = "Buffer 2", .pme_ucode = 0x02, }, { .pme_uname = "BUFFER_3", .pme_udesc = "Buffer 3", .pme_ucode = 0x03, }, { .pme_uname = "BUFFER_4", .pme_udesc = "Buffer 4", .pme_ucode = 0x04, }, { .pme_uname = "BUFFER_5", .pme_udesc = "Buffer 5", .pme_ucode = 0x05, }, { .pme_uname = "BUFFER_6", .pme_udesc = "Buffer 6", .pme_ucode = 0x06, }, { .pme_uname = "BUFFER_7", .pme_udesc = "Buffer 7", .pme_ucode = 0x07, }, { .pme_uname = "BUFFER_8", .pme_udesc = "Buffer 8", .pme_ucode = 0x08, }, { .pme_uname = "BUFFER_9", .pme_udesc = "Buffer 9", .pme_ucode = 0x09, }, }, }, /* 127 */{.pme_name = "NON_CANCELLED_L3_READ_REQUESTS", .pme_code = 0x4ED, .pme_desc = "Non-cancelled L3 Read Requests", .pme_numasks = 5, .pme_umasks = { { .pme_uname = "READ_BLOCK_EXCLUSIVE", .pme_udesc = "Read Block Exclusive (Data cache read)", .pme_ucode = 0x01, }, { .pme_uname = "READ_BLOCK_SHARED", .pme_udesc = "Read Block Shared (Instruction cache read)", .pme_ucode = 0x02, }, { .pme_uname = "READ_BLOCK_MODIFY", .pme_udesc = "Read Block Modify", .pme_ucode = 0x04, }, { .pme_uname = "ANY_READ", .pme_udesc = "any read modes (exclusive, shared, modify)", .pme_ucode = 0x07, }, #if 0 /* * http://support.amd.com/us/Processor_TechDocs/41322.pdf * * Issue number 437 on page 131. * */ { .pme_uname = "CORE_0_SELECT", .pme_udesc = "Core 0 Select", .pme_ucode = 0x00, }, { .pme_uname = "CORE_1_SELECT", .pme_udesc = "Core 1 Select", .pme_ucode = 0x10, }, { .pme_uname = "CORE_2_SELECT", .pme_udesc = "Core 2 Select", .pme_ucode = 0x20, }, { .pme_uname = "CORE_3_SELECT", .pme_udesc = "Core 3 Select", .pme_ucode = 0x30, }, { .pme_uname = "CORE_4_SELECT", .pme_udesc = "Core 4 Select", .pme_ucode = 0x40, }, { .pme_uname = "CORE_5_SELECT", .pme_udesc = "Core 5 Select", .pme_ucode = 0x50, }, #endif { .pme_uname = "ALL_CORES", .pme_udesc = "All cores", .pme_ucode = 0xF0, }, }, }, }; #define PME_AMD64_FAM10H_EVENT_COUNT (sizeof(amd64_fam10h_pe)/sizeof(pme_amd64_entry_t)) #define PME_AMD64_FAM10H_CPU_CLK_UNHALTED 36 #define PME_AMD64_FAM10H_RETIRED_INSTRUCTIONS 54 #define PME_AMD64_IBSOP 123 #define PME_AMD64_IBSFETCH 124 papi-5.5.1/src/libpfm-3.y/lib/pfmlib_crayx2_priv.h0000644000307100002310000000707013013651450021646 0ustar yarkhangraduate/* * Copyright (c) 2007 Cray Inc. * Contributed by Steve Kaufmann based on code from * Copyright (c) 2001-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef __PMLIB_CRAYX2_PRIV_H__ #define __PMLIB_CRAYX2_PRIV_H__ 1 #include /* Chips (substrates) that contain performance counters. */ #define PME_CRAYX2_CHIP_CPU 1 #define PME_CRAYX2_CHIP_CACHE 2 #define PME_CRAYX2_CHIP_MEMORY 3 /* Number of chips monitored per single process. */ #define PME_CRAYX2_CPU_CHIPS 1 #define PME_CRAYX2_CACHE_CHIPS 1 #define PME_CRAYX2_MEMORY_CHIPS 16 /* Number of events per physical counter. */ #define PME_CRAYX2_EVENTS_PER_COUNTER 4 /* Number of counters per chip (CPU, L2 Cache, Memory) */ #define PME_CRAYX2_CPU_CTRS_PER_CHIP PFM_CPU_PMD_COUNT #define PME_CRAYX2_CACHE_CTRS_PER_CHIP PFM_CACHE_PMD_PER_CHIP #define PME_CRAYX2_MEMORY_CTRS_PER_CHIP PFM_MEM_PMD_PER_CHIP /* Number of events per chip (CPU, L2 Cache, Memory) */ #define PME_CRAYX2_CPU_EVENTS \ (PME_CRAYX2_CPU_CHIPS*PME_CRAYX2_CPU_CTRS_PER_CHIP*PME_CRAYX2_EVENTS_PER_COUNTER) #define PME_CRAYX2_CACHE_EVENTS \ (PME_CRAYX2_CACHE_CHIPS*PME_CRAYX2_CACHE_CTRS_PER_CHIP*PME_CRAYX2_EVENTS_PER_COUNTER) #define PME_CRAYX2_MEMORY_EVENTS \ (PME_CRAYX2_MEMORY_CHIPS*PME_CRAYX2_MEMORY_CTRS_PER_CHIP*PME_CRAYX2_EVENTS_PER_COUNTER) /* No unit masks are (currently) used. */ #define PFMLIB_CRAYX2_MAX_UMASK 1 typedef struct { const char *pme_uname; /* unit mask name */ const char *pme_udesc; /* event/umask description */ unsigned int pme_ucode; /* unit mask code */ } pme_crayx2_umask_t; /* Description of each performance counter event available on all * substrates. Listed contiguously for all substrates. */ typedef struct { const char *pme_name; /* event name */ const char *pme_desc; /* event description */ unsigned int pme_code; /* event code */ unsigned int pme_flags; /* flags */ unsigned int pme_numasks; /* number of unit masks */ pme_crayx2_umask_t pme_umasks[PFMLIB_CRAYX2_MAX_UMASK]; /* unit masks (chip numbers) */ unsigned int pme_chip; /* substrate/chip containing counter */ unsigned int pme_ctr; /* counter on chip */ unsigned int pme_event; /* event number on counter */ unsigned int pme_chipno; /* chip# upon which the event lies */ unsigned int pme_base; /* PMD base reg_num for this chip */ unsigned int pme_nctrs; /* PMDs/counters per chip */ unsigned int pme_nchips; /* number of chips per process */ } pme_crayx2_entry_t; #endif /* __PMLIB_CRAYX2_PRIV_H__ */ papi-5.5.1/src/libpfm-3.y/lib/pfmlib_itanium2_priv.h0000644000307100002310000001217113013651450022164 0ustar yarkhangraduate/* * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #ifndef __PFMLIB_ITANIUM2_PRIV_H__ #define __PFMLIB_ITANIUM2_PRIV_H__ /* * Event type definitions * * The virtual events are not really defined in the specs but are an artifact used * to quickly and easily setup EAR and/or BTB. The event type encodes the exact feature * which must be configured in combination with a counting monitor. * For instance, DATA_EAR_CACHE_LAT4 is a virtual D-EAR cache event. If the user * requests this event, this will configure a counting monitor to count DATA_EAR_EVENTS * and PMC11 will be configured for cache mode. The latency is encoded in the umask, here * it would correspond to 4 cycles. * */ #define PFMLIB_ITA2_EVENT_NORMAL 0x0 /* standard counter */ #define PFMLIB_ITA2_EVENT_BTB 0x1 /* virtual event used with BTB configuration */ #define PFMLIB_ITA2_EVENT_IEAR_TLB 0x2 /* virtual event used for I-EAR TLB configuration */ #define PFMLIB_ITA2_EVENT_IEAR_CACHE 0x3 /* virtual event used for I-EAR cache configuration */ #define PFMLIB_ITA2_EVENT_DEAR_TLB 0x4 /* virtual event used for D-EAR TLB configuration */ #define PFMLIB_ITA2_EVENT_DEAR_CACHE 0x5 /* virtual event used for D-EAR cache configuration */ #define PFMLIB_ITA2_EVENT_DEAR_ALAT 0x6 /* virtual event used for D-EAR ALAT configuration */ #define event_is_ear(e) ((e)->pme_type >= PFMLIB_ITA2_EVENT_IEAR_TLB &&(e)->pme_type <= PFMLIB_ITA2_EVENT_DEAR_ALAT) #define event_is_iear(e) ((e)->pme_type == PFMLIB_ITA2_EVENT_IEAR_TLB || (e)->pme_type == PFMLIB_ITA2_EVENT_IEAR_CACHE) #define event_is_dear(e) ((e)->pme_type >= PFMLIB_ITA2_EVENT_DEAR_TLB && (e)->pme_type <= PFMLIB_ITA2_EVENT_DEAR_ALAT) #define event_is_ear_cache(e) ((e)->pme_type == PFMLIB_ITA2_EVENT_DEAR_CACHE || (e)->pme_type == PFMLIB_ITA2_EVENT_IEAR_CACHE) #define event_is_ear_tlb(e) ((e)->pme_type == PFMLIB_ITA2_EVENT_IEAR_TLB || (e)->pme_type == PFMLIB_ITA2_EVENT_DEAR_TLB) #define event_is_ear_alat(e) ((e)->pme_type == PFMLIB_ITA2_EVENT_DEAR_ALAT) #define event_is_btb(e) ((e)->pme_type == PFMLIB_ITA2_EVENT_BTB) /* * Itanium encoding structure * (code must be first 8 bits) */ typedef struct { unsigned long pme_code:8; /* major event code */ unsigned long pme_type:3; /* see definitions above */ unsigned long pme_ig1:5; /* ignored */ unsigned long pme_umask:16; /* unit mask*/ unsigned long pme_ig:32; /* ignored */ } pme_ita2_entry_code_t; typedef union { unsigned long pme_vcode; pme_ita2_entry_code_t pme_ita2_code; /* must not be larger than vcode */ } pme_ita2_code_t; typedef union { unsigned long qual; /* generic qualifier */ struct { unsigned long pme_iar:1; /* instruction address range supported */ unsigned long pme_opm:1; /* opcode match supported */ unsigned long pme_dar:1; /* data address range supported */ unsigned long pme_res1:13; /* reserved */ unsigned long pme_group:4; /* event group */ unsigned long pme_set:4; /* event feature set*/ unsigned long pme_res2:40; /* reserved */ } pme_qual; } pme_ita2_qualifiers_t; typedef struct { char *pme_name; pme_ita2_code_t pme_entry_code; unsigned long pme_counters; /* supported counters */ unsigned int pme_maxincr; pme_ita2_qualifiers_t pme_qualifiers; char *pme_desc; /* text description of the event */ } pme_ita2_entry_t; /* * We embed the umask value into the event code. Because it really is * like a subevent. * pme_code: * - lower 16 bits: major event code * - upper 16 bits: unit mask */ #define pme_code pme_entry_code.pme_ita2_code.pme_code #define pme_umask pme_entry_code.pme_ita2_code.pme_umask #define pme_used pme_qualifiers.pme_qual_struct.pme_used #define pme_type pme_entry_code.pme_ita2_code.pme_type #define event_opcm_ok(e) ((e)->pme_qualifiers.pme_qual.pme_opm==1) #define event_iarr_ok(e) ((e)->pme_qualifiers.pme_qual.pme_iar==1) #define event_darr_ok(e) ((e)->pme_qualifiers.pme_qual.pme_dar==1) #endif /* __PFMLIB_ITANIUM2_PRIV_H__ */ papi-5.5.1/src/libpfm-3.y/lib/pfmlib_intel_atom_priv.h0000644000307100002310000000653013013651450022571 0ustar yarkhangraduate/* * Copyright (c) 2008 Google, Inc * Contributed by Stephane Eranian * * Based on: * Copyright (c) 2006-2007 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #ifndef __PFMLIB_INTEL_ATOM_PRIV_H__ #define __PFMLIB_INTEL_ATOM_PRIV_H__ #define PFMLIB_INTEL_ATOM_MAX_UMASK 16 typedef struct { char *pme_uname; /* unit mask name */ char *pme_udesc; /* event/umask description */ unsigned int pme_ucode; /* unit mask code */ unsigned int pme_flags; /* unit mask flags */ } pme_intel_atom_umask_t; typedef struct { char *pme_name; /* event name */ char *pme_desc; /* event description */ unsigned int pme_code; /* event code */ unsigned int pme_numasks; /* number of umasks */ unsigned int pme_flags; /* flags */ unsigned int pme_fixed; /* fixed counter index, < FIXED_CTR0 if unsupported */ pme_intel_atom_umask_t pme_umasks[PFMLIB_INTEL_ATOM_MAX_UMASK]; /* umask desc */ } pme_intel_atom_entry_t; /* * pme_flags value */ /* * pme_flags value (event and unit mask) */ #define PFMLIB_INTEL_ATOM_UMASK_NCOMBO 0x01 /* unit mask cannot be combined (default exclusive) */ #define PFMLIB_INTEL_ATOM_FIXED0 0x02 /* event supported by FIXED_CTR0, can work on generic counters */ #define PFMLIB_INTEL_ATOM_FIXED1 0x04 /* event supported by FIXED_CTR1, can work on generic counters */ #define PFMLIB_INTEL_ATOM_FIXED2_ONLY 0x08 /* works only on FIXED_CTR2 */ #define PFMLIB_INTEL_ATOM_PEBS 0x10 /* support PEBS (precise event) */ #define PFMLIB_INTEL_ATOM_PMC0 0x20 /* works only on IA32_PMC0 */ #define PFMLIB_INTEL_ATOM_PMC1 0x40 /* works only on IA32_PMC1 */ typedef struct { unsigned int version:8; unsigned int num_cnt:8; unsigned int cnt_width:8; unsigned int ebx_length:8; } pmu_eax_t; typedef struct { unsigned int num_cnt:6; unsigned int cnt_width:6; unsigned int reserved:20; } pmu_edx_t; typedef struct { unsigned int no_core_cycle:1; unsigned int no_inst_retired:1; unsigned int no_ref_cycle:1; unsigned int no_llc_ref:1; unsigned int no_llc_miss:1; unsigned int no_br_retired:1; unsigned int no_br_mispred_retired:1; unsigned int reserved:25; } pmu_ebx_t; #endif /* __PFMLIB_INTEL_ATOM_PRIV_H__ */ papi-5.5.1/src/libpfm-3.y/lib/pfmlib_os_linux_v2.c0000644000307100002310000003125313013651450021640 0ustar yarkhangraduate/* * pfmlib_os_linux_v2.c: Perfmon2 syscall API * * Copyright (c) 2003-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include "pfmlib_priv.h" /* * v2.x interface */ #define PFM_pfm_create_context (_pfmlib_get_sys_base()+0) #define PFM_pfm_write_pmcs (_pfmlib_get_sys_base()+1) #define PFM_pfm_write_pmds (_pfmlib_get_sys_base()+2) #define PFM_pfm_read_pmds (_pfmlib_get_sys_base()+3) #define PFM_pfm_load_context (_pfmlib_get_sys_base()+4) #define PFM_pfm_start (_pfmlib_get_sys_base()+5) #define PFM_pfm_stop (_pfmlib_get_sys_base()+6) #define PFM_pfm_restart (_pfmlib_get_sys_base()+7) #define PFM_pfm_create_evtsets (_pfmlib_get_sys_base()+8) #define PFM_pfm_getinfo_evtsets (_pfmlib_get_sys_base()+9) #define PFM_pfm_delete_evtsets (_pfmlib_get_sys_base()+10) #define PFM_pfm_unload_context (_pfmlib_get_sys_base()+11) /* * argument to v2.2 pfm_create_context() * ALWAYS use pfarg_ctx_t in programs, libpfm * does convert ths structure on the fly if v2.2. is detected */ typedef struct { unsigned char ctx_smpl_buf_id[16]; /* which buffer format to use */ uint32_t ctx_flags; /* noblock/block/syswide */ int32_t ctx_fd; /* ret arg: fd for context */ uint64_t ctx_smpl_buf_size; /* ret arg: actual buffer sz */ uint64_t ctx_reserved3[12]; /* for future use */ } pfarg_ctx22_t; /* * perfmon2 compatibility layer with perfmon3 */ #ifndef PFMLIB_OLD_PFMV2 static int pfm_create_context_2v3(pfarg_ctx_t *ctx, char *name, void *smpl_arg, size_t smpl_size) { pfarg_sinfo_t cinfo; uint32_t fl; /* * simulate kernel returning error on NULL ctx */ if (!ctx) { errno = EINVAL; return -1; } /* * if sampling format is used, then force SMPL_FMT * and PFM_FL_SINFO because it comes first */ fl = ctx->ctx_flags; if (name || smpl_arg || smpl_size) fl |= PFM_FL_SMPL_FMT; return pfm_create(fl, &cinfo, name, smpl_arg, smpl_size); } static int pfm_write_pmcs_2v3(int fd, pfarg_pmc_t *pmcs, int count) { pfarg_pmr_t *pmrs; int errno_save; int i, ret; size_t sz; sz = count * sizeof(pfarg_pmr_t); if (!pmcs) return pfm_write(fd, 0, PFM_RW_PMC, NULL, sz); pmrs = calloc(count, sizeof(*pmrs)); if (!pmrs) { errno = ENOMEM; return -1; } for (i=0 ; i < count; i++) { pmrs[i].reg_num = pmcs[i].reg_num; pmrs[i].reg_set = pmcs[i].reg_set; pmrs[i].reg_flags = pmcs[i].reg_flags; pmrs[i].reg_value = pmcs[i].reg_value; } ret = pfm_write(fd, 0, PFM_RW_PMC, pmrs, sz); errno_save = errno; free(pmrs); errno = errno_save; return ret; } static int pfm_write_pmds_2v3(int fd, pfarg_pmd_t *pmds, int count) { pfarg_pmd_attr_t *pmas; size_t sz; int errno_save; int i, ret; sz = count * sizeof(*pmas); if (!pmds) return pfm_write(fd, 0, PFM_RW_PMD, NULL, sz); pmas = calloc(count, sizeof(*pmas)); if (!pmas) { errno = ENOMEM; return -1; } for (i=0 ; i < count; i++) { pmas[i].reg_num = pmds[i].reg_num; pmas[i].reg_set = pmds[i].reg_set; pmas[i].reg_flags = pmds[i].reg_flags; pmas[i].reg_value = pmds[i].reg_value; pmas[i].reg_long_reset = pmds[i].reg_long_reset; pmas[i].reg_short_reset = pmds[i].reg_short_reset; /* skip last_value not used on write */ pmas[i].reg_ovfl_swcnt = pmds[i].reg_ovfl_switch_cnt; memcpy(pmas[i].reg_smpl_pmds, pmds[i].reg_smpl_pmds, sizeof(pmds[i].reg_smpl_pmds)); memcpy(pmas[i].reg_reset_pmds, pmds[i].reg_reset_pmds, sizeof(pmds[i].reg_reset_pmds)); pmas[i].reg_smpl_eventid = pmds[i].reg_smpl_eventid; pmas[i].reg_random_mask = pmds[i].reg_random_mask; } ret = pfm_write(fd, 0, PFM_RW_PMD_ATTR, pmas, sz); errno_save = errno; free(pmas); errno = errno_save; return ret; } static int pfm_read_pmds_2v3(int fd, pfarg_pmd_t *pmds, int count) { pfarg_pmd_attr_t *pmas; int errno_save; int i, ret; size_t sz; sz = count * sizeof(*pmas); if (!pmds) return pfm_write(fd, 0, PFM_RW_PMD, NULL, sz); pmas = calloc(count, sizeof(*pmas)); if (!pmas) { errno = ENOMEM; return -1; } for (i=0 ; i < count; i++) { pmas[i].reg_num = pmds[i].reg_num; pmas[i].reg_set = pmds[i].reg_set; pmas[i].reg_flags = pmds[i].reg_flags; pmas[i].reg_value = pmds[i].reg_value; } ret = pfm_read(fd, 0, PFM_RW_PMD_ATTR, pmas, sz); errno_save = errno; for (i=0 ; i < count; i++) { pmds[i].reg_value = pmas[i].reg_value; pmds[i].reg_long_reset = pmas[i].reg_long_reset; pmds[i].reg_short_reset = pmas[i].reg_short_reset; pmds[i].reg_last_reset_val = pmas[i].reg_last_value; pmds[i].reg_ovfl_switch_cnt = pmas[i].reg_ovfl_swcnt; /* skip reg_smpl_pmds */ /* skip reg_reset_pmds */ /* skip reg_smpl_eventid */ /* skip reg_random_mask */ } free(pmas); errno = errno_save; return ret; } static int pfm_load_context_2v3(int fd, pfarg_load_t *load) { if (!load) { errno = EINVAL; return -1; } return pfm_attach(fd, 0, load->load_pid); } static int pfm_start_2v3(int fd, pfarg_start_t *start) { if (start) { __pfm_vbprintf("pfarg_start_t not supported in v3.x\n"); errno = EINVAL; return -1; } return pfm_set_state(fd, 0, PFM_ST_START); } static int pfm_stop_2v3(int fd) { return pfm_set_state(fd, 0, PFM_ST_STOP); } static int pfm_restart_2v3(int fd) { return pfm_set_state(fd, 0, PFM_ST_RESTART); } static int pfm_create_evtsets_2v3(int fd, pfarg_setdesc_t *setd, int count) { /* set_desc an setdesc are identical so we can cast */ return pfm_create_sets(fd, 0, (pfarg_set_desc_t *)setd, count * sizeof(pfarg_setdesc_t)); } static int pfm_delete_evtsets_2v3(int fd, pfarg_setdesc_t *setd, int count) { __pfm_vbprintf("pfm_delete_evtsets not supported in v3.x\n"); errno = EINVAL; return -1; } static int pfm_getinfo_evtsets_2v3(int fd, pfarg_setinfo_t *info, int count) { pfarg_sinfo_t cinfo; pfarg_set_info_t *sif; int fdx, i, ret, errno_save; if (!info) { errno = EFAULT; return -1; } /* * initialize bitmask to all available and defer checking * until kernel. That means libpfm must be misled but we * have no other way of fixing this */ memset(&cinfo, -1, sizeof(cinfo)); /* * XXX: relies on the fact that cinfo is independent * of the session type (which is wrong in the future) */ fdx = pfm_create(0, &cinfo); if (fdx > -1) close(fdx); sif = calloc(count, sizeof(*sif)); if (!sif) { errno = ENOMEM; return -1; } for (i=0 ; i < count; i++) sif[i].set_id = info[i].set_id; ret = pfm_getinfo_sets(fd, 0, sif, count * sizeof(pfarg_set_info_t)); errno_save = errno; if (ret) goto skip; for (i=0 ; i < count; i++) { info[i].set_flags = 0; memcpy(info[i].set_ovfl_pmds, sif[i].set_ovfl_pmds, sizeof(info[i].set_ovfl_pmds)); info[i].set_runs = sif[i].set_runs; info[i].set_timeout = sif[i].set_timeout; info[i].set_act_duration = sif[i].set_duration; memcpy(info[i].set_avail_pmcs, cinfo.sif_avail_pmcs, sizeof(info[i].set_avail_pmcs)); memcpy(info[i].set_avail_pmds, cinfo.sif_avail_pmds, sizeof(info[i].set_avail_pmds)); } skip: free(sif); errno = errno_save; return ret; } static int pfm_unload_context_2v3(int fd) { return pfm_attach(fd, 0, PFM_NO_TARGET); } #else /* PFMLIB_OLD_PFMV2 */ static int pfm_create_context_2v3(pfarg_ctx_t *ctx, char *name, void *smpl_arg, size_t smpl_size) { return -1; } static int pfm_write_pmcs_2v3(int fd, pfarg_pmc_t *pmcs, int count) { return -1; } static int pfm_write_pmds_2v3(int fd, pfarg_pmd_t *pmds, int count) { return -1; } static int pfm_read_pmds_2v3(int fd, pfarg_pmd_t *pmds, int count) { return -1; } static int pfm_load_context_2v3(int fd, pfarg_load_t *load) { return -1; } static int pfm_start_2v3(int fd, pfarg_start_t *start) { return -1; } static int pfm_stop_2v3(int fd) { return -1; } static int pfm_restart_2v3(int fd) { return -1; } static int pfm_create_evtsets_2v3(int fd, pfarg_setdesc_t *setd, int count) { return -1; } static int pfm_delete_evtsets_2v3(int fd, pfarg_setdesc_t *setd, int count) { return -1; } static int pfm_getinfo_evtsets_2v3(int fd, pfarg_setinfo_t *info, int count) { return -1; } static int pfm_unload_context_2v3(int fd) { return -1; } #endif /* PFMLIB_OLD_PFMV2 */ int pfm_load_context(int fd, pfarg_load_t *load) { if (_pfmlib_major_version < 3) return (int)syscall(PFM_pfm_load_context, fd, load); return pfm_load_context_2v3(fd, load); } int pfm_start(int fd, pfarg_start_t *start) { if (_pfmlib_major_version < 3) return (int)syscall(PFM_pfm_start, fd, start); return pfm_start_2v3(fd, start); } int pfm_stop(int fd) { if (_pfmlib_major_version < 3) return (int)syscall(PFM_pfm_stop, fd); return pfm_stop_2v3(fd); } int pfm_restart(int fd) { if (_pfmlib_major_version < 3) return (int)syscall(PFM_pfm_restart, fd); return pfm_restart_2v3(fd); } int pfm_create_evtsets(int fd, pfarg_setdesc_t *setd, int count) { if (_pfmlib_major_version < 3) return (int)syscall(PFM_pfm_create_evtsets, fd, setd, count); return pfm_create_evtsets_2v3(fd, setd, count); } int pfm_delete_evtsets(int fd, pfarg_setdesc_t *setd, int count) { if (_pfmlib_major_version < 3) return (int)syscall(PFM_pfm_delete_evtsets, fd, setd, count); return pfm_delete_evtsets_2v3(fd, setd, count); } int pfm_getinfo_evtsets(int fd, pfarg_setinfo_t *info, int count) { if (_pfmlib_major_version < 3) return (int)syscall(PFM_pfm_getinfo_evtsets, fd, info, count); return pfm_getinfo_evtsets_2v3(fd, info, count); } int pfm_unload_context(int fd) { if (_pfmlib_major_version < 3) return (int)syscall(PFM_pfm_unload_context, fd); return pfm_unload_context_2v3(fd); } int pfm_create_context(pfarg_ctx_t *ctx, char *name, void *smpl_arg, size_t smpl_size) { if (_pfmlib_major_version < 3) { /* * In perfmon v2.2, the pfm_create_context() call had a * different return value. It used to return errno, in v2.3 * it returns the file descriptor. */ if (_pfmlib_minor_version < 3) { int r; pfarg_ctx22_t ctx22; /* transfer the v2.3 contents to v2.2 for sys call */ memset (&ctx22, 0, sizeof(ctx22)); if (name != NULL) { memcpy (ctx22.ctx_smpl_buf_id, name, 16); } ctx22.ctx_flags = ctx->ctx_flags; /* ctx22.ctx_fd returned */ /* ctx22.ctx_smpl_buf_size returned */ memcpy (ctx22.ctx_reserved3, &ctx->ctx_reserved1, 64); r = syscall (PFM_pfm_create_context, &ctx22, smpl_arg, smpl_size); /* transfer the v2.2 contents back to v2.3 */ ctx->ctx_flags = ctx22.ctx_flags; memcpy (&ctx->ctx_reserved1, ctx22.ctx_reserved3, 64); return (r < 0 ? r : ctx22.ctx_fd); } else { return (int)syscall(PFM_pfm_create_context, ctx, name, smpl_arg, smpl_size); } } return pfm_create_context_2v3(ctx, name, smpl_arg, smpl_size); } int pfm_write_pmcs(int fd, pfarg_pmc_t *pmcs, int count) { if (_pfmlib_major_version < 3) return (int)syscall(PFM_pfm_write_pmcs, fd, pmcs, count); return pfm_write_pmcs_2v3(fd, pmcs, count); } int pfm_write_pmds(int fd, pfarg_pmd_t *pmds, int count) { if (_pfmlib_major_version < 3) return (int)syscall(PFM_pfm_write_pmds, fd, pmds, count); return pfm_write_pmds_2v3(fd, pmds, count); } int pfm_read_pmds(int fd, pfarg_pmd_t *pmds, int count) { if (_pfmlib_major_version < 3) return (int)syscall(PFM_pfm_read_pmds, fd, pmds, count); return pfm_read_pmds_2v3(fd, pmds, count); } #ifdef __ia64__ #define __PFMLIB_OS_COMPILE #include /* * this is the old perfmon2 interface, maintained for backward * compatibility reasons with older applications. This is for IA-64 ONLY. */ int perfmonctl(int fd, int cmd, void *arg, int narg) { return syscall(__NR_perfmonctl, fd, cmd, arg, narg); } #endif /* __ia64__ */ papi-5.5.1/src/libpfm-3.y/lib/ultra3i_events.h0000644000307100002310000002600713013651450021015 0ustar yarkhangraduatestatic pme_sparc_entry_t ultra3i_pe[] = { /* These two must always be first. */ { .pme_name = "Cycle_cnt", .pme_desc = "Accumulated cycles", .pme_ctrl = PME_CTRL_S0 | PME_CTRL_S1, .pme_val = 0x0, }, { .pme_name = "Instr_cnt", .pme_desc = "Number of instructions completed", .pme_ctrl = PME_CTRL_S0 | PME_CTRL_S1, .pme_val = 0x1, }, /* PIC0 events common to all UltraSPARC processors */ { .pme_name = "Dispatch0_IC_miss", .pme_desc = "I-buffer is empty from I-Cache miss", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x2, }, { .pme_name = "IC_ref", .pme_desc = "I-cache refrences", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x8, }, { .pme_name = "DC_rd", .pme_desc = "D-cache read references (including accesses that subsequently trap)", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x9, }, { .pme_name = "DC_wr", .pme_desc = "D-cache store accesses (including cacheable stores that subsequently trap)", .pme_ctrl = PME_CTRL_S0, .pme_val = 0xa, }, { .pme_name = "EC_ref", .pme_desc = "E-cache references", .pme_ctrl = PME_CTRL_S0, .pme_val = 0xc, }, { .pme_name = "EC_snoop_inv", .pme_desc = "L2-cache invalidates generated from a snoop by a remote processor", .pme_ctrl = PME_CTRL_S0, .pme_val = 0xe, }, /* PIC1 events common to all UltraSPARC processors */ { .pme_name = "Dispatch0_mispred", .pme_desc = "I-buffer is empty from Branch misprediction", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x2, }, { .pme_name = "EC_wb", .pme_desc = "Dirty sub-blocks that produce writebacks due to L2-cache miss events", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xd, }, { .pme_name = "EC_snoop_cb", .pme_desc = "L2-cache copybacks generated from a snoop by a remote processor", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xe, }, /* PIC0 events common to all UltraSPARC-III/III+/IIIi processors */ { .pme_name = "Dispatch0_br_target", .pme_desc = "I-buffer is empty due to a branch target address calculation", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x3, }, { .pme_name = "Dispatch0_2nd_br", .pme_desc = "Stall cycles due to having two branch instructions line-up in one 4-instruction group causing the second branch in the group to be re-fetched, delaying it's entrance into the I-buffer", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x4, }, { .pme_name = "Rstall_storeQ", .pme_desc = "R-stage stall for a store instruction which is the next instruction to be executed, but it stailled due to the store queue being full", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x5, }, { .pme_name = "Rstall_IU_use", .pme_desc = "R-stage stall for an event that the next instruction to be executed depends on the result of a preceeding integer instruction in the pipeline that is not yet available", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x6, }, { .pme_name = "EC_write_hit_RTO", .pme_desc = "W-cache exclusive requests that hit L2-cache in S, O, or Os state and thus, do a read-to-own bus transaction", .pme_ctrl = PME_CTRL_S0, .pme_val = 0xd, }, { .pme_name = "EC_rd_miss", .pme_desc = "L2-cache miss events (including atomics) from D-cache events", .pme_ctrl = PME_CTRL_S0, .pme_val = 0xf, }, { .pme_name = "PC_port0_rd", .pme_desc = "P-cache cacheable FP loads to the first port (general purpose load path to D-cache and P-cache via MS pipeline)", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x10, }, { .pme_name = "SI_snoop", .pme_desc = "Counts snoops from remote processor(s) including RTS, RTSR, RTO, RTOR, RS, RSR, RTSM, and WS", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x11, }, { .pme_name = "SI_ciq_flow", .pme_desc = "Counts system clock cycles when the flow control (PauseOut) signal is asserted", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x12, }, { .pme_name = "SI_owned", .pme_desc = "Counts events where owned_in is asserted on bus requests from the local processor", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x13, }, { .pme_name = "SW_count0", .pme_desc = "Counts software-generated occurrences of 'sethi %hi(0xfc000), %g0' instruction", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x14, }, { .pme_name = "IU_Stat_Br_miss_taken", .pme_desc = "Retired branches that were predicted to be taken, but in fact were not taken", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x15, }, { .pme_name = "IU_Stat_Br_Count_taken", .pme_desc = "Retired taken branches", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x16, }, { .pme_name = "Dispatch0_rs_mispred", .pme_desc = "I-buffer is empty due to a Return Address Stack misprediction", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x4, }, { .pme_name = "FA_pipe_completion", .pme_desc = "Instructions that complete execution on the FPG ALU pipelines", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x18, }, /* PIC1 events common to all UltraSPARC-III/III+/IIIi processors */ { .pme_name = "IC_miss_cancelled", .pme_desc = "I-cache misses cancelled due to mis-speculation, recycle, or other events", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x3, }, { .pme_name = "Re_FPU_bypass", .pme_desc = "Stall due to recirculation when an FPU bypass condition that does not have a direct bypass path occurs", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x5, }, { .pme_name = "Re_DC_miss", .pme_desc = "Stall due to loads that miss D-cache and get recirculated", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x6, }, { .pme_name = "Re_EC_miss", .pme_desc = "Stall due to loads that miss L2-cache and get recirculated", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x7, }, { .pme_name = "IC_miss", .pme_desc = "I-cache misses, including fetches from mis-speculated execution paths which are later cancelled", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x8, }, { .pme_name = "DC_rd_miss", .pme_desc = "Recirculated loads that miss the D-cache", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x9, }, { .pme_name = "DC_wr_miss", .pme_desc = "D-cache store accesses that miss D-cache", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xa, }, { .pme_name = "Rstall_FP_use", .pme_desc = "R-stage stall for an event that the next instruction to be executed depends on the result of a preceeding floating-point instruction in the pipeline that is not yet available", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xb, }, { .pme_name = "EC_misses", .pme_desc = "E-cache misses", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xc, }, { .pme_name = "EC_ic_miss", .pme_desc = "L2-cache read misses from I-cache requests", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xf, }, { .pme_name = "Re_PC_miss", .pme_desc = "Stall due to recirculation when a prefetch cache miss occurs on a prefetch predicted second load", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x10, }, { .pme_name = "ITLB_miss", .pme_desc = "I-TLB miss traps taken", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x11, }, { .pme_name = "DTLB_miss", .pme_desc = "Memory reference instructions which trap due to D-TLB miss", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x12, }, { .pme_name = "WC_miss", .pme_desc = "W-cache misses", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x13, }, { .pme_name = "WC_snoop_cb", .pme_desc = "W-cache copybacks generated by a snoop from a remote processor", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x14, }, { .pme_name = "WC_scrubbed", .pme_desc = "W-cache hits to clean lines", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x15, }, { .pme_name = "WC_wb_wo_read", .pme_desc = "W-cache writebacks not requiring a read", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x16, }, { .pme_name = "PC_soft_hit", .pme_desc = "FP loads that hit a P-cache line that was prefetched by a software-prefetch instruction", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x18, }, { .pme_name = "PC_snoop_inv", .pme_desc = "P-cache invalidates that were generated by a snoop from a remote processor and stores by a local processor", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x19, }, { .pme_name = "PC_hard_hit", .pme_desc = "FP loads that hit a P-cache line that was prefetched by a hardware prefetch", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x1a, }, { .pme_name = "PC_port1_rd", .pme_desc = "P-cache cacheable FP loads to the second port (memory and out-of-pipeline instruction execution loads via the A0 and A1 pipelines)", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x1b, }, { .pme_name = "SW_count1", .pme_desc = "Counts software-generated occurrences of 'sethi %hi(0xfc000), %g0' instruction", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x1c, }, { .pme_name = "IU_Stat_Br_miss_untaken", .pme_desc = "Retired branches that were predicted to be untaken, but in fact were taken", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x1d, }, { .pme_name = "IU_Stat_Br_Count_untaken", .pme_desc = "Retired untaken branches", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x1e, }, { .pme_name = "PC_MS_miss", .pme_desc = "FP loads through the MS pipeline that miss P-cache", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x1f, }, { .pme_name = "Re_RAW_miss", .pme_desc = "Stall due to recirculation when there is a load in the E-stage which has a non-bypassable read-after-write hazard with an earlier store instruction", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x26, }, { .pme_name = "FM_pipe_completion", .pme_desc = "Instructions that complete execution on the FPG Multiply pipelines", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x27, }, /* PIC0 memory controller events specific to UltraSPARC-IIIi processors */ { .pme_name = "MC_read_dispatched", .pme_desc = "DDR 64-byte reads dispatched by the MIU", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x20, }, { .pme_name = "MC_write_dispatched", .pme_desc = "DDR 64-byte writes dispatched by the MIU", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x21, }, { .pme_name = "MC_read_returned_to_JBU", .pme_desc = "64-byte reads that return data to JBU", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x22, }, { .pme_name = "MC_msl_busy_stall", .pme_desc = "Stall cycles due to msl_busy", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x23, }, { .pme_name = "MC_mdb_overflow_stall", .pme_desc = "Stall cycles due to potential memory data buffer overflow", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x24, }, { .pme_name = "MC_miu_spec_request", .pme_desc = "Speculative requests accepted by MIU", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x25, }, /* PIC1 memory controller events specific to UltraSPARC-IIIi processors */ { .pme_name = "MC_reads", .pme_desc = "64-byte reads by the MSL", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x20, }, { .pme_name = "MC_writes", .pme_desc = "64-byte writes by the MSL", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x21, }, { .pme_name = "MC_page_close_stall", .pme_desc = "DDR page conflicts", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x22, }, /* PIC1 events specific to UltraSPARC-III+/IIIi */ { .pme_name = "Re_DC_missovhd", .pme_desc = "Used to measure D-cache stall counts seperatedly for L2-cache hits and misses. This counter is used with the recirculation and cache access events to seperately calculate the D-cache loads that hit and miss the L2-cache", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x4, }, }; #define PME_ULTRA3I_EVENT_COUNT (sizeof(ultra3i_pe)/sizeof(pme_sparc_entry_t)) papi-5.5.1/src/libpfm-3.y/lib/niagara1_events.h0000644000307100002310000000226413013651450021114 0ustar yarkhangraduatestatic pme_sparc_entry_t niagara1_pe[] = { /* PIC1 Niagara-1 events */ { .pme_name = "Instr_cnt", .pme_desc = "Number of instructions completed", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x0, }, /* PIC0 Niagara-1 events */ { .pme_name = "SB_full", .pme_desc = "Store-buffer full", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x0, }, { .pme_name = "FP_instr_cnt", .pme_desc = "FPU instructions", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x1, }, { .pme_name = "IC_miss", .pme_desc = "I-cache miss", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x2, }, { .pme_name = "DC_miss", .pme_desc = "D-cache miss", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x3, }, { .pme_name = "ITLB_miss", .pme_desc = "I-TLB miss", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x4, }, { .pme_name = "DTLB_miss", .pme_desc = "D-TLB miss", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x5, }, { .pme_name = "L2_imiss", .pme_desc = "E-cache instruction fetch miss", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x6, }, { .pme_name = "L2_dmiss_ld", .pme_desc = "E-cache data load miss", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x7, }, }; #define PME_NIAGARA1_EVENT_COUNT (sizeof(niagara1_pe)/sizeof(pme_sparc_entry_t)) papi-5.5.1/src/libpfm-3.y/lib/pfmlib_intel_nhm_priv.h0000644000307100002310000000602613013651450022413 0ustar yarkhangraduate/* * Copyright (c) 2008 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #ifndef __PFMLIB_NHM_PRIV_H__ #define __PFMLIB_NHM_PRIV_H__ #define PFMLIB_NHM_MAX_UMASK 32 typedef struct { char *pme_uname; /* unit mask name */ char *pme_udesc; /* event/umask description */ unsigned int pme_cntmsk; /* counter mask */ unsigned int pme_ucode; /* unit mask code */ unsigned int pme_uflags; /* unit mask flags */ unsigned int pme_umodel; /* CPU model for this umask */ } pme_nhm_umask_t; typedef struct { char *pme_name; /* event name */ char *pme_desc; /* event description */ unsigned int pme_code; /* event code */ unsigned int pme_cntmsk; /* counter mask */ unsigned int pme_numasks; /* number of umasks */ unsigned int pme_flags; /* flags */ pme_nhm_umask_t pme_umasks[PFMLIB_NHM_MAX_UMASK]; /* umask desc */ } pme_nhm_entry_t; /* * pme_flags value (event and unit mask) */ /* event or unit-mask level constraints */ #define PFMLIB_NHM_UMASK_NCOMBO 0x001 /* unit mask cannot be combined (default: combination ok) */ #define PFMLIB_NHM_FIXED0 0x002 /* event supported by FIXED_CTR0, can work on generic counters */ #define PFMLIB_NHM_FIXED1 0x004 /* event supported by FIXED_CTR1, can work on generic counters */ #define PFMLIB_NHM_FIXED2_ONLY 0x008 /* only works in FIXED_CTR2 */ #define PFMLIB_NHM_OFFCORE_RSP0 0x010 /* requires OFFCORE_RSP0 register */ #define PFMLIB_NHM_PMC01 0x020 /* works only on IA32_PMC0 or IA32_PMC1 */ #define PFMLIB_NHM_PEBS 0x040 /* support PEBS (precise event) */ #define PFMLIB_NHM_UNC 0x080 /* uncore event */ #define PFMLIB_NHM_UNC_FIXED 0x100 /* uncore fixed event */ #define PFMLIB_NHM_OFFCORE_RSP1 0x200 /* requires OFFCORE_RSP1 register */ #define PFMLIB_NHM_PMC0 0x400 /* works only on IA32_PMC0 */ #define PFMLIB_NHM_EX 0x800 /* has Nehalem-EX specific unit masks */ #endif /* __PFMLIB_NHM_PRIV_H__ */ papi-5.5.1/src/libpfm-3.y/lib/pfmlib_cell.c0000644000307100002310000004354513013651450020317 0ustar yarkhangraduate/* * pfmlib_cell.c : support for the Cell PMU family * * Copyright (c) 2007 TOSHIBA CORPORATION based on code from * Copyright (c) 2001-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* public headers */ #include /* private headers */ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_cell_priv.h" /* architecture private */ #include "cell_events.h" /* PMU private */ #define SIGNAL_TYPE_CYCLES 0 #define PM_COUNTER_CTRL_CYLES 0x42C00000U #define PFM_CELL_NUM_PMCS 24 #define PFM_CELL_EVENT_MIN 1 #define PFM_CELL_EVENT_MAX 8 #define PMX_MIN_NUM 1 #define PMX_MAX_NUM 8 #define PFM_CELL_16BIT_CNTR_EVENT_MAX 8 #define PFM_CELL_32BIT_CNTR_EVENT_MAX 4 #define COMMON_REG_NUMS 8 #define ENABLE_WORD0 0 #define ENABLE_WORD1 1 #define ENABLE_WORD2 2 #define PFM_CELL_GRP_CONTROL_REG_GRP0_BIT 30 #define PFM_CELL_GRP_CONTROL_REG_GRP1_BIT 28 #define PFM_CELL_BASE_WORD_UNIT_FIELD_BIT 24 #define PFM_CELL_WORD_UNIT_FIELD_WIDTH 2 #define PFM_CELL_MAX_WORD_NUMBER 3 #define PFM_CELL_COUNTER_CONTROL_GRP1 0x80000000U #define PFM_CELL_DEFAULT_TRIGGER_EVENT_UNIT 0x00555500U #define PFM_CELL_PM_CONTROL_16BIT_CNTR_MASK 0x01E00000U #define PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_PROBLEM 0x00080000U #define PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_SUPERVISOR 0x00000000U #define PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_HYPERVISOR 0x00040000U #define PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_ALL 0x000C0000U #define PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_MASK 0x000C0000U #define ONLY_WORD(x) \ ((x == WORD_0_ONLY)||(x == WORD_2_ONLY)) ? x : 0 struct pfm_cell_signal_group_desc { unsigned int signal_type; unsigned int word_type; unsigned long long word; unsigned long long freq; unsigned int subunit; }; #define swap_int(num1, num2) do { \ int tmp = num1; \ num1 = num2; \ num2 = tmp; \ } while(0) static int pfm_cell_detect(void) { int ret; char buffer[128]; ret = __pfm_getcpuinfo_attr("cpu", buffer, sizeof(buffer)); if (ret == -1) { return PFMLIB_ERR_NOTSUPP; } if (strcmp(buffer, "Cell Broadband Engine, altivec supported")) { return PFMLIB_ERR_NOTSUPP; } return PFMLIB_SUCCESS; } static int get_pmx_offset(int pmx_num, unsigned int *pmx_ctrl_bits) { /* pmx_num==0 -> not specified * pmx_num==1 -> pm0 * : * pmx_num==8 -> pm7 */ int i = 0; int offset; if ((pmx_num >= PMX_MIN_NUM) && (pmx_num <= PMX_MAX_NUM)) { /* offset is specified */ offset = (pmx_num - 1); if ((~*pmx_ctrl_bits >> offset) & 0x1) { *pmx_ctrl_bits |= (0x1 << offset); return offset; } else { /* offset is used */ return PFMLIB_ERR_INVAL; } } else if (pmx_num == 0){ /* offset is not specified */ while (((*pmx_ctrl_bits >> i) & 0x1) && (i < PMX_MAX_NUM)) { i++; } *pmx_ctrl_bits |= (0x1 << i); return i; } /* pmx_num is invalid */ return PFMLIB_ERR_INVAL; } static unsigned long long search_enable_word(int word) { unsigned long long count = 0; while ((~word) & 0x1) { count++; word >>= 1; } return count; } static int get_count_bit(unsigned int type) { int count = 0; while(type) { if (type & 1) { count++; } type >>= 1; } return count; } static int get_debug_bus_word(struct pfm_cell_signal_group_desc *group0, struct pfm_cell_signal_group_desc *group1) { unsigned int word_type0, word_type1; /* search enable word */ word_type0 = group0->word_type; word_type1 = group1->word_type; if (group1->signal_type == NONE_SIGNAL) { group0->word = search_enable_word(word_type0); goto found; } /* swap */ if ((get_count_bit(word_type0) > get_count_bit(word_type1)) || (group0->freq == PFM_CELL_PME_FREQ_SPU)) { swap_int(group0->signal_type, group1->signal_type); swap_int(group0->freq, group1->freq); swap_int(group0->word_type, group1->word_type); swap_int(group0->subunit, group1->subunit); swap_int(word_type0, word_type1); } if ((ONLY_WORD(word_type0) != 0) && (word_type0 == word_type1)) { return PFMLIB_ERR_INVAL; } if (ONLY_WORD(word_type0)) { group0->word = search_enable_word(ONLY_WORD(word_type0)); word_type1 &= ~(1UL << (group0->word)); group1->word = search_enable_word(word_type1); } else if (ONLY_WORD(word_type1)) { group1->word = search_enable_word(ONLY_WORD(word_type1)); word_type0 &= ~(1UL << (group1->word)); group0->word = search_enable_word(word_type0); } else { group0->word = ENABLE_WORD0; if (word_type1 == WORD_0_AND_1) { group1->word = ENABLE_WORD1; } else if(word_type1 == WORD_0_AND_2) { group1->word = ENABLE_WORD2; } else { return PFMLIB_ERR_INVAL; } } found: return PFMLIB_SUCCESS; } static unsigned int get_signal_type(unsigned long long event_code) { return (event_code & 0x00000000FFFFFFFFULL) / 100; } static unsigned int get_signal_bit(unsigned long long event_code) { return (event_code & 0x00000000FFFFFFFFULL) % 100; } static int is_spe_signal_group(unsigned int signal_type) { if (41 <= signal_type && signal_type <= 56) { return 1; } else { return 0; } } static int check_signal_type(pfmlib_input_param_t *inp, pfmlib_cell_input_param_t *mod_in, struct pfm_cell_signal_group_desc *group0, struct pfm_cell_signal_group_desc *group1) { pfmlib_event_t *e; unsigned int event_cnt; int signal_cnt = 0; int i; int cycles_signal_cnt = 0; unsigned int signal_type, subunit; e = inp->pfp_events; event_cnt = inp->pfp_event_count; for(i = 0; i < event_cnt; i++) { signal_type = get_signal_type(cell_pe[e[i].event].pme_code); if ((signal_type == SIGNAL_SPU_TRIGGER) || (signal_type == SIGNAL_SPU_EVENT)) { continue; } if (signal_type == SIGNAL_TYPE_CYCLES) { cycles_signal_cnt = 1; continue; } subunit = 0; if (is_spe_signal_group(signal_type)) { subunit = mod_in->pfp_cell_counters[i].spe_subunit; } switch(signal_cnt) { case 0: group0->signal_type = signal_type; group0->word_type = cell_pe[e[i].event].pme_enable_word; group0->freq = cell_pe[e[i].event].pme_freq; group0->subunit = subunit; signal_cnt++; break; case 1: if ((group0->signal_type != signal_type) || (is_spe_signal_group(signal_type) && group0->subunit != subunit)) { group1->signal_type = signal_type; group1->word_type = cell_pe[e[i].event].pme_enable_word; group1->freq = cell_pe[e[i].event].pme_freq; group1->subunit = subunit; signal_cnt++; } break; case 2: if ((group0->signal_type != signal_type) && (group1->signal_type != signal_type)) { DPRINT("signal count is invalid\n"); return PFMLIB_ERR_INVAL; } break; default: DPRINT("signal count is invalid\n"); return PFMLIB_ERR_INVAL; } } return (signal_cnt + cycles_signal_cnt); } /* * The assignment between the privilege leve options * and ppu-count-mode field in pm_control register. * * option ppu count mode(pm_control) * --------------------------------- * -u(-3) 0b10 : Problem mode * -k(-0) 0b00 : Supervisor mode * -1 0b00 : Supervisor mode * -2 0b01 : Hypervisor mode * two options 0b11 : Any mode * * Note : Hypervisor-mode and Any-mode don't work on PS3. * */ static unsigned int get_ppu_count_mode(unsigned int plm) { unsigned int ppu_count_mode = 0; switch (plm) { case PFM_PLM0: case PFM_PLM1: ppu_count_mode = PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_SUPERVISOR; break; case PFM_PLM2: ppu_count_mode = PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_HYPERVISOR; break; case PFM_PLM3: ppu_count_mode = PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_PROBLEM; break; default : ppu_count_mode = PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_ALL; break; } return ppu_count_mode; } static int pfm_cell_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_cell_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfmlib_event_t *e; pfmlib_reg_t *pc, *pd; unsigned int event_cnt; unsigned int signal_cnt = 0, pmcs_cnt = 0; unsigned int signal_type; unsigned long long signal_bit; struct pfm_cell_signal_group_desc group[2]; int pmx_offset = 0; int i, ret; int input_control, polarity, count_cycle, count_enable; unsigned long long subunit; int shift0, shift1; unsigned int pmx_ctrl_bits; int max_event_cnt = PFM_CELL_32BIT_CNTR_EVENT_MAX; count_enable = 1; group[0].signal_type = group[1].signal_type = NONE_SIGNAL; group[0].word = group[1].word = 0L; group[0].freq = group[1].freq = 0L; group[0].subunit = group[1].subunit = 0; group[0].word_type = group[1].word_type = WORD_NONE; event_cnt = inp->pfp_event_count; e = inp->pfp_events; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; /* check event_cnt */ if (mod_in->control & PFM_CELL_PM_CONTROL_16BIT_CNTR_MASK) max_event_cnt = PFM_CELL_16BIT_CNTR_EVENT_MAX; if (event_cnt < PFM_CELL_EVENT_MIN) return PFMLIB_ERR_NOTFOUND; if (event_cnt > max_event_cnt) return PFMLIB_ERR_TOOMANY; /* check signal type */ signal_cnt = check_signal_type(inp, mod_in, &group[0], &group[1]); if (signal_cnt == PFMLIB_ERR_INVAL) return PFMLIB_ERR_NOASSIGN; /* decide debug_bus word */ if (signal_cnt != 0 && group[0].signal_type != NONE_SIGNAL) { ret = get_debug_bus_word(&group[0], &group[1]); if (ret != PFMLIB_SUCCESS) return PFMLIB_ERR_NOASSIGN; } /* common register setting */ pc[pmcs_cnt].reg_num = REG_GROUP_CONTROL; if (signal_cnt == 1) { pc[pmcs_cnt].reg_value = group[0].word << PFM_CELL_GRP_CONTROL_REG_GRP0_BIT; } else if (signal_cnt == 2) { pc[pmcs_cnt].reg_value = (group[0].word << PFM_CELL_GRP_CONTROL_REG_GRP0_BIT) | (group[1].word << PFM_CELL_GRP_CONTROL_REG_GRP1_BIT); } pmcs_cnt++; pc[pmcs_cnt].reg_num = REG_DEBUG_BUS_CONTROL; if (signal_cnt == 1) { shift0 = PFM_CELL_BASE_WORD_UNIT_FIELD_BIT + ((PFM_CELL_MAX_WORD_NUMBER - group[0].word) * PFM_CELL_WORD_UNIT_FIELD_WIDTH); pc[pmcs_cnt].reg_value = group[0].freq << shift0; } else if (signal_cnt == 2) { shift0 = PFM_CELL_BASE_WORD_UNIT_FIELD_BIT + ((PFM_CELL_MAX_WORD_NUMBER - group[0].word) * PFM_CELL_WORD_UNIT_FIELD_WIDTH); shift1 = PFM_CELL_BASE_WORD_UNIT_FIELD_BIT + ((PFM_CELL_MAX_WORD_NUMBER - group[1].word) * PFM_CELL_WORD_UNIT_FIELD_WIDTH); pc[pmcs_cnt].reg_value = (group[0].freq << shift0) | (group[1].freq << shift1); } pc[pmcs_cnt].reg_value |= PFM_CELL_DEFAULT_TRIGGER_EVENT_UNIT; pmcs_cnt++; pc[pmcs_cnt].reg_num = REG_TRACE_ADDRESS; pc[pmcs_cnt].reg_value = 0; pmcs_cnt++; pc[pmcs_cnt].reg_num = REG_EXT_TRACE_TIMER; pc[pmcs_cnt].reg_value = 0; pmcs_cnt++; pc[pmcs_cnt].reg_num = REG_PM_STATUS; pc[pmcs_cnt].reg_value = 0; pmcs_cnt++; pc[pmcs_cnt].reg_num = REG_PM_CONTROL; pc[pmcs_cnt].reg_value = (mod_in->control & ~PFM_CELL_PM_CONTROL_PPU_CNTR_MODE_MASK) | get_ppu_count_mode(inp->pfp_dfl_plm); pmcs_cnt++; pc[pmcs_cnt].reg_num = REG_PM_INTERVAL; pc[pmcs_cnt].reg_value = mod_in->interval; pmcs_cnt++; pc[pmcs_cnt].reg_num = REG_PM_START_STOP; pc[pmcs_cnt].reg_value = mod_in->triggers; pmcs_cnt++; pmx_ctrl_bits = 0; /* pmX register setting */ for(i = 0; i < event_cnt; i++) { /* PMX_CONTROL */ pmx_offset = get_pmx_offset(mod_in->pfp_cell_counters[i].pmX_control_num, &pmx_ctrl_bits); if (pmx_offset == PFMLIB_ERR_INVAL) { DPRINT("pmX already used\n"); return PFMLIB_ERR_INVAL; } signal_type = get_signal_type(cell_pe[e[i].event].pme_code); if (signal_type == SIGNAL_TYPE_CYCLES) { pc[pmcs_cnt].reg_value = PM_COUNTER_CTRL_CYLES; pc[pmcs_cnt].reg_num = REG_PM0_CONTROL + pmx_offset; pmcs_cnt++; pc[pmcs_cnt].reg_value = cell_pe[e[i].event].pme_code; pc[pmcs_cnt].reg_num = REG_PM0_EVENT + pmx_offset; pmcs_cnt++; pd[i].reg_num = pmx_offset; pd[i].reg_value = 0; continue; } switch(cell_pe[e[i].event].pme_type) { case COUNT_TYPE_BOTH_TYPE: case COUNT_TYPE_CUMULATIVE_LEN: case COUNT_TYPE_MULTI_CYCLE: case COUNT_TYPE_SINGLE_CYCLE: count_cycle = 1; break; case COUNT_TYPE_OCCURRENCE: count_cycle = 0; break; default: return PFMLIB_ERR_INVAL; } signal_bit = get_signal_bit(cell_pe[e[i].event].pme_code); polarity = mod_in->pfp_cell_counters[i].polarity; input_control = mod_in->pfp_cell_counters[i].input_control; subunit = 0; if (is_spe_signal_group(signal_type)) { subunit = mod_in->pfp_cell_counters[i].spe_subunit; } pc[pmcs_cnt].reg_value = ( (signal_bit << (31 - 5)) | (input_control << (31 - 6)) | (polarity << (31 - 7)) | (count_cycle << (31 - 8)) | (count_enable << (31 - 9)) ); pc[pmcs_cnt].reg_num = REG_PM0_CONTROL + pmx_offset; if (signal_type == group[1].signal_type && subunit == group[1].subunit) { pc[pmcs_cnt].reg_value |= PFM_CELL_COUNTER_CONTROL_GRP1; } pmcs_cnt++; /* PMX_EVENT */ pc[pmcs_cnt].reg_num = REG_PM0_EVENT + pmx_offset; /* debug bus word setting */ if (signal_type == group[0].signal_type && subunit == group[0].subunit) { pc[pmcs_cnt].reg_value = (cell_pe[e[i].event].pme_code | (group[0].word << 48) | (subunit << 32)); } else if (signal_type == group[1].signal_type && subunit == group[1].subunit) { pc[pmcs_cnt].reg_value = (cell_pe[e[i].event].pme_code | (group[1].word << 48) | (subunit << 32)); } else if ((signal_type == SIGNAL_SPU_TRIGGER) || (signal_type == SIGNAL_SPU_EVENT)) { pc[pmcs_cnt].reg_value = cell_pe[e[i].event].pme_code | (subunit << 32); } else { return PFMLIB_ERR_INVAL; } pmcs_cnt++; /* pmd setting */ pd[i].reg_num = pmx_offset; pd[i].reg_value = 0; } outp->pfp_pmc_count = pmcs_cnt; outp->pfp_pmd_count = event_cnt; return PFMLIB_SUCCESS; } static int pfm_cell_dispatch_events(pfmlib_input_param_t *inp, void *model_in, pfmlib_output_param_t *outp, void *model_out) { pfmlib_cell_input_param_t *mod_in = (pfmlib_cell_input_param_t *)model_in; pfmlib_cell_input_param_t default_model_in; int i; if (model_in) { mod_in = (pfmlib_cell_input_param_t *)model_in; } else { mod_in = &default_model_in; mod_in->control = 0x80000000; mod_in->interval = 0; mod_in->triggers = 0; for (i = 0; i < PMU_CELL_NUM_COUNTERS; i++) { mod_in->pfp_cell_counters[i].pmX_control_num = 0; mod_in->pfp_cell_counters[i].spe_subunit = 0; mod_in->pfp_cell_counters[i].polarity = 1; mod_in->pfp_cell_counters[i].input_control = 0; mod_in->pfp_cell_counters[i].cnt_mask = 0; mod_in->pfp_cell_counters[i].flags = 0; } } return pfm_cell_dispatch_counters(inp, mod_in, outp); } static int pfm_cell_get_event_code(unsigned int i, unsigned int cnt, int *code) { // if (cnt != PFMLIB_CNT_FIRST && cnt > 2) { if (cnt != PFMLIB_CNT_FIRST && cnt > cell_support.num_cnt) { return PFMLIB_ERR_INVAL; } *code = cell_pe[i].pme_code; return PFMLIB_SUCCESS; } static void pfm_cell_get_event_counters(unsigned int j, pfmlib_regmask_t *counters) { unsigned int i; memset(counters, 0, sizeof(*counters)); for(i=0; i < PMU_CELL_NUM_COUNTERS; i++) { pfm_regmask_set(counters, i); } } static void pfm_cell_get_impl_pmcs(pfmlib_regmask_t *impl_pmcs) { unsigned int i; memset(impl_pmcs, 0, sizeof(*impl_pmcs)); for(i=0; i < PFM_CELL_NUM_PMCS; i++) { pfm_regmask_set(impl_pmcs, i); } } static void pfm_cell_get_impl_pmds(pfmlib_regmask_t *impl_pmds) { unsigned int i; memset(impl_pmds, 0, sizeof(*impl_pmds)); for(i=0; i < PMU_CELL_NUM_PERFCTR; i++) { pfm_regmask_set(impl_pmds, i); } } static void pfm_cell_get_impl_counters(pfmlib_regmask_t *impl_counters) { unsigned int i; for(i=0; i < PMU_CELL_NUM_COUNTERS; i++) { pfm_regmask_set(impl_counters, i); } } static char* pfm_cell_get_event_name(unsigned int i) { return cell_pe[i].pme_name; } static int pfm_cell_get_event_desc(unsigned int ev, char **str) { char *s; s = cell_pe[ev].pme_desc; if (s) { *str = strdup(s); } else { *str = NULL; } return PFMLIB_SUCCESS; } static int pfm_cell_get_cycle_event(pfmlib_event_t *e) { int i; for (i = 0; i < PME_CELL_EVENT_COUNT; i++) { if (!strcmp(cell_pe[i].pme_name, "CYCLES")) { e->event = i; return PFMLIB_SUCCESS; } } return PFMLIB_ERR_NOTFOUND; } int pfm_cell_spe_event(unsigned int event_index) { if (event_index >= PME_CELL_EVENT_COUNT) return 0; return is_spe_signal_group(get_signal_type(cell_pe[event_index].pme_code)); } pfm_pmu_support_t cell_support={ .pmu_name = "CELL", .pmu_type = PFMLIB_CELL_PMU, .pme_count = PME_CELL_EVENT_COUNT, .pmc_count = PFM_CELL_NUM_PMCS, .pmd_count = PMU_CELL_NUM_PERFCTR, .num_cnt = PMU_CELL_NUM_COUNTERS, .get_event_code = pfm_cell_get_event_code, .get_event_name = pfm_cell_get_event_name, .get_event_counters = pfm_cell_get_event_counters, .dispatch_events = pfm_cell_dispatch_events, .pmu_detect = pfm_cell_detect, .get_impl_pmcs = pfm_cell_get_impl_pmcs, .get_impl_pmds = pfm_cell_get_impl_pmds, .get_impl_counters = pfm_cell_get_impl_counters, .get_event_desc = pfm_cell_get_event_desc, .get_cycle_event = pfm_cell_get_cycle_event }; papi-5.5.1/src/libpfm-3.y/lib/pfmlib_gen_mips64.c0000644000307100002310000003523213013651450021345 0ustar yarkhangraduate/* * pfmlib_gen_mips64.c : support for the generic MIPS64 PMU family * * Contributed by Philip Mucci based on code from * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include /* public headers */ #include /* private headers */ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_gen_mips64_priv.h" /* architecture private */ #include "gen_mips64_events.h" /* PMU private */ /* let's define some handy shortcuts! */ #define sel_event_mask perfsel.sel_event_mask #define sel_exl perfsel.sel_exl #define sel_os perfsel.sel_os #define sel_usr perfsel.sel_usr #define sel_sup perfsel.sel_sup #define sel_int perfsel.sel_int static pme_gen_mips64_entry_t *gen_mips64_pe = NULL; pfm_pmu_support_t generic_mips64_support; static int pfm_gen_mips64_detect(void) { static char mips_name[64] = ""; int ret; char buffer[128]; ret = __pfm_getcpuinfo_attr("cpu model", buffer, sizeof(buffer)); if (ret == -1) return PFMLIB_ERR_NOTSUPP; generic_mips64_support.pmu_name = mips_name; generic_mips64_support.num_cnt = 0; if (strstr(buffer,"MIPS 20Kc")) { gen_mips64_pe = gen_mips64_20K_pe; strcpy(generic_mips64_support.pmu_name,"MIPS20KC"), generic_mips64_support.pme_count = (sizeof(gen_mips64_20K_pe)/sizeof(pme_gen_mips64_entry_t)); generic_mips64_support.pmc_count = 1; generic_mips64_support.pmd_count = 1; generic_mips64_support.pmu_type = PFMLIB_MIPS_20KC_PMU; } else if (strstr(buffer,"MIPS 24K")) { gen_mips64_pe = gen_mips64_24K_pe; strcpy(generic_mips64_support.pmu_name,"MIPS24K"), generic_mips64_support.pme_count = (sizeof(gen_mips64_24K_pe)/sizeof(pme_gen_mips64_entry_t)); generic_mips64_support.pmc_count = 2; generic_mips64_support.pmd_count = 2; generic_mips64_support.pmu_type = PFMLIB_MIPS_24K_PMU; } else if (strstr(buffer,"MIPS 25Kf")) { gen_mips64_pe = gen_mips64_25K_pe; strcpy(generic_mips64_support.pmu_name,"MIPS25KF"), generic_mips64_support.pme_count = (sizeof(gen_mips64_25K_pe)/sizeof(pme_gen_mips64_entry_t)); generic_mips64_support.pmc_count = 2; generic_mips64_support.pmd_count = 2; generic_mips64_support.pmu_type = PFMLIB_MIPS_25KF_PMU; } else if (strstr(buffer,"MIPS 34K")) { gen_mips64_pe = gen_mips64_34K_pe; strcpy(generic_mips64_support.pmu_name,"MIPS34K"), generic_mips64_support.pme_count = (sizeof(gen_mips64_34K_pe)/sizeof(pme_gen_mips64_entry_t)); generic_mips64_support.pmc_count = 4; generic_mips64_support.pmd_count = 4; generic_mips64_support.pmu_type = PFMLIB_MIPS_34K_PMU; } else if (strstr(buffer,"MIPS 5Kc")) { gen_mips64_pe = gen_mips64_5K_pe; strcpy(generic_mips64_support.pmu_name,"MIPS5KC"), generic_mips64_support.pme_count = (sizeof(gen_mips64_5K_pe)/sizeof(pme_gen_mips64_entry_t)); generic_mips64_support.pmc_count = 2; generic_mips64_support.pmd_count = 2; generic_mips64_support.pmu_type = PFMLIB_MIPS_5KC_PMU; } #if 0 else if (strstr(buffer,"MIPS 74K")) { gen_mips64_pe = gen_mips64_74K_pe; strcpy(generic_mips64_support.pmu_name,"MIPS74K"), generic_mips64_support.pme_count = (sizeof(gen_mips64_74K_pe)/sizeof(pme_gen_mips64_entry_t)); generic_mips64_support.pmc_count = 4; generic_mips64_support.pmd_count = 4; generic_mips64_support.pmu_type = PFMLIB_MIPS_74K_PMU; } #endif else if (strstr(buffer,"R10000")) { gen_mips64_pe = gen_mips64_r10000_pe; strcpy(generic_mips64_support.pmu_name,"MIPSR10000"), generic_mips64_support.pme_count = (sizeof(gen_mips64_r10000_pe)/sizeof(pme_gen_mips64_entry_t)); generic_mips64_support.pmc_count = 2; generic_mips64_support.pmd_count = 2; generic_mips64_support.pmu_type = PFMLIB_MIPS_R10000_PMU; } else if (strstr(buffer,"R12000")) { gen_mips64_pe = gen_mips64_r12000_pe; strcpy(generic_mips64_support.pmu_name,"MIPSR12000"), generic_mips64_support.pme_count = (sizeof(gen_mips64_r12000_pe)/sizeof(pme_gen_mips64_entry_t)); generic_mips64_support.pmc_count = 4; generic_mips64_support.pmd_count = 4; generic_mips64_support.pmu_type = PFMLIB_MIPS_R12000_PMU; } else if (strstr(buffer,"RM7000")) { gen_mips64_pe = gen_mips64_rm7000_pe; strcpy(generic_mips64_support.pmu_name,"MIPSRM7000"), generic_mips64_support.pme_count = (sizeof(gen_mips64_rm7000_pe)/sizeof(pme_gen_mips64_entry_t)); generic_mips64_support.pmc_count = 2; generic_mips64_support.pmd_count = 2; generic_mips64_support.pmu_type = PFMLIB_MIPS_RM7000_PMU; } else if (strstr(buffer,"RM9000")) { gen_mips64_pe = gen_mips64_rm9000_pe; strcpy(generic_mips64_support.pmu_name,"MIPSRM9000"), generic_mips64_support.pme_count = (sizeof(gen_mips64_rm9000_pe)/sizeof(pme_gen_mips64_entry_t)); generic_mips64_support.pmc_count = 2; generic_mips64_support.pmd_count = 2; generic_mips64_support.pmu_type = PFMLIB_MIPS_RM9000_PMU; } else if (strstr(buffer,"SB1")) { gen_mips64_pe = gen_mips64_sb1_pe; strcpy(generic_mips64_support.pmu_name,"MIPSSB1"), generic_mips64_support.pme_count = (sizeof(gen_mips64_sb1_pe)/sizeof(pme_gen_mips64_entry_t)); generic_mips64_support.pmc_count = 4; generic_mips64_support.pmd_count = 4; generic_mips64_support.pmu_type = PFMLIB_MIPS_SB1_PMU; } else if (strstr(buffer,"VR5432")) { gen_mips64_pe = gen_mips64_vr5432_pe; generic_mips64_support.pme_count = (sizeof(gen_mips64_vr5432_pe)/sizeof(pme_gen_mips64_entry_t)); strcpy(generic_mips64_support.pmu_name,"MIPSVR5432"), generic_mips64_support.pmc_count = 2; generic_mips64_support.pmd_count = 2; generic_mips64_support.pmu_type = PFMLIB_MIPS_VR5432_PMU; } else if (strstr(buffer,"VR5500")) { gen_mips64_pe = gen_mips64_vr5500_pe; generic_mips64_support.pme_count = (sizeof(gen_mips64_vr5500_pe)/sizeof(pme_gen_mips64_entry_t)); strcpy(generic_mips64_support.pmu_name,"MIPSVR5500"), generic_mips64_support.pmc_count = 2; generic_mips64_support.pmd_count = 2; generic_mips64_support.pmu_type = PFMLIB_MIPS_VR5500_PMU; } else return PFMLIB_ERR_NOTSUPP; if (generic_mips64_support.num_cnt == 0) generic_mips64_support.num_cnt = generic_mips64_support.pmd_count; return PFMLIB_SUCCESS; } static void stuff_regs(pfmlib_event_t *e, int plm, pfmlib_reg_t *pc, pfmlib_reg_t *pd, int cntr, int j, pfmlib_gen_mips64_input_param_t *mod_in) { pfm_gen_mips64_sel_reg_t reg; reg.val = 0; /* assume reserved bits are zerooed */ /* if plm is 0, then assume not specified per-event and use default */ plm = e[j].plm ? e[j].plm : plm; reg.sel_usr = plm & PFM_PLM3 ? 1 : 0; reg.sel_os = plm & PFM_PLM0 ? 1 : 0; reg.sel_sup = plm & PFM_PLM1 ? 1 : 0; reg.sel_exl = plm & PFM_PLM2 ? 1 : 0; reg.sel_int = 1; /* force int to 1 */ reg.sel_event_mask = (gen_mips64_pe[e[j].event].pme_code >> (cntr*8)) & 0xff; pc[j].reg_value = reg.val; pc[j].reg_addr = cntr*2; pc[j].reg_num = cntr; __pfm_vbprintf("[CP0_25_%"PRIx64"(pmc%u)=0x%"PRIx64" event_mask=0x%x usr=%d os=%d sup=%d exl=%d int=1] %s\n", pc[j].reg_addr, pc[j].reg_num, pc[j].reg_value, reg.sel_event_mask, reg.sel_usr, reg.sel_os, reg.sel_sup, reg.sel_exl, gen_mips64_pe[e[j].event].pme_name); pd[j].reg_num = cntr; pd[j].reg_addr = cntr*2 + 1; __pfm_vbprintf("[CP0_25_%u(pmd%u)]\n", pc[j].reg_addr, pc[j].reg_num); } /* * Automatically dispatch events to corresponding counters following constraints. * Upon return the pfarg_regt structure is ready to be submitted to kernel */ static int pfm_gen_mips64_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_gen_mips64_input_param_t *mod_in, pfmlib_output_param_t *outp) { /* pfmlib_gen_mips64_input_param_t *param = mod_in; */ pfmlib_event_t *e = inp->pfp_events; pfmlib_reg_t *pc, *pd; unsigned int i, j, cnt = inp->pfp_event_count; unsigned int used = 0; extern pfm_pmu_support_t generic_mips64_support; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; /* Degree 2 rank based allocation */ if (cnt > generic_mips64_support.pmc_count) return PFMLIB_ERR_TOOMANY; if (PFMLIB_DEBUG()) { for (j=0; j < cnt; j++) { DPRINT("ev[%d]=%s, counters=0x%x\n", j, gen_mips64_pe[e[j].event].pme_name,gen_mips64_pe[e[j].event].pme_counters); } } /* Do rank based allocation, counters that live on 1 reg before counters that live on 2 regs etc. */ for (i=1;i<=PMU_GEN_MIPS64_NUM_COUNTERS;i++) { for (j=0; j < cnt;j++) { unsigned int cntr, avail; if (pfmlib_popcnt(gen_mips64_pe[e[j].event].pme_counters) == i) { /* These counters can be used for this event */ avail = ~used & gen_mips64_pe[e[j].event].pme_counters; DPRINT("Rank %d: Counters available 0x%x\n",i,avail); if (avail == 0x0) return PFMLIB_ERR_NOASSIGN; /* Pick one, mark as used*/ cntr = ffs(avail) - 1; DPRINT("Rank %d: Chose counter %d\n",i,cntr); /* Update registers */ stuff_regs(e,inp->pfp_dfl_plm,pc,pd,cntr,j,mod_in); used |= (1 << cntr); DPRINT("%d: Used counters 0x%x\n",i, used); } } } /* number of evtsel registers programmed */ outp->pfp_pmc_count = cnt; outp->pfp_pmd_count = cnt; return PFMLIB_SUCCESS; } static int pfm_gen_mips64_dispatch_events(pfmlib_input_param_t *inp, void *model_in, pfmlib_output_param_t *outp, void *model_out) { pfmlib_gen_mips64_input_param_t *mod_in = (pfmlib_gen_mips64_input_param_t *)model_in; return pfm_gen_mips64_dispatch_counters(inp, mod_in, outp); } static int pfm_gen_mips64_get_event_code(unsigned int i, unsigned int cnt, int *code) { extern pfm_pmu_support_t generic_mips64_support; /* check validity of counter index */ if (cnt != PFMLIB_CNT_FIRST) { if (cnt < 0 || cnt >= generic_mips64_support.pmc_count) return PFMLIB_ERR_INVAL; } else { cnt = ffs(gen_mips64_pe[i].pme_counters)-1; if (cnt == -1) return(PFMLIB_ERR_INVAL); } /* if cnt == 1, shift right by 0, if cnt == 2, shift right by 8 */ /* Works on both 5k anf 20K */ if (gen_mips64_pe[i].pme_counters & (1<< cnt)) *code = 0xff & (gen_mips64_pe[i].pme_code >> (cnt*8)); else return PFMLIB_ERR_INVAL; return PFMLIB_SUCCESS; } static void pfm_gen_mips64_get_event_counters(unsigned int j, pfmlib_regmask_t *counters) { extern pfm_pmu_support_t generic_mips64_support; unsigned int tmp; memset(counters, 0, sizeof(*counters)); tmp = gen_mips64_pe[j].pme_counters; while (tmp) { int t = ffs(tmp) - 1; pfm_regmask_set(counters, t); tmp = tmp ^ (1 << t); } } static void pfm_gen_mips64_get_impl_perfsel(pfmlib_regmask_t *impl_pmcs) { unsigned int i = 0; extern pfm_pmu_support_t generic_mips64_support; /* all pmcs are contiguous */ for(i=0; i < generic_mips64_support.pmc_count; i++) pfm_regmask_set(impl_pmcs, i); } static void pfm_gen_mips64_get_impl_perfctr(pfmlib_regmask_t *impl_pmds) { unsigned int i = 0; extern pfm_pmu_support_t generic_mips64_support; /* all pmds are contiguous */ for(i=0; i < generic_mips64_support.pmd_count; i++) pfm_regmask_set(impl_pmds, i); } static void pfm_gen_mips64_get_impl_counters(pfmlib_regmask_t *impl_counters) { unsigned int i = 0; extern pfm_pmu_support_t generic_mips64_support; for(i=0; i < generic_mips64_support.pmc_count; i++) pfm_regmask_set(impl_counters, i); } static void pfm_gen_mips64_get_hw_counter_width(unsigned int *width) { *width = PMU_GEN_MIPS64_COUNTER_WIDTH; } static char * pfm_gen_mips64_get_event_name(unsigned int i) { return gen_mips64_pe[i].pme_name; } static int pfm_gen_mips64_get_event_description(unsigned int ev, char **str) { char *s; s = gen_mips64_pe[ev].pme_desc; if (s) { *str = strdup(s); } else { *str = NULL; } return PFMLIB_SUCCESS; } static int pfm_gen_mips64_get_cycle_event(pfmlib_event_t *e) { return pfm_find_full_event("CYCLES",e); } static int pfm_gen_mips64_get_inst_retired(pfmlib_event_t *e) { if (pfm_current == NULL) return(PFMLIB_ERR_NOINIT); switch (pfm_current->pmu_type) { case PFMLIB_MIPS_20KC_PMU: return pfm_find_full_event("INSNS_COMPLETED",e); case PFMLIB_MIPS_24K_PMU: return pfm_find_full_event("INSTRUCTIONS",e); case PFMLIB_MIPS_25KF_PMU: return pfm_find_full_event("INSNS_COMPLETE",e); case PFMLIB_MIPS_34K_PMU: return pfm_find_full_event("INSTRUCTIONS",e); case PFMLIB_MIPS_5KC_PMU: return pfm_find_full_event("INSNS_EXECD",e); case PFMLIB_MIPS_R10000_PMU: case PFMLIB_MIPS_R12000_PMU: return pfm_find_full_event("INSTRUCTIONS_GRADUATED",e); case PFMLIB_MIPS_RM7000_PMU: case PFMLIB_MIPS_RM9000_PMU: return pfm_find_full_event("INSTRUCTIONS_ISSUED",e); case PFMLIB_MIPS_VR5432_PMU: case PFMLIB_MIPS_VR5500_PMU: return pfm_find_full_event("INSTRUCTIONS_EXECUTED",e); case PFMLIB_MIPS_SB1_PMU: return pfm_find_full_event("INSN_SURVIVED_STAGE7",e); default: return(PFMLIB_ERR_NOTFOUND); } } /* SiCortex specific functions */ pfm_pmu_support_t generic_mips64_support = { .pmu_name = NULL, .pmu_type = PFMLIB_UNKNOWN_PMU, .pme_count = 0, .pmc_count = 0, .pmd_count = 0, .num_cnt = 0, .flags = PFMLIB_MULT_CODE_EVENT, .get_event_code = pfm_gen_mips64_get_event_code, .get_event_name = pfm_gen_mips64_get_event_name, .get_event_counters = pfm_gen_mips64_get_event_counters, .dispatch_events = pfm_gen_mips64_dispatch_events, .pmu_detect = pfm_gen_mips64_detect, .get_impl_pmcs = pfm_gen_mips64_get_impl_perfsel, .get_impl_pmds = pfm_gen_mips64_get_impl_perfctr, .get_impl_counters = pfm_gen_mips64_get_impl_counters, .get_hw_counter_width = pfm_gen_mips64_get_hw_counter_width, .get_event_desc = pfm_gen_mips64_get_event_description, .get_cycle_event = pfm_gen_mips64_get_cycle_event, .get_inst_retired_event = pfm_gen_mips64_get_inst_retired }; papi-5.5.1/src/libpfm-3.y/lib/pfmlib_priv.h0000644000307100002310000001302713013651450020355 0ustar yarkhangraduate/* * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #ifndef __PFMLIB_PRIV_H__ #define __PFMLIB_PRIV_H__ #include #include "pfmlib_priv_comp.h" typedef struct { char *pmu_name; int pmu_type; /* must remain int, using -1 */ unsigned int pme_count; /* number of events */ unsigned int pmd_count; /* number of PMD registers */ unsigned int pmc_count; /* number of PMC registers */ unsigned int num_cnt; /* number of counters (counting PMD registers) */ unsigned int flags; int (*get_event_code)(unsigned int i, unsigned int cnt, int *code); int (*get_event_mask_code)(unsigned int i, unsigned int mask_idx, unsigned int *code); char *(*get_event_name)(unsigned int i); char *(*get_event_mask_name)(unsigned int event_idx, unsigned int mask_idx); void (*get_event_counters)(unsigned int i, pfmlib_regmask_t *counters); unsigned int (*get_num_event_masks)(unsigned int event_idx); int (*dispatch_events)(pfmlib_input_param_t *p, void *model_in, pfmlib_output_param_t *q, void *model_out); int (*pmu_detect)(void); int (*pmu_init)(void); void (*get_impl_pmcs)(pfmlib_regmask_t *impl_pmcs); void (*get_impl_pmds)(pfmlib_regmask_t *impl_pmds); void (*get_impl_counters)(pfmlib_regmask_t *impl_counters); void (*get_hw_counter_width)(unsigned int *width); int (*get_event_desc)(unsigned int i, char **buf); int (*get_event_mask_desc)(unsigned int event_idx, unsigned int mask_idx, char **buf); int (*get_cycle_event)(pfmlib_event_t *e); int (*get_inst_retired_event)(pfmlib_event_t *e); int (*has_umask_default)(unsigned int i); /* optional */ } pfm_pmu_support_t; #define PFMLIB_MULT_CODE_EVENT 0x1 /* more than one code per event (depending on counter) */ #define PFMLIB_CNT_FIRST -1 /* return code for event on first counter */ #define PFMLIB_NO_EVT (~0U) /* no event index associated with event */ typedef struct { pfmlib_options_t options; pfm_pmu_support_t *current; int options_env_set; /* 1 if options set by env variables */ } pfm_config_t; #define PFMLIB_INITIALIZED() (pfm_config.current != NULL) extern pfm_config_t pfm_config; #define PFMLIB_DEBUG() pfm_config.options.pfm_debug #define PFMLIB_VERBOSE() pfm_config.options.pfm_verbose #define pfm_current pfm_config.current extern void __pfm_vbprintf(const char *fmt,...); extern int __pfm_check_event(pfmlib_event_t *e); /* * provided by OS-specific module */ extern int __pfm_getcpuinfo_attr(const char *attr, char *ret_buf, size_t maxlen); extern void pfm_init_syscalls(void); #ifdef PFMLIB_DEBUG #define DPRINT(fmt, a...) \ do { \ if (pfm_config.options.pfm_debug) { \ fprintf(libpfm_fp, "%s (%s.%d): " fmt, __FILE__, __func__, __LINE__, ## a); } \ } while (0) #else #define DPRINT(a) #endif #define ALIGN_DOWN(a,p) ((a) & ~((1UL<<(p))-1)) #define ALIGN_UP(a,p) ((((a) + ((1UL<<(p))-1))) & ~((1UL<<(p))-1)) extern pfm_pmu_support_t crayx2_support; extern pfm_pmu_support_t montecito_support; extern pfm_pmu_support_t itanium2_support; extern pfm_pmu_support_t itanium_support; extern pfm_pmu_support_t generic_ia64_support; extern pfm_pmu_support_t amd64_support; extern pfm_pmu_support_t i386_p6_support; extern pfm_pmu_support_t i386_ppro_support; extern pfm_pmu_support_t i386_pii_support; extern pfm_pmu_support_t i386_pm_support; extern pfm_pmu_support_t gen_ia32_support; extern pfm_pmu_support_t generic_mips64_support; extern pfm_pmu_support_t sicortex_support; extern pfm_pmu_support_t pentium4_support; extern pfm_pmu_support_t coreduo_support; extern pfm_pmu_support_t core_support; extern pfm_pmu_support_t gen_powerpc_support; extern pfm_pmu_support_t sparc_support; extern pfm_pmu_support_t cell_support; extern pfm_pmu_support_t intel_atom_support; extern pfm_pmu_support_t intel_nhm_support; extern pfm_pmu_support_t intel_wsm_support; static inline unsigned int pfm_num_masks(int e) { if (pfm_current->get_num_event_masks == NULL) return 0; return pfm_current->get_num_event_masks(e); } extern FILE *libpfm_fp; extern int forced_pmu; extern int _pfmlib_sys_base; /* syscall base */ extern int _pfmlib_major_version; /* kernel perfmon major version */ extern int _pfmlib_minor_version; /* kernel perfmon minor version */ extern void pfm_init_syscalls(void); static inline int _pfmlib_get_sys_base() { if (!_pfmlib_sys_base) pfm_init_syscalls(); return _pfmlib_sys_base; } #endif /* __PFMLIB_PRIV_H__ */ papi-5.5.1/src/libpfm-3.y/lib/pfmlib_gen_powerpc.c0000644000307100002310000006042213013651450021701 0ustar yarkhangraduate/* * Copyright (C) IBM Corporation, 2007. All rights reserved. * Contributed by Corey Ashford (cjashfor@us.ibm.com) * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * pfmlib_gen_powerpc.c * * Support for libpfm for the PowerPC970, POWER4,4+,5,5+,6 processors. */ #ifndef _GNU_SOURCE #define _GNU_SOURCE /* for getline */ #endif #include #include #include #include /* private headers */ #include "powerpc_reg.h" #include "pfmlib_priv.h" #include "pfmlib_power_priv.h" #include "pfmlib_ppc970_priv.h" #include "pfmlib_ppc970mp_priv.h" #include "pfmlib_power4_priv.h" #include "pfmlib_power5_priv.h" #include "pfmlib_power5+_priv.h" #include "pfmlib_power6_priv.h" #include "pfmlib_power7_priv.h" #include "ppc970_events.h" #include "ppc970mp_events.h" #include "power4_events.h" #include "power5_events.h" #include "power5+_events.h" #include "power6_events.h" #include "power7_events.h" #define FIRST_POWER_PMU PFMLIB_PPC970_PMU static const int num_group_vec[] = { [PFMLIB_PPC970_PMU - FIRST_POWER_PMU] = PPC970_NUM_GROUP_VEC, [PFMLIB_PPC970MP_PMU - FIRST_POWER_PMU] = PPC970MP_NUM_GROUP_VEC, [PFMLIB_POWER4_PMU - FIRST_POWER_PMU] = POWER4_NUM_GROUP_VEC, [PFMLIB_POWER5_PMU - FIRST_POWER_PMU] = POWER5_NUM_GROUP_VEC, [PFMLIB_POWER5p_PMU - FIRST_POWER_PMU] = POWER5p_NUM_GROUP_VEC, [PFMLIB_POWER6_PMU - FIRST_POWER_PMU] = POWER6_NUM_GROUP_VEC, [PFMLIB_POWER7_PMU - FIRST_POWER_PMU] = POWER7_NUM_GROUP_VEC }; static const int event_count[] = { [PFMLIB_PPC970_PMU - FIRST_POWER_PMU] = PPC970_PME_EVENT_COUNT, [PFMLIB_PPC970MP_PMU - FIRST_POWER_PMU] = PPC970MP_PME_EVENT_COUNT, [PFMLIB_POWER5_PMU - FIRST_POWER_PMU] = POWER5_PME_EVENT_COUNT, [PFMLIB_POWER5p_PMU - FIRST_POWER_PMU] = POWER5p_PME_EVENT_COUNT, [PFMLIB_POWER6_PMU - FIRST_POWER_PMU] = POWER6_PME_EVENT_COUNT, [PFMLIB_POWER7_PMU - FIRST_POWER_PMU] = POWER7_PME_EVENT_COUNT }; unsigned *pmd_priv_vec; static unsigned long long mmcr0_fc5_6_mask; static unsigned long long *mmcr0_counter_mask; static unsigned long long *mmcr1_counter_mask; static unsigned long long *mmcr0_counter_off_val; static unsigned long long *mmcr1_counter_off_val; static const pme_power_entry_t *pe; static const pmg_power_group_t *groups; static inline int get_num_event_counters() { return gen_powerpc_support.pmd_count; } static inline int get_num_control_regs() { return gen_powerpc_support.pmc_count; } static inline const unsigned long long *get_group_vector(int event) { return pe[event].pme_group_vector; } static inline int get_event_id(int event, int counter) { return pe[event].pme_event_ids[counter]; } static inline char *get_event_name(int event) { return pe[event].pme_name; } static inline char *get_long_desc(int event) { return pe[event].pme_long_desc; } static inline int get_group_event_id(int group, int counter) { return groups[group].pmg_event_ids[counter]; } static inline unsigned long long get_mmcr0(int group) { return groups[group].pmg_mmcr0; } static inline unsigned long long get_mmcr1(int group) { return groups[group].pmg_mmcr1; } static inline unsigned long long get_mmcra(int group) { return groups[group].pmg_mmcra; } /** * pfm_gen_powerpc_get_event_code * * Return the event-select value for the specified event as * needed for the specified PMD counter. **/ static int pfm_gen_powerpc_get_event_code(unsigned int event, unsigned int pmd, int *code) { if (event < event_count[gen_powerpc_support.pmu_type - FIRST_POWER_PMU]) { *code = pe[event].pme_code; return PFMLIB_SUCCESS; } else return PFMLIB_ERR_INVAL; } /** * pfm_gen_powerpc_get_event_name * * Return the name of the specified event. **/ static char *pfm_gen_powerpc_get_event_name(unsigned int event) { return get_event_name(event); } /** * pfm_gen_powerpc_get_event_mask_name * * Return the name of the specified event-mask. **/ static char *pfm_gen_powerpc_get_event_mask_name(unsigned int event, unsigned int mask) { return ""; } /** * pfm_gen_powerpc_get_event_counters * * Fill in the 'counters' bitmask with all possible PMDs that could be * used to count the specified event. **/ static void pfm_gen_powerpc_get_event_counters(unsigned int event, pfmlib_regmask_t *counters) { int i; counters->bits[0] = 0; for (i = 0; i < get_num_event_counters(); i++) { if (get_event_id(event, i) != -1) { counters->bits[0] |= (1 << i); } } } /** * pfm_gen_powerpc_get_num_event_masks * * Count the number of available event-masks for the specified event. **/ static unsigned int pfm_gen_powerpc_get_num_event_masks(unsigned int event) { /* POWER arch doesn't use event masks */ return 0; } static void remove_group(unsigned long long *group_vec, int group) { group_vec[group / 64] &= ~(1ULL << (group % 64)); } static void intersect_groups(unsigned long long *result, const unsigned long long *operand) { int i; for (i = 0; i < num_group_vec[gen_powerpc_support.pmu_type - FIRST_POWER_PMU]; i++) { result[i] &= operand[i]; } } static int first_group(unsigned long long *group_vec) { int i, bit; for (i = 0; i < num_group_vec[gen_powerpc_support.pmu_type - FIRST_POWER_PMU]; i++) { bit = ffsll(group_vec[i]); if (bit) { return (bit - 1) + (i * 64); } } /* There were no groups */ return -1; } static unsigned gq_pmd_priv_vec[8] = { 0x0f0e, 0x0f0e, 0x0f0e, 0x0f0e, 0x0f0e, 0x0f0e, 0x0f0e, 0x0f0e }; static unsigned gr_pmd_priv_vec[6] = { 0x0f0e, 0x0f0e, 0x0f0e, 0x0f0e, 0x0f0e, 0x0f0e, }; static unsigned gs_pmd_priv_vec[6] = { 0x0f0e, 0x0f0e, 0x0f0e, 0x0f0e, 0x0800, 0x0800, }; /* These masks are used on the PPC970*, and POWER4,4+ chips */ static unsigned long long power4_mmcr0_counter_mask[POWER4_NUM_EVENT_COUNTERS] = { 0x1fUL << (63 - 55), /* PMC1 */ 0x1fUL << (63 - 62), /* PMC2 */ 0, 0, 0, 0, 0, 0 }; static unsigned long long power4_mmcr1_counter_mask[POWER4_NUM_EVENT_COUNTERS] = { 0, 0, 0x1fUL << (63 - 36), /* PMC3 */ 0x1fUL << (63 - 41), /* PMC4 */ 0x1fUL << (63 - 46), /* PMC5 */ 0x1fUL << (63 - 51), /* PMC6 */ 0x1fUL << (63 - 56), /* PMC7 */ 0x1fUL << (63 - 61) /* PMC8 */ }; static unsigned long long power4_mmcr0_counter_off_val[POWER4_NUM_EVENT_COUNTERS] = { 0, /* PMC1 */ 0, /* PMC2 */ 0, 0, 0, 0, 0, 0 }; static unsigned long long power4_mmcr1_counter_off_val[POWER4_NUM_EVENT_COUNTERS] = { 0, 0, 0, /* PMC3 */ 0, /* PMC4 */ 0, /* PMC5 */ 0, /* PMC6 */ 0, /* PMC7 */ 0 /* PMC8 */ }; static unsigned long long ppc970_mmcr0_counter_off_val[POWER4_NUM_EVENT_COUNTERS] = { 0x8UL << (63 - 55), /* PMC1 */ 0x8UL << (63 - 62), /* PMC2 */ 0, 0, 0, 0, 0, 0 }; static unsigned long long ppc970_mmcr1_counter_off_val[POWER4_NUM_EVENT_COUNTERS] = { 0, 0, 0x8UL << (63 - 36), /* PMC3 */ 0x8UL << (63 - 41), /* PMC4 */ 0x8UL << (63 - 46), /* PMC5 */ 0x8UL << (63 - 51), /* PMC6 */ 0x8UL << (63 - 56), /* PMC7 */ 0x8UL << (63 - 61) /* PMC8 */ }; /* These masks are used on POWER5,5+,5++,6,7 */ static unsigned long long power5_mmcr0_counter_mask[POWER5_NUM_EVENT_COUNTERS] = { 0, 0, 0, 0, 0, 0 }; static unsigned long long power5_mmcr1_counter_mask[POWER5_NUM_EVENT_COUNTERS] = { 0xffUL << (63 - 39), /* PMC1 */ 0xffUL << (63 - 47), /* PMC2 */ 0xffUL << (63 - 55), /* PMC3 */ 0xffUL << (63 - 63), /* PMC4 */ 0, 0 }; static unsigned long long power5_mmcr0_counter_off_val[POWER5_NUM_EVENT_COUNTERS] = { 0, 0, 0, 0, 0, 0 }; static unsigned long long power5_mmcr1_counter_off_val[POWER5_NUM_EVENT_COUNTERS] = { 0, /* PMC1 */ 0, /* PMC2 */ 0, /* PMC3 */ 0, /* PMC4 */ 0, 0 }; /** * pfm_gen_powerpc_dispatch_events * * Examine each desired event specified in "input" and find an appropriate * set of PMCs and PMDs to count them. **/ static int pfm_gen_powerpc_dispatch_events(pfmlib_input_param_t *input, void *model_input, pfmlib_output_param_t *output, void *model_output) { /* model_input and model_output are unused on POWER */ int i, j, group; int counters_used = 0; unsigned long long mmcr0_val, mmcr1_val; unsigned long long group_vector[num_group_vec[gen_powerpc_support.pmu_type - FIRST_POWER_PMU]]; unsigned int plm; plm = (input->pfp_events[0].plm != 0) ? input->pfp_events[0].plm : input->pfp_dfl_plm; /* * Verify that all of the privilege level masks are identical, as * we cannot have mixed levels on POWER */ for (i = 1; i < input->pfp_event_count; i++) { if (input->pfp_events[i].plm == 0) { /* it's ok if the default is the same as plm */ if (plm != input->pfp_dfl_plm) return PFMLIB_ERR_NOASSIGN; } else { if (plm != input->pfp_events[i].plm) return PFMLIB_ERR_NOASSIGN; } } /* start by setting all of the groups as available */ memset(group_vector, 0xff, sizeof(unsigned long long) * num_group_vec[gen_powerpc_support.pmu_type - FIRST_POWER_PMU]); for (i = 0; i < input->pfp_event_count; i++) { mmcr0_val |= mmcr0_counter_off_val[i]; intersect_groups(group_vector, get_group_vector(input->pfp_events[i].event)); mmcr1_val |= mmcr1_counter_off_val[i]; } group = first_group(group_vector); while (group != -1) { /* find out if the the privilege levels are compatible with each counter */ for (i = 0; i < input->pfp_event_count; i++) { /* find event counter in group */ for (j = 0; j < get_num_event_counters(); j++) { if (get_event_id(input->pfp_events[i].event,j) == get_group_event_id(group, j)) { /* found counter */ if (input->pfp_events[i].plm != 0) { if (! (pmd_priv_vec[j] & (1 << input->pfp_events[0].plm))) { remove_group(group_vector, group); group = first_group(group_vector); goto try_next_group; } } else { if (! (pmd_priv_vec[j] & (1 << input->pfp_dfl_plm))) { remove_group(group_vector, group); group = first_group(group_vector); goto try_next_group; } } /* We located this counter and its privilege checks out ok. */ counters_used |= (1 << j); output->pfp_pmds[i].reg_value = 0; output->pfp_pmds[i].reg_addr = 0; output->pfp_pmds[i].reg_alt_addr = 0; output->pfp_pmds[i].reg_num = j + 1; output->pfp_pmds[i].reg_reserved1 = 0; output->pfp_pmd_count = i + 1; /* Find the next counter */ break; } } if (j == get_num_event_counters()) { printf ("libpfm: Internal error. Unable to find counter in group.\n"); } } /* * Success! We found a group (group) that meets the * privilege constraints */ break; try_next_group: ; } if (group == -1) /* We did not find a group that meets the constraints */ return PFMLIB_ERR_NOASSIGN; /* We now have a group that meets the constraints */ mmcr0_val = get_mmcr0(group); mmcr1_val = get_mmcr1(group); for (i = 0; i < get_num_event_counters(); i++) { if (! (counters_used & (1 << i))) { /* * This counter is not used, so set that * selector to its off value. */ mmcr0_val &= ~mmcr0_counter_mask[i]; mmcr0_val |= mmcr0_counter_off_val[i]; mmcr1_val &= ~mmcr1_counter_mask[i]; mmcr1_val |= mmcr1_counter_off_val[i]; } } /* * As a special case for PMC5 and PMC6 on POWER5/5+, freeze these * two counters if neither are used. Note that the * mmcr0_fc5_6_mask is zero for all processors except POWER5/5+ */ if ((counters_used & ((1 << (5 - 1)) | (1 << (6 - 1)))) == 0) mmcr0_val |= mmcr0_fc5_6_mask; /* * Enable counter "exception on negative" and performance monitor * exceptions */ mmcr0_val |= MMCR0_PMXE | MMCR0_PMC1CE | MMCR0_PMCjCE; /* Start with the counters frozen in every state, then selectively enable them */ mmcr0_val |= MMCR0_FCP | MMCR0_FCS | MMCR0_FCHV; if (plm & PFM_PLM3) { /* user */ mmcr0_val &= ~MMCR0_FCP; } if (plm & PFM_PLM0) { /* kernel */ mmcr0_val &= ~MMCR0_FCS; } if (plm & PFM_PLM1) { /* hypervisor */ mmcr0_val &= ~MMCR0_FCHV; } /* PFM_PLM2 is not supported */ output->pfp_pmcs[0].reg_value = mmcr0_val; output->pfp_pmcs[0].reg_addr = 0; output->pfp_pmcs[0].reg_alt_addr = 0; output->pfp_pmcs[0].reg_num = 0; output->pfp_pmcs[0].reg_reserved1 = 0; output->pfp_pmcs[1].reg_value = mmcr1_val; output->pfp_pmcs[1].reg_addr = 0; output->pfp_pmcs[1].reg_alt_addr = 0; output->pfp_pmcs[1].reg_num = 1; output->pfp_pmcs[1].reg_reserved1 = 0; output->pfp_pmcs[2].reg_value = get_mmcra(group); output->pfp_pmcs[2].reg_addr = 0; output->pfp_pmcs[2].reg_alt_addr = 0; output->pfp_pmcs[2].reg_num = 2; output->pfp_pmcs[2].reg_reserved1 = 0; /* We always use the same number of control regs */ output->pfp_pmc_count = get_num_control_regs(); return PFMLIB_SUCCESS; } /** * pfm_gen_powerpc_pmu_detect * * Determine which POWER processor, if any, we are running on. * **/ /** * These should be defined in more recent versions of * /usr/include/asm-ppc64/reg.h. It isn't pretty to have these here, but * maybe we can remove them someday. **/ static int pfm_gen_powerpc_pmu_detect(void) { if (__is_processor(PV_970) || __is_processor(PV_970FX) || __is_processor(PV_970GX)) { gen_powerpc_support.pmu_type = PFMLIB_PPC970_PMU; gen_powerpc_support.pmu_name = "PPC970"; gen_powerpc_support.pme_count = PPC970_PME_EVENT_COUNT; gen_powerpc_support.pmd_count = PPC970_NUM_EVENT_COUNTERS; gen_powerpc_support.pmc_count = PPC970_NUM_CONTROL_REGS; gen_powerpc_support.num_cnt = PPC970_NUM_EVENT_COUNTERS; mmcr0_fc5_6_mask = 0; mmcr0_counter_mask = power4_mmcr0_counter_mask; mmcr1_counter_mask = power4_mmcr1_counter_mask; mmcr0_counter_off_val = ppc970_mmcr0_counter_off_val; mmcr1_counter_off_val = ppc970_mmcr1_counter_off_val; pmd_priv_vec = gq_pmd_priv_vec; pe = ppc970_pe; groups = ppc970_groups; return PFMLIB_SUCCESS; } if (__is_processor(PV_970MP)) { gen_powerpc_support.pmu_type = PFMLIB_PPC970MP_PMU; gen_powerpc_support.pmu_name = "PPC970MP"; gen_powerpc_support.pme_count = PPC970MP_PME_EVENT_COUNT; gen_powerpc_support.pmd_count = PPC970MP_NUM_EVENT_COUNTERS; gen_powerpc_support.pmc_count = PPC970MP_NUM_CONTROL_REGS; gen_powerpc_support.num_cnt = PPC970MP_NUM_EVENT_COUNTERS; mmcr0_fc5_6_mask = 0; mmcr0_counter_mask = power4_mmcr0_counter_mask; mmcr1_counter_mask = power4_mmcr1_counter_mask; mmcr0_counter_off_val = ppc970_mmcr0_counter_off_val; mmcr1_counter_off_val = ppc970_mmcr1_counter_off_val; pmd_priv_vec = gq_pmd_priv_vec; pe = ppc970mp_pe; groups = ppc970mp_groups; return PFMLIB_SUCCESS; } if (__is_processor(PV_POWER4) || __is_processor(PV_POWER4p)) { gen_powerpc_support.pmu_type = PFMLIB_PPC970_PMU; gen_powerpc_support.pmu_name = "POWER4"; gen_powerpc_support.pme_count = POWER4_PME_EVENT_COUNT; gen_powerpc_support.pmd_count = POWER4_NUM_EVENT_COUNTERS; gen_powerpc_support.pmc_count = POWER4_NUM_CONTROL_REGS; gen_powerpc_support.num_cnt = POWER4_NUM_EVENT_COUNTERS; mmcr0_fc5_6_mask = 0; mmcr0_counter_mask = power4_mmcr0_counter_mask; mmcr1_counter_mask = power4_mmcr1_counter_mask; mmcr0_counter_off_val = ppc970_mmcr0_counter_off_val; mmcr1_counter_off_val = ppc970_mmcr1_counter_off_val; mmcr0_counter_off_val = power4_mmcr0_counter_off_val; mmcr1_counter_off_val = power4_mmcr1_counter_off_val; pmd_priv_vec = gq_pmd_priv_vec; pe = power4_pe; groups = power4_groups; return PFMLIB_SUCCESS; } if (__is_processor(PV_POWER5)) { gen_powerpc_support.pmu_type = PFMLIB_POWER5_PMU; gen_powerpc_support.pmu_name = "POWER5"; gen_powerpc_support.pme_count = POWER5_PME_EVENT_COUNT; gen_powerpc_support.pmd_count = POWER5_NUM_EVENT_COUNTERS; gen_powerpc_support.pmc_count = POWER5_NUM_CONTROL_REGS; gen_powerpc_support.num_cnt = POWER5_NUM_EVENT_COUNTERS; mmcr0_fc5_6_mask = MMCR0_FC5_6; mmcr0_counter_off_val = ppc970_mmcr0_counter_off_val; mmcr1_counter_off_val = ppc970_mmcr1_counter_off_val; mmcr0_counter_mask = power5_mmcr0_counter_mask; mmcr1_counter_mask = power5_mmcr1_counter_mask; mmcr0_counter_off_val = power5_mmcr0_counter_off_val; mmcr1_counter_off_val = power5_mmcr1_counter_off_val; pmd_priv_vec = gr_pmd_priv_vec; pe = power5_pe; groups = power5_groups; return PFMLIB_SUCCESS; } if (__is_processor(PV_POWER5p)) { gen_powerpc_support.pmu_type = PFMLIB_POWER5p_PMU; gen_powerpc_support.pmu_name = "POWER5+"; gen_powerpc_support.pme_count = POWER5p_PME_EVENT_COUNT; gen_powerpc_support.pmd_count = POWER5p_NUM_EVENT_COUNTERS; gen_powerpc_support.pmc_count = POWER5p_NUM_CONTROL_REGS; mmcr0_counter_off_val = power4_mmcr0_counter_off_val; mmcr1_counter_off_val = power4_mmcr1_counter_off_val; gen_powerpc_support.num_cnt = POWER5p_NUM_EVENT_COUNTERS; mmcr0_counter_mask = power5_mmcr0_counter_mask; mmcr1_counter_mask = power5_mmcr1_counter_mask; mmcr0_counter_off_val = power5_mmcr0_counter_off_val; mmcr1_counter_off_val = power5_mmcr1_counter_off_val; if (PVR_VER(mfspr(SPRN_PVR)) >= 0x300) { /* this is a newer, GS model POWER5+ */ mmcr0_fc5_6_mask = 0; pmd_priv_vec = gs_pmd_priv_vec; } else { mmcr0_fc5_6_mask = MMCR0_FC5_6; pmd_priv_vec = gr_pmd_priv_vec; } mmcr0_counter_off_val = power5_mmcr0_counter_off_val; mmcr1_counter_off_val = power5_mmcr1_counter_off_val; pe = power5p_pe; groups = power5p_groups; return PFMLIB_SUCCESS; } if (__is_processor(PV_POWER6)) { gen_powerpc_support.pmu_type = PFMLIB_POWER6_PMU; gen_powerpc_support.pmu_name = "POWER6"; gen_powerpc_support.pme_count = POWER6_PME_EVENT_COUNT; gen_powerpc_support.pmd_count = POWER6_NUM_EVENT_COUNTERS; gen_powerpc_support.pmc_count = POWER6_NUM_CONTROL_REGS; gen_powerpc_support.num_cnt = POWER6_NUM_EVENT_COUNTERS; mmcr0_fc5_6_mask = 0; mmcr0_counter_mask = power5_mmcr0_counter_mask; mmcr1_counter_mask = power5_mmcr1_counter_mask; mmcr0_counter_off_val = power5_mmcr0_counter_off_val; mmcr1_counter_off_val = power5_mmcr1_counter_off_val; mmcr0_counter_off_val = power5_mmcr0_counter_off_val; mmcr1_counter_off_val = power5_mmcr1_counter_off_val; pmd_priv_vec = gs_pmd_priv_vec; pe = power6_pe; groups = power6_groups; return PFMLIB_SUCCESS; } if (__is_processor(PV_POWER7)) { gen_powerpc_support.pmu_type = PFMLIB_POWER7_PMU; gen_powerpc_support.pmu_name = "POWER7"; gen_powerpc_support.pme_count = POWER7_PME_EVENT_COUNT; gen_powerpc_support.pmd_count = POWER7_NUM_EVENT_COUNTERS; gen_powerpc_support.pmc_count = POWER7_NUM_CONTROL_REGS; gen_powerpc_support.num_cnt = POWER7_NUM_EVENT_COUNTERS; mmcr0_fc5_6_mask = 0; mmcr0_counter_mask = power5_mmcr0_counter_mask; mmcr1_counter_mask = power5_mmcr1_counter_mask; mmcr0_counter_off_val = power5_mmcr0_counter_off_val; mmcr1_counter_off_val = power5_mmcr1_counter_off_val; mmcr0_counter_off_val = power5_mmcr0_counter_off_val; mmcr1_counter_off_val = power5_mmcr1_counter_off_val; pmd_priv_vec = gr_pmd_priv_vec; pe = power7_pe; groups = power7_groups; return PFMLIB_SUCCESS; } return PFMLIB_ERR_NOTSUPP; } /** * pfm_gen_powerpc_get_impl_pmcs * * Set the appropriate bit in the impl_pmcs bitmask for each PMC that's * available on power4. **/ static void pfm_gen_powerpc_get_impl_pmcs(pfmlib_regmask_t *impl_pmcs) { impl_pmcs->bits[0] = (0xffffffff >> (32 - get_num_control_regs())); } /** * pfm_gen_powerpc_get_impl_pmds * * Set the appropriate bit in the impl_pmcs bitmask for each PMD that's * available. **/ static void pfm_gen_powerpc_get_impl_pmds(pfmlib_regmask_t *impl_pmds) { impl_pmds->bits[0] = (0xffffffff >> (32 - get_num_event_counters())); } /** * pfm_gen_powerpc_get_impl_counters * * Set the appropriate bit in the impl_counters bitmask for each counter * that's available on power4. * * For now, all PMDs are counters, so just call get_impl_pmds(). **/ static void pfm_gen_powerpc_get_impl_counters(pfmlib_regmask_t *impl_counters) { pfm_gen_powerpc_get_impl_pmds(impl_counters); } /** * pfm_gen_powerpc_get_hw_counter_width * * Return the number of usable bits in the PMD counters. **/ static void pfm_gen_powerpc_get_hw_counter_width(unsigned int *width) { *width = 64; } /** * pfm_gen_powerpc_get_event_desc * * Return the description for the specified event (if it has one). **/ static int pfm_gen_powerpc_get_event_desc(unsigned int event, char **desc) { *desc = strdup(get_long_desc(event)); return 0; } /** * pfm_gen_powerpc_get_event_mask_desc * * Return the description for the specified event-mask (if it has one). **/ static int pfm_gen_powerpc_get_event_mask_desc(unsigned int event, unsigned int mask, char **desc) { *desc = strdup(""); return 0; } static int pfm_gen_powerpc_get_event_mask_code(unsigned int event, unsigned int mask, unsigned int *code) { *code = 0; return 0; } static int pfm_gen_powerpc_get_cycle_event(pfmlib_event_t *e) { switch (gen_powerpc_support.pmu_type) { case PFMLIB_PPC970_PMU: e->event = PPC970_PME_PM_CYC; break; case PFMLIB_PPC970MP_PMU: e->event = PPC970MP_PME_PM_CYC; break; case PFMLIB_POWER4_PMU: e->event = POWER4_PME_PM_CYC; break; case PFMLIB_POWER5_PMU: e->event = POWER5_PME_PM_CYC; break; case PFMLIB_POWER5p_PMU: e->event = POWER5p_PME_PM_RUN_CYC; break; case PFMLIB_POWER6_PMU: e->event = POWER6_PME_PM_RUN_CYC; break; case PFMLIB_POWER7_PMU: e->event = POWER7_PME_PM_RUN_CYC; break; default: /* perhaps gen_powerpc_suport.pmu_type wasn't initialized? */ return PFMLIB_ERR_NOINIT; } e->num_masks = 0; e->unit_masks[0] = 0; return PFMLIB_SUCCESS; } static int pfm_gen_powerpc_get_inst_retired(pfmlib_event_t *e) { switch (gen_powerpc_support.pmu_type) { case PFMLIB_PPC970_PMU: e->event = PPC970_PME_PM_INST_CMPL; break; case PFMLIB_PPC970MP_PMU: e->event = PPC970MP_PME_PM_INST_CMPL; break; case PFMLIB_POWER4_PMU: e->event = POWER4_PME_PM_INST_CMPL; break; case PFMLIB_POWER5_PMU: e->event = POWER5_PME_PM_INST_CMPL; break; case PFMLIB_POWER5p_PMU: e->event = POWER5p_PME_PM_INST_CMPL; break; case PFMLIB_POWER6_PMU: e->event = POWER6_PME_PM_INST_CMPL; break; case PFMLIB_POWER7_PMU: e->event = POWER7_PME_PM_INST_CMPL; break; default: /* perhaps gen_powerpc_suport.pmu_type wasn't initialized? */ return PFMLIB_ERR_NOINIT; } e->num_masks = 0; e->unit_masks[0] = 0; return 0; } /** * gen_powerpc_support **/ pfm_pmu_support_t gen_powerpc_support = { /* the next 6 fields are initialized in pfm_gen_powerpc_pmu_detect */ .pmu_name = NULL, .pmu_type = PFMLIB_UNKNOWN_PMU, .pme_count = 0, .pmd_count = 0, .pmc_count = 0, .num_cnt = 0, .get_event_code = pfm_gen_powerpc_get_event_code, .get_event_name = pfm_gen_powerpc_get_event_name, .get_event_mask_name = pfm_gen_powerpc_get_event_mask_name, .get_event_counters = pfm_gen_powerpc_get_event_counters, .get_num_event_masks = pfm_gen_powerpc_get_num_event_masks, .dispatch_events = pfm_gen_powerpc_dispatch_events, .pmu_detect = pfm_gen_powerpc_pmu_detect, .get_impl_pmcs = pfm_gen_powerpc_get_impl_pmcs, .get_impl_pmds = pfm_gen_powerpc_get_impl_pmds, .get_impl_counters = pfm_gen_powerpc_get_impl_counters, .get_hw_counter_width = pfm_gen_powerpc_get_hw_counter_width, .get_event_desc = pfm_gen_powerpc_get_event_desc, .get_event_mask_desc = pfm_gen_powerpc_get_event_mask_desc, .get_event_mask_code = pfm_gen_powerpc_get_event_mask_code, .get_cycle_event = pfm_gen_powerpc_get_cycle_event, .get_inst_retired_event = pfm_gen_powerpc_get_inst_retired }; papi-5.5.1/src/libpfm-3.y/lib/intel_corei7_unc_events.h0000644000307100002310000010276113013651450022664 0ustar yarkhangraduate/* * Copyright (c) 2008 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ static pme_nhm_entry_t corei7_unc_pe[]={ /* * BEGIN uncore events */ { .pme_name = "UNC_CLK_UNHALTED", .pme_desc = "Uncore clockticks.", .pme_code = 0x0000, .pme_flags = PFMLIB_NHM_UNC_FIXED, }, { .pme_name = "UNC_DRAM_OPEN", .pme_desc = "DRAM open comamnds issued for read or write", .pme_code = 0x60, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CH0", .pme_udesc = "DRAM Channel 0 open comamnds issued for read or write", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "CH1", .pme_udesc = "DRAM Channel 1 open comamnds issued for read or write", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "CH2", .pme_udesc = "DRAM Channel 2 open comamnds issued for read or write", .pme_ucode = 0x04, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "UNC_DRAM_PAGE_CLOSE", .pme_desc = "DRAM page close due to idle timer expiration", .pme_code = 0x61, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CH0", .pme_udesc = "DRAM Channel 0 page close", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "CH1", .pme_udesc = "DRAM Channel 1 page close", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "CH2", .pme_udesc = "DRAM Channel 2 page close", .pme_ucode = 0x04, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "UNC_DRAM_PAGE_MISS", .pme_desc = "DRAM Channel 0 page miss", .pme_code = 0x62, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CH0", .pme_udesc = "DRAM Channel 0 page miss", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "CH1", .pme_udesc = "DRAM Channel 1 page miss", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "CH2", .pme_udesc = "DRAM Channel 2 page miss", .pme_ucode = 0x04, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "UNC_DRAM_PRE_ALL", .pme_desc = "DRAM Channel 0 precharge all commands", .pme_code = 0x66, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CH0", .pme_udesc = "DRAM Channel 0 precharge all commands", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "CH1", .pme_udesc = "DRAM Channel 1 precharge all commands", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "CH2", .pme_udesc = "DRAM Channel 2 precharge all commands", .pme_ucode = 0x04, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "UNC_DRAM_READ_CAS", .pme_desc = "DRAM Channel 0 read CAS commands", .pme_code = 0x63, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CH0", .pme_udesc = "DRAM Channel 0 read CAS commands", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "AUTOPRE_CH0", .pme_udesc = "DRAM Channel 0 read CAS auto page close commands", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "CH1", .pme_udesc = "DRAM Channel 1 read CAS commands", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "AUTOPRE_CH1", .pme_udesc = "DRAM Channel 1 read CAS auto page close commands", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "CH2", .pme_udesc = "DRAM Channel 2 read CAS commands", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "AUTOPRE_CH2", .pme_udesc = "DRAM Channel 2 read CAS auto page close commands", .pme_ucode = 0x20, .pme_uflags = 0, }, }, .pme_numasks = 6 }, { .pme_name = "UNC_DRAM_REFRESH", .pme_desc = "DRAM Channel 0 refresh commands", .pme_code = 0x65, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CH0", .pme_udesc = "DRAM Channel 0 refresh commands", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "CH1", .pme_udesc = "DRAM Channel 1 refresh commands", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "CH2", .pme_udesc = "DRAM Channel 2 refresh commands", .pme_ucode = 0x04, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "UNC_DRAM_WRITE_CAS", .pme_desc = "DRAM Channel 0 write CAS commands", .pme_code = 0x64, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CH0", .pme_udesc = "DRAM Channel 0 write CAS commands", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "AUTOPRE_CH0", .pme_udesc = "DRAM Channel 0 write CAS auto page close commands", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "CH1", .pme_udesc = "DRAM Channel 1 write CAS commands", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "AUTOPRE_CH1", .pme_udesc = "DRAM Channel 1 write CAS auto page close commands", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "CH2", .pme_udesc = "DRAM Channel 2 write CAS commands", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "AUTOPRE_CH2", .pme_udesc = "DRAM Channel 2 write CAS auto page close commands", .pme_ucode = 0x20, .pme_uflags = 0, }, }, .pme_numasks = 6 }, { .pme_name = "UNC_GQ_ALLOC", .pme_desc = "GQ read tracker requests", .pme_code = 0x03, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "READ_TRACKER", .pme_udesc = "GQ read tracker requests", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "RT_LLC_MISS", .pme_udesc = "GQ read tracker LLC misses", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "RT_TO_LLC_RESP", .pme_udesc = "GQ read tracker LLC requests", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "RT_TO_RTID_ACQUIRED", .pme_udesc = "GQ read tracker LLC miss to RTID acquired", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "WT_TO_RTID_ACQUIRED", .pme_udesc = "GQ write tracker LLC miss to RTID acquired", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "WRITE_TRACKER", .pme_udesc = "GQ write tracker LLC misses", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "PEER_PROBE_TRACKER", .pme_udesc = "GQ peer probe tracker requests", .pme_ucode = 0x40, .pme_uflags = 0, }, }, .pme_numasks = 7 }, { .pme_name = "UNC_GQ_CYCLES_FULL", .pme_desc = "Cycles GQ read tracker is full.", .pme_code = 0x00, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "READ_TRACKER", .pme_udesc = "Cycles GQ read tracker is full.", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "WRITE_TRACKER", .pme_udesc = "Cycles GQ write tracker is full.", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "PEER_PROBE_TRACKER", .pme_udesc = "Cycles GQ peer probe tracker is full.", .pme_ucode = 0x04, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "UNC_GQ_CYCLES_NOT_EMPTY", .pme_desc = "Cycles GQ read tracker is busy", .pme_code = 0x01, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "READ_TRACKER", .pme_udesc = "Cycles GQ read tracker is busy", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "WRITE_TRACKER", .pme_udesc = "Cycles GQ write tracker is busy", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "PEER_PROBE_TRACKER", .pme_udesc = "Cycles GQ peer probe tracker is busy", .pme_ucode = 0x04, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "UNC_GQ_DATA", .pme_desc = "Cycles GQ data is imported from Quickpath interface", .pme_code = 0x04, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "FROM_QPI", .pme_udesc = "Cycles GQ data is imported from Quickpath interface", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "FROM_QMC", .pme_udesc = "Cycles GQ data is imported from Quickpath memory interface", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "FROM_LLC", .pme_udesc = "Cycles GQ data is imported from LLC", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "FROM_CORES_02", .pme_udesc = "Cycles GQ data is imported from Cores 0 and 2", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "FROM_CORES_13", .pme_udesc = "Cycles GQ data is imported from Cores 1 and 3", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "TO_QPI_QMC", .pme_udesc = "Cycles GQ data sent to the QPI or QMC", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "TO_LLC", .pme_udesc = "Cycles GQ data sent to LLC", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "TO_CORES", .pme_udesc = "Cycles GQ data sent to cores", .pme_ucode = 0x04, .pme_uflags = 0, }, }, .pme_numasks = 8 }, { .pme_name = "UNC_LLC_HITS", .pme_desc = "Number of LLC read hits", .pme_code = 0x08, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "READ", .pme_udesc = "Number of LLC read hits", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "WRITE", .pme_udesc = "Number of LLC write hits", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "PROBE", .pme_udesc = "Number of LLC peer probe hits", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "ANY", .pme_udesc = "Number of LLC hits", .pme_ucode = 0x03, .pme_uflags = 0, }, }, .pme_numasks = 4 }, { .pme_name = "UNC_LLC_LINES_IN", .pme_desc = "LLC lines allocated in M state", .pme_code = 0x0A, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "M_STATE", .pme_udesc = "LLC lines allocated in M state", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "E_STATE", .pme_udesc = "LLC lines allocated in E state", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "S_STATE", .pme_udesc = "LLC lines allocated in S state", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "F_STATE", .pme_udesc = "LLC lines allocated in F state", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "ANY", .pme_udesc = "LLC lines allocated", .pme_ucode = 0x0F, .pme_uflags = 0, }, }, .pme_numasks = 5 }, { .pme_name = "UNC_LLC_LINES_OUT", .pme_desc = "LLC lines victimized in M state", .pme_code = 0x0B, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "M_STATE", .pme_udesc = "LLC lines victimized in M state", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "E_STATE", .pme_udesc = "LLC lines victimized in E state", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "S_STATE", .pme_udesc = "LLC lines victimized in S state", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "I_STATE", .pme_udesc = "LLC lines victimized in I state", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "F_STATE", .pme_udesc = "LLC lines victimized in F state", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "ANY", .pme_udesc = "LLC lines victimized", .pme_ucode = 0x1F, .pme_uflags = 0, }, }, .pme_numasks = 6 }, { .pme_name = "UNC_LLC_MISS", .pme_desc = "Number of LLC read misses", .pme_code = 0x09, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "READ", .pme_udesc = "Number of LLC read misses", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "WRITE", .pme_udesc = "Number of LLC write misses", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "PROBE", .pme_udesc = "Number of LLC peer probe misses", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "ANY", .pme_udesc = "Number of LLC misses", .pme_ucode = 0x03, .pme_uflags = 0, }, }, .pme_numasks = 4 }, { .pme_name = "UNC_QHL_ADDRESS_CONFLICTS", .pme_desc = "QHL 2 way address conflicts", .pme_code = 0x24, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "2WAY", .pme_udesc = "QHL 2 way address conflicts", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "3WAY", .pme_udesc = "QHL 3 way address conflicts", .pme_ucode = 0x04, .pme_uflags = 0, }, }, .pme_numasks = 2 }, { .pme_name = "UNC_QHL_CONFLICT_CYCLES", .pme_desc = "QHL IOH Tracker conflict cycles", .pme_code = 0x25, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "IOH", .pme_udesc = "QHL IOH Tracker conflict cycles", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "REMOTE", .pme_udesc = "QHL Remote Tracker conflict cycles", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "LOCAL", .pme_udesc = "QHL Local Tracker conflict cycles", .pme_ucode = 0x04, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "UNC_QHL_CYCLES_FULL", .pme_desc = "Cycles QHL Remote Tracker is full", .pme_code = 0x21, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "REMOTE", .pme_udesc = "Cycles QHL Remote Tracker is full", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "LOCAL", .pme_udesc = "Cycles QHL Local Tracker is full", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "IOH", .pme_udesc = "Cycles QHL IOH Tracker is full", .pme_ucode = 0x01, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "UNC_QHL_CYCLES_NOT_EMPTY", .pme_desc = "Cycles QHL Tracker is not empty", .pme_code = 0x22, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "IOH", .pme_udesc = "Cycles QHL IOH is busy", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "REMOTE", .pme_udesc = "Cycles QHL Remote Tracker is busy", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "LOCAL", .pme_udesc = "Cycles QHL Local Tracker is busy", .pme_ucode = 0x04, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "UNC_QHL_FRC_ACK_CNFLTS", .pme_desc = "QHL FrcAckCnflts sent to local home", .pme_code = 0x33, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "LOCAL", .pme_udesc = "QHL FrcAckCnflts sent to local home", .pme_ucode = 0x04, .pme_uflags = 0, }, }, .pme_numasks = 1 }, { .pme_name = "UNC_QHL_OCCUPANCY", .pme_desc = "Cycles QHL Tracker Allocate to Deallocate Read Occupancy", .pme_code = 0x23, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "IOH", .pme_udesc = "Cycles QHL IOH Tracker Allocate to Deallocate Read Occupancy", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "REMOTE", .pme_udesc = "Cycles QHL Remote Tracker Allocate to Deallocate Read Occupancy", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "LOCAL", .pme_udesc = "Cycles QHL Local Tracker Allocate to Deallocate Read Occupancy", .pme_ucode = 0x04, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "UNC_QHL_REQUESTS", .pme_desc = "Quickpath Home Logic local read requests", .pme_code = 0x20, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "LOCAL_READS", .pme_udesc = "Quickpath Home Logic local read requests", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "LOCAL_WRITES", .pme_udesc = "Quickpath Home Logic local write requests", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "REMOTE_READS", .pme_udesc = "Quickpath Home Logic remote read requests", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "IOH_READS", .pme_udesc = "Quickpath Home Logic IOH read requests", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "IOH_WRITES", .pme_udesc = "Quickpath Home Logic IOH write requests", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "REMOTE_WRITES", .pme_udesc = "Quickpath Home Logic remote write requests", .pme_ucode = 0x08, .pme_uflags = 0, }, }, .pme_numasks = 6 }, { .pme_name = "UNC_QHL_TO_QMC_BYPASS", .pme_desc = "Number of requests to QMC that bypass QHL", .pme_code = 0x0126, .pme_flags = PFMLIB_NHM_UNC, }, { .pme_name = "UNC_QMC_BUSY", .pme_desc = "Cycles QMC busy with a read request", .pme_code = 0x29, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "READ_CH0", .pme_udesc = "Cycles QMC channel 0 busy with a read request", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "READ_CH1", .pme_udesc = "Cycles QMC channel 1 busy with a read request", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "READ_CH2", .pme_udesc = "Cycles QMC channel 2 busy with a read request", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "WRITE_CH0", .pme_udesc = "Cycles QMC channel 0 busy with a write request", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "WRITE_CH1", .pme_udesc = "Cycles QMC channel 1 busy with a write request", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "WRITE_CH2", .pme_udesc = "Cycles QMC channel 2 busy with a write request", .pme_ucode = 0x20, .pme_uflags = 0, }, }, .pme_numasks = 6 }, { .pme_name = "UNC_QMC_CANCEL", .pme_desc = "QMC cancels", .pme_code = 0x30, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CH0", .pme_udesc = "QMC channel 0 cancels", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "CH1", .pme_udesc = "QMC channel 1 cancels", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "CH2", .pme_udesc = "QMC channel 2 cancels", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "ANY", .pme_udesc = "QMC cancels", .pme_ucode = 0x07, .pme_uflags = 0, }, }, .pme_numasks = 4 }, { .pme_name = "UNC_QMC_CRITICAL_PRIORITY_READS", .pme_desc = "QMC critical priority read requests", .pme_code = 0x2E, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CH0", .pme_udesc = "QMC channel 0 critical priority read requests", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "CH1", .pme_udesc = "QMC channel 1 critical priority read requests", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "CH2", .pme_udesc = "QMC channel 2 critical priority read requests", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "ANY", .pme_udesc = "QMC critical priority read requests", .pme_ucode = 0x07, .pme_uflags = 0, }, }, .pme_numasks = 4 }, { .pme_name = "UNC_QMC_HIGH_PRIORITY_READS", .pme_desc = "QMC high priority read requests", .pme_code = 0x2D, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CH0", .pme_udesc = "QMC channel 0 high priority read requests", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "CH1", .pme_udesc = "QMC channel 1 high priority read requests", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "CH2", .pme_udesc = "QMC channel 2 high priority read requests", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "ANY", .pme_udesc = "QMC high priority read requests", .pme_ucode = 0x07, .pme_uflags = 0, }, }, .pme_numasks = 4 }, { .pme_name = "UNC_QMC_ISOC_FULL", .pme_desc = "Cycles DRAM full with isochronous read requests", .pme_code = 0x28, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "READ_CH0", .pme_udesc = "Cycles DRAM channel 0 full with isochronous read requests", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "READ_CH1", .pme_udesc = "Cycles DRAM channel 1 full with isochronous read requests", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "READ_CH2", .pme_udesc = "Cycles DRAM channel 2 full with ISOC read requests", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "WRITE_CH0", .pme_udesc = "Cycles DRAM channel 0 full with ISOC write requests", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "WRITE_CH1", .pme_udesc = "Cycles DRAM channel 1 full with ISOC write requests", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "WRITE_CH2", .pme_udesc = "Cycles DRAM channel 2 full with ISOC write requests", .pme_ucode = 0x20, .pme_uflags = 0, }, }, .pme_numasks = 6 }, { .pme_name = "UNC_IMC_ISOC_OCCUPANCY", .pme_desc = "IMC isochronous (ISOC) Read Occupancy", .pme_code = 0x2B, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CH0", .pme_udesc = "IMC channel 0 isochronous read request occupancy", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "CH1", .pme_udesc = "IMC channel 1 isochronous read request occupancy", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "CH2", .pme_udesc = "IMC channel 2 isochronous read request occupancy", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "ANY", .pme_udesc = "IMC any channel isochronous read request occupancy", .pme_ucode = 0x07, .pme_uflags = 0, }, }, .pme_numasks = 4 }, { .pme_name = "UNC_QMC_NORMAL_FULL", .pme_desc = "Cycles DRAM full with normal read requests", .pme_code = 0x27, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "READ_CH0", .pme_udesc = "Cycles DRAM channel 0 full with normal read requests", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "READ_CH1", .pme_udesc = "Cycles DRAM channel 1 full with normal read requests", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "READ_CH2", .pme_udesc = "Cycles DRAM channel 2 full with normal read requests", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "WRITE_CH0", .pme_udesc = "Cycles DRAM channel 0 full with normal write requests", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "WRITE_CH1", .pme_udesc = "Cycles DRAM channel 1 full with normal write requests", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "WRITE_CH2", .pme_udesc = "Cycles DRAM channel 2 full with normal write requests", .pme_ucode = 0x20, .pme_uflags = 0, }, }, .pme_numasks = 6 }, { .pme_name = "UNC_QMC_NORMAL_READS", .pme_desc = "QMC normal read requests", .pme_code = 0x2C, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CH0", .pme_udesc = "QMC channel 0 normal read requests", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "CH1", .pme_udesc = "QMC channel 1 normal read requests", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "CH2", .pme_udesc = "QMC channel 2 normal read requests", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "ANY", .pme_udesc = "QMC normal read requests", .pme_ucode = 0x07, .pme_uflags = 0, }, }, .pme_numasks = 4 }, { .pme_name = "UNC_QMC_OCCUPANCY", .pme_desc = "QMC Occupancy", .pme_code = 0x2A, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CH0", .pme_udesc = "IMC channel 0 normal read request occupancy", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "CH1", .pme_udesc = "IMC channel 1 normal read request occupancy", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "CH2", .pme_udesc = "IMC channel 2 normal read request occupancy", .pme_ucode = 0x04, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "UNC_QMC_PRIORITY_UPDATES", .pme_desc = "QMC priority updates", .pme_code = 0x31, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CH0", .pme_udesc = "QMC channel 0 priority updates", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "CH1", .pme_udesc = "QMC channel 1 priority updates", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "CH2", .pme_udesc = "QMC channel 2 priority updates", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "ANY", .pme_udesc = "QMC priority updates", .pme_ucode = 0x07, .pme_uflags = 0, }, }, .pme_numasks = 4 }, { .pme_name = "UNC_QMC_WRITES", .pme_desc = "QMC full cache line writes", .pme_code = 0x2F, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "FULL_CH0", .pme_udesc = "QMC channel 0 full cache line writes", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "FULL_CH1", .pme_udesc = "QMC channel 1 full cache line writes", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "FULL_CH2", .pme_udesc = "QMC channel 2 full cache line writes", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "FULL_ANY", .pme_udesc = "QMC full cache line writes", .pme_ucode = 0x07, .pme_uflags = 0, }, { .pme_uname = "PARTIAL_CH0", .pme_udesc = "QMC channel 0 partial cache line writes", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "PARTIAL_CH1", .pme_udesc = "QMC channel 1 partial cache line writes", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "PARTIAL_CH2", .pme_udesc = "QMC channel 2 partial cache line writes", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "PARTIAL_ANY", .pme_udesc = "QMC partial cache line writes", .pme_ucode = 0x38, .pme_uflags = 0, }, }, .pme_numasks = 8 }, { .pme_name = "UNC_QPI_RX_NO_PPT_CREDIT", .pme_desc = "Link 0 snoop stalls due to no PPT entry", .pme_code = 0x43, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "STALLS_LINK_0", .pme_udesc = "Link 0 snoop stalls due to no PPT entry", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "STALLS_LINK_1", .pme_udesc = "Link 1 snoop stalls due to no PPT entry", .pme_ucode = 0x02, .pme_uflags = 0, }, }, .pme_numasks = 2 }, { .pme_name = "UNC_QPI_TX_HEADER", .pme_desc = "Cycles link 0 outbound header busy", .pme_code = 0x42, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "BUSY_LINK_0", .pme_udesc = "Cycles link 0 outbound header busy", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "BUSY_LINK_1", .pme_udesc = "Cycles link 1 outbound header busy", .pme_ucode = 0x08, .pme_uflags = 0, }, }, .pme_numasks = 2 }, { .pme_name = "UNC_QPI_TX_STALLED_MULTI_FLIT", .pme_desc = "Cycles QPI outbound link 0 DRS stalled", .pme_code = 0x41, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "DRS_LINK_0", .pme_udesc = "Cycles QPI outbound link 0 DRS stalled", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "NCB_LINK_0", .pme_udesc = "Cycles QPI outbound link 0 NCB stalled", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "NCS_LINK_0", .pme_udesc = "Cycles QPI outbound link 0 NCS stalled", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "DRS_LINK_1", .pme_udesc = "Cycles QPI outbound link 1 DRS stalled", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "NCB_LINK_1", .pme_udesc = "Cycles QPI outbound link 1 NCB stalled", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "NCS_LINK_1", .pme_udesc = "Cycles QPI outbound link 1 NCS stalled", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "LINK_0", .pme_udesc = "Cycles QPI outbound link 0 multi flit stalled", .pme_ucode = 0x07, .pme_uflags = 0, }, { .pme_uname = "LINK_1", .pme_udesc = "Cycles QPI outbound link 1 multi flit stalled", .pme_ucode = 0x38, .pme_uflags = 0, }, }, .pme_numasks = 8 }, { .pme_name = "UNC_QPI_TX_STALLED_SINGLE_FLIT", .pme_desc = "Cycles QPI outbound link 0 HOME stalled", .pme_code = 0x40, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "HOME_LINK_0", .pme_udesc = "Cycles QPI outbound link 0 HOME stalled", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "SNOOP_LINK_0", .pme_udesc = "Cycles QPI outbound link 0 SNOOP stalled", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "NDR_LINK_0", .pme_udesc = "Cycles QPI outbound link 0 NDR stalled", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "HOME_LINK_1", .pme_udesc = "Cycles QPI outbound link 1 HOME stalled", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "SNOOP_LINK_1", .pme_udesc = "Cycles QPI outbound link 1 SNOOP stalled", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "NDR_LINK_1", .pme_udesc = "Cycles QPI outbound link 1 NDR stalled", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "LINK_0", .pme_udesc = "Cycles QPI outbound link 0 single flit stalled", .pme_ucode = 0x07, .pme_uflags = 0, }, { .pme_uname = "LINK_1", .pme_udesc = "Cycles QPI outbound link 1 single flit stalled", .pme_ucode = 0x38, .pme_uflags = 0, }, }, .pme_numasks = 8 }, { .pme_name = "UNC_SNP_RESP_TO_LOCAL_HOME", .pme_desc = "Local home snoop response - LLC does not have cache line", .pme_code = 0x06, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "I_STATE", .pme_udesc = "Local home snoop response - LLC does not have cache line", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "S_STATE", .pme_udesc = "Local home snoop response - LLC has cache line in S state", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "FWD_S_STATE", .pme_udesc = "Local home snoop response - LLC forwarding cache line in S state.", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "FWD_I_STATE", .pme_udesc = "Local home snoop response - LLC has forwarded a modified cache line", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "CONFLICT", .pme_udesc = "Local home conflict snoop response", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "WB", .pme_udesc = "Local home snoop response - LLC has cache line in the M state", .pme_ucode = 0x20, .pme_uflags = 0, }, }, .pme_numasks = 6 }, { .pme_name = "UNC_SNP_RESP_TO_REMOTE_HOME", .pme_desc = "Remote home snoop response - LLC does not have cache line", .pme_code = 0x07, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "I_STATE", .pme_udesc = "Remote home snoop response - LLC does not have cache line", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "S_STATE", .pme_udesc = "Remote home snoop response - LLC has cache line in S state", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "FWD_S_STATE", .pme_udesc = "Remote home snoop response - LLC forwarding cache line in S state.", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "FWD_I_STATE", .pme_udesc = "Remote home snoop response - LLC has forwarded a modified cache line", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "CONFLICT", .pme_udesc = "Remote home conflict snoop response", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "WB", .pme_udesc = "Remote home snoop response - LLC has cache line in the M state", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "HITM", .pme_udesc = "Remote home snoop response - LLC HITM", .pme_ucode = 0x24, .pme_uflags = 0, }, }, .pme_numasks = 7 }, }; #define PME_COREI7_UNC_EVENT_COUNT (sizeof(corei7_unc_pe)/sizeof(pme_nhm_entry_t)) papi-5.5.1/src/libpfm-3.y/lib/gen_ia32_events.h0000644000307100002310000000675413013651450021030 0ustar yarkhangraduate/* * Copyright (c) 2006-2007 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ /* * architected events for architectural perfmon v1 and v2 as defined by the IA-32 developer's manual * Vol 3B, table 18-6 (May 2007) */ static pme_gen_ia32_entry_t gen_ia32_all_pe[]={ {.pme_name = "UNHALTED_CORE_CYCLES", .pme_code = 0x003c, .pme_fixed = 17, .pme_desc = "count core clock cycles whenever the clock signal on the specific core is running (not halted)" }, {.pme_name = "INSTRUCTIONS_RETIRED", .pme_code = 0x00c0, .pme_fixed = 16, .pme_desc = "count the number of instructions at retirement. For instructions that consists of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction", }, {.pme_name = "UNHALTED_REFERENCE_CYCLES", .pme_code = 0x013c, .pme_fixed = 18, .pme_desc = "count reference clock cycles while the clock signal on the specific core is running. The reference clock operates at a fixed frequency, irrespective of core freqeuncy changes due to performance state transitions", }, {.pme_name = "LAST_LEVEL_CACHE_REFERENCES", .pme_code = 0x4f2e, .pme_desc = "count each request originating from the core to reference a cache line in the last level cache. The count may include speculation, but excludes cache line fills due to hardware prefetch", }, {.pme_name = "LAST_LEVEL_CACHE_MISSES", .pme_code = 0x412e, .pme_desc = "count each cache miss condition for references to the last level cache. The event count may include speculation, but excludes cache line fills due to hardware prefetch", }, {.pme_name = "BRANCH_INSTRUCTIONS_RETIRED", .pme_code = 0x00c4, .pme_desc = "count branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instruction", }, {.pme_name = "MISPREDICTED_BRANCH_RETIRED", .pme_code = 0x00c5, .pme_desc = "count mispredicted branch instructions at retirement. Specifically, this event counts at retirement of the last micro-op of a branch instruction in the architectural path of the execution and experienced misprediction in the branch prediction hardware", } }; #define PME_GEN_IA32_UNHALTED_CORE_CYCLES 0 #define PME_GEN_IA32_INSTRUCTIONS_RETIRED 1 #define PFMLIB_GEN_IA32_EVENT_COUNT (sizeof(gen_ia32_all_pe)/sizeof(pme_gen_ia32_entry_t)) papi-5.5.1/src/libpfm-3.y/lib/pfmlib_power5_priv.h0000644000307100002310000000117313013651450021655 0ustar yarkhangraduate/****************************/ /* THIS IS OPEN SOURCE CODE */ /****************************/ #ifndef __PFMLIB_POWER5_PRIV_H__ #define __PFMLIB_POWER5_PRIV_H__ /* * File: pfmlib_power5_priv.h * CVS: * Author: Corey Ashford * cjashfor@us.ibm.com * Mods: * * * (C) Copyright IBM Corporation, 2007. All Rights Reserved. * Contributed by Corey Ashford * * Note: This code was automatically generated and should not be modified by * hand. * */ #define POWER5_NUM_EVENT_COUNTERS 6 #define POWER5_NUM_GROUP_VEC 3 #define POWER5_NUM_CONTROL_REGS 3 #endif papi-5.5.1/src/libpfm-3.y/lib/i386_p6_events.h0000644000307100002310000010064113013651450020525 0ustar yarkhangraduate/* * Copyright (c) 2005-2007 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #define I386_P6_MESI_UMASKS \ .pme_flags = PFMLIB_I386_P6_UMASK_COMBO, \ .pme_numasks = 4, \ .pme_umasks = { \ { .pme_uname = "I", \ .pme_udesc = "invalid state", \ .pme_ucode = 0x1 \ }, \ { .pme_uname = "S", \ .pme_udesc = "shared state", \ .pme_ucode = 0x2 \ }, \ { .pme_uname = "E", \ .pme_udesc = "exclusive state", \ .pme_ucode = 0x4 \ }, \ { .pme_uname = "M", \ .pme_udesc = "modified state", \ .pme_ucode = 0x8 \ }} #define I386_PM_MESI_PREFETCH_UMASKS \ .pme_flags = PFMLIB_I386_P6_UMASK_COMBO, \ .pme_numasks = 7, \ .pme_umasks = { \ { .pme_uname = "I", \ .pme_udesc = "invalid state", \ .pme_ucode = 0x1 \ }, \ { .pme_uname = "S", \ .pme_udesc = "shared state", \ .pme_ucode = 0x2 \ }, \ { .pme_uname = "E", \ .pme_udesc = "exclusive state", \ .pme_ucode = 0x4 \ }, \ { .pme_uname = "M", \ .pme_udesc = "modified state", \ .pme_ucode = 0x8 \ }, \ { .pme_uname = "EXCL_HW_PREFETCH", \ .pme_udesc = "exclude hardware prefetched lines", \ .pme_ucode = 0x0 \ }, \ { .pme_uname = "ONLY_HW_PREFETCH", \ .pme_udesc = "only hardware prefetched lines", \ .pme_ucode = 0x1 << 4 \ }, \ { .pme_uname = "NON_HW_PREFETCH", \ .pme_udesc = "non hardware prefetched lines", \ .pme_ucode = 0x2 << 4 \ }} #define I386_P6_PII_ONLY_PME \ {.pme_name = "MMX_INSTR_EXEC",\ .pme_code = 0xb0,\ .pme_desc = "Number of MMX instructions executed"\ },\ {.pme_name = "MMX_INSTR_RET",\ .pme_code = 0xce,\ .pme_desc = "Number of MMX instructions retired"\ }\ #define I386_P6_PII_PIII_PME \ {.pme_name = "MMX_SAT_INSTR_EXEC",\ .pme_code = 0xb1,\ .pme_desc = "Number of MMX saturating instructions executed"\ },\ {.pme_name = "MMX_UOPS_EXEC",\ .pme_code = 0xb2,\ .pme_desc = "Number of MMX micro-ops executed"\ },\ {.pme_name = "MMX_INSTR_TYPE_EXEC",\ .pme_code = 0xb3,\ .pme_desc = "Number of MMX instructions executed by type",\ .pme_flags = PFMLIB_I386_P6_UMASK_COMBO, \ .pme_numasks = 6, \ .pme_umasks = { \ { .pme_uname = "MUL", \ .pme_udesc = "MMX packed multiply instructions executed", \ .pme_ucode = 0x1 \ }, \ { .pme_uname = "SHIFT", \ .pme_udesc = "MMX packed shift instructions executed", \ .pme_ucode = 0x2 \ }, \ { .pme_uname = "PACK", \ .pme_udesc = "MMX pack operation instructions executed", \ .pme_ucode = 0x4 \ }, \ { .pme_uname = "UNPACK", \ .pme_udesc = "MMX unpack operation instructions executed", \ .pme_ucode = 0x8 \ }, \ { .pme_uname = "LOGICAL", \ .pme_udesc = "MMX packed logical instructions executed", \ .pme_ucode = 0x10 \ }, \ { .pme_uname = "ARITH", \ .pme_udesc = "MMX packed arithmetic instructions executed", \ .pme_ucode = 0x20 \ } \ }\ },\ {.pme_name = "FP_MMX_TRANS",\ .pme_code = 0xcc,\ .pme_desc = "Number of MMX transitions",\ .pme_numasks = 2, \ .pme_umasks = { \ { .pme_uname = "TO_FP", \ .pme_udesc = "from MMX instructions to floating-point instructions", \ .pme_ucode = 0x00 \ }, \ { .pme_uname = "TO_MMX", \ .pme_udesc = "from floating-point instructions to MMX instructions", \ .pme_ucode = 0x01 \ }\ }\ },\ {.pme_name = "MMX_ASSIST",\ .pme_code = 0xcd,\ .pme_desc = "Number of MMX micro-ops executed"\ },\ {.pme_name = "SEG_RENAME_STALLS",\ .pme_code = 0xd4,\ .pme_desc = "Number of Segment Register Renaming Stalls", \ .pme_flags = PFMLIB_I386_P6_UMASK_COMBO, \ .pme_numasks = 4, \ .pme_umasks = { \ { .pme_uname = "ES", \ .pme_udesc = "Segment register ES", \ .pme_ucode = 0x1 \ }, \ { .pme_uname = "DS", \ .pme_udesc = "Segment register DS", \ .pme_ucode = 0x2 \ }, \ { .pme_uname = "FS", \ .pme_udesc = "Segment register FS", \ .pme_ucode = 0x4 \ }, \ { .pme_uname = "GS", \ .pme_udesc = "Segment register GS", \ .pme_ucode = 0x8 \ } \ }\ },\ {.pme_name = "SEG_REG_RENAMES",\ .pme_code = 0xd5,\ .pme_desc = "Number of Segment Register Renames", \ .pme_flags = PFMLIB_I386_P6_UMASK_COMBO, \ .pme_numasks = 4, \ .pme_umasks = { \ { .pme_uname = "ES", \ .pme_udesc = "Segment register ES", \ .pme_ucode = 0x1 \ }, \ { .pme_uname = "DS", \ .pme_udesc = "Segment register DS", \ .pme_ucode = 0x2 \ }, \ { .pme_uname = "FS", \ .pme_udesc = "Segment register FS", \ .pme_ucode = 0x4 \ }, \ { .pme_uname = "GS", \ .pme_udesc = "Segment register GS", \ .pme_ucode = 0x8 \ } \ }\ },\ {.pme_name = "RET_SEG_RENAMES",\ .pme_code = 0xd6,\ .pme_desc = "Number of segment register rename events retired"\ } \ #define I386_P6_PIII_PME \ {.pme_name = "EMON_KNI_PREF_DISPATCHED",\ .pme_code = 0x07,\ .pme_desc = "Number of Streaming SIMD extensions prefetch/weakly-ordered instructions dispatched " \ "(speculative prefetches are included in counting). Pentium III and later",\ .pme_numasks = 4, \ .pme_umasks = { \ { .pme_uname = "NTA", \ .pme_udesc = "prefetch NTA", \ .pme_ucode = 0x00 \ }, \ { .pme_uname = "T1", \ .pme_udesc = "prefetch T1", \ .pme_ucode = 0x01 \ }, \ { .pme_uname = "T2", \ .pme_udesc = "prefetch T2", \ .pme_ucode = 0x02 \ }, \ { .pme_uname = "WEAK", \ .pme_udesc = "weakly ordered stores", \ .pme_ucode = 0x03 \ } \ } \ },\ {.pme_name = "EMON_KNI_PREF_MISS",\ .pme_code = 0x4b,\ .pme_desc = "Number of prefetch/weakly-ordered instructions that miss all caches. Pentium III and later",\ .pme_numasks = 4, \ .pme_umasks = { \ { .pme_uname = "NTA", \ .pme_udesc = "prefetch NTA", \ .pme_ucode = 0x00 \ }, \ { .pme_uname = "T1", \ .pme_udesc = "prefetch T1", \ .pme_ucode = 0x01 \ }, \ { .pme_uname = "T2", \ .pme_udesc = "prefetch T2", \ .pme_ucode = 0x02 \ }, \ { .pme_uname = "WEAK", \ .pme_udesc = "weakly ordered stores", \ .pme_ucode = 0x03 \ } \ } \ } \ #define I386_P6_CPU_CLK_UNHALTED \ {.pme_name = "CPU_CLK_UNHALTED",\ .pme_code = 0x79,\ .pme_desc = "Number cycles during which the processor is not halted"\ }\ #define I386_P6_NOT_PM_PME \ {.pme_name = "L2_LD",\ .pme_code = 0x29,\ .pme_desc = "Number of L2 data loads. This event indicates that a normal, unlocked, load memory access "\ "was received by the L2. It includes only L2 cacheable memory accesses; it does not include I/O "\ "accesses, other non-memory accesses, or memory accesses such as UC/WT memory accesses. It does include "\ "L2 cacheable TLB miss memory accesses",\ I386_P6_MESI_UMASKS\ },\ {.pme_name = "L2_LINES_IN",\ .pme_code = 0x24,\ .pme_desc = "Number of lines allocated in the L2"\ },\ {.pme_name = "L2_LINES_OUT",\ .pme_code = 0x26,\ .pme_desc = "Number of lines removed from the L2 for any reason"\ },\ {.pme_name = "L2_M_LINES_OUTM",\ .pme_code = 0x27,\ .pme_desc = "Number of modified lines removed from the L2 for any reason"\ }\ #define I386_P6_PIII_NOT_PM_PME \ {.pme_name = "EMON_KNI_INST_RETIRED",\ .pme_code = 0xd8,\ .pme_desc = "Number of SSE instructions retired. Pentium III and later",\ .pme_numasks = 2, \ .pme_umasks = { \ { .pme_uname = "PACKED_SCALAR", \ .pme_udesc = "packed and scalar instructions", \ .pme_ucode = 0x00 \ }, \ { .pme_uname = "SCALAR", \ .pme_udesc = "scalar only", \ .pme_ucode = 0x01 \ } \ } \ },\ {.pme_name = "EMON_KNI_COMP_INST_RET",\ .pme_code = 0xd9,\ .pme_desc = "Number of SSE computation instructions retired. Pentium III and later",\ .pme_numasks = 2, \ .pme_umasks = { \ { .pme_uname = "PACKED_SCALAR", \ .pme_udesc = "packed and scalar instructions", \ .pme_ucode = 0x00 \ }, \ { .pme_uname = "SCALAR", \ .pme_udesc = "scalar only", \ .pme_ucode = 0x01 \ } \ } \ }\ #define I386_P6_COMMON_PME \ {.pme_name = "INST_RETIRED",\ .pme_code = 0xc0,\ .pme_desc = "Number of instructions retired"\ },\ {.pme_name = "DATA_MEM_REFS",\ .pme_code = 0x43,\ .pme_desc = "All loads from any memory type. All stores to any memory type"\ "Each part of a split is counted separately. The internal logic counts not only memory loads and stores"\ " but also internal retries. 80-bit floating point accesses are double counted, since they are decomposed"\ " into a 16-bit exponent load and a 64-bit mantissa load. Memory accesses are only counted when they are "\ " actually performed (such as a load that gets squashed because a previous cache miss is outstanding to the"\ " same address, and which finally gets performe, is only counted once). Does ot include I/O accesses or other"\ " non-memory accesses"\ },\ {.pme_name = "DCU_LINES_IN",\ .pme_code = 0x45,\ .pme_desc = "Total lines allocated in the DCU"\ },\ {.pme_name = "DCU_M_LINES_IN",\ .pme_code = 0x46,\ .pme_desc = "Number of M state lines allocated in the DCU"\ },\ {.pme_name = "DCU_M_LINES_OUT",\ .pme_code = 0x47,\ .pme_desc = "Number of M state lines evicted from the DCU. This includes evictions via snoop HITM, intervention"\ " or replacement"\ },\ {.pme_name = "DCU_MISS_OUTSTANDING",\ .pme_code = 0x48,\ .pme_desc = "Weighted number of cycle while a DCU miss is outstanding, incremented by the number of cache misses"\ " at any particular time. Cacheable read requests only are considered. Uncacheable requests are excluded"\ " Read-for-ownerships are counted, as well as line fills, invalidates, and stores"\ },\ {.pme_name = "IFU_IFETCH",\ .pme_code = 0x80,\ .pme_desc = "Number of instruction fetches, both cacheable and noncacheable including UC fetches"\ },\ {.pme_name = "IFU_IFETCH_MISS",\ .pme_code = 0x81,\ .pme_desc = "Number of instruction fetch misses. All instructions fetches that do not hit the IFU (i.e., that"\ " produce memory requests). Includes UC accesses"\ },\ {.pme_name = "ITLB_MISS",\ .pme_code = 0x85,\ .pme_desc = "Number of ITLB misses"\ },\ {.pme_name = "IFU_MEM_STALL",\ .pme_code = 0x86,\ .pme_desc = "Number of cycles instruction fetch is stalled for any reason. Includs IFU cache misses, ITLB misses,"\ " ITLB faults, and other minor stalls"\ },\ {.pme_name = "ILD_STALL",\ .pme_code = 0x87,\ .pme_desc = "Number of cycles that the instruction length decoder is stalled"\ },\ {.pme_name = "L2_IFETCH",\ .pme_code = 0x28,\ .pme_desc = "Number of L2 instruction fetches. This event indicates that a normal instruction fetch was received by"\ " the L2. The count includes only L2 cacheable instruction fetches: it does not include UC instruction fetches"\ " It does not include ITLB miss accesses",\ I386_P6_MESI_UMASKS \ }, \ {.pme_name = "L2_ST",\ .pme_code = 0x2a,\ .pme_desc = "Number of L2 data stores. This event indicates that a normal, unlocked, store memory access "\ "was received by the L2. Specifically, it indictes that the DCU sent a read-for ownership request to " \ "the L2. It also includes Invalid to Modified reqyests sent by the DCU to the L2. " \ "It includes only L2 cacheable memory accesses; it does not include I/O " \ "accesses, other non-memory accesses, or memory accesses such as UC/WT memory accesses. It does include " \ "L2 cacheable TLB miss memory accesses", \ I386_P6_MESI_UMASKS \ },\ {.pme_name = "L2_M_LINES_INM",\ .pme_code = 0x25,\ .pme_desc = "Number of modified lines allocated in the L2"\ },\ {.pme_name = "L2_RQSTS",\ .pme_code = 0x2e,\ .pme_desc = "Total number of L2 requests",\ I386_P6_MESI_UMASKS \ },\ {.pme_name = "L2_ADS",\ .pme_code = 0x21,\ .pme_desc = "Number of L2 address strobes"\ },\ {.pme_name = "L2_DBUS_BUSY",\ .pme_code = 0x22,\ .pme_desc = "Number of cycles during which the L2 cache data bus was busy"\ },\ {.pme_name = "L2_DBUS_BUSY_RD",\ .pme_code = 0x23,\ .pme_desc = "Number of cycles during which the data bus was busy transferring read data from L2 to the processor"\ },\ {.pme_name = "BUS_DRDY_CLOCKS",\ .pme_code = 0x62,\ .pme_desc = "Number of clocks during which DRDY# is asserted. " \ "Utilization of the external system data bus during data transfers", \ .pme_numasks = 2, \ .pme_umasks = { \ { .pme_uname = "SELF", \ .pme_udesc = "clocks when processor is driving bus", \ .pme_ucode = 0x00 \ }, \ { .pme_uname = "ANY", \ .pme_udesc = "clocks when any agent is driving bus", \ .pme_ucode = 0x20 \ } \ } \ },\ {.pme_name = "BUS_LOCK_CLOCKS",\ .pme_code = 0x63,\ .pme_desc = "Number of clocks during which LOCK# is asserted on the external system bus", \ .pme_numasks = 2, \ .pme_umasks = { \ { .pme_uname = "SELF", \ .pme_udesc = "clocks when processor is driving bus", \ .pme_ucode = 0x00 \ }, \ { .pme_uname = "ANY", \ .pme_udesc = "clocks when any agent is driving bus", \ .pme_ucode = 0x20 \ } \ } \ },\ {.pme_name = "BUS_REQ_OUTSTANDING",\ .pme_code = 0x60,\ .pme_desc = "Number of bus requests outstanding. This counter is incremented " \ "by the number of cacheable read bus requests outstanding in any given cycle", \ },\ {.pme_name = "BUS_TRANS_BRD",\ .pme_code = 0x65,\ .pme_desc = "Number of burst read transactions", \ .pme_numasks = 2, \ .pme_umasks = { \ { .pme_uname = "SELF", \ .pme_udesc = "clocks when processor is driving bus", \ .pme_ucode = 0x00 \ }, \ { .pme_uname = "ANY", \ .pme_udesc = "clocks when any agent is driving bus", \ .pme_ucode = 0x20 \ } \ } \ },\ {.pme_name = "BUS_TRANS_RFO",\ .pme_code = 0x66,\ .pme_desc = "Number of completed read for ownership transactions",\ .pme_numasks = 2, \ .pme_umasks = { \ { .pme_uname = "SELF", \ .pme_udesc = "clocks when processor is driving bus", \ .pme_ucode = 0x00 \ }, \ { .pme_uname = "ANY", \ .pme_udesc = "clocks when any agent is driving bus", \ .pme_ucode = 0x20 \ } \ } \ },\ {.pme_name = "BUS_TRANS_WB",\ .pme_code = 0x67,\ .pme_desc = "Number of completed write back transactions",\ .pme_numasks = 2, \ .pme_umasks = { \ { .pme_uname = "SELF", \ .pme_udesc = "clocks when processor is driving bus", \ .pme_ucode = 0x00 \ }, \ { .pme_uname = "ANY", \ .pme_udesc = "clocks when any agent is driving bus", \ .pme_ucode = 0x20 \ } \ } \ },\ {.pme_name = "BUS_TRAN_IFETCH",\ .pme_code = 0x68,\ .pme_desc = "Number of completed instruction fetch transactions",\ .pme_numasks = 2, \ .pme_umasks = { \ { .pme_uname = "SELF", \ .pme_udesc = "clocks when processor is driving bus", \ .pme_ucode = 0x00 \ }, \ { .pme_uname = "ANY", \ .pme_udesc = "clocks when any agent is driving bus", \ .pme_ucode = 0x20 \ } \ } \ },\ {.pme_name = "BUS_TRAN_INVAL",\ .pme_code = 0x69,\ .pme_desc = "Number of completed invalidate transactions",\ .pme_numasks = 2, \ .pme_umasks = { \ { .pme_uname = "SELF", \ .pme_udesc = "clocks when processor is driving bus", \ .pme_ucode = 0x00 \ }, \ { .pme_uname = "ANY", \ .pme_udesc = "clocks when any agent is driving bus", \ .pme_ucode = 0x20 \ } \ } \ },\ {.pme_name = "BUS_TRAN_PWR",\ .pme_code = 0x6a,\ .pme_desc = "Number of completed partial write transactions",\ .pme_numasks = 2, \ .pme_umasks = { \ { .pme_uname = "SELF", \ .pme_udesc = "clocks when processor is driving bus", \ .pme_ucode = 0x00 \ }, \ { .pme_uname = "ANY", \ .pme_udesc = "clocks when any agent is driving bus", \ .pme_ucode = 0x20 \ } \ } \ },\ {.pme_name = "BUS_TRANS_P",\ .pme_code = 0x6b,\ .pme_desc = "Number of completed partial transactions",\ .pme_numasks = 2, \ .pme_umasks = { \ { .pme_uname = "SELF", \ .pme_udesc = "clocks when processor is driving bus", \ .pme_ucode = 0x00 \ }, \ { .pme_uname = "ANY", \ .pme_udesc = "clocks when any agent is driving bus", \ .pme_ucode = 0x20 \ } \ } \ },\ {.pme_name = "BUS_TRANS_IO",\ .pme_code = 0x6c,\ .pme_desc = "Number of completed I/O transactions",\ .pme_numasks = 2, \ .pme_umasks = { \ { .pme_uname = "SELF", \ .pme_udesc = "clocks when processor is driving bus", \ .pme_ucode = 0x00 \ }, \ { .pme_uname = "ANY", \ .pme_udesc = "clocks when any agent is driving bus", \ .pme_ucode = 0x20 \ } \ } \ },\ {.pme_name = "BUS_TRAN_DEF",\ .pme_code = 0x6d,\ .pme_desc = "Number of completed deferred transactions",\ .pme_numasks = 2, \ .pme_umasks = { \ { .pme_uname = "SELF", \ .pme_udesc = "clocks when processor is driving bus", \ .pme_ucode = 0x1 \ }, \ { .pme_uname = "ANY", \ .pme_udesc = "clocks when any agent is driving bus", \ .pme_ucode = 0x2 \ } \ } \ },\ {.pme_name = "BUS_TRAN_BURST",\ .pme_code = 0x6e,\ .pme_desc = "Number of completed burst transactions",\ .pme_numasks = 2, \ .pme_umasks = { \ { .pme_uname = "SELF", \ .pme_udesc = "clocks when processor is driving bus", \ .pme_ucode = 0x00 \ }, \ { .pme_uname = "ANY", \ .pme_udesc = "clocks when any agent is driving bus", \ .pme_ucode = 0x20 \ } \ } \ },\ {.pme_name = "BUS_TRAN_ANY",\ .pme_code = 0x70,\ .pme_desc = "Number of all completed bus transactions. Address bus utilization " \ "can be calculated knowing the minimum address bus occupancy. Includes special cycles, etc.",\ .pme_numasks = 2, \ .pme_umasks = { \ { .pme_uname = "SELF", \ .pme_udesc = "clocks when processor is driving bus", \ .pme_ucode = 0x00 \ }, \ { .pme_uname = "ANY", \ .pme_udesc = "clocks when any agent is driving bus", \ .pme_ucode = 0x20 \ } \ } \ },\ {.pme_name = "BUS_TRAN_MEM",\ .pme_code = 0x6f,\ .pme_desc = "Number of completed memory transactions",\ .pme_numasks = 2, \ .pme_umasks = { \ { .pme_uname = "SELF", \ .pme_udesc = "clocks when processor is driving bus", \ .pme_ucode = 0x00 \ }, \ { .pme_uname = "ANY", \ .pme_udesc = "clocks when any agent is driving bus", \ .pme_ucode = 0x20 \ } \ } \ },\ {.pme_name = "BUS_DATA_RECV",\ .pme_code = 0x64,\ .pme_desc = "Number of bus clock cycles during which this processor is receiving data"\ },\ {.pme_name = "BUS_BNR_DRV",\ .pme_code = 0x61,\ .pme_desc = "Number of bus clock cycles during which this processor is driving the BNR# pin"\ },\ {.pme_name = "BUS_HIT_DRV",\ .pme_code = 0x7a,\ .pme_desc = "Number of bus clock cycles during which this processor is driving the HIT# pin"\ },\ {.pme_name = "BUS_HITM_DRV",\ .pme_code = 0x7b,\ .pme_desc = "Number of bus clock cycles during which this processor is driving the HITM# pin"\ },\ {.pme_name = "BUS_SNOOP_STALL",\ .pme_code = 0x7e,\ .pme_desc = "Number of clock cycles during which the bus is snoop stalled"\ },\ {.pme_name = "FLOPS",\ .pme_code = 0xc1,\ .pme_desc = "Number of computational floating-point operations retired. " \ "Excludes floating-point computational operations that cause traps or assists. " \ "Includes internal sub-operations for complex floating-point instructions like transcendentals. " \ "Excludes floating point loads and stores", \ .pme_flags = PFMLIB_I386_P6_CTR0_ONLY \ },\ {.pme_name = "FP_COMP_OPS_EXE",\ .pme_code = 0x10,\ .pme_desc = "Number of computational floating-point operations executed. The number of FADD, FSUB, " \ "FCOM, FMULs, integer MULs and IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. " \ "This number does not include the number of cycles, but the number of operations. " \ "This event does not distinguish an FADD used in the middle of a transcendental flow " \ "from a separate FADD instruction", \ .pme_flags = PFMLIB_I386_P6_CTR0_ONLY \ },\ {.pme_name = "FP_ASSIST",\ .pme_code = 0x11,\ .pme_desc = "Number of floating-point exception cases handled by microcode.", \ .pme_flags = PFMLIB_I386_P6_CTR1_ONLY \ },\ {.pme_name = "MUL",\ .pme_code = 0x12,\ .pme_desc = "Number of multiplies." \ "This count includes integer as well as FP multiplies and is speculative", \ .pme_flags = PFMLIB_I386_P6_CTR1_ONLY \ },\ {.pme_name = "DIV",\ .pme_code = 0x13,\ .pme_desc = "Number of divides." \ "This count includes integer as well as FP divides and is speculative", \ .pme_flags = PFMLIB_I386_P6_CTR1_ONLY \ },\ {.pme_name = "CYCLES_DIV_BUSY",\ .pme_code = 0x14,\ .pme_desc = "Number of cycles during which the divider is busy, and cannot accept new divides. " \ "This includes integer and FP divides, FPREM, FPSQRT, etc. and is speculative", \ .pme_flags = PFMLIB_I386_P6_CTR0_ONLY \ },\ {.pme_name = "LD_BLOCKS",\ .pme_code = 0x03,\ .pme_desc = "Number of load operations delayed due to store buffer blocks. Includes counts " \ "caused by preceding stores whose addresses are unknown, preceding stores whose addresses " \ "are known but whose data is unknown, and preceding stores that conflicts with the load " \ "but which incompletely overlap the load" \ },\ {.pme_name = "SB_DRAINS",\ .pme_code = 0x04,\ .pme_desc = "Number of store buffer drain cycles. Incremented every cycle the store buffer is draining. " \ "Draining is caused by serializing operations like CPUID, synchronizing operations " \ "like XCHG, interrupt acknowledgment, as well as other conditions (such as cache flushing)."\ },\ {.pme_name = "MISALIGN_MEM_REF",\ .pme_code = 0x05,\ .pme_desc = "Number of misaligned data memory references. Incremented by 1 every cycle during "\ "which, either the processor's load or store pipeline dispatches a misaligned micro-op "\ "Counting is performed if it is the first or second half or if it is blocked, squashed, "\ "or missed. In this context, misaligned means crossing a 64-bit boundary"\ },\ {.pme_name = "UOPS_RETIRED",\ .pme_code = 0xc2,\ .pme_desc = "Number of micro-ops retired"\ },\ {.pme_name = "INST_DECODED",\ .pme_code = 0xd0,\ .pme_desc = "Number of instructions decoded"\ },\ {.pme_name = "HW_INT_RX",\ .pme_code = 0xc8,\ .pme_desc = "Number of hardware interrupts received"\ },\ {.pme_name = "CYCLES_INT_MASKED",\ .pme_code = 0xc6,\ .pme_desc = "Number of processor cycles for which interrupts are disabled"\ },\ {.pme_name = "CYCLES_INT_PENDING_AND_MASKED",\ .pme_code = 0xc7,\ .pme_desc = "Number of processor cycles for which interrupts are disabled and interrupts are pending."\ },\ {.pme_name = "BR_INST_RETIRED",\ .pme_code = 0xc4,\ .pme_desc = "Number of branch instructions retired"\ },\ {.pme_name = "BR_MISS_PRED_RETIRED",\ .pme_code = 0xc5,\ .pme_desc = "Number of mispredicted branches retired"\ },\ {.pme_name = "BR_TAKEN_RETIRED",\ .pme_code = 0xc9,\ .pme_desc = "Number of taken branches retired"\ },\ {.pme_name = "BR_MISS_PRED_TAKEN_RET",\ .pme_code = 0xca,\ .pme_desc = "Number of taken mispredicted branches retired"\ },\ {.pme_name = "BR_INST_DECODED",\ .pme_code = 0xe0,\ .pme_desc = "Number of branch instructions decoded"\ },\ {.pme_name = "BTB_MISSES",\ .pme_code = 0xe2,\ .pme_desc = "Number of branches for which the BTB did not produce a prediction"\ },\ {.pme_name = "BR_BOGUS",\ .pme_code = 0xe4,\ .pme_desc = "Number of bogus branches"\ },\ {.pme_name = "BACLEARS",\ .pme_code = 0xe6,\ .pme_desc = "Number of times BACLEAR is asserted. This is the number of times that " \ "a static branch prediction was made, in which the branch decoder decided " \ "to make a branch prediction because the BTB did not" \ },\ {.pme_name = "RESOURCE_STALLS",\ .pme_code = 0xa2,\ .pme_desc = "Incremented by 1 during every cycle for which there is a resource related stall. " \ "Includes register renaming buffer entries, memory buffer entries. Does not include " \ "stalls due to bus queue full, too many cache misses, etc. In addition to resource " \ "related stalls, this event counts some other events. Includes stalls arising during " \ "branch misprediction recovery, such as if retirement of the mispredicted branch is " \ "delayed and stalls arising while store buffer is draining from synchronizing operations" \ },\ {.pme_name = "PARTIAL_RAT_STALLS",\ .pme_code = 0xd2,\ .pme_desc = "Number of cycles or events for partial stalls. This includes flag partial stalls"\ },\ {.pme_name = "SEGMENT_REG_LOADS",\ .pme_code = 0x06,\ .pme_desc = "Number of segment register loads."\ }\ /* * Pentium Pro Processor Event Table */ static pme_i386_p6_entry_t i386_ppro_pe []={ I386_P6_CPU_CLK_UNHALTED, /* should be first */ I386_P6_COMMON_PME, /* generic p6 */ I386_P6_NOT_PM_PME, /* generic p6 that conflict with Pentium M */ }; #define PME_I386_PPRO_CPU_CLK_UNHALTED 0 #define PME_I386_PPRO_INST_RETIRED 1 #define PME_I386_PPRO_EVENT_COUNT (sizeof(i386_ppro_pe)/sizeof(pme_i386_p6_entry_t)) /* * Pentium II Processor Event Table */ static pme_i386_p6_entry_t i386_pII_pe []={ I386_P6_CPU_CLK_UNHALTED, /* should be first */ I386_P6_COMMON_PME, /* generic p6 */ I386_P6_PII_ONLY_PME, /* pentium II only */ I386_P6_PII_PIII_PME, /* pentium II and later */ I386_P6_NOT_PM_PME, /* generic p6 that conflict with Pentium M */ }; #define PME_I386_PII_CPU_CLK_UNHALTED 0 #define PME_I386_PII_INST_RETIRED 1 #define PME_I386_PII_EVENT_COUNT (sizeof(i386_pII_pe)/sizeof(pme_i386_p6_entry_t)) /* * Pentium III Processor Event Table */ static pme_i386_p6_entry_t i386_pIII_pe []={ I386_P6_CPU_CLK_UNHALTED, /* should be first */ I386_P6_COMMON_PME, /* generic p6 */ I386_P6_PII_PIII_PME, /* pentium II and later */ I386_P6_PIII_PME, /* pentium III and later */ I386_P6_NOT_PM_PME, /* generic p6 that conflict with Pentium M */ I386_P6_PIII_NOT_PM_PME /* pentium III that conflict with Pentium M */ }; #define PME_I386_PIII_CPU_CLK_UNHALTED 0 #define PME_I386_PIII_INST_RETIRED 1 #define PME_I386_PIII_EVENT_COUNT (sizeof(i386_pIII_pe)/sizeof(pme_i386_p6_entry_t)) /* * Pentium M event table * It is different from regular P6 because it supports additional events * and also because the semantics of some events is slightly different * * The library autodetects which table to use during pfmlib_initialize() */ static pme_i386_p6_entry_t i386_pm_pe []={ {.pme_name = "CPU_CLK_UNHALTED", .pme_code = 0x79, .pme_desc = "Number cycles during which the processor is not halted and not in a thermal trip" }, I386_P6_COMMON_PME, /* generic p6 */ I386_P6_PII_PIII_PME, /* pentium II and later */ I386_P6_PIII_PME, /* pentium III and later */ {.pme_name = "EMON_EST_TRANS", .pme_code = 0x58, .pme_desc = "Number of Enhanced Intel SpeedStep technology transitions", .pme_numasks = 2, .pme_umasks = { { .pme_uname = "ALL", .pme_udesc = "All transitions", .pme_ucode = 0x0 }, { .pme_uname = "FREQ", .pme_udesc = "Only frequency transitions", .pme_ucode = 0x2 }, } }, {.pme_name = "EMON_THERMAL_TRIP", .pme_code = 0x59, .pme_desc = "Duration/occurrences in thermal trip; to count the number of thermal trips; edge detect must be used" }, {.pme_name = "BR_INST_EXEC", .pme_code = 0x088, .pme_desc = "Branch instructions executed (not necessarily retired)" }, {.pme_name = "BR_MISSP_EXEC", .pme_code = 0x89, .pme_desc = "Branch instructions executed that were mispredicted at execution" }, {.pme_name = "BR_BAC_MISSP_EXEC", .pme_code = 0x8a, .pme_desc = "Branch instructions executed that were mispredicted at Front End (BAC)" }, {.pme_name = "BR_CND_EXEC", .pme_code = 0x8b, .pme_desc = "Conditional branch instructions executed" }, {.pme_name = "BR_CND_MISSP_EXEC", .pme_code = 0x8c, .pme_desc = "Conditional branch instructions executed that were mispredicted" }, {.pme_name = "BR_IND_EXEC", .pme_code = 0x8d, .pme_desc = "Indirect branch instructions executed" }, {.pme_name = "BR_IND_MISSP_EXEC", .pme_code = 0x8e, .pme_desc = "Indirect branch instructions executed that were mispredicted" }, {.pme_name = "BR_RET_EXEC", .pme_code = 0x8f, .pme_desc = "Return branch instructions executed" }, {.pme_name = "BR_RET_MISSP_EXEC", .pme_code = 0x90, .pme_desc = "Return branch instructions executed that were mispredicted at Execution" }, {.pme_name = "BR_RET_BAC_MISSP_EXEC", .pme_code = 0x91, .pme_desc = "Return branch instructions executed that were mispredicted at Front End (BAC)" }, {.pme_name = "BR_CALL_EXEC", .pme_code = 0x92, .pme_desc = "CALL instructions executed" }, {.pme_name = "BR_CALL_MISSP_EXEC", .pme_code = 0x93, .pme_desc = "CALL instructions executed that were mispredicted" }, {.pme_name = "BR_IND_CALL_EXEC", .pme_code = 0x94, .pme_desc = "Indirect CALL instructions executed" }, {.pme_name = "EMON_SIMD_INSTR_RETIRED", .pme_code = 0xce, .pme_desc = "Number of retired MMX instructions" }, {.pme_name = "EMON_SYNCH_UOPS", .pme_code = 0xd3, .pme_desc = "Sync micro-ops" }, {.pme_name = "EMON_ESP_UOPS", .pme_code = 0xd7, .pme_desc = "Total number of micro-ops" }, {.pme_name = "EMON_FUSED_UOPS_RET", .pme_code = 0xda, .pme_desc = "Total number of micro-ops", .pme_flags = PFMLIB_I386_P6_UMASK_COMBO, .pme_numasks = 3, .pme_umasks = { { .pme_uname = "ALL", .pme_udesc = "All fused micro-ops", .pme_ucode = 0x0 }, { .pme_uname = "LD_OP", .pme_udesc = "Only load+Op micro-ops", .pme_ucode = 0x1 }, { .pme_uname = "STD_STA", .pme_udesc = "Only std+sta micro-ops", .pme_ucode = 0x2 } } }, {.pme_name = "EMON_UNFUSION", .pme_code = 0xdb, .pme_desc = "Number of unfusion events in the ROB, happened on a FP exception to a fused micro-op" }, {.pme_name = "EMON_PREF_RQSTS_UP", .pme_code = 0xf0, .pme_desc = "Number of upward prefetches issued" }, {.pme_name = "EMON_PREF_RQSTS_DN", .pme_code = 0xf8, .pme_desc = "Number of downward prefetches issued" }, {.pme_name = "EMON_SSE_SSE2_INST_RETIRED", .pme_code = 0xd8, .pme_desc = "Streaming SIMD extensions instructions retired", .pme_numasks = 4, .pme_umasks = { { .pme_uname = "SSE_PACKED_SCALAR_SINGLE", .pme_udesc = "SSE Packed Single and Scalar Single", .pme_ucode = 0x0 }, { .pme_uname = "SSE_SCALAR_SINGLE", .pme_udesc = "SSE Scalar Single", .pme_ucode = 0x1 }, { .pme_uname = "SSE2_PACKED_DOUBLE", .pme_udesc = "SSE2 Packed Double", .pme_ucode = 0x2 }, { .pme_uname = "SSE2_SCALAR_DOUBLE", .pme_udesc = "SSE2 Scalar Double", .pme_ucode = 0x3 } } }, {.pme_name = "EMON_SSE_SSE2_COMP_INST_RETIRED", .pme_code = 0xd9, .pme_desc = "Computational SSE instructions retired", .pme_numasks = 4, .pme_umasks = { { .pme_uname = "SSE_PACKED_SINGLE", .pme_udesc = "SSE Packed Single", .pme_ucode = 0x0 }, { .pme_uname = "SSE_SCALAR_SINGLE", .pme_udesc = "SSE Scalar Single", .pme_ucode = 0x1 }, { .pme_uname = "SSE2_PACKED_DOUBLE", .pme_udesc = "SSE2 Packed Double", .pme_ucode = 0x2 }, { .pme_uname = "SSE2_SCALAR_DOUBLE", .pme_udesc = "SSE2 Scalar Double", .pme_ucode = 0x3 } } }, {.pme_name = "L2_LD", .pme_code = 0x29, .pme_desc = "Number of L2 data loads", I386_PM_MESI_PREFETCH_UMASKS }, {.pme_name = "L2_LINES_IN", .pme_code = 0x24, .pme_desc = "Number of L2 lines allocated", I386_PM_MESI_PREFETCH_UMASKS }, {.pme_name = "L2_LINES_OUT", .pme_code = 0x26, .pme_desc = "Number of L2 lines evicted", I386_PM_MESI_PREFETCH_UMASKS }, {.pme_name = "L2_M_LINES_OUT", .pme_code = 0x27, .pme_desc = "Number of L2 M-state lines evicted", I386_PM_MESI_PREFETCH_UMASKS } }; #define PME_I386_PM_CPU_CLK_UNHALTED 0 #define PME_I386_PM_INST_RETIRED 1 #define PME_I386_PM_EVENT_COUNT (sizeof(i386_pm_pe)/sizeof(pme_i386_p6_entry_t)) papi-5.5.1/src/libpfm-3.y/lib/power4_events.h0000644000307100002310000050555513013651450020664 0ustar yarkhangraduate/****************************/ /* THIS IS OPEN SOURCE CODE */ /****************************/ #ifndef __POWER4_EVENTS_H__ #define __POWER4_EVENTS_H__ /* * File: power4_events.h * CVS: * Author: Corey Ashford * cjashfor@us.ibm.com * Mods: * * * (C) Copyright IBM Corporation, 2007. All Rights Reserved. * Contributed by Corey Ashford * * Note: This code was automatically generated and should not be modified by * hand. * */ #define POWER4_PME_PM_MRK_LSU_SRQ_INST_VALID 0 #define POWER4_PME_PM_FPU1_SINGLE 1 #define POWER4_PME_PM_DC_PREF_OUT_STREAMS 2 #define POWER4_PME_PM_FPU0_STALL3 3 #define POWER4_PME_PM_TB_BIT_TRANS 4 #define POWER4_PME_PM_GPR_MAP_FULL_CYC 5 #define POWER4_PME_PM_MRK_ST_CMPL 6 #define POWER4_PME_PM_MRK_LSU_FLUSH_LRQ 7 #define POWER4_PME_PM_FPU0_STF 8 #define POWER4_PME_PM_FPU1_FMA 9 #define POWER4_PME_PM_L2SA_MOD_TAG 10 #define POWER4_PME_PM_MRK_DATA_FROM_L275_SHR 11 #define POWER4_PME_PM_1INST_CLB_CYC 12 #define POWER4_PME_PM_LSU1_FLUSH_ULD 13 #define POWER4_PME_PM_MRK_INST_FIN 14 #define POWER4_PME_PM_MRK_LSU0_FLUSH_UST 15 #define POWER4_PME_PM_FPU_FDIV 16 #define POWER4_PME_PM_LSU_LRQ_S0_ALLOC 17 #define POWER4_PME_PM_FPU0_FULL_CYC 18 #define POWER4_PME_PM_FPU_SINGLE 19 #define POWER4_PME_PM_FPU0_FMA 20 #define POWER4_PME_PM_MRK_LSU1_FLUSH_ULD 21 #define POWER4_PME_PM_LSU1_FLUSH_LRQ 22 #define POWER4_PME_PM_L2SA_ST_HIT 23 #define POWER4_PME_PM_L2SB_SHR_INV 24 #define POWER4_PME_PM_DTLB_MISS 25 #define POWER4_PME_PM_MRK_ST_MISS_L1 26 #define POWER4_PME_PM_EXT_INT 27 #define POWER4_PME_PM_MRK_LSU1_FLUSH_LRQ 28 #define POWER4_PME_PM_MRK_ST_GPS 29 #define POWER4_PME_PM_GRP_DISP_SUCCESS 30 #define POWER4_PME_PM_LSU1_LDF 31 #define POWER4_PME_PM_FAB_CMD_ISSUED 32 #define POWER4_PME_PM_LSU0_SRQ_STFWD 33 #define POWER4_PME_PM_CR_MAP_FULL_CYC 34 #define POWER4_PME_PM_MRK_LSU0_FLUSH_ULD 35 #define POWER4_PME_PM_LSU_DERAT_MISS 36 #define POWER4_PME_PM_FPU0_SINGLE 37 #define POWER4_PME_PM_FPU1_FDIV 38 #define POWER4_PME_PM_FPU1_FEST 39 #define POWER4_PME_PM_FPU0_FRSP_FCONV 40 #define POWER4_PME_PM_MRK_ST_CMPL_INT 41 #define POWER4_PME_PM_FXU_FIN 42 #define POWER4_PME_PM_FPU_STF 43 #define POWER4_PME_PM_DSLB_MISS 44 #define POWER4_PME_PM_DATA_FROM_L275_SHR 45 #define POWER4_PME_PM_FXLS1_FULL_CYC 46 #define POWER4_PME_PM_L3B0_DIR_MIS 47 #define POWER4_PME_PM_2INST_CLB_CYC 48 #define POWER4_PME_PM_MRK_STCX_FAIL 49 #define POWER4_PME_PM_LSU_LMQ_LHR_MERGE 50 #define POWER4_PME_PM_FXU0_BUSY_FXU1_IDLE 51 #define POWER4_PME_PM_L3B1_DIR_REF 52 #define POWER4_PME_PM_MRK_LSU_FLUSH_UST 53 #define POWER4_PME_PM_MRK_DATA_FROM_L25_SHR 54 #define POWER4_PME_PM_LSU_FLUSH_ULD 55 #define POWER4_PME_PM_MRK_BRU_FIN 56 #define POWER4_PME_PM_IERAT_XLATE_WR 57 #define POWER4_PME_PM_LSU0_BUSY 58 #define POWER4_PME_PM_L2SA_ST_REQ 59 #define POWER4_PME_PM_DATA_FROM_MEM 60 #define POWER4_PME_PM_FPR_MAP_FULL_CYC 61 #define POWER4_PME_PM_FPU1_FULL_CYC 62 #define POWER4_PME_PM_FPU0_FIN 63 #define POWER4_PME_PM_3INST_CLB_CYC 64 #define POWER4_PME_PM_DATA_FROM_L35 65 #define POWER4_PME_PM_L2SA_SHR_INV 66 #define POWER4_PME_PM_MRK_LSU_FLUSH_SRQ 67 #define POWER4_PME_PM_THRESH_TIMEO 68 #define POWER4_PME_PM_FPU_FSQRT 69 #define POWER4_PME_PM_MRK_LSU0_FLUSH_LRQ 70 #define POWER4_PME_PM_FXLS0_FULL_CYC 71 #define POWER4_PME_PM_DATA_TABLEWALK_CYC 72 #define POWER4_PME_PM_FPU0_ALL 73 #define POWER4_PME_PM_FPU0_FEST 74 #define POWER4_PME_PM_DATA_FROM_L25_MOD 75 #define POWER4_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 76 #define POWER4_PME_PM_FPU_FEST 77 #define POWER4_PME_PM_0INST_FETCH 78 #define POWER4_PME_PM_LARX_LSU1 79 #define POWER4_PME_PM_LD_MISS_L1_LSU0 80 #define POWER4_PME_PM_L1_PREF 81 #define POWER4_PME_PM_FPU1_STALL3 82 #define POWER4_PME_PM_BRQ_FULL_CYC 83 #define POWER4_PME_PM_LARX 84 #define POWER4_PME_PM_MRK_DATA_FROM_L35 85 #define POWER4_PME_PM_WORK_HELD 86 #define POWER4_PME_PM_MRK_LD_MISS_L1_LSU0 87 #define POWER4_PME_PM_FXU_IDLE 88 #define POWER4_PME_PM_INST_CMPL 89 #define POWER4_PME_PM_LSU1_FLUSH_UST 90 #define POWER4_PME_PM_LSU0_FLUSH_ULD 91 #define POWER4_PME_PM_INST_FROM_L2 92 #define POWER4_PME_PM_DATA_FROM_L3 93 #define POWER4_PME_PM_FPU0_DENORM 94 #define POWER4_PME_PM_FPU1_FMOV_FEST 95 #define POWER4_PME_PM_GRP_DISP_REJECT 96 #define POWER4_PME_PM_INST_FETCH_CYC 97 #define POWER4_PME_PM_LSU_LDF 98 #define POWER4_PME_PM_INST_DISP 99 #define POWER4_PME_PM_L2SA_MOD_INV 100 #define POWER4_PME_PM_DATA_FROM_L25_SHR 101 #define POWER4_PME_PM_FAB_CMD_RETRIED 102 #define POWER4_PME_PM_L1_DCACHE_RELOAD_VALID 103 #define POWER4_PME_PM_MRK_GRP_ISSUED 104 #define POWER4_PME_PM_FPU_FULL_CYC 105 #define POWER4_PME_PM_FPU_FMA 106 #define POWER4_PME_PM_MRK_CRU_FIN 107 #define POWER4_PME_PM_MRK_LSU1_FLUSH_UST 108 #define POWER4_PME_PM_MRK_FXU_FIN 109 #define POWER4_PME_PM_BR_ISSUED 110 #define POWER4_PME_PM_EE_OFF 111 #define POWER4_PME_PM_INST_FROM_L3 112 #define POWER4_PME_PM_ITLB_MISS 113 #define POWER4_PME_PM_FXLS_FULL_CYC 114 #define POWER4_PME_PM_FXU1_BUSY_FXU0_IDLE 115 #define POWER4_PME_PM_GRP_DISP_VALID 116 #define POWER4_PME_PM_L2SC_ST_HIT 117 #define POWER4_PME_PM_MRK_GRP_DISP 118 #define POWER4_PME_PM_L2SB_MOD_TAG 119 #define POWER4_PME_PM_INST_FROM_L25_L275 120 #define POWER4_PME_PM_LSU_FLUSH_UST 121 #define POWER4_PME_PM_L2SB_ST_HIT 122 #define POWER4_PME_PM_FXU1_FIN 123 #define POWER4_PME_PM_L3B1_DIR_MIS 124 #define POWER4_PME_PM_4INST_CLB_CYC 125 #define POWER4_PME_PM_GRP_CMPL 126 #define POWER4_PME_PM_DC_PREF_L2_CLONE_L3 127 #define POWER4_PME_PM_FPU_FRSP_FCONV 128 #define POWER4_PME_PM_5INST_CLB_CYC 129 #define POWER4_PME_PM_MRK_LSU0_FLUSH_SRQ 130 #define POWER4_PME_PM_MRK_LSU_FLUSH_ULD 131 #define POWER4_PME_PM_8INST_CLB_CYC 132 #define POWER4_PME_PM_LSU_LMQ_FULL_CYC 133 #define POWER4_PME_PM_ST_REF_L1_LSU0 134 #define POWER4_PME_PM_LSU0_DERAT_MISS 135 #define POWER4_PME_PM_LSU_SRQ_SYNC_CYC 136 #define POWER4_PME_PM_FPU_STALL3 137 #define POWER4_PME_PM_MRK_DATA_FROM_L2 138 #define POWER4_PME_PM_FPU0_FMOV_FEST 139 #define POWER4_PME_PM_LSU0_FLUSH_SRQ 140 #define POWER4_PME_PM_LD_REF_L1_LSU0 141 #define POWER4_PME_PM_L2SC_SHR_INV 142 #define POWER4_PME_PM_LSU1_FLUSH_SRQ 143 #define POWER4_PME_PM_LSU_LMQ_S0_ALLOC 144 #define POWER4_PME_PM_ST_REF_L1 145 #define POWER4_PME_PM_LSU_SRQ_EMPTY_CYC 146 #define POWER4_PME_PM_FPU1_STF 147 #define POWER4_PME_PM_L3B0_DIR_REF 148 #define POWER4_PME_PM_RUN_CYC 149 #define POWER4_PME_PM_LSU_LMQ_S0_VALID 150 #define POWER4_PME_PM_LSU_LRQ_S0_VALID 151 #define POWER4_PME_PM_LSU0_LDF 152 #define POWER4_PME_PM_MRK_IMR_RELOAD 153 #define POWER4_PME_PM_7INST_CLB_CYC 154 #define POWER4_PME_PM_MRK_GRP_TIMEO 155 #define POWER4_PME_PM_FPU_FMOV_FEST 156 #define POWER4_PME_PM_GRP_DISP_BLK_SB_CYC 157 #define POWER4_PME_PM_XER_MAP_FULL_CYC 158 #define POWER4_PME_PM_ST_MISS_L1 159 #define POWER4_PME_PM_STOP_COMPLETION 160 #define POWER4_PME_PM_MRK_GRP_CMPL 161 #define POWER4_PME_PM_ISLB_MISS 162 #define POWER4_PME_PM_CYC 163 #define POWER4_PME_PM_LD_MISS_L1_LSU1 164 #define POWER4_PME_PM_STCX_FAIL 165 #define POWER4_PME_PM_LSU1_SRQ_STFWD 166 #define POWER4_PME_PM_GRP_DISP 167 #define POWER4_PME_PM_DATA_FROM_L2 168 #define POWER4_PME_PM_L2_PREF 169 #define POWER4_PME_PM_FPU0_FPSCR 170 #define POWER4_PME_PM_FPU1_DENORM 171 #define POWER4_PME_PM_MRK_DATA_FROM_L25_MOD 172 #define POWER4_PME_PM_L2SB_ST_REQ 173 #define POWER4_PME_PM_L2SB_MOD_INV 174 #define POWER4_PME_PM_FPU0_FSQRT 175 #define POWER4_PME_PM_LD_REF_L1 176 #define POWER4_PME_PM_MRK_L1_RELOAD_VALID 177 #define POWER4_PME_PM_L2SB_SHR_MOD 178 #define POWER4_PME_PM_INST_FROM_L1 179 #define POWER4_PME_PM_1PLUS_PPC_CMPL 180 #define POWER4_PME_PM_EE_OFF_EXT_INT 181 #define POWER4_PME_PM_L2SC_SHR_MOD 182 #define POWER4_PME_PM_LSU_LRQ_FULL_CYC 183 #define POWER4_PME_PM_IC_PREF_INSTALL 184 #define POWER4_PME_PM_MRK_LSU1_FLUSH_SRQ 185 #define POWER4_PME_PM_GCT_FULL_CYC 186 #define POWER4_PME_PM_INST_FROM_MEM 187 #define POWER4_PME_PM_FXU_BUSY 188 #define POWER4_PME_PM_ST_REF_L1_LSU1 189 #define POWER4_PME_PM_MRK_LD_MISS_L1 190 #define POWER4_PME_PM_MRK_LSU1_INST_FIN 191 #define POWER4_PME_PM_L1_WRITE_CYC 192 #define POWER4_PME_PM_BIQ_IDU_FULL_CYC 193 #define POWER4_PME_PM_MRK_LSU0_INST_FIN 194 #define POWER4_PME_PM_L2SC_ST_REQ 195 #define POWER4_PME_PM_LSU1_BUSY 196 #define POWER4_PME_PM_FPU_ALL 197 #define POWER4_PME_PM_LSU_SRQ_S0_ALLOC 198 #define POWER4_PME_PM_GRP_MRK 199 #define POWER4_PME_PM_FPU1_FIN 200 #define POWER4_PME_PM_DC_PREF_STREAM_ALLOC 201 #define POWER4_PME_PM_BR_MPRED_CR 202 #define POWER4_PME_PM_BR_MPRED_TA 203 #define POWER4_PME_PM_CRQ_FULL_CYC 204 #define POWER4_PME_PM_INST_FROM_PREF 205 #define POWER4_PME_PM_LD_MISS_L1 206 #define POWER4_PME_PM_STCX_PASS 207 #define POWER4_PME_PM_DC_INV_L2 208 #define POWER4_PME_PM_LSU_SRQ_FULL_CYC 209 #define POWER4_PME_PM_LSU0_FLUSH_LRQ 210 #define POWER4_PME_PM_LSU_SRQ_S0_VALID 211 #define POWER4_PME_PM_LARX_LSU0 212 #define POWER4_PME_PM_GCT_EMPTY_CYC 213 #define POWER4_PME_PM_FPU1_ALL 214 #define POWER4_PME_PM_FPU1_FSQRT 215 #define POWER4_PME_PM_FPU_FIN 216 #define POWER4_PME_PM_L2SA_SHR_MOD 217 #define POWER4_PME_PM_MRK_LD_MISS_L1_LSU1 218 #define POWER4_PME_PM_LSU_SRQ_STFWD 219 #define POWER4_PME_PM_FXU0_FIN 220 #define POWER4_PME_PM_MRK_FPU_FIN 221 #define POWER4_PME_PM_LSU_BUSY 222 #define POWER4_PME_PM_INST_FROM_L35 223 #define POWER4_PME_PM_FPU1_FRSP_FCONV 224 #define POWER4_PME_PM_SNOOP_TLBIE 225 #define POWER4_PME_PM_FPU0_FDIV 226 #define POWER4_PME_PM_LD_REF_L1_LSU1 227 #define POWER4_PME_PM_MRK_DATA_FROM_L275_MOD 228 #define POWER4_PME_PM_HV_CYC 229 #define POWER4_PME_PM_6INST_CLB_CYC 230 #define POWER4_PME_PM_LR_CTR_MAP_FULL_CYC 231 #define POWER4_PME_PM_L2SC_MOD_INV 232 #define POWER4_PME_PM_FPU_DENORM 233 #define POWER4_PME_PM_DATA_FROM_L275_MOD 234 #define POWER4_PME_PM_LSU1_DERAT_MISS 235 #define POWER4_PME_PM_IC_PREF_REQ 236 #define POWER4_PME_PM_MRK_LSU_FIN 237 #define POWER4_PME_PM_MRK_DATA_FROM_L3 238 #define POWER4_PME_PM_MRK_DATA_FROM_MEM 239 #define POWER4_PME_PM_LSU0_FLUSH_UST 240 #define POWER4_PME_PM_LSU_FLUSH_LRQ 241 #define POWER4_PME_PM_LSU_FLUSH_SRQ 242 #define POWER4_PME_PM_L2SC_MOD_TAG 243 static const int power4_event_ids[][POWER4_NUM_EVENT_COUNTERS] = { [ POWER4_PME_PM_MRK_LSU_SRQ_INST_VALID ] = { -1, -1, 68, 68, -1, -1, 68, 68 }, [ POWER4_PME_PM_FPU1_SINGLE ] = { 23, 23, -1, -1, 23, 23, -1, -1 }, [ POWER4_PME_PM_DC_PREF_OUT_STREAMS ] = { -1, -1, 14, 14, -1, -1, 14, 14 }, [ POWER4_PME_PM_FPU0_STALL3 ] = { 15, 15, -1, -1, 15, 15, -1, -1 }, [ POWER4_PME_PM_TB_BIT_TRANS ] = { -1, -1, -1, -1, -1, -1, -1, 86 }, [ POWER4_PME_PM_GPR_MAP_FULL_CYC ] = { -1, -1, 33, 33, -1, -1, 33, 33 }, [ POWER4_PME_PM_MRK_ST_CMPL ] = { 93, -1, -1, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_MRK_LSU_FLUSH_LRQ ] = { -1, -1, 81, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_FPU0_STF ] = { 16, 16, -1, -1, 16, 16, -1, -1 }, [ POWER4_PME_PM_FPU1_FMA ] = { 20, 20, -1, -1, 20, 20, -1, -1 }, [ POWER4_PME_PM_L2SA_MOD_TAG ] = { 38, 38, -1, -1, 38, 38, -1, -1 }, [ POWER4_PME_PM_MRK_DATA_FROM_L275_SHR ] = { -1, -1, -1, -1, -1, 90, -1, -1 }, [ POWER4_PME_PM_1INST_CLB_CYC ] = { -1, -1, 0, 0, -1, -1, 0, 0 }, [ POWER4_PME_PM_LSU1_FLUSH_ULD ] = { 63, 63, -1, -1, 63, 63, -1, -1 }, [ POWER4_PME_PM_MRK_INST_FIN ] = { -1, -1, -1, -1, -1, -1, 82, -1 }, [ POWER4_PME_PM_MRK_LSU0_FLUSH_UST ] = { -1, -1, 61, 61, -1, -1, 61, 61 }, [ POWER4_PME_PM_FPU_FDIV ] = { 84, -1, -1, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_LSU_LRQ_S0_ALLOC ] = { 68, 68, -1, -1, 68, 68, -1, -1 }, [ POWER4_PME_PM_FPU0_FULL_CYC ] = { 13, 13, -1, -1, 13, 13, -1, -1 }, [ POWER4_PME_PM_FPU_SINGLE ] = { -1, -1, -1, -1, 87, -1, -1, -1 }, [ POWER4_PME_PM_FPU0_FMA ] = { 11, 11, -1, -1, 11, 11, -1, -1 }, [ POWER4_PME_PM_MRK_LSU1_FLUSH_ULD ] = { -1, -1, 65, 65, -1, -1, 65, 65 }, [ POWER4_PME_PM_LSU1_FLUSH_LRQ ] = { 61, 61, -1, -1, 61, 61, -1, -1 }, [ POWER4_PME_PM_L2SA_ST_HIT ] = { -1, -1, 37, 37, -1, -1, 37, 37 }, [ POWER4_PME_PM_L2SB_SHR_INV ] = { 43, 43, -1, -1, 43, 43, -1, -1 }, [ POWER4_PME_PM_DTLB_MISS ] = { 6, 6, -1, -1, 6, 6, -1, -1 }, [ POWER4_PME_PM_MRK_ST_MISS_L1 ] = { 76, 76, -1, -1, 76, 76, -1, -1 }, [ POWER4_PME_PM_EXT_INT ] = { -1, -1, -1, -1, -1, -1, -1, 76 }, [ POWER4_PME_PM_MRK_LSU1_FLUSH_LRQ ] = { -1, -1, 63, 63, -1, -1, 63, 63 }, [ POWER4_PME_PM_MRK_ST_GPS ] = { -1, -1, -1, -1, -1, 93, -1, -1 }, [ POWER4_PME_PM_GRP_DISP_SUCCESS ] = { -1, -1, -1, -1, 89, -1, -1, -1 }, [ POWER4_PME_PM_LSU1_LDF ] = { -1, -1, 20, 20, -1, -1, 20, 20 }, [ POWER4_PME_PM_FAB_CMD_ISSUED ] = { -1, -1, 17, 17, -1, -1, 17, 17 }, [ POWER4_PME_PM_LSU0_SRQ_STFWD ] = { 59, 59, -1, -1, 59, 59, -1, -1 }, [ POWER4_PME_PM_CR_MAP_FULL_CYC ] = { 2, 2, -1, -1, 2, 2, -1, -1 }, [ POWER4_PME_PM_MRK_LSU0_FLUSH_ULD ] = { -1, -1, 60, 60, -1, -1, 60, 60 }, [ POWER4_PME_PM_LSU_DERAT_MISS ] = { -1, -1, -1, -1, -1, 88, -1, -1 }, [ POWER4_PME_PM_FPU0_SINGLE ] = { 14, 14, -1, -1, 14, 14, -1, -1 }, [ POWER4_PME_PM_FPU1_FDIV ] = { 19, 19, -1, -1, 19, 19, -1, -1 }, [ POWER4_PME_PM_FPU1_FEST ] = { -1, -1, 26, 26, -1, -1, 26, 26 }, [ POWER4_PME_PM_FPU0_FRSP_FCONV ] = { -1, -1, 25, 25, -1, -1, 25, 25 }, [ POWER4_PME_PM_MRK_ST_CMPL_INT ] = { -1, -1, 82, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_FXU_FIN ] = { -1, -1, 77, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_FPU_STF ] = { -1, -1, -1, -1, -1, 84, -1, -1 }, [ POWER4_PME_PM_DSLB_MISS ] = { 5, 5, -1, -1, 5, 5, -1, -1 }, [ POWER4_PME_PM_DATA_FROM_L275_SHR ] = { -1, -1, -1, -1, -1, 82, -1, -1 }, [ POWER4_PME_PM_FXLS1_FULL_CYC ] = { -1, -1, 85, 86, -1, -1, 85, 87 }, [ POWER4_PME_PM_L3B0_DIR_MIS ] = { 49, 49, -1, -1, 49, 49, -1, -1 }, [ POWER4_PME_PM_2INST_CLB_CYC ] = { -1, -1, 1, 1, -1, -1, 1, 1 }, [ POWER4_PME_PM_MRK_STCX_FAIL ] = { 75, 75, -1, -1, 75, 75, -1, -1 }, [ POWER4_PME_PM_LSU_LMQ_LHR_MERGE ] = { 67, 67, -1, -1, 67, 67, -1, -1 }, [ POWER4_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { -1, -1, -1, -1, -1, -1, 76, -1 }, [ POWER4_PME_PM_L3B1_DIR_REF ] = { 52, 52, -1, -1, 52, 52, -1, -1 }, [ POWER4_PME_PM_MRK_LSU_FLUSH_UST ] = { -1, -1, -1, -1, -1, -1, 83, -1 }, [ POWER4_PME_PM_MRK_DATA_FROM_L25_SHR ] = { -1, -1, -1, -1, 93, -1, -1, -1 }, [ POWER4_PME_PM_LSU_FLUSH_ULD ] = { 88, -1, -1, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_MRK_BRU_FIN ] = { -1, 89, -1, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_IERAT_XLATE_WR ] = { 31, 31, -1, -1, 31, 31, -1, -1 }, [ POWER4_PME_PM_LSU0_BUSY ] = { -1, -1, 50, 50, -1, -1, 50, 50 }, [ POWER4_PME_PM_L2SA_ST_REQ ] = { -1, -1, 38, 38, -1, -1, 38, 38 }, [ POWER4_PME_PM_DATA_FROM_MEM ] = { -1, 82, -1, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_FPR_MAP_FULL_CYC ] = { 7, 7, -1, -1, 7, 7, -1, -1 }, [ POWER4_PME_PM_FPU1_FULL_CYC ] = { 22, 22, -1, -1, 22, 22, -1, -1 }, [ POWER4_PME_PM_FPU0_FIN ] = { -1, -1, 22, 22, -1, -1, 22, 22 }, [ POWER4_PME_PM_3INST_CLB_CYC ] = { -1, -1, 2, 2, -1, -1, 2, 2 }, [ POWER4_PME_PM_DATA_FROM_L35 ] = { -1, -1, 74, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_L2SA_SHR_INV ] = { 39, 39, -1, -1, 39, 39, -1, -1 }, [ POWER4_PME_PM_MRK_LSU_FLUSH_SRQ ] = { -1, -1, -1, 85, -1, -1, -1, -1 }, [ POWER4_PME_PM_THRESH_TIMEO ] = { -1, 91, -1, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_FPU_FSQRT ] = { -1, -1, -1, -1, -1, 83, -1, -1 }, [ POWER4_PME_PM_MRK_LSU0_FLUSH_LRQ ] = { -1, -1, 58, 58, -1, -1, 58, 58 }, [ POWER4_PME_PM_FXLS0_FULL_CYC ] = { -1, -1, 30, 30, -1, -1, 30, 30 }, [ POWER4_PME_PM_DATA_TABLEWALK_CYC ] = { -1, -1, 12, 12, -1, -1, 12, 12 }, [ POWER4_PME_PM_FPU0_ALL ] = { 8, 8, -1, -1, 8, 8, -1, -1 }, [ POWER4_PME_PM_FPU0_FEST ] = { -1, -1, 21, 21, -1, -1, 21, 21 }, [ POWER4_PME_PM_DATA_FROM_L25_MOD ] = { -1, -1, -1, -1, -1, -1, -1, 75 }, [ POWER4_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { -1, 88, -1, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_FPU_FEST ] = { -1, -1, 75, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_0INST_FETCH ] = { -1, -1, -1, -1, -1, -1, -1, 73 }, [ POWER4_PME_PM_LARX_LSU1 ] = { -1, -1, 45, 45, -1, -1, 45, 45 }, [ POWER4_PME_PM_LD_MISS_L1_LSU0 ] = { -1, -1, 46, 46, -1, -1, 46, 46 }, [ POWER4_PME_PM_L1_PREF ] = { -1, -1, 35, 35, -1, -1, 35, 35 }, [ POWER4_PME_PM_FPU1_STALL3 ] = { 24, 24, -1, -1, 24, 24, -1, -1 }, [ POWER4_PME_PM_BRQ_FULL_CYC ] = { 1, 1, -1, -1, 1, 1, -1, -1 }, [ POWER4_PME_PM_LARX ] = { -1, -1, -1, 79, -1, -1, -1, -1 }, [ POWER4_PME_PM_MRK_DATA_FROM_L35 ] = { -1, -1, 80, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_WORK_HELD ] = { -1, 92, -1, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_MRK_LD_MISS_L1_LSU0 ] = { 73, 73, -1, -1, 73, 73, -1, -1 }, [ POWER4_PME_PM_FXU_IDLE ] = { -1, -1, -1, -1, 88, -1, -1, -1 }, [ POWER4_PME_PM_INST_CMPL ] = { 86, -1, -1, 77, -1, 86, 78, 81 }, [ POWER4_PME_PM_LSU1_FLUSH_UST ] = { 64, 64, -1, -1, 64, 64, -1, -1 }, [ POWER4_PME_PM_LSU0_FLUSH_ULD ] = { 57, 57, -1, -1, 57, 57, -1, -1 }, [ POWER4_PME_PM_INST_FROM_L2 ] = { -1, -1, 78, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_DATA_FROM_L3 ] = { 82, -1, -1, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_FPU0_DENORM ] = { 9, 9, -1, -1, 9, 9, -1, -1 }, [ POWER4_PME_PM_FPU1_FMOV_FEST ] = { -1, -1, 28, 28, -1, -1, 28, 28 }, [ POWER4_PME_PM_GRP_DISP_REJECT ] = { 27, 27, -1, -1, 27, 27, -1, 80 }, [ POWER4_PME_PM_INST_FETCH_CYC ] = { 33, 33, -1, -1, 33, 33, -1, -1 }, [ POWER4_PME_PM_LSU_LDF ] = { -1, -1, -1, -1, -1, -1, -1, 78 }, [ POWER4_PME_PM_INST_DISP ] = { 32, 32, -1, -1, 32, 32, -1, -1 }, [ POWER4_PME_PM_L2SA_MOD_INV ] = { 37, 37, -1, -1, 37, 37, -1, -1 }, [ POWER4_PME_PM_DATA_FROM_L25_SHR ] = { -1, -1, -1, -1, 83, -1, -1, -1 }, [ POWER4_PME_PM_FAB_CMD_RETRIED ] = { -1, -1, 18, 18, -1, -1, 18, 18 }, [ POWER4_PME_PM_L1_DCACHE_RELOAD_VALID ] = { 36, 36, -1, -1, 36, 36, -1, -1 }, [ POWER4_PME_PM_MRK_GRP_ISSUED ] = { -1, -1, -1, -1, -1, 92, -1, -1 }, [ POWER4_PME_PM_FPU_FULL_CYC ] = { -1, -1, -1, -1, 86, -1, -1, -1 }, [ POWER4_PME_PM_FPU_FMA ] = { -1, 83, -1, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_MRK_CRU_FIN ] = { -1, -1, -1, 82, -1, -1, -1, -1 }, [ POWER4_PME_PM_MRK_LSU1_FLUSH_UST ] = { -1, -1, 66, 66, -1, -1, 66, 66 }, [ POWER4_PME_PM_MRK_FXU_FIN ] = { -1, -1, -1, -1, -1, 91, -1, -1 }, [ POWER4_PME_PM_BR_ISSUED ] = { -1, -1, 8, 8, -1, -1, 8, 8 }, [ POWER4_PME_PM_EE_OFF ] = { -1, -1, 15, 15, -1, -1, 15, 15 }, [ POWER4_PME_PM_INST_FROM_L3 ] = { -1, -1, -1, -1, 91, -1, -1, -1 }, [ POWER4_PME_PM_ITLB_MISS ] = { 35, 35, -1, -1, 35, 35, -1, -1 }, [ POWER4_PME_PM_FXLS_FULL_CYC ] = { -1, -1, -1, -1, -1, -1, -1, 79 }, [ POWER4_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { -1, -1, -1, 76, -1, -1, -1, -1 }, [ POWER4_PME_PM_GRP_DISP_VALID ] = { 28, 28, -1, -1, 28, 28, -1, -1 }, [ POWER4_PME_PM_L2SC_ST_HIT ] = { -1, -1, 41, 41, -1, -1, 41, 41 }, [ POWER4_PME_PM_MRK_GRP_DISP ] = { 91, -1, -1, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_L2SB_MOD_TAG ] = { 42, 42, -1, -1, 42, 42, -1, -1 }, [ POWER4_PME_PM_INST_FROM_L25_L275 ] = { -1, 86, -1, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_LSU_FLUSH_UST ] = { -1, 87, -1, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_L2SB_ST_HIT ] = { -1, -1, 39, 39, -1, -1, 39, 39 }, [ POWER4_PME_PM_FXU1_FIN ] = { -1, -1, 32, 32, -1, -1, 32, 32 }, [ POWER4_PME_PM_L3B1_DIR_MIS ] = { 51, 51, -1, -1, 51, 51, -1, -1 }, [ POWER4_PME_PM_4INST_CLB_CYC ] = { -1, -1, 3, 3, -1, -1, 3, 3 }, [ POWER4_PME_PM_GRP_CMPL ] = { -1, -1, -1, -1, -1, -1, 77, -1 }, [ POWER4_PME_PM_DC_PREF_L2_CLONE_L3 ] = { 3, 3, -1, -1, 3, 3, -1, -1 }, [ POWER4_PME_PM_FPU_FRSP_FCONV ] = { -1, -1, -1, -1, -1, -1, 75, -1 }, [ POWER4_PME_PM_5INST_CLB_CYC ] = { -1, -1, 4, 4, -1, -1, 4, 4 }, [ POWER4_PME_PM_MRK_LSU0_FLUSH_SRQ ] = { -1, -1, 59, 59, -1, -1, 59, 59 }, [ POWER4_PME_PM_MRK_LSU_FLUSH_ULD ] = { -1, -1, -1, -1, -1, -1, -1, 85 }, [ POWER4_PME_PM_8INST_CLB_CYC ] = { -1, -1, 7, 7, -1, -1, 7, 7 }, [ POWER4_PME_PM_LSU_LMQ_FULL_CYC ] = { 66, 66, -1, -1, 66, 66, -1, -1 }, [ POWER4_PME_PM_ST_REF_L1_LSU0 ] = { -1, -1, 71, 71, -1, -1, 71, 71 }, [ POWER4_PME_PM_LSU0_DERAT_MISS ] = { 54, 54, -1, -1, 54, 54, -1, -1 }, [ POWER4_PME_PM_LSU_SRQ_SYNC_CYC ] = { -1, -1, 56, 56, -1, -1, 56, 56 }, [ POWER4_PME_PM_FPU_STALL3 ] = { -1, 84, -1, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_MRK_DATA_FROM_L2 ] = { -1, -1, -1, 83, -1, -1, -1, -1 }, [ POWER4_PME_PM_FPU0_FMOV_FEST ] = { -1, -1, 23, 23, -1, -1, 23, 23 }, [ POWER4_PME_PM_LSU0_FLUSH_SRQ ] = { 56, 56, -1, -1, 56, 56, -1, -1 }, [ POWER4_PME_PM_LD_REF_L1_LSU0 ] = { -1, -1, 48, 48, -1, -1, 48, 48 }, [ POWER4_PME_PM_L2SC_SHR_INV ] = { 47, 47, -1, -1, 47, 47, -1, -1 }, [ POWER4_PME_PM_LSU1_FLUSH_SRQ ] = { 62, 62, -1, -1, 62, 62, -1, -1 }, [ POWER4_PME_PM_LSU_LMQ_S0_ALLOC ] = { -1, -1, 52, 52, -1, -1, 52, 52 }, [ POWER4_PME_PM_ST_REF_L1 ] = { -1, -1, -1, -1, -1, -1, 84, -1 }, [ POWER4_PME_PM_LSU_SRQ_EMPTY_CYC ] = { -1, -1, -1, 81, -1, -1, -1, -1 }, [ POWER4_PME_PM_FPU1_STF ] = { 25, 25, -1, -1, 25, 25, -1, -1 }, [ POWER4_PME_PM_L3B0_DIR_REF ] = { 50, 50, -1, -1, 50, 50, -1, -1 }, [ POWER4_PME_PM_RUN_CYC ] = { 94, -1, -1, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_LSU_LMQ_S0_VALID ] = { -1, -1, 53, 53, -1, -1, 53, 53 }, [ POWER4_PME_PM_LSU_LRQ_S0_VALID ] = { 69, 69, -1, -1, 69, 69, -1, -1 }, [ POWER4_PME_PM_LSU0_LDF ] = { -1, -1, 19, 19, -1, -1, 19, 19 }, [ POWER4_PME_PM_MRK_IMR_RELOAD ] = { 72, 72, -1, -1, 72, 72, -1, -1 }, [ POWER4_PME_PM_7INST_CLB_CYC ] = { -1, -1, 6, 6, -1, -1, 6, 6 }, [ POWER4_PME_PM_MRK_GRP_TIMEO ] = { -1, -1, -1, -1, 94, -1, -1, -1 }, [ POWER4_PME_PM_FPU_FMOV_FEST ] = { -1, -1, -1, -1, -1, -1, -1, 77 }, [ POWER4_PME_PM_GRP_DISP_BLK_SB_CYC ] = { -1, -1, 34, 34, -1, -1, 34, 34 }, [ POWER4_PME_PM_XER_MAP_FULL_CYC ] = { 80, 80, -1, -1, 80, 80, -1, -1 }, [ POWER4_PME_PM_ST_MISS_L1 ] = { 79, 79, 70, 70, 79, 79, 70, 70 }, [ POWER4_PME_PM_STOP_COMPLETION ] = { -1, -1, 83, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_MRK_GRP_CMPL ] = { -1, -1, -1, 84, -1, -1, -1, -1 }, [ POWER4_PME_PM_ISLB_MISS ] = { 34, 34, -1, -1, 34, 34, -1, -1 }, [ POWER4_PME_PM_CYC ] = { 81, 81, 73, 73, 82, 81, 73, 74 }, [ POWER4_PME_PM_LD_MISS_L1_LSU1 ] = { -1, -1, 47, 47, -1, -1, 47, 47 }, [ POWER4_PME_PM_STCX_FAIL ] = { 78, 78, -1, -1, 78, 78, -1, -1 }, [ POWER4_PME_PM_LSU1_SRQ_STFWD ] = { 65, 65, -1, -1, 65, 65, -1, -1 }, [ POWER4_PME_PM_GRP_DISP ] = { -1, 85, -1, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_DATA_FROM_L2 ] = { -1, -1, -1, 74, -1, -1, -1, -1 }, [ POWER4_PME_PM_L2_PREF ] = { -1, -1, 43, 43, -1, -1, 43, 43 }, [ POWER4_PME_PM_FPU0_FPSCR ] = { -1, -1, 24, 24, -1, -1, 24, 24 }, [ POWER4_PME_PM_FPU1_DENORM ] = { 18, 18, -1, -1, 18, 18, -1, -1 }, [ POWER4_PME_PM_MRK_DATA_FROM_L25_MOD ] = { -1, -1, -1, -1, -1, -1, -1, 83 }, [ POWER4_PME_PM_L2SB_ST_REQ ] = { -1, -1, 40, 40, -1, -1, 40, 40 }, [ POWER4_PME_PM_L2SB_MOD_INV ] = { 41, 41, -1, -1, 41, 41, -1, -1 }, [ POWER4_PME_PM_FPU0_FSQRT ] = { 12, 12, -1, -1, 12, 12, -1, -1 }, [ POWER4_PME_PM_LD_REF_L1 ] = { -1, -1, -1, -1, -1, -1, -1, 82 }, [ POWER4_PME_PM_MRK_L1_RELOAD_VALID ] = { -1, -1, 57, 57, -1, -1, 57, 57 }, [ POWER4_PME_PM_L2SB_SHR_MOD ] = { 44, 44, -1, -1, 44, 44, -1, -1 }, [ POWER4_PME_PM_INST_FROM_L1 ] = { -1, -1, -1, -1, -1, 87, -1, -1 }, [ POWER4_PME_PM_1PLUS_PPC_CMPL ] = { -1, -1, -1, -1, 81, -1, -1, -1 }, [ POWER4_PME_PM_EE_OFF_EXT_INT ] = { -1, -1, 16, 16, -1, -1, 16, 16 }, [ POWER4_PME_PM_L2SC_SHR_MOD ] = { 48, 48, -1, -1, 48, 48, -1, -1 }, [ POWER4_PME_PM_LSU_LRQ_FULL_CYC ] = { -1, -1, 54, 54, -1, -1, 54, 54 }, [ POWER4_PME_PM_IC_PREF_INSTALL ] = { 29, 29, -1, -1, 29, 29, -1, -1 }, [ POWER4_PME_PM_MRK_LSU1_FLUSH_SRQ ] = { -1, -1, 64, 64, -1, -1, 64, 64 }, [ POWER4_PME_PM_GCT_FULL_CYC ] = { 26, 26, -1, -1, 26, 26, -1, -1 }, [ POWER4_PME_PM_INST_FROM_MEM ] = { 87, -1, -1, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_FXU_BUSY ] = { -1, -1, -1, -1, -1, 85, -1, -1 }, [ POWER4_PME_PM_ST_REF_L1_LSU1 ] = { -1, -1, 72, 72, -1, -1, 72, 72 }, [ POWER4_PME_PM_MRK_LD_MISS_L1 ] = { 92, -1, -1, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_MRK_LSU1_INST_FIN ] = { -1, -1, 67, 67, -1, -1, 67, 67 }, [ POWER4_PME_PM_L1_WRITE_CYC ] = { -1, -1, 36, 36, -1, -1, 36, 36 }, [ POWER4_PME_PM_BIQ_IDU_FULL_CYC ] = { 0, 0, -1, -1, 0, 0, -1, -1 }, [ POWER4_PME_PM_MRK_LSU0_INST_FIN ] = { -1, -1, 62, 62, -1, -1, 62, 62 }, [ POWER4_PME_PM_L2SC_ST_REQ ] = { -1, -1, 42, 42, -1, -1, 42, 42 }, [ POWER4_PME_PM_LSU1_BUSY ] = { -1, -1, 51, 51, -1, -1, 51, 51 }, [ POWER4_PME_PM_FPU_ALL ] = { -1, -1, -1, -1, 84, -1, -1, -1 }, [ POWER4_PME_PM_LSU_SRQ_S0_ALLOC ] = { 70, 70, -1, -1, 70, 70, -1, -1 }, [ POWER4_PME_PM_GRP_MRK ] = { -1, -1, -1, -1, 90, -1, -1, -1 }, [ POWER4_PME_PM_FPU1_FIN ] = { -1, -1, 27, 27, -1, -1, 27, 27 }, [ POWER4_PME_PM_DC_PREF_STREAM_ALLOC ] = { 4, 4, -1, -1, 4, 4, -1, -1 }, [ POWER4_PME_PM_BR_MPRED_CR ] = { -1, -1, 9, 9, -1, -1, 9, 9 }, [ POWER4_PME_PM_BR_MPRED_TA ] = { -1, -1, 10, 10, -1, -1, 10, 10 }, [ POWER4_PME_PM_CRQ_FULL_CYC ] = { -1, -1, 11, 11, -1, -1, 11, 11 }, [ POWER4_PME_PM_INST_FROM_PREF ] = { -1, -1, -1, -1, -1, -1, 79, -1 }, [ POWER4_PME_PM_LD_MISS_L1 ] = { -1, -1, 79, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_STCX_PASS ] = { -1, -1, 69, 69, -1, -1, 69, 69 }, [ POWER4_PME_PM_DC_INV_L2 ] = { -1, -1, 13, 13, -1, -1, 13, 13 }, [ POWER4_PME_PM_LSU_SRQ_FULL_CYC ] = { -1, -1, 55, 55, -1, -1, 55, 55 }, [ POWER4_PME_PM_LSU0_FLUSH_LRQ ] = { 55, 55, -1, -1, 55, 55, -1, -1 }, [ POWER4_PME_PM_LSU_SRQ_S0_VALID ] = { 71, 71, -1, -1, 71, 71, -1, -1 }, [ POWER4_PME_PM_LARX_LSU0 ] = { -1, -1, 44, 44, -1, -1, 44, 44 }, [ POWER4_PME_PM_GCT_EMPTY_CYC ] = { 85, -1, -1, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_FPU1_ALL ] = { 17, 17, -1, -1, 17, 17, -1, -1 }, [ POWER4_PME_PM_FPU1_FSQRT ] = { 21, 21, -1, -1, 21, 21, -1, -1 }, [ POWER4_PME_PM_FPU_FIN ] = { -1, -1, -1, 75, -1, -1, -1, -1 }, [ POWER4_PME_PM_L2SA_SHR_MOD ] = { 40, 40, -1, -1, 40, 40, -1, -1 }, [ POWER4_PME_PM_MRK_LD_MISS_L1_LSU1 ] = { 74, 74, -1, -1, 74, 74, -1, -1 }, [ POWER4_PME_PM_LSU_SRQ_STFWD ] = { 89, -1, -1, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_FXU0_FIN ] = { -1, -1, 31, 31, -1, -1, 31, 31 }, [ POWER4_PME_PM_MRK_FPU_FIN ] = { -1, -1, -1, -1, -1, -1, 81, -1 }, [ POWER4_PME_PM_LSU_BUSY ] = { -1, -1, -1, 80, -1, -1, -1, -1 }, [ POWER4_PME_PM_INST_FROM_L35 ] = { -1, -1, -1, 78, -1, -1, -1, -1 }, [ POWER4_PME_PM_FPU1_FRSP_FCONV ] = { -1, -1, 29, 29, -1, -1, 29, 29 }, [ POWER4_PME_PM_SNOOP_TLBIE ] = { 77, 77, -1, -1, 77, 77, -1, -1 }, [ POWER4_PME_PM_FPU0_FDIV ] = { 10, 10, -1, -1, 10, 10, -1, -1 }, [ POWER4_PME_PM_LD_REF_L1_LSU1 ] = { -1, -1, 49, 49, -1, -1, 49, 49 }, [ POWER4_PME_PM_MRK_DATA_FROM_L275_MOD ] = { -1, -1, -1, -1, -1, -1, 80, -1 }, [ POWER4_PME_PM_HV_CYC ] = { -1, -1, 84, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_6INST_CLB_CYC ] = { -1, -1, 5, 5, -1, -1, 5, 5 }, [ POWER4_PME_PM_LR_CTR_MAP_FULL_CYC ] = { 53, 53, -1, -1, 53, 53, -1, -1 }, [ POWER4_PME_PM_L2SC_MOD_INV ] = { 45, 45, -1, -1, 45, 45, -1, -1 }, [ POWER4_PME_PM_FPU_DENORM ] = { 83, -1, -1, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_DATA_FROM_L275_MOD ] = { -1, -1, -1, -1, -1, -1, 74, -1 }, [ POWER4_PME_PM_LSU1_DERAT_MISS ] = { 60, 60, -1, -1, 60, 60, -1, -1 }, [ POWER4_PME_PM_IC_PREF_REQ ] = { 30, 30, -1, -1, 30, 30, -1, -1 }, [ POWER4_PME_PM_MRK_LSU_FIN ] = { -1, -1, -1, -1, -1, -1, -1, 84 }, [ POWER4_PME_PM_MRK_DATA_FROM_L3 ] = { 90, -1, -1, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_MRK_DATA_FROM_MEM ] = { -1, 90, -1, -1, -1, -1, -1, -1 }, [ POWER4_PME_PM_LSU0_FLUSH_UST ] = { 58, 58, -1, -1, 58, 58, -1, -1 }, [ POWER4_PME_PM_LSU_FLUSH_LRQ ] = { -1, -1, -1, -1, -1, 89, -1, -1 }, [ POWER4_PME_PM_LSU_FLUSH_SRQ ] = { -1, -1, -1, -1, 92, -1, -1, -1 }, [ POWER4_PME_PM_L2SC_MOD_TAG ] = { 46, 46, -1, -1, 46, 46, -1, -1 } }; static const unsigned long long power4_group_vecs[][POWER4_NUM_GROUP_VEC] = { [ POWER4_PME_PM_MRK_LSU_SRQ_INST_VALID ] = { 0x0000100000000000ULL }, [ POWER4_PME_PM_FPU1_SINGLE ] = { 0x0000000080000000ULL }, [ POWER4_PME_PM_DC_PREF_OUT_STREAMS ] = { 0x0000010000000000ULL }, [ POWER4_PME_PM_FPU0_STALL3 ] = { 0x0000000100000000ULL }, [ POWER4_PME_PM_TB_BIT_TRANS ] = { 0x0000020000000000ULL }, [ POWER4_PME_PM_GPR_MAP_FULL_CYC ] = { 0x0000000000000010ULL }, [ POWER4_PME_PM_MRK_ST_CMPL ] = { 0x0000100000000000ULL }, [ POWER4_PME_PM_MRK_LSU_FLUSH_LRQ ] = { 0x0000200000000000ULL }, [ POWER4_PME_PM_FPU0_STF ] = { 0x0000000080000000ULL }, [ POWER4_PME_PM_FPU1_FMA ] = { 0x0000000010000000ULL }, [ POWER4_PME_PM_L2SA_MOD_TAG ] = { 0x0000000000000800ULL }, [ POWER4_PME_PM_MRK_DATA_FROM_L275_SHR ] = { 0x0000c00000000000ULL }, [ POWER4_PME_PM_1INST_CLB_CYC ] = { 0x0000000000010000ULL }, [ POWER4_PME_PM_LSU1_FLUSH_ULD ] = { 0x0000001000000000ULL }, [ POWER4_PME_PM_MRK_INST_FIN ] = { 0x0008040000000000ULL }, [ POWER4_PME_PM_MRK_LSU0_FLUSH_UST ] = { 0x0002000000000000ULL }, [ POWER4_PME_PM_FPU_FDIV ] = { 0x1020000000004000ULL }, [ POWER4_PME_PM_LSU_LRQ_S0_ALLOC ] = { 0x0000000000800000ULL }, [ POWER4_PME_PM_FPU0_FULL_CYC ] = { 0x0000000000080000ULL }, [ POWER4_PME_PM_FPU_SINGLE ] = { 0x0000000000000000ULL }, [ POWER4_PME_PM_FPU0_FMA ] = { 0x0000000010000000ULL }, [ POWER4_PME_PM_MRK_LSU1_FLUSH_ULD ] = { 0x0002000000000000ULL }, [ POWER4_PME_PM_LSU1_FLUSH_LRQ ] = { 0x0000000800000000ULL }, [ POWER4_PME_PM_L2SA_ST_HIT ] = { 0x0000000000000800ULL }, [ POWER4_PME_PM_L2SB_SHR_INV ] = { 0x0000000000001000ULL }, [ POWER4_PME_PM_DTLB_MISS ] = { 0x0900000000000100ULL }, [ POWER4_PME_PM_MRK_ST_MISS_L1 ] = { 0x0002000000000000ULL }, [ POWER4_PME_PM_EXT_INT ] = { 0x0000000000200000ULL }, [ POWER4_PME_PM_MRK_LSU1_FLUSH_LRQ ] = { 0x0004000000000000ULL }, [ POWER4_PME_PM_MRK_ST_GPS ] = { 0x0000100000000000ULL }, [ POWER4_PME_PM_GRP_DISP_SUCCESS ] = { 0x0000000000020000ULL }, [ POWER4_PME_PM_LSU1_LDF ] = { 0x0000000080000000ULL }, [ POWER4_PME_PM_FAB_CMD_ISSUED ] = { 0x0000000000000400ULL }, [ POWER4_PME_PM_LSU0_SRQ_STFWD ] = { 0x0000004000000000ULL }, [ POWER4_PME_PM_CR_MAP_FULL_CYC ] = { 0x0000000000040000ULL }, [ POWER4_PME_PM_MRK_LSU0_FLUSH_ULD ] = { 0x0002000000000000ULL }, [ POWER4_PME_PM_LSU_DERAT_MISS ] = { 0x0000000000000300ULL }, [ POWER4_PME_PM_FPU0_SINGLE ] = { 0x0000000080000000ULL }, [ POWER4_PME_PM_FPU1_FDIV ] = { 0x0000000010000000ULL }, [ POWER4_PME_PM_FPU1_FEST ] = { 0x0000000040000000ULL }, [ POWER4_PME_PM_FPU0_FRSP_FCONV ] = { 0x0000000010000000ULL }, [ POWER4_PME_PM_MRK_ST_CMPL_INT ] = { 0x0000100000000000ULL }, [ POWER4_PME_PM_FXU_FIN ] = { 0x0020000000000000ULL }, [ POWER4_PME_PM_FPU_STF ] = { 0x1040000000008000ULL }, [ POWER4_PME_PM_DSLB_MISS ] = { 0x0000000000000200ULL }, [ POWER4_PME_PM_DATA_FROM_L275_SHR ] = { 0x0200000001000020ULL }, [ POWER4_PME_PM_FXLS1_FULL_CYC ] = { 0x0000000000000000ULL }, [ POWER4_PME_PM_L3B0_DIR_MIS ] = { 0x0000000000000400ULL }, [ POWER4_PME_PM_2INST_CLB_CYC ] = { 0x0000000000010000ULL }, [ POWER4_PME_PM_MRK_STCX_FAIL ] = { 0x0008000000000000ULL }, [ POWER4_PME_PM_LSU_LMQ_LHR_MERGE ] = { 0x0010000400000000ULL }, [ POWER4_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { 0x0000000200000000ULL }, [ POWER4_PME_PM_L3B1_DIR_REF ] = { 0x0000000000000400ULL }, [ POWER4_PME_PM_MRK_LSU_FLUSH_UST ] = { 0x0000000000000000ULL }, [ POWER4_PME_PM_MRK_DATA_FROM_L25_SHR ] = { 0x0000c00000000000ULL }, [ POWER4_PME_PM_LSU_FLUSH_ULD ] = { 0x0000000000000080ULL }, [ POWER4_PME_PM_MRK_BRU_FIN ] = { 0x0000080000000000ULL }, [ POWER4_PME_PM_IERAT_XLATE_WR ] = { 0x0000000000000300ULL }, [ POWER4_PME_PM_LSU0_BUSY ] = { 0x0000000000800000ULL }, [ POWER4_PME_PM_L2SA_ST_REQ ] = { 0x0000000000000800ULL }, [ POWER4_PME_PM_DATA_FROM_MEM ] = { 0x0400000002000020ULL }, [ POWER4_PME_PM_FPR_MAP_FULL_CYC ] = { 0x0000000000000010ULL }, [ POWER4_PME_PM_FPU1_FULL_CYC ] = { 0x0000000000080000ULL }, [ POWER4_PME_PM_FPU0_FIN ] = { 0x1040000120000000ULL }, [ POWER4_PME_PM_3INST_CLB_CYC ] = { 0x0000000000010000ULL }, [ POWER4_PME_PM_DATA_FROM_L35 ] = { 0x0600000002000020ULL }, [ POWER4_PME_PM_L2SA_SHR_INV ] = { 0x0000000000000800ULL }, [ POWER4_PME_PM_MRK_LSU_FLUSH_SRQ ] = { 0x0000200000000000ULL }, [ POWER4_PME_PM_THRESH_TIMEO ] = { 0x0010040000000000ULL }, [ POWER4_PME_PM_FPU_FSQRT ] = { 0x0020000000004000ULL }, [ POWER4_PME_PM_MRK_LSU0_FLUSH_LRQ ] = { 0x0004000000000000ULL }, [ POWER4_PME_PM_FXLS0_FULL_CYC ] = { 0x0000000000080000ULL }, [ POWER4_PME_PM_DATA_TABLEWALK_CYC ] = { 0x0000000400000100ULL }, [ POWER4_PME_PM_FPU0_ALL ] = { 0x0000000020000000ULL }, [ POWER4_PME_PM_FPU0_FEST ] = { 0x0000000040000000ULL }, [ POWER4_PME_PM_DATA_FROM_L25_MOD ] = { 0x0600000001000020ULL }, [ POWER4_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { 0x0800020000000000ULL }, [ POWER4_PME_PM_FPU_FEST ] = { 0x0000000000004000ULL }, [ POWER4_PME_PM_0INST_FETCH ] = { 0x0000000004000040ULL }, [ POWER4_PME_PM_LARX_LSU1 ] = { 0x0000000000400000ULL }, [ POWER4_PME_PM_LD_MISS_L1_LSU0 ] = { 0x0000001000000000ULL }, [ POWER4_PME_PM_L1_PREF ] = { 0x0000010000000000ULL }, [ POWER4_PME_PM_FPU1_STALL3 ] = { 0x0000000100000000ULL }, [ POWER4_PME_PM_BRQ_FULL_CYC ] = { 0x0080000000000010ULL }, [ POWER4_PME_PM_LARX ] = { 0x0000000000000000ULL }, [ POWER4_PME_PM_MRK_DATA_FROM_L35 ] = { 0x0001400000000000ULL }, [ POWER4_PME_PM_WORK_HELD ] = { 0x0000000000200000ULL }, [ POWER4_PME_PM_MRK_LD_MISS_L1_LSU0 ] = { 0x0004000000000000ULL }, [ POWER4_PME_PM_FXU_IDLE ] = { 0x0000000200000000ULL }, [ POWER4_PME_PM_INST_CMPL ] = { 0x7fffb7ffffffff9fULL }, [ POWER4_PME_PM_LSU1_FLUSH_UST ] = { 0x0000002000000000ULL }, [ POWER4_PME_PM_LSU0_FLUSH_ULD ] = { 0x0000001000000000ULL }, [ POWER4_PME_PM_INST_FROM_L2 ] = { 0x000000000c000040ULL }, [ POWER4_PME_PM_DATA_FROM_L3 ] = { 0x0400000002000020ULL }, [ POWER4_PME_PM_FPU0_DENORM ] = { 0x0000000040000000ULL }, [ POWER4_PME_PM_FPU1_FMOV_FEST ] = { 0x0000000040000000ULL }, [ POWER4_PME_PM_GRP_DISP_REJECT ] = { 0x0000000000100001ULL }, [ POWER4_PME_PM_INST_FETCH_CYC ] = { 0x0000000000000008ULL }, [ POWER4_PME_PM_LSU_LDF ] = { 0x1040000000008000ULL }, [ POWER4_PME_PM_INST_DISP ] = { 0x0000000000140006ULL }, [ POWER4_PME_PM_L2SA_MOD_INV ] = { 0x0000000000000800ULL }, [ POWER4_PME_PM_DATA_FROM_L25_SHR ] = { 0x0600000001000020ULL }, [ POWER4_PME_PM_FAB_CMD_RETRIED ] = { 0x0000000000000400ULL }, [ POWER4_PME_PM_L1_DCACHE_RELOAD_VALID ] = { 0x0000008003000000ULL }, [ POWER4_PME_PM_MRK_GRP_ISSUED ] = { 0x0018240000000000ULL }, [ POWER4_PME_PM_FPU_FULL_CYC ] = { 0x0040000000000010ULL }, [ POWER4_PME_PM_FPU_FMA ] = { 0x1020000000004000ULL }, [ POWER4_PME_PM_MRK_CRU_FIN ] = { 0x0000080000000000ULL }, [ POWER4_PME_PM_MRK_LSU1_FLUSH_UST ] = { 0x0002000000000000ULL }, [ POWER4_PME_PM_MRK_FXU_FIN ] = { 0x0000080000000000ULL }, [ POWER4_PME_PM_BR_ISSUED ] = { 0x6080000000000008ULL }, [ POWER4_PME_PM_EE_OFF ] = { 0x0000000000200000ULL }, [ POWER4_PME_PM_INST_FROM_L3 ] = { 0x000000000c000040ULL }, [ POWER4_PME_PM_ITLB_MISS ] = { 0x0100000000000100ULL }, [ POWER4_PME_PM_FXLS_FULL_CYC ] = { 0x0000000200000010ULL }, [ POWER4_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { 0x0000000200000000ULL }, [ POWER4_PME_PM_GRP_DISP_VALID ] = { 0x0000000000100000ULL }, [ POWER4_PME_PM_L2SC_ST_HIT ] = { 0x0000000000002000ULL }, [ POWER4_PME_PM_MRK_GRP_DISP ] = { 0x0000080000000000ULL }, [ POWER4_PME_PM_L2SB_MOD_TAG ] = { 0x0000000000001000ULL }, [ POWER4_PME_PM_INST_FROM_L25_L275 ] = { 0x0000000008000040ULL }, [ POWER4_PME_PM_LSU_FLUSH_UST ] = { 0x0000000000000080ULL }, [ POWER4_PME_PM_L2SB_ST_HIT ] = { 0x0000000000001000ULL }, [ POWER4_PME_PM_FXU1_FIN ] = { 0x0000000000100000ULL }, [ POWER4_PME_PM_L3B1_DIR_MIS ] = { 0x0000000000000400ULL }, [ POWER4_PME_PM_4INST_CLB_CYC ] = { 0x0000000000010000ULL }, [ POWER4_PME_PM_GRP_CMPL ] = { 0x0010020000000001ULL }, [ POWER4_PME_PM_DC_PREF_L2_CLONE_L3 ] = { 0x0000010000000000ULL }, [ POWER4_PME_PM_FPU_FRSP_FCONV ] = { 0x0000000000008000ULL }, [ POWER4_PME_PM_5INST_CLB_CYC ] = { 0x0000000000020000ULL }, [ POWER4_PME_PM_MRK_LSU0_FLUSH_SRQ ] = { 0x0004000000000000ULL }, [ POWER4_PME_PM_MRK_LSU_FLUSH_ULD ] = { 0x0000200000000000ULL }, [ POWER4_PME_PM_8INST_CLB_CYC ] = { 0x0000000000020000ULL }, [ POWER4_PME_PM_LSU_LMQ_FULL_CYC ] = { 0x0000000400000000ULL }, [ POWER4_PME_PM_ST_REF_L1_LSU0 ] = { 0x0000006000000000ULL }, [ POWER4_PME_PM_LSU0_DERAT_MISS ] = { 0x0000008000000000ULL }, [ POWER4_PME_PM_LSU_SRQ_SYNC_CYC ] = { 0x0000000400000200ULL }, [ POWER4_PME_PM_FPU_STALL3 ] = { 0x0040000000008000ULL }, [ POWER4_PME_PM_MRK_DATA_FROM_L2 ] = { 0x0001c00000000000ULL }, [ POWER4_PME_PM_FPU0_FMOV_FEST ] = { 0x0000000040000000ULL }, [ POWER4_PME_PM_LSU0_FLUSH_SRQ ] = { 0x0000000800000000ULL }, [ POWER4_PME_PM_LD_REF_L1_LSU0 ] = { 0x0000001000000000ULL }, [ POWER4_PME_PM_L2SC_SHR_INV ] = { 0x0000000000002000ULL }, [ POWER4_PME_PM_LSU1_FLUSH_SRQ ] = { 0x0000000800000000ULL }, [ POWER4_PME_PM_LSU_LMQ_S0_ALLOC ] = { 0x0010000400000200ULL }, [ POWER4_PME_PM_ST_REF_L1 ] = { 0x4900000000000086ULL }, [ POWER4_PME_PM_LSU_SRQ_EMPTY_CYC ] = { 0x0000000000000000ULL }, [ POWER4_PME_PM_FPU1_STF ] = { 0x0000000080000000ULL }, [ POWER4_PME_PM_L3B0_DIR_REF ] = { 0x0000000000000400ULL }, [ POWER4_PME_PM_RUN_CYC ] = { 0x0000000000000001ULL }, [ POWER4_PME_PM_LSU_LMQ_S0_VALID ] = { 0x0010000400000100ULL }, [ POWER4_PME_PM_LSU_LRQ_S0_VALID ] = { 0x0000000000800000ULL }, [ POWER4_PME_PM_LSU0_LDF ] = { 0x0000000080000000ULL }, [ POWER4_PME_PM_MRK_IMR_RELOAD ] = { 0x0002000000000000ULL }, [ POWER4_PME_PM_7INST_CLB_CYC ] = { 0x0000000000020000ULL }, [ POWER4_PME_PM_MRK_GRP_TIMEO ] = { 0x0000300000000000ULL }, [ POWER4_PME_PM_FPU_FMOV_FEST ] = { 0x0020000000004000ULL }, [ POWER4_PME_PM_GRP_DISP_BLK_SB_CYC ] = { 0x0000000000040000ULL }, [ POWER4_PME_PM_XER_MAP_FULL_CYC ] = { 0x0000000000040000ULL }, [ POWER4_PME_PM_ST_MISS_L1 ] = { 0x6900006000000000ULL }, [ POWER4_PME_PM_STOP_COMPLETION ] = { 0x0000000000200001ULL }, [ POWER4_PME_PM_MRK_GRP_CMPL ] = { 0x0000140000000000ULL }, [ POWER4_PME_PM_ISLB_MISS ] = { 0x0000000000000200ULL }, [ POWER4_PME_PM_CYC ] = { 0x7fffbfffffffff9fULL }, [ POWER4_PME_PM_LD_MISS_L1_LSU1 ] = { 0x0000001000000000ULL }, [ POWER4_PME_PM_STCX_FAIL ] = { 0x0000000000400000ULL }, [ POWER4_PME_PM_LSU1_SRQ_STFWD ] = { 0x0000004000000000ULL }, [ POWER4_PME_PM_GRP_DISP ] = { 0x0000000000000000ULL }, [ POWER4_PME_PM_DATA_FROM_L2 ] = { 0x0600000003000020ULL }, [ POWER4_PME_PM_L2_PREF ] = { 0x0000010000000000ULL }, [ POWER4_PME_PM_FPU0_FPSCR ] = { 0x0000000100000000ULL }, [ POWER4_PME_PM_FPU1_DENORM ] = { 0x0000000040000000ULL }, [ POWER4_PME_PM_MRK_DATA_FROM_L25_MOD ] = { 0x0000c00000000000ULL }, [ POWER4_PME_PM_L2SB_ST_REQ ] = { 0x0000000000001000ULL }, [ POWER4_PME_PM_L2SB_MOD_INV ] = { 0x0000000000001000ULL }, [ POWER4_PME_PM_FPU0_FSQRT ] = { 0x0000000020000000ULL }, [ POWER4_PME_PM_LD_REF_L1 ] = { 0x4900000000000086ULL }, [ POWER4_PME_PM_MRK_L1_RELOAD_VALID ] = { 0x0001800000000000ULL }, [ POWER4_PME_PM_L2SB_SHR_MOD ] = { 0x0000000000001000ULL }, [ POWER4_PME_PM_INST_FROM_L1 ] = { 0x000000000c000040ULL }, [ POWER4_PME_PM_1PLUS_PPC_CMPL ] = { 0x0000020000410001ULL }, [ POWER4_PME_PM_EE_OFF_EXT_INT ] = { 0x0000000000200000ULL }, [ POWER4_PME_PM_L2SC_SHR_MOD ] = { 0x0000000000002000ULL }, [ POWER4_PME_PM_LSU_LRQ_FULL_CYC ] = { 0x0000000000080000ULL }, [ POWER4_PME_PM_IC_PREF_INSTALL ] = { 0x0000000000000000ULL }, [ POWER4_PME_PM_MRK_LSU1_FLUSH_SRQ ] = { 0x0004000000000000ULL }, [ POWER4_PME_PM_GCT_FULL_CYC ] = { 0x0000000000000010ULL }, [ POWER4_PME_PM_INST_FROM_MEM ] = { 0x0000000008000040ULL }, [ POWER4_PME_PM_FXU_BUSY ] = { 0x0000000200000000ULL }, [ POWER4_PME_PM_ST_REF_L1_LSU1 ] = { 0x0000006000000000ULL }, [ POWER4_PME_PM_MRK_LD_MISS_L1 ] = { 0x0000240000000000ULL }, [ POWER4_PME_PM_MRK_LSU1_INST_FIN ] = { 0x0008000000000000ULL }, [ POWER4_PME_PM_L1_WRITE_CYC ] = { 0x0080000000000008ULL }, [ POWER4_PME_PM_BIQ_IDU_FULL_CYC ] = { 0x0080000000000008ULL }, [ POWER4_PME_PM_MRK_LSU0_INST_FIN ] = { 0x0008000000000000ULL }, [ POWER4_PME_PM_L2SC_ST_REQ ] = { 0x0000000000002000ULL }, [ POWER4_PME_PM_LSU1_BUSY ] = { 0x0000000000800000ULL }, [ POWER4_PME_PM_FPU_ALL ] = { 0x0000000000008000ULL }, [ POWER4_PME_PM_LSU_SRQ_S0_ALLOC ] = { 0x0000000000800000ULL }, [ POWER4_PME_PM_GRP_MRK ] = { 0x00000c0000000000ULL }, [ POWER4_PME_PM_FPU1_FIN ] = { 0x1040000120000000ULL }, [ POWER4_PME_PM_DC_PREF_STREAM_ALLOC ] = { 0x0000010000000000ULL }, [ POWER4_PME_PM_BR_MPRED_CR ] = { 0x2080000000000008ULL }, [ POWER4_PME_PM_BR_MPRED_TA ] = { 0x2080000000000008ULL }, [ POWER4_PME_PM_CRQ_FULL_CYC ] = { 0x0000000000040000ULL }, [ POWER4_PME_PM_INST_FROM_PREF ] = { 0x0000000004000040ULL }, [ POWER4_PME_PM_LD_MISS_L1 ] = { 0x6900000000000006ULL }, [ POWER4_PME_PM_STCX_PASS ] = { 0x0000000000400000ULL }, [ POWER4_PME_PM_DC_INV_L2 ] = { 0x0000002000000006ULL }, [ POWER4_PME_PM_LSU_SRQ_FULL_CYC ] = { 0x0000000000080000ULL }, [ POWER4_PME_PM_LSU0_FLUSH_LRQ ] = { 0x0000000800000000ULL }, [ POWER4_PME_PM_LSU_SRQ_S0_VALID ] = { 0x0000000000800000ULL }, [ POWER4_PME_PM_LARX_LSU0 ] = { 0x0000000000400000ULL }, [ POWER4_PME_PM_GCT_EMPTY_CYC ] = { 0x0000020000200000ULL }, [ POWER4_PME_PM_FPU1_ALL ] = { 0x0000000020000000ULL }, [ POWER4_PME_PM_FPU1_FSQRT ] = { 0x0000000020000000ULL }, [ POWER4_PME_PM_FPU_FIN ] = { 0x0020000000004000ULL }, [ POWER4_PME_PM_L2SA_SHR_MOD ] = { 0x0000000000000800ULL }, [ POWER4_PME_PM_MRK_LD_MISS_L1_LSU1 ] = { 0x0004000000000000ULL }, [ POWER4_PME_PM_LSU_SRQ_STFWD ] = { 0x0000000000000000ULL }, [ POWER4_PME_PM_FXU0_FIN ] = { 0x0000000000100000ULL }, [ POWER4_PME_PM_MRK_FPU_FIN ] = { 0x0000080000000000ULL }, [ POWER4_PME_PM_LSU_BUSY ] = { 0x0000000000000000ULL }, [ POWER4_PME_PM_INST_FROM_L35 ] = { 0x000000000c000040ULL }, [ POWER4_PME_PM_FPU1_FRSP_FCONV ] = { 0x0000000010000000ULL }, [ POWER4_PME_PM_SNOOP_TLBIE ] = { 0x0000000000400000ULL }, [ POWER4_PME_PM_FPU0_FDIV ] = { 0x0000000010000000ULL }, [ POWER4_PME_PM_LD_REF_L1_LSU1 ] = { 0x0000001000000000ULL }, [ POWER4_PME_PM_MRK_DATA_FROM_L275_MOD ] = { 0x0001c00000000000ULL }, [ POWER4_PME_PM_HV_CYC ] = { 0x0000020000000000ULL }, [ POWER4_PME_PM_6INST_CLB_CYC ] = { 0x0000000000020000ULL }, [ POWER4_PME_PM_LR_CTR_MAP_FULL_CYC ] = { 0x0000000000040000ULL }, [ POWER4_PME_PM_L2SC_MOD_INV ] = { 0x0000000000002000ULL }, [ POWER4_PME_PM_FPU_DENORM ] = { 0x0000000000008000ULL }, [ POWER4_PME_PM_DATA_FROM_L275_MOD ] = { 0x0200000003000020ULL }, [ POWER4_PME_PM_LSU1_DERAT_MISS ] = { 0x0000008000000000ULL }, [ POWER4_PME_PM_IC_PREF_REQ ] = { 0x0000000000000000ULL }, [ POWER4_PME_PM_MRK_LSU_FIN ] = { 0x0000080000000000ULL }, [ POWER4_PME_PM_MRK_DATA_FROM_L3 ] = { 0x0001400000000000ULL }, [ POWER4_PME_PM_MRK_DATA_FROM_MEM ] = { 0x0001400000000000ULL }, [ POWER4_PME_PM_LSU0_FLUSH_UST ] = { 0x0000002000000000ULL }, [ POWER4_PME_PM_LSU_FLUSH_LRQ ] = { 0x0000000000000080ULL }, [ POWER4_PME_PM_LSU_FLUSH_SRQ ] = { 0x0000000000000080ULL }, [ POWER4_PME_PM_L2SC_MOD_TAG ] = { 0x0000000000002000ULL } }; static const pme_power_entry_t power4_pe[] = { [ POWER4_PME_PM_MRK_LSU_SRQ_INST_VALID ] = { .pme_name = "PM_MRK_LSU_SRQ_INST_VALID", .pme_code = 0x933, .pme_short_desc = "Marked instruction valid in SRQ", .pme_long_desc = "This signal is asserted every cycle when a marked request is resident in the Store Request Queue", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU_SRQ_INST_VALID], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU_SRQ_INST_VALID] }, [ POWER4_PME_PM_FPU1_SINGLE ] = { .pme_name = "PM_FPU1_SINGLE", .pme_code = 0x127, .pme_short_desc = "FPU1 executed single precision instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing single precision instruction.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU1_SINGLE], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU1_SINGLE] }, [ POWER4_PME_PM_DC_PREF_OUT_STREAMS ] = { .pme_name = "PM_DC_PREF_OUT_STREAMS", .pme_code = 0xc36, .pme_short_desc = "Out of prefetch streams", .pme_long_desc = "A new prefetch stream was detected, but no more stream entries were available", .pme_event_ids = power4_event_ids[POWER4_PME_PM_DC_PREF_OUT_STREAMS], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DC_PREF_OUT_STREAMS] }, [ POWER4_PME_PM_FPU0_STALL3 ] = { .pme_name = "PM_FPU0_STALL3", .pme_code = 0x121, .pme_short_desc = "FPU0 stalled in pipe3", .pme_long_desc = "This signal indicates that fp0 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. ", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU0_STALL3], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU0_STALL3] }, [ POWER4_PME_PM_TB_BIT_TRANS ] = { .pme_name = "PM_TB_BIT_TRANS", .pme_code = 0x8005, .pme_short_desc = "Time Base bit transition", .pme_long_desc = "When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 ", .pme_event_ids = power4_event_ids[POWER4_PME_PM_TB_BIT_TRANS], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_TB_BIT_TRANS] }, [ POWER4_PME_PM_GPR_MAP_FULL_CYC ] = { .pme_name = "PM_GPR_MAP_FULL_CYC", .pme_code = 0x235, .pme_short_desc = "Cycles GPR mapper full", .pme_long_desc = "The ISU sends a signal indicating that the gpr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_GPR_MAP_FULL_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_GPR_MAP_FULL_CYC] }, [ POWER4_PME_PM_MRK_ST_CMPL ] = { .pme_name = "PM_MRK_ST_CMPL", .pme_code = 0x1003, .pme_short_desc = "Marked store instruction completed", .pme_long_desc = "A sampled store has completed (data home)", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_ST_CMPL], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_ST_CMPL] }, [ POWER4_PME_PM_MRK_LSU_FLUSH_LRQ ] = { .pme_name = "PM_MRK_LSU_FLUSH_LRQ", .pme_code = 0x3910, .pme_short_desc = "Marked LRQ flushes", .pme_long_desc = "A marked load was flushed because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU_FLUSH_LRQ], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU_FLUSH_LRQ] }, [ POWER4_PME_PM_FPU0_STF ] = { .pme_name = "PM_FPU0_STF", .pme_code = 0x122, .pme_short_desc = "FPU0 executed store instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing a store instruction.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU0_STF], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU0_STF] }, [ POWER4_PME_PM_FPU1_FMA ] = { .pme_name = "PM_FPU1_FMA", .pme_code = 0x105, .pme_short_desc = "FPU1 executed multiply-add instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU1_FMA], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU1_FMA] }, [ POWER4_PME_PM_L2SA_MOD_TAG ] = { .pme_name = "PM_L2SA_MOD_TAG", .pme_code = 0xf06, .pme_short_desc = "L2 slice A transition from modified to tagged", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SA_MOD_TAG], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SA_MOD_TAG] }, [ POWER4_PME_PM_MRK_DATA_FROM_L275_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L275_SHR", .pme_code = 0x6c76, .pme_short_desc = "Marked data loaded from L2.75 shared", .pme_long_desc = "DL1 was reloaded with shared (T) data from the L2 of another MCM due to a marked demand load", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_DATA_FROM_L275_SHR], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_DATA_FROM_L275_SHR] }, [ POWER4_PME_PM_1INST_CLB_CYC ] = { .pme_name = "PM_1INST_CLB_CYC", .pme_code = 0x450, .pme_short_desc = "Cycles 1 instruction in CLB", .pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_1INST_CLB_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_1INST_CLB_CYC] }, [ POWER4_PME_PM_LSU1_FLUSH_ULD ] = { .pme_name = "PM_LSU1_FLUSH_ULD", .pme_code = 0xc04, .pme_short_desc = "LSU1 unaligned load flushes", .pme_long_desc = "A load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU1_FLUSH_ULD], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU1_FLUSH_ULD] }, [ POWER4_PME_PM_MRK_INST_FIN ] = { .pme_name = "PM_MRK_INST_FIN", .pme_code = 0x7005, .pme_short_desc = "Marked instruction finished", .pme_long_desc = "One of the execution units finished a marked instruction. Instructions that finish may not necessary complete", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_INST_FIN], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_INST_FIN] }, [ POWER4_PME_PM_MRK_LSU0_FLUSH_UST ] = { .pme_name = "PM_MRK_LSU0_FLUSH_UST", .pme_code = 0x911, .pme_short_desc = "LSU0 marked unaligned store flushes", .pme_long_desc = "A marked store was flushed from unit 0 because it was unaligned", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU0_FLUSH_UST], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU0_FLUSH_UST] }, [ POWER4_PME_PM_FPU_FDIV ] = { .pme_name = "PM_FPU_FDIV", .pme_code = 0x1100, .pme_short_desc = "FPU executed FDIV instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when FPU is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs. Combined Unit 0 + Unit 1", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU_FDIV], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU_FDIV] }, [ POWER4_PME_PM_LSU_LRQ_S0_ALLOC ] = { .pme_name = "PM_LSU_LRQ_S0_ALLOC", .pme_code = 0xc26, .pme_short_desc = "LRQ slot 0 allocated", .pme_long_desc = "LRQ slot zero was allocated", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_LRQ_S0_ALLOC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_LRQ_S0_ALLOC] }, [ POWER4_PME_PM_FPU0_FULL_CYC ] = { .pme_name = "PM_FPU0_FULL_CYC", .pme_code = 0x203, .pme_short_desc = "Cycles FPU0 issue queue full", .pme_long_desc = "The issue queue for FPU unit 0 cannot accept any more instructions. Issue is stopped", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU0_FULL_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU0_FULL_CYC] }, [ POWER4_PME_PM_FPU_SINGLE ] = { .pme_name = "PM_FPU_SINGLE", .pme_code = 0x5120, .pme_short_desc = "FPU executed single precision instruction", .pme_long_desc = "FPU is executing single precision instruction. Combined Unit 0 + Unit 1", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU_SINGLE], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU_SINGLE] }, [ POWER4_PME_PM_FPU0_FMA ] = { .pme_name = "PM_FPU0_FMA", .pme_code = 0x101, .pme_short_desc = "FPU0 executed multiply-add instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU0_FMA], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU0_FMA] }, [ POWER4_PME_PM_MRK_LSU1_FLUSH_ULD ] = { .pme_name = "PM_MRK_LSU1_FLUSH_ULD", .pme_code = 0x914, .pme_short_desc = "LSU1 marked unaligned load flushes", .pme_long_desc = "A marked load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU1_FLUSH_ULD], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU1_FLUSH_ULD] }, [ POWER4_PME_PM_LSU1_FLUSH_LRQ ] = { .pme_name = "PM_LSU1_FLUSH_LRQ", .pme_code = 0xc06, .pme_short_desc = "LSU1 LRQ flushes", .pme_long_desc = "A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU1_FLUSH_LRQ], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU1_FLUSH_LRQ] }, [ POWER4_PME_PM_L2SA_ST_HIT ] = { .pme_name = "PM_L2SA_ST_HIT", .pme_code = 0xf11, .pme_short_desc = "L2 slice A store hits", .pme_long_desc = "A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A,B, and C.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SA_ST_HIT], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SA_ST_HIT] }, [ POWER4_PME_PM_L2SB_SHR_INV ] = { .pme_name = "PM_L2SB_SHR_INV", .pme_code = 0xf21, .pme_short_desc = "L2 slice B transition from shared to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A,B,and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SB_SHR_INV], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SB_SHR_INV] }, [ POWER4_PME_PM_DTLB_MISS ] = { .pme_name = "PM_DTLB_MISS", .pme_code = 0x904, .pme_short_desc = "Data TLB misses", .pme_long_desc = "A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_DTLB_MISS], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DTLB_MISS] }, [ POWER4_PME_PM_MRK_ST_MISS_L1 ] = { .pme_name = "PM_MRK_ST_MISS_L1", .pme_code = 0x923, .pme_short_desc = "Marked L1 D cache store misses", .pme_long_desc = "A marked store missed the dcache", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_ST_MISS_L1], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_ST_MISS_L1] }, [ POWER4_PME_PM_EXT_INT ] = { .pme_name = "PM_EXT_INT", .pme_code = 0x8002, .pme_short_desc = "External interrupts", .pme_long_desc = "An external interrupt occurred", .pme_event_ids = power4_event_ids[POWER4_PME_PM_EXT_INT], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_EXT_INT] }, [ POWER4_PME_PM_MRK_LSU1_FLUSH_LRQ ] = { .pme_name = "PM_MRK_LSU1_FLUSH_LRQ", .pme_code = 0x916, .pme_short_desc = "LSU1 marked LRQ flushes", .pme_long_desc = "A marked load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU1_FLUSH_LRQ], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU1_FLUSH_LRQ] }, [ POWER4_PME_PM_MRK_ST_GPS ] = { .pme_name = "PM_MRK_ST_GPS", .pme_code = 0x6003, .pme_short_desc = "Marked store sent to GPS", .pme_long_desc = "A sampled store has been sent to the memory subsystem", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_ST_GPS], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_ST_GPS] }, [ POWER4_PME_PM_GRP_DISP_SUCCESS ] = { .pme_name = "PM_GRP_DISP_SUCCESS", .pme_code = 0x5001, .pme_short_desc = "Group dispatch success", .pme_long_desc = "Number of groups sucessfully dispatched (not rejected)", .pme_event_ids = power4_event_ids[POWER4_PME_PM_GRP_DISP_SUCCESS], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_GRP_DISP_SUCCESS] }, [ POWER4_PME_PM_LSU1_LDF ] = { .pme_name = "PM_LSU1_LDF", .pme_code = 0x934, .pme_short_desc = "LSU1 executed Floating Point load instruction", .pme_long_desc = "A floating point load was executed from LSU unit 1", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU1_LDF], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU1_LDF] }, [ POWER4_PME_PM_FAB_CMD_ISSUED ] = { .pme_name = "PM_FAB_CMD_ISSUED", .pme_code = 0xf16, .pme_short_desc = "Fabric command issued", .pme_long_desc = "A bus command was issued on the MCM to MCM fabric from the local (this chip's) Fabric Bus Controller. This event is scaled to the fabric frequency and must be adjusted for a true count. i.e. if the fabric is running 2:1, divide the count by 2.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FAB_CMD_ISSUED], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FAB_CMD_ISSUED] }, [ POWER4_PME_PM_LSU0_SRQ_STFWD ] = { .pme_name = "PM_LSU0_SRQ_STFWD", .pme_code = 0xc20, .pme_short_desc = "LSU0 SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load on unit 0", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU0_SRQ_STFWD], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU0_SRQ_STFWD] }, [ POWER4_PME_PM_CR_MAP_FULL_CYC ] = { .pme_name = "PM_CR_MAP_FULL_CYC", .pme_code = 0x204, .pme_short_desc = "Cycles CR logical operation mapper full", .pme_long_desc = "The ISU sends a signal indicating that the cr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_CR_MAP_FULL_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_CR_MAP_FULL_CYC] }, [ POWER4_PME_PM_MRK_LSU0_FLUSH_ULD ] = { .pme_name = "PM_MRK_LSU0_FLUSH_ULD", .pme_code = 0x910, .pme_short_desc = "LSU0 marked unaligned load flushes", .pme_long_desc = "A marked load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU0_FLUSH_ULD], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU0_FLUSH_ULD] }, [ POWER4_PME_PM_LSU_DERAT_MISS ] = { .pme_name = "PM_LSU_DERAT_MISS", .pme_code = 0x6900, .pme_short_desc = "DERAT misses", .pme_long_desc = "Total D-ERAT Misses (Unit 0 + Unit 1). Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_DERAT_MISS], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_DERAT_MISS] }, [ POWER4_PME_PM_FPU0_SINGLE ] = { .pme_name = "PM_FPU0_SINGLE", .pme_code = 0x123, .pme_short_desc = "FPU0 executed single precision instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing single precision instruction.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU0_SINGLE], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU0_SINGLE] }, [ POWER4_PME_PM_FPU1_FDIV ] = { .pme_name = "PM_FPU1_FDIV", .pme_code = 0x104, .pme_short_desc = "FPU1 executed FDIV instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp1 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU1_FDIV], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU1_FDIV] }, [ POWER4_PME_PM_FPU1_FEST ] = { .pme_name = "PM_FPU1_FEST", .pme_code = 0x116, .pme_short_desc = "FPU1 executed FEST instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. ", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU1_FEST], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU1_FEST] }, [ POWER4_PME_PM_FPU0_FRSP_FCONV ] = { .pme_name = "PM_FPU0_FRSP_FCONV", .pme_code = 0x111, .pme_short_desc = "FPU0 executed FRSP or FCONV instructions", .pme_long_desc = "fThis signal is active for one cycle when fp0 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU0_FRSP_FCONV], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU0_FRSP_FCONV] }, [ POWER4_PME_PM_MRK_ST_CMPL_INT ] = { .pme_name = "PM_MRK_ST_CMPL_INT", .pme_code = 0x3003, .pme_short_desc = "Marked store completed with intervention", .pme_long_desc = "A marked store previously sent to the memory subsystem completed (data home) after requiring intervention", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_ST_CMPL_INT], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_ST_CMPL_INT] }, [ POWER4_PME_PM_FXU_FIN ] = { .pme_name = "PM_FXU_FIN", .pme_code = 0x3230, .pme_short_desc = "FXU produced a result", .pme_long_desc = "The fixed point unit (Unit 0 + Unit 1) finished a marked instruction. Instructions that finish may not necessary complete.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FXU_FIN], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FXU_FIN] }, [ POWER4_PME_PM_FPU_STF ] = { .pme_name = "PM_FPU_STF", .pme_code = 0x6120, .pme_short_desc = "FPU executed store instruction", .pme_long_desc = "FPU is executing a store instruction. Combined Unit 0 + Unit 1", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU_STF], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU_STF] }, [ POWER4_PME_PM_DSLB_MISS ] = { .pme_name = "PM_DSLB_MISS", .pme_code = 0x905, .pme_short_desc = "Data SLB misses", .pme_long_desc = "A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve", .pme_event_ids = power4_event_ids[POWER4_PME_PM_DSLB_MISS], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DSLB_MISS] }, [ POWER4_PME_PM_DATA_FROM_L275_SHR ] = { .pme_name = "PM_DATA_FROM_L275_SHR", .pme_code = 0x6c66, .pme_short_desc = "Data loaded from L2.75 shared", .pme_long_desc = "DL1 was reloaded with shared (T) data from the L2 of another MCM due to a demand load", .pme_event_ids = power4_event_ids[POWER4_PME_PM_DATA_FROM_L275_SHR], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DATA_FROM_L275_SHR] }, [ POWER4_PME_PM_FXLS1_FULL_CYC ] = { .pme_name = "PM_FXLS1_FULL_CYC", .pme_code = 0x214, .pme_short_desc = "Cycles FXU1/LS1 queue full", .pme_long_desc = "The issue queue for FXU/LSU unit 1 cannot accept any more instructions. Issue is stopped", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FXLS1_FULL_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FXLS1_FULL_CYC] }, [ POWER4_PME_PM_L3B0_DIR_MIS ] = { .pme_name = "PM_L3B0_DIR_MIS", .pme_code = 0xf01, .pme_short_desc = "L3 bank 0 directory misses", .pme_long_desc = "A reference was made to the local L3 directory by a local CPU and it missed in the L3. Only requests from on-MCM CPUs are counted. This event is scaled to the L3 speed and the count must be scaled. i.e. if the L3 is running 3:1, divide the count by 3", .pme_event_ids = power4_event_ids[POWER4_PME_PM_L3B0_DIR_MIS], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L3B0_DIR_MIS] }, [ POWER4_PME_PM_2INST_CLB_CYC ] = { .pme_name = "PM_2INST_CLB_CYC", .pme_code = 0x451, .pme_short_desc = "Cycles 2 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_2INST_CLB_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_2INST_CLB_CYC] }, [ POWER4_PME_PM_MRK_STCX_FAIL ] = { .pme_name = "PM_MRK_STCX_FAIL", .pme_code = 0x925, .pme_short_desc = "Marked STCX failed", .pme_long_desc = "A marked stcx (stwcx or stdcx) failed", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_STCX_FAIL], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_STCX_FAIL] }, [ POWER4_PME_PM_LSU_LMQ_LHR_MERGE ] = { .pme_name = "PM_LSU_LMQ_LHR_MERGE", .pme_code = 0x926, .pme_short_desc = "LMQ LHR merges", .pme_long_desc = "A dcache miss occured for the same real cache line address as an earlier request already in the Load Miss Queue and was merged into the LMQ entry.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_LMQ_LHR_MERGE], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_LMQ_LHR_MERGE] }, [ POWER4_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { .pme_name = "PM_FXU0_BUSY_FXU1_IDLE", .pme_code = 0x7002, .pme_short_desc = "FXU0 busy FXU1 idle", .pme_long_desc = "FXU0 is busy while FXU1 was idle", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FXU0_BUSY_FXU1_IDLE], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FXU0_BUSY_FXU1_IDLE] }, [ POWER4_PME_PM_L3B1_DIR_REF ] = { .pme_name = "PM_L3B1_DIR_REF", .pme_code = 0xf02, .pme_short_desc = "L3 bank 1 directory references", .pme_long_desc = "A reference was made to the local L3 directory by a local CPU. Only requests from on-MCM CPUs are counted. This event is scaled to the L3 speed and the count must be scaled. i.e. if the L3 is running 3:1, divide the count by 3", .pme_event_ids = power4_event_ids[POWER4_PME_PM_L3B1_DIR_REF], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L3B1_DIR_REF] }, [ POWER4_PME_PM_MRK_LSU_FLUSH_UST ] = { .pme_name = "PM_MRK_LSU_FLUSH_UST", .pme_code = 0x7910, .pme_short_desc = "Marked unaligned store flushes", .pme_long_desc = "A marked store was flushed because it was unaligned", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU_FLUSH_UST], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU_FLUSH_UST] }, [ POWER4_PME_PM_MRK_DATA_FROM_L25_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L25_SHR", .pme_code = 0x5c76, .pme_short_desc = "Marked data loaded from L2.5 shared", .pme_long_desc = "DL1 was reloaded with shared (T or SL) data from the L2 of a chip on this MCM due to a marked demand load", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_DATA_FROM_L25_SHR], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_DATA_FROM_L25_SHR] }, [ POWER4_PME_PM_LSU_FLUSH_ULD ] = { .pme_name = "PM_LSU_FLUSH_ULD", .pme_code = 0x1c00, .pme_short_desc = "LRQ unaligned load flushes", .pme_long_desc = "A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_FLUSH_ULD], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_FLUSH_ULD] }, [ POWER4_PME_PM_MRK_BRU_FIN ] = { .pme_name = "PM_MRK_BRU_FIN", .pme_code = 0x2005, .pme_short_desc = "Marked instruction BRU processing finished", .pme_long_desc = "The branch unit finished a marked instruction. Instructions that finish may not necessary complete", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_BRU_FIN], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_BRU_FIN] }, [ POWER4_PME_PM_IERAT_XLATE_WR ] = { .pme_name = "PM_IERAT_XLATE_WR", .pme_code = 0x327, .pme_short_desc = "Translation written to ierat", .pme_long_desc = "This signal will be asserted each time the I-ERAT is written. This indicates that an ERAT miss has been serviced. ERAT misses will initiate a sequence resulting in the ERAT being written. ERAT misses that are later ignored will not be counted unless the ERAT is written before the instruction stream is changed, This should be a fairly accurate count of ERAT missed (best available).", .pme_event_ids = power4_event_ids[POWER4_PME_PM_IERAT_XLATE_WR], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_IERAT_XLATE_WR] }, [ POWER4_PME_PM_LSU0_BUSY ] = { .pme_name = "PM_LSU0_BUSY", .pme_code = 0xc33, .pme_short_desc = "LSU0 busy", .pme_long_desc = "LSU unit 0 is busy rejecting instructions", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU0_BUSY], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU0_BUSY] }, [ POWER4_PME_PM_L2SA_ST_REQ ] = { .pme_name = "PM_L2SA_ST_REQ", .pme_code = 0xf10, .pme_short_desc = "L2 slice A store requests", .pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A,B,and C.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SA_ST_REQ], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SA_ST_REQ] }, [ POWER4_PME_PM_DATA_FROM_MEM ] = { .pme_name = "PM_DATA_FROM_MEM", .pme_code = 0x2c66, .pme_short_desc = "Data loaded from memory", .pme_long_desc = "DL1 was reloaded from memory due to a demand load", .pme_event_ids = power4_event_ids[POWER4_PME_PM_DATA_FROM_MEM], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DATA_FROM_MEM] }, [ POWER4_PME_PM_FPR_MAP_FULL_CYC ] = { .pme_name = "PM_FPR_MAP_FULL_CYC", .pme_code = 0x201, .pme_short_desc = "Cycles FPR mapper full", .pme_long_desc = "The ISU sends a signal indicating that the FPR mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPR_MAP_FULL_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPR_MAP_FULL_CYC] }, [ POWER4_PME_PM_FPU1_FULL_CYC ] = { .pme_name = "PM_FPU1_FULL_CYC", .pme_code = 0x207, .pme_short_desc = "Cycles FPU1 issue queue full", .pme_long_desc = "The issue queue for FPU unit 1 cannot accept any more instructions. Issue is stopped", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU1_FULL_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU1_FULL_CYC] }, [ POWER4_PME_PM_FPU0_FIN ] = { .pme_name = "PM_FPU0_FIN", .pme_code = 0x113, .pme_short_desc = "FPU0 produced a result", .pme_long_desc = "fp0 finished, produced a result This only indicates finish, not completion. ", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU0_FIN], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU0_FIN] }, [ POWER4_PME_PM_3INST_CLB_CYC ] = { .pme_name = "PM_3INST_CLB_CYC", .pme_code = 0x452, .pme_short_desc = "Cycles 3 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_3INST_CLB_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_3INST_CLB_CYC] }, [ POWER4_PME_PM_DATA_FROM_L35 ] = { .pme_name = "PM_DATA_FROM_L35", .pme_code = 0x3c66, .pme_short_desc = "Data loaded from L3.5", .pme_long_desc = "DL1 was reloaded from the L3 of another MCM due to a demand load", .pme_event_ids = power4_event_ids[POWER4_PME_PM_DATA_FROM_L35], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DATA_FROM_L35] }, [ POWER4_PME_PM_L2SA_SHR_INV ] = { .pme_name = "PM_L2SA_SHR_INV", .pme_code = 0xf05, .pme_short_desc = "L2 slice A transition from shared to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A,B,and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SA_SHR_INV], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SA_SHR_INV] }, [ POWER4_PME_PM_MRK_LSU_FLUSH_SRQ ] = { .pme_name = "PM_MRK_LSU_FLUSH_SRQ", .pme_code = 0x4910, .pme_short_desc = "Marked SRQ flushes", .pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU_FLUSH_SRQ], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU_FLUSH_SRQ] }, [ POWER4_PME_PM_THRESH_TIMEO ] = { .pme_name = "PM_THRESH_TIMEO", .pme_code = 0x2003, .pme_short_desc = "Threshold timeout", .pme_long_desc = "The threshold timer expired", .pme_event_ids = power4_event_ids[POWER4_PME_PM_THRESH_TIMEO], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_THRESH_TIMEO] }, [ POWER4_PME_PM_FPU_FSQRT ] = { .pme_name = "PM_FPU_FSQRT", .pme_code = 0x6100, .pme_short_desc = "FPU executed FSQRT instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when FPU is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU_FSQRT], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU_FSQRT] }, [ POWER4_PME_PM_MRK_LSU0_FLUSH_LRQ ] = { .pme_name = "PM_MRK_LSU0_FLUSH_LRQ", .pme_code = 0x912, .pme_short_desc = "LSU0 marked LRQ flushes", .pme_long_desc = "A marked load was flushed by unit 0 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU0_FLUSH_LRQ], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU0_FLUSH_LRQ] }, [ POWER4_PME_PM_FXLS0_FULL_CYC ] = { .pme_name = "PM_FXLS0_FULL_CYC", .pme_code = 0x210, .pme_short_desc = "Cycles FXU0/LS0 queue full", .pme_long_desc = "The issue queue for FXU/LSU unit 0 cannot accept any more instructions. Issue is stopped", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FXLS0_FULL_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FXLS0_FULL_CYC] }, [ POWER4_PME_PM_DATA_TABLEWALK_CYC ] = { .pme_name = "PM_DATA_TABLEWALK_CYC", .pme_code = 0x936, .pme_short_desc = "Cycles doing data tablewalks", .pme_long_desc = "This signal is asserted every cycle when a tablewalk is active. While a tablewalk is active any request attempting to access the TLB will be rejected and retried.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_DATA_TABLEWALK_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DATA_TABLEWALK_CYC] }, [ POWER4_PME_PM_FPU0_ALL ] = { .pme_name = "PM_FPU0_ALL", .pme_code = 0x103, .pme_short_desc = "FPU0 executed add", .pme_long_desc = " mult", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU0_ALL], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU0_ALL] }, [ POWER4_PME_PM_FPU0_FEST ] = { .pme_name = "PM_FPU0_FEST", .pme_code = 0x112, .pme_short_desc = "FPU0 executed FEST instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. ", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU0_FEST], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU0_FEST] }, [ POWER4_PME_PM_DATA_FROM_L25_MOD ] = { .pme_name = "PM_DATA_FROM_L25_MOD", .pme_code = 0x8c66, .pme_short_desc = "Data loaded from L2.5 modified", .pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a demand load", .pme_event_ids = power4_event_ids[POWER4_PME_PM_DATA_FROM_L25_MOD], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DATA_FROM_L25_MOD] }, [ POWER4_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_LMQ_SRQ_EMPTY_CYC", .pme_code = 0x2002, .pme_short_desc = "Cycles LMQ and SRQ empty", .pme_long_desc = "Cycles when both the LMQ and SRQ are empty (LSU is idle)", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC] }, [ POWER4_PME_PM_FPU_FEST ] = { .pme_name = "PM_FPU_FEST", .pme_code = 0x3110, .pme_short_desc = "FPU executed FEST instruction", .pme_long_desc = "This signal is active for one cycle when executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. Combined Unit 0 + Unit 1.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU_FEST], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU_FEST] }, [ POWER4_PME_PM_0INST_FETCH ] = { .pme_name = "PM_0INST_FETCH", .pme_code = 0x8327, .pme_short_desc = "No instructions fetched", .pme_long_desc = "No instructions were fetched this cycles (due to IFU hold, redirect, or icache miss)", .pme_event_ids = power4_event_ids[POWER4_PME_PM_0INST_FETCH], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_0INST_FETCH] }, [ POWER4_PME_PM_LARX_LSU1 ] = { .pme_name = "PM_LARX_LSU1", .pme_code = 0xc77, .pme_short_desc = "Larx executed on LSU1", .pme_long_desc = "Invalid event, larx instructions are never executed on unit 1", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LARX_LSU1], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LARX_LSU1] }, [ POWER4_PME_PM_LD_MISS_L1_LSU0 ] = { .pme_name = "PM_LD_MISS_L1_LSU0", .pme_code = 0xc12, .pme_short_desc = "LSU0 L1 D cache load misses", .pme_long_desc = "A load, executing on unit 0, missed the dcache", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LD_MISS_L1_LSU0], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LD_MISS_L1_LSU0] }, [ POWER4_PME_PM_L1_PREF ] = { .pme_name = "PM_L1_PREF", .pme_code = 0xc35, .pme_short_desc = "L1 cache data prefetches", .pme_long_desc = "A request to prefetch data into the L1 was made", .pme_event_ids = power4_event_ids[POWER4_PME_PM_L1_PREF], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L1_PREF] }, [ POWER4_PME_PM_FPU1_STALL3 ] = { .pme_name = "PM_FPU1_STALL3", .pme_code = 0x125, .pme_short_desc = "FPU1 stalled in pipe3", .pme_long_desc = "This signal indicates that fp1 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. ", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU1_STALL3], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU1_STALL3] }, [ POWER4_PME_PM_BRQ_FULL_CYC ] = { .pme_name = "PM_BRQ_FULL_CYC", .pme_code = 0x205, .pme_short_desc = "Cycles branch queue full", .pme_long_desc = "The ISU sends a signal indicating that the issue queue that feeds the ifu br unit cannot accept any more group (queue is full of groups).", .pme_event_ids = power4_event_ids[POWER4_PME_PM_BRQ_FULL_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_BRQ_FULL_CYC] }, [ POWER4_PME_PM_LARX ] = { .pme_name = "PM_LARX", .pme_code = 0x4c70, .pme_short_desc = "Larx executed", .pme_long_desc = "A Larx (lwarx or ldarx) was executed. This is the combined count from LSU0 + LSU1, but these instructions only execute on LSU0", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LARX], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LARX] }, [ POWER4_PME_PM_MRK_DATA_FROM_L35 ] = { .pme_name = "PM_MRK_DATA_FROM_L35", .pme_code = 0x3c76, .pme_short_desc = "Marked data loaded from L3.5", .pme_long_desc = "DL1 was reloaded from the L3 of another MCM due to a marked demand load", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_DATA_FROM_L35], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_DATA_FROM_L35] }, [ POWER4_PME_PM_WORK_HELD ] = { .pme_name = "PM_WORK_HELD", .pme_code = 0x2001, .pme_short_desc = "Work held", .pme_long_desc = "RAS Unit has signaled completion to stop and there are groups waiting to complete", .pme_event_ids = power4_event_ids[POWER4_PME_PM_WORK_HELD], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_WORK_HELD] }, [ POWER4_PME_PM_MRK_LD_MISS_L1_LSU0 ] = { .pme_name = "PM_MRK_LD_MISS_L1_LSU0", .pme_code = 0x920, .pme_short_desc = "LSU0 L1 D cache load misses", .pme_long_desc = "A marked load, executing on unit 0, missed the dcache", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LD_MISS_L1_LSU0], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LD_MISS_L1_LSU0] }, [ POWER4_PME_PM_FXU_IDLE ] = { .pme_name = "PM_FXU_IDLE", .pme_code = 0x5002, .pme_short_desc = "FXU idle", .pme_long_desc = "FXU0 and FXU1 are both idle", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FXU_IDLE], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FXU_IDLE] }, [ POWER4_PME_PM_INST_CMPL ] = { .pme_name = "PM_INST_CMPL", .pme_code = 0x8001, .pme_short_desc = "Instructions completed", .pme_long_desc = "Number of Eligible Instructions that completed. ", .pme_event_ids = power4_event_ids[POWER4_PME_PM_INST_CMPL], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_INST_CMPL] }, [ POWER4_PME_PM_LSU1_FLUSH_UST ] = { .pme_name = "PM_LSU1_FLUSH_UST", .pme_code = 0xc05, .pme_short_desc = "LSU1 unaligned store flushes", .pme_long_desc = "A store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU1_FLUSH_UST], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU1_FLUSH_UST] }, [ POWER4_PME_PM_LSU0_FLUSH_ULD ] = { .pme_name = "PM_LSU0_FLUSH_ULD", .pme_code = 0xc00, .pme_short_desc = "LSU0 unaligned load flushes", .pme_long_desc = "A load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU0_FLUSH_ULD], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU0_FLUSH_ULD] }, [ POWER4_PME_PM_INST_FROM_L2 ] = { .pme_name = "PM_INST_FROM_L2", .pme_code = 0x3327, .pme_short_desc = "Instructions fetched from L2", .pme_long_desc = "An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions", .pme_event_ids = power4_event_ids[POWER4_PME_PM_INST_FROM_L2], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_INST_FROM_L2] }, [ POWER4_PME_PM_DATA_FROM_L3 ] = { .pme_name = "PM_DATA_FROM_L3", .pme_code = 0x1c66, .pme_short_desc = "Data loaded from L3", .pme_long_desc = "DL1 was reloaded from the local L3 due to a demand load", .pme_event_ids = power4_event_ids[POWER4_PME_PM_DATA_FROM_L3], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DATA_FROM_L3] }, [ POWER4_PME_PM_FPU0_DENORM ] = { .pme_name = "PM_FPU0_DENORM", .pme_code = 0x120, .pme_short_desc = "FPU0 received denormalized data", .pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU0_DENORM], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU0_DENORM] }, [ POWER4_PME_PM_FPU1_FMOV_FEST ] = { .pme_name = "PM_FPU1_FMOV_FEST", .pme_code = 0x114, .pme_short_desc = "FPU1 executing FMOV or FEST instructions", .pme_long_desc = "This signal is active for one cycle when fp1 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU1_FMOV_FEST], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU1_FMOV_FEST] }, [ POWER4_PME_PM_GRP_DISP_REJECT ] = { .pme_name = "PM_GRP_DISP_REJECT", .pme_code = 0x8003, .pme_short_desc = "Group dispatch rejected", .pme_long_desc = "A group that previously attempted dispatch was rejected.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_GRP_DISP_REJECT], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_GRP_DISP_REJECT] }, [ POWER4_PME_PM_INST_FETCH_CYC ] = { .pme_name = "PM_INST_FETCH_CYC", .pme_code = 0x323, .pme_short_desc = "Cycles at least 1 instruction fetched", .pme_long_desc = "Asserted each cycle when the IFU sends at least one instruction to the IDU. ", .pme_event_ids = power4_event_ids[POWER4_PME_PM_INST_FETCH_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_INST_FETCH_CYC] }, [ POWER4_PME_PM_LSU_LDF ] = { .pme_name = "PM_LSU_LDF", .pme_code = 0x8930, .pme_short_desc = "LSU executed Floating Point load instruction", .pme_long_desc = "LSU executed Floating Point load instruction", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_LDF], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_LDF] }, [ POWER4_PME_PM_INST_DISP ] = { .pme_name = "PM_INST_DISP", .pme_code = 0x221, .pme_short_desc = "Instructions dispatched", .pme_long_desc = "The ISU sends the number of instructions dispatched.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_INST_DISP], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_INST_DISP] }, [ POWER4_PME_PM_L2SA_MOD_INV ] = { .pme_name = "PM_L2SA_MOD_INV", .pme_code = 0xf07, .pme_short_desc = "L2 slice A transition from modified to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SA_MOD_INV], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SA_MOD_INV] }, [ POWER4_PME_PM_DATA_FROM_L25_SHR ] = { .pme_name = "PM_DATA_FROM_L25_SHR", .pme_code = 0x5c66, .pme_short_desc = "Data loaded from L2.5 shared", .pme_long_desc = "DL1 was reloaded with shared (T or SL) data from the L2 of a chip on this MCM due to a demand load", .pme_event_ids = power4_event_ids[POWER4_PME_PM_DATA_FROM_L25_SHR], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DATA_FROM_L25_SHR] }, [ POWER4_PME_PM_FAB_CMD_RETRIED ] = { .pme_name = "PM_FAB_CMD_RETRIED", .pme_code = 0xf17, .pme_short_desc = "Fabric command retried", .pme_long_desc = "A bus command on the MCM to MCM fabric was retried. This event is the total count of all retried fabric commands for the local MCM (all four chips report the same value). This event is scaled to the fabric frequency and must be adjusted for a true count. i.e. if the fabric is running 2:1, divide the count by 2.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FAB_CMD_RETRIED], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FAB_CMD_RETRIED] }, [ POWER4_PME_PM_L1_DCACHE_RELOAD_VALID ] = { .pme_name = "PM_L1_DCACHE_RELOAD_VALID", .pme_code = 0xc64, .pme_short_desc = "L1 reload data source valid", .pme_long_desc = "The data source information is valid", .pme_event_ids = power4_event_ids[POWER4_PME_PM_L1_DCACHE_RELOAD_VALID], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L1_DCACHE_RELOAD_VALID] }, [ POWER4_PME_PM_MRK_GRP_ISSUED ] = { .pme_name = "PM_MRK_GRP_ISSUED", .pme_code = 0x6005, .pme_short_desc = "Marked group issued", .pme_long_desc = "A sampled instruction was issued", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_GRP_ISSUED], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_GRP_ISSUED] }, [ POWER4_PME_PM_FPU_FULL_CYC ] = { .pme_name = "PM_FPU_FULL_CYC", .pme_code = 0x5200, .pme_short_desc = "Cycles FPU issue queue full", .pme_long_desc = "Cycles when one or both FPU issue queues are full", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU_FULL_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU_FULL_CYC] }, [ POWER4_PME_PM_FPU_FMA ] = { .pme_name = "PM_FPU_FMA", .pme_code = 0x2100, .pme_short_desc = "FPU executed multiply-add instruction", .pme_long_desc = "This signal is active for one cycle when FPU is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU_FMA], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU_FMA] }, [ POWER4_PME_PM_MRK_CRU_FIN ] = { .pme_name = "PM_MRK_CRU_FIN", .pme_code = 0x4005, .pme_short_desc = "Marked instruction CRU processing finished", .pme_long_desc = "The Condition Register Unit finished a marked instruction. Instructions that finish may not necessary complete", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_CRU_FIN], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_CRU_FIN] }, [ POWER4_PME_PM_MRK_LSU1_FLUSH_UST ] = { .pme_name = "PM_MRK_LSU1_FLUSH_UST", .pme_code = 0x915, .pme_short_desc = "LSU1 marked unaligned store flushes", .pme_long_desc = "A marked store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU1_FLUSH_UST], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU1_FLUSH_UST] }, [ POWER4_PME_PM_MRK_FXU_FIN ] = { .pme_name = "PM_MRK_FXU_FIN", .pme_code = 0x6004, .pme_short_desc = "Marked instruction FXU processing finished", .pme_long_desc = "One of the Fixed Point Units finished a marked instruction. Instructions that finish may not necessary complete", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_FXU_FIN], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_FXU_FIN] }, [ POWER4_PME_PM_BR_ISSUED ] = { .pme_name = "PM_BR_ISSUED", .pme_code = 0x330, .pme_short_desc = "Branches issued", .pme_long_desc = "This signal will be asserted each time the ISU issues a branch instruction. This signal will be asserted each time the ISU selects a branch instruction to issue.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_BR_ISSUED], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_BR_ISSUED] }, [ POWER4_PME_PM_EE_OFF ] = { .pme_name = "PM_EE_OFF", .pme_code = 0x233, .pme_short_desc = "Cycles MSR(EE) bit off", .pme_long_desc = "The number of Cycles MSR(EE) bit was off.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_EE_OFF], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_EE_OFF] }, [ POWER4_PME_PM_INST_FROM_L3 ] = { .pme_name = "PM_INST_FROM_L3", .pme_code = 0x5327, .pme_short_desc = "Instruction fetched from L3", .pme_long_desc = "An instruction fetch group was fetched from L3. Fetch Groups can contain up to 8 instructions", .pme_event_ids = power4_event_ids[POWER4_PME_PM_INST_FROM_L3], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_INST_FROM_L3] }, [ POWER4_PME_PM_ITLB_MISS ] = { .pme_name = "PM_ITLB_MISS", .pme_code = 0x900, .pme_short_desc = "Instruction TLB misses", .pme_long_desc = "A TLB miss for an Instruction Fetch has occurred", .pme_event_ids = power4_event_ids[POWER4_PME_PM_ITLB_MISS], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_ITLB_MISS] }, [ POWER4_PME_PM_FXLS_FULL_CYC ] = { .pme_name = "PM_FXLS_FULL_CYC", .pme_code = 0x8210, .pme_short_desc = "Cycles FXLS queue is full", .pme_long_desc = "Cycles when one or both FXU/LSU issue queue are full", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FXLS_FULL_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FXLS_FULL_CYC] }, [ POWER4_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { .pme_name = "PM_FXU1_BUSY_FXU0_IDLE", .pme_code = 0x4002, .pme_short_desc = "FXU1 busy FXU0 idle", .pme_long_desc = "FXU0 was idle while FXU1 was busy", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FXU1_BUSY_FXU0_IDLE], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FXU1_BUSY_FXU0_IDLE] }, [ POWER4_PME_PM_GRP_DISP_VALID ] = { .pme_name = "PM_GRP_DISP_VALID", .pme_code = 0x223, .pme_short_desc = "Group dispatch valid", .pme_long_desc = "Dispatch has been attempted for a valid group. Some groups may be rejected. The total number of successful dispatches is the number of dispatch valid minus dispatch reject.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_GRP_DISP_VALID], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_GRP_DISP_VALID] }, [ POWER4_PME_PM_L2SC_ST_HIT ] = { .pme_name = "PM_L2SC_ST_HIT", .pme_code = 0xf15, .pme_short_desc = "L2 slice C store hits", .pme_long_desc = "A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A,B, and C.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SC_ST_HIT], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SC_ST_HIT] }, [ POWER4_PME_PM_MRK_GRP_DISP ] = { .pme_name = "PM_MRK_GRP_DISP", .pme_code = 0x1002, .pme_short_desc = "Marked group dispatched", .pme_long_desc = "A group containing a sampled instruction was dispatched", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_GRP_DISP], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_GRP_DISP] }, [ POWER4_PME_PM_L2SB_MOD_TAG ] = { .pme_name = "PM_L2SB_MOD_TAG", .pme_code = 0xf22, .pme_short_desc = "L2 slice B transition from modified to tagged", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SB_MOD_TAG], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SB_MOD_TAG] }, [ POWER4_PME_PM_INST_FROM_L25_L275 ] = { .pme_name = "PM_INST_FROM_L25_L275", .pme_code = 0x2327, .pme_short_desc = "Instruction fetched from L2.5/L2.75", .pme_long_desc = "An instruction fetch group was fetched from the L2 of another chip. Fetch Groups can contain up to 8 instructions", .pme_event_ids = power4_event_ids[POWER4_PME_PM_INST_FROM_L25_L275], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_INST_FROM_L25_L275] }, [ POWER4_PME_PM_LSU_FLUSH_UST ] = { .pme_name = "PM_LSU_FLUSH_UST", .pme_code = 0x2c00, .pme_short_desc = "SRQ unaligned store flushes", .pme_long_desc = "A store was flushed because it was unaligned", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_FLUSH_UST], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_FLUSH_UST] }, [ POWER4_PME_PM_L2SB_ST_HIT ] = { .pme_name = "PM_L2SB_ST_HIT", .pme_code = 0xf13, .pme_short_desc = "L2 slice B store hits", .pme_long_desc = "A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A,B, and C.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SB_ST_HIT], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SB_ST_HIT] }, [ POWER4_PME_PM_FXU1_FIN ] = { .pme_name = "PM_FXU1_FIN", .pme_code = 0x236, .pme_short_desc = "FXU1 produced a result", .pme_long_desc = "The Fixed Point unit 1 finished an instruction and produced a result", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FXU1_FIN], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FXU1_FIN] }, [ POWER4_PME_PM_L3B1_DIR_MIS ] = { .pme_name = "PM_L3B1_DIR_MIS", .pme_code = 0xf03, .pme_short_desc = "L3 bank 1 directory misses", .pme_long_desc = "A reference was made to the local L3 directory by a local CPU and it missed in the L3. Only requests from on-MCM CPUs are counted. This event is scaled to the L3 speed and the count must be scaled. i.e. if the L3 is running 3:1, divide the count by 3", .pme_event_ids = power4_event_ids[POWER4_PME_PM_L3B1_DIR_MIS], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L3B1_DIR_MIS] }, [ POWER4_PME_PM_4INST_CLB_CYC ] = { .pme_name = "PM_4INST_CLB_CYC", .pme_code = 0x453, .pme_short_desc = "Cycles 4 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_4INST_CLB_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_4INST_CLB_CYC] }, [ POWER4_PME_PM_GRP_CMPL ] = { .pme_name = "PM_GRP_CMPL", .pme_code = 0x7003, .pme_short_desc = "Group completed", .pme_long_desc = "A group completed. Microcoded instructions that span multiple groups will generate this event once per group.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_GRP_CMPL], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_GRP_CMPL] }, [ POWER4_PME_PM_DC_PREF_L2_CLONE_L3 ] = { .pme_name = "PM_DC_PREF_L2_CLONE_L3", .pme_code = 0xc27, .pme_short_desc = "L2 prefetch cloned with L3", .pme_long_desc = "A prefetch request was made to the L2 with a cloned request sent to the L3", .pme_event_ids = power4_event_ids[POWER4_PME_PM_DC_PREF_L2_CLONE_L3], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DC_PREF_L2_CLONE_L3] }, [ POWER4_PME_PM_FPU_FRSP_FCONV ] = { .pme_name = "PM_FPU_FRSP_FCONV", .pme_code = 0x7110, .pme_short_desc = "FPU executed FRSP or FCONV instructions", .pme_long_desc = "This signal is active for one cycle when executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU_FRSP_FCONV], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU_FRSP_FCONV] }, [ POWER4_PME_PM_5INST_CLB_CYC ] = { .pme_name = "PM_5INST_CLB_CYC", .pme_code = 0x454, .pme_short_desc = "Cycles 5 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_5INST_CLB_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_5INST_CLB_CYC] }, [ POWER4_PME_PM_MRK_LSU0_FLUSH_SRQ ] = { .pme_name = "PM_MRK_LSU0_FLUSH_SRQ", .pme_code = 0x913, .pme_short_desc = "LSU0 marked SRQ flushes", .pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU0_FLUSH_SRQ], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU0_FLUSH_SRQ] }, [ POWER4_PME_PM_MRK_LSU_FLUSH_ULD ] = { .pme_name = "PM_MRK_LSU_FLUSH_ULD", .pme_code = 0x8910, .pme_short_desc = "Marked unaligned load flushes", .pme_long_desc = "A marked load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU_FLUSH_ULD], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU_FLUSH_ULD] }, [ POWER4_PME_PM_8INST_CLB_CYC ] = { .pme_name = "PM_8INST_CLB_CYC", .pme_code = 0x457, .pme_short_desc = "Cycles 8 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_8INST_CLB_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_8INST_CLB_CYC] }, [ POWER4_PME_PM_LSU_LMQ_FULL_CYC ] = { .pme_name = "PM_LSU_LMQ_FULL_CYC", .pme_code = 0x927, .pme_short_desc = "Cycles LMQ full", .pme_long_desc = "The LMQ was full", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_LMQ_FULL_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_LMQ_FULL_CYC] }, [ POWER4_PME_PM_ST_REF_L1_LSU0 ] = { .pme_name = "PM_ST_REF_L1_LSU0", .pme_code = 0xc11, .pme_short_desc = "LSU0 L1 D cache store references", .pme_long_desc = "A store executed on unit 0", .pme_event_ids = power4_event_ids[POWER4_PME_PM_ST_REF_L1_LSU0], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_ST_REF_L1_LSU0] }, [ POWER4_PME_PM_LSU0_DERAT_MISS ] = { .pme_name = "PM_LSU0_DERAT_MISS", .pme_code = 0x902, .pme_short_desc = "LSU0 DERAT misses", .pme_long_desc = "A data request (load or store) from LSU Unit 0 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU0_DERAT_MISS], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU0_DERAT_MISS] }, [ POWER4_PME_PM_LSU_SRQ_SYNC_CYC ] = { .pme_name = "PM_LSU_SRQ_SYNC_CYC", .pme_code = 0x932, .pme_short_desc = "SRQ sync duration", .pme_long_desc = "This signal is asserted every cycle when a sync is in the SRQ.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_SRQ_SYNC_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_SRQ_SYNC_CYC] }, [ POWER4_PME_PM_FPU_STALL3 ] = { .pme_name = "PM_FPU_STALL3", .pme_code = 0x2120, .pme_short_desc = "FPU stalled in pipe3", .pme_long_desc = "FPU has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. Combined Unit 0 + Unit 1", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU_STALL3], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU_STALL3] }, [ POWER4_PME_PM_MRK_DATA_FROM_L2 ] = { .pme_name = "PM_MRK_DATA_FROM_L2", .pme_code = 0x4c76, .pme_short_desc = "Marked data loaded from L2", .pme_long_desc = "DL1 was reloaded from the local L2 due to a marked demand load", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_DATA_FROM_L2], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_DATA_FROM_L2] }, [ POWER4_PME_PM_FPU0_FMOV_FEST ] = { .pme_name = "PM_FPU0_FMOV_FEST", .pme_code = 0x110, .pme_short_desc = "FPU0 executed FMOV or FEST instructions", .pme_long_desc = "This signal is active for one cycle when fp0 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU0_FMOV_FEST], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU0_FMOV_FEST] }, [ POWER4_PME_PM_LSU0_FLUSH_SRQ ] = { .pme_name = "PM_LSU0_FLUSH_SRQ", .pme_code = 0xc03, .pme_short_desc = "LSU0 SRQ flushes", .pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU0_FLUSH_SRQ], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU0_FLUSH_SRQ] }, [ POWER4_PME_PM_LD_REF_L1_LSU0 ] = { .pme_name = "PM_LD_REF_L1_LSU0", .pme_code = 0xc10, .pme_short_desc = "LSU0 L1 D cache load references", .pme_long_desc = "A load executed on unit 0", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LD_REF_L1_LSU0], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LD_REF_L1_LSU0] }, [ POWER4_PME_PM_L2SC_SHR_INV ] = { .pme_name = "PM_L2SC_SHR_INV", .pme_code = 0xf25, .pme_short_desc = "L2 slice C transition from shared to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A,B,and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SC_SHR_INV], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SC_SHR_INV] }, [ POWER4_PME_PM_LSU1_FLUSH_SRQ ] = { .pme_name = "PM_LSU1_FLUSH_SRQ", .pme_code = 0xc07, .pme_short_desc = "LSU1 SRQ flushes", .pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group. ", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU1_FLUSH_SRQ], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU1_FLUSH_SRQ] }, [ POWER4_PME_PM_LSU_LMQ_S0_ALLOC ] = { .pme_name = "PM_LSU_LMQ_S0_ALLOC", .pme_code = 0x935, .pme_short_desc = "LMQ slot 0 allocated", .pme_long_desc = "The first entry in the LMQ was allocated.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_LMQ_S0_ALLOC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_LMQ_S0_ALLOC] }, [ POWER4_PME_PM_ST_REF_L1 ] = { .pme_name = "PM_ST_REF_L1", .pme_code = 0x7c10, .pme_short_desc = "L1 D cache store references", .pme_long_desc = "Total DL1 Store references", .pme_event_ids = power4_event_ids[POWER4_PME_PM_ST_REF_L1], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_ST_REF_L1] }, [ POWER4_PME_PM_LSU_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_SRQ_EMPTY_CYC", .pme_code = 0x4003, .pme_short_desc = "Cycles SRQ empty", .pme_long_desc = "The Store Request Queue is empty", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_SRQ_EMPTY_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_SRQ_EMPTY_CYC] }, [ POWER4_PME_PM_FPU1_STF ] = { .pme_name = "PM_FPU1_STF", .pme_code = 0x126, .pme_short_desc = "FPU1 executed store instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing a store instruction.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU1_STF], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU1_STF] }, [ POWER4_PME_PM_L3B0_DIR_REF ] = { .pme_name = "PM_L3B0_DIR_REF", .pme_code = 0xf00, .pme_short_desc = "L3 bank 0 directory references", .pme_long_desc = "A reference was made to the local L3 directory by a local CPU. Only requests from on-MCM CPUs are counted. This event is scaled to the L3 speed and the count must be scaled. i.e. if the L3 is running 3:1, divide the count by 3", .pme_event_ids = power4_event_ids[POWER4_PME_PM_L3B0_DIR_REF], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L3B0_DIR_REF] }, [ POWER4_PME_PM_RUN_CYC ] = { .pme_name = "PM_RUN_CYC", .pme_code = 0x1005, .pme_short_desc = "Run cycles", .pme_long_desc = "Processor Cycles gated by the run latch", .pme_event_ids = power4_event_ids[POWER4_PME_PM_RUN_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_RUN_CYC] }, [ POWER4_PME_PM_LSU_LMQ_S0_VALID ] = { .pme_name = "PM_LSU_LMQ_S0_VALID", .pme_code = 0x931, .pme_short_desc = "LMQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle when the first entry in the LMQ is valid. The LMQ had eight entries that are allocated FIFO", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_LMQ_S0_VALID], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_LMQ_S0_VALID] }, [ POWER4_PME_PM_LSU_LRQ_S0_VALID ] = { .pme_name = "PM_LSU_LRQ_S0_VALID", .pme_code = 0xc22, .pme_short_desc = "LRQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_LRQ_S0_VALID], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_LRQ_S0_VALID] }, [ POWER4_PME_PM_LSU0_LDF ] = { .pme_name = "PM_LSU0_LDF", .pme_code = 0x930, .pme_short_desc = "LSU0 executed Floating Point load instruction", .pme_long_desc = "A floating point load was executed from LSU unit 0", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU0_LDF], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU0_LDF] }, [ POWER4_PME_PM_MRK_IMR_RELOAD ] = { .pme_name = "PM_MRK_IMR_RELOAD", .pme_code = 0x922, .pme_short_desc = "Marked IMR reloaded", .pme_long_desc = "A DL1 reload occured due to marked load", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_IMR_RELOAD], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_IMR_RELOAD] }, [ POWER4_PME_PM_7INST_CLB_CYC ] = { .pme_name = "PM_7INST_CLB_CYC", .pme_code = 0x456, .pme_short_desc = "Cycles 7 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_7INST_CLB_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_7INST_CLB_CYC] }, [ POWER4_PME_PM_MRK_GRP_TIMEO ] = { .pme_name = "PM_MRK_GRP_TIMEO", .pme_code = 0x5005, .pme_short_desc = "Marked group completion timeout", .pme_long_desc = "The sampling timeout expired indicating that the previously sampled instruction is no longer in the processor", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_GRP_TIMEO], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_GRP_TIMEO] }, [ POWER4_PME_PM_FPU_FMOV_FEST ] = { .pme_name = "PM_FPU_FMOV_FEST", .pme_code = 0x8110, .pme_short_desc = "FPU executing FMOV or FEST instructions", .pme_long_desc = "This signal is active for one cycle when executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ . Combined Unit 0 + Unit 1", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU_FMOV_FEST], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU_FMOV_FEST] }, [ POWER4_PME_PM_GRP_DISP_BLK_SB_CYC ] = { .pme_name = "PM_GRP_DISP_BLK_SB_CYC", .pme_code = 0x231, .pme_short_desc = "Cycles group dispatch blocked by scoreboard", .pme_long_desc = "The ISU sends a signal indicating that dispatch is blocked by scoreboard.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_GRP_DISP_BLK_SB_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_GRP_DISP_BLK_SB_CYC] }, [ POWER4_PME_PM_XER_MAP_FULL_CYC ] = { .pme_name = "PM_XER_MAP_FULL_CYC", .pme_code = 0x202, .pme_short_desc = "Cycles XER mapper full", .pme_long_desc = "The ISU sends a signal indicating that the xer mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_XER_MAP_FULL_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_XER_MAP_FULL_CYC] }, [ POWER4_PME_PM_ST_MISS_L1 ] = { .pme_name = "PM_ST_MISS_L1", .pme_code = 0xc23, .pme_short_desc = "L1 D cache store misses", .pme_long_desc = "A store missed the dcache", .pme_event_ids = power4_event_ids[POWER4_PME_PM_ST_MISS_L1], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_ST_MISS_L1] }, [ POWER4_PME_PM_STOP_COMPLETION ] = { .pme_name = "PM_STOP_COMPLETION", .pme_code = 0x3001, .pme_short_desc = "Completion stopped", .pme_long_desc = "RAS Unit has signaled completion to stop", .pme_event_ids = power4_event_ids[POWER4_PME_PM_STOP_COMPLETION], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_STOP_COMPLETION] }, [ POWER4_PME_PM_MRK_GRP_CMPL ] = { .pme_name = "PM_MRK_GRP_CMPL", .pme_code = 0x4004, .pme_short_desc = "Marked group completed", .pme_long_desc = "A group containing a sampled instruction completed. Microcoded instructions that span multiple groups will generate this event once per group.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_GRP_CMPL], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_GRP_CMPL] }, [ POWER4_PME_PM_ISLB_MISS ] = { .pme_name = "PM_ISLB_MISS", .pme_code = 0x901, .pme_short_desc = "Instruction SLB misses", .pme_long_desc = "A SLB miss for an instruction fetch as occurred", .pme_event_ids = power4_event_ids[POWER4_PME_PM_ISLB_MISS], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_ISLB_MISS] }, [ POWER4_PME_PM_CYC ] = { .pme_name = "PM_CYC", .pme_code = 0x7, .pme_short_desc = "Processor cycles", .pme_long_desc = "Processor cycles", .pme_event_ids = power4_event_ids[POWER4_PME_PM_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_CYC] }, [ POWER4_PME_PM_LD_MISS_L1_LSU1 ] = { .pme_name = "PM_LD_MISS_L1_LSU1", .pme_code = 0xc16, .pme_short_desc = "LSU1 L1 D cache load misses", .pme_long_desc = "A load, executing on unit 1, missed the dcache", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LD_MISS_L1_LSU1], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LD_MISS_L1_LSU1] }, [ POWER4_PME_PM_STCX_FAIL ] = { .pme_name = "PM_STCX_FAIL", .pme_code = 0x921, .pme_short_desc = "STCX failed", .pme_long_desc = "A stcx (stwcx or stdcx) failed", .pme_event_ids = power4_event_ids[POWER4_PME_PM_STCX_FAIL], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_STCX_FAIL] }, [ POWER4_PME_PM_LSU1_SRQ_STFWD ] = { .pme_name = "PM_LSU1_SRQ_STFWD", .pme_code = 0xc24, .pme_short_desc = "LSU1 SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load on unit 1", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU1_SRQ_STFWD], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU1_SRQ_STFWD] }, [ POWER4_PME_PM_GRP_DISP ] = { .pme_name = "PM_GRP_DISP", .pme_code = 0x2004, .pme_short_desc = "Group dispatches", .pme_long_desc = "A group was dispatched", .pme_event_ids = power4_event_ids[POWER4_PME_PM_GRP_DISP], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_GRP_DISP] }, [ POWER4_PME_PM_DATA_FROM_L2 ] = { .pme_name = "PM_DATA_FROM_L2", .pme_code = 0x4c66, .pme_short_desc = "Data loaded from L2", .pme_long_desc = "DL1 was reloaded from the local L2 due to a demand load", .pme_event_ids = power4_event_ids[POWER4_PME_PM_DATA_FROM_L2], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DATA_FROM_L2] }, [ POWER4_PME_PM_L2_PREF ] = { .pme_name = "PM_L2_PREF", .pme_code = 0xc34, .pme_short_desc = "L2 cache prefetches", .pme_long_desc = "A request to prefetch data into L2 was made", .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2_PREF], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2_PREF] }, [ POWER4_PME_PM_FPU0_FPSCR ] = { .pme_name = "PM_FPU0_FPSCR", .pme_code = 0x130, .pme_short_desc = "FPU0 executed FPSCR instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing fpscr move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*. mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU0_FPSCR], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU0_FPSCR] }, [ POWER4_PME_PM_FPU1_DENORM ] = { .pme_name = "PM_FPU1_DENORM", .pme_code = 0x124, .pme_short_desc = "FPU1 received denormalized data", .pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU1_DENORM], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU1_DENORM] }, [ POWER4_PME_PM_MRK_DATA_FROM_L25_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L25_MOD", .pme_code = 0x8c76, .pme_short_desc = "Marked data loaded from L2.5 modified", .pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a marked demand load", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_DATA_FROM_L25_MOD], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_DATA_FROM_L25_MOD] }, [ POWER4_PME_PM_L2SB_ST_REQ ] = { .pme_name = "PM_L2SB_ST_REQ", .pme_code = 0xf12, .pme_short_desc = "L2 slice B store requests", .pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A,B,and C.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SB_ST_REQ], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SB_ST_REQ] }, [ POWER4_PME_PM_L2SB_MOD_INV ] = { .pme_name = "PM_L2SB_MOD_INV", .pme_code = 0xf23, .pme_short_desc = "L2 slice B transition from modified to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SB_MOD_INV], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SB_MOD_INV] }, [ POWER4_PME_PM_FPU0_FSQRT ] = { .pme_name = "PM_FPU0_FSQRT", .pme_code = 0x102, .pme_short_desc = "FPU0 executed FSQRT instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp0 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU0_FSQRT], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU0_FSQRT] }, [ POWER4_PME_PM_LD_REF_L1 ] = { .pme_name = "PM_LD_REF_L1", .pme_code = 0x8c10, .pme_short_desc = "L1 D cache load references", .pme_long_desc = "Total DL1 Load references", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LD_REF_L1], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LD_REF_L1] }, [ POWER4_PME_PM_MRK_L1_RELOAD_VALID ] = { .pme_name = "PM_MRK_L1_RELOAD_VALID", .pme_code = 0xc74, .pme_short_desc = "Marked L1 reload data source valid", .pme_long_desc = "The source information is valid and is for a marked load", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_L1_RELOAD_VALID], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_L1_RELOAD_VALID] }, [ POWER4_PME_PM_L2SB_SHR_MOD ] = { .pme_name = "PM_L2SB_SHR_MOD", .pme_code = 0xf20, .pme_short_desc = "L2 slice B transition from shared to modified", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A,B,and C. ", .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SB_SHR_MOD], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SB_SHR_MOD] }, [ POWER4_PME_PM_INST_FROM_L1 ] = { .pme_name = "PM_INST_FROM_L1", .pme_code = 0x6327, .pme_short_desc = "Instruction fetched from L1", .pme_long_desc = "An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions", .pme_event_ids = power4_event_ids[POWER4_PME_PM_INST_FROM_L1], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_INST_FROM_L1] }, [ POWER4_PME_PM_1PLUS_PPC_CMPL ] = { .pme_name = "PM_1PLUS_PPC_CMPL", .pme_code = 0x5003, .pme_short_desc = "One or more PPC instruction completed", .pme_long_desc = "A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_1PLUS_PPC_CMPL], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_1PLUS_PPC_CMPL] }, [ POWER4_PME_PM_EE_OFF_EXT_INT ] = { .pme_name = "PM_EE_OFF_EXT_INT", .pme_code = 0x237, .pme_short_desc = "Cycles MSR(EE) bit off and external interrupt pending", .pme_long_desc = "Cycles MSR(EE) bit off and external interrupt pending", .pme_event_ids = power4_event_ids[POWER4_PME_PM_EE_OFF_EXT_INT], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_EE_OFF_EXT_INT] }, [ POWER4_PME_PM_L2SC_SHR_MOD ] = { .pme_name = "PM_L2SC_SHR_MOD", .pme_code = 0xf24, .pme_short_desc = "L2 slice C transition from shared to modified", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A,B,and C. ", .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SC_SHR_MOD], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SC_SHR_MOD] }, [ POWER4_PME_PM_LSU_LRQ_FULL_CYC ] = { .pme_name = "PM_LSU_LRQ_FULL_CYC", .pme_code = 0x212, .pme_short_desc = "Cycles LRQ full", .pme_long_desc = "The isu sends this signal when the lrq is full.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_LRQ_FULL_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_LRQ_FULL_CYC] }, [ POWER4_PME_PM_IC_PREF_INSTALL ] = { .pme_name = "PM_IC_PREF_INSTALL", .pme_code = 0x325, .pme_short_desc = "Instruction prefetched installed in prefetch buffer", .pme_long_desc = "This signal is asserted when a prefetch buffer entry (line) is allocated but the request is not a demand fetch.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_IC_PREF_INSTALL], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_IC_PREF_INSTALL] }, [ POWER4_PME_PM_MRK_LSU1_FLUSH_SRQ ] = { .pme_name = "PM_MRK_LSU1_FLUSH_SRQ", .pme_code = 0x917, .pme_short_desc = "LSU1 marked SRQ flushes", .pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU1_FLUSH_SRQ], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU1_FLUSH_SRQ] }, [ POWER4_PME_PM_GCT_FULL_CYC ] = { .pme_name = "PM_GCT_FULL_CYC", .pme_code = 0x200, .pme_short_desc = "Cycles GCT full", .pme_long_desc = "The ISU sends a signal indicating the gct is full. ", .pme_event_ids = power4_event_ids[POWER4_PME_PM_GCT_FULL_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_GCT_FULL_CYC] }, [ POWER4_PME_PM_INST_FROM_MEM ] = { .pme_name = "PM_INST_FROM_MEM", .pme_code = 0x1327, .pme_short_desc = "Instruction fetched from memory", .pme_long_desc = "An instruction fetch group was fetched from memory. Fetch Groups can contain up to 8 instructions", .pme_event_ids = power4_event_ids[POWER4_PME_PM_INST_FROM_MEM], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_INST_FROM_MEM] }, [ POWER4_PME_PM_FXU_BUSY ] = { .pme_name = "PM_FXU_BUSY", .pme_code = 0x6002, .pme_short_desc = "FXU busy", .pme_long_desc = "FXU0 and FXU1 are both busy", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FXU_BUSY], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FXU_BUSY] }, [ POWER4_PME_PM_ST_REF_L1_LSU1 ] = { .pme_name = "PM_ST_REF_L1_LSU1", .pme_code = 0xc15, .pme_short_desc = "LSU1 L1 D cache store references", .pme_long_desc = "A store executed on unit 1", .pme_event_ids = power4_event_ids[POWER4_PME_PM_ST_REF_L1_LSU1], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_ST_REF_L1_LSU1] }, [ POWER4_PME_PM_MRK_LD_MISS_L1 ] = { .pme_name = "PM_MRK_LD_MISS_L1", .pme_code = 0x1920, .pme_short_desc = "Marked L1 D cache load misses", .pme_long_desc = "Marked L1 D cache load misses", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LD_MISS_L1], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LD_MISS_L1] }, [ POWER4_PME_PM_MRK_LSU1_INST_FIN ] = { .pme_name = "PM_MRK_LSU1_INST_FIN", .pme_code = 0xc32, .pme_short_desc = "LSU1 finished a marked instruction", .pme_long_desc = "LSU unit 1 finished a marked instruction", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU1_INST_FIN], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU1_INST_FIN] }, [ POWER4_PME_PM_L1_WRITE_CYC ] = { .pme_name = "PM_L1_WRITE_CYC", .pme_code = 0x333, .pme_short_desc = "Cycles writing to instruction L1", .pme_long_desc = "This signal is asserted each cycle a cache write is active.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_L1_WRITE_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L1_WRITE_CYC] }, [ POWER4_PME_PM_BIQ_IDU_FULL_CYC ] = { .pme_name = "PM_BIQ_IDU_FULL_CYC", .pme_code = 0x324, .pme_short_desc = "Cycles BIQ or IDU full", .pme_long_desc = "This signal will be asserted each time either the IDU is full or the BIQ is full.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_BIQ_IDU_FULL_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_BIQ_IDU_FULL_CYC] }, [ POWER4_PME_PM_MRK_LSU0_INST_FIN ] = { .pme_name = "PM_MRK_LSU0_INST_FIN", .pme_code = 0xc31, .pme_short_desc = "LSU0 finished a marked instruction", .pme_long_desc = "LSU unit 0 finished a marked instruction", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU0_INST_FIN], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU0_INST_FIN] }, [ POWER4_PME_PM_L2SC_ST_REQ ] = { .pme_name = "PM_L2SC_ST_REQ", .pme_code = 0xf14, .pme_short_desc = "L2 slice C store requests", .pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A,B,and C.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SC_ST_REQ], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SC_ST_REQ] }, [ POWER4_PME_PM_LSU1_BUSY ] = { .pme_name = "PM_LSU1_BUSY", .pme_code = 0xc37, .pme_short_desc = "LSU1 busy", .pme_long_desc = "LSU unit 1 is busy rejecting instructions ", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU1_BUSY], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU1_BUSY] }, [ POWER4_PME_PM_FPU_ALL ] = { .pme_name = "PM_FPU_ALL", .pme_code = 0x5100, .pme_short_desc = "FPU executed add", .pme_long_desc = " mult", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU_ALL], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU_ALL] }, [ POWER4_PME_PM_LSU_SRQ_S0_ALLOC ] = { .pme_name = "PM_LSU_SRQ_S0_ALLOC", .pme_code = 0xc25, .pme_short_desc = "SRQ slot 0 allocated", .pme_long_desc = "SRQ Slot zero was allocated", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_SRQ_S0_ALLOC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_SRQ_S0_ALLOC] }, [ POWER4_PME_PM_GRP_MRK ] = { .pme_name = "PM_GRP_MRK", .pme_code = 0x5004, .pme_short_desc = "Group marked in IDU", .pme_long_desc = "A group was sampled (marked)", .pme_event_ids = power4_event_ids[POWER4_PME_PM_GRP_MRK], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_GRP_MRK] }, [ POWER4_PME_PM_FPU1_FIN ] = { .pme_name = "PM_FPU1_FIN", .pme_code = 0x117, .pme_short_desc = "FPU1 produced a result", .pme_long_desc = "fp1 finished, produced a result. This only indicates finish, not completion. ", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU1_FIN], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU1_FIN] }, [ POWER4_PME_PM_DC_PREF_STREAM_ALLOC ] = { .pme_name = "PM_DC_PREF_STREAM_ALLOC", .pme_code = 0x907, .pme_short_desc = "D cache new prefetch stream allocated", .pme_long_desc = "A new Prefetch Stream was allocated", .pme_event_ids = power4_event_ids[POWER4_PME_PM_DC_PREF_STREAM_ALLOC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DC_PREF_STREAM_ALLOC] }, [ POWER4_PME_PM_BR_MPRED_CR ] = { .pme_name = "PM_BR_MPRED_CR", .pme_code = 0x331, .pme_short_desc = "Branch mispredictions due CR bit setting", .pme_long_desc = "This signal is asserted when the branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This signal is asserted after a branch issue event and will result in a branch redirect flush if not overridden by a flush of an older instruction.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_BR_MPRED_CR], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_BR_MPRED_CR] }, [ POWER4_PME_PM_BR_MPRED_TA ] = { .pme_name = "PM_BR_MPRED_TA", .pme_code = 0x332, .pme_short_desc = "Branch mispredictions due to target address", .pme_long_desc = "branch miss predict due to a target address prediction. This signal will be asserted each time the branch execution unit detects an incorrect target address prediction. This signal will be asserted after a valid branch execution unit issue and will cause a branch mispredict flush unless a flush is detected from an older instruction.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_BR_MPRED_TA], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_BR_MPRED_TA] }, [ POWER4_PME_PM_CRQ_FULL_CYC ] = { .pme_name = "PM_CRQ_FULL_CYC", .pme_code = 0x211, .pme_short_desc = "Cycles CR issue queue full", .pme_long_desc = "The ISU sends a signal indicating that the issue queue that feeds the ifu cr unit cannot accept any more group (queue is full of groups).", .pme_event_ids = power4_event_ids[POWER4_PME_PM_CRQ_FULL_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_CRQ_FULL_CYC] }, [ POWER4_PME_PM_INST_FROM_PREF ] = { .pme_name = "PM_INST_FROM_PREF", .pme_code = 0x7327, .pme_short_desc = "Instructions fetched from prefetch", .pme_long_desc = "An instruction fetch group was fetched from the prefetch buffer. Fetch Groups can contain up to 8 instructions", .pme_event_ids = power4_event_ids[POWER4_PME_PM_INST_FROM_PREF], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_INST_FROM_PREF] }, [ POWER4_PME_PM_LD_MISS_L1 ] = { .pme_name = "PM_LD_MISS_L1", .pme_code = 0x3c10, .pme_short_desc = "L1 D cache load misses", .pme_long_desc = "Total DL1 Load references that miss the DL1", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LD_MISS_L1], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LD_MISS_L1] }, [ POWER4_PME_PM_STCX_PASS ] = { .pme_name = "PM_STCX_PASS", .pme_code = 0xc75, .pme_short_desc = "Stcx passes", .pme_long_desc = "A stcx (stwcx or stdcx) instruction was successful", .pme_event_ids = power4_event_ids[POWER4_PME_PM_STCX_PASS], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_STCX_PASS] }, [ POWER4_PME_PM_DC_INV_L2 ] = { .pme_name = "PM_DC_INV_L2", .pme_code = 0xc17, .pme_short_desc = "L1 D cache entries invalidated from L2", .pme_long_desc = "A dcache invalidated was received from the L2 because a line in L2 was castout.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_DC_INV_L2], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DC_INV_L2] }, [ POWER4_PME_PM_LSU_SRQ_FULL_CYC ] = { .pme_name = "PM_LSU_SRQ_FULL_CYC", .pme_code = 0x213, .pme_short_desc = "Cycles SRQ full", .pme_long_desc = "The isu sends this signal when the srq is full.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_SRQ_FULL_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_SRQ_FULL_CYC] }, [ POWER4_PME_PM_LSU0_FLUSH_LRQ ] = { .pme_name = "PM_LSU0_FLUSH_LRQ", .pme_code = 0xc02, .pme_short_desc = "LSU0 LRQ flushes", .pme_long_desc = "A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU0_FLUSH_LRQ], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU0_FLUSH_LRQ] }, [ POWER4_PME_PM_LSU_SRQ_S0_VALID ] = { .pme_name = "PM_LSU_SRQ_S0_VALID", .pme_code = 0xc21, .pme_short_desc = "SRQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_SRQ_S0_VALID], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_SRQ_S0_VALID] }, [ POWER4_PME_PM_LARX_LSU0 ] = { .pme_name = "PM_LARX_LSU0", .pme_code = 0xc73, .pme_short_desc = "Larx executed on LSU0", .pme_long_desc = "A larx (lwarx or ldarx) was executed on side 0 (there is no coresponding unit 1 event since larx instructions can only execute on unit 0)", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LARX_LSU0], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LARX_LSU0] }, [ POWER4_PME_PM_GCT_EMPTY_CYC ] = { .pme_name = "PM_GCT_EMPTY_CYC", .pme_code = 0x1004, .pme_short_desc = "Cycles GCT empty", .pme_long_desc = "The Global Completion Table is completely empty", .pme_event_ids = power4_event_ids[POWER4_PME_PM_GCT_EMPTY_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_GCT_EMPTY_CYC] }, [ POWER4_PME_PM_FPU1_ALL ] = { .pme_name = "PM_FPU1_ALL", .pme_code = 0x107, .pme_short_desc = "FPU1 executed add", .pme_long_desc = " mult", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU1_ALL], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU1_ALL] }, [ POWER4_PME_PM_FPU1_FSQRT ] = { .pme_name = "PM_FPU1_FSQRT", .pme_code = 0x106, .pme_short_desc = "FPU1 executed FSQRT instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp1 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU1_FSQRT], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU1_FSQRT] }, [ POWER4_PME_PM_FPU_FIN ] = { .pme_name = "PM_FPU_FIN", .pme_code = 0x4110, .pme_short_desc = "FPU produced a result", .pme_long_desc = "FPU finished, produced a result This only indicates finish, not completion. Combined Unit 0 + Unit 1", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU_FIN], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU_FIN] }, [ POWER4_PME_PM_L2SA_SHR_MOD ] = { .pme_name = "PM_L2SA_SHR_MOD", .pme_code = 0xf04, .pme_short_desc = "L2 slice A transition from shared to modified", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A,B,and C. ", .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SA_SHR_MOD], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SA_SHR_MOD] }, [ POWER4_PME_PM_MRK_LD_MISS_L1_LSU1 ] = { .pme_name = "PM_MRK_LD_MISS_L1_LSU1", .pme_code = 0x924, .pme_short_desc = "LSU1 L1 D cache load misses", .pme_long_desc = "A marked load, executing on unit 1, missed the dcache", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LD_MISS_L1_LSU1], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LD_MISS_L1_LSU1] }, [ POWER4_PME_PM_LSU_SRQ_STFWD ] = { .pme_name = "PM_LSU_SRQ_STFWD", .pme_code = 0x1c20, .pme_short_desc = "SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_SRQ_STFWD], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_SRQ_STFWD] }, [ POWER4_PME_PM_FXU0_FIN ] = { .pme_name = "PM_FXU0_FIN", .pme_code = 0x232, .pme_short_desc = "FXU0 produced a result", .pme_long_desc = "The Fixed Point unit 0 finished an instruction and produced a result", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FXU0_FIN], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FXU0_FIN] }, [ POWER4_PME_PM_MRK_FPU_FIN ] = { .pme_name = "PM_MRK_FPU_FIN", .pme_code = 0x7004, .pme_short_desc = "Marked instruction FPU processing finished", .pme_long_desc = "One of the Floating Point Units finished a marked instruction. Instructions that finish may not necessary complete", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_FPU_FIN], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_FPU_FIN] }, [ POWER4_PME_PM_LSU_BUSY ] = { .pme_name = "PM_LSU_BUSY", .pme_code = 0x4c30, .pme_short_desc = "LSU busy", .pme_long_desc = "LSU (unit 0 + unit 1) is busy rejecting instructions ", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_BUSY], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_BUSY] }, [ POWER4_PME_PM_INST_FROM_L35 ] = { .pme_name = "PM_INST_FROM_L35", .pme_code = 0x4327, .pme_short_desc = "Instructions fetched from L3.5", .pme_long_desc = "An instruction fetch group was fetched from the L3 of another module. Fetch Groups can contain up to 8 instructions", .pme_event_ids = power4_event_ids[POWER4_PME_PM_INST_FROM_L35], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_INST_FROM_L35] }, [ POWER4_PME_PM_FPU1_FRSP_FCONV ] = { .pme_name = "PM_FPU1_FRSP_FCONV", .pme_code = 0x115, .pme_short_desc = "FPU1 executed FRSP or FCONV instructions", .pme_long_desc = "fThis signal is active for one cycle when fp1 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU1_FRSP_FCONV], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU1_FRSP_FCONV] }, [ POWER4_PME_PM_SNOOP_TLBIE ] = { .pme_name = "PM_SNOOP_TLBIE", .pme_code = 0x903, .pme_short_desc = "Snoop TLBIE", .pme_long_desc = "A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_SNOOP_TLBIE], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_SNOOP_TLBIE] }, [ POWER4_PME_PM_FPU0_FDIV ] = { .pme_name = "PM_FPU0_FDIV", .pme_code = 0x100, .pme_short_desc = "FPU0 executed FDIV instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp0 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU0_FDIV], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU0_FDIV] }, [ POWER4_PME_PM_LD_REF_L1_LSU1 ] = { .pme_name = "PM_LD_REF_L1_LSU1", .pme_code = 0xc14, .pme_short_desc = "LSU1 L1 D cache load references", .pme_long_desc = "A load executed on unit 1", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LD_REF_L1_LSU1], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LD_REF_L1_LSU1] }, [ POWER4_PME_PM_MRK_DATA_FROM_L275_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L275_MOD", .pme_code = 0x7c76, .pme_short_desc = "Marked data loaded from L2.75 modified", .pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of another MCM due to a marked demand load. ", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_DATA_FROM_L275_MOD], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_DATA_FROM_L275_MOD] }, [ POWER4_PME_PM_HV_CYC ] = { .pme_name = "PM_HV_CYC", .pme_code = 0x3004, .pme_short_desc = "Hypervisor Cycles", .pme_long_desc = "Cycles when the processor is executing in Hypervisor (MSR[HV] = 0 and MSR[PR]=0)", .pme_event_ids = power4_event_ids[POWER4_PME_PM_HV_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_HV_CYC] }, [ POWER4_PME_PM_6INST_CLB_CYC ] = { .pme_name = "PM_6INST_CLB_CYC", .pme_code = 0x455, .pme_short_desc = "Cycles 6 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is an 8-deep, 4-wide instruction buffer. Fullness is indicated in the 8 valid bits associated with each of the 4-wide slots with full(0) correspanding to the number of cycles there are 8 instructions in the queue and full (7) corresponding to the number of cycles there is 1 instruction in the queue. This signal gives a real time history of the number of instruction quads valid in the instruction queue.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_6INST_CLB_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_6INST_CLB_CYC] }, [ POWER4_PME_PM_LR_CTR_MAP_FULL_CYC ] = { .pme_name = "PM_LR_CTR_MAP_FULL_CYC", .pme_code = 0x206, .pme_short_desc = "Cycles LR/CTR mapper full", .pme_long_desc = "The ISU sends a signal indicating that the lr/ctr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LR_CTR_MAP_FULL_CYC], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LR_CTR_MAP_FULL_CYC] }, [ POWER4_PME_PM_L2SC_MOD_INV ] = { .pme_name = "PM_L2SC_MOD_INV", .pme_code = 0xf27, .pme_short_desc = "L2 slice C transition from modified to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SC_MOD_INV], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SC_MOD_INV] }, [ POWER4_PME_PM_FPU_DENORM ] = { .pme_name = "PM_FPU_DENORM", .pme_code = 0x1120, .pme_short_desc = "FPU received denormalized data", .pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized. Combined Unit 0 + Unit 1", .pme_event_ids = power4_event_ids[POWER4_PME_PM_FPU_DENORM], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_FPU_DENORM] }, [ POWER4_PME_PM_DATA_FROM_L275_MOD ] = { .pme_name = "PM_DATA_FROM_L275_MOD", .pme_code = 0x7c66, .pme_short_desc = "Data loaded from L2.75 modified", .pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of another MCM due to a demand load. ", .pme_event_ids = power4_event_ids[POWER4_PME_PM_DATA_FROM_L275_MOD], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_DATA_FROM_L275_MOD] }, [ POWER4_PME_PM_LSU1_DERAT_MISS ] = { .pme_name = "PM_LSU1_DERAT_MISS", .pme_code = 0x906, .pme_short_desc = "LSU1 DERAT misses", .pme_long_desc = "A data request (load or store) from LSU Unit 1 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU1_DERAT_MISS], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU1_DERAT_MISS] }, [ POWER4_PME_PM_IC_PREF_REQ ] = { .pme_name = "PM_IC_PREF_REQ", .pme_code = 0x326, .pme_short_desc = "Instruction prefetch requests", .pme_long_desc = "Asserted when a non-canceled prefetch is made to the cache interface unit (CIU).", .pme_event_ids = power4_event_ids[POWER4_PME_PM_IC_PREF_REQ], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_IC_PREF_REQ] }, [ POWER4_PME_PM_MRK_LSU_FIN ] = { .pme_name = "PM_MRK_LSU_FIN", .pme_code = 0x8004, .pme_short_desc = "Marked instruction LSU processing finished", .pme_long_desc = "One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_LSU_FIN], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_LSU_FIN] }, [ POWER4_PME_PM_MRK_DATA_FROM_L3 ] = { .pme_name = "PM_MRK_DATA_FROM_L3", .pme_code = 0x1c76, .pme_short_desc = "Marked data loaded from L3", .pme_long_desc = "DL1 was reloaded from the local L3 due to a marked demand load", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_DATA_FROM_L3], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_DATA_FROM_L3] }, [ POWER4_PME_PM_MRK_DATA_FROM_MEM ] = { .pme_name = "PM_MRK_DATA_FROM_MEM", .pme_code = 0x2c76, .pme_short_desc = "Marked data loaded from memory", .pme_long_desc = "DL1 was reloaded from memory due to a marked demand load", .pme_event_ids = power4_event_ids[POWER4_PME_PM_MRK_DATA_FROM_MEM], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_MRK_DATA_FROM_MEM] }, [ POWER4_PME_PM_LSU0_FLUSH_UST ] = { .pme_name = "PM_LSU0_FLUSH_UST", .pme_code = 0xc01, .pme_short_desc = "LSU0 unaligned store flushes", .pme_long_desc = "A store was flushed from unit 0 because it was unaligned (crossed a 4k boundary)", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU0_FLUSH_UST], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU0_FLUSH_UST] }, [ POWER4_PME_PM_LSU_FLUSH_LRQ ] = { .pme_name = "PM_LSU_FLUSH_LRQ", .pme_code = 0x6c00, .pme_short_desc = "LRQ flushes", .pme_long_desc = "A load was flushed because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_FLUSH_LRQ], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_FLUSH_LRQ] }, [ POWER4_PME_PM_LSU_FLUSH_SRQ ] = { .pme_name = "PM_LSU_FLUSH_SRQ", .pme_code = 0x5c00, .pme_short_desc = "SRQ flushes", .pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_LSU_FLUSH_SRQ], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_LSU_FLUSH_SRQ] }, [ POWER4_PME_PM_L2SC_MOD_TAG ] = { .pme_name = "PM_L2SC_MOD_TAG", .pme_code = 0xf26, .pme_short_desc = "L2 slice C transition from modified to tagged", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A,B,and C.", .pme_event_ids = power4_event_ids[POWER4_PME_PM_L2SC_MOD_TAG], .pme_group_vector = power4_group_vecs[POWER4_PME_PM_L2SC_MOD_TAG] } }; #define POWER4_PME_EVENT_COUNT 244 static const int power4_group_event_ids[][POWER4_NUM_EVENT_COUNTERS] = { [ 0 ] = { 94, 81, 83, 77, 81, 81, 77, 80 }, [ 1 ] = { 81, 81, 79, 13, 32, 86, 84, 82 }, [ 2 ] = { 86, 81, 79, 13, 32, 86, 84, 82 }, [ 3 ] = { 86, 0, 8, 9, 33, 81, 10, 36 }, [ 4 ] = { 7, 1, 33, 77, 86, 26, 73, 79 }, [ 5 ] = { 82, 82, 74, 74, 83, 82, 74, 75 }, [ 6 ] = { 87, 86, 78, 78, 91, 87, 79, 73 }, [ 7 ] = { 88, 87, 73, 77, 92, 89, 84, 82 }, [ 8 ] = { 35, 6, 12, 53, 31, 88, 78, 74 }, [ 9 ] = { 34, 5, 56, 52, 31, 88, 78, 74 }, [ 10 ] = { 50, 49, 17, 18, 52, 51, 78, 74 }, [ 11 ] = { 38, 39, 38, 37, 40, 37, 78, 74 }, [ 12 ] = { 42, 43, 40, 39, 44, 41, 78, 74 }, [ 13 ] = { 46, 47, 42, 41, 48, 45, 78, 74 }, [ 14 ] = { 84, 83, 75, 75, 82, 83, 78, 77 }, [ 15 ] = { 83, 84, 73, 77, 84, 84, 75, 78 }, [ 16 ] = { 86, 81, 0, 1, 81, 81, 2, 3 }, [ 17 ] = { 86, 81, 4, 5, 89, 81, 6, 7 }, [ 18 ] = { 80, 2, 11, 34, 53, 32, 78, 74 }, [ 19 ] = { 13, 22, 30, 30, 82, 86, 54, 55 }, [ 20 ] = { 32, 81, 31, 32, 28, 27, 78, 74 }, [ 21 ] = { 85, 92, 83, 16, 82, 86, 15, 76 }, [ 22 ] = { 77, 78, 69, 73, 81, 86, 44, 45 }, [ 23 ] = { 71, 70, 50, 51, 69, 68, 78, 74 }, [ 24 ] = { 86, 36, 73, 74, 83, 82, 74, 75 }, [ 25 ] = { 82, 82, 74, 74, 36, 81, 74, 81 }, [ 26 ] = { 86, 81, 78, 78, 91, 87, 79, 73 }, [ 27 ] = { 87, 86, 78, 78, 91, 87, 73, 81 }, [ 28 ] = { 10, 19, 25, 29, 11, 20, 78, 74 }, [ 29 ] = { 12, 21, 22, 27, 8, 17, 78, 74 }, [ 30 ] = { 9, 18, 23, 28, 82, 86, 21, 26 }, [ 31 ] = { 14, 23, 19, 20, 16, 25, 73, 81 }, [ 32 ] = { 15, 24, 22, 27, 82, 86, 73, 24 }, [ 33 ] = { 86, 81, 76, 76, 88, 85, 76, 79 }, [ 34 ] = { 67, 66, 52, 53, 82, 86, 56, 12 }, [ 35 ] = { 55, 61, 73, 73, 56, 62, 78, 74 }, [ 36 ] = { 57, 63, 48, 49, 82, 86, 46, 47 }, [ 37 ] = { 58, 64, 71, 72, 82, 86, 70, 13 }, [ 38 ] = { 59, 65, 71, 72, 79, 81, 78, 74 }, [ 39 ] = { 54, 60, 73, 73, 36, 81, 78, 74 }, [ 40 ] = { 4, 3, 43, 35, 82, 86, 73, 14 }, [ 41 ] = { 85, 88, 84, 73, 81, 86, 77, 86 }, [ 42 ] = { 92, 91, 73, 84, 90, 92, 82, 81 }, [ 43 ] = { 91, 89, 73, 82, 90, 91, 81, 84 }, [ 44 ] = { 93, 81, 82, 84, 94, 93, 68, 81 }, [ 45 ] = { 92, 81, 81, 85, 94, 92, 78, 85 }, [ 46 ] = { 90, 90, 80, 83, 93, 90, 80, 83 }, [ 47 ] = { 86, 81, 57, 83, 93, 90, 80, 83 }, [ 48 ] = { 90, 90, 80, 83, 82, 86, 80, 57 }, [ 49 ] = { 76, 72, 60, 65, 82, 86, 61, 66 }, [ 50 ] = { 73, 74, 58, 63, 82, 86, 59, 64 }, [ 51 ] = { 75, 81, 62, 67, 82, 92, 82, 81 }, [ 52 ] = { 67, 91, 53, 77, 82, 92, 77, 52 }, [ 53 ] = { 84, 83, 77, 75, 82, 83, 78, 77 }, [ 54 ] = { 81, 84, 22, 77, 86, 84, 27, 78 }, [ 55 ] = { 86, 0, 8, 9, 1, 81, 10, 36 }, [ 56 ] = { 6, 35, 79, 70, 82, 86, 84, 82 }, [ 57 ] = { 86, 81, 74, 74, 83, 82, 74, 75 }, [ 58 ] = { 82, 82, 74, 74, 83, 81, 78, 75 }, [ 59 ] = { 6, 88, 79, 70, 82, 86, 84, 82 }, [ 60 ] = { 84, 83, 22, 27, 82, 84, 78, 78 }, [ 61 ] = { 86, 81, 79, 8, 79, 81, 9, 10 }, [ 62 ] = { 86, 81, 79, 8, 82, 79, 84, 82 } }; static const pmg_power_group_t power4_groups[] = { [ 0 ] = { .pmg_name = "pm_slice0", .pmg_desc = "Time Slice 0", .pmg_event_ids = power4_group_event_ids[0], .pmg_mmcr0 = 0x0000000000000d0eULL, .pmg_mmcr1 = 0x000000004a5675acULL, .pmg_mmcra = 0x0000000000022000ULL }, [ 1 ] = { .pmg_name = "pm_eprof", .pmg_desc = "Group for use with eprof", .pmg_event_ids = power4_group_event_ids[1], .pmg_mmcr0 = 0x000000000000070eULL, .pmg_mmcr1 = 0x1003400045f29420ULL, .pmg_mmcra = 0x0000000000002001ULL }, [ 2 ] = { .pmg_name = "pm_basic", .pmg_desc = "Basic performance indicators", .pmg_event_ids = power4_group_event_ids[2], .pmg_mmcr0 = 0x000000000000090eULL, .pmg_mmcr1 = 0x1003400045f29420ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 3 ] = { .pmg_name = "pm_ifu", .pmg_desc = "IFU events", .pmg_event_ids = power4_group_event_ids[3], .pmg_mmcr0 = 0x0000000000000938ULL, .pmg_mmcr1 = 0x80000000c6767d6cULL, .pmg_mmcra = 0x0000000000022000ULL }, [ 4 ] = { .pmg_name = "pm_isu", .pmg_desc = "ISU Queue full events", .pmg_event_ids = power4_group_event_ids[4], .pmg_mmcr0 = 0x000000000000112aULL, .pmg_mmcr1 = 0x50041000ea5103a0ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 5 ] = { .pmg_name = "pm_lsource", .pmg_desc = "Information on data source", .pmg_event_ids = power4_group_event_ids[5], .pmg_mmcr0 = 0x0000000000000e1cULL, .pmg_mmcr1 = 0x0010c000739ce738ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 6 ] = { .pmg_name = "pm_isource", .pmg_desc = "Instruction Source information", .pmg_event_ids = power4_group_event_ids[6], .pmg_mmcr0 = 0x0000000000000f1eULL, .pmg_mmcr1 = 0x800000007bdef7bcULL, .pmg_mmcra = 0x0000000000022000ULL }, [ 7 ] = { .pmg_name = "pm_lsu", .pmg_desc = "Information on the Load Store Unit", .pmg_event_ids = power4_group_event_ids[7], .pmg_mmcr0 = 0x0000000000000810ULL, .pmg_mmcr1 = 0x000f00003a508420ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 8 ] = { .pmg_name = "pm_xlate1", .pmg_desc = "Translation Events", .pmg_event_ids = power4_group_event_ids[8], .pmg_mmcr0 = 0x0000000000001028ULL, .pmg_mmcr1 = 0x81082000f67e849cULL, .pmg_mmcra = 0x0000000000022000ULL }, [ 9 ] = { .pmg_name = "pm_xlate2", .pmg_desc = "Translation Events", .pmg_event_ids = power4_group_event_ids[9], .pmg_mmcr0 = 0x000000000000112aULL, .pmg_mmcr1 = 0x81082000d77e849cULL, .pmg_mmcra = 0x0000000000022000ULL }, [ 10 ] = { .pmg_name = "pm_gps1", .pmg_desc = "L3 Events", .pmg_event_ids = power4_group_event_ids[10], .pmg_mmcr0 = 0x0000000000001022ULL, .pmg_mmcr1 = 0x00000c00b5e5349cULL, .pmg_mmcra = 0x0000000000022000ULL }, [ 11 ] = { .pmg_name = "pm_l2a", .pmg_desc = "L2 SliceA events", .pmg_event_ids = power4_group_event_ids[11], .pmg_mmcr0 = 0x000000000000162aULL, .pmg_mmcr1 = 0x00000c008469749cULL, .pmg_mmcra = 0x0000000000022000ULL }, [ 12 ] = { .pmg_name = "pm_l2b", .pmg_desc = "L2 SliceB events", .pmg_event_ids = power4_group_event_ids[12], .pmg_mmcr0 = 0x0000000000001a32ULL, .pmg_mmcr1 = 0x0000060094f1b49cULL, .pmg_mmcra = 0x0000000000022000ULL }, [ 13 ] = { .pmg_name = "pm_l2c", .pmg_desc = "L2 SliceC events", .pmg_event_ids = power4_group_event_ids[13], .pmg_mmcr0 = 0x0000000000001e3aULL, .pmg_mmcr1 = 0x00000600a579f49cULL, .pmg_mmcra = 0x0000000000022000ULL }, [ 14 ] = { .pmg_name = "pm_fpu1", .pmg_desc = "Floating Point events", .pmg_event_ids = power4_group_event_ids[14], .pmg_mmcr0 = 0x0000000000000810ULL, .pmg_mmcr1 = 0x00000000420e84a0ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 15 ] = { .pmg_name = "pm_fpu2", .pmg_desc = "Floating Point events", .pmg_event_ids = power4_group_event_ids[15], .pmg_mmcr0 = 0x0000000000000810ULL, .pmg_mmcr1 = 0x010020e83a508420ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 16 ] = { .pmg_name = "pm_idu1", .pmg_desc = "Instruction Decode Unit events", .pmg_event_ids = power4_group_event_ids[16], .pmg_mmcr0 = 0x000000000000090eULL, .pmg_mmcr1 = 0x040100008456794cULL, .pmg_mmcra = 0x0000000000022000ULL }, [ 17 ] = { .pmg_name = "pm_idu2", .pmg_desc = "Instruction Decode Unit events", .pmg_event_ids = power4_group_event_ids[17], .pmg_mmcr0 = 0x000000000000090eULL, .pmg_mmcr1 = 0x04010000a5527b5cULL, .pmg_mmcra = 0x0000000000022000ULL }, [ 18 ] = { .pmg_name = "pm_isu_rename", .pmg_desc = "ISU Rename Pool Events", .pmg_event_ids = power4_group_event_ids[18], .pmg_mmcr0 = 0x0000000000001228ULL, .pmg_mmcr1 = 0x100550008e6d949cULL, .pmg_mmcra = 0x0000000000022000ULL }, [ 19 ] = { .pmg_name = "pm_isu_queues1", .pmg_desc = "ISU Queue Full Events", .pmg_event_ids = power4_group_event_ids[19], .pmg_mmcr0 = 0x000000000000132eULL, .pmg_mmcr1 = 0x10050000850e994cULL, .pmg_mmcra = 0x0000000000022000ULL }, [ 20 ] = { .pmg_name = "pm_isu_flow", .pmg_desc = "ISU Instruction Flow Events", .pmg_event_ids = power4_group_event_ids[20], .pmg_mmcr0 = 0x000000000000190eULL, .pmg_mmcr1 = 0x10005000d7b7c49cULL, .pmg_mmcra = 0x0000000000022000ULL }, [ 21 ] = { .pmg_name = "pm_isu_work", .pmg_desc = "ISU Indicators of Work Blockage", .pmg_event_ids = power4_group_event_ids[21], .pmg_mmcr0 = 0x0000000000000c12ULL, .pmg_mmcr1 = 0x100010004fce9da8ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 22 ] = { .pmg_name = "pm_serialize", .pmg_desc = "LSU Serializing Events", .pmg_event_ids = power4_group_event_ids[22], .pmg_mmcr0 = 0x0000000000001332ULL, .pmg_mmcr1 = 0x0118b000e9d69dfcULL, .pmg_mmcra = 0x0000000000022000ULL }, [ 23 ] = { .pmg_name = "pm_lsubusy", .pmg_desc = "LSU Busy Events", .pmg_event_ids = power4_group_event_ids[23], .pmg_mmcr0 = 0x000000000000193aULL, .pmg_mmcr1 = 0x0000f000dff5e49cULL, .pmg_mmcra = 0x0000000000022000ULL }, [ 24 ] = { .pmg_name = "pm_lsource2", .pmg_desc = "Information on data source", .pmg_event_ids = power4_group_event_ids[24], .pmg_mmcr0 = 0x0000000000000938ULL, .pmg_mmcr1 = 0x0010c0003b9ce738ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 25 ] = { .pmg_name = "pm_lsource3", .pmg_desc = "Information on data source", .pmg_event_ids = power4_group_event_ids[25], .pmg_mmcr0 = 0x0000000000000e1cULL, .pmg_mmcr1 = 0x0010c00073b87724ULL, .pmg_mmcra = 0x0000000000022000ULL }, [ 26 ] = { .pmg_name = "pm_isource2", .pmg_desc = "Instruction Source information", .pmg_event_ids = power4_group_event_ids[26], .pmg_mmcr0 = 0x000000000000090eULL, .pmg_mmcr1 = 0x800000007bdef7bcULL, .pmg_mmcra = 0x0000000000022000ULL }, [ 27 ] = { .pmg_name = "pm_isource3", .pmg_desc = "Instruction Source information", .pmg_event_ids = power4_group_event_ids[27], .pmg_mmcr0 = 0x0000000000000f1eULL, .pmg_mmcr1 = 0x800000007bdef3a4ULL, .pmg_mmcra = 0x0000000000022000ULL }, [ 28 ] = { .pmg_name = "pm_fpu3", .pmg_desc = "Floating Point events by unit", .pmg_event_ids = power4_group_event_ids[28], .pmg_mmcr0 = 0x0000000000001028ULL, .pmg_mmcr1 = 0x000000008d63549cULL, .pmg_mmcra = 0x0000000000022000ULL }, [ 29 ] = { .pmg_name = "pm_fpu4", .pmg_desc = "Floating Point events by unit", .pmg_event_ids = power4_group_event_ids[29], .pmg_mmcr0 = 0x000000000000122cULL, .pmg_mmcr1 = 0x000000009de7749cULL, .pmg_mmcra = 0x0000000000022000ULL }, [ 30 ] = { .pmg_name = "pm_fpu5", .pmg_desc = "Floating Point events by unit", .pmg_event_ids = power4_group_event_ids[30], .pmg_mmcr0 = 0x0000000000001838ULL, .pmg_mmcr1 = 0x00000000850e9958ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 31 ] = { .pmg_name = "pm_fpu6", .pmg_desc = "Floating Point events by unit", .pmg_event_ids = power4_group_event_ids[31], .pmg_mmcr0 = 0x0000000000001b3eULL, .pmg_mmcr1 = 0x01002000c735e3a4ULL, .pmg_mmcra = 0x0000000000022000ULL }, [ 32 ] = { .pmg_name = "pm_fpu7", .pmg_desc = "Floating Point events by unit", .pmg_event_ids = power4_group_event_ids[32], .pmg_mmcr0 = 0x000000000000193aULL, .pmg_mmcr1 = 0x000000009dce93e0ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 33 ] = { .pmg_name = "pm_fxu", .pmg_desc = "Fix Point Unit events", .pmg_event_ids = power4_group_event_ids[33], .pmg_mmcr0 = 0x000000000000090eULL, .pmg_mmcr1 = 0x400000024294a520ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 34 ] = { .pmg_name = "pm_lsu_lmq", .pmg_desc = "LSU Load Miss Queue Events", .pmg_event_ids = power4_group_event_ids[34], .pmg_mmcr0 = 0x0000000000001e3eULL, .pmg_mmcr1 = 0x0100a000ee4e9d78ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 35 ] = { .pmg_name = "pm_lsu_flush", .pmg_desc = "LSU Flush Events", .pmg_event_ids = power4_group_event_ids[35], .pmg_mmcr0 = 0x000000000000122cULL, .pmg_mmcr1 = 0x000c000039e7749cULL, .pmg_mmcra = 0x0000000000022000ULL }, [ 36 ] = { .pmg_name = "pm_lsu_load1", .pmg_desc = "LSU Load Events", .pmg_event_ids = power4_group_event_ids[36], .pmg_mmcr0 = 0x0000000000001028ULL, .pmg_mmcr1 = 0x000f0000850e9958ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 37 ] = { .pmg_name = "pm_lsu_store1", .pmg_desc = "LSU Store Events", .pmg_event_ids = power4_group_event_ids[37], .pmg_mmcr0 = 0x000000000000112aULL, .pmg_mmcr1 = 0x000f00008d4e99dcULL, .pmg_mmcra = 0x0000000000022000ULL }, [ 38 ] = { .pmg_name = "pm_lsu_store2", .pmg_desc = "LSU Store Events", .pmg_event_ids = power4_group_event_ids[38], .pmg_mmcr0 = 0x0000000000001838ULL, .pmg_mmcr1 = 0x0003c0008d76749cULL, .pmg_mmcra = 0x0000000000022000ULL }, [ 39 ] = { .pmg_name = "pm_lsu7", .pmg_desc = "Information on the Load Store Unit", .pmg_event_ids = power4_group_event_ids[39], .pmg_mmcr0 = 0x000000000000122cULL, .pmg_mmcr1 = 0x0118c00039f8749cULL, .pmg_mmcra = 0x0000000000022000ULL }, [ 40 ] = { .pmg_name = "pm_dpfetch", .pmg_desc = "Data Prefetch Events", .pmg_event_ids = power4_group_event_ids[40], .pmg_mmcr0 = 0x000000000000173eULL, .pmg_mmcr1 = 0x0108f000e74e93f8ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 41 ] = { .pmg_name = "pm_misc", .pmg_desc = "Misc Events for testing", .pmg_event_ids = power4_group_event_ids[41], .pmg_mmcr0 = 0x0000000000000c14ULL, .pmg_mmcr1 = 0x0000000061d695b4ULL, .pmg_mmcra = 0x0000000000022000ULL }, [ 42 ] = { .pmg_name = "pm_mark1", .pmg_desc = "Information on marked instructions", .pmg_event_ids = power4_group_event_ids[42], .pmg_mmcr0 = 0x0000000000000816ULL, .pmg_mmcr1 = 0x010080803b18d6a4ULL, .pmg_mmcra = 0x0000000000722001ULL }, [ 43 ] = { .pmg_name = "pm_mark2", .pmg_desc = "Marked Instructions Processing Flow", .pmg_event_ids = power4_group_event_ids[43], .pmg_mmcr0 = 0x0000000000000a1aULL, .pmg_mmcr1 = 0x000000003b58c630ULL, .pmg_mmcra = 0x0000000000002001ULL }, [ 44 ] = { .pmg_name = "pm_mark3", .pmg_desc = "Marked Stores Processing Flow", .pmg_event_ids = power4_group_event_ids[44], .pmg_mmcr0 = 0x0000000000000b0eULL, .pmg_mmcr1 = 0x010020005b1abda4ULL, .pmg_mmcra = 0x0000000000022001ULL }, [ 45 ] = { .pmg_name = "pm_mark4", .pmg_desc = "Marked Loads Processing FLow", .pmg_event_ids = power4_group_event_ids[45], .pmg_mmcr0 = 0x000000000000080eULL, .pmg_mmcr1 = 0x01028080421ad4a0ULL, .pmg_mmcra = 0x0000000000002001ULL }, [ 46 ] = { .pmg_name = "pm_mark_lsource", .pmg_desc = "Information on marked data source", .pmg_event_ids = power4_group_event_ids[46], .pmg_mmcr0 = 0x0000000000000e1cULL, .pmg_mmcr1 = 0x00103000739ce738ULL, .pmg_mmcra = 0x0000000000002001ULL }, [ 47 ] = { .pmg_name = "pm_mark_lsource2", .pmg_desc = "Information on marked data source", .pmg_event_ids = power4_group_event_ids[47], .pmg_mmcr0 = 0x000000000000090eULL, .pmg_mmcr1 = 0x00103000e39ce738ULL, .pmg_mmcra = 0x0000000000002001ULL }, [ 48 ] = { .pmg_name = "pm_mark_lsource3", .pmg_desc = "Information on marked data source", .pmg_event_ids = power4_group_event_ids[48], .pmg_mmcr0 = 0x0000000000000e1cULL, .pmg_mmcr1 = 0x00103000738e9770ULL, .pmg_mmcra = 0x0000000000002001ULL }, [ 49 ] = { .pmg_name = "pm_lsu_mark1", .pmg_desc = "Load Store Unit Marked Events", .pmg_event_ids = power4_group_event_ids[49], .pmg_mmcr0 = 0x0000000000001b34ULL, .pmg_mmcr1 = 0x01028000850e98d4ULL, .pmg_mmcra = 0x0000000000022001ULL }, [ 50 ] = { .pmg_name = "pm_lsu_mark2", .pmg_desc = "Load Store Unit Marked Events", .pmg_event_ids = power4_group_event_ids[50], .pmg_mmcr0 = 0x0000000000001838ULL, .pmg_mmcr1 = 0x01028000958e99dcULL, .pmg_mmcra = 0x0000000000022001ULL }, [ 51 ] = { .pmg_name = "pm_lsu_mark3", .pmg_desc = "Load Store Unit Marked Events", .pmg_event_ids = power4_group_event_ids[51], .pmg_mmcr0 = 0x0000000000001d0eULL, .pmg_mmcr1 = 0x0100b000ce8ed6a4ULL, .pmg_mmcra = 0x0000000000022001ULL }, [ 52 ] = { .pmg_name = "pm_threshold", .pmg_desc = "Group for pipeline threshold studies", .pmg_event_ids = power4_group_event_ids[52], .pmg_mmcr0 = 0x0000000000001e16ULL, .pmg_mmcr1 = 0x0100a000ca4ed5f4ULL, .pmg_mmcra = 0x0000000000722001ULL }, [ 53 ] = { .pmg_name = "pm_pe_bench1", .pmg_desc = "PE Benchmarker group for FP analysis", .pmg_event_ids = power4_group_event_ids[53], .pmg_mmcr0 = 0x0000000000000810ULL, .pmg_mmcr1 = 0x10001002420e84a0ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 54 ] = { .pmg_name = "pm_pe_bench2", .pmg_desc = "PE Benchmarker group for FP stalls analysis", .pmg_event_ids = power4_group_event_ids[54], .pmg_mmcr0 = 0x0000000000000710ULL, .pmg_mmcr1 = 0x110420689a508ba0ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 55 ] = { .pmg_name = "pm_pe_bench3", .pmg_desc = "PE Benchmarker group for branch analysis", .pmg_event_ids = power4_group_event_ids[55], .pmg_mmcr0 = 0x0000000000000938ULL, .pmg_mmcr1 = 0x90040000c66a7d6cULL, .pmg_mmcra = 0x0000000000022000ULL }, [ 56 ] = { .pmg_name = "pm_pe_bench4", .pmg_desc = "PE Benchmarker group for L1 and TLB analysis", .pmg_event_ids = power4_group_event_ids[56], .pmg_mmcr0 = 0x0000000000001420ULL, .pmg_mmcr1 = 0x010b000044ce9420ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 57 ] = { .pmg_name = "pm_pe_bench5", .pmg_desc = "PE Benchmarker group for L2 analysis", .pmg_event_ids = power4_group_event_ids[57], .pmg_mmcr0 = 0x000000000000090eULL, .pmg_mmcr1 = 0x0010c000739ce738ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 58 ] = { .pmg_name = "pm_pe_bench6", .pmg_desc = "PE Benchmarker group for L3 analysis", .pmg_event_ids = power4_group_event_ids[58], .pmg_mmcr0 = 0x0000000000000e1cULL, .pmg_mmcr1 = 0x0010c000739c74b8ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 59 ] = { .pmg_name = "pm_hpmcount1", .pmg_desc = "Hpmcount group for L1 and TLB behavior analysis", .pmg_event_ids = power4_group_event_ids[59], .pmg_mmcr0 = 0x0000000000001414ULL, .pmg_mmcr1 = 0x010b000044ce9420ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 60 ] = { .pmg_name = "pm_hpmcount2", .pmg_desc = "Hpmcount group for computation intensity analysis", .pmg_event_ids = power4_group_event_ids[60], .pmg_mmcr0 = 0x0000000000000810ULL, .pmg_mmcr1 = 0x010020289dce84a0ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 61 ] = { .pmg_name = "pm_l1andbr", .pmg_desc = "L1 misses and branch misspredict analysis", .pmg_event_ids = power4_group_event_ids[61], .pmg_mmcr0 = 0x000000000000090eULL, .pmg_mmcr1 = 0x8003c00046367ce8ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 62 ] = { .pmg_name = "Instruction mix: loads", .pmg_desc = " stores and branches", .pmg_event_ids = power4_group_event_ids[62], .pmg_mmcr0 = 0x000000000000090eULL, .pmg_mmcr1 = 0x8003c000460fb420ULL, .pmg_mmcra = 0x0000000000002000ULL } }; #endif papi-5.5.1/src/libpfm-3.y/lib/pfmlib_sparc_priv.h0000644000307100002310000000120713013651450021542 0ustar yarkhangraduatetypedef struct { char *pme_name; /* event name */ char *pme_desc; /* event description */ char pme_ctrl; /* S0 or S1 */ char __pad; int pme_val; /* S0/S1 encoding */ } pme_sparc_entry_t; typedef struct { char *mask_name; /* mask name */ char *mask_desc; /* mask description */ } pme_sparc_mask_t; #define EVENT_MASK_BITS 8 typedef struct { char *pme_name; /* event name */ char *pme_desc; /* event description */ char pme_ctrl; /* S0 or S1 */ char __pad; int pme_val; /* S0/S1 encoding */ pme_sparc_mask_t pme_masks[EVENT_MASK_BITS]; } pme_sparc_mask_entry_t; #define PME_CTRL_S0 1 #define PME_CTRL_S1 2 papi-5.5.1/src/libpfm-3.y/lib/pfmlib_intel_atom.c0000644000307100002310000005242213013651450021525 0ustar yarkhangraduate/* * pfmlib_intel_atom.c : Intel Atom PMU * * Copyright (c) 2008 Google, Inc * Contributed by Stephane Eranian * * Based on work: * Copyright (c) 2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * * This file implements support for Intel Core PMU as specified in the following document: * "IA-32 Intel Architecture Software Developer's Manual - Volume 3B: System * Programming Guide" * * Intel Atom = architectural v3 + PEBS */ #include #include #include #include #include /* public headers */ #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_atom_priv.h" #include "intel_atom_events.h" /* let's define some handy shortcuts! */ #define sel_event_select perfevtsel.sel_event_select #define sel_unit_mask perfevtsel.sel_unit_mask #define sel_usr perfevtsel.sel_usr #define sel_os perfevtsel.sel_os #define sel_edge perfevtsel.sel_edge #define sel_pc perfevtsel.sel_pc #define sel_int perfevtsel.sel_int #define sel_en perfevtsel.sel_en #define sel_inv perfevtsel.sel_inv #define sel_cnt_mask perfevtsel.sel_cnt_mask #define sel_any perfevtsel.sel_any #define has_pebs(i) (intel_atom_pe[i].pme_flags & PFMLIB_INTEL_ATOM_PEBS) /* * Description of the PMC register mappings: * * 0 -> PMC0 -> PERFEVTSEL0 * 1 -> PMC1 -> PERFEVTSEL1 * 16 -> PMC16 -> FIXED_CTR_CTRL * 17 -> PMC17 -> PEBS_ENABLED * * Description of the PMD register mapping: * * 0 -> PMD0 -> PMC0 * 1 -> PMD1 -> PMC1 * 16 -> PMD2 -> FIXED_CTR0 * 17 -> PMD3 -> FIXED_CTR1 * 18 -> PMD4 -> FIXED_CTR2 */ #define INTEL_ATOM_SEL_BASE 0x186 #define INTEL_ATOM_CTR_BASE 0xc1 #define FIXED_CTR_BASE 0x309 #define PFMLIB_INTEL_ATOM_ALL_FLAGS \ (PFM_INTEL_ATOM_SEL_INV|PFM_INTEL_ATOM_SEL_EDGE|PFM_INTEL_ATOM_SEL_ANYTHR) static pfmlib_regmask_t intel_atom_impl_pmcs, intel_atom_impl_pmds; static int highest_counter; static int pfm_intel_atom_detect(void) { int ret, family, model; char buffer[128]; ret = __pfm_getcpuinfo_attr("vendor_id", buffer, sizeof(buffer)); if (ret == -1) return PFMLIB_ERR_NOTSUPP; if (strcmp(buffer, "GenuineIntel")) return PFMLIB_ERR_NOTSUPP; ret = __pfm_getcpuinfo_attr("cpu family", buffer, sizeof(buffer)); if (ret == -1) return PFMLIB_ERR_NOTSUPP; family = atoi(buffer); ret = __pfm_getcpuinfo_attr("model", buffer, sizeof(buffer)); if (ret == -1) return PFMLIB_ERR_NOTSUPP; model = atoi(buffer); /* * Atom : family 6 model 28 */ return family == 6 && model == 28 ? PFMLIB_SUCCESS : PFMLIB_ERR_NOTSUPP; } static int pfm_intel_atom_init(void) { int i; /* generic counters */ pfm_regmask_set(&intel_atom_impl_pmcs, 0); pfm_regmask_set(&intel_atom_impl_pmds, 0); pfm_regmask_set(&intel_atom_impl_pmcs, 1); pfm_regmask_set(&intel_atom_impl_pmds, 1); /* fixed counters */ pfm_regmask_set(&intel_atom_impl_pmcs, 16); pfm_regmask_set(&intel_atom_impl_pmds, 16); pfm_regmask_set(&intel_atom_impl_pmds, 17); pfm_regmask_set(&intel_atom_impl_pmds, 18); /* lbr */ pfm_regmask_set(&intel_atom_impl_pmds, 19); for(i=0; i < 16; i++) pfm_regmask_set(&intel_atom_impl_pmds, i); highest_counter = 18; /* PEBS */ pfm_regmask_set(&intel_atom_impl_pmcs, 17); return PFMLIB_SUCCESS; } static int pfm_intel_atom_is_fixed(pfmlib_event_t *e, unsigned int f) { unsigned int fl, flc, i; unsigned int mask = 0; fl = intel_atom_pe[e->event].pme_flags; /* * first pass: check if event as a whole supports fixed counters */ switch(f) { case 0: mask = PFMLIB_INTEL_ATOM_FIXED0; break; case 1: mask = PFMLIB_INTEL_ATOM_FIXED1; break; case 2: mask = PFMLIB_INTEL_ATOM_FIXED2_ONLY; break; default: return 0; } if (fl & mask) return 1; /* * second pass: check if unit mask supports fixed counter * * reject if mask not found OR if not all unit masks have * same fixed counter mask */ flc = 0; for(i=0; i < e->num_masks; i++) { fl = intel_atom_pe[e->event].pme_umasks[e->unit_masks[i]].pme_flags; if (fl & mask) flc++; } return flc > 0 && flc == e->num_masks ? 1 : 0; } /* * IMPORTANT: the interface guarantees that pfp_pmds[] elements are returned in the order the events * were submitted. */ static int pfm_intel_atom_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_intel_atom_input_param_t *param, pfmlib_output_param_t *outp) { #define HAS_OPTIONS(x) (cntrs && (cntrs[x].flags || cntrs[x].cnt_mask)) #define is_fixed_pmc(a) (a == 16 || a == 17 || a == 18) pfmlib_intel_atom_counter_t *cntrs; pfm_intel_atom_sel_reg_t reg; pfmlib_event_t *e; pfmlib_reg_t *pc, *pd; pfmlib_regmask_t *r_pmcs; uint64_t val; unsigned long plm; unsigned long long fixed_ctr; unsigned int npc, npmc0, npmc1, nf2; unsigned int i, j, n, k, ucode, use_pebs = 0, done_pebs; unsigned int assign_pc[PMU_INTEL_ATOM_NUM_COUNTERS]; unsigned int next_gen, last_gen; npc = npmc0 = npmc1 = nf2 = 0; e = inp->pfp_events; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; n = inp->pfp_event_count; r_pmcs = &inp->pfp_unavail_pmcs; cntrs = param ? param->pfp_intel_atom_counters : NULL; use_pebs = param ? param->pfp_intel_atom_pebs_used : 0; if (n > PMU_INTEL_ATOM_NUM_COUNTERS) return PFMLIB_ERR_TOOMANY; /* * initilize to empty */ for(i=0; i < PMU_INTEL_ATOM_NUM_COUNTERS; i++) assign_pc[i] = -1; /* * error checking */ for(i=0; i < n; i++) { /* * only supports two priv levels for perf counters */ if (e[i].plm & (PFM_PLM1|PFM_PLM2)) return PFMLIB_ERR_INVAL; /* * check for valid flags */ if (cntrs && cntrs[i].flags & ~PFMLIB_INTEL_ATOM_ALL_FLAGS) return PFMLIB_ERR_INVAL; if (intel_atom_pe[e[i].event].pme_flags & PFMLIB_INTEL_ATOM_UMASK_NCOMBO && e[i].num_masks > 1) { DPRINT("events does not support unit mask combination\n"); return PFMLIB_ERR_NOASSIGN; } /* * check event-level single register constraint (PMC0, PMC1, FIXED_CTR2) * fail if more than two events requested for the same counter */ if (intel_atom_pe[e[i].event].pme_flags & PFMLIB_INTEL_ATOM_PMC0) { if (++npmc0 > 1) { DPRINT("two events compete for a PMC0\n"); return PFMLIB_ERR_NOASSIGN; } } /* * check if PMC1 is available and if only one event is dependent on it */ if (intel_atom_pe[e[i].event].pme_flags & PFMLIB_INTEL_ATOM_PMC1) { if (++npmc1 > 1) { DPRINT("two events compete for a PMC1\n"); return PFMLIB_ERR_NOASSIGN; } } /* * UNHALTED_REFERENCE_CYCLES can only be measured on FIXED_CTR2 */ if (intel_atom_pe[e[i].event].pme_flags & PFMLIB_INTEL_ATOM_FIXED2_ONLY) { if (++nf2 > 1) { DPRINT("two events compete for FIXED_CTR2\n"); return PFMLIB_ERR_NOASSIGN; } if (cntrs && ((cntrs[i].flags & (PFM_INTEL_ATOM_SEL_EDGE|PFM_INTEL_ATOM_SEL_INV)) || cntrs[i].cnt_mask)) { DPRINT("UNHALTED_REFERENCE_CYCLES only accepts anythr filter\n"); return PFMLIB_ERR_NOASSIGN; } } /* * unit-mask level constraint checking (PMC0, PMC1, FIXED_CTR2) */ for(j=0; j < e[i].num_masks; j++) { unsigned int flags; flags = intel_atom_pe[e[i].event].pme_umasks[e[i].unit_masks[j]].pme_flags; if (flags & PFMLIB_INTEL_ATOM_FIXED2_ONLY) { if (++nf2 > 1) { DPRINT("two events compete for FIXED_CTR2\n"); return PFMLIB_ERR_NOASSIGN; } if (HAS_OPTIONS(i)) { DPRINT("fixed counters do not support inversion/counter-mask\n"); return PFMLIB_ERR_NOASSIGN; } } } } next_gen = 0; /* first generic counter */ last_gen = 1; /* last generic counter */ /* * strongest constraint first: works only in IA32_PMC0, IA32_PMC1, FIXED_CTR2 * * When PEBS is used, we pick the first PEBS event and * place it into PMC0. Subsequent PEBS events, will go * in the other counters. */ done_pebs = 0; for(i=0; i < n; i++) { if ((intel_atom_pe[e[i].event].pme_flags & PFMLIB_INTEL_ATOM_PMC0) || (use_pebs && pfm_intel_atom_has_pebs(e+i) && done_pebs == 0)) { if (pfm_regmask_isset(r_pmcs, 0)) return PFMLIB_ERR_NOASSIGN; assign_pc[i] = 0; next_gen = 1; done_pebs = 1; } if (intel_atom_pe[e[i].event].pme_flags & PFMLIB_INTEL_ATOM_PMC1) { if (pfm_regmask_isset(r_pmcs, 1)) return PFMLIB_ERR_NOASSIGN; assign_pc[i] = 1; if (next_gen == 1) next_gen = 2; else next_gen = 0; } } /* * next constraint: fixed counters * * We abuse the mapping here for assign_pc to make it easier * to provide the correct values for pd[]. * We use: * - 16 : fixed counter 0 (pmc16, pmd16) * - 17 : fixed counter 1 (pmc16, pmd17) * - 18 : fixed counter 1 (pmc16, pmd18) */ fixed_ctr = pfm_regmask_isset(r_pmcs, 16) ? 0 : 0x7; if (fixed_ctr) { for(i=0; i < n; i++) { /* fixed counters do not support event options (filters) */ if (HAS_OPTIONS(i)) { if (use_pebs && pfm_intel_atom_has_pebs(e+i)) continue; if (cntrs[i].flags != PFM_INTEL_ATOM_SEL_ANYTHR) continue; } if ((fixed_ctr & 0x1) && pfm_intel_atom_is_fixed(e+i, 0)) { assign_pc[i] = 16; fixed_ctr &= ~1; } if ((fixed_ctr & 0x2) && pfm_intel_atom_is_fixed(e+i, 1)) { assign_pc[i] = 17; fixed_ctr &= ~2; } if ((fixed_ctr & 0x4) && pfm_intel_atom_is_fixed(e+i, 2)) { assign_pc[i] = 18; fixed_ctr &= ~4; } } } /* * assign what is left */ for(i=0; i < n; i++) { if (assign_pc[i] == -1) { for(; next_gen <= last_gen; next_gen++) { if (!pfm_regmask_isset(r_pmcs, next_gen)) break; } if (next_gen <= last_gen) assign_pc[i] = next_gen++; else { DPRINT("cannot assign generic counters\n"); return PFMLIB_ERR_NOASSIGN; } } } j = 0; /* setup fixed counters */ reg.val = 0; k = 0; for (i=0; i < n ; i++ ) { if (!is_fixed_pmc(assign_pc[i])) continue; val = 0; /* if plm is 0, then assume not specified per-event and use default */ plm = e[i].plm ? e[i].plm : inp->pfp_dfl_plm; if (plm & PFM_PLM0) val |= 1ULL; if (plm & PFM_PLM3) val |= 2ULL; if (cntrs && cntrs[i].flags & PFM_INTEL_ATOM_SEL_ANYTHR) val |= 4ULL; val |= 1ULL << 3; /* force APIC int (kernel may force it anyway) */ reg.val |= val << ((assign_pc[i]-16)<<2); } if (reg.val) { pc[npc].reg_num = 16; pc[npc].reg_value = reg.val; pc[npc].reg_addr = 0x38D; pc[npc].reg_alt_addr = 0x38D; __pfm_vbprintf("[FIXED_CTRL(pmc%u)=0x%"PRIx64" pmi0=1 en0=0x%"PRIx64" any0=%d pmi1=1 en1=0x%"PRIx64" any1=%d pmi2=1 en2=0x%"PRIx64" any2=%d] ", pc[npc].reg_num, reg.val, reg.val & 0x3ULL, !!(reg.val & 0x4ULL), (reg.val>>4) & 0x3ULL, !!((reg.val>>4) & 0x4ULL), (reg.val>>8) & 0x3ULL, !!((reg.val>>8) & 0x4ULL)); if ((fixed_ctr & 0x1) == 0) __pfm_vbprintf("INSTRUCTIONS_RETIRED "); if ((fixed_ctr & 0x2) == 0) __pfm_vbprintf("UNHALTED_CORE_CYCLES "); if ((fixed_ctr & 0x4) == 0) __pfm_vbprintf("UNHALTED_REFERENCE_CYCLES "); __pfm_vbprintf("\n"); npc++; if ((fixed_ctr & 0x1) == 0) __pfm_vbprintf("[FIXED_CTR0(pmd16)]\n"); if ((fixed_ctr & 0x2) == 0) __pfm_vbprintf("[FIXED_CTR1(pmd17)]\n"); if ((fixed_ctr & 0x4) == 0) __pfm_vbprintf("[FIXED_CTR2(pmd18)]\n"); } for (i=0; i < n ; i++ ) { /* skip fixed counters */ if (is_fixed_pmc(assign_pc[i])) continue; reg.val = 0; /* assume reserved bits are zerooed */ /* if plm is 0, then assume not specified per-event and use default */ plm = e[i].plm ? e[i].plm : inp->pfp_dfl_plm; val = intel_atom_pe[e[i].event].pme_code; reg.sel_event_select = val & 0xff; ucode = (val >> 8) & 0xff; for(k=0; k < e[i].num_masks; k++) ucode |= intel_atom_pe[e[i].event].pme_umasks[e[i].unit_masks[k]].pme_ucode; val |= ucode << 8; reg.sel_unit_mask = ucode; reg.sel_usr = plm & PFM_PLM3 ? 1 : 0; reg.sel_os = plm & PFM_PLM0 ? 1 : 0; reg.sel_en = 1; /* force enable bit to 1 */ reg.sel_int = 1; /* force APIC int to 1 */ reg.sel_cnt_mask = val >>24; reg.sel_inv = val >> 23; reg.sel_edge = val >> 18; reg.sel_any = val >> 21;; if (cntrs) { if (!reg.sel_cnt_mask) { /* * counter mask is 8-bit wide, do not silently * wrap-around */ if (cntrs[i].cnt_mask > 255) return PFMLIB_ERR_INVAL; reg.sel_cnt_mask = cntrs[i].cnt_mask; } if (!reg.sel_edge) reg.sel_edge = cntrs[i].flags & PFM_INTEL_ATOM_SEL_EDGE ? 1 : 0; if (!reg.sel_inv) reg.sel_inv = cntrs[i].flags & PFM_INTEL_ATOM_SEL_INV ? 1 : 0; if (!reg.sel_any) reg.sel_any = cntrs[i].flags & PFM_INTEL_ATOM_SEL_ANYTHR? 1 : 0; } pc[npc].reg_num = assign_pc[i]; pc[npc].reg_value = reg.val; pc[npc].reg_addr = INTEL_ATOM_SEL_BASE+assign_pc[i]; pc[npc].reg_alt_addr= INTEL_ATOM_SEL_BASE+assign_pc[i]; __pfm_vbprintf("[PERFEVTSEL%u(pmc%u)=0x%"PRIx64" event_sel=0x%x umask=0x%x os=%d usr=%d en=%d int=%d inv=%d edge=%d cnt_mask=%d anythr=%d] %s\n", pc[npc].reg_num, pc[npc].reg_num, reg.val, reg.sel_event_select, reg.sel_unit_mask, reg.sel_os, reg.sel_usr, reg.sel_en, reg.sel_int, reg.sel_inv, reg.sel_edge, reg.sel_cnt_mask, reg.sel_any, intel_atom_pe[e[i].event].pme_name); __pfm_vbprintf("[PMC%u(pmd%u)]\n", pc[npc].reg_num, pc[npc].reg_num); npc++; } /* * setup pmds: must be in the same order as the events */ for (i=0; i < n ; i++) { if (is_fixed_pmc(assign_pc[i])) { /* setup pd array */ pd[i].reg_num = assign_pc[i]; pd[i].reg_addr = FIXED_CTR_BASE+assign_pc[i]-16; pd[i].reg_alt_addr = 0x40000000+assign_pc[i]-16; } else { pd[i].reg_num = assign_pc[i]; pd[i].reg_addr = INTEL_ATOM_CTR_BASE+assign_pc[i]; /* index to use with RDPMC */ pd[i].reg_alt_addr = assign_pc[i]; } } outp->pfp_pmd_count = i; /* * setup PEBS_ENABLE */ if (use_pebs && done_pebs) { /* * check that PEBS_ENABLE is available */ if (pfm_regmask_isset(r_pmcs, 17)) return PFMLIB_ERR_NOASSIGN; pc[npc].reg_num = 17; pc[npc].reg_value = 1ULL; pc[npc].reg_addr = 0x3f1; /* IA32_PEBS_ENABLE */ pc[npc].reg_alt_addr = 0x3f1; /* IA32_PEBS_ENABLE */ __pfm_vbprintf("[PEBS_ENABLE(pmc%u)=0x%"PRIx64" ena=%d]\n", pc[npc].reg_num, pc[npc].reg_value, pc[npc].reg_value & 0x1ull); npc++; } outp->pfp_pmc_count = npc; return PFMLIB_SUCCESS; } static int pfm_intel_atom_dispatch_events(pfmlib_input_param_t *inp, void *model_in, pfmlib_output_param_t *outp, void *model_out) { pfmlib_intel_atom_input_param_t *mod_in = (pfmlib_intel_atom_input_param_t *)model_in; if (inp->pfp_dfl_plm & (PFM_PLM1|PFM_PLM2)) { DPRINT("invalid plm=%x\n", inp->pfp_dfl_plm); return PFMLIB_ERR_INVAL; } return pfm_intel_atom_dispatch_counters(inp, mod_in, outp); } static int pfm_intel_atom_get_event_code(unsigned int i, unsigned int cnt, int *code) { if (cnt != PFMLIB_CNT_FIRST && (cnt > highest_counter || !pfm_regmask_isset(&intel_atom_impl_pmds, cnt))) return PFMLIB_ERR_INVAL; *code = intel_atom_pe[i].pme_code; return PFMLIB_SUCCESS; } static void pfm_intel_atom_get_event_counters(unsigned int j, pfmlib_regmask_t *counters) { unsigned int n, i; unsigned int has_f0, has_f1, has_f2; memset(counters, 0, sizeof(*counters)); n = intel_atom_pe[j].pme_numasks; has_f0 = has_f1 = has_f2 = 0; for (i=0; i < n; i++) { if (intel_atom_pe[j].pme_umasks[i].pme_flags & PFMLIB_INTEL_ATOM_FIXED0) has_f0 = 1; if (intel_atom_pe[j].pme_umasks[i].pme_flags & PFMLIB_INTEL_ATOM_FIXED1) has_f1 = 1; if (intel_atom_pe[j].pme_umasks[i].pme_flags & PFMLIB_INTEL_ATOM_FIXED2_ONLY) has_f2 = 1; } if (has_f0 == 0) has_f0 = intel_atom_pe[j].pme_flags & PFMLIB_INTEL_ATOM_FIXED0; if (has_f1 == 0) has_f1 = intel_atom_pe[j].pme_flags & PFMLIB_INTEL_ATOM_FIXED1; if (has_f2 == 0) has_f2 = intel_atom_pe[j].pme_flags & PFMLIB_INTEL_ATOM_FIXED2_ONLY; if (has_f0) pfm_regmask_set(counters, 16); if (has_f1) pfm_regmask_set(counters, 17); if (has_f2) pfm_regmask_set(counters, 18); /* the event on FIXED_CTR2 is exclusive CPU_CLK_UNHALTED:REF */ if (!has_f2) { pfm_regmask_set(counters, 0); pfm_regmask_set(counters, 1); if (intel_atom_pe[j].pme_flags & PFMLIB_INTEL_ATOM_PMC0) pfm_regmask_clr(counters, 1); if (intel_atom_pe[j].pme_flags & PFMLIB_INTEL_ATOM_PMC1) pfm_regmask_clr(counters, 0); } } static void pfm_intel_atom_get_impl_pmcs(pfmlib_regmask_t *impl_pmcs) { *impl_pmcs = intel_atom_impl_pmcs; } static void pfm_intel_atom_get_impl_pmds(pfmlib_regmask_t *impl_pmds) { *impl_pmds = intel_atom_impl_pmds; } static void pfm_intel_atom_get_impl_counters(pfmlib_regmask_t *impl_counters) { pfm_regmask_set(impl_counters, 0); pfm_regmask_set(impl_counters, 1); pfm_regmask_set(impl_counters, 16); pfm_regmask_set(impl_counters, 17); pfm_regmask_set(impl_counters, 18); } /* * Even though, CPUID 0xa returns in eax the actual counter * width, the architecture specifies that writes are limited * to lower 32-bits. As such, only the lower 32-bit have full * degree of freedom. That is the "useable" counter width. */ #define PMU_INTEL_ATOM_COUNTER_WIDTH 32 static void pfm_intel_atom_get_hw_counter_width(unsigned int *width) { /* * Even though, CPUID 0xa returns in eax the actual counter * width, the architecture specifies that writes are limited * to lower 32-bits. As such, only the lower 31 bits have full * degree of freedom. That is the "useable" counter width. */ *width = PMU_INTEL_ATOM_COUNTER_WIDTH; } static char * pfm_intel_atom_get_event_name(unsigned int i) { return intel_atom_pe[i].pme_name; } static int pfm_intel_atom_get_event_description(unsigned int ev, char **str) { char *s; s = intel_atom_pe[ev].pme_desc; if (s) { *str = strdup(s); } else { *str = NULL; } return PFMLIB_SUCCESS; } static char * pfm_intel_atom_get_event_mask_name(unsigned int ev, unsigned int midx) { return intel_atom_pe[ev].pme_umasks[midx].pme_uname; } static int pfm_intel_atom_get_event_mask_desc(unsigned int ev, unsigned int midx, char **str) { char *s; s = intel_atom_pe[ev].pme_umasks[midx].pme_udesc; if (s) { *str = strdup(s); } else { *str = NULL; } return PFMLIB_SUCCESS; } static unsigned int pfm_intel_atom_get_num_event_masks(unsigned int ev) { return intel_atom_pe[ev].pme_numasks; } static int pfm_intel_atom_get_event_mask_code(unsigned int ev, unsigned int midx, unsigned int *code) { *code =intel_atom_pe[ev].pme_umasks[midx].pme_ucode; return PFMLIB_SUCCESS; } static int pfm_intel_atom_get_cycle_event(pfmlib_event_t *e) { e->event = PME_INTEL_ATOM_UNHALTED_CORE_CYCLES; return PFMLIB_SUCCESS; } static int pfm_intel_atom_get_inst_retired(pfmlib_event_t *e) { e->event = PME_INTEL_ATOM_INSTRUCTIONS_RETIRED; return PFMLIB_SUCCESS; } /* * this function is directly accessible by external caller * library initialization is not required, though recommended */ int pfm_intel_atom_has_pebs(pfmlib_event_t *e) { unsigned int i, n=0; if (e == NULL || e->event >= PME_INTEL_ATOM_EVENT_COUNT) return 0; if (intel_atom_pe[e->event].pme_flags & PFMLIB_INTEL_ATOM_PEBS) return 1; /* * ALL unit mask must support PEBS for this test to return true */ for(i=0; i < e->num_masks; i++) { /* check for valid unit mask */ if (e->unit_masks[i] >= intel_atom_pe[e->event].pme_numasks) return 0; if (intel_atom_pe[e->event].pme_umasks[e->unit_masks[i]].pme_flags & PFMLIB_INTEL_ATOM_PEBS) n++; } return n > 0 && n == e->num_masks; } pfm_pmu_support_t intel_atom_support={ .pmu_name = "Intel Atom", .pmu_type = PFMLIB_INTEL_ATOM_PMU, .pme_count = PME_INTEL_ATOM_EVENT_COUNT, .pmc_count = 4, .pmd_count = 22, .num_cnt = 5, .get_event_code = pfm_intel_atom_get_event_code, .get_event_name = pfm_intel_atom_get_event_name, .get_event_counters = pfm_intel_atom_get_event_counters, .dispatch_events = pfm_intel_atom_dispatch_events, .pmu_detect = pfm_intel_atom_detect, .pmu_init = pfm_intel_atom_init, .get_impl_pmcs = pfm_intel_atom_get_impl_pmcs, .get_impl_pmds = pfm_intel_atom_get_impl_pmds, .get_impl_counters = pfm_intel_atom_get_impl_counters, .get_hw_counter_width = pfm_intel_atom_get_hw_counter_width, .get_event_desc = pfm_intel_atom_get_event_description, .get_num_event_masks = pfm_intel_atom_get_num_event_masks, .get_event_mask_name = pfm_intel_atom_get_event_mask_name, .get_event_mask_code = pfm_intel_atom_get_event_mask_code, .get_event_mask_desc = pfm_intel_atom_get_event_mask_desc, .get_cycle_event = pfm_intel_atom_get_cycle_event, .get_inst_retired_event = pfm_intel_atom_get_inst_retired }; papi-5.5.1/src/libpfm-3.y/lib/pfmlib_gen_ia32_priv.h0000644000307100002310000000521613013651450022025 0ustar yarkhangraduate/* * Copyright (c) 2006-2007 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #ifndef __PFMLIB_GEN_IA32_PRIV_H__ #define __PFMLIB_GEN_IA32_PRIV_H__ #define PFMLIB_GEN_IA32_MAX_UMASK 16 typedef struct { char *pme_uname; /* unit mask name */ char *pme_udesc; /* event/umask description */ unsigned int pme_ucode; /* unit mask code */ } pme_gen_ia32_umask_t; typedef struct { char *pme_name; /* event name */ char *pme_desc; /* event description */ unsigned int pme_code; /* event code */ unsigned int pme_numasks; /* number of umasks */ unsigned int pme_flags; /* flags */ unsigned int pme_fixed; /* fixed counter index, < FIXED_CTR0 if unsupported */ pme_gen_ia32_umask_t pme_umasks[PFMLIB_GEN_IA32_MAX_UMASK]; /* umask desc */ } pme_gen_ia32_entry_t; /* * pme_flags value */ #define PFMLIB_GEN_IA32_UMASK_COMBO 0x01 /* unit mask can be combined (default exclusive) */ typedef struct { unsigned int version:8; unsigned int num_cnt:8; unsigned int cnt_width:8; unsigned int ebx_length:8; } pmu_eax_t; typedef struct { unsigned int num_cnt:6; unsigned int cnt_width:6; unsigned int reserved:20; } pmu_edx_t; typedef struct { unsigned int no_core_cycle:1; unsigned int no_inst_retired:1; unsigned int no_ref_cycle:1; unsigned int no_llc_ref:1; unsigned int no_llc_miss:1; unsigned int no_br_retired:1; unsigned int no_br_mispred_retired:1; unsigned int reserved:25; } pmu_ebx_t; #endif /* __PFMLIB_GEN_IA32_PRIV_H__ */ papi-5.5.1/src/libpfm-3.y/lib/niagara2_events.h0000644000307100002310000002021313013651450021107 0ustar yarkhangraduatestatic pme_sparc_mask_entry_t niagara2_pe[] = { /* PIC0 Niagara-2 events */ { .pme_name = "All_strands_idle", .pme_desc = "Cycles when no strand can be picked for the physical core on which the monitoring strand resides.", .pme_ctrl = PME_CTRL_S0 | PME_CTRL_S1, .pme_val = 0x0, .pme_masks = { { .mask_name = "ignored0", .mask_desc = "Ignored", }, { .mask_name = "ignored1", .mask_desc = "Ignored", }, { .mask_name = "ignored2", .mask_desc = "Ignored", }, { .mask_name = "ignored3", .mask_desc = "Ignored", }, { .mask_name = "ignored4", .mask_desc = "Ignored", }, { .mask_name = "ignored5", .mask_desc = "Ignored", }, { .mask_name = "ignored6", .mask_desc = "Ignored", }, { .mask_name = "ignored7", .mask_desc = "Ignored", }, }, }, { .pme_name = "Instr_cnt", .pme_desc = "Number of instructions completed", .pme_ctrl = PME_CTRL_S0 | PME_CTRL_S1, .pme_val = 0x2, .pme_masks = { { .mask_name = "branches", .mask_desc = "Completed branches", }, { .mask_name = "taken_branches", .mask_desc = "Taken branches, which are always mispredicted", }, { .mask_name = "FGU_arith", .mask_desc = "All FADD, FSUB, FCMP, convert, FMUL, FDIV, FNEG, FABS, FSQRT, FMOV, FPADD, FPSUB, FPACK, FEXPAND, FPMERGE, FMUL8, FMULD8, FALIGNDATA, BSHUFFLE, FZERO, FONE, FSRC, FNOT1, FNOT2, FOR, FNOR, FAND, FNAND, FXOR, FXNOR, FORNOT1, FORNOT2, FANDNOT1, FANDNOT2, PDIST, SIAM", }, { .mask_name = "Loads", .mask_desc = "Load instructions", }, { .mask_name = "Stores", .mask_desc = "Stores instructions", }, { .mask_name = "SW_count", .mask_desc = "Software count 'sethi %hi(fc00), %g0' instructions", }, { .mask_name = "other", .mask_desc = "Instructions not covered by other mask bits", }, { .mask_name = "atomics", .mask_desc = "Atomics are LDSTUB/A, CASA/XA, SWAP/A", }, }, }, { .pme_name = "cache", .pme_desc = "Cache events", .pme_ctrl = PME_CTRL_S0 | PME_CTRL_S1, .pme_val = 0x3, .pme_masks = { { .mask_name = "IC_miss", .mask_desc = "I-cache misses. This counts only primary instruction cache misses, and does not count duplicate instruction cache misses.4 Also, only 'true' misses are counted. If a thread encounters an I$ miss, but the thread is redirected (due to a branch misprediction or trap, for example) before the line returns from L2 and is loaded into the I$, then the miss is not counted.", }, { .mask_name = "DC_miss", .mask_desc = "D-cache misses. This counts both primary and duplicate data cache misses.", }, { .mask_name = "ignored0", .mask_desc = "Ignored", }, { .mask_name = "ignored1", .mask_desc = "Ignored", }, { .mask_name = "L2IC_miss", .mask_desc = "L2 cache instruction misses", }, { .mask_name = "L2LD_miss", .mask_desc = "L2 cache load misses. Block loads are treated as one L2 miss event. In reality, each individual load can hit or miss in the L2 since the block load is not atomic.", }, { .mask_name = "ignored2", .mask_desc = "Ignored", }, { .mask_name = "ignored3", .mask_desc = "Ignored", }, }, }, { .pme_name = "TLB", .pme_desc = "TLB events", .pme_ctrl = PME_CTRL_S0 | PME_CTRL_S1, .pme_val = 0x4, .pme_masks = { { .mask_name = "ignored0", .mask_desc = "Ignored", }, { .mask_name = "ignored1", .mask_desc = "Ignored", }, { .mask_name = "ITLB_L2ref", .mask_desc = "ITLB references to L2. For each ITLB miss with hardware tablewalk enabled, count each access the ITLB hardware tablewalk makes to L2.", }, { .mask_name = "DTLB_L2ref", .mask_desc = "DTLB references to L2. For each DTLB miss with hardware tablewalk enabled, count each access the DTLB hardware tablewalk makes to L2.", }, { .mask_name = "ITLB_L2miss", .mask_desc = "For each ITLB miss with hardware tablewalk enabled, count each access the ITLB hardware tablewalk makes to L2 which misses in L2. Note: Depending upon the hardware table walk configuration, each ITLB miss may issue from 1 to 4 requests to L2 to search TSBs.", }, { .mask_name = "DTLB_L2miss", .mask_desc = "For each DTLB miss with hardware tablewalk enabled, count each access the DTLB hardware tablewalk makes to L2 which misses in L2. Note: Depending upon the hardware table walk configuration, each DTLB miss may issue from 1 to 4 requests to L2 to search TSBs.", }, { .mask_name = "ignored2", .mask_desc = "Ignored", }, { .mask_name = "ignored3", .mask_desc = "Ignored", }, }, }, { .pme_name = "mem", .pme_desc = "Memory operations", .pme_ctrl = PME_CTRL_S0 | PME_CTRL_S1, .pme_val = 0x5, .pme_masks = { { .mask_name = "stream_load", .mask_desc = "Stream Unit load operations to L2", }, { .mask_name = "stream_store", .mask_desc = "Stream Unit store operations to L2", }, { .mask_name = "cpu_load", .mask_desc = "CPU loads to L2", }, { .mask_name = "cpu_ifetch", .mask_desc = "CPU instruction fetches to L2", }, { .mask_name = "ignored0", .mask_desc = "Ignored", }, { .mask_name = "ignored0", .mask_desc = "Ignored", }, { .mask_name = "cpu_store", .mask_desc = "CPU stores to L2", }, { .mask_name = "mmu_load", .mask_desc = "MMU loads to L2", }, }, }, { .pme_name = "spu_ops", .pme_desc = "Stream Unit operations. User, supervisor, and hypervisor counting must all be enabled to properly count these events.", .pme_ctrl = PME_CTRL_S0 | PME_CTRL_S1, .pme_val = 0x6, .pme_masks = { { .mask_name = "DES", .mask_desc = "Increment for each CWQ or ASI operation that uses DES/3DES unit", }, { .mask_name = "AES", .mask_desc = "Increment for each CWQ or ASI operation that uses AES unit", }, { .mask_name = "RC4", .mask_desc = "Increment for each CWQ or ASI operation that uses RC4 unit", }, { .mask_name = "HASH", .mask_desc = "Increment for each CWQ or ASI operation that uses MD5/SHA-1/SHA-256 unit", }, { .mask_name = "MA", .mask_desc = "Increment for each CWQ or ASI modular arithmetic operation", }, { .mask_name = "CSUM", .mask_desc = "Increment for each iSCSI CRC or TCP/IP checksum operation", }, { .mask_name = "ignored0", .mask_desc = "Ignored", }, { .mask_name = "ignored1", .mask_desc = "Ignored", }, }, }, { .pme_name = "spu_busy", .pme_desc = "Stream Unit busy cycles. User, supervisor, and hypervisor counting must all be enabled to properly count these events.", .pme_ctrl = PME_CTRL_S0 | PME_CTRL_S1, .pme_val = 0x07, .pme_masks = { { .mask_name = "DES", .mask_desc = "Cycles the DES/3DES unit is busy", }, { .mask_name = "AES", .mask_desc = "Cycles the AES unit is busy", }, { .mask_name = "RC4", .mask_desc = "Cycles the RC4 unit is busy", }, { .mask_name = "HASH", .mask_desc = "Cycles the MD5/SHA-1/SHA-256 unit is busy", }, { .mask_name = "MA", .mask_desc = "Cycles the modular arithmetic unit is busy", }, { .mask_name = "CSUM", .mask_desc = "Cycles the CRC/MPA/checksum unit is busy", }, { .mask_name = "ignored0", .mask_desc = "Ignored", }, { .mask_name = "ignored1", .mask_desc = "Ignored", }, }, }, { .pme_name = "tlb_miss", .pme_desc = "TLB misses", .pme_ctrl = PME_CTRL_S0 | PME_CTRL_S1, .pme_val = 0xb, .pme_masks = { { .mask_name = "ignored0", .mask_desc = "Ignored", }, { .mask_name = "ignored1", .mask_desc = "Ignored", }, { .mask_name = "ITLB", .mask_desc = "I-TLB misses", }, { .mask_name = "DTLB", .mask_desc = "D-TLB misses", }, { .mask_name = "ignored2", .mask_desc = "Ignored", }, { .mask_name = "ignored3", .mask_desc = "Ignored", }, { .mask_name = "ignored4", .mask_desc = "Ignored", }, { .mask_name = "ignored5", .mask_desc = "Ignored", }, }, }, }; #define PME_NIAGARA2_EVENT_COUNT (sizeof(niagara2_pe)/sizeof(pme_sparc_mask_entry_t)) papi-5.5.1/src/libpfm-3.y/lib/pfmlib_ppc970mp_priv.h0000644000307100002310000000120713013651450022011 0ustar yarkhangraduate/****************************/ /* THIS IS OPEN SOURCE CODE */ /****************************/ #ifndef __PFMLIB_PPC970MP_PRIV_H__ #define __PFMLIB_PPC970MP_PRIV_H__ /* * File: pfmlib_ppc970mp_priv.h * CVS: * Author: Corey Ashford * cjashfor@us.ibm.com * Mods: * * * (C) Copyright IBM Corporation, 2007. All Rights Reserved. * Contributed by Corey Ashford * * Note: This code was automatically generated and should not be modified by * hand. * */ #define PPC970MP_NUM_EVENT_COUNTERS 8 #define PPC970MP_NUM_GROUP_VEC 1 #define PPC970MP_NUM_CONTROL_REGS 3 #endif papi-5.5.1/src/libpfm-3.y/lib/cell_events.h0000644000307100002310000033644113013651450020357 0ustar yarkhangraduate/* * Copyright (c) 2007 TOSHIBA CORPORATION based on code from * Copyright (c) 2001-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ static pme_cell_entry_t cell_pe[] = { {.pme_name = "CYCLES", .pme_desc = "CPU cycles", .pme_code = 0x0, /* 0 */ .pme_enable_word = WORD_NONE, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BRANCH_COMMIT_TH0", .pme_desc = "Branch instruction committed.", .pme_code = 0x834, /* 2100 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BRANCH_FLUSH_TH0", .pme_desc = "Branch instruction that caused a misprediction flush is committed. Branch misprediction includes", .pme_code = 0x835, /* 2101 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "INST_BUFF_EMPTY_TH0", .pme_desc = "Instruction buffer empty.", .pme_code = 0x836, /* 2102 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "INST_ERAT_MISS_TH0", .pme_desc = "Instruction effective-address-to-real-address translation (I-ERAT) miss.", .pme_code = 0x837, /* 2103 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L1_ICACHE_MISS_CYCLES_TH0", .pme_desc = "L1 Instruction cache miss cycles. Counts the cycles from the miss event until the returned instruction is dispatched or cancelled due to branch misprediction, completion restart, or exceptions.", .pme_code = 0x838, /* 2104 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "DISPATCH_BLOCKED_TH0", .pme_desc = "Valid instruction available for dispatch, but dispatch is blocked.", .pme_code = 0x83a, /* 2106 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "INST_FLUSH_TH0", .pme_desc = "Instruction in pipeline stage EX7 causes a flush.", .pme_code = 0x83d, /* 2109 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "PPC_INST_COMMIT_TH0", .pme_desc = "Two PowerPC instructions committed. For microcode sequences, only the last microcode operation is counted. Committed instructions are counted two at a time. If only one instruction has committed for a given cycle, this event will not be raised until another instruction has been committed in a future cycle.", .pme_code = 0x83f, /* 2111 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BRANCH_COMMIT_TH1", .pme_desc = "Branch instruction committed.", .pme_code = 0x847, /* 2119 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BRANCH_FLUSH_TH1", .pme_desc = "Branch instruction that caused a misprediction flush is committed. Branch misprediction includes", .pme_code = 0x848, /* 2120 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "INST_BUFF_EMPTY_TH1", .pme_desc = "Instruction buffer empty.", .pme_code = 0x849, /* 2121 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "INST_ERAT_MISS_TH1", .pme_desc = "Instruction effective-address-to-real-address translation (I-ERAT) miss.", .pme_code = 0x84a, /* 2122 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L1_ICACHE_MISS_CYCLES_TH1", .pme_desc = "L1 Instruction cache miss cycles. Counts the cycles from the miss event until the returned instruction is dispatched or cancelled due to branch misprediction, completion restart, or exceptions.", .pme_code = 0x84b, /* 2123 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "DISPATCH_BLOCKED_TH1", .pme_desc = "Valid instruction available for dispatch, but dispatch is blocked.", .pme_code = 0x84d, /* 2125 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "INST_FLUSH_TH1", .pme_desc = "Instruction in pipeline stage EX7 causes a flush.", .pme_code = 0x850, /* 2128 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "PPC_INST_COMMIT_TH1", .pme_desc = "Two PowerPC instructions committed. For microcode sequences, only the last microcode operation is counted. Committed instructions are counted two at a time. If only one instruction has committed for a given cycle, this event will not be raised until another instruction has been committed in a future cycle.", .pme_code = 0x852, /* 2130 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "DATA_ERAT_MISS_TH0", .pme_desc = "Data effective-address-to-real-address translation (D-ERAT) miss. Not speculative.", .pme_code = 0x89a, /* 2202 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "ST_REQ_TH0", .pme_desc = "Store request counted at the L2 interface. Counts microcoded PPE sequences more than once. (Thread 0 and 1)", .pme_code = 0x89b, /* 2203 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "LD_VALID_TH0", .pme_desc = "Load valid at a particular pipe stage. Speculative, since flushed operations are counted as well. Counts microcoded PPE sequences more than once. Misaligned flushes might be counted the first time as well. Load operations include all loads that read data from the cache, dcbt and dcbtst. Does not include load Vector/SIMD multimedia extension pattern instructions.", .pme_code = 0x89c, /* 2204 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "L1_DCACHE_MISS_TH0", .pme_desc = "L1 D-cache load miss. Pulsed when there is a miss request that has a tag miss but not an ERAT miss. Speculative, since flushed operations are counted as well.", .pme_code = 0x89d, /* 2205 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "DATA_ERAT_MISS_TH1", .pme_desc = "Data effective-address-to-real-address translation (D-ERAT) miss. Not speculative.", .pme_code = 0x8aa, /* 2218 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "LD_VALID_TH1", .pme_desc = "Load valid at a particular pipe stage. Speculative, since flushed operations are counted as well. Counts microcoded PPE sequences more than once. Misaligned flushes might be counted the first time as well. Load operations include all loads that read data from the cache, dcbt and dcbtst. Does not include load Vector/SIMD multimedia extension pattern instructions.", .pme_code = 0x8ac, /* 2220 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "DATA_ERAT_MISS_TH1", .pme_desc = "L1 D-cache load miss. Pulsed when there is a miss request that has a tag miss but not an ERAT miss. Speculative, since flushed operations are counted as well.", .pme_code = 0x8ad, /* 2221 */ .pme_enable_word = WORD_0_AND_1, .pme_freq = PFM_CELL_PME_FREQ_PPU_MFC, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "LD_MFC_MMIO", .pme_desc = "Load from MFC memory-mapped I/O (MMIO) space.", .pme_code = 0xc1c, /* 3100 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "ST_MFC_MMIO", .pme_desc = "Stores to MFC MMIO space.", .pme_code = 0xc1d, /* 3101 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "REQ_TOKEN_TYPE", .pme_desc = "Request token for even memory bank numbers 0-14.", .pme_code = 0xc22, /* 3106 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "RCV_8BEAT_DATA", .pme_desc = "Receive 8-beat data from the Element Interconnect Bus (EIB).", .pme_code = 0xc2b, /* 3115 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "SEND_8BEAT_DATA", .pme_desc = "Send 8-beat data to the EIB.", .pme_code = 0xc2c, /* 3116 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "SEND_CMD", .pme_desc = "Send a command to the EIB; includes retried commands.", .pme_code = 0xc2d, /* 3117 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "DATA_GRANT_CYCLES", .pme_desc = "Cycles between data request and data grant.", .pme_code = 0xc2e, /* 3118 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "NCU_ST_Q_NOT_EMPTY_CYCLES", .pme_desc = "The five-entry Non-Cacheable Unit (NCU) Store Command queue not empty.", .pme_code = 0xc33, /* 3123 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "L2_CACHE_HIT", .pme_desc = "Cache hit for core interface unit (CIU) loads and stores.", .pme_code = 0xc80, /* 3200 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_CACHE_MISS", .pme_desc = "Cache miss for CIU loads and stores.", .pme_code = 0xc81, /* 3201 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_LD_MISS", .pme_desc = "CIU load miss.", .pme_code = 0xc84, /* 3204 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_ST_MISS", .pme_desc = "CIU store to Invalid state (miss).", .pme_code = 0xc85, /* 3205 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_LWARX_LDARX_MISS_TH0", .pme_desc = "Load word and reserve indexed (lwarx/ldarx) for Thread 0 hits Invalid cache state", .pme_code = 0xc87, /* 3207 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_STWCX_STDCX_MISS_TH0", .pme_desc = "Store word conditional indexed (stwcx/stdcx) for Thread 0 hits Invalid cache state when reservation is set.", .pme_code = 0xc8e, /* 3214 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_ALL_SNOOP_SM_BUSY", .pme_desc = "All four snoop state machines busy.", .pme_code = 0xc99, /* 3225 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "L2_DCLAIM_GOOD", .pme_desc = "Data line claim (dclaim) that received good combined response; includes store/stcx/dcbz to Shared (S), Shared Last (SL),or Tagged (T) cache state; does not include dcbz to Invalid (I) cache state.", .pme_code = 0xce8, /* 3304 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_DCLAIM_TO_RWITM", .pme_desc = "Dclaim converted into rwitm; may still not get to the bus if stcx is aborted .", .pme_code = 0xcef, /* 3311 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_ST_TO_M_MU_E", .pme_desc = "Store to modified (M), modified unsolicited (MU), or exclusive (E) cache state.", .pme_code = 0xcf0, /* 3312 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_ST_Q_FULL", .pme_desc = "8-entry store queue (STQ) full.", .pme_code = 0xcf1, /* 3313 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "L2_ST_TO_RC_ACKED", .pme_desc = "Store dispatched to RC machine is acknowledged.", .pme_code = 0xcf2, /* 3314 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_GATHERABLE_ST", .pme_desc = "Gatherable store (type = 00000) received from CIU.", .pme_code = 0xcf3, /* 3315 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_SNOOP_PUSH", .pme_desc = "Snoop push.", .pme_code = 0xcf6, /* 3318 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_INTERVENTION_FROM_SL_E_SAME_MODE", .pme_desc = "Send intervention from (SL | E) cache state to a destination within the same CBE chip.", .pme_code = 0xcf7, /* 3319 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_INTERVENTION_FROM_M_MU_SAME_MODE", .pme_desc = "Send intervention from (M | MU) cache state to a destination within the same CBE chip.", .pme_code = 0xcf8, /* 3320 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_SNOOP_RETRY_CONFLICTS", .pme_desc = "Respond with Retry to a snooped request due to one of the following conflicts", .pme_code = 0xcfd, /* 3325 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_SNOOP_RETRY_BUSY", .pme_desc = "Respond with Retry to a snooped request because all snoop machines are busy.", .pme_code = 0xcfe, /* 3326 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_SNOOP_RESP_MMU_TO_EST", .pme_desc = "Snooped response causes a cache state transition from (M | MU) to (E | S | T).", .pme_code = 0xcff, /* 3327 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_SNOOP_RESP_E_TO_S", .pme_desc = "Snooped response causes a cache state transition from E to S.", .pme_code = 0xd00, /* 3328 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_SNOOP_RESP_ESLST_TO_I", .pme_desc = "Snooped response causes a cache state transition from (E | SL | S | T) to Invalid (I).", .pme_code = 0xd01, /* 3329 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_SNOOP_RESP_MMU_TO_I", .pme_desc = "Snooped response causes a cache state transition from (M | MU) to I.", .pme_code = 0xd02, /* 3330 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_LWARX_LDARX_MISS_TH1", .pme_desc = "Load and reserve indexed (lwarx/ldarx) for Thread 1 hits Invalid cache state.", .pme_code = 0xd54, /* 3412 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "L2_STWCX_STDCX_MISS_TH1", .pme_desc = "Store conditional indexed (stwcx/stdcx) for Thread 1 hits Invalid cache state.", .pme_code = 0xd5b, /* 3419 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "NCU_NON_CACHEABLE_ST_ALL", .pme_desc = "Non-cacheable store request received from CIU; includes all synchronization operations such as sync and eieio.", .pme_code = 0xdac, /* 3500 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "NCU_SYNC_REQ", .pme_desc = "sync received from CIU.", .pme_code = 0xdad, /* 3501 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "NCU_NON_CACHEABLE_ST", .pme_desc = "Non-cacheable store request received from CIU; includes only stores.", .pme_code = 0xdb0, /* 3504 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "NCU_EIEIO_REQ", .pme_desc = "eieio received from CIU.", .pme_code = 0xdb2, /* 3506 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "NCU_TLBIE_REQ", .pme_desc = "tlbie received from CIU.", .pme_code = 0xdb3, /* 3507 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "NCU_SYNC_WAIT", .pme_desc = "sync at the bottom of the store queue, while waiting on st_done signal from the Bus Interface Unit (BIU) and sync_done signal from L2.", .pme_code = 0xdb4, /* 3508 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "NCU_LWSYNC_WAIT", .pme_desc = "lwsync at the bottom of the store queue, while waiting for a sync_done signal from the L2.", .pme_code = 0xdb5, /* 3509 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "NCU_EIEIO_WAIT", .pme_desc = "eieio at the bottom of the store queue, while waiting for a st_done signal from the BIU and a sync_done signal from the L2.", .pme_code = 0xdb6, /* 3510 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "NCU_TLBIE_WAIT", .pme_desc = "tlbie at the bottom of the store queue, while waiting for a st_done signal from the BIU.", .pme_code = 0xdb7, /* 3511 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "NCU_COMBINED_NON_CACHEABLE_ST", .pme_desc = "Non-cacheable store combined with the previous non-cacheable store with a contiguous address.", .pme_code = 0xdb8, /* 3512 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "NCU_ALL_ST_GATHER_BUFFS_FULL", .pme_desc = "All four store-gather buffers full.", .pme_code = 0xdbb, /* 3515 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "NCU_LD_REQ", .pme_desc = "Non-cacheable load request received from CIU; includes instruction and data fetches.", .pme_code = 0xdbc, /* 3516 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "NCU_ST_Q_NOT_EMPTY", .pme_desc = "The four-deep store queue not empty.", .pme_code = 0xdbd, /* 3517 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "NCU_ST_Q_FULL", .pme_desc = "The four-deep store queue full.", .pme_code = 0xdbe, /* 3518 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "NCU_AT_LEAST_ONE_ST_GATHER_BUFF_NOT_EMPTY", .pme_desc = "At least one store gather buffer not empty.", .pme_code = 0xdbf, /* 3519 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_DUAL_INST_COMMITTED", .pme_desc = "A dual instruction is committed.", .pme_code = 0x1004, /* 4100 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_SINGLE_INST_COMMITTED", .pme_desc = "A single instruction is committed.", .pme_code = 0x1005, /* 4101 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_PIPE0_INST_COMMITTED", .pme_desc = "A pipeline 0 instruction is committed.", .pme_code = 0x1006, /* 4102 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_PIPE1_INST_COMMITTED", .pme_desc = "A pipeline 1 instruction is committed.", .pme_code = 0x1007, /* 4103 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_LS_BUSY", .pme_desc = "Local storage is busy.", .pme_code = 0x1009, /* 4105 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "SPU_DMA_CONFLICT_LD_ST", .pme_desc = "A direct memory access (DMA) might conflict with a load or store.", .pme_code = 0x100a, /* 4106 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_LS_ST", .pme_desc = "A store instruction to local storage is issued.", .pme_code = 0x100b, /* 4107 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_LS_LD", .pme_desc = "A load instruction from local storage is issued.", .pme_code = 0x100c, /* 4108 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_FP_EXCEPTION", .pme_desc = "A floating-point unit exception occurred.", .pme_code = 0x100d, /* 4109 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_BRANCH_COMMIT", .pme_desc = "A branch instruction is committed.", .pme_code = 0x100e, /* 4110 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_NON_SEQ_PC", .pme_desc = "A nonsequential change of the SPU program counter has occurred. This can be caused by branch, asynchronous interrupt, stalled wait on channel, error-correction code (ECC) error, and so forth.", .pme_code = 0x100f, /* 4111 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_BRANCH_NOT_TAKEN", .pme_desc = "A branch was not taken.", .pme_code = 0x1010, /* 4112 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_BRANCH_MISS_PREDICTION", .pme_desc = "Branch miss prediction. This count is not exact. Certain other code sequences can cause additional pulses on this signal.", .pme_code = 0x1011, /* 4113 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_BRANCH_HINT_MISS_PREDICTION", .pme_desc = "Branch hint miss prediction. This count is not exact. Certain other code sequences can cause additional pulses on this signal.", .pme_code = 0x1012, /* 4114 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_INST_SEQ_ERROR", .pme_desc = "Instruction sequence error", .pme_code = 0x1013, /* 4115 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "SPU_STALL_CH_WRITE", .pme_desc = "Stalled waiting on any blocking channel write.", .pme_code = 0x1015, /* 4117 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "SPU_STALL_EXTERNAL_EVENT_CH0", .pme_desc = "Stalled waiting on external event status (Channel 0).", .pme_code = 0x1016, /* 4118 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "SPU_STALL_SIGNAL_1_CH3", .pme_desc = "Stalled waiting on SPU Signal Notification 1 (Channel 3).", .pme_code = 0x1017, /* 4119 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "SPU_STALL_SIGNAL_2_CH4", .pme_desc = "Stalled waiting on SPU Signal Notification 2 (Channel 4).", .pme_code = 0x1018, /* 4120 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "SPU_STALL_DMA_CH21", .pme_desc = "Stalled waiting on DMA Command Opcode or ClassID Register (Channel 21).", .pme_code = 0x1019, /* 4121 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "SPU_STALL_MFC_READ_CH24", .pme_desc = "Stalled waiting on memory flow control (MFC) Read Tag-Group Status (Channel 24).", .pme_code = 0x101a, /* 4122 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "SPU_STALL_MFC_READ_CH25", .pme_desc = "Stalled waiting on MFC Read List Stall-and-Notify Tag Status (Channel 25).", .pme_code = 0x101b, /* 4123 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "SPU_STALL_OUTBOUND_MAILBOX_WRITE_CH28", .pme_desc = "Stalled waiting on SPU Write Outbound Mailbox (Channel 28).", .pme_code = 0x101c, /* 4124 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "SPU_STALL_MAILBOX_CH29", .pme_desc = "Stalled waiting on SPU Mailbox (Channel 29).", .pme_code = 0x1022, /* 4130 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "SPU_TR_STALL_CH", .pme_desc = "Stalled waiting on a channel operation.", .pme_code = 0x10a1, /* 4257 */ .pme_enable_word = WORD_NONE, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "SPU_EV_INST_FETCH_STALL", .pme_desc = "Instruction fetch stall", .pme_code = 0x1107, /* 4359 */ .pme_enable_word = WORD_NONE, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "SPU_EV_ADDR_TRACE", .pme_desc = "Serialized SPU address (program counter) trace.", .pme_code = 0x110b, /* 4363 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_SPU, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_ATOMIC_LD", .pme_desc = "An atomic load was received from direct memory access controller (DMAC).", .pme_code = 0x13ed, /* 5101 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_ATOMIC_DCLAIM", .pme_desc = "An atomic dclaim was sent to synergistic bus interface (SBI); includes retried requests.", .pme_code = 0x13ee, /* 5102 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_ATOMIC_RWITM", .pme_desc = "An atomic rwitm performed was sent to SBI; includes retried requests.", .pme_code = 0x13ef, /* 5103 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_ATOMIC_LD_CACHE_MISS_MU", .pme_desc = "An atomic load miss caused MU cache state.", .pme_code = 0x13f0, /* 5104 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_ATOMIC_LD_CACHE_MISS_E", .pme_desc = "An atomic load miss caused E cache state.", .pme_code = 0x13f1, /* 5105 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_ATOMIC_LD_CACHE_MISS_SL", .pme_desc = "An atomic load miss caused SL cache state.", .pme_code = 0x13f2, /* 5106 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_ATOMIC_LD_CACHE_HIT", .pme_desc = "An atomic load hits cache.", .pme_code = 0x13f3, /* 5107 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_ATOMIC_LD_CACHE_MISS_INTERVENTION", .pme_desc = "Atomic load misses cache with data intervention; sum of signals 4 and 6 in this group.", .pme_code = 0x13f4, /* 5108 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_ATOMIC_PUTLLXC_CACHE_MISS_WO_INTERVENTION", .pme_desc = "putllc or putlluc misses cache without data intervention; for putllc, counts only when reservation is set for the address.", .pme_code = 0x13fa, /* 5114 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_SNOOP_MACHINE_BUSY", .pme_desc = "Snoop machine busy.", .pme_code = 0x13fd, /* 5117 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MFC_SNOOP_MMU_TO_I", .pme_desc = "A snoop caused cache transition from [M | MU] to I.", .pme_code = 0x13ff, /* 5119 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_SNOOP_ESSL_TO_I", .pme_desc = "A snoop caused cache transition from [E | S | SL] to I.", .pme_code = 0x1401, /* 5121 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_SNOOP_MU_TO_T", .pme_desc = "A snoop caused cache transition from MU to T cache state.", .pme_code = 0x1403, /* 5123 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_SENT_INTERVENTION_LOCAL", .pme_desc = "Sent modified data intervention to a destination within the same CBE chip.", .pme_code = 0x1407, /* 5127 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_ANY_DMA_GET", .pme_desc = "Any flavor of DMA get[] command issued to Synergistic Bus Interface (SBI); sum of signals 17-25 in this group.", .pme_code = 0x1450, /* 5200 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_ANY_DMA_PUT", .pme_desc = "Any flavor of DMA put[] command issued to SBI; sum of signals 2-16 in this group.", .pme_code = 0x1451, /* 5201 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_DMA_PUT", .pme_desc = "DMA put (put) is issued to SBI.", .pme_code = 0x1452, /* 5202 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_DMA_GET", .pme_desc = "DMA get data from effective address to local storage (get) issued to SBI.", .pme_code = 0x1461, /* 5217 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_LD_REQ", .pme_desc = "Load request sent to element interconnect bus (EIB); includes read, read atomic, rwitm, rwitm atomic, and retried commands.", .pme_code = 0x14b8, /* 5304 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_ST_REQ", .pme_desc = "Store request sent to EIB; includes wwf, wwc, wwk, dclaim, dclaim atomic, and retried commands.", .pme_code = 0x14b9, /* 5305 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_RECV_DATA", .pme_desc = "Received data from EIB, including partial cache line data.", .pme_code = 0x14ba, /* 5306 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_SENT_DATA", .pme_desc = "Sent data to EIB, both as a master and a snooper.", .pme_code = 0x14bb, /* 5307 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_SBI_Q_NOT_EMPTY", .pme_desc = "16-deep synergistic bus interface (SBI) queue with outgoing requests not empty; does not include atomic requests.", .pme_code = 0x14bc, /* 5308 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MFC_SBI_Q_FULL", .pme_desc = "16-deep SBI queue with outgoing requests full; does not include atomic requests.", .pme_code = 0x14bd, /* 5309 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MFC_SENT_REQ", .pme_desc = "Sent request to EIB.", .pme_code = 0x14be, /* 5310 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_RECV_DATA_BUS_GRANT", .pme_desc = "Received data bus grant; includes data sent for MMIO operations.", .pme_code = 0x14c0, /* 5312 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_WAIT_DATA_BUS_GRANT", .pme_desc = "Cycles between data bus request and data bus grant.", .pme_code = 0x14c1, /* 5313 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MFC_CMD_O_MEM", .pme_desc = "Command (read or write) for an odd-numbered memory bank; valid only when resource allocation is turned on.", .pme_code = 0x14c2, /* 5314 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_CMD_E_MEM", .pme_desc = "Command (read or write) for an even-numbered memory bank; valid only when resource allocation is turned on.", .pme_code = 0x14c3, /* 5315 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_RECV_RETRY_RESP", .pme_desc = "Request gets the Retry response; includes local and global requests.", .pme_code = 0x14c6, /* 5318 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_SENT_DATA_BUS_REQ", .pme_desc = "Sent data bus request to EIB.", .pme_code = 0x14c7, /* 5319 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_TLB_MISS", .pme_desc = "Translation Lookaside Buffer (TLB) miss without parity or protection errors.", .pme_code = 0x1518, /* 5400 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "MFC_TLB_CYCLES", .pme_desc = "TLB miss (cycles).", .pme_code = 0x1519, /* 5401 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MFC_TLB_HIT", .pme_desc = "TLB hit.", .pme_code = 0x151a, /* 5402 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_READ_RWITM_1", .pme_desc = "Number of read and rwitm commands (including atomic) AC1 to AC0. (Group 1)", .pme_code = 0x17d4, /* 6100 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_DCLAIM_1", .pme_desc = "Number of dclaim commands (including atomic) AC1 to AC0. (Group 1)", .pme_code = 0x17d5, /* 6101 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_WWK_WWC_WWF_1", .pme_desc = "Number of wwk, wwc, and wwf commands from AC1 to AC0. (Group 1)", .pme_code = 0x17d6, /* 6102 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SYNC_TLBSYNC_EIEIO_1", .pme_desc = "Number of sync, tlbsync, and eieio commands from AC1 to AC0. (Group 1)", .pme_code = 0x17d7, /* 6103 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_TLBIE_1", .pme_desc = "Number of tlbie commands from AC1 to AC0. (Group 1)", .pme_code = 0x17d8, /* 6104 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_PAAM_CAM_HIT_1", .pme_desc = "Previous adjacent address match (PAAM) Content Addressable Memory (CAM) hit. (Group 1)", .pme_code = 0x17df, /* 6111 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_PAAM_CAM_MISS_1", .pme_desc = "PAAM CAM miss. (Group 1)", .pme_code = 0x17e0, /* 6112 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_CMD_REFLECTED_1", .pme_desc = "Command reflected. (Group 1)", .pme_code = 0x17e2, /* 6114 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_READ_RWITM_2", .pme_desc = "Number of read and rwitm commands (including atomic) AC1 to AC0. (Group 2)", .pme_code = 0x17e4, /* 6116 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_DCLAIM_2", .pme_desc = "Number of dclaim commands (including atomic) AC1 to AC0. (Group 2)", .pme_code = 0x17e5, /* 6117 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_WWK_WWC_WWF_2", .pme_desc = "Number of wwk, wwc, and wwf commands from AC1 to AC0. (Group 2)", .pme_code = 0x17e6, /* 6118 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SYNC_TLBSYNC_EIEIO_2", .pme_desc = "Number of sync, tlbsync, and eieio commands from AC1 to AC0. (Group 2)", .pme_code = 0x17e7, /* 6119 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_TLBIE_2", .pme_desc = "Number of tlbie commands from AC1 to AC0. (Group 2)", .pme_code = 0x17e8, /* 6120 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_PAAM_CAM_HIT_2", .pme_desc = "PAAM CAM hit. (Group 2)", .pme_code = 0x17ef, /* 6127 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_PAAM_CAM_MISS_2", .pme_desc = "PAAM CAM miss. (Group 2)", .pme_code = 0x17f0, /* 6128 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_CMD_REFLECTED_2", .pme_desc = "Command reflected. (Group 2)", .pme_code = 0x17f2, /* 6130 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_LOCAL_CMD_FROM_SPE6", .pme_desc = "Local command from SPE 6.", .pme_code = 0x1839, /* 6201 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_LOCAL_CMD_FROM_SPE4", .pme_desc = "Local command from SPE 4.", .pme_code = 0x183a, /* 6202 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_LOCAL_CME_FROM_SPE2", .pme_desc = "Local command from SPE 2.", .pme_code = 0x183b, /* 6203 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_LOCAL_CMD_FROM_PPE", .pme_desc = "Local command from PPE.", .pme_code = 0x183d, /* 6205 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_LOCAL_CMD_FROM_SPE1", .pme_desc = "Local command from SPE 1.", .pme_code = 0x183e, /* 6206 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_LOCAL_CMD_FROM_SPE3", .pme_desc = "Local command from SPE 3.", .pme_code = 0x183f, /* 6207 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_LOCAL_CMD_FROM_SPE5", .pme_desc = "Local command from SPE 5.", .pme_code = 0x1840, /* 6208 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_LOCAL_CMD_FROM_SPE7", .pme_desc = "Local command from SPE 7.", .pme_code = 0x1841, /* 6209 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GLOBAL_CMD_FROM_SPE6", .pme_desc = "AC1-to-AC0 global command from SPE 6.", .pme_code = 0x1844, /* 6212 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GLOBAL_CMD_FROM_SPE4", .pme_desc = "AC1-to-AC0 global command from SPE 4.", .pme_code = 0x1845, /* 6213 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GLOBAL_CMD_FROM_SPE2", .pme_desc = "AC1-to-AC0 global command from SPE 2.", .pme_code = 0x1846, /* 6214 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GLOBAL_CMD_FROM_SPE0", .pme_desc = "AC1-to-AC0 global command from SPE 0.", .pme_code = 0x1847, /* 6215 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GLOBAL_CMD_FROM_PPE", .pme_desc = "AC1-to-AC0 global command from PPE.", .pme_code = 0x1848, /* 6216 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GLOBAL_CMD_FROM_SPE1", .pme_desc = "AC1-to-AC0 global command from SPE 1.", .pme_code = 0x1849, /* 6217 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GLOBAL_CMD_FROM_SPE3", .pme_desc = "AC1-to-AC0 global command from SPE 3.", .pme_code = 0x184a, /* 6218 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GLOBAL_CMD_FROM_SPE5", .pme_desc = "AC1-to-AC0 global command from SPE 5.", .pme_code = 0x184b, /* 6219 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GLOBAL_CMD_FROM_SPE7", .pme_desc = "AC1-to-AC0 global command from SPE 7", .pme_code = 0x184c, /* 6220 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_AC1_REFLECTING_LOCAL_CMD", .pme_desc = "AC1 is reflecting any local command.", .pme_code = 0x184e, /* 6222 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_AC1_SEND_GLOBAL_CMD", .pme_desc = "AC1 sends a global command to AC0.", .pme_code = 0x184f, /* 6223 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_AC0_REFLECT_GLOBAL_CMD", .pme_desc = "AC0 reflects a global command back to AC1.", .pme_code = 0x1850, /* 6224 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_AC1_REFLECT_CMD_TO_BM", .pme_desc = "AC1 reflects a command back to the bus masters.", .pme_code = 0x1851, /* 6225 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GRANT_DATA_RING0_1", .pme_desc = "Grant on data ring 0.", .pme_code = 0x189c, /* 6300 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GRANT_DATA_RING1_1", .pme_desc = "Grant on data ring 1.", .pme_code = 0x189d, /* 6301 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GRANT_DATA_RING2_1", .pme_desc = "Grant on data ring 2.", .pme_code = 0x189e, /* 6302 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GRANT_DATA_RING3_1", .pme_desc = "Grant on data ring 3.", .pme_code = 0x189f, /* 6303 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_DATA_RING0_INUSE_1", .pme_desc = "Data ring 0 is in use.", .pme_code = 0x18a0, /* 6304 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_DATA_RING1_INUSE_1", .pme_desc = "Data ring 1 is in use.", .pme_code = 0x18a1, /* 6305 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_DATA_RING2_INUSE_1", .pme_desc = "Data ring 2 is in use.", .pme_code = 0x18a2, /* 6306 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_DATA_RING3_INUSE_1", .pme_desc = "Data ring 3 is in use.", .pme_code = 0x18a3, /* 6307 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_ALL_DATA_RINGS_IDLE_1", .pme_desc = "All data rings are idle.", .pme_code = 0x18a4, /* 6308 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_ONE_DATA_RING_BUSY_1", .pme_desc = "One data ring is busy.", .pme_code = 0x18a5, /* 6309 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_TWO_OR_THREE_DATA_RINGS_BUSY_1", .pme_desc = "Two or three data rings are busy.", .pme_code = 0x18a6, /* 6310 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_ALL_DATA_RINGS_BUSY_1", .pme_desc = "All data rings are busy.", .pme_code = 0x18a7, /* 6311 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_IOIF0_DATA_REQ_PENDING_1", .pme_desc = "BIC(IOIF0) data request pending.", .pme_code = 0x18a8, /* 6312 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE6_DATA_REQ_PENDING_1", .pme_desc = "SPE 6 data request pending.", .pme_code = 0x18a9, /* 6313 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE4_DATA_REQ_PENDING_1", .pme_desc = "SPE 4 data request pending.", .pme_code = 0x18aa, /* 6314 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE2_DATA_REQ_PENDING_1", .pme_desc = "SPE 2 data request pending.", .pme_code = 0x18ab, /* 6315 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE0_DATA_REQ_PENDING_1", .pme_desc = "SPE 0 data request pending.", .pme_code = 0x18ac, /* 6316 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_MIC_DATA_REQ_PENDING_1", .pme_desc = "MIC data request pending.", .pme_code = 0x18ad, /* 6317 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_PPE_DATA_REQ_PENDING_1", .pme_desc = "PPE data request pending.", .pme_code = 0x18ae, /* 6318 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE1_DATA_REQ_PENDING_1", .pme_desc = "SPE 1 data request pending.", .pme_code = 0x18af, /* 6319 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE3_DATA_REQ_PENDING_1", .pme_desc = "SPE 3 data request pending.", .pme_code = 0x18b0, /* 6320 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE5_DATA_REQ_PENDING_1", .pme_desc = "SPE 5 data request pending.", .pme_code = 0x18b1, /* 6321 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE7_DATA_REQ_PENDING_1", .pme_desc = "SPE 7 data request pending.", .pme_code = 0x18b2, /* 6322 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_IOIF0_DATA_DEST_1", .pme_desc = "IOIF0 is data destination.", .pme_code = 0x18b4, /* 6324 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SPE6_DATA_DEST_1", .pme_desc = "SPE 6 is data destination.", .pme_code = 0x18b5, /* 6325 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SPE4_DATA_DEST_1", .pme_desc = "SPE 4 is data destination.", .pme_code = 0x18b6, /* 6326 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SPE2_DATA_DEST_1", .pme_desc = "SPE 2 is data destination.", .pme_code = 0x18b7, /* 6327 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SPE0_DATA_DEST_1", .pme_desc = "SPE 0 is data destination.", .pme_code = 0x18b8, /* 6328 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_MIC_DATA_DEST_1", .pme_desc = "MIC is data destination.", .pme_code = 0x18b9, /* 6329 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_PPE_DATA_DEST_1", .pme_desc = "PPE is data destination.", .pme_code = 0x18ba, /* 6330 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SPE1_DATA_DEST_1", .pme_desc = "SPE 1 is data destination.", .pme_code = 0x18bb, /* 6331 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_IOIF0_DATA_REQ_PENDING_2", .pme_desc = "BIC(IOIF0) data request pending.", .pme_code = 0x1900, /* 6400 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE6_DATA_REQ_PENDING_2", .pme_desc = "SPE 6 data request pending.", .pme_code = 0x1901, /* 6401 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE4_DATA_REQ_PENDING_2", .pme_desc = "SPE 4 data request pending.", .pme_code = 0x1902, /* 6402 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE2_DATA_REQ_PENDING_2", .pme_desc = "SPE 2 data request pending.", .pme_code = 0x1903, /* 6403 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE0_DATA_REQ_PENDING_2", .pme_desc = "SPE 0 data request pending.", .pme_code = 0x1904, /* 6404 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_MIC_DATA_REQ_PENDING_2", .pme_desc = "MIC data request pending.", .pme_code = 0x1905, /* 6405 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_PPE_DATA_REQ_PENDING_2", .pme_desc = "PPE data request pending.", .pme_code = 0x1906, /* 6406 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE1_DATA_REQ_PENDING_2", .pme_desc = "SPE 1 data request pending.", .pme_code = 0x1907, /* 6407 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE3_DATA_REQ_PENDING_2", .pme_desc = "SPE 3 data request pending.", .pme_code = 0x1908, /* 6408 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE5_DATA_REQ_PENDING_2", .pme_desc = "SPE 5 data request pending.", .pme_code = 0x1909, /* 6409 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_SPE7_DATA_REQ_PENDING_2", .pme_desc = "SPE 7 data request pending.", .pme_code = 0x190a, /* 6410 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_IOIF1_DATA_REQ_PENDING_2", .pme_desc = "IOIF1 data request pending.", .pme_code = 0x190b, /* 6411 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "EIB_IOIF0_DATA_DEST_2", .pme_desc = "IOIF0 is data destination.", .pme_code = 0x190c, /* 6412 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SPE6_DATA_DEST_2", .pme_desc = "SPE 6 is data destination.", .pme_code = 0x190d, /* 6413 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SPE4_DATA_DEST_2", .pme_desc = "SPE 4 is data destination.", .pme_code = 0x190e, /* 6414 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SPE2_DATA_DEST_2", .pme_desc = "SPE 2 is data destination.", .pme_code = 0x190f, /* 6415 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SPE0_DATA_DEST_2", .pme_desc = "SPE 0 is data destination.", .pme_code = 0x1910, /* 6416 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_MIC_DATA_DEST_2", .pme_desc = "MIC is data destination.", .pme_code = 0x1911, /* 6417 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_PPE_DATA_DEST_2", .pme_desc = "PPE is data destination.", .pme_code = 0x1912, /* 6418 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SPE1_DATA_DEST_2", .pme_desc = "SPE 1 is data destination.", .pme_code = 0x1913, /* 6419 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SPE3_DATA_DEST_2", .pme_desc = "SPE 3 is data destination.", .pme_code = 0x1914, /* 6420 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SPE5_DATA_DEST_2", .pme_desc = "SPE 5 is data destination.", .pme_code = 0x1915, /* 6421 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_SPE7_DATA_DEST_2", .pme_desc = "SPE 7 is data destination.", .pme_code = 0x1916, /* 6422 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_IOIF1_DATA_DEST_2", .pme_desc = "IOIF1 is data destination.", .pme_code = 0x1917, /* 6423 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GRANT_DATA_RING0_2", .pme_desc = "Grant on data ring 0.", .pme_code = 0x1918, /* 6424 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GRANT_DATA_RING1_2", .pme_desc = "Grant on data ring 1.", .pme_code = 0x1919, /* 6425 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GRANT_DATA_RING2_2", .pme_desc = "Grant on data ring 2.", .pme_code = 0x191a, /* 6426 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_GRANT_DATA_RING3_2", .pme_desc = "Grant on data ring 3.", .pme_code = 0x191b, /* 6427 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "EIB_ALL_DATA_RINGS_IDLE_2", .pme_desc = "All data rings are idle.", .pme_code = 0x191c, /* 6428 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_ONE_DATA_RING_BUSY_2", .pme_desc = "One data ring is busy.", .pme_code = 0x191d, /* 6429 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_TWO_OR_THREE_DATA_RINGS_BUSY_2", .pme_desc = "Two or three data rings are busy.", .pme_code = 0x191e, /* 6430 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_ALL_DATA_RINGS_BUSY_2", .pme_desc = "All four data rings are busy.", .pme_code = 0x191f, /* 6431 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_E_XIO_UNUSED", .pme_desc = "Even XIO token unused by RAG 0.", .pme_code = 0xfe4c, /* 65100 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_O_XIO_UNUSED", .pme_desc = "Odd XIO token unused by RAG 0.", .pme_code = 0xfe4d, /* 65101 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_E_BANK_UNUSED", .pme_desc = "Even bank token unused by RAG 0.", .pme_code = 0xfe4e, /* 65102 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_O_BANK_UNUSED", .pme_desc = "Odd bank token unused by RAG 0.", .pme_code = 0xfe4f, /* 65103 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_TOKEN_GRANTED_SPE0", .pme_desc = "Token granted for SPE 0.", .pme_code = 0xfe54, /* 65108 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_TOKEN_GRANTED_SPE1", .pme_desc = "Token granted for SPE 1.", .pme_code = 0xfe55, /* 65109 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_TOKEN_GRANTED_SPE2", .pme_desc = "Token granted for SPE 2.", .pme_code = 0xfe56, /* 65110 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_TOKEN_GRANTED_SPE3", .pme_desc = "Token granted for SPE 3.", .pme_code = 0xfe57, /* 65111 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_TOKEN_GRANTED_SPE4", .pme_desc = "Token granted for SPE 4.", .pme_code = 0xfe58, /* 65112 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_TOKEN_GRANTED_SPE5", .pme_desc = "Token granted for SPE 5.", .pme_code = 0xfe59, /* 65113 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_TOKEN_GRANTED_SPE6", .pme_desc = "Token granted for SPE 6.", .pme_code = 0xfe5a, /* 65114 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_TOKEN_GRANTED_SPE7", .pme_desc = "Token granted for SPE 7.", .pme_code = 0xfe5b, /* 65115 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_E_XIO_WASTED", .pme_desc = "Even XIO token wasted by RAG 0; valid only when Unused Enable (UE) = 1 in TKM_CR register.", .pme_code = 0xfeb0, /* 65200 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_O_XIO_WASTED", .pme_desc = "Odd XIO token wasted by RAG 0; valid only when Unused Enable (UE) = 1 in TKM_CR register.", .pme_code = 0xfeb1, /* 65201 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_E_BANK_WASTED", .pme_desc = "Even bank token wasted by RAG 0; valid only when Unused Enable (UE) = 1 in TKM_CR register.", .pme_code = 0xfeb2, /* 65202 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_O_BANK_WASTED", .pme_desc = "Odd bank token wasted by RAG 0; valid only when Unused Enable (UE) = 1 in TKM_CR register.", .pme_code = 0xfeb3, /* 65203 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAGU_E_XIO_WASTED", .pme_desc = "Even XIO token wasted by RAG U.", .pme_code = 0xfebc, /* 65212 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAGU_O_XIO_WASTED", .pme_desc = "Odd XIO token wasted by RAG U.", .pme_code = 0xfebd, /* 65213 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAGU_E_BANK_WASTED", .pme_desc = "Even bank token wasted by RAG U.", .pme_code = 0xfebe, /* 65214 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAGU_O_BANK_WASTED", .pme_desc = "Odd bank token wasted by RAG U.", .pme_code = 0xfebf, /* 65215 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_E_XIO_RAG1", .pme_desc = "Even XIO token from RAG 0 shared with RAG 1", .pme_code = 0xff14, /* 65300 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_E_XIO_RAG2", .pme_desc = "Even XIO token from RAG 0 shared with RAG 2", .pme_code = 0xff15, /* 65301 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_E_XIO_RAG3", .pme_desc = "Even XIO token from RAG 0 shared with RAG 3", .pme_code = 0xff16, /* 65302 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_O_XIO_RAG1", .pme_desc = "Odd XIO token from RAG 0 shared with RAG 1", .pme_code = 0xff17, /* 65303 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_O_XIO_RAG2", .pme_desc = "Odd XIO token from RAG 0 shared with RAG 2", .pme_code = 0xff18, /* 65304 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_O_XIO_RAG3", .pme_desc = "Odd XIO token from RAG 0 shared with RAG 3", .pme_code = 0xff19, /* 65305 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_E_BANK_RAG1", .pme_desc = "Even bank token from RAG 0 shared with RAG 1", .pme_code = 0xff1a, /* 65306 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_E_BANK_RAG2", .pme_desc = "Even bank token from RAG 0 shared with RAG 2", .pme_code = 0xff1b, /* 65307 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_E_BANK_RAG3", .pme_desc = "Even bank token from RAG 0 shared with RAG 3", .pme_code = 0xff1c, /* 65308 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_O_BANK_RAG1", .pme_desc = "Odd bank token from RAG 0 shared with RAG 1", .pme_code = 0xff1d, /* 65309 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_O_BANK_RAG2", .pme_desc = "Odd bank token from RAG 0 shared with RAG 2", .pme_code = 0xff1e, /* 65310 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_O_BANK_RAG3", .pme_desc = "Odd bank token from RAG 0 shared with RAG 3", .pme_code = 0xff1f, /* 65311 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_E_XIO_UNUSED", .pme_desc = "Even XIO token was unused by RAG 1.", .pme_code = 0xff88, /* 65416 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_O_XIO_UNUSED", .pme_desc = "Odd XIO token was unused by RAG 1.", .pme_code = 0xff89, /* 65417 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_E_BANK_UNUSED", .pme_desc = "Even bank token was unused by RAG 1.", .pme_code = 0xff8a, /* 65418 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_O_BANK_UNUSED", .pme_desc = "Odd bank token was unused by RAG 1.", .pme_code = 0xff8b, /* 65419 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_TOKEN_GRANTED_IOC0", .pme_desc = "Token was granted for IOC0.", .pme_code = 0xff91, /* 65425 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_TOKEN_GRANTED_IOC1", .pme_desc = "Token was granted for IOC1.", .pme_code = 0xff92, /* 65426 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_E_XIO_WASTED", .pme_desc = "Even XIO token was wasted by RAG 1. This is valid only when UE = 1 in TKM_CR.", .pme_code = 0xffec, /* 65516 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_O_XIO_WASTED", .pme_desc = "Odd XIO token was wasted by RAG 1. This is valid only when UE = 1 in TKM_CR.", .pme_code = 0xffed, /* 65517 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_E_BANK_WASTED", .pme_desc = "Even bank token was wasted by RAG 1. This is valid only when UE = 1 in TKM_CR.", .pme_code = 0xffee, /* 65518 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_O_BANK_WASTED", .pme_desc = "Odd bank token was wasted by RAG 1. This is valid only when UE = 1 in TKM_CR.", .pme_code = 0xffef, /* 65519 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_E_XIO_RAG0", .pme_desc = "Even XIO token from RAG 1 shared with RAG 0", .pme_code = 0x10050, /* 65616 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_E_XIO_RAG2", .pme_desc = "Even XIO token from RAG 1 shared with RAG 2", .pme_code = 0x10051, /* 65617 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_E_XIO_RAG3", .pme_desc = "Even XIO token from RAG 1 shared with RAG 3", .pme_code = 0x10052, /* 65618 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_O_XIO_RAG0", .pme_desc = "Odd XIO token from RAG 1 shared with RAG 0", .pme_code = 0x10053, /* 65619 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_O_XIO_RAG2", .pme_desc = "Odd XIO token from RAG 1 shared with RAG 2", .pme_code = 0x10054, /* 65620 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_O_XIO_RAG3", .pme_desc = "Odd XIO token from RAG 1 shared with RAG 3", .pme_code = 0x10055, /* 65621 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_E_BANK_RAG0", .pme_desc = "Even bank token from RAG 1 shared with RAG 0", .pme_code = 0x10056, /* 65622 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_E_BANK_RAG2", .pme_desc = "Even bank token from RAG 1 shared with RAG 2", .pme_code = 0x10057, /* 65623 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_E_BANK_RAG3", .pme_desc = "Even bank token from RAG 1 shared with RAG 3", .pme_code = 0x10058, /* 65624 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_O_BANK_RAG0", .pme_desc = "Odd bank token from RAG 1 shared with RAG 0", .pme_code = 0x10059, /* 65625 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_O_BANK_RAG2", .pme_desc = "Odd bank token from RAG 1 shared with RAG 2", .pme_code = 0x1005a, /* 65626 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG1_O_BANK_RAG3", .pme_desc = "Odd bank token from RAG 1 shared with RAG 3", .pme_code = 0x1005b, /* 65627 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAGU_E_XIO_RAG1", .pme_desc = "Even XIO token from RAG U shared with RAG 1", .pme_code = 0x1005c, /* 65628 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAGU_O_XIO_RAG1", .pme_desc = "Odd XIO token from RAG U shared with RAG 1", .pme_code = 0x1005d, /* 65629 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAGU_E_BANK_RAG1", .pme_desc = "Even bank token from RAG U shared with RAG 1", .pme_code = 0x1005e, /* 65630 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAGU_O_BANK_RAG1", .pme_desc = "Odd bank token from RAG U shared with RAG 1", .pme_code = 0x1005f, /* 65631 */ .pme_enable_word = WORD_0_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_E_XIO_UNUSED", .pme_desc = "Even XIO token unused by RAG 2", .pme_code = 0x100e4, /* 65764 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_O_XIO_UNUSED", .pme_desc = "Odd XIO token unused by RAG 2", .pme_code = 0x100e5, /* 65765 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_E_BANK_UNUSED", .pme_desc = "Even bank token unused by RAG 2", .pme_code = 0x100e6, /* 65766 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_O_BANK_UNUSED", .pme_desc = "Odd bank token unused by RAG 2", .pme_code = 0x100e7, /* 65767 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_IOIF0_IN_TOKEN_UNUSED", .pme_desc = "IOIF0 In token unused by RAG 0", .pme_code = 0x100e8, /* 65768 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_IOIF0_OUT_TOKEN_UNUSED", .pme_desc = "IOIF0 Out token unused by RAG 0", .pme_code = 0x100e9, /* 65769 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_IOIF1_IN_TOKEN_UNUSED", .pme_desc = "IOIF1 In token unused by RAG 0", .pme_code = 0x100ea, /* 65770 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_IOIF1_OUT_TOKEN_UNUSED", .pme_desc = "IOIF1 Out token unused by RAG 0", .pme_code = 0x100eb, /* 65771 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_E_XIO_WASTED", .pme_desc = "Even XIO token wasted by RAG 2", .pme_code = 0x10148, /* 65864 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_O_XIO_WASTED", .pme_desc = "Odd XIO token wasted by RAG 2", .pme_code = 0x10149, /* 65865 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_E_BANK_WASTED", .pme_desc = "Even bank token wasted by RAG 2", .pme_code = 0x1014a, /* 65866 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_O_BANK_WASTED", .pme_desc = "Odd bank token wasted by RAG 2", .pme_code = 0x1014b, /* 65867 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_E_XIO_RAG0", .pme_desc = "Even XIO token from RAG 2 shared with RAG 0", .pme_code = 0x101ac, /* 65964 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_E_XIO_RAG1", .pme_desc = "Even XIO token from RAG 2 shared with RAG 1", .pme_code = 0x101ad, /* 65965 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_E_XIO_RAG3", .pme_desc = "Even XIO token from RAG 2 shared with RAG 3", .pme_code = 0x101ae, /* 65966 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_O_XIO_RAG0", .pme_desc = "Odd XIO token from RAG 2 shared with RAG 0", .pme_code = 0x101af, /* 65967 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_O_XIO_RAG1", .pme_desc = "Odd XIO token from RAG 2 shared with RAG 1", .pme_code = 0x101b0, /* 65968 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_O_XIO_RAG3", .pme_desc = "Odd XIO token from RAG 2 shared with RAG 3", .pme_code = 0x101b1, /* 65969 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_E_BANK_RAG0", .pme_desc = "Even bank token from RAG 2 shared with RAG 0", .pme_code = 0x101b2, /* 65970 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_E_BANK_RAG1", .pme_desc = "Even bank token from RAG 2 shared with RAG 1", .pme_code = 0x101b3, /* 65971 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_E_BANK_RAG3", .pme_desc = "Even bank token from RAG 2 shared with RAG 3", .pme_code = 0x101b4, /* 65972 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_O_BANK_RAG0", .pme_desc = "Odd bank token from RAG 2 shared with RAG 0", .pme_code = 0x101b5, /* 65973 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_O_BANK_RAG1", .pme_desc = "Odd bank token from RAG 2 shared with RAG 1", .pme_code = 0x101b6, /* 65974 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG2_O_BANK_RAG3", .pme_desc = "Odd bank token from RAG 2 shared with RAG 3", .pme_code = 0x101b7, /* 65975 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_IOIF0_IN_TOKEN_WASTED", .pme_desc = "IOIF0 In token wasted by RAG 0", .pme_code = 0x9ef38, /* 651064 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_IOIF0_OUT_TOKEN_WASTED", .pme_desc = "IOIF0 Out token wasted by RAG 0", .pme_code = 0x9ef39, /* 651065 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_IOIF1_IN_TOKEN_WASTED", .pme_desc = "IOIF1 In token wasted by RAG 0", .pme_code = 0x9ef3a, /* 651066 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG0_IOIF1_OUT_TOKEN_WASTED", .pme_desc = "IOIF1 Out token wasted by RAG 0", .pme_code = 0x9ef3b, /* 651067 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_E_XIO_UNUSED", .pme_desc = "Even XIO token was unused by RAG 3.", .pme_code = 0x9efac, /* 651180 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_O_XIO_UNUSED", .pme_desc = "Odd XIO token was unused by RAG 3.", .pme_code = 0x9efad, /* 651181 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_E_BANK_UNUSED", .pme_desc = "Even bank token was unused by RAG 3.", .pme_code = 0x9efae, /* 651182 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_O_BANK_UNUSED", .pme_desc = "Odd bank token was unused by RAG 3.", .pme_code = 0x9efaf, /* 651183 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_E_XIO_WASTED", .pme_desc = "Even XIO token wasted by RAG 3", .pme_code = 0x9f010, /* 651280 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_O_XIO_WASTED", .pme_desc = "Odd XIO token wasted by RAG 3", .pme_code = 0x9f011, /* 651281 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_E_BANK_WASTED", .pme_desc = "Even bank token wasted by RAG 3", .pme_code = 0x9f012, /* 651282 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_O_BANK_WASTED", .pme_desc = "Odd bank token wasted by RAG 3", .pme_code = 0x9f013, /* 651283 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_E_XIO_RAG0", .pme_desc = "Even XIO token from RAG 3 shared with RAG 0", .pme_code = 0x9f074, /* 651380 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_E_XIO_RAG1", .pme_desc = "Even XIO token from RAG 3 shared with RAG 1", .pme_code = 0x9f075, /* 651381 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_E_XIO_RAG2", .pme_desc = "Even XIO token from RAG 3 shared with RAG 2", .pme_code = 0x9f076, /* 651382 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_O_XIO_RAG0", .pme_desc = "Odd XIO token from RAG 3 shared with RAG 0", .pme_code = 0x9f077, /* 651383 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_O_XIO_RAG1", .pme_desc = "Odd XIO token from RAG 3 shared with RAG 1", .pme_code = 0x9f078, /* 651384 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_O_XIO_RAG2", .pme_desc = "Odd XIO token from RAG 3 shared with RAG 2", .pme_code = 0x9f079, /* 651385 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_E_BANK_RAG0", .pme_desc = "Even bank token from RAG 3 shared with RAG 0", .pme_code = 0x9f07a, /* 651386 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_E_BANK_RAG1", .pme_desc = "Even bank token from RAG 3 shared with RAG 1", .pme_code = 0x9f07b, /* 651387 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_E_BANK_RAG2", .pme_desc = "Even bank token from RAG 3 shared with RAG 2", .pme_code = 0x9f07c, /* 651388 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_O_BANK_RAG0", .pme_desc = "Odd bank token from RAG 3 shared with RAG 0", .pme_code = 0x9f07d, /* 651389 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_O_BANK_RAG1", .pme_desc = "Odd bank token from RAG 3 shared with RAG 1", .pme_code = 0x9f07e, /* 651390 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "EIB_RAG3_O_BANK_RAG2", .pme_desc = "Odd bank token from RAG 3 shared with RAG 2", .pme_code = 0x9f07f, /* 651391 */ .pme_enable_word = WORD_2_ONLY, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO1_READ_CMD_Q_EMPTY", .pme_desc = "XIO1 - Read command queue is empty.", .pme_code = 0x1bc5, /* 7109 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO1_WRITE_CMD_Q_EMPTY", .pme_desc = "XIO1 - Write command queue is empty.", .pme_code = 0x1bc6, /* 7110 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO1_READ_CMD_Q_FULL", .pme_desc = "XIO1 - Read command queue is full.", .pme_code = 0x1bc8, /* 7112 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO1_RESPONDS_READ_RETRY", .pme_desc = "XIO1 - MIC responds with a Retry for a read command because the read command queue is full.", .pme_code = 0x1bc9, /* 7113 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO1_WRITE_CMD_Q_FULL", .pme_desc = "XIO1 - Write command queue is full.", .pme_code = 0x1bca, /* 7114 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO1_RESPONDS_WRITE_RETRY", .pme_desc = "XIO1 - MIC responds with a Retry for a write command because the write command queue is full.", .pme_code = 0x1bcb, /* 7115 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO1_READ_CMD_DISPATCHED", .pme_desc = "XIO1 - Read command dispatched; includes high-priority and fast-path reads.", .pme_code = 0x1bde, /* 7134 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO1_WRITE_CMD_DISPATCHED", .pme_desc = "XIO1 - Write command dispatched.", .pme_code = 0x1bdf, /* 7135 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO1_READ_MOD_WRITE_CMD_DISPATCHED", .pme_desc = "XIO1 - Read-Modify-Write command (data size < 16 bytes) dispatched.", .pme_code = 0x1be0, /* 7136 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO1_REFRESH_DISPATCHED", .pme_desc = "XIO1 - Refresh dispatched.", .pme_code = 0x1be1, /* 7137 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO1_BYTE_MSK_WRITE_CMD_DISPATCHED", .pme_desc = "XIO1 - Byte-masking write command (data size >= 16 bytes) dispatched.", .pme_code = 0x1be3, /* 7139 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO1_WRITE_CMD_DISPATCHED_AFTER_READ", .pme_desc = "XIO1 - Write command dispatched after a read command was previously dispatched.", .pme_code = 0x1be5, /* 7141 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO1_READ_CMD_DISPATCHED_AFTER_WRITE", .pme_desc = "XIO1 - Read command dispatched after a write command was previously dispatched.", .pme_code = 0x1be6, /* 7142 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_READ_CMD_Q_EMPTY", .pme_desc = "XIO0 - Read command queue is empty.", .pme_code = 0x1c29, /* 7209 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_WRITE_CMD_Q_EMPTY", .pme_desc = "XIO0 - Write command queue is empty.", .pme_code = 0x1c2a, /* 7210 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_READ_CMD_Q_FULL", .pme_desc = "XIO0 - Read command queue is full.", .pme_code = 0x1c2c, /* 7212 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_RESPONDS_READ_RETRY", .pme_desc = "XIO0 - MIC responds with a Retry for a read command because the read command queue is full.", .pme_code = 0x1c2d, /* 7213 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_WRITE_CMD_Q_FULL", .pme_desc = "XIO0 - Write command queue is full.", .pme_code = 0x1c2e, /* 7214 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_RESPONDS_WRITE_RETRY", .pme_desc = "XIO0 - MIC responds with a Retry for a write command because the write command queue is full.", .pme_code = 0x1c2f, /* 7215 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_READ_CMD_DISPATCHED", .pme_desc = "XIO0 - Read command dispatched; includes high-priority and fast-path reads.", .pme_code = 0x1c42, /* 7234 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_WRITE_CMD_DISPATCHED", .pme_desc = "XIO0 - Write command dispatched.", .pme_code = 0x1c43, /* 7235 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_READ_MOD_WRITE_CMD_DISPATCHED", .pme_desc = "XIO0 - Read-Modify-Write command (data size < 16 bytes) dispatched.", .pme_code = 0x1c44, /* 7236 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_REFRESH_DISPATCHED", .pme_desc = "XIO0 - Refresh dispatched.", .pme_code = 0x1c45, /* 7237 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_WRITE_CMD_DISPATCHED_AFTER_READ", .pme_desc = "XIO0 - Write command dispatched after a read command was previously dispatched.", .pme_code = 0x1c49, /* 7241 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_READ_CMD_DISPATCHED_AFTER_WRITE", .pme_desc = "XIO0 - Read command dispatched after a write command was previously dispatched.", .pme_code = 0x1c4a, /* 7242 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_WRITE_CMD_DISPATCHED_2", .pme_desc = "XIO0 - Write command dispatched.", .pme_code = 0x1ca7, /* 7335 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_READ_MOD_WRITE_CMD_DISPATCHED_2", .pme_desc = "XIO0 - Read-Modify-Write command (data size < 16 bytes) dispatched.", .pme_code = 0x1ca8, /* 7336 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_REFRESH_DISPATCHED_2", .pme_desc = "XIO0 - Refresh dispatched.", .pme_code = 0x1ca9, /* 7337 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "MIC_XIO0_BYTE_MSK_WRITE_CMD_DISPATCHED", .pme_desc = "XIO0 - Byte-masking write command (data size >= 16 bytes) dispatched.", .pme_code = 0x1cab, /* 7339 */ .pme_enable_word = 0xF, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_TYPEA_DATA_PLG", .pme_desc = "Type A data physical layer group (PLG). Does not include header-only or credit-only data PLGs. In IOIF mode, counts I/O device read data; in BIF mode, counts all outbound data.", .pme_code = 0x1fb0, /* 8112 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_TYPEB_DATA_PLG", .pme_desc = "Type B data PLG. In IOIF mode, counts I/O device read data; in BIF mode, counts all outbound data.", .pme_code = 0x1fb1, /* 8113 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_IOIF_TYPEA_DATA_PLG", .pme_desc = "Type A data PLG. Does not include header-only or credit-only PLGs. In IOIF mode, counts CBE store data to I/O device. Does not apply in BIF mode.", .pme_code = 0x1fb2, /* 8114 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_IOIF_TYPEB_DATA_PLG", .pme_desc = "Type B data PLG. In IOIF mode, counts CBE store data to an I/O device. Does not apply in BIF mode.", .pme_code = 0x1fb3, /* 8115 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_DATA_PLG", .pme_desc = "Data PLG. Does not include header-only or credit-only PLGs.", .pme_code = 0x1fb4, /* 8116 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_CMD_PLG", .pme_desc = "Command PLG (no credit-only PLG). In IOIF mode, counts I/O command or reply PLGs. In BIF mode, counts command/ reflected command or snoop/combined responses.", .pme_code = 0x1fb5, /* 8117 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_TYPEA_TRANSFER", .pme_desc = "Type A data transfer regardless of length. Can also be used to count Type A data header PLGs (but not credit-only PLGs).", .pme_code = 0x1fb6, /* 8118 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_TYPEB_TRANSFER", .pme_desc = "Type B data transfer.", .pme_code = 0x1fb7, /* 8119 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_CMD_GREDIT_ONLY_PLG", .pme_desc = "Command-credit-only command PLG in either IOIF or BIF mode.", .pme_code = 0x1fb8, /* 8120 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_DATA_CREDIT_ONLY_PLG", .pme_desc = "Data-credit-only data PLG sent in either IOIF or BIF mode.", .pme_code = 0x1fb9, /* 8121 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_NON_NULL_ENVLP_SENT", .pme_desc = "Non-null envelope sent (does not include long envelopes).", .pme_code = 0x1fba, /* 8122 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_NULL_ENVLP_SENT", .pme_desc = "Null envelope sent.", .pme_code = 0x1fbc, /* 8124 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BIF_IOIF0_NO_VALID_DATA_SENT", .pme_desc = "No valid data sent this cycle.", .pme_code = 0x1fbd, /* 8125 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BIF_IOIF0_NORMAL_ENVLP_SENT", .pme_desc = "Normal envelope sent.", .pme_code = 0x1fbe, /* 8126 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BIF_IOIF0_LONG_ENVLP_SENT", .pme_desc = "Long envelope sent.", .pme_code = 0x1fbf, /* 8127 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BIF_IOIF0_NULL_PLG_INSERTED", .pme_desc = "A Null PLG inserted in an outgoing envelope.", .pme_code = 0x1fc0, /* 8128 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BIF_IOIF0_OUTBOUND_ENV_ARRAY_FULL", .pme_desc = "Outbound envelope array is full.", .pme_code = 0x1fc1, /* 8129 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF1_TYPEB_TRANSFER", .pme_desc = "Type B data transfer.", .pme_code = 0x201b, /* 8219 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_NULL_ENVLP_RECV", .pme_desc = "Null envelope received.", .pme_code = 0x206d, /* 8301 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BIF_IOIF0_CMD_PLG_2", .pme_desc = "Command PLG, but not credit-only PLG. In IOIF mode, counts I/O command or reply PLGs. In BIF mode, counts command/reflected command or snoop/combined responses.", .pme_code = 0x207a, /* 8314 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_CMD_GREDIT_ONLY_PLG_2", .pme_desc = "Command-credit-only command PLG.", .pme_code = 0x207b, /* 8315 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_NORMAL_ENVLP_RECV", .pme_desc = "Normal envelope received is good.", .pme_code = 0x2080, /* 8320 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BIF_IOIF0_LONG_ENVLP_RECV", .pme_desc = "Long envelope received is good.", .pme_code = 0x2081, /* 8321 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BIF_IOIF0_DATA_GREDIT_ONLY_PLG_2", .pme_desc = "Data-credit-only data PLG in either IOIF or BIF mode; will count a maximum of one per envelope.", .pme_code = 0x2082, /* 8322 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_NON_NULL_ENVLP", .pme_desc = "Non-null envelope; does not include long envelopes; includes retried envelopes.", .pme_code = 0x2083, /* 8323 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_DATA_GRANT_RECV", .pme_desc = "Data grant received.", .pme_code = 0x2084, /* 8324 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_DATA_PLG_2", .pme_desc = "Data PLG. Does not include header-only or credit-only PLGs.", .pme_code = 0x2088, /* 8328 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_TYPEA_TRANSFER_2", .pme_desc = "Type A data transfer regardless of length. Can also be used to count Type A data header PLGs, but not credit-only PLGs.", .pme_code = 0x2089, /* 8329 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF0_TYPEB_TRANSFER_2", .pme_desc = "Type B data transfer.", .pme_code = 0x208a, /* 8330 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF1_NULL_ENVLP_RECV", .pme_desc = "Null envelope received.", .pme_code = 0x20d1, /* 8401 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BIF_IOIF1_CMD_PLG_2", .pme_desc = "Command PLG (no credit-only PLG). Counts I/O command or reply PLGs.", .pme_code = 0x20de, /* 8414 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF1_CMD_GREDIT_ONLY_PLG_2", .pme_desc = "Command-credit-only command PLG.", .pme_code = 0x20df, /* 8415 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF1_NORMAL_ENVLP_RECV", .pme_desc = "Normal envelope received is good.", .pme_code = 0x20e4, /* 8420 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BIF_IOIF1_LONG_ENVLP_RECV", .pme_desc = "Long envelope received is good.", .pme_code = 0x20e5, /* 8421 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "BIF_IOIF1_DATA_GREDIT_ONLY_PLG_2", .pme_desc = "Data-credit-only data PLG received; will count a maximum of one per envelope.", .pme_code = 0x20e6, /* 8422 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF1_NON_NULL_ENVLP", .pme_desc = "Non-Null envelope received; does not include long envelopes; includes retried envelopes.", .pme_code = 0x20e7, /* 8423 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF1_DATA_GRANT_RECV", .pme_desc = "Data grant received.", .pme_code = 0x20e8, /* 8424 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF1_DATA_PLG_2", .pme_desc = "Data PLG received. Does not include header-only or credit-only PLGs.", .pme_code = 0x20ec, /* 8428 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF1_TYPEA_TRANSFER_2", .pme_desc = "Type I A data transfer regardless of length. Can also be used to count Type A data header PLGs (but not credit-only PLGs).", .pme_code = 0x20ed, /* 8429 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "BIF_IOIF1_TYPEB_TRANSFER_2", .pme_desc = "Type B data transfer received.", .pme_code = 0x20ee, /* 8430 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "IOC_MMIO_READ_IOIF1", .pme_desc = "Received MMIO read targeted to IOIF1.", .pme_code = 0x213c, /* 8508 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_MMIO_WRITE_IOIF1", .pme_desc = "Received MMIO write targeted to IOIF1.", .pme_code = 0x213d, /* 8509 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_MMIO_READ_IOIF0", .pme_desc = "Received MMIO read targeted to IOIF0.", .pme_code = 0x213e, /* 8510 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_MMIO_WRITE_IOIF0", .pme_desc = "Received MMIO write targeted to IOIF0.", .pme_code = 0x213f, /* 8511 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_CMD_TO_IOIF0", .pme_desc = "Sent command to IOIF0.", .pme_code = 0x2140, /* 8512 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "IOC_CMD_TO_IOIF1", .pme_desc = "Sent command to IOIF1.", .pme_code = 0x2141, /* 8513 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "IOC_IOIF0_MATRIX3_OCCUPIED", .pme_desc = "IOIF0 Dependency Matrix 3 is occupied by a dependent command.", .pme_code = 0x219d, /* 8605 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "IOC_IOIF0_MATRIX4_OCCUPIED", .pme_desc = "IOIF0 Dependency Matrix 4 is occupied by a dependent command.", .pme_code = 0x219e, /* 8606 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "IOC_IOIF0_MATRIX5_OCCUPIED", .pme_desc = "IOIF0 Dependency Matrix 5 is occupied by a dependent command.", .pme_code = 0x219f, /* 8607 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_BOTH_TYPE, }, {.pme_name = "IOC_DMA_READ_IOIF0", .pme_desc = "Received read request from IOIF0.", .pme_code = 0x21a2, /* 8610 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_DMA_WRITE_IOIF0", .pme_desc = "Received write request from IOIF0.", .pme_code = 0x21a3, /* 8611 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_INTERRUPT_IOIF0", .pme_desc = "Received interrupt from the IOIF0.", .pme_code = 0x21a6, /* 8614 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_IOIF0_REQ_TOKEN_E_MEM", .pme_desc = "IOIF0 request for token for even memory banks 0-14.", .pme_code = 0x220c, /* 8716 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "IOC_IOIF0_REQ_TOKEN_O_MEM", .pme_desc = "IOIF0 request for token for odd memory banks 1-15.", .pme_code = 0x220d, /* 8717 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "IOC_IOIF0_REQ_TOKEN_1357", .pme_desc = "IOIF0 request for token type 1, 3, 5, or 7.", .pme_code = 0x220e, /* 8718 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "IOC_IOIF0_REQ_TOKEN_9111315", .pme_desc = "IOIF0 request for token type 9, 11, 13, or 15.", .pme_code = 0x220f, /* 8719 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "IOC_IOIF0_REQ_TOKEN_16", .pme_desc = "IOIF0 request for token type 16.", .pme_code = 0x2214, /* 8724 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "IOC_IOIF0_REQ_TOKEN_17", .pme_desc = "IOIF0 request for token type 17.", .pme_code = 0x2215, /* 8725 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "IOC_IOIF0_REQ_TOKEN_18", .pme_desc = "IOIF0 request for token type 18.", .pme_code = 0x2216, /* 8726 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "IOC_IOIF0_REQ_TOKEN_19", .pme_desc = "IOIF0 request for token type 19.", .pme_code = 0x2217, /* 8727 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_CUMULATIVE_LEN, }, {.pme_name = "IOC_IOPT_CACHE_HIT", .pme_desc = "I/O page table cache hit for commands from IOIF.", .pme_code = 0x2260, /* 8800 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_IOPT_CACHE_MISS", .pme_desc = "I/O page table cache miss for commands from IOIF.", .pme_code = 0x2261, /* 8801 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_IOST_CACHE_HIT", .pme_desc = "I/O segment table cache hit.", .pme_code = 0x2263, /* 8803 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_IOST_CACHE_MISS", .pme_desc = "I/O segment table cache miss.", .pme_code = 0x2264, /* 8804 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_INTERRUPT_FROM_SPU", .pme_desc = "Interrupt received from any SPU (reflected cmd when IIC has sent ACK response).", .pme_code = 0x2278, /* 8824 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_IIC_INTERRUPT_TO_PPU_TH0", .pme_desc = "Internal interrupt controller (IIC) generated interrupt to PPU thread 0.", .pme_code = 0x2279, /* 8825 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_IIC_INTERRUPT_TO_PPU_TH1", .pme_desc = "IIC generated interrupt to PPU thread 1.", .pme_code = 0x227a, /* 8826 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_RECV_EXTERNAL_INTERRUPT_TO_TH0", .pme_desc = "Received external interrupt (using MMIO) from PPU to PPU thread 0.", .pme_code = 0x227b, /* 8827 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, {.pme_name = "IOC_RECV_EXTERNAL_INTERRUPT_TO_TH1", .pme_desc = "Received external interrupt (using MMIO) from PPU to PPU thread 1.", .pme_code = 0x227c, /* 8828 */ .pme_enable_word = WORD_0_AND_2, .pme_freq = PFM_CELL_PME_FREQ_HALF, .pme_type = COUNT_TYPE_OCCURRENCE, }, }; /*--- The number of events : 435 ---*/ #define PME_CELL_EVENT_COUNT (sizeof(cell_pe)/sizeof(pme_cell_entry_t)) papi-5.5.1/src/libpfm-3.y/lib/Makefile0000644000307100002310000001602613013651450017335 0ustar yarkhangraduate# # Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. # Contributed by Stephane Eranian # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies # of the Software, and to permit persons to whom the Software is furnished to do so, # subject to the following conditions: # # The above copyright notice and this permission notice shall be included in all # copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, # INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A # PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT # HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE # OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # TOPDIR := $(shell if [ "$$PWD" != "" ]; then echo $$PWD; else pwd; fi)/.. include $(TOPDIR)/config.mk include $(TOPDIR)/rules.mk # # Common files # SRCS=pfmlib_common.c pfmlib_priv.c ifeq ($(SYS),Linux) SRCS += pfmlib_os_linux.c pfmlib_os_linux_v2.c ifneq ($(CONFIG_PFMLIB_OLD_PFMV2),y) SRCS += pfmlib_os_linux_v3.c endif endif ifeq ($(SYS),Darwin) SRCS += pfmlib_os_macos.c endif CFLAGS+=-D_REENTRANT # # list all library support modules # ifeq ($(CONFIG_PFMLIB_ARCH_IA64),y) INCARCH = $(INC_IA64) SRCS += pfmlib_gen_ia64.c pfmlib_itanium.c pfmlib_itanium2.c pfmlib_montecito.c CFLAGS += -DCONFIG_PFMLIB_ARCH_IA64 endif ifeq ($(CONFIG_PFMLIB_ARCH_I386),y) INCARCH = $(INC_IA32) SRCS += pfmlib_i386_p6.c pfmlib_pentium4.c pfmlib_amd64.c pfmlib_core.c pfmlib_gen_ia32.c \ pfmlib_intel_atom.c pfmlib_intel_nhm.c pfmlib_coreduo.c CFLAGS += -DCONFIG_PFMLIB_ARCH_I386 endif ifeq ($(CONFIG_PFMLIB_ARCH_X86_64),y) INCARCH = $(INC_X86_64) SRCS += pfmlib_pentium4.c pfmlib_amd64.c pfmlib_core.c pfmlib_gen_ia32.c pfmlib_intel_atom.c \ pfmlib_intel_nhm.c CFLAGS += -DCONFIG_PFMLIB_ARCH_X86_64 endif ifeq ($(CONFIG_PFMLIB_ARCH_MIPS64),y) INCARCH = $(INC_MIPS64) SRCS += pfmlib_gen_mips64.c CFLAGS += -DCONFIG_PFMLIB_ARCH_MIPS64 ifeq ($(CONFIG_PFMLIB_ARCH_SICORTEX),y) INCARCH = $(INC_SICORTEX) CFLAGS += -DCONFIG_PFMLIB_ARCH_SICORTEX ifneq ($(SCINCDIR),) CFLAGS += -I$(SCINCDIR) endif SRCS += pfmlib_sicortex.c endif endif ifeq ($(CONFIG_PFMLIB_ARCH_POWERPC),y) INCARCH = $(INC_POWERPC) SRCS += pfmlib_gen_powerpc.c CFLAGS += -DCONFIG_PFMLIB_ARCH_POWERPC endif ifeq ($(CONFIG_PFMLIB_ARCH_SPARC),y) INCARCH = $(INC_SPARC) SRCS += pfmlib_sparc.c CFLAGS += -DCONFIG_PFMLIB_ARCH_SPARC endif ifeq ($(CONFIG_PFMLIB_ARCH_CRAYX2),y) INCARCH = $(INC_CRAYX2) SRCS += pfmlib_crayx2.c CFLAGS += -DCONFIG_PFMLIB_ARCH_CRAYX2 endif ifeq ($(CONFIG_PFMLIB_ARCH_CRAYXT),y) CFLAGS += -DCONFIG_PFMLIB_ARCH_CRAYXT endif ifeq ($(CONFIG_PFMLIB_CELL),y) INCARCH = $(INC_CELL) SRCS += pfmlib_cell.c CFLAGS += -DCONFIG_PFMLIB_CELL endif ifeq ($(SYS),Linux) SLDFLAGS=-shared -Wl,-soname -Wl,$(VLIBPFM) SLIBPFM=libpfm.so.$(VERSION).$(REVISION).$(AGE) VLIBPFM=libpfm.so.$(VERSION) SOLIBEXT=so endif CFLAGS+=-I. ALIBPFM=libpfm.a TARGETS=$(ALIBPFM) ifeq ($(CONFIG_PFMLIB_SHARED),y) TARGETS += $(SLIBPFM) endif OBJS=$(SRCS:.c=.o) SOBJS=$(OBJS:.o=.lo) INC_COMMON= $(PFMINCDIR)/perfmon/pfmlib.h \ $(PFMINCDIR)/perfmon/pfmlib_comp.h \ $(PFMINCDIR)/perfmon/pfmlib_os.h \ $(PFMINCDIR)/perfmon/perfmon.h \ $(PFMINCDIR)/perfmon/perfmon_dfl_smpl.h \ pfmlib_priv.h pfmlib_priv_comp.h \ INC_IA64= $(PFMINCDIR)/perfmon/pfmlib_itanium.h \ $(PFMINCDIR)/perfmon/pfmlib_itanium2.h \ $(PFMINCDIR)/perfmon/pfmlib_montecito.h \ $(PFMINCDIR)/perfmon/perfmon_compat.h \ $(PFMINCDIR)/perfmon/perfmon_default_smpl.h \ $(PFMINCDIR)/perfmon/perfmon_ia64.h \ $(PFMINCDIR)/perfmon/pfmlib_comp_ia64.h \ $(PFMINCDIR)/perfmon/pfmlib_gen_ia64.h \ $(PFMINCDIR)/perfmon/pfmlib_os_ia64.h \ itanium_events.h itanium2_events.h montecito_events.h INC_IA32=$(PFMINCDIR)/perfmon/perfmon_pebs_core_smpl.h \ $(PFMINCDIR)/perfmon/perfmon_pebs_p4_smpl.h \ $(PFMINCDIR)/perfmon/pfmlib_pentium4.h \ $(PFMINCDIR)/perfmon/pfmlib_amd64.h \ $(PFMINCDIR)/perfmon/pfmlib_core.h \ $(PFMINCDIR)/perfmon/pfmlib_intel_atom.h \ $(PFMINCDIR)/perfmon/pfmlib_intel_nhm.h \ $(PFMINCDIR)/perfmon/pfmlib_i386_p6.h \ $(PFMINCDIR)/perfmon/pfmlib_gen_ia32.h \ $(PFMINCDIR)/perfmon/pfmlib_comp_i386.h \ $(PFMINCDIR)/perfmon/pfmlib_os_i386.h \ amd64_events.h i386_p6_events.h \ pentium4_events.h gen_ia32_events.h coreduo_events.h core_events.h \ intel_atom_events.h intel_corei7_events.h intel_corei7_unc_events.h INC_X86_64= $(PFMINCDIR)/perfmon/perfmon_pebs_core_smpl.h \ $(PFMINCDIR)/perfmon/perfmon_pebs_p4_smpl.h \ $(PFMINCDIR)/perfmon/pfmlib_amd64.h \ $(PFMINCDIR)/perfmon/pfmlib_core.h \ $(PFMINCDIR)/perfmon/pfmlib_intel_atom.h \ $(PFMINCDIR)/perfmon/pfmlib_intel_nhm.h \ $(PFMINCDIR)/perfmon/pfmlib_gen_ia32.h \ $(PFMINCDIR)/perfmon/pfmlib_pentium4.h \ $(PFMINCDIR)/perfmon/pfmlib_comp_x86_64.h \ $(PFMINCDIR)/perfmon/pfmlib_os_x86_64.h \ amd64_events.h pentium4_events.h gen_ia32_events.h core_events.h \ intel_atom_events.h intel_corei7_events.h intel_corei7_unc_events.h INC_MIPS64= $(PFMINCDIR)/perfmon/pfmlib_gen_mips64.h \ $(PFMINCDIR)/perfmon/pfmlib_comp_mips64.h \ $(PFMINCDIR)/perfmon/pfmlib_os_mips64.h \ gen_mips64_events.h INC_SICORTEX= $(INC_MIPS64) $(PFMINCDIR)/perfmon/pfmlib_sicortex.h INC_POWERPC= $(PFMINCDIR)/perfmon/pfmlib_powerpc.h \ $(PFMINCDIR)/perfmon/pfmlib_comp_powerpc.h \ $(PFMINCDIR)/perfmon/pfmlib_os_powerpc.h \ ppc970_events.h ppc970mp_events.h power4_events.h \ power5_events.h power5+_events.h power6_events.h \ power7_events.h powerpc_reg.h INC_SPARC= $(PFMINCDIR)/perfmon/pfmlib_sparc.h \ $(PFMINCDIR)/perfmon/pfmlib_comp_sparc.h \ $(PFMINCDIR)/perfmon/pfmlib_os_sparc.h \ ultra12_events.h ultra3_events.h ultra3plus_events.h ultra3i_events.h \ ultra4plus_events.h niagara1_events.h niagara2_events.h INC_CRAYX2= $(PFMINCDIR)/perfmon/pfmlib_crayx2.h \ crayx2_events.h pfmlib_crayx2_priv.h INC_CELL= $(PFMINCDIR)/perfmon/pfmlib_cell.h \ cell_events.h INCDEP=$(INC_COMMON) $(INCARCH) all: $(TARGETS) $(OBJS) $(SOBJS): $(TOPDIR)/config.mk $(TOPDIR)/rules.mk Makefile $(INCDEP) libpfm.a: $(OBJS) $(RM) $@ $(AR) cru $@ $(OBJS) $(SLIBPFM): $(SOBJS) $(CC) $(CFLAGS) $(SLDFLAGS) -o $@ $(SOBJS) $(LN) $@ $(VLIBPFM) $(LN) $@ libpfm.$(SOLIBEXT) clean: $(RM) -f *.o *.lo *.a *.so* *~ *.$(SOLIBEXT) distclean: clean depend: $(MKDEP) $(CFLAGS) $(SRCS) install: $(TARGETS) install: @echo building: $(TARGETS) -mkdir -p $(DESTDIR)$(LIBDIR) $(INSTALL) -m 644 $(ALIBPFM) $(DESTDIR)$(LIBDIR) ifeq ($(CONFIG_PFMLIB_SHARED),y) $(INSTALL) $(SLIBPFM) $(DESTDIR)$(LIBDIR) cd $(DESTDIR)$(LIBDIR); $(LN) $(SLIBPFM) $(VLIBPFM) cd $(DESTDIR)$(LIBDIR); $(LN) $(SLIBPFM) libpfm.$(SOLIBEXT) endif papi-5.5.1/src/libpfm-3.y/lib/pfmlib_cell_priv.h0000644000307100002310000000565713013651450021366 0ustar yarkhangraduate/* * Copyright (c) 2007 TOSHIBA CORPORATION based on code from * Copyright (c) 2001-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef __PFMLIB_CELL_PRIV_H__ #define __PFMLIB_CELL_PRIV_H__ #define PFM_CELL_PME_FREQ_PPU_MFC 0 #define PFM_CELL_PME_FREQ_SPU 1 #define PFM_CELL_PME_FREQ_HALF 2 typedef struct { char *pme_name; /* event name */ char *pme_desc; /* event description */ unsigned long long pme_code; /* event code */ unsigned int pme_type; /* count type */ unsigned int pme_freq; /* debug_bus_control's frequency value */ unsigned int pme_enable_word; } pme_cell_entry_t; /* PMC register */ #define REG_PM0_CONTROL 0x0000 #define REG_PM1_CONTROL 0x0001 #define REG_PM2_CONTROL 0x0002 #define REG_PM3_CONTROL 0x0003 #define REG_PM4_CONTROL 0x0004 #define REG_PM5_CONTROL 0x0005 #define REG_PM6_CONTROL 0x0006 #define REG_PM7_CONTROL 0x0007 #define REG_PM0_EVENT 0x0008 #define REG_PM1_EVENT 0x0009 #define REG_PM2_EVENT 0x000A #define REG_PM3_EVENT 0x000B #define REG_PM4_EVENT 0x000C #define REG_PM5_EVENT 0x000D #define REG_PM6_EVENT 0x000E #define REG_PM7_EVENT 0x000F #define REG_GROUP_CONTROL 0x0010 #define REG_DEBUG_BUS_CONTROL 0x0011 #define REG_TRACE_ADDRESS 0x0012 #define REG_EXT_TRACE_TIMER 0x0013 #define REG_PM_STATUS 0x0014 #define REG_PM_CONTROL 0x0015 #define REG_PM_INTERVAL 0x0016 #define REG_PM_START_STOP 0x0017 #define NONE_SIGNAL 0x0000 #define SIGNAL_SPU 41 #define SIGNAL_SPU_TRIGGER 42 #define SIGNAL_SPU_EVENT 43 #define COUNT_TYPE_BOTH_TYPE 1 #define COUNT_TYPE_CUMULATIVE_LEN 2 #define COUNT_TYPE_OCCURRENCE 3 #define COUNT_TYPE_MULTI_CYCLE 4 #define COUNT_TYPE_SINGLE_CYCLE 5 #define WORD_0_ONLY 1 /* 0001 */ #define WORD_2_ONLY 4 /* 0100 */ #define WORD_0_AND_1 3 /* 0011 */ #define WORD_0_AND_2 5 /* 0101 */ #define WORD_NONE 0 #endif /* __PFMLIB_CELL_PRIV_H__ */ papi-5.5.1/src/libpfm-3.y/lib/pfmlib_priv.c0000644000307100002310000000505313013651450020350 0ustar yarkhangraduate/* * pfmlib_priv.c: set of internal utility functions for all architectures * * Copyright (c) 2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include "pfmlib_priv.h" /* * file for all libpfm verbose and debug output * * By default, it is set to stderr, unless the * PFMLIB_DEBUG_STDOUT environment variable is set */ FILE *libpfm_fp; /* * by convention all internal utility function must be prefixed by __ */ /* * debug printf */ void __pfm_vbprintf(const char *fmt, ...) { va_list ap; if (pfm_config.options.pfm_verbose == 0) return; va_start(ap, fmt); vfprintf(libpfm_fp, fmt, ap); va_end(ap); } int __pfm_check_event(pfmlib_event_t *e) { unsigned int n, j; if (e->event >= pfm_current->pme_count) return PFMLIB_ERR_INVAL; n = pfm_num_masks(e->event); if (n == 0 && e->num_masks) return PFMLIB_ERR_UMASK; for(j=0; j < e->num_masks; j++) { if (e->unit_masks[j] >= n) return PFMLIB_ERR_UMASK; } /* * if event has umask, but non specified by user, then * return: * - error if no default umask is defined * - success if default umask exists for event */ if (n && j == 0) { if (pfm_current->has_umask_default && pfm_current->has_umask_default(e->event)) return PFMLIB_SUCCESS; return PFMLIB_ERR_UMASK; } return PFMLIB_SUCCESS; } papi-5.5.1/src/libpfm-3.y/lib/pfmlib_power5+_priv.h0000644000307100002310000000120113013651450021720 0ustar yarkhangraduate/****************************/ /* THIS IS OPEN SOURCE CODE */ /****************************/ #ifndef __PFMLIB_POWER5p_PRIV_H__ #define __PFMLIB_POWER5p_PRIV_H__ /* * File: pfmlib_power5+_priv.h * CVS: * Author: Corey Ashford * cjashfor@us.ibm.com * Mods: * * * (C) Copyright IBM Corporation, 2007. All Rights Reserved. * Contributed by Corey Ashford * * Note: This code was automatically generated and should not be modified by * hand. * */ #define POWER5p_NUM_EVENT_COUNTERS 6 #define POWER5p_NUM_GROUP_VEC 3 #define POWER5p_NUM_CONTROL_REGS 3 #endif papi-5.5.1/src/libpfm-3.y/lib/gen_mips64_events.h0000644000307100002310000015251313013651450021407 0ustar yarkhangraduatestatic pme_gen_mips64_entry_t gen_mips64_20K_pe[] = { {.pme_name="INSN_REQ_FROM_IFU_TO_BIU", .pme_code = 0x00000009, .pme_counters = 0x1, .pme_desc = "Instruction requests from the IFU to the BIU" }, {.pme_name="BRANCHES_MISSPREDICTED", .pme_code = 0x00000005, .pme_counters = 0x1, .pme_desc = "Branches that mispredicted before completing execution" }, {.pme_name="REPLAYS", .pme_code = 0x0000000b, .pme_counters = 0x1, .pme_desc = "Total number of LSU requested replays, Load-dependent speculative dispatch or FPU exception prediction replays." }, {.pme_name="JR_INSNS_COMPLETED", .pme_code = 0x0000000d, .pme_counters = 0x1, .pme_desc = "JR instruction that completed execution" }, {.pme_name="CYCLES", .pme_code = 0x00000000, .pme_counters = 0x1, .pme_desc = "CPU cycles" }, {.pme_name="REPLAY_DUE_TO_LOAD_DEPENDENT_SPEC_DISPATCH", .pme_code = 0x00000008, .pme_counters = 0x1, .pme_desc = "Replays due to load-dependent speculative dispatch" }, {.pme_name="LSU_REPLAYS", .pme_code = 0x0000000e, .pme_counters = 0x1, .pme_desc = "LSU requested replays" }, {.pme_name="FP_INSNS_COMPLETED", .pme_code = 0x00000003, .pme_counters = 0x1, .pme_desc = "Instructions completed in FPU datapath (computational event" }, {.pme_name="FPU_EXCEPTIONS_TAKEN", .pme_code = 0x0000000a, .pme_counters = 0x1, .pme_desc = "Taken FPU exceptions" }, {.pme_name="TLB_REFILLS_TAKEN", .pme_code = 0x00000004, .pme_counters = 0x1, .pme_desc = "Taken TLB refill exceptions" }, {.pme_name="RPS_MISSPREDICTS", .pme_code = 0x0000000c, .pme_counters = 0x1, .pme_desc = "JR instructions that mispredicted using the Return Prediction Stack (RPS)" }, {.pme_name="INSN_ISSUED", .pme_code = 0x00000001, .pme_counters = 0x1, .pme_desc = "Dispatched/issued instructions" }, {.pme_name="INSNS_COMPLETED", .pme_code = 0x0000000f, .pme_counters = 0x1, .pme_desc = "Instruction that completed execution (with or without exception)" }, {.pme_name="BRANCHES_COMPLETED", .pme_code = 0x00000006, .pme_counters = 0x1, .pme_desc = "Branches that completed execution" }, {.pme_name="JTLB_EXCEPTIONS", .pme_code = 0x00000007, .pme_counters = 0x1, .pme_desc = "Taken Joint-TLB exceptions" }, {.pme_name="FETCH_GROUPS", .pme_code = 0x00000002, .pme_counters = 0x1, .pme_desc = "Fetch groups entering CPU execution pipes" }, }; static pme_gen_mips64_entry_t gen_mips64_24K_pe[] = { {.pme_name="DCACHE_MISS", .pme_code = 0x00000b0b, .pme_counters = 0x3, .pme_desc = "Data cache misses" }, {.pme_name="REPLAY_TRAPS_NOT_UTLB", .pme_code = 0x00001200, .pme_counters = 0x2, .pme_desc = "``replay traps'' (other than micro-TLB related)" }, {.pme_name="ITLB_ACCESSES", .pme_code = 0x00000005, .pme_counters = 0x1, .pme_desc = "Instruction micro-TLB accesses" }, {.pme_name="INSTRUCTIONS", .pme_code = 0x00000101, .pme_counters = 0x3, .pme_desc = "Instructions completed" }, {.pme_name="LOADS_COMPLETED", .pme_code = 0x0000000f, .pme_counters = 0x1, .pme_desc = "Loads completed (including FP)" }, {.pme_name="SC_COMPLETE_BUT_FAILED", .pme_code = 0x00001300, .pme_counters = 0x2, .pme_desc = "sc instructions completed, but store failed (because the link bit had been cleared)." }, {.pme_name="JTLB_DATA_MISSES", .pme_code = 0x00000800, .pme_counters = 0x2, .pme_desc = "Joint TLB data (non-instruction) misses" }, {.pme_name="L2_MISSES", .pme_code = 0x00001616, .pme_counters = 0x3, .pme_desc = "L2 cache misses" }, {.pme_name="SC_COMPLETED", .pme_code = 0x00000013, .pme_counters = 0x1, .pme_desc = "sc instructions completed" }, {.pme_name="SUPERFLUOUS_INSTRUCTIONS", .pme_code = 0x00001400, .pme_counters = 0x2, .pme_desc = "``superfluous'' prefetch instructions (data was already in cache)." }, {.pme_name="DCACHE_WRITEBACKS", .pme_code = 0x00000a00, .pme_counters = 0x2, .pme_desc = "Data cache writebacks" }, {.pme_name="JR_31_MISSPREDICTS", .pme_code = 0x00000300, .pme_counters = 0x2, .pme_desc = "jr r31 (return) mispredictions" }, {.pme_name="JTLB_DATA_ACCESSES", .pme_code = 0x00000007, .pme_counters = 0x1, .pme_desc = "Joint TLB instruction accesses" }, {.pme_name="ICACHE_MISSES", .pme_code = 0x00000900, .pme_counters = 0x2, .pme_desc = "Instruction cache misses" }, {.pme_name="STALLS", .pme_code = 0x00000012, .pme_counters = 0x1, .pme_desc = "Stalls" }, {.pme_name="INTEGER_INSNS_COMPLETED", .pme_code = 0x0000000e, .pme_counters = 0x1, .pme_desc = "Integer instructions completed" }, {.pme_name="INTEGER_MUL_DIV_COMPLETED", .pme_code = 0x00001100, .pme_counters = 0x2, .pme_desc = "integer multiply/divide unit instructions completed" }, {.pme_name="STORES_COMPLETED", .pme_code = 0x00000f00, .pme_counters = 0x2, .pme_desc = "Stores completed (including FP)" }, {.pme_name="MIPS16_INSTRUCTIONS_COMPLETED", .pme_code = 0x00001000, .pme_counters = 0x2, .pme_desc = "MIPS16 instructions completed" }, {.pme_name="BRANCHES_LAUNCHED", .pme_code = 0x00000002, .pme_counters = 0x1, .pme_desc = "Branch instructions launched (whether completed or mispredicted)" }, {.pme_name="SCACHE_ACCESSES", .pme_code = 0x00001500, .pme_counters = 0x2, .pme_desc = "L2 cache accesses" }, {.pme_name="JR_31_LAUNCHED", .pme_code = 0x00000003, .pme_counters = 0x1, .pme_desc = "jr r31 (return) instructions launched (whether completed or mispredicted)" }, {.pme_name="PREFETCH_COMPLETED", .pme_code = 0x00000014, .pme_counters = 0x1, .pme_desc = "Prefetch instructions completed" }, {.pme_name="EXCEPTIONS_TAKEN", .pme_code = 0x00000017, .pme_counters = 0x1, .pme_desc = "Exceptions taken" }, {.pme_name="JR_NON_31_LAUNCHED", .pme_code = 0x00000004, .pme_counters = 0x1, .pme_desc = "jr (not r31) issues, which cost the same as a mispredict." }, {.pme_name="DTLB_ACCESSES", .pme_code = 0x00000006, .pme_counters = 0x1, .pme_desc = "Data micro-TLB accesses" }, {.pme_name="JTLB_INSTRUCTION_ACCESSES", .pme_code = 0x00000008, .pme_counters = 0x1, .pme_desc = "Joint TLB data (non-instruction) accesses" }, {.pme_name="CACHE_FIXUPS", .pme_code = 0x00000018, .pme_counters = 0x1, .pme_desc = "``cache fixup'' events (specific to the 24K family microarchitecture)." }, {.pme_name="INSTRUCTION_CACHE_ACCESSES", .pme_code = 0x00000009, .pme_counters = 0x1, .pme_desc = "Instruction cache accesses" }, {.pme_name="DTLB_MISSES", .pme_code = 0x00000600, .pme_counters = 0x2, .pme_desc = "Data micro-TLB misses" }, {.pme_name="J_JAL_INSNS_COMPLETED", .pme_code = 0x00000010, .pme_counters = 0x1, .pme_desc = "j/jal instructions completed" }, {.pme_name="DCACHE_ACCESSES", .pme_code = 0x0000000a, .pme_counters = 0x1, .pme_desc = "Data cache accesses" }, {.pme_name="BRANCH_MISSPREDICTS", .pme_code = 0x00000200, .pme_counters = 0x2, .pme_desc = "Branch mispredictions" }, {.pme_name="SCACHE_WRITEBACKS", .pme_code = 0x00000015, .pme_counters = 0x1, .pme_desc = "L2 cache writebacks" }, {.pme_name="CYCLES", .pme_code = 0x00000000, .pme_counters = 0x3, .pme_desc = "Cycles" }, {.pme_name="JTLB_INSN_MISSES", .pme_code = 0x00000700, .pme_counters = 0x2, .pme_desc = "Joint TLB instruction misses" }, {.pme_name="FPU_INSNS_NON_LOAD_STORE_COMPLETED", .pme_code = 0x00000e00, .pme_counters = 0x2, .pme_desc = "FPU instructions completed (not including loads/stores)" }, {.pme_name="NOPS_COMPLETED", .pme_code = 0x00000011, .pme_counters = 0x1, .pme_desc = "no-ops completed, ie instructions writing $0" }, {.pme_name="ITLB_MISSES", .pme_code = 0x00000500, .pme_counters = 0x2, .pme_desc = "Instruction micro-TLB misses" }, }; static pme_gen_mips64_entry_t gen_mips64_25K_pe[] = { {.pme_name="INSNS_FETCHED_FROM_ICACHE", .pme_code = 0x00001818, .pme_counters = 0x3, .pme_desc = "Total number of instructions fetched from the I-Cache" }, {.pme_name="FP_EXCEPTIONS_TAKEN", .pme_code = 0x00000b0b, .pme_counters = 0x3, .pme_desc = "Taken FPU exceptions" }, {.pme_name="INSN_ISSUED", .pme_code = 0x00000101, .pme_counters = 0x3, .pme_desc = "Dispatched/issued instructions" }, {.pme_name="STORE_INSNS_ISSUED", .pme_code = 0x00000505, .pme_counters = 0x3, .pme_desc = "Store instructions issued" }, {.pme_name="L2_MISSES", .pme_code = 0x00001e1e, .pme_counters = 0x3, .pme_desc = "L2 Cache miss" }, {.pme_name="REPLAYS_LOAD_DEP_DISPATCH", .pme_code = 0x00002323, .pme_counters = 0x3, .pme_desc = "replays due to load-dependent speculative dispatch" }, {.pme_name="BRANCHES_JUMPS_ISSUED", .pme_code = 0x00000606, .pme_counters = 0x3, .pme_desc = "Branch/Jump instructions issued" }, {.pme_name="REPLAYS_LSU_LOAD_DEP_FPU", .pme_code = 0x00002121, .pme_counters = 0x3, .pme_desc = "LSU requested replays, load-dependent speculative dispatch, FPU exception prediction" }, {.pme_name="INSNS_COMPLETE", .pme_code = 0x00000808, .pme_counters = 0x3, .pme_desc = "Instruction that completed execution (with or without exception)" }, {.pme_name="JTLB_MISSES_LOADS_STORES", .pme_code = 0x00001313, .pme_counters = 0x3, .pme_desc = "Raw count of Joint-TLB misses for loads/stores" }, {.pme_name="CACHEABLE_DCACHE_REQUEST", .pme_code = 0x00001d1d, .pme_counters = 0x3, .pme_desc = "number of cacheable requests to D-Cache" }, {.pme_name="DCACHE_WRITEBACKS", .pme_code = 0x00001c1c, .pme_counters = 0x3, .pme_desc = "D-Cache number of write-backs" }, {.pme_name="ICACHE_MISSES", .pme_code = 0x00001a1a, .pme_counters = 0x3, .pme_desc = "I-Cache miss" }, {.pme_name="ICACHE_PSEUDO_HITS", .pme_code = 0x00002626, .pme_counters = 0x3, .pme_desc = "I-Cache pseudo-hits" }, {.pme_name="FP_EXCEPTION_PREDICTED", .pme_code = 0x00000c0c, .pme_counters = 0x3, .pme_desc = "Predicted FPU exceptions" }, {.pme_name="LOAD_STORE_ISSUED", .pme_code = 0x00002727, .pme_counters = 0x3, .pme_desc = "Load/store instructions issued" }, {.pme_name="REPLAYS_WBB_FULL", .pme_code = 0x00002424, .pme_counters = 0x3, .pme_desc = "replays due to WBB full" }, {.pme_name="L2_WBACKS", .pme_code = 0x00001f1f, .pme_counters = 0x3, .pme_desc = "L2 Cache number of write-backs" }, {.pme_name="JR_COMPLETED", .pme_code = 0x00001010, .pme_counters = 0x3, .pme_desc = "JR instruction that completed execution" }, {.pme_name="JR_RPD_MISSPREDICTED", .pme_code = 0x00000f0f, .pme_counters = 0x3, .pme_desc = "JR instructions that mispredicted using the Return Prediction Stack" }, {.pme_name="JTLB_IFETCH_REFILL_EXCEPTIONS", .pme_code = 0x00001515, .pme_counters = 0x3, .pme_desc = "Joint-TLB refill exceptions due to instruction fetch" }, {.pme_name="DUAL_ISSUED_PAIRS", .pme_code = 0x00000707, .pme_counters = 0x3, .pme_desc = "Dual-issued pairs" }, {.pme_name="FSB_FULL_REPLAYS", .pme_code = 0x00002525, .pme_counters = 0x3, .pme_desc = "replays due to FSB full" }, {.pme_name="JTLB_REFILL_EXCEPTIONS", .pme_code = 0x00001717, .pme_counters = 0x3, .pme_desc = "total Joint-TLB Instruction exceptions (refill)" }, {.pme_name="INT_INSNS_ISSUED", .pme_code = 0x00000303, .pme_counters = 0x3, .pme_desc = "Integer instructions issued" }, {.pme_name="FP_INSNS_ISSUED", .pme_code = 0x00000202, .pme_counters = 0x3, .pme_desc = "FPU instructions issued" }, {.pme_name="BRANCHES_MISSPREDICTED", .pme_code = 0x00000d0d, .pme_counters = 0x3, .pme_desc = "Branches that mispredicted before completing execution" }, {.pme_name="FETCH_GROUPS_IN_PIPE", .pme_code = 0x00000909, .pme_counters = 0x3, .pme_desc = "Fetch groups entering CPU execution pipes" }, {.pme_name="CACHEABLE_L2_REQS", .pme_code = 0x00002020, .pme_counters = 0x3, .pme_desc = "Number of cacheable requests to L2" }, {.pme_name="JTLB_DATA_ACCESS_REFILL_EXCEPTIONS", .pme_code = 0x00001616, .pme_counters = 0x3, .pme_desc = "Joint-TLB refill exceptions due to data access" }, {.pme_name="UTLB_MISSES", .pme_code = 0x00001111, .pme_counters = 0x3, .pme_desc = "U-TLB misses" }, {.pme_name="LOAD_INSNS_ISSUED", .pme_code = 0x00000404, .pme_counters = 0x3, .pme_desc = "Load instructions issued" }, {.pme_name="JTLB_MISSES_IFETCH", .pme_code = 0x00001212, .pme_counters = 0x3, .pme_desc = "Raw count of Joint-TLB misses for instruction fetch" }, {.pme_name="CYCLES", .pme_code = 0x00000000, .pme_counters = 0x3, .pme_desc = "CPU cycles" }, {.pme_name="LSU_REQ_REPLAYS", .pme_code = 0x00002222, .pme_counters = 0x3, .pme_desc = "LSU requested replays" }, {.pme_name="INSN_REQ_FROM_IFU_BIU", .pme_code = 0x00001919, .pme_counters = 0x3, .pme_desc = "instruction requests from the IFU to the BIU" }, {.pme_name="JTLB_EXCEPTIONS", .pme_code = 0x00001414, .pme_counters = 0x3, .pme_desc = "Refill, Invalid and Modified TLB exceptions" }, {.pme_name="BRANCHES_COMPLETED", .pme_code = 0x00000e0e, .pme_counters = 0x3, .pme_desc = "Branches that completed execution" }, {.pme_name="INSN_FP_DATAPATH_COMPLETED", .pme_code = 0x00000a0a, .pme_counters = 0x3, .pme_desc = "Instructions completed in FPU datapath (computational instructions only)" }, {.pme_name="DCACHE_MISSES", .pme_code = 0x00001b1b, .pme_counters = 0x3, .pme_desc = "D-Cache miss" }, }; static pme_gen_mips64_entry_t gen_mips64_34K_pe[] = { {.pme_name="YIELD_INSNS", .pme_code = 0x00220022, .pme_counters = 0x5, .pme_desc = "yield instructions." }, {.pme_name="BRANCH_MISPREDICT_STALLS", .pme_code = 0x002e002e, .pme_counters = 0x5, .pme_desc = "Branch mispredict stalls" }, {.pme_name="SC_FAILED_INSNS", .pme_code = 0x00130013, .pme_counters = 0x5, .pme_desc = "sc instructions completed, but store failed (because the link bit had been cleared)." }, {.pme_name="ITC_LOAD_STORE_STALLS", .pme_code = 0x00280028, .pme_counters = 0x5, .pme_desc = "ITC load/store stalls" }, {.pme_name="ITC_LOADS", .pme_code = 0x00200020, .pme_counters = 0x5, .pme_desc = "ITC Loads" }, {.pme_name="LOADS_COMPLETED", .pme_code = 0x000f000f, .pme_counters = 0x5, .pme_desc = "Loads completed (including FP)" }, {.pme_name="BRANCH_INSNS_LAUNCHED", .pme_code = 0x00020002, .pme_counters = 0x5, .pme_desc = "Branch instructions launched (whether completed or mispredicted)" }, {.pme_name="DATA_SIDE_SCRATCHPAD_ACCESS_STALLS", .pme_code = 0x002b002b, .pme_counters = 0x5, .pme_desc = "Data-side scratchpad access stalls" }, {.pme_name="FB_ENTRY_ALLOCATED", .pme_code = 0x00300030, .pme_counters = 0x5, .pme_desc = "FB entry allocated" }, {.pme_name="CP2_STALLS", .pme_code = 0x002a002a, .pme_counters = 0x5, .pme_desc = "CP2 stalls" }, {.pme_name="FSB_25_50_FULL", .pme_code = 0x00320032, .pme_counters = 0x5, .pme_desc = "FSB 25-50% full" }, {.pme_name="CACHE_FIXUP_EVENTS", .pme_code = 0x00180018, .pme_counters = 0x5, .pme_desc = "cache fixup events (specific to the 34K family microarchitecture)" }, {.pme_name="IFU_FB_FULL_REFETCHES", .pme_code = 0x00300030, .pme_counters = 0x5, .pme_desc = "IFU FB full re-fetches" }, {.pme_name="L1_DCACHE_MISS_STALLS", .pme_code = 0x00250025, .pme_counters = 0x5, .pme_desc = "L1 D-cache miss stalls" }, {.pme_name="INT_MUL_DIV_UNIT_INSNS_COMPLETED", .pme_code = 0x00110011, .pme_counters = 0x5, .pme_desc = "integer multiply/divide unit instructions completed" }, {.pme_name="JTLB_INSN_ACCESSES", .pme_code = 0x00070007, .pme_counters = 0x5, .pme_desc = "Joint TLB instruction accesses" }, {.pme_name="ALU_STALLS", .pme_code = 0x00190019, .pme_counters = 0x5, .pme_desc = "ALU stalls" }, {.pme_name="FPU_STALLS", .pme_code = 0x00290029, .pme_counters = 0x5, .pme_desc = "FPU stalls" }, {.pme_name="JTLB_DATA_ACCESSES", .pme_code = 0x00080008, .pme_counters = 0x5, .pme_desc = "Joint TLB data (non-instruction) accesses" }, {.pme_name="INTEGER_INSNS_COMPLETED", .pme_code = 0x000e000e, .pme_counters = 0x5, .pme_desc = "Integer instructions completed" }, {.pme_name="MFC2_MTC2_INSNS", .pme_code = 0x00230023, .pme_counters = 0x5, .pme_desc = "CP2 move to/from instructions." }, {.pme_name="STORES_COMPLETED", .pme_code = 0x000f000f, .pme_counters = 0x5, .pme_desc = "Stores completed (including FP)" }, {.pme_name="JR_NON_31_INSN_EXECED", .pme_code = 0x00040004, .pme_counters = 0x5, .pme_desc = "jr $xx (not $31), which cost the same as a mispredict." }, {.pme_name="EXCEPTIONS_TAKEN", .pme_code = 0x00170017, .pme_counters = 0x5, .pme_desc = "Exceptions taken" }, {.pme_name="L2_MISS_PENDING_CYCLES", .pme_code = 0x00270027, .pme_counters = 0x5, .pme_desc = "Cycles where L2 miss is pending" }, {.pme_name="LDQ_FULL_PIPE_STALLS", .pme_code = 0x00350035, .pme_counters = 0x5, .pme_desc = "LDQ full pipeline stalls" }, {.pme_name="DTLB_ACCESSES", .pme_code = 0x00060006, .pme_counters = 0x5, .pme_desc = "Data micro-TLB accesses" }, {.pme_name="SUPERFLUOUS_PREFETCHES", .pme_code = 0x00140014, .pme_counters = 0x5, .pme_desc = "``superfluous'' prefetch instructions (data was already in cache)." }, {.pme_name="LDQ_LESS_25_FULL", .pme_code = 0x00340034, .pme_counters = 0x5, .pme_desc = "LDQ < 25% full" }, {.pme_name="FORK_INSTRUCTIONS", .pme_code = 0x00220022, .pme_counters = 0x5, .pme_desc = "fork instructions" }, {.pme_name="UNCACHED_LOAD_STALLS", .pme_code = 0x00280028, .pme_counters = 0x5, .pme_desc = "Uncached load stalls" }, {.pme_name="FSB_FULL_PIPE_STALLS", .pme_code = 0x00330033, .pme_counters = 0x5, .pme_desc = "FSB full pipeline stalls" }, {.pme_name="MDU_STALLS", .pme_code = 0x00290029, .pme_counters = 0x5, .pme_desc = "MDU stalls" }, {.pme_name="FSB_LESS_25_FULL", .pme_code = 0x00320032, .pme_counters = 0x5, .pme_desc = "FSB < 25% full" }, {.pme_name="UNCACHED_LOADS", .pme_code = 0x00210021, .pme_counters = 0x5, .pme_desc = "Uncached Loads" }, {.pme_name="NO_OPS_COMPLETED", .pme_code = 0x00110011, .pme_counters = 0x5, .pme_desc = "no-ops completed, ie instructions writing $0" }, {.pme_name="DATA_SIDE_SCRATCHPAD_RAM_LOGIC", .pme_code = 0x001d001d, .pme_counters = 0x5, .pme_desc = "Data-side scratchpad RAM logic" }, {.pme_name="CYCLES_INSN_NOT_IN_SKID_BUFFER", .pme_code = 0x00180018, .pme_counters = 0x5, .pme_desc = "Cycles lost when an unblocked thread's instruction isn't in the skid buffer, and must be re-fetched from I-cache." }, {.pme_name="ITC_LOGIC", .pme_code = 0x001f001f, .pme_counters = 0x5, .pme_desc = "ITC logic" }, {.pme_name="L2_IMISS_STALLS", .pme_code = 0x00260026, .pme_counters = 0x5, .pme_desc = "L2 I-miss stalls" }, {.pme_name="DSP_RESULT_SATURATED", .pme_code = 0x00240024, .pme_counters = 0x5, .pme_desc = "DSP result saturated" }, {.pme_name="INSTRUCTIONS", .pme_code = 0x01010101, .pme_counters = 0xf, .pme_desc = "Instructions completed" }, {.pme_name="ITLB_ACCESSES", .pme_code = 0x00050005, .pme_counters = 0x5, .pme_desc = "Instruction micro-TLB accesses" }, {.pme_name="CP2_REG_TO_REG_INSNS", .pme_code = 0x00230023, .pme_counters = 0x5, .pme_desc = "CP2 register-to-register instructions" }, {.pme_name="SC_INSNS_COMPLETED", .pme_code = 0x00130013, .pme_counters = 0x5, .pme_desc = "sc instructions completed" }, {.pme_name="COREEXTEND_STALLS", .pme_code = 0x002a002a, .pme_counters = 0x5, .pme_desc = "CorExtend stalls" }, {.pme_name="LOAD_USE_STALLS", .pme_code = 0x002d002d, .pme_counters = 0x5, .pme_desc = "Load to Use stalls" }, {.pme_name="JR_31_INSN_EXECED", .pme_code = 0x00030003, .pme_counters = 0x5, .pme_desc = "jr $31 (return) instructions executed." }, {.pme_name="JR_31_MISPREDICTS", .pme_code = 0x00030003, .pme_counters = 0x5, .pme_desc = "jr $31 mispredictions." }, {.pme_name="REPLAY_CYCLES", .pme_code = 0x00120012, .pme_counters = 0x5, .pme_desc = "Cycles lost due to ``replays'' - when a thread blocks, its instructions in the pipeline are discarded to allow other threads to advance." }, {.pme_name="L2_MISSES", .pme_code = 0x16161616, .pme_counters = 0xf, .pme_desc = "L2 cache misses" }, {.pme_name="JTLB_DATA_MISSES", .pme_code = 0x00080008, .pme_counters = 0x5, .pme_desc = "Joint TLB data (non-instruction) misses" }, {.pme_name="SYSTEM_INTERFACE", .pme_code = 0x001e001e, .pme_counters = 0x5, .pme_desc = "System interface" }, {.pme_name="BRANCH_MISPREDICTS", .pme_code = 0x00020002, .pme_counters = 0x5, .pme_desc = "Branch mispredictions" }, {.pme_name="ITC_STORES", .pme_code = 0x00200020, .pme_counters = 0x5, .pme_desc = "ITC Stores" }, {.pme_name="LDQ_OVER_50_FULL", .pme_code = 0x00350035, .pme_counters = 0x5, .pme_desc = "LDQ > 50% full" }, {.pme_name="FSB_OVER_50_FULL", .pme_code = 0x00330033, .pme_counters = 0x5, .pme_desc = "FSB > 50% full" }, {.pme_name="STALLS_NO_ROOM_PENDING_WRITE", .pme_code = 0x002c002c, .pme_counters = 0x5, .pme_desc = "Stalls when no more room to store pending write." }, {.pme_name="JR_31_NOT_PREDICTED", .pme_code = 0x00040004, .pme_counters = 0x5, .pme_desc = "jr $31 not predicted (stack mismatch)." }, {.pme_name="EXTERNAL_YIELD_MANAGER_LOGIC", .pme_code = 0x001f001f, .pme_counters = 0x5, .pme_desc = "External Yield Manager logic" }, {.pme_name="DCACHE_WRITEBACKS", .pme_code = 0x000a000a, .pme_counters = 0x5, .pme_desc = "Data cache writebacks" }, {.pme_name="RELAX_BUBBLES", .pme_code = 0x002f002f, .pme_counters = 0x5, .pme_desc = "``Relax bubbles'' - when thread scheduler chooses to schedule nothing to reduce power consumption." }, {.pme_name="ICACHE_MISSES", .pme_code = 0x00090009, .pme_counters = 0x5, .pme_desc = "Instruction cache misses" }, {.pme_name="MIPS16_INSNS_COMPLETED", .pme_code = 0x00100010, .pme_counters = 0x5, .pme_desc = "MIPS16 instructions completed" }, {.pme_name="OTHER_INTERLOCK_STALLS", .pme_code = 0x002e002e, .pme_counters = 0x5, .pme_desc = "Other interlock stalls" }, {.pme_name="L2_CACHE_WRITEBACKS", .pme_code = 0x00150015, .pme_counters = 0x5, .pme_desc = "L2 cache writebacks" }, {.pme_name="WBB_LESS_25_FULL", .pme_code = 0x00360036, .pme_counters = 0x5, .pme_desc = "WBB < 25% full" }, {.pme_name="L2_DCACHE_MISS_STALLS", .pme_code = 0x00260026, .pme_counters = 0x5, .pme_desc = "L2 D-miss stalls" }, {.pme_name="CACHE_INSTRUCTION_STALLS", .pme_code = 0x002c002c, .pme_counters = 0x5, .pme_desc = "Stalls due to cache instructions" }, {.pme_name="L1_DCACHE_MISS_PENDING_CYCLES", .pme_code = 0x00270027, .pme_counters = 0x5, .pme_desc = "Cycles where L1 D-cache miss pending" }, {.pme_name="ALU_TO_AGEN_STALLS", .pme_code = 0x002d002d, .pme_counters = 0x5, .pme_desc = "ALU to AGEN stalls" }, {.pme_name="L2_ACCESSES", .pme_code = 0x00150015, .pme_counters = 0x5, .pme_desc = "L2 cache accesses" }, {.pme_name="J_JAL_INSN_COMPLETED", .pme_code = 0x00100010, .pme_counters = 0x5, .pme_desc = "j/jal instructions completed" }, {.pme_name="ALL_STALLS", .pme_code = 0x00120012, .pme_counters = 0x5, .pme_desc = "All stalls (no action in RF pipe stage)" }, {.pme_name="DSP_INSTRUCTIONS", .pme_code = 0x00240024, .pme_counters = 0x5, .pme_desc = "DSP instructions" }, {.pme_name="UNCACHED_STORES", .pme_code = 0x00210021, .pme_counters = 0x5, .pme_desc = "Uncached Stores" }, {.pme_name="WBB_FULL_PIPE_STALLS", .pme_code = 0x00370037, .pme_counters = 0x5, .pme_desc = "WBB full pipeline stalls" }, {.pme_name="INSN_CACHE_ACCESSES", .pme_code = 0x00090009, .pme_counters = 0x5, .pme_desc = "Instruction cache accesses" }, {.pme_name="EXT_POLICY_MANAGER", .pme_code = 0x001c001c, .pme_counters = 0x5, .pme_desc = "External policy manager" }, {.pme_name="WBB_OVER_50_FULL", .pme_code = 0x00370037, .pme_counters = 0x5, .pme_desc = "WBB > 50% full" }, {.pme_name="DTLB_MISSES", .pme_code = 0x00060006, .pme_counters = 0x5, .pme_desc = "Data micro-TLB misses" }, {.pme_name="DCACHE_ACCESSES", .pme_code = 0x000a000a, .pme_counters = 0x5, .pme_desc = "Data cache accesses" }, {.pme_name="COREEXTEND_LOGIC", .pme_code = 0x001e001e, .pme_counters = 0x5, .pme_desc = "CorExtend logic" }, {.pme_name="LDQ_25_50_FULL", .pme_code = 0x00340034, .pme_counters = 0x5, .pme_desc = "LDQ 25-50% full" }, {.pme_name="PREFETCH_INSNS_COMPLETED", .pme_code = 0x00140014, .pme_counters = 0x5, .pme_desc = "Prefetch instructions completed" }, {.pme_name="CYCLES", .pme_code = 0x00000000, .pme_counters = 0xf, .pme_desc = "Cycles" }, {.pme_name="L1_ICACHE_MISS_STALLS", .pme_code = 0x00250025, .pme_counters = 0x5, .pme_desc = "L1 I-cache miss stalls" }, {.pme_name="JTLB_INSN_MISSES", .pme_code = 0x00070007, .pme_counters = 0x5, .pme_desc = "Joint TLB instruction misses" }, {.pme_name="COP2", .pme_code = 0x001c001c, .pme_counters = 0x5, .pme_desc = "Co-Processor 2" }, {.pme_name="FPU_INSNS_COMPLETED", .pme_code = 0x000e000e, .pme_counters = 0x5, .pme_desc = "FPU instructions completed (not including loads/stores)" }, {.pme_name="ITLB_MISSES", .pme_code = 0x00050005, .pme_counters = 0x5, .pme_desc = "Instruction micro-TLB misses" }, {.pme_name="IFU_STALLS", .pme_code = 0x00190019, .pme_counters = 0x5, .pme_desc = "IFU stalls (when no instruction offered) ALU stalls" }, {.pme_name="WBB_25_50_FULL", .pme_code = 0x00360036, .pme_counters = 0x5, .pme_desc = "WBB 25-50% full" }, {.pme_name="DCACHE_MISSES", .pme_code = 0x0b0b0b0b, .pme_counters = 0xf, .pme_desc = "Data cache misses" }, }; static pme_gen_mips64_entry_t gen_mips64_5K_pe[] = { {.pme_name="DCACHE_LINE_EVICTED", .pme_code = 0x00000600, .pme_counters = 0x2, .pme_desc = "Data cache line evicted" }, {.pme_name="LOADS_EXECED", .pme_code = 0x00000202, .pme_counters = 0x3, .pme_desc = "Load/pref(x)/sync/cache-ops executed" }, {.pme_name="INSN_SCHEDULED", .pme_code = 0x0000000a, .pme_counters = 0x1, .pme_desc = "Instruction scheduled" }, {.pme_name="DUAL_ISSUED_INSNS", .pme_code = 0x0000000e, .pme_counters = 0x1, .pme_desc = "Dual issued instructions executed" }, {.pme_name="BRANCHES_MISSPREDICTED", .pme_code = 0x00000800, .pme_counters = 0x2, .pme_desc = "Branch mispredicted" }, {.pme_name="CONFLICT_STALL_M_STAGE", .pme_code = 0x00000a00, .pme_counters = 0x2, .pme_desc = "Instruction stall in M stage due to scheduling conflicts" }, {.pme_name="STORES_EXECED", .pme_code = 0x00000303, .pme_counters = 0x3, .pme_desc = "Stores (including conditional stores) executed" }, {.pme_name="DCACHE_MISS", .pme_code = 0x00000900, .pme_counters = 0x2, .pme_desc = "Data cache miss" }, {.pme_name="INSN_FETCHED", .pme_code = 0x00000001, .pme_counters = 0x1, .pme_desc = "Instructions fetched" }, {.pme_name="TLB_MISS_EXCEPTIONS", .pme_code = 0x00000700, .pme_counters = 0x2, .pme_desc = "TLB miss exceptions" }, {.pme_name="COP2_INSNS_EXECED", .pme_code = 0x00000f00, .pme_counters = 0x2, .pme_desc = "COP2 instructions executed" }, {.pme_name="FAILED_COND_STORES", .pme_code = 0x00000005, .pme_counters = 0x1, .pme_desc = "Failed conditional stores" }, {.pme_name="INSNS_EXECED", .pme_code = 0x0000010f, .pme_counters = 0x3, .pme_desc = "Instructions executed" }, {.pme_name="ICACHE_MISS", .pme_code = 0x00000009, .pme_counters = 0x1, .pme_desc = "Instruction cache miss" }, {.pme_name="COND_STORES_EXECED", .pme_code = 0x00000404, .pme_counters = 0x3, .pme_desc = "Conditional stores executed" }, {.pme_name="FP_INSNS_EXECED", .pme_code = 0x00000500, .pme_counters = 0x2, .pme_desc = "Floating-point instructions executed" }, {.pme_name="DTLB_MISSES", .pme_code = 0x00000008, .pme_counters = 0x1, .pme_desc = "DTLB miss" }, {.pme_name="BRANCHES_EXECED", .pme_code = 0x00000006, .pme_counters = 0x1, .pme_desc = "Branches executed" }, {.pme_name="CYCLES", .pme_code = 0x00000000, .pme_counters = 0x3, .pme_desc = "Cycles" }, {.pme_name="ITLB_MISSES", .pme_code = 0x00000007, .pme_counters = 0x1, .pme_desc = "ITLB miss" }, }; static pme_gen_mips64_entry_t gen_mips64_r10000_pe[] = { {.pme_name="BRANCHES_RESOLVED", .pme_code = 0x00000006, .pme_counters = 0x1, .pme_desc = "Branches resolved" }, {.pme_name="TLB_REFILL_EXCEPTIONS", .pme_code = 0x00000700, .pme_counters = 0x2, .pme_desc = "TLB refill exceptions" }, {.pme_name="EXTERNAL_INTERVENTION_RQ", .pme_code = 0x0000000c, .pme_counters = 0x1, .pme_desc = "External intervention requests" }, {.pme_name="STORES_GRADUATED", .pme_code = 0x00000300, .pme_counters = 0x2, .pme_desc = "Stores graduated" }, {.pme_name="SCACHE_WAY_MISPREDICTED_INSN", .pme_code = 0x0000000b, .pme_counters = 0x1, .pme_desc = "Secondary cache way mispredicted (instruction)" }, {.pme_name="INSTRUCTION_CACHE_MISSES", .pme_code = 0x00000009, .pme_counters = 0x1, .pme_desc = "Instruction cache misses" }, {.pme_name="SCACHE_MISSES_DATA", .pme_code = 0x00000a00, .pme_counters = 0x2, .pme_desc = "Secondary cache misses (data)" }, {.pme_name="QUADWORDS_WB_FROM_PRIMARY_DCACHE", .pme_code = 0x00000600, .pme_counters = 0x2, .pme_desc = "Quadwords written back from primary data cache" }, {.pme_name="EXTERNAL_INVALIDATE_RQ_HITS_SCACHE", .pme_code = 0x00000d00, .pme_counters = 0x2, .pme_desc = "External invalidate request is determined to have hit in secondary cache" }, {.pme_name="LOAD_PREFETC_SYNC_CACHEOP_ISSUED", .pme_code = 0x00000002, .pme_counters = 0x1, .pme_desc = "Load / prefetch / sync / CacheOp issued" }, {.pme_name="STORES_OR_STORE_PREF_TO_SHD_SCACHE_BLOCKS", .pme_code = 0x00000f00, .pme_counters = 0x2, .pme_desc = "Stores or prefetches with store hint to Shared secondary cache blocks" }, {.pme_name="STORE_COND_ISSUED", .pme_code = 0x00000004, .pme_counters = 0x1, .pme_desc = "Store conditional issued" }, {.pme_name="BRANCHES_MISPREDICTED", .pme_code = 0x00000800, .pme_counters = 0x2, .pme_desc = "Branches mispredicted" }, {.pme_name="EXTERNAL_INVALIDATE_RQ", .pme_code = 0x0000000d, .pme_counters = 0x1, .pme_desc = "External invalidate requests" }, {.pme_name="LOAD_PREFETC_SYNC_CACHEOP_GRADUATED", .pme_code = 0x00000200, .pme_counters = 0x2, .pme_desc = "Load / prefetch / sync / CacheOp graduated" }, {.pme_name="INSTRUCTIONS_ISSUED", .pme_code = 0x00000001, .pme_counters = 0x1, .pme_desc = "Instructions issued" }, {.pme_name="INSTRUCTION_GRADUATED", .pme_code = 0x0000000f, .pme_counters = 0x1, .pme_desc = "Instructions graduated" }, {.pme_name="EXTERNAL_INTERVENTION_RQ_HITS_SCACHE", .pme_code = 0x00000c00, .pme_counters = 0x2, .pme_desc = "External intervention request is determined to have hit in secondary cache" }, {.pme_name="SCACHE_MISSES_INSTRUCTION", .pme_code = 0x0000000a, .pme_counters = 0x1, .pme_desc = "Secondary cache misses (instruction)" }, {.pme_name="SCACHE_LOAD_STORE_CACHEOP_OPERATIONS", .pme_code = 0x00000900, .pme_counters = 0x2, .pme_desc = "Secondary cache load / store and cache-ops operations" }, {.pme_name="STORES_OR_STORE_PREF_TO_CLEANEXCLUSIVE_SCACHE_BLOCKS", .pme_code = 0x00000e00, .pme_counters = 0x2, .pme_desc = "Stores or prefetches with store hint to CleanExclusive secondary cache blocks" }, {.pme_name="INSTRUCTIONS_GRADUATED", .pme_code = 0x00000100, .pme_counters = 0x2, .pme_desc = "Instructions graduated" }, {.pme_name="FP_INSTRUCTON_GRADUATED", .pme_code = 0x00000500, .pme_counters = 0x2, .pme_desc = "Floating-point instructions graduated" }, {.pme_name="STORES_ISSUED", .pme_code = 0x00000003, .pme_counters = 0x1, .pme_desc = "Stores issued" }, {.pme_name="CYCLES", .pme_code = 0x00000000, .pme_counters = 0x3, .pme_desc = "Cycles" }, {.pme_name="CORRECTABLE_ECC_ERRORS_SCACHE", .pme_code = 0x00000008, .pme_counters = 0x1, .pme_desc = "Correctable ECC errors on secondary cache data" }, {.pme_name="QUADWORDS_WB_FROM_SCACHE", .pme_code = 0x00000007, .pme_counters = 0x1, .pme_desc = "Quadwords written back from secondary cache" }, {.pme_name="STORE_COND_GRADUATED", .pme_code = 0x00000400, .pme_counters = 0x2, .pme_desc = "Store conditional graduated" }, {.pme_name="FUNCTIONAL_UNIT_COMPLETION_CYCLES", .pme_code = 0x0000000e, .pme_counters = 0x1, .pme_desc = "Functional unit completion cycles" }, {.pme_name="FAILED_STORE_CONDITIONAL", .pme_code = 0x00000005, .pme_counters = 0x1, .pme_desc = "Failed store conditional" }, {.pme_name="SCACHE_WAY_MISPREDICTED_DATA", .pme_code = 0x00000b00, .pme_counters = 0x2, .pme_desc = "Secondary cache way mispredicted (data)" }, }; static pme_gen_mips64_entry_t gen_mips64_r12000_pe[] = { {.pme_name="INTERVENTION_REQUESTS", .pme_code = 0x0c0c0c0c, .pme_counters = 0xf, .pme_desc = "External intervention requests" }, {.pme_name="QUADWORDS", .pme_code = 0x16161616, .pme_counters = 0xf, .pme_desc = "Quadwords written back from primary data cache" }, {.pme_name="MISPREDICTED_BRANCHES", .pme_code = 0x18181818, .pme_counters = 0xf, .pme_desc = "Mispredicted branches" }, {.pme_name="DECODED_STORES", .pme_code = 0x03030303, .pme_counters = 0xf, .pme_desc = "Decoded stores" }, {.pme_name="TLB_MISSES", .pme_code = 0x17171717, .pme_counters = 0xf, .pme_desc = "TLB misses" }, {.pme_name="GRADUATED_FP_INSTRUCTIONS", .pme_code = 0x15151515, .pme_counters = 0xf, .pme_desc = "Graduated floating point instructions" }, {.pme_name="EXTERNAL_REQUESTS", .pme_code = 0x0d0d0d0d, .pme_counters = 0xf, .pme_desc = "External invalidate requests" }, {.pme_name="GRADUATED_STORES", .pme_code = 0x13131313, .pme_counters = 0xf, .pme_desc = "Graduated stores" }, {.pme_name="PREFETCH_MISSES_IN_DCACHE", .pme_code = 0x11111111, .pme_counters = 0xf, .pme_desc = "Primary data cache misses by prefetch instructions" }, {.pme_name="STORE_PREFETCH_EXCLUSIVE_SHARED_SC_BLOCK", .pme_code = 0x1f1f1f1f, .pme_counters = 0xf, .pme_desc = "Store/prefetch exclusive to shared block in secondary" }, {.pme_name="DECODED_LOADS", .pme_code = 0x02020202, .pme_counters = 0xf, .pme_desc = "Decoded loads" }, {.pme_name="GRADUATED_STORE_CONDITIONALS", .pme_code = 0x14141414, .pme_counters = 0xf, .pme_desc = "Graduated store conditionals" }, {.pme_name="INSTRUCTION_SECONDARY_CACHE_MISSES", .pme_code = 0x0a0a0a0a, .pme_counters = 0xf, .pme_desc = "Secondary cache misses (instruction)" }, {.pme_name="STATE_OF_EXTERNAL_INVALIDATION_HIT", .pme_code = 0x1d1d1d1d, .pme_counters = 0xf, .pme_desc = "State of external invalidation hits in secondary cache" }, {.pme_name="SECONDARY_CACHE_WAY_MISSPREDICTED", .pme_code = 0x0b0b0b0b, .pme_counters = 0xf, .pme_desc = "Secondary cache way mispredicted (instruction)" }, {.pme_name="DECODED_INSTRUCTIONS", .pme_code = 0x01010101, .pme_counters = 0xf, .pme_desc = "Decoded instructions" }, {.pme_name="SCACHE_MISSES", .pme_code = 0x1a1a1a1a, .pme_counters = 0xf, .pme_desc = "Secondary cache misses (data)" }, {.pme_name="ICACHE_MISSES", .pme_code = 0x09090909, .pme_counters = 0xf, .pme_desc = "Instruction cache misses" }, {.pme_name="SCACHE_WAY_MISPREDICTION", .pme_code = 0x1b1b1b1b, .pme_counters = 0xf, .pme_desc = "Misprediction from scache way prediction table (data)" }, {.pme_name="STATE_OF_SCACHE_INTERVENTION_HIT", .pme_code = 0x1c1c1c1c, .pme_counters = 0xf, .pme_desc = "State of external intervention hit in secondary cache" }, {.pme_name="GRADUATED_LOADS", .pme_code = 0x12121212, .pme_counters = 0xf, .pme_desc = "Graduated loads" }, {.pme_name="PREFETCH_INSTRUCTIONS_EXECUTED", .pme_code = 0x10101010, .pme_counters = 0xf, .pme_desc = "Executed prefetch instructions" }, {.pme_name="MISS_TABLE_OCCUPANCY", .pme_code = 0x04040404, .pme_counters = 0xf, .pme_desc = "Miss Handling Table Occupancy" }, {.pme_name="INSTRUCTIONS_GRADUATED", .pme_code = 0x0f0f0f0f, .pme_counters = 0xf, .pme_desc = "Instructions graduated" }, {.pme_name="QUADWORDS_WRITEBACK_FROM_SC", .pme_code = 0x07070707, .pme_counters = 0xf, .pme_desc = "Quadwords written back from secondary cache" }, {.pme_name="CORRECTABLE_ECC_ERRORS", .pme_code = 0x08080808, .pme_counters = 0xf, .pme_desc = "Correctable ECC errors on secondary cache data" }, {.pme_name="CYCLES", .pme_code = 0x00000000, .pme_counters = 0xf, .pme_desc = "Cycles" }, {.pme_name="RESOLVED_BRANCH_CONDITIONAL", .pme_code = 0x06060606, .pme_counters = 0xf, .pme_desc = "Resolved conditional branches" }, {.pme_name="STORE_PREFETCH_EXCLUSIVE_TO_CLEAN_SC_BLOCK", .pme_code = 0x1e1e1e1e, .pme_counters = 0xf, .pme_desc = "Store/prefetch exclusive to clean block in secondary cache" }, {.pme_name="FAILED_STORE_CONDITIONAL", .pme_code = 0x05050505, .pme_counters = 0xf, .pme_desc = "Failed store conditional" }, {.pme_name="DCACHE_MISSES", .pme_code = 0x19191919, .pme_counters = 0xf, .pme_desc = "Primary data cache misses" }, }; static pme_gen_mips64_entry_t gen_mips64_rm7000_pe[] = { {.pme_name="SLIP_CYCLES_PENDING_NON_BLKING_LOAD", .pme_code = 0x00001a1a, .pme_counters = 0x3, .pme_desc = "Slip cycles due to pending non-blocking loads" }, {.pme_name="STORE_INSTRUCTIONS_ISSUED", .pme_code = 0x00000505, .pme_counters = 0x3, .pme_desc = "Store instructions issued" }, {.pme_name="BRANCH_PREFETCHES", .pme_code = 0x00000707, .pme_counters = 0x3, .pme_desc = "Branch prefetches" }, {.pme_name="PCACHE_WRITEBACKS", .pme_code = 0x00001414, .pme_counters = 0x3, .pme_desc = "Primary cache writebacks" }, {.pme_name="STALL_CYCLES_PENDING_NON_BLKING_LOAD", .pme_code = 0x00001f1f, .pme_counters = 0x3, .pme_desc = "Stall cycles due to pending non-blocking loads - stall start of exception" }, {.pme_name="STALL_CYCLES", .pme_code = 0x00000909, .pme_counters = 0x3, .pme_desc = "Stall cycles" }, {.pme_name="CACHE_MISSES", .pme_code = 0x00001616, .pme_counters = 0x3, .pme_desc = "Cache misses" }, {.pme_name="DUAL_ISSUED_PAIRS", .pme_code = 0x00000606, .pme_counters = 0x3, .pme_desc = "Dual issued pairs" }, {.pme_name="SLIP_CYCLES_DUE_MULTIPLIER_BUSY", .pme_code = 0x00001818, .pme_counters = 0x3, .pme_desc = "Slip Cycles due to multiplier busy" }, {.pme_name="INTEGER_INSTRUCTIONS_ISSUED", .pme_code = 0x00000303, .pme_counters = 0x3, .pme_desc = "Integer instructions issued" }, {.pme_name="SCACHE_WRITEBACKS", .pme_code = 0x00001313, .pme_counters = 0x3, .pme_desc = "Secondary cache writebacks" }, {.pme_name="DCACHE_MISS_STALL_CYCLES", .pme_code = 0x00001515, .pme_counters = 0x3, .pme_desc = "Dcache miss stall cycles (cycles where both cache miss tokens taken and a third try is requested)" }, {.pme_name="MULTIPLIER_STALL_CYCLES", .pme_code = 0x00001e1e, .pme_counters = 0x3, .pme_desc = "Multiplier stall cycles" }, {.pme_name="WRITE_BUFFER_FULL_STALL_CYCLES", .pme_code = 0x00001c1c, .pme_counters = 0x3, .pme_desc = "Write buffer full stall cycles" }, {.pme_name="FP_INSTRUCTIONS_ISSUED", .pme_code = 0x00000202, .pme_counters = 0x3, .pme_desc = "Floating-point instructions issued" }, {.pme_name="JTLB_DATA_MISSES", .pme_code = 0x00001010, .pme_counters = 0x3, .pme_desc = "Joint TLB data misses" }, {.pme_name="FP_EXCEPTION_STALL_CYCLES", .pme_code = 0x00001717, .pme_counters = 0x3, .pme_desc = "FP possible exception cycles" }, {.pme_name="SCACHE_MISSES", .pme_code = 0x00000a0a, .pme_counters = 0x3, .pme_desc = "Secondary cache misses" }, {.pme_name="BRANCHES_ISSUED", .pme_code = 0x00001212, .pme_counters = 0x3, .pme_desc = "Branches issued" }, {.pme_name="ICACHE_MISSES", .pme_code = 0x00000b0b, .pme_counters = 0x3, .pme_desc = "Instruction cache misses" }, {.pme_name="INSTRUCTIONS_ISSUED", .pme_code = 0x00000101, .pme_counters = 0x3, .pme_desc = "Total instructions issued" }, {.pme_name="JTLB_INSTRUCTION_MISSES", .pme_code = 0x00000f0f, .pme_counters = 0x3, .pme_desc = "Joint TLB instruction misses" }, {.pme_name="LOAD_INSTRUCTIONS_ISSUED", .pme_code = 0x00000404, .pme_counters = 0x3, .pme_desc = "Load instructions issued" }, {.pme_name="EXTERNAL_CACHE_MISSES", .pme_code = 0x00000808, .pme_counters = 0x3, .pme_desc = "External Cache Misses" }, {.pme_name="BRANCHES_TAKEN", .pme_code = 0x00001111, .pme_counters = 0x3, .pme_desc = "Branches taken" }, {.pme_name="DTLB_MISSES", .pme_code = 0x00000d0d, .pme_counters = 0x3, .pme_desc = "Data TLB misses" }, {.pme_name="CACHE_INSTRUCTION_STALL_CYCLES", .pme_code = 0x00001d1d, .pme_counters = 0x3, .pme_desc = "Cache instruction stall cycles" }, {.pme_name="CYCLES", .pme_code = 0x00000000, .pme_counters = 0x3, .pme_desc = "Clock cycles" }, {.pme_name="COP0_SLIP_CYCLES", .pme_code = 0x00001919, .pme_counters = 0x3, .pme_desc = "Coprocessor 0 slip cycles" }, {.pme_name="ITLB_MISSES", .pme_code = 0x00000e0e, .pme_counters = 0x3, .pme_desc = "Instruction TLB misses" }, {.pme_name="DCACHE_MISSES", .pme_code = 0x00000c0c, .pme_counters = 0x3, .pme_desc = "Data cache misses" }, }; static pme_gen_mips64_entry_t gen_mips64_rm9000_pe[] = { {.pme_name="FP_POSSIBLE_EXCEPTION_CYCLES", .pme_code = 0x00001717, .pme_counters = 0x3, .pme_desc = "Floating-point possible exception cycles" }, {.pme_name="STORE_INSTRUCTIONS_ISSUED", .pme_code = 0x00000505, .pme_counters = 0x3, .pme_desc = "Store instructions issued" }, {.pme_name="STALL_CYCLES", .pme_code = 0x00000909, .pme_counters = 0x3, .pme_desc = "Stall cycles" }, {.pme_name="L2_WRITEBACKS", .pme_code = 0x00001313, .pme_counters = 0x3, .pme_desc = "L2 cache writebacks" }, {.pme_name="NONBLOCKING_LOAD_SLIP_CYCLES", .pme_code = 0x00001a1a, .pme_counters = 0x3, .pme_desc = "Slip cycles due to pending non-blocking loads" }, {.pme_name="NONBLOCKING_LOAD_PENDING_EXCEPTION_STALL_CYCLES", .pme_code = 0x00001e1e, .pme_counters = 0x3, .pme_desc = "Stall cycles due to pending non-blocking loads - stall start of exception" }, {.pme_name="BRANCH_MISSPREDICTS", .pme_code = 0x00000707, .pme_counters = 0x3, .pme_desc = "Branch mispredictions" }, {.pme_name="DCACHE_MISS_STALL_CYCLES", .pme_code = 0x00001515, .pme_counters = 0x3, .pme_desc = "Dcache-miss stall cycles" }, {.pme_name="WRITE_BUFFER_FULL_STALL_CYCLES", .pme_code = 0x00001b1b, .pme_counters = 0x3, .pme_desc = "Stall cycles due to a full write buffer" }, {.pme_name="INT_INSTRUCTIONS_ISSUED", .pme_code = 0x00000303, .pme_counters = 0x3, .pme_desc = "Integer instructions issued" }, {.pme_name="FP_INSTRUCTIONS_ISSUED", .pme_code = 0x00000202, .pme_counters = 0x3, .pme_desc = "Floating-point instructions issued" }, {.pme_name="JTLB_DATA_MISSES", .pme_code = 0x00001010, .pme_counters = 0x3, .pme_desc = "Joint TLB data misses" }, {.pme_name="L2_CACHE_MISSES", .pme_code = 0x00000a0a, .pme_counters = 0x3, .pme_desc = "L2 cache misses" }, {.pme_name="DCACHE_WRITEBACKS", .pme_code = 0x00001414, .pme_counters = 0x3, .pme_desc = "Dcache writebacks" }, {.pme_name="BRANCHES_ISSUED", .pme_code = 0x00001212, .pme_counters = 0x3, .pme_desc = "Branch instructions issued" }, {.pme_name="ICACHE_MISSES", .pme_code = 0x00000b0b, .pme_counters = 0x3, .pme_desc = "Icache misses" }, {.pme_name="INSTRUCTIONS_ISSUED", .pme_code = 0x00000101, .pme_counters = 0x3, .pme_desc = "Instructions issued" }, {.pme_name="MULTIPLIER_BUSY_SLIP_CYCLES", .pme_code = 0x00001818, .pme_counters = 0x3, .pme_desc = "Slip cycles due to busy multiplier" }, {.pme_name="INSTRUCTIONS_DUAL_ISSUED", .pme_code = 0x00000606, .pme_counters = 0x3, .pme_desc = "Dual-issued instruction pairs" }, {.pme_name="CACHE_INSN_STALL_CYCLES", .pme_code = 0x00001c1c, .pme_counters = 0x3, .pme_desc = "Stall cycles due to cache instructions" }, {.pme_name="JTLB_INSTRUCTION_MISSES", .pme_code = 0x00000f0f, .pme_counters = 0x3, .pme_desc = "Joint TLB instruction misses" }, {.pme_name="LOAD_INSTRUCTIONS_ISSUED", .pme_code = 0x00000404, .pme_counters = 0x3, .pme_desc = "Load instructions issued" }, {.pme_name="CACHE_REMISSES", .pme_code = 0x00001616, .pme_counters = 0x3, .pme_desc = "Cache remisses" }, {.pme_name="BRANCHES_TAKEN", .pme_code = 0x00001111, .pme_counters = 0x3, .pme_desc = "Branches taken" }, {.pme_name="DTLB_MISSES", .pme_code = 0x00000d0d, .pme_counters = 0x3, .pme_desc = "Data TLB misses" }, {.pme_name="CYCLES", .pme_code = 0x00000000, .pme_counters = 0x3, .pme_desc = "Processor clock cycles" }, {.pme_name="COP0_SLIP_CYCLES", .pme_code = 0x00001919, .pme_counters = 0x3, .pme_desc = "Co-processor 0 slip cycles" }, {.pme_name="ITLB_MISSES", .pme_code = 0x00000e0e, .pme_counters = 0x3, .pme_desc = "Instruction TLB misses" }, {.pme_name="DCACHE_MISSES", .pme_code = 0x00000c0c, .pme_counters = 0x3, .pme_desc = "Dcache misses" }, }; static pme_gen_mips64_entry_t gen_mips64_sb1_pe[] = { {.pme_name="DATA_DEPENDENCY_REPLAY", .pme_code = 0x1e1e1e1e, .pme_counters = 0xf, .pme_desc = "Data dependency replay" }, {.pme_name="DCACHE_READ_MISS", .pme_code = 0x0f0f0f00, .pme_counters = 0xe, .pme_desc = "Dcache read results in a miss" }, {.pme_name="R_RESP_OTHER_CORE_D_MOD", .pme_code = 0x19191900, .pme_counters = 0xe, .pme_desc = "Read response comes from the other core with D_MOD set" }, {.pme_name="RQ_LENGTH", .pme_code = 0x01010100, .pme_counters = 0xe, .pme_desc = "Read queue length" }, {.pme_name="READ_RQ_NOPS_SENT_TO_ABUS", .pme_code = 0x14141400, .pme_counters = 0xe, .pme_desc = "Read requests and NOPs sent to ZB Abus" }, {.pme_name="R_RESP_OTHER_CORE", .pme_code = 0x18181800, .pme_counters = 0xe, .pme_desc = "Read response comes from the other core" }, {.pme_name="SNOOP_RQ_HITS", .pme_code = 0x16161600, .pme_counters = 0xe, .pme_desc = "Snoop request hits anywhere" }, {.pme_name="LOAD_SURVIVED_STAGE4", .pme_code = 0x08080800, .pme_counters = 0xe, .pme_desc = "Load survived stage 4" }, {.pme_name="BRANCH_PREDICTED_TAKEN", .pme_code = 0x2e2e2e00, .pme_counters = 0xe, .pme_desc = "Predicted taken conditional branch" }, {.pme_name="ISSUE_L1", .pme_code = 0x29292900, .pme_counters = 0xe, .pme_desc = "Issue to L0" }, {.pme_name="ANY_REPLAY", .pme_code = 0x1f1f1f1f, .pme_counters = 0xf, .pme_desc = "Any replay except mispredict" }, {.pme_name="LD_ST_HITS_PREFETCH_IN_QUEUE", .pme_code = 0x06060600, .pme_counters = 0xe, .pme_desc = "Load/store hits prefetch in read queue" }, {.pme_name="NOT_DATA_READY", .pme_code = 0x23232300, .pme_counters = 0xe, .pme_desc = "Not data ready" }, {.pme_name="DCFIFO", .pme_code = 0x1c1c1c1c, .pme_counters = 0xf, .pme_desc = "DCFIFO" }, {.pme_name="ISSUE_E1", .pme_code = 0x2b2b2b00, .pme_counters = 0xe, .pme_desc = "Issue to E1" }, {.pme_name="PREFETCH_HITS_CACHE_OR_READ_Q", .pme_code = 0x05050500, .pme_counters = 0xe, .pme_desc = "Prefetch hits in cache or read queue" }, {.pme_name="BRANCH_STAGE4", .pme_code = 0x2c2c2c00, .pme_counters = 0xe, .pme_desc = "Branch survived stage 4" }, {.pme_name="SNOOP_ADDR_Q_FULL", .pme_code = 0x17171700, .pme_counters = 0xe, .pme_desc = "Snoop address queue is full" }, {.pme_name="CONSUMER_WAITING_FOR_LOAD", .pme_code = 0x22222200, .pme_counters = 0xe, .pme_desc = "load consumer waiting for dfill" }, {.pme_name="VICTIM_WRITEBACK", .pme_code = 0x0d0d0d00, .pme_counters = 0xe, .pme_desc = "A writeback occurs due to replacement" }, {.pme_name="BRANCH_MISSPREDICTS", .pme_code = 0x2f2f2f00, .pme_counters = 0xe, .pme_desc = "Branch mispredicts" }, {.pme_name="UPGRADE_SHARED_TO_EXCLUSIVE", .pme_code = 0x07070700, .pme_counters = 0xe, .pme_desc = "A line is upgraded from shared to exclusive" }, {.pme_name="READ_HITS_READ_Q", .pme_code = 0x04040400, .pme_counters = 0xe, .pme_desc = "Read hits in read queue" }, {.pme_name="INSN_STAGE4", .pme_code = 0x27272700, .pme_counters = 0xe, .pme_desc = "One or more instructions survives stage 4" }, {.pme_name="UNCACHED_RQ_LENGTH", .pme_code = 0x02020200, .pme_counters = 0xe, .pme_desc = "Number of valid uncached entries in read queue" }, {.pme_name="READ_RQ_SENT_TO_ABUS", .pme_code = 0x17171700, .pme_counters = 0xe, .pme_desc = "Read requests sent to ZB Abus" }, {.pme_name="DCACHE_FILL_SHARED_LINE", .pme_code = 0x0b0b0b00, .pme_counters = 0xe, .pme_desc = "Dcache is filled with shared line" }, {.pme_name="ISSUE_CONFLICT_DUE_IMISS", .pme_code = 0x25252500, .pme_counters = 0xe, .pme_desc = "issue conflict due to imiss using LS0" }, {.pme_name="NO_VALID_INSN", .pme_code = 0x21212100, .pme_counters = 0xe, .pme_desc = "No valid instr to issue" }, {.pme_name="ISSUE_E0", .pme_code = 0x2a2a2a00, .pme_counters = 0xe, .pme_desc = "Issue to E0" }, {.pme_name="INSN_SURVIVED_STAGE7", .pme_code = 0x00000000, .pme_counters = 0xe, .pme_desc = "Instruction survived stage 7" }, {.pme_name="BRANCH_REALLY_TAKEN", .pme_code = 0x2d2d2d00, .pme_counters = 0xe, .pme_desc = "Conditional branch was really taken" }, {.pme_name="STORE_COND_FAILED", .pme_code = 0x1a1a1a00, .pme_counters = 0xe, .pme_desc = "Failed store conditional" }, {.pme_name="MAX_ISSUE", .pme_code = 0x20202000, .pme_counters = 0xe, .pme_desc = "Max issue" }, {.pme_name="BIU_STALLS_ON_ZB_ADDR_BUS", .pme_code = 0x11111100, .pme_counters = 0xe, .pme_desc = "BIU stalls on ZB addr bus" }, {.pme_name="STORE_SURVIVED_STAGE4", .pme_code = 0x09090900, .pme_counters = 0xe, .pme_desc = "Store survived stage 4" }, {.pme_name="RESOURCE_CONSTRAINT", .pme_code = 0x24242400, .pme_counters = 0xe, .pme_desc = "Resource (L0/1 E0/1) constraint" }, {.pme_name="DCACHE_FILL_REPLAY", .pme_code = 0x1b1b1b1b, .pme_counters = 0xf, .pme_desc = "Dcache fill replay" }, {.pme_name="BIU_STALLS_ON_ZB_DATA_BUS", .pme_code = 0x12121200, .pme_counters = 0xe, .pme_desc = "BIU stalls on ZB data bus" }, {.pme_name="ISSUE_CONFLICT_DUE_DFILL", .pme_code = 0x26262600, .pme_counters = 0xe, .pme_desc = "issue conflict due to dfill using LS0/1" }, {.pme_name="WRITEBACK_RETURNS", .pme_code = 0x0f0f0f00, .pme_counters = 0xe, .pme_desc = "Number of instruction returns" }, {.pme_name="DCACHE_FILLED_SHD_NONC_EXC", .pme_code = 0x0a0a0a00, .pme_counters = 0xe, .pme_desc = "Dcache is filled (shared, nonc, exclusive)" }, {.pme_name="ISSUE_L0", .pme_code = 0x28282800, .pme_counters = 0xe, .pme_desc = "Issue to L0" }, {.pme_name="CYCLES", .pme_code = 0x10101010, .pme_counters = 0xf, .pme_desc = "Elapsed cycles" }, {.pme_name="MBOX_RQ_WHEN_BIU_BUSY", .pme_code = 0x0e0e0e00, .pme_counters = 0xe, .pme_desc = "MBOX requests to BIU when BIU busy" }, {.pme_name="MBOX_REPLAY", .pme_code = 0x1d1d1d1d, .pme_counters = 0xf, .pme_desc = "MBOX replay" }, }; static pme_gen_mips64_entry_t gen_mips64_vr5432_pe[] = { {.pme_name="INSTRUCTIONS_EXECUTED", .pme_code = 0x00000101, .pme_counters = 0x3, .pme_desc = "(Instructions executed)/2 and truncated" }, {.pme_name="JTLB_REFILLS", .pme_code = 0x00000707, .pme_counters = 0x3, .pme_desc = "JTLB refills" }, {.pme_name="BRANCHES", .pme_code = 0x00000404, .pme_counters = 0x3, .pme_desc = "Branch execution (no jumps or jump registers)" }, {.pme_name="FP_INSTRUCTIONS", .pme_code = 0x00000505, .pme_counters = 0x3, .pme_desc = "(FP instruction execution) / 2 and truncated excluding cp1 loads and stores" }, {.pme_name="BRANCHES_MISPREDICTED", .pme_code = 0x00000a0a, .pme_counters = 0x3, .pme_desc = "Branches mispredicted" }, {.pme_name="DOUBLEWORDS_FLUSHED", .pme_code = 0x00000606, .pme_counters = 0x3, .pme_desc = "Doublewords flushed to main memory (no uncached stores)" }, {.pme_name="ICACHE_MISSES", .pme_code = 0x00000909, .pme_counters = 0x3, .pme_desc = "Instruction cache misses (no D-cache misses)" }, {.pme_name="LOAD_PREF_CACHE_INSTRUCTIONS", .pme_code = 0x00000202, .pme_counters = 0x3, .pme_desc = "Load, prefetch/CacheOps execution (no sync)" }, {.pme_name="CYCLES", .pme_code = 0x00000000, .pme_counters = 0x3, .pme_desc = "Processor cycles (PClock)" }, {.pme_name="DCACHE_MISSES", .pme_code = 0x00000808, .pme_counters = 0x3, .pme_desc = "Data cache misses (no I-cache misses)" }, {.pme_name="STORES", .pme_code = 0x00000303, .pme_counters = 0x3, .pme_desc = "Store execution" }, }; static pme_gen_mips64_entry_t gen_mips64_vr5500_pe[] = { {.pme_name="INSTRUCTIONS_EXECUTED", .pme_code = 0x00000101, .pme_counters = 0x3, .pme_desc = "Instructions executed" }, {.pme_name="JTLB_REFILLS", .pme_code = 0x00000707, .pme_counters = 0x3, .pme_desc = "TLB refill" }, {.pme_name="BRANCHES", .pme_code = 0x00000404, .pme_counters = 0x3, .pme_desc = "Execution of branch instruction" }, {.pme_name="FP_INSTRUCTIONS", .pme_code = 0x00000505, .pme_counters = 0x3, .pme_desc = "Execution of floating-point instruction" }, {.pme_name="BRANCHES_MISPREDICTED", .pme_code = 0x00000a0a, .pme_counters = 0x3, .pme_desc = "Branch prediction miss" }, {.pme_name="DOUBLEWORDS_FLUSHED", .pme_code = 0x00000606, .pme_counters = 0x3, .pme_desc = "Doubleword flush to main memory" }, {.pme_name="ICACHE_MISSES", .pme_code = 0x00000909, .pme_counters = 0x3, .pme_desc = "Instruction cache miss" }, {.pme_name="LOAD_PREF_CACHE_INSTRUCTIONS", .pme_code = 0x00000202, .pme_counters = 0x3, .pme_desc = "Execution of load/prefetch/cache instruction" }, {.pme_name="CYCLES", .pme_code = 0x00000000, .pme_counters = 0x3, .pme_desc = "Processor clock cycles" }, {.pme_name="DCACHE_MISSES", .pme_code = 0x00000808, .pme_counters = 0x3, .pme_desc = "Data cache miss" }, {.pme_name="STORES", .pme_code = 0x00000303, .pme_counters = 0x3, .pme_desc = "Execution of store instruction" }, }; papi-5.5.1/src/libpfm-3.y/lib/pfmlib_powerpc_priv.h0000644000307100002310000000235713013651450022120 0ustar yarkhangraduate/* * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * pfmlib_pentium4_priv.h * * Structures and definitions for use in the Pentium4/Xeon/EM64T libpfm code. */ #ifndef _PFMLIB_POWERPC_PRIV_H_ #define _PFMLIB_POWERPC_PRIV_H_ #endif papi-5.5.1/src/libpfm-3.y/lib/pfmlib_gen_mips64_priv.h0000644000307100002310000000334113013651450022406 0ustar yarkhangraduate/* * Contributed by Philip Mucci based on code from * Copyright (c) 2004-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #ifndef __PFMLIB_GEN_MIPS64_PRIV_H__ #define __PFMLIB_GEN_MIPS64_PRIV_H__ typedef struct { char *pme_name; char *pme_desc; /* text description of the event */ unsigned int pme_code; /* event mask, holds room for four events, low 8 bits cntr0, ... high 8 bits cntr3 */ unsigned int pme_counters; } pme_gen_mips64_entry_t; #endif /* __PFMLIB_GEN_MIPS64_PRIV_H__ */ papi-5.5.1/src/libpfm-3.y/lib/pfmlib_core.c0000644000307100002310000005650313013651450020326 0ustar yarkhangraduate/* * pfmlib_core.c : Intel Core PMU * * Copyright (c) 2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * * This file implements support for Intel Core PMU as specified in the following document: * "IA-32 Intel Architecture Software Developer's Manual - Volume 3B: System * Programming Guide" * * Core PMU = architectural perfmon v2 + PEBS */ #include #include #include #include #include /* public headers */ #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_core_priv.h" #include "core_events.h" /* let's define some handy shortcuts! */ #define sel_event_select perfevtsel.sel_event_select #define sel_unit_mask perfevtsel.sel_unit_mask #define sel_usr perfevtsel.sel_usr #define sel_os perfevtsel.sel_os #define sel_edge perfevtsel.sel_edge #define sel_pc perfevtsel.sel_pc #define sel_int perfevtsel.sel_int #define sel_en perfevtsel.sel_en #define sel_inv perfevtsel.sel_inv #define sel_cnt_mask perfevtsel.sel_cnt_mask #define is_pebs(i) (core_pe[i].pme_flags & PFMLIB_CORE_PEBS) /* * Description of the PMC register mappings: * * 0 -> PMC0 -> PERFEVTSEL0 * 1 -> PMC1 -> PERFEVTSEL1 * 16 -> PMC16 -> FIXED_CTR_CTRL * 17 -> PMC17 -> PEBS_ENABLED * * Description of the PMD register mapping: * * 0 -> PMD0 -> PMC0 * 1 -> PMD1 -> PMC1 * 16 -> PMD2 -> FIXED_CTR0 * 17 -> PMD3 -> FIXED_CTR1 * 18 -> PMD4 -> FIXED_CTR2 */ #define CORE_SEL_BASE 0x186 #define CORE_CTR_BASE 0xc1 #define FIXED_CTR_BASE 0x309 #define PFMLIB_CORE_ALL_FLAGS \ (PFM_CORE_SEL_INV|PFM_CORE_SEL_EDGE) static pfmlib_regmask_t core_impl_pmcs, core_impl_pmds; static int highest_counter; static int pfm_core_detect(void) { int ret; int family, model; char buffer[128]; ret = __pfm_getcpuinfo_attr("vendor_id", buffer, sizeof(buffer)); if (ret == -1) return PFMLIB_ERR_NOTSUPP; if (strcmp(buffer, "GenuineIntel")) return PFMLIB_ERR_NOTSUPP; ret = __pfm_getcpuinfo_attr("cpu family", buffer, sizeof(buffer)); if (ret == -1) return PFMLIB_ERR_NOTSUPP; family = atoi(buffer); ret = __pfm_getcpuinfo_attr("model", buffer, sizeof(buffer)); if (ret == -1) return PFMLIB_ERR_NOTSUPP; if (family != 6) return PFMLIB_ERR_NOTSUPP; model = atoi(buffer); switch(model) { case 15: /* Merom */ case 23: /* Penryn */ case 29: /* Dunnington */ break; default: return PFMLIB_ERR_NOTSUPP; } return PFMLIB_SUCCESS; } static int pfm_core_init(void) { int i; pfm_regmask_set(&core_impl_pmcs, 0); pfm_regmask_set(&core_impl_pmcs, 1); pfm_regmask_set(&core_impl_pmcs, 16); pfm_regmask_set(&core_impl_pmcs, 17); pfm_regmask_set(&core_impl_pmds, 0); pfm_regmask_set(&core_impl_pmds, 1); pfm_regmask_set(&core_impl_pmds, 16); pfm_regmask_set(&core_impl_pmds, 17); pfm_regmask_set(&core_impl_pmds, 18); /* lbr */ pfm_regmask_set(&core_impl_pmds, 19); for(i=0; i < 8; i++) pfm_regmask_set(&core_impl_pmds, i); highest_counter = 18; return PFMLIB_SUCCESS; } static int pfm_core_is_fixed(pfmlib_event_t *e, unsigned int f) { unsigned int fl, flc, i; unsigned int mask = 0; fl = core_pe[e->event].pme_flags; /* * first pass: check if event as a whole supports fixed counters */ switch(f) { case 0: mask = PFMLIB_CORE_FIXED0; break; case 1: mask = PFMLIB_CORE_FIXED1; break; case 2: mask = PFMLIB_CORE_FIXED2_ONLY; break; default: return 0; } if (fl & mask) return 1; /* * second pass: check if unit mask support fixed counter * * reject if mask not found OR if not all unit masks have * same fixed counter mask */ flc = 0; for(i=0; i < e->num_masks; i++) { fl = core_pe[e->event].pme_umasks[e->unit_masks[i]].pme_flags; if (fl & mask) flc++; } return flc > 0 && flc == e->num_masks ? 1 : 0; } /* * IMPORTANT: the interface guarantees that pfp_pmds[] elements are returned in the order the events * were submitted. */ static int pfm_core_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_core_input_param_t *param, pfmlib_output_param_t *outp) { #define HAS_OPTIONS(x) (cntrs && (cntrs[x].flags || cntrs[x].cnt_mask)) #define is_fixed_pmc(a) (a == 16 || a == 17 || a == 18) pfmlib_core_counter_t *cntrs; pfm_core_sel_reg_t reg; pfmlib_event_t *e; pfmlib_reg_t *pc, *pd; pfmlib_regmask_t *r_pmcs; uint64_t val; unsigned long plm; unsigned long long fixed_ctr; unsigned int npc, npmc0, npmc1, nf2; unsigned int i, j, n, k, ucode, use_pebs = 0, done_pebs; unsigned int assign_pc[PMU_CORE_NUM_COUNTERS]; unsigned int next_gen, last_gen; npc = npmc0 = npmc1 = nf2 = 0; e = inp->pfp_events; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; n = inp->pfp_event_count; r_pmcs = &inp->pfp_unavail_pmcs; cntrs = param ? param->pfp_core_counters : NULL; use_pebs = param ? param->pfp_core_pebs.pebs_used : 0; if (n > PMU_CORE_NUM_COUNTERS) return PFMLIB_ERR_TOOMANY; /* * initilize to empty */ for(i=0; i < PMU_CORE_NUM_COUNTERS; i++) assign_pc[i] = -1; /* * error checking */ for(i=0; i < n; i++) { /* * only supports two priv levels for perf counters */ if (e[i].plm & (PFM_PLM1|PFM_PLM2)) return PFMLIB_ERR_INVAL; /* * check for valid flags */ if (cntrs && cntrs[i].flags & ~PFMLIB_CORE_ALL_FLAGS) return PFMLIB_ERR_INVAL; if (core_pe[e[i].event].pme_flags & PFMLIB_CORE_UMASK_NCOMBO && e[i].num_masks > 1) { DPRINT("events does not support unit mask combination\n"); return PFMLIB_ERR_NOASSIGN; } /* * check event-level single register constraint (PMC0, PMC1, FIXED_CTR2) * fail if more than two events requested for the same counter */ if (core_pe[e[i].event].pme_flags & PFMLIB_CORE_PMC0) { if (++npmc0 > 1) { DPRINT("two events compete for a PMC0\n"); return PFMLIB_ERR_NOASSIGN; } } /* * check if PMC1 is available and if only one event is dependent on it */ if (core_pe[e[i].event].pme_flags & PFMLIB_CORE_PMC1) { if (++npmc1 > 1) { DPRINT("two events compete for a PMC1\n"); return PFMLIB_ERR_NOASSIGN; } } /* * UNHALTED_REFERENCE_CYCLES can only be measured on FIXED_CTR2 */ if (core_pe[e[i].event].pme_flags & PFMLIB_CORE_FIXED2_ONLY) { if (++nf2 > 1) { DPRINT("two events compete for FIXED_CTR2\n"); return PFMLIB_ERR_NOASSIGN; } if (HAS_OPTIONS(i)) { DPRINT("fixed counters do not support inversion/counter-mask\n"); return PFMLIB_ERR_NOASSIGN; } } /* * unit-mask level constraint checking (PMC0, PMC1, FIXED_CTR2) */ for(j=0; j < e[i].num_masks; j++) { unsigned int flags; flags = core_pe[e[i].event].pme_umasks[e[i].unit_masks[j]].pme_flags; if (flags & PFMLIB_CORE_FIXED2_ONLY) { if (++nf2 > 1) { DPRINT("two events compete for FIXED_CTR2\n"); return PFMLIB_ERR_NOASSIGN; } if (HAS_OPTIONS(i)) { DPRINT("fixed counters do not support inversion/counter-mask\n"); return PFMLIB_ERR_NOASSIGN; } } } } next_gen = 0; /* first generic counter */ last_gen = 1; /* last generic counter */ /* * strongest constraint first: works only in IA32_PMC0, IA32_PMC1, FIXED_CTR2 * * When PEBS is used, we pick the first PEBS event and * place it into PMC0. Subsequent PEBS events, will go * in the other counters. */ done_pebs = 0; for(i=0; i < n; i++) { if ((core_pe[e[i].event].pme_flags & PFMLIB_CORE_PMC0) || (use_pebs && pfm_core_is_pebs(e+i) && done_pebs == 0)) { if (pfm_regmask_isset(r_pmcs, 0)) return PFMLIB_ERR_NOASSIGN; assign_pc[i] = 0; next_gen = 1; done_pebs = 1; } if (core_pe[e[i].event].pme_flags & PFMLIB_CORE_PMC1) { if (pfm_regmask_isset(r_pmcs, 1)) return PFMLIB_ERR_NOASSIGN; assign_pc[i] = 1; if (next_gen == 1) next_gen = 2; else next_gen = 0; } } /* * next constraint: fixed counters * * We abuse the mapping here for assign_pc to make it easier * to provide the correct values for pd[]. * We use: * - 16 : fixed counter 0 (pmc16, pmd16) * - 17 : fixed counter 1 (pmc16, pmd17) * - 18 : fixed counter 1 (pmc16, pmd18) */ fixed_ctr = pfm_regmask_isset(r_pmcs, 16) ? 0 : 0x7; if (fixed_ctr) { for(i=0; i < n; i++) { /* fixed counters do not support event options (filters) */ if (HAS_OPTIONS(i) || (use_pebs && pfm_core_is_pebs(e+i))) continue; if ((fixed_ctr & 0x1) && pfm_core_is_fixed(e+i, 0)) { assign_pc[i] = 16; fixed_ctr &= ~1; } if ((fixed_ctr & 0x2) && pfm_core_is_fixed(e+i, 1)) { assign_pc[i] = 17; fixed_ctr &= ~2; } if ((fixed_ctr & 0x4) && pfm_core_is_fixed(e+i, 2)) { assign_pc[i] = 18; fixed_ctr &= ~4; } } } /* * assign what is left */ for(i=0; i < n; i++) { if (assign_pc[i] == -1) { for(; next_gen <= last_gen; next_gen++) { DPRINT("i=%d next_gen=%d last=%d isset=%d\n", i, next_gen, last_gen, pfm_regmask_isset(r_pmcs, next_gen)); if (!pfm_regmask_isset(r_pmcs, next_gen)) break; } if (next_gen <= last_gen) assign_pc[i] = next_gen++; else { DPRINT("cannot assign generic counters\n"); return PFMLIB_ERR_NOASSIGN; } } } j = 0; /* setup fixed counters */ reg.val = 0; k = 0; for (i=0; i < n ; i++ ) { if (!is_fixed_pmc(assign_pc[i])) continue; val = 0; /* if plm is 0, then assume not specified per-event and use default */ plm = e[i].plm ? e[i].plm : inp->pfp_dfl_plm; if (plm & PFM_PLM0) val |= 1ULL; if (plm & PFM_PLM3) val |= 2ULL; val |= 1ULL << 3; /* force APIC int (kernel may force it anyway) */ reg.val |= val << ((assign_pc[i]-16)<<2); } if (reg.val) { pc[npc].reg_num = 16; pc[npc].reg_value = reg.val; pc[npc].reg_addr = 0x38D; pc[npc].reg_alt_addr = 0x38D; __pfm_vbprintf("[FIXED_CTRL(pmc%u)=0x%"PRIx64" pmi0=1 en0=0x%"PRIx64" pmi1=1 en1=0x%"PRIx64" pmi2=1 en2=0x%"PRIx64"] ", pc[npc].reg_num, reg.val, reg.val & 0x3ULL, (reg.val>>4) & 0x3ULL, (reg.val>>8) & 0x3ULL); if ((fixed_ctr & 0x1) == 0) __pfm_vbprintf("INSTRUCTIONS_RETIRED "); if ((fixed_ctr & 0x2) == 0) __pfm_vbprintf("UNHALTED_CORE_CYCLES "); if ((fixed_ctr & 0x4) == 0) __pfm_vbprintf("UNHALTED_REFERENCE_CYCLES "); __pfm_vbprintf("\n"); npc++; if ((fixed_ctr & 0x1) == 0) __pfm_vbprintf("[FIXED_CTR0(pmd16)]\n"); if ((fixed_ctr & 0x2) == 0) __pfm_vbprintf("[FIXED_CTR1(pmd17)]\n"); if ((fixed_ctr & 0x4) == 0) __pfm_vbprintf("[FIXED_CTR2(pmd18)]\n"); } for (i=0; i < n ; i++ ) { /* skip fixed counters */ if (is_fixed_pmc(assign_pc[i])) continue; reg.val = 0; /* assume reserved bits are zerooed */ /* if plm is 0, then assume not specified per-event and use default */ plm = e[i].plm ? e[i].plm : inp->pfp_dfl_plm; val = core_pe[e[i].event].pme_code; reg.sel_event_select = val & 0xff; ucode = (val >> 8) & 0xff; for(k=0; k < e[i].num_masks; k++) { ucode |= core_pe[e[i].event].pme_umasks[e[i].unit_masks[k]].pme_ucode; } /* * for events supporting Core specificity (self, both), a value * of 0 for bits 15:14 (7:6 in our umask) is reserved, therefore we * force to SELF if user did not specify anything */ if ((core_pe[e[i].event].pme_flags & PFMLIB_CORE_CSPEC) && ((ucode & (0x3 << 6)) == 0)) { ucode |= 1 << 6; } /* * for events supporting MESI, a value * of 0 for bits 11:8 (0-3 in our umask) means nothing will be * counted. Therefore, we force a default of 0xf (M,E,S,I). */ if ((core_pe[e[i].event].pme_flags & PFMLIB_CORE_MESI) && ((ucode & 0xf) == 0)) { ucode |= 0xf; } val |= ucode << 8; reg.sel_unit_mask = ucode; reg.sel_usr = plm & PFM_PLM3 ? 1 : 0; reg.sel_os = plm & PFM_PLM0 ? 1 : 0; reg.sel_en = 1; /* force enable bit to 1 */ reg.sel_int = 1; /* force APIC int to 1 */ reg.sel_cnt_mask = val >>24; reg.sel_inv = val >> 23; reg.sel_edge = val >> 18; if (cntrs) { if (!reg.sel_cnt_mask) { /* * counter mask is 8-bit wide, do not silently * wrap-around */ if (cntrs[i].cnt_mask > 255) return PFMLIB_ERR_INVAL; reg.sel_cnt_mask = cntrs[i].cnt_mask; } if (!reg.sel_edge) reg.sel_edge = cntrs[i].flags & PFM_CORE_SEL_EDGE ? 1 : 0; if (!reg.sel_inv) reg.sel_inv = cntrs[i].flags & PFM_CORE_SEL_INV ? 1 : 0; } pc[npc].reg_num = assign_pc[i]; pc[npc].reg_value = reg.val; pc[npc].reg_addr = CORE_SEL_BASE+assign_pc[i]; pc[npc].reg_alt_addr= CORE_SEL_BASE+assign_pc[i]; __pfm_vbprintf("[PERFEVTSEL%u(pmc%u)=0x%"PRIx64" event_sel=0x%x umask=0x%x os=%d usr=%d en=%d int=%d inv=%d edge=%d cnt_mask=%d] %s\n", pc[npc].reg_num, pc[npc].reg_num, reg.val, reg.sel_event_select, reg.sel_unit_mask, reg.sel_os, reg.sel_usr, reg.sel_en, reg.sel_int, reg.sel_inv, reg.sel_edge, reg.sel_cnt_mask, core_pe[e[i].event].pme_name); __pfm_vbprintf("[PMC%u(pmd%u)]\n", pc[npc].reg_num, pc[npc].reg_num); npc++; } /* * setup pmds: must be in the same order as the events */ for (i=0; i < n ; i++) { if (is_fixed_pmc(assign_pc[i])) { /* setup pd array */ pd[i].reg_num = assign_pc[i]; pd[i].reg_addr = FIXED_CTR_BASE+assign_pc[i]-16; pd[i].reg_alt_addr = 0x40000000+assign_pc[i]-16; } else { pd[i].reg_num = assign_pc[i]; pd[i].reg_addr = CORE_CTR_BASE+assign_pc[i]; /* index to use with RDPMC */ pd[i].reg_alt_addr = assign_pc[i]; } } outp->pfp_pmd_count = i; /* * setup PEBS_ENABLE */ if (use_pebs && done_pebs) { /* * check that PEBS_ENABLE is available */ if (pfm_regmask_isset(r_pmcs, 17)) return PFMLIB_ERR_NOASSIGN; pc[npc].reg_num = 17; pc[npc].reg_value = 1ULL; pc[npc].reg_addr = 0x3f1; /* IA32_PEBS_ENABLE */ pc[npc].reg_alt_addr = 0x3f1; /* IA32_PEBS_ENABLE */ __pfm_vbprintf("[PEBS_ENABLE(pmc%u)=0x%"PRIx64" ena=%d]\n", pc[npc].reg_num, pc[npc].reg_value, pc[npc].reg_value & 0x1ull); npc++; } outp->pfp_pmc_count = npc; return PFMLIB_SUCCESS; } #if 0 static int pfm_core_dispatch_pebs(pfmlib_input_param_t *inp, pfmlib_core_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfmlib_event_t *e; pfm_core_sel_reg_t reg; unsigned int umask, npc, npd, k, plm; pfmlib_regmask_t *r_pmcs; pfmlib_reg_t *pc, *pd; int event; npc = outp->pfp_pmc_count; npd = outp->pfp_pmd_count; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; r_pmcs = &inp->pfp_unavail_pmcs; e = inp->pfp_events; /* * check for valid flags */ if (e[0].flags & ~PFMLIB_CORE_ALL_FLAGS) return PFMLIB_ERR_INVAL; /* * check event supports PEBS */ if (pfm_core_is_pebs(e) == 0) return PFMLIB_ERR_FEATCOMB; /* * check that PMC0 is available * PEBS works only on PMC0 * Some PEBS at-retirement events do require PMC0 anyway */ if (pfm_regmask_isset(r_pmcs, 0)) return PFMLIB_ERR_NOASSIGN; /* * check that PEBS_ENABLE is available */ if (pfm_regmask_isset(r_pmcs, 17)) return PFMLIB_ERR_NOASSIGN; reg.val = 0; /* assume reserved bits are zerooed */ event = e[0].event; /* if plm is 0, then assume not specified per-event and use default */ plm = e[0].plm ? e[0].plm : inp->pfp_dfl_plm; reg.sel_event_select = core_pe[event].pme_code & 0xff; umask = (core_pe[event].pme_code >> 8) & 0xff; for(k=0; k < e[0].num_masks; k++) { umask |= core_pe[event].pme_umasks[e[0].unit_masks[k]].pme_ucode; } reg.sel_unit_mask = umask; reg.sel_usr = plm & PFM_PLM3 ? 1 : 0; reg.sel_os = plm & PFM_PLM0 ? 1 : 0; reg.sel_en = 1; /* force enable bit to 1 */ reg.sel_int = 0; /* not INT for PEBS counter */ reg.sel_cnt_mask = mod_in->pfp_core_counters[0].cnt_mask; reg.sel_edge = mod_in->pfp_core_counters[0].flags & PFM_CORE_SEL_EDGE ? 1 : 0; reg.sel_inv = mod_in->pfp_core_counters[0].flags & PFM_CORE_SEL_INV ? 1 : 0; pc[npc].reg_num = 0; pc[npc].reg_value = reg.val; pc[npc].reg_addr = CORE_SEL_BASE; pc[npc].reg_alt_addr= CORE_SEL_BASE; pd[npd].reg_num = 0; pd[npd].reg_addr = CORE_CTR_BASE; pd[npd].reg_alt_addr = 0; __pfm_vbprintf("[PERFEVTSEL%u(pmc%u)=0x%"PRIx64" event_sel=0x%x umask=0x%x os=%d usr=%d en=%d int=%d inv=%d edge=%d cnt_mask=%d] %s\n", pc[npc].reg_num, pc[npc].reg_num, reg.val, reg.sel_event_select, reg.sel_unit_mask, reg.sel_os, reg.sel_usr, reg.sel_en, reg.sel_int, reg.sel_inv, reg.sel_edge, reg.sel_cnt_mask, core_pe[e[0].event].pme_name); __pfm_vbprintf("[PMC%u(pmd%u)]\n", pd[npd].reg_num, pd[npd].reg_num); npc++; npd++; /* * setup PEBS_ENABLE */ pc[npc].reg_num = 17; pc[npc].reg_value = 1ULL; pc[npc].reg_addr = 0x3f1; /* IA32_PEBS_ENABLE */ pc[npc].reg_alt_addr = 0x3f1; /* IA32_PEBS_ENABLE */ __pfm_vbprintf("[PEBS_ENABLE(pmc%u)=0x%"PRIx64" ena=%d]\n", pc[npc].reg_num, pc[npc].reg_value, pc[npc].reg_value & 0x1ull); npc++; /* number of evtsel/ctr registers programmed */ outp->pfp_pmc_count = npc; outp->pfp_pmd_count = npd; return PFMLIB_SUCCESS; } #endif static int pfm_core_dispatch_events(pfmlib_input_param_t *inp, void *model_in, pfmlib_output_param_t *outp, void *model_out) { pfmlib_core_input_param_t *mod_in = (pfmlib_core_input_param_t *)model_in; if (inp->pfp_dfl_plm & (PFM_PLM1|PFM_PLM2)) { DPRINT("invalid plm=%x\n", inp->pfp_dfl_plm); return PFMLIB_ERR_INVAL; } return pfm_core_dispatch_counters(inp, mod_in, outp); } static int pfm_core_get_event_code(unsigned int i, unsigned int cnt, int *code) { if (cnt != PFMLIB_CNT_FIRST && (cnt > highest_counter || !pfm_regmask_isset(&core_impl_pmds, cnt))) return PFMLIB_ERR_INVAL; *code = core_pe[i].pme_code; return PFMLIB_SUCCESS; } static void pfm_core_get_event_counters(unsigned int j, pfmlib_regmask_t *counters) { unsigned int n, i; unsigned int has_f0, has_f1, has_f2; memset(counters, 0, sizeof(*counters)); n = core_pe[j].pme_numasks; has_f0 = has_f1 = has_f2 = 0; for (i=0; i < n; i++) { if (core_pe[j].pme_umasks[i].pme_flags & PFMLIB_CORE_FIXED0) has_f0 = 1; if (core_pe[j].pme_umasks[i].pme_flags & PFMLIB_CORE_FIXED1) has_f1 = 1; if (core_pe[j].pme_umasks[i].pme_flags & PFMLIB_CORE_FIXED2_ONLY) has_f2 = 1; } if (has_f0 == 0) has_f0 = core_pe[j].pme_flags & PFMLIB_CORE_FIXED0; if (has_f1 == 0) has_f1 = core_pe[j].pme_flags & PFMLIB_CORE_FIXED1; if (has_f2 == 0) has_f2 = core_pe[j].pme_flags & PFMLIB_CORE_FIXED2_ONLY; if (has_f0) pfm_regmask_set(counters, 16); if (has_f1) pfm_regmask_set(counters, 17); if (has_f2) pfm_regmask_set(counters, 18); /* the event on FIXED_CTR2 is exclusive CPU_CLK_UNHALTED:REF */ if (!has_f2) { pfm_regmask_set(counters, 0); pfm_regmask_set(counters, 1); if (core_pe[j].pme_flags & PFMLIB_CORE_PMC0) pfm_regmask_clr(counters, 1); if (core_pe[j].pme_flags & PFMLIB_CORE_PMC1) pfm_regmask_clr(counters, 0); } } static void pfm_core_get_impl_pmcs(pfmlib_regmask_t *impl_pmcs) { *impl_pmcs = core_impl_pmcs; } static void pfm_core_get_impl_pmds(pfmlib_regmask_t *impl_pmds) { *impl_pmds = core_impl_pmds; } static void pfm_core_get_impl_counters(pfmlib_regmask_t *impl_counters) { pfm_regmask_set(impl_counters, 0); pfm_regmask_set(impl_counters, 1); pfm_regmask_set(impl_counters, 16); pfm_regmask_set(impl_counters, 17); pfm_regmask_set(impl_counters, 18); } /* * Even though, CPUID 0xa returns in eax the actual counter * width, the architecture specifies that writes are limited * to lower 32-bits. As such, only the lower 32-bit have full * degree of freedom. That is the "useable" counter width. */ #define PMU_CORE_COUNTER_WIDTH 32 static void pfm_core_get_hw_counter_width(unsigned int *width) { /* * Even though, CPUID 0xa returns in eax the actual counter * width, the architecture specifies that writes are limited * to lower 32-bits. As such, only the lower 31 bits have full * degree of freedom. That is the "useable" counter width. */ *width = PMU_CORE_COUNTER_WIDTH; } static char * pfm_core_get_event_name(unsigned int i) { return core_pe[i].pme_name; } static int pfm_core_get_event_description(unsigned int ev, char **str) { char *s; s = core_pe[ev].pme_desc; if (s) { *str = strdup(s); } else { *str = NULL; } return PFMLIB_SUCCESS; } static char * pfm_core_get_event_mask_name(unsigned int ev, unsigned int midx) { return core_pe[ev].pme_umasks[midx].pme_uname; } static int pfm_core_get_event_mask_desc(unsigned int ev, unsigned int midx, char **str) { char *s; s = core_pe[ev].pme_umasks[midx].pme_udesc; if (s) { *str = strdup(s); } else { *str = NULL; } return PFMLIB_SUCCESS; } static unsigned int pfm_core_get_num_event_masks(unsigned int ev) { return core_pe[ev].pme_numasks; } static int pfm_core_get_event_mask_code(unsigned int ev, unsigned int midx, unsigned int *code) { *code =core_pe[ev].pme_umasks[midx].pme_ucode; return PFMLIB_SUCCESS; } static int pfm_core_get_cycle_event(pfmlib_event_t *e) { e->event = PME_CORE_UNHALTED_CORE_CYCLES; return PFMLIB_SUCCESS; } static int pfm_core_get_inst_retired(pfmlib_event_t *e) { e->event = PME_CORE_INSTRUCTIONS_RETIRED; return PFMLIB_SUCCESS; } int pfm_core_is_pebs(pfmlib_event_t *e) { unsigned int i, n=0; if (e == NULL || e->event >= PME_CORE_EVENT_COUNT) return 0; if (core_pe[e->event].pme_flags & PFMLIB_CORE_PEBS) return 1; /* * ALL unit mask must support PEBS for this test to return true */ for(i=0; i < e->num_masks; i++) { /* check for valid unit mask */ if (e->unit_masks[i] >= core_pe[e->event].pme_numasks) return 0; if (core_pe[e->event].pme_umasks[e->unit_masks[i]].pme_flags & PFMLIB_CORE_PEBS) n++; } return n > 0 && n == e->num_masks; } pfm_pmu_support_t core_support={ .pmu_name = "Intel Core", .pmu_type = PFMLIB_CORE_PMU, .pme_count = PME_CORE_EVENT_COUNT, .pmc_count = 4, .pmd_count = 14, .num_cnt = 5, .get_event_code = pfm_core_get_event_code, .get_event_name = pfm_core_get_event_name, .get_event_counters = pfm_core_get_event_counters, .dispatch_events = pfm_core_dispatch_events, .pmu_detect = pfm_core_detect, .pmu_init = pfm_core_init, .get_impl_pmcs = pfm_core_get_impl_pmcs, .get_impl_pmds = pfm_core_get_impl_pmds, .get_impl_counters = pfm_core_get_impl_counters, .get_hw_counter_width = pfm_core_get_hw_counter_width, .get_event_desc = pfm_core_get_event_description, .get_num_event_masks = pfm_core_get_num_event_masks, .get_event_mask_name = pfm_core_get_event_mask_name, .get_event_mask_code = pfm_core_get_event_mask_code, .get_event_mask_desc = pfm_core_get_event_mask_desc, .get_cycle_event = pfm_core_get_cycle_event, .get_inst_retired_event = pfm_core_get_inst_retired }; papi-5.5.1/src/libpfm-3.y/lib/pfmlib_os_macos.c0000644000307100002310000000554113013651450021175 0ustar yarkhangraduate/* * pfmlib_os_macos.c: set of functions for MacOS (Tiger) * * Copyright (c) 2008 Stephane Eranian * Contributed by Stephane Eranian * As a sign of friendship to my friend Eric, big fan of MacOS * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include "pfmlib_priv.h" typedef enum { TYPE_NONE, TYPE_STR, TYPE_INT } mib_name_t; /* * helper function to retrieve one value from /proc/cpuinfo * for internal libpfm use only * attr: the attribute (line) to look for * ret_buf: a buffer to store the value of the attribute (as a string) * maxlen : number of bytes of capacity in ret_buf * * ret_buf is null terminated. * * Return: * 0 : attribute found, ret_buf populated * -1: attribute not found */ int __pfm_getcpuinfo_attr(const char *attr, char *ret_buf, size_t maxlen) { mib_name_t type = TYPE_NONE; union { char str[32]; int val; } value; char *name = NULL; int mib[16]; int ret = -1; size_t len, mib_len; if (attr == NULL || ret_buf == NULL || maxlen < 1) return -1; *ret_buf = '\0'; if (!strcmp(attr, "vendor_id")) { name = "machdep.cpu.vendor"; type = TYPE_STR; } else if (!strcmp(attr, "model")) { name = "machdep.cpu.model"; type = TYPE_INT; } else if (!strcmp(attr, "cpu family")) { name = "machdep.cpu.family"; type = TYPE_INT; } mib_len = 16; ret = sysctlnametomib(name, mib, &mib_len); if (ret) return -1; len = sizeof(value); ret = sysctl(mib, mib_len, &value, &len, NULL, 0); if (ret) return ret; if (type == TYPE_STR) strncpy(ret_buf, value.str, maxlen); else if (type == TYPE_INT) snprintf(ret_buf, maxlen, "%d", value.val); __pfm_vbprintf("attr=%s ret=%d ret_buf=%s\n", attr, ret, ret_buf); return ret; } void pfm_init_syscalls(void) { } papi-5.5.1/src/libpfm-3.y/lib/pfmlib_priv_ia64.h0000644000307100002310000000371413013651450021202 0ustar yarkhangraduate/* * Copyright (c) 2003-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #ifndef __PFMLIB_PRIV_IA64_H__ #define __PFMLIB_PRIV_IA64_H__ typedef struct { unsigned long db_mask:56; unsigned long db_plm:4; unsigned long db_ig:2; unsigned long db_w:1; unsigned long db_rx:1; } br_mask_reg_t; typedef union { unsigned long val; br_mask_reg_t db; } dbreg_t; static inline int pfm_ia64_get_cpu_family(void) { return (int)((ia64_get_cpuid(3) >> 24) & 0xff); } static inline int pfm_ia64_get_cpu_model(void) { return (int)((ia64_get_cpuid(3) >> 16) & 0xff); } /* * find last bit set */ static inline int pfm_ia64_fls (unsigned long x) { double d = x; long exp; exp = ia64_getf(d); return exp - 0xffff; } #endif /* __PFMLIB_PRIV_IA64_H__ */ papi-5.5.1/src/libpfm-3.y/lib/pfmlib_os_linux.c0000644000307100002310000001711013013651450021225 0ustar yarkhangraduate/* * pfmlib_os.c: set of functions OS dependent functions * * Copyright (c) 2003-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _GNU_SOURCE #define _GNU_SOURCE /* for getline */ #endif #include #include #include #include #include #include #include #include #include #include #include #include "pfmlib_priv.h" int _pfmlib_sys_base; /* syscall base */ int _pfmlib_major_version; /* kernel perfmon major version */ int _pfmlib_minor_version; /* kernel perfmon minor version */ /* * helper function to retrieve one value from /proc/cpuinfo * for internal libpfm use only * attr: the attribute (line) to look for * ret_buf: a buffer to store the value of the attribute (as a string) * maxlen : number of bytes of capacity in ret_buf * * ret_buf is null terminated. * * Return: * 0 : attribute found, ret_buf populated * -1: attribute not found */ int __pfm_getcpuinfo_attr(const char *attr, char *ret_buf, size_t maxlen) { FILE *fp = NULL; int ret = -1; size_t attr_len, buf_len = 0; char *p, *value = NULL; char *buffer = NULL; if (attr == NULL || ret_buf == NULL || maxlen < 1) return -1; attr_len = strlen(attr); fp = fopen("/proc/cpuinfo", "r"); if (fp == NULL) return -1; while(getline(&buffer, &buf_len, fp) != -1){ /* skip blank lines */ if (*buffer == '\n') continue; p = strchr(buffer, ':'); if (p == NULL) goto error; /* * p+2: +1 = space, +2= firt character * strlen()-1 gets rid of \n */ *p = '\0'; value = p+2; value[strlen(value)-1] = '\0'; if (!strncmp(attr, buffer, attr_len)) break; } strncpy(ret_buf, value, maxlen-1); ret_buf[maxlen-1] = '\0'; ret = 0; error: free(buffer); fclose(fp); return ret; } #if defined(__x86_64__) static void adjust__pfmlib_sys_base(int version) { #ifdef CONFIG_PFMLIB_ARCH_CRAYXT _pfmlib_sys_base = 273; #else switch(version) { case 29: case 28: case 27: _pfmlib_sys_base = 295; break; case 26: case 25: _pfmlib_sys_base = 288; break; case 24: default: /* 2.6.24 as default */ _pfmlib_sys_base = 286; } #endif } #elif defined(__i386__) static void adjust__pfmlib_sys_base(int version) { switch(version) { case 29: case 28: case 27: _pfmlib_sys_base = 333; break; case 26: case 25: _pfmlib_sys_base = 327; break; case 24: default: /* 2.6.24 as default */ _pfmlib_sys_base = 325; } } #elif defined(__mips__) #if (_MIPS_SIM == _ABIN32) || (_MIPS_SIM == _MIPS_SIM_NABI32) static void adjust__pfmlib_sys_base(int version) { _pfmlib_sys_base = 6000; #ifdef CONFIG_PFMLIB_ARCH_SICORTEX _pfmlib_sys_base += 279; #else switch(version) { case 29: case 28: case 27: _pfmlib_sys_base += 293; break; case 26: case 25: _pfmlib_sys_base += 287; break; case 24: default: /* 2.6.24 as default */ _pfmlib_sys_base += 284; } #endif } #elif (_MIPS_SIM == _ABIO32) || (_MIPS_SIM == _MIPS_SIM_ABI32) static void adjust__pfmlib_sys_base(int version) { _pfmlib_sys_base = 4000; #ifdef CONFIG_PFMLIB_ARCH_SICORTEX _pfmlib_sys_base += 316; #else switch(version) { case 29: case 28: case 27: _pfmlib_sys_base += 330; break; case 26: case 25: _pfmlib_sys_base += 324; break; case 24: default: /* 2.6.24 as default */ _pfmlib_sys_base += 321; } #endif } #elif (_MIPS_SIM == _ABI64) || (_MIPS_SIM == _MIPS_SIM_ABI64) static void adjust__pfmlib_sys_base(int version) { _pfmlib_sys_base = 5000; #ifdef CONFIG_PFMLIB_ARCH_SICORTEX _pfmlib_sys_base += 275; #else switch(version) { case 29: case 28: case 27: _pfmlib_sys_base += 289; break; case 26: case 25: _pfmlib_sys_base += 283; break; case 24: default: /* 2.6.24 as default */ _pfmlib_sys_base += 280; } #endif } #endif #elif defined(__ia64__) static void adjust__pfmlib_sys_base(int version) { switch(version) { case 29: case 28: case 27: _pfmlib_sys_base = 1319; break; case 26: case 25: _pfmlib_sys_base = 1313; break; case 24: default: /* 2.6.24 as default */ _pfmlib_sys_base = 1310; } } #elif defined(__powerpc__) static void adjust__pfmlib_sys_base(int version) { switch(version) { case 29: case 28: case 27: _pfmlib_sys_base = 319; break; case 26: case 25: _pfmlib_sys_base = 313; break; case 24: default: /* 2.6.24 as default */ _pfmlib_sys_base = 310; } } #elif defined(__sparc__) static void adjust__pfmlib_sys_base(int version) { switch(version) { case 28: _pfmlib_sys_base = 324; break; case 27: _pfmlib_sys_base = 323; break; case 26: case 25: _pfmlib_sys_base = 317; break; case 24: default: /* 2.6.24 as default */ _pfmlib_sys_base = 310; } } #elif defined(__crayx2) static inline void adjust__pfmlib_sys_base(int version) { _pfmlib_sys_base = 294; } #else static inline void adjust__pfmlib_sys_base(int version) {} #endif static void pfm_init_syscalls_hardcoded(void) { struct utsname b; char *p, *s; int ret, v; /* * get version information */ ret = uname(&b); if (ret == -1) return; /* * expect major number 2 */ s= b.release; p = strchr(s, '.'); if (!p) return; *p = '\0'; v = atoi(s); if (v != 2) return; /* * expect 2.6 */ s = ++p; p = strchr(s, '.'); if (!p) return; *p = '\0'; v = atoi(s); if (v != 6) return; s = ++p; while (*p >= '0' && *p <= '9') p++; *p = '\0'; /* v is subversion: 23, 24 25 */ v = atoi(s); adjust__pfmlib_sys_base(v); } static int pfm_init_syscalls_sysfs(void) { FILE *fp; int ret; fp = fopen("/sys/kernel/perfmon/syscall", "r"); if (!fp) return -1; ret = fscanf(fp, "%d", &_pfmlib_sys_base); fclose(fp); return ret == 1 ? 0 : -1; } static int pfm_init_version_sysfs(void) { FILE *fp; char *p; char v[8]; int ret; fp = fopen("/sys/kernel/perfmon/version", "r"); if (!fp) return -1; ret = fscanf(fp, "%s", v); if (ret != 1) goto skip; p = strchr(v, '.'); if (p) { *p++ = '\0'; _pfmlib_major_version = atoi(v); _pfmlib_minor_version = atoi(p); } skip: fclose(fp); return ret == 1 ? 0 : -1; } void pfm_init_syscalls(void) { int ret; /* * first try via sysfs */ ret = pfm_init_syscalls_sysfs(); if (ret) pfm_init_syscalls_hardcoded(); ret = pfm_init_version_sysfs(); if (ret) { _pfmlib_major_version = 3; _pfmlib_minor_version = 0; } __pfm_vbprintf("sycall base %d\n", _pfmlib_sys_base); __pfm_vbprintf("major version %d\nminor version %d\n", _pfmlib_major_version, _pfmlib_minor_version); } papi-5.5.1/src/libpfm-3.y/lib/pfmlib_sicortex_priv.h0000644000307100002310000000516113013651450022275 0ustar yarkhangraduate/* * Contributed by Philip Mucci based on code from * Copyright (c) 2004-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #ifndef __PFMLIB_SICORTEX_PRIV_H__ #define __PFMLIB_SICORTEX_PRIV_H__ #include "pfmlib_gen_mips64_priv.h" #define PFMLIB_SICORTEX_MAX_UMASK 5 typedef struct { char *pme_uname; /* unit mask name */ char *pme_udesc; /* event/umask description */ unsigned int pme_ucode; /* unit mask code */ } pme_sicortex_umask_t; typedef struct { char *pme_name; char *pme_desc; /* text description of the event */ unsigned int pme_code; /* event mask, holds room for four events, low 8 bits cntr0, ... high 8 bits cntr3 */ unsigned int pme_counters; /* Which counter event lives on */ unsigned int pme_numasks; /* number of umasks */ pme_sicortex_umask_t pme_umasks[PFMLIB_SICORTEX_MAX_UMASK]; /* umask desc */ } pme_sicortex_entry_t; static pme_sicortex_umask_t sicortex_scb_umasks[PFMLIB_SICORTEX_MAX_UMASK] = { { "IFOTHER_NONE","Both buckets count independently",0x00 }, { "IFOTHER_AND","Increment where this event counts and the opposite bucket counts",0x02 }, { "IFOTHER_ANDNOT","Increment where this event counts and the opposite bucket does not",0x04 }, { "HIST_NONE","Count cycles where the event is asserted",0x0 }, { "HIST_EDGE","Histogram on edges of the specified event",0x1 } }; #endif /* __PFMLIB_GEN_MIPS64_PRIV_H__ */ papi-5.5.1/src/libpfm-3.y/lib/montecito_events.h0000644000307100002310000037213713013651450021443 0ustar yarkhangraduate/* * Copyright (c) 2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ /* * This file is generated automatically * !! DO NOT CHANGE !! */ static pme_mont_entry_t montecito_pe []={ #define PME_MONT_ALAT_CAPACITY_MISS_ALL 0 { "ALAT_CAPACITY_MISS_ALL", {0x30058}, 0xfff0, 2, {0xffff0007}, "ALAT Entry Replaced -- both integer and floating point instructions"}, #define PME_MONT_ALAT_CAPACITY_MISS_FP 1 { "ALAT_CAPACITY_MISS_FP", {0x20058}, 0xfff0, 2, {0xffff0007}, "ALAT Entry Replaced -- only floating point instructions"}, #define PME_MONT_ALAT_CAPACITY_MISS_INT 2 { "ALAT_CAPACITY_MISS_INT", {0x10058}, 0xfff0, 2, {0xffff0007}, "ALAT Entry Replaced -- only integer instructions"}, #define PME_MONT_BACK_END_BUBBLE_ALL 3 { "BACK_END_BUBBLE_ALL", {0x0}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe -- Front-end, RSE, EXE, FPU/L1D stall or a pipeline flush due to an exception/branch misprediction"}, #define PME_MONT_BACK_END_BUBBLE_FE 4 { "BACK_END_BUBBLE_FE", {0x10000}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe -- front-end"}, #define PME_MONT_BACK_END_BUBBLE_L1D_FPU_RSE 5 { "BACK_END_BUBBLE_L1D_FPU_RSE", {0x20000}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe -- L1D_FPU or RSE."}, #define PME_MONT_BE_BR_MISPRED_DETAIL_ANY 6 { "BE_BR_MISPRED_DETAIL_ANY", {0x61}, 0xfff0, 1, {0xffff0003}, "BE Branch Misprediction Detail -- any back-end (be) mispredictions"}, #define PME_MONT_BE_BR_MISPRED_DETAIL_PFS 7 { "BE_BR_MISPRED_DETAIL_PFS", {0x30061}, 0xfff0, 1, {0xffff0003}, "BE Branch Misprediction Detail -- only back-end pfs mispredictions for taken branches"}, #define PME_MONT_BE_BR_MISPRED_DETAIL_ROT 8 { "BE_BR_MISPRED_DETAIL_ROT", {0x20061}, 0xfff0, 1, {0xffff0003}, "BE Branch Misprediction Detail -- only back-end rotate mispredictions"}, #define PME_MONT_BE_BR_MISPRED_DETAIL_STG 9 { "BE_BR_MISPRED_DETAIL_STG", {0x10061}, 0xfff0, 1, {0xffff0003}, "BE Branch Misprediction Detail -- only back-end stage mispredictions"}, #define PME_MONT_BE_EXE_BUBBLE_ALL 10 { "BE_EXE_BUBBLE_ALL", {0x2}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe"}, #define PME_MONT_BE_EXE_BUBBLE_ARCR 11 { "BE_EXE_BUBBLE_ARCR", {0x40002}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to AR or CR dependency"}, #define PME_MONT_BE_EXE_BUBBLE_ARCR_PR_CANCEL_BANK 12 { "BE_EXE_BUBBLE_ARCR_PR_CANCEL_BANK", {0x80002}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- ARCR, PR, CANCEL or BANK_SWITCH"}, #define PME_MONT_BE_EXE_BUBBLE_BANK_SWITCH 13 { "BE_EXE_BUBBLE_BANK_SWITCH", {0x70002}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to bank switching."}, #define PME_MONT_BE_EXE_BUBBLE_CANCEL 14 { "BE_EXE_BUBBLE_CANCEL", {0x60002}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to a canceled load"}, #define PME_MONT_BE_EXE_BUBBLE_FRALL 15 { "BE_EXE_BUBBLE_FRALL", {0x20002}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to FR/FR or FR/load dependency"}, #define PME_MONT_BE_EXE_BUBBLE_GRALL 16 { "BE_EXE_BUBBLE_GRALL", {0x10002}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to GR/GR or GR/load dependency"}, #define PME_MONT_BE_EXE_BUBBLE_GRGR 17 { "BE_EXE_BUBBLE_GRGR", {0x50002}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to GR/GR dependency"}, #define PME_MONT_BE_EXE_BUBBLE_PR 18 { "BE_EXE_BUBBLE_PR", {0x30002}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to PR dependency"}, #define PME_MONT_BE_FLUSH_BUBBLE_ALL 19 { "BE_FLUSH_BUBBLE_ALL", {0x4}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to Flushes. -- Back-end was stalled due to either an exception/interruption or branch misprediction flush"}, #define PME_MONT_BE_FLUSH_BUBBLE_BRU 20 { "BE_FLUSH_BUBBLE_BRU", {0x10004}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to Flushes. -- Back-end was stalled due to a branch misprediction flush"}, #define PME_MONT_BE_FLUSH_BUBBLE_XPN 21 { "BE_FLUSH_BUBBLE_XPN", {0x20004}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to Flushes. -- Back-end was stalled due to an exception/interruption flush"}, #define PME_MONT_BE_L1D_FPU_BUBBLE_ALL 22 { "BE_L1D_FPU_BUBBLE_ALL", {0xca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D or FPU"}, #define PME_MONT_BE_L1D_FPU_BUBBLE_FPU 23 { "BE_L1D_FPU_BUBBLE_FPU", {0x100ca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by FPU."}, #define PME_MONT_BE_L1D_FPU_BUBBLE_L1D 24 { "BE_L1D_FPU_BUBBLE_L1D", {0x200ca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D. This includes all stalls caused by the L1 pipeline (created in the L1D stage of the L1 pipeline which corresponds to the DET stage of the main pipe)."}, #define PME_MONT_BE_L1D_FPU_BUBBLE_L1D_AR_CR 25 { "BE_L1D_FPU_BUBBLE_L1D_AR_CR", {0x800ca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to ar/cr requiring a stall"}, #define PME_MONT_BE_L1D_FPU_BUBBLE_L1D_FILLCONF 26 { "BE_L1D_FPU_BUBBLE_L1D_FILLCONF", {0x700ca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due a store in conflict with a returning fill."}, #define PME_MONT_BE_L1D_FPU_BUBBLE_L1D_FULLSTBUF 27 { "BE_L1D_FPU_BUBBLE_L1D_FULLSTBUF", {0x300ca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to store buffer being full"}, #define PME_MONT_BE_L1D_FPU_BUBBLE_L1D_HPW 28 { "BE_L1D_FPU_BUBBLE_L1D_HPW", {0x500ca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to Hardware Page Walker"}, #define PME_MONT_BE_L1D_FPU_BUBBLE_L1D_L2BPRESS 29 { "BE_L1D_FPU_BUBBLE_L1D_L2BPRESS", {0x900ca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to L2 Back Pressure"}, #define PME_MONT_BE_L1D_FPU_BUBBLE_L1D_LDCHK 30 { "BE_L1D_FPU_BUBBLE_L1D_LDCHK", {0xc00ca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to architectural ordering conflict"}, #define PME_MONT_BE_L1D_FPU_BUBBLE_L1D_LDCONF 31 { "BE_L1D_FPU_BUBBLE_L1D_LDCONF", {0xb00ca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to architectural ordering conflict"}, #define PME_MONT_BE_L1D_FPU_BUBBLE_L1D_NAT 32 { "BE_L1D_FPU_BUBBLE_L1D_NAT", {0xd00ca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to L1D data return needing recirculated NaT generation."}, #define PME_MONT_BE_L1D_FPU_BUBBLE_L1D_NATCONF 33 { "BE_L1D_FPU_BUBBLE_L1D_NATCONF", {0xf00ca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to ld8.fill conflict with st8.spill not written to unat."}, #define PME_MONT_BE_L1D_FPU_BUBBLE_L1D_PIPE_RECIRC 34 { "BE_L1D_FPU_BUBBLE_L1D_PIPE_RECIRC", {0x400ca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to recirculate"}, #define PME_MONT_BE_L1D_FPU_BUBBLE_L1D_STBUFRECIR 35 { "BE_L1D_FPU_BUBBLE_L1D_STBUFRECIR", {0xe00ca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to store buffer cancel needing recirculate."}, #define PME_MONT_BE_L1D_FPU_BUBBLE_L1D_TLB 36 { "BE_L1D_FPU_BUBBLE_L1D_TLB", {0xa00ca}, 0xfff0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to L2DTLB to L1DTLB transfer"}, #define PME_MONT_BE_LOST_BW_DUE_TO_FE_ALL 37 { "BE_LOST_BW_DUE_TO_FE_ALL", {0x72}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- count regardless of cause"}, #define PME_MONT_BE_LOST_BW_DUE_TO_FE_BI 38 { "BE_LOST_BW_DUE_TO_FE_BI", {0x90072}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by branch initialization stall"}, #define PME_MONT_BE_LOST_BW_DUE_TO_FE_BRQ 39 { "BE_LOST_BW_DUE_TO_FE_BRQ", {0xa0072}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by branch retirement queue stall"}, #define PME_MONT_BE_LOST_BW_DUE_TO_FE_BR_ILOCK 40 { "BE_LOST_BW_DUE_TO_FE_BR_ILOCK", {0xc0072}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by branch interlock stall"}, #define PME_MONT_BE_LOST_BW_DUE_TO_FE_BUBBLE 41 { "BE_LOST_BW_DUE_TO_FE_BUBBLE", {0xd0072}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by branch resteer bubble stall"}, #define PME_MONT_BE_LOST_BW_DUE_TO_FE_FEFLUSH 42 { "BE_LOST_BW_DUE_TO_FE_FEFLUSH", {0x10072}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by a front-end flush"}, #define PME_MONT_BE_LOST_BW_DUE_TO_FE_FILL_RECIRC 43 { "BE_LOST_BW_DUE_TO_FE_FILL_RECIRC", {0x80072}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by a recirculate for a cache line fill operation"}, #define PME_MONT_BE_LOST_BW_DUE_TO_FE_IBFULL 44 { "BE_LOST_BW_DUE_TO_FE_IBFULL", {0x50072}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- (* meaningless for this event *)"}, #define PME_MONT_BE_LOST_BW_DUE_TO_FE_IMISS 45 { "BE_LOST_BW_DUE_TO_FE_IMISS", {0x60072}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by instruction cache miss stall"}, #define PME_MONT_BE_LOST_BW_DUE_TO_FE_PLP 46 { "BE_LOST_BW_DUE_TO_FE_PLP", {0xb0072}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by perfect loop prediction stall"}, #define PME_MONT_BE_LOST_BW_DUE_TO_FE_TLBMISS 47 { "BE_LOST_BW_DUE_TO_FE_TLBMISS", {0x70072}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by TLB stall"}, #define PME_MONT_BE_LOST_BW_DUE_TO_FE_UNREACHED 48 { "BE_LOST_BW_DUE_TO_FE_UNREACHED", {0x40072}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by unreachable bundle"}, #define PME_MONT_BE_RSE_BUBBLE_ALL 49 { "BE_RSE_BUBBLE_ALL", {0x1}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE"}, #define PME_MONT_BE_RSE_BUBBLE_AR_DEP 50 { "BE_RSE_BUBBLE_AR_DEP", {0x20001}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to AR dependencies"}, #define PME_MONT_BE_RSE_BUBBLE_BANK_SWITCH 51 { "BE_RSE_BUBBLE_BANK_SWITCH", {0x10001}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to bank switching"}, #define PME_MONT_BE_RSE_BUBBLE_LOADRS 52 { "BE_RSE_BUBBLE_LOADRS", {0x50001}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to loadrs calculations"}, #define PME_MONT_BE_RSE_BUBBLE_OVERFLOW 53 { "BE_RSE_BUBBLE_OVERFLOW", {0x30001}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to need to spill"}, #define PME_MONT_BE_RSE_BUBBLE_UNDERFLOW 54 { "BE_RSE_BUBBLE_UNDERFLOW", {0x40001}, 0xfff0, 1, {0xffff0000}, "Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to need to fill"}, #define PME_MONT_BR_MISPRED_DETAIL_ALL_ALL_PRED 55 { "BR_MISPRED_DETAIL_ALL_ALL_PRED", {0x5b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- All branch types regardless of prediction result"}, #define PME_MONT_BR_MISPRED_DETAIL_ALL_CORRECT_PRED 56 { "BR_MISPRED_DETAIL_ALL_CORRECT_PRED", {0x1005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- All branch types, correctly predicted branches (outcome and target)"}, #define PME_MONT_BR_MISPRED_DETAIL_ALL_WRONG_PATH 57 { "BR_MISPRED_DETAIL_ALL_WRONG_PATH", {0x2005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- All branch types, mispredicted branches due to wrong branch direction"}, #define PME_MONT_BR_MISPRED_DETAIL_ALL_WRONG_TARGET 58 { "BR_MISPRED_DETAIL_ALL_WRONG_TARGET", {0x3005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- All branch types, mispredicted branches due to wrong target for taken branches"}, #define PME_MONT_BR_MISPRED_DETAIL_IPREL_ALL_PRED 59 { "BR_MISPRED_DETAIL_IPREL_ALL_PRED", {0x4005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- Only IP relative branches, regardless of prediction result"}, #define PME_MONT_BR_MISPRED_DETAIL_IPREL_CORRECT_PRED 60 { "BR_MISPRED_DETAIL_IPREL_CORRECT_PRED", {0x5005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- Only IP relative branches, correctly predicted branches (outcome and target)"}, #define PME_MONT_BR_MISPRED_DETAIL_IPREL_WRONG_PATH 61 { "BR_MISPRED_DETAIL_IPREL_WRONG_PATH", {0x6005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- Only IP relative branches, mispredicted branches due to wrong branch direction"}, #define PME_MONT_BR_MISPRED_DETAIL_IPREL_WRONG_TARGET 62 { "BR_MISPRED_DETAIL_IPREL_WRONG_TARGET", {0x7005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- Only IP relative branches, mispredicted branches due to wrong target for taken branches"}, #define PME_MONT_BR_MISPRED_DETAIL_NRETIND_ALL_PRED 63 { "BR_MISPRED_DETAIL_NRETIND_ALL_PRED", {0xc005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- Only non-return indirect branches, regardless of prediction result"}, #define PME_MONT_BR_MISPRED_DETAIL_NRETIND_CORRECT_PRED 64 { "BR_MISPRED_DETAIL_NRETIND_CORRECT_PRED", {0xd005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- Only non-return indirect branches, correctly predicted branches (outcome and target)"}, #define PME_MONT_BR_MISPRED_DETAIL_NRETIND_WRONG_PATH 65 { "BR_MISPRED_DETAIL_NRETIND_WRONG_PATH", {0xe005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- Only non-return indirect branches, mispredicted branches due to wrong branch direction"}, #define PME_MONT_BR_MISPRED_DETAIL_NRETIND_WRONG_TARGET 66 { "BR_MISPRED_DETAIL_NRETIND_WRONG_TARGET", {0xf005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- Only non-return indirect branches, mispredicted branches due to wrong target for taken branches"}, #define PME_MONT_BR_MISPRED_DETAIL_RETURN_ALL_PRED 67 { "BR_MISPRED_DETAIL_RETURN_ALL_PRED", {0x8005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- Only return type branches, regardless of prediction result"}, #define PME_MONT_BR_MISPRED_DETAIL_RETURN_CORRECT_PRED 68 { "BR_MISPRED_DETAIL_RETURN_CORRECT_PRED", {0x9005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- Only return type branches, correctly predicted branches (outcome and target)"}, #define PME_MONT_BR_MISPRED_DETAIL_RETURN_WRONG_PATH 69 { "BR_MISPRED_DETAIL_RETURN_WRONG_PATH", {0xa005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- Only return type branches, mispredicted branches due to wrong branch direction"}, #define PME_MONT_BR_MISPRED_DETAIL_RETURN_WRONG_TARGET 70 { "BR_MISPRED_DETAIL_RETURN_WRONG_TARGET", {0xb005b}, 0xfff0, 3, {0xffff0003}, "FE Branch Mispredict Detail -- Only return type branches, mispredicted branches due to wrong target for taken branches"}, #define PME_MONT_BR_MISPRED_DETAIL2_ALL_ALL_UNKNOWN_PRED 71 { "BR_MISPRED_DETAIL2_ALL_ALL_UNKNOWN_PRED", {0x68}, 0xfff0, 2, {0xffff0003}, "FE Branch Mispredict Detail (Unknown Path Component) -- All branch types, branches with unknown path prediction"}, #define PME_MONT_BR_MISPRED_DETAIL2_ALL_UNKNOWN_PATH_CORRECT_PRED 72 { "BR_MISPRED_DETAIL2_ALL_UNKNOWN_PATH_CORRECT_PRED", {0x10068}, 0xfff0, 2, {0xffff0003}, "FE Branch Mispredict Detail (Unknown Path Component) -- All branch types, branches with unknown path prediction and correctly predicted branch (outcome & target)"}, #define PME_MONT_BR_MISPRED_DETAIL2_ALL_UNKNOWN_PATH_WRONG_PATH 73 { "BR_MISPRED_DETAIL2_ALL_UNKNOWN_PATH_WRONG_PATH", {0x20068}, 0xfff0, 2, {0xffff0003}, "FE Branch Mispredict Detail (Unknown Path Component) -- All branch types, branches with unknown path prediction and wrong branch direction"}, #define PME_MONT_BR_MISPRED_DETAIL2_IPREL_ALL_UNKNOWN_PRED 74 { "BR_MISPRED_DETAIL2_IPREL_ALL_UNKNOWN_PRED", {0x40068}, 0xfff0, 2, {0xffff0003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only IP relative branches, branches with unknown path prediction"}, #define PME_MONT_BR_MISPRED_DETAIL2_IPREL_UNKNOWN_PATH_CORRECT_PRED 75 { "BR_MISPRED_DETAIL2_IPREL_UNKNOWN_PATH_CORRECT_PRED", {0x50068}, 0xfff0, 2, {0xffff0003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only IP relative branches, branches with unknown path prediction and correct predicted branch (outcome & target)"}, #define PME_MONT_BR_MISPRED_DETAIL2_IPREL_UNKNOWN_PATH_WRONG_PATH 76 { "BR_MISPRED_DETAIL2_IPREL_UNKNOWN_PATH_WRONG_PATH", {0x60068}, 0xfff0, 2, {0xffff0003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only IP relative branches, branches with unknown path prediction and wrong branch direction"}, #define PME_MONT_BR_MISPRED_DETAIL2_NRETIND_ALL_UNKNOWN_PRED 77 { "BR_MISPRED_DETAIL2_NRETIND_ALL_UNKNOWN_PRED", {0xc0068}, 0xfff0, 2, {0xffff0003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only non-return indirect branches, branches with unknown path prediction"}, #define PME_MONT_BR_MISPRED_DETAIL2_NRETIND_UNKNOWN_PATH_CORRECT_PRED 78 { "BR_MISPRED_DETAIL2_NRETIND_UNKNOWN_PATH_CORRECT_PRED", {0xd0068}, 0xfff0, 2, {0xffff0003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only non-return indirect branches, branches with unknown path prediction and correct predicted branch (outcome & target)"}, #define PME_MONT_BR_MISPRED_DETAIL2_NRETIND_UNKNOWN_PATH_WRONG_PATH 79 { "BR_MISPRED_DETAIL2_NRETIND_UNKNOWN_PATH_WRONG_PATH", {0xe0068}, 0xfff0, 2, {0xffff0003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only non-return indirect branches, branches with unknown path prediction and wrong branch direction"}, #define PME_MONT_BR_MISPRED_DETAIL2_RETURN_ALL_UNKNOWN_PRED 80 { "BR_MISPRED_DETAIL2_RETURN_ALL_UNKNOWN_PRED", {0x80068}, 0xfff0, 2, {0xffff0003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only return type branches, branches with unknown path prediction"}, #define PME_MONT_BR_MISPRED_DETAIL2_RETURN_UNKNOWN_PATH_CORRECT_PRED 81 { "BR_MISPRED_DETAIL2_RETURN_UNKNOWN_PATH_CORRECT_PRED", {0x90068}, 0xfff0, 2, {0xffff0003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only return type branches, branches with unknown path prediction and correct predicted branch (outcome & target)"}, #define PME_MONT_BR_MISPRED_DETAIL2_RETURN_UNKNOWN_PATH_WRONG_PATH 82 { "BR_MISPRED_DETAIL2_RETURN_UNKNOWN_PATH_WRONG_PATH", {0xa0068}, 0xfff0, 2, {0xffff0003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only return type branches, branches with unknown path prediction and wrong branch direction"}, #define PME_MONT_BR_PATH_PRED_ALL_MISPRED_NOTTAKEN 83 { "BR_PATH_PRED_ALL_MISPRED_NOTTAKEN", {0x54}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- All branch types, incorrectly predicted path and not taken branch"}, #define PME_MONT_BR_PATH_PRED_ALL_MISPRED_TAKEN 84 { "BR_PATH_PRED_ALL_MISPRED_TAKEN", {0x10054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- All branch types, incorrectly predicted path and taken branch"}, #define PME_MONT_BR_PATH_PRED_ALL_OKPRED_NOTTAKEN 85 { "BR_PATH_PRED_ALL_OKPRED_NOTTAKEN", {0x20054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- All branch types, correctly predicted path and not taken branch"}, #define PME_MONT_BR_PATH_PRED_ALL_OKPRED_TAKEN 86 { "BR_PATH_PRED_ALL_OKPRED_TAKEN", {0x30054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- All branch types, correctly predicted path and taken branch"}, #define PME_MONT_BR_PATH_PRED_IPREL_MISPRED_NOTTAKEN 87 { "BR_PATH_PRED_IPREL_MISPRED_NOTTAKEN", {0x40054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- Only IP relative branches, incorrectly predicted path and not taken branch"}, #define PME_MONT_BR_PATH_PRED_IPREL_MISPRED_TAKEN 88 { "BR_PATH_PRED_IPREL_MISPRED_TAKEN", {0x50054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- Only IP relative branches, incorrectly predicted path and taken branch"}, #define PME_MONT_BR_PATH_PRED_IPREL_OKPRED_NOTTAKEN 89 { "BR_PATH_PRED_IPREL_OKPRED_NOTTAKEN", {0x60054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- Only IP relative branches, correctly predicted path and not taken branch"}, #define PME_MONT_BR_PATH_PRED_IPREL_OKPRED_TAKEN 90 { "BR_PATH_PRED_IPREL_OKPRED_TAKEN", {0x70054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- Only IP relative branches, correctly predicted path and taken branch"}, #define PME_MONT_BR_PATH_PRED_NRETIND_MISPRED_NOTTAKEN 91 { "BR_PATH_PRED_NRETIND_MISPRED_NOTTAKEN", {0xc0054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- Only non-return indirect branches, incorrectly predicted path and not taken branch"}, #define PME_MONT_BR_PATH_PRED_NRETIND_MISPRED_TAKEN 92 { "BR_PATH_PRED_NRETIND_MISPRED_TAKEN", {0xd0054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- Only non-return indirect branches, incorrectly predicted path and taken branch"}, #define PME_MONT_BR_PATH_PRED_NRETIND_OKPRED_NOTTAKEN 93 { "BR_PATH_PRED_NRETIND_OKPRED_NOTTAKEN", {0xe0054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- Only non-return indirect branches, correctly predicted path and not taken branch"}, #define PME_MONT_BR_PATH_PRED_NRETIND_OKPRED_TAKEN 94 { "BR_PATH_PRED_NRETIND_OKPRED_TAKEN", {0xf0054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- Only non-return indirect branches, correctly predicted path and taken branch"}, #define PME_MONT_BR_PATH_PRED_RETURN_MISPRED_NOTTAKEN 95 { "BR_PATH_PRED_RETURN_MISPRED_NOTTAKEN", {0x80054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- Only return type branches, incorrectly predicted path and not taken branch"}, #define PME_MONT_BR_PATH_PRED_RETURN_MISPRED_TAKEN 96 { "BR_PATH_PRED_RETURN_MISPRED_TAKEN", {0x90054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- Only return type branches, incorrectly predicted path and taken branch"}, #define PME_MONT_BR_PATH_PRED_RETURN_OKPRED_NOTTAKEN 97 { "BR_PATH_PRED_RETURN_OKPRED_NOTTAKEN", {0xa0054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- Only return type branches, correctly predicted path and not taken branch"}, #define PME_MONT_BR_PATH_PRED_RETURN_OKPRED_TAKEN 98 { "BR_PATH_PRED_RETURN_OKPRED_TAKEN", {0xb0054}, 0xfff0, 3, {0xffff0003}, "FE Branch Path Prediction Detail -- Only return type branches, correctly predicted path and taken branch"}, #define PME_MONT_BR_PATH_PRED2_ALL_UNKNOWNPRED_NOTTAKEN 99 { "BR_PATH_PRED2_ALL_UNKNOWNPRED_NOTTAKEN", {0x6a}, 0xfff0, 2, {0xffff0003}, "FE Branch Path Prediction Detail (Unknown pred component) -- All branch types, unknown predicted path and not taken branch (which impacts OKPRED_NOTTAKEN)"}, #define PME_MONT_BR_PATH_PRED2_ALL_UNKNOWNPRED_TAKEN 100 { "BR_PATH_PRED2_ALL_UNKNOWNPRED_TAKEN", {0x1006a}, 0xfff0, 2, {0xffff0003}, "FE Branch Path Prediction Detail (Unknown pred component) -- All branch types, unknown predicted path and taken branch (which impacts MISPRED_TAKEN)"}, #define PME_MONT_BR_PATH_PRED2_IPREL_UNKNOWNPRED_NOTTAKEN 101 { "BR_PATH_PRED2_IPREL_UNKNOWNPRED_NOTTAKEN", {0x4006a}, 0xfff0, 2, {0xffff0003}, "FE Branch Path Prediction Detail (Unknown pred component) -- Only IP relative branches, unknown predicted path and not taken branch (which impacts OKPRED_NOTTAKEN)"}, #define PME_MONT_BR_PATH_PRED2_IPREL_UNKNOWNPRED_TAKEN 102 { "BR_PATH_PRED2_IPREL_UNKNOWNPRED_TAKEN", {0x5006a}, 0xfff0, 2, {0xffff0003}, "FE Branch Path Prediction Detail (Unknown pred component) -- Only IP relative branches, unknown predicted path and taken branch (which impacts MISPRED_TAKEN)"}, #define PME_MONT_BR_PATH_PRED2_NRETIND_UNKNOWNPRED_NOTTAKEN 103 { "BR_PATH_PRED2_NRETIND_UNKNOWNPRED_NOTTAKEN", {0xc006a}, 0xfff0, 2, {0xffff0003}, "FE Branch Path Prediction Detail (Unknown pred component) -- Only non-return indirect branches, unknown predicted path and not taken branch (which impacts OKPRED_NOTTAKEN)"}, #define PME_MONT_BR_PATH_PRED2_NRETIND_UNKNOWNPRED_TAKEN 104 { "BR_PATH_PRED2_NRETIND_UNKNOWNPRED_TAKEN", {0xd006a}, 0xfff0, 2, {0xffff0003}, "FE Branch Path Prediction Detail (Unknown pred component) -- Only non-return indirect branches, unknown predicted path and taken branch (which impacts MISPRED_TAKEN)"}, #define PME_MONT_BR_PATH_PRED2_RETURN_UNKNOWNPRED_NOTTAKEN 105 { "BR_PATH_PRED2_RETURN_UNKNOWNPRED_NOTTAKEN", {0x8006a}, 0xfff0, 2, {0xffff0003}, "FE Branch Path Prediction Detail (Unknown pred component) -- Only return type branches, unknown predicted path and not taken branch (which impacts OKPRED_NOTTAKEN)"}, #define PME_MONT_BR_PATH_PRED2_RETURN_UNKNOWNPRED_TAKEN 106 { "BR_PATH_PRED2_RETURN_UNKNOWNPRED_TAKEN", {0x9006a}, 0xfff0, 2, {0xffff0003}, "FE Branch Path Prediction Detail (Unknown pred component) -- Only return type branches, unknown predicted path and taken branch (which impacts MISPRED_TAKEN)"}, #define PME_MONT_BUS_ALL_ANY 107 { "BUS_ALL_ANY", {0x31887}, 0x03f0, 1, {0xffff0000}, "Bus Transactions -- CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_ALL_EITHER 108 { "BUS_ALL_EITHER", {0x1887}, 0x03f0, 1, {0xffff0000}, "Bus Transactions -- transactions initiated by either cpu core"}, #define PME_MONT_BUS_ALL_IO 109 { "BUS_ALL_IO", {0x11887}, 0x03f0, 1, {0xffff0000}, "Bus Transactions -- transactions initiated by non-CPU priority agents"}, #define PME_MONT_BUS_ALL_SELF 110 { "BUS_ALL_SELF", {0x21887}, 0x03f0, 1, {0xffff0000}, "Bus Transactions -- transactions initiated by 'this' cpu core"}, #define PME_MONT_BUS_B2B_DATA_CYCLES_ANY 111 { "BUS_B2B_DATA_CYCLES_ANY", {0x31093}, 0x03f0, 1, {0xffff0000}, "Back to Back Data Cycles on the Bus -- CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_B2B_DATA_CYCLES_EITHER 112 { "BUS_B2B_DATA_CYCLES_EITHER", {0x1093}, 0x03f0, 1, {0xffff0000}, "Back to Back Data Cycles on the Bus -- transactions initiated by either cpu core"}, #define PME_MONT_BUS_B2B_DATA_CYCLES_IO 113 { "BUS_B2B_DATA_CYCLES_IO", {0x11093}, 0x03f0, 1, {0xffff0000}, "Back to Back Data Cycles on the Bus -- transactions initiated by non-CPU priority agents"}, #define PME_MONT_BUS_B2B_DATA_CYCLES_SELF 114 { "BUS_B2B_DATA_CYCLES_SELF", {0x21093}, 0x03f0, 1, {0xffff0000}, "Back to Back Data Cycles on the Bus -- transactions initiated by 'this' cpu core"}, #define PME_MONT_BUS_DATA_CYCLE_ANY 115 { "BUS_DATA_CYCLE_ANY", {0x31088}, 0x03f0, 1, {0xffff0000}, "Valid Data Cycle on the Bus -- CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_DATA_CYCLE_EITHER 116 { "BUS_DATA_CYCLE_EITHER", {0x1088}, 0x03f0, 1, {0xffff0000}, "Valid Data Cycle on the Bus -- transactions initiated by either cpu core"}, #define PME_MONT_BUS_DATA_CYCLE_IO 117 { "BUS_DATA_CYCLE_IO", {0x11088}, 0x03f0, 1, {0xffff0000}, "Valid Data Cycle on the Bus -- transactions initiated by non-CPU priority agents"}, #define PME_MONT_BUS_DATA_CYCLE_SELF 118 { "BUS_DATA_CYCLE_SELF", {0x21088}, 0x03f0, 1, {0xffff0000}, "Valid Data Cycle on the Bus -- transactions initiated by 'this' cpu core"}, #define PME_MONT_BUS_HITM_ANY 119 { "BUS_HITM_ANY", {0x31884}, 0x03f0, 1, {0xffff0000}, "Bus Hit Modified Line Transactions -- CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_HITM_EITHER 120 { "BUS_HITM_EITHER", {0x1884}, 0x03f0, 1, {0xffff0000}, "Bus Hit Modified Line Transactions -- transactions initiated by either cpu core"}, #define PME_MONT_BUS_HITM_IO 121 { "BUS_HITM_IO", {0x11884}, 0x03f0, 1, {0xffff0000}, "Bus Hit Modified Line Transactions -- transactions initiated by non-CPU priority agents"}, #define PME_MONT_BUS_HITM_SELF 122 { "BUS_HITM_SELF", {0x21884}, 0x03f0, 1, {0xffff0000}, "Bus Hit Modified Line Transactions -- transactions initiated by 'this' cpu core"}, #define PME_MONT_BUS_IO_ANY 123 { "BUS_IO_ANY", {0x31890}, 0x03f0, 1, {0xffff0000}, "IA-32 Compatible IO Bus Transactions -- CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_IO_EITHER 124 { "BUS_IO_EITHER", {0x1890}, 0x03f0, 1, {0xffff0000}, "IA-32 Compatible IO Bus Transactions -- transactions initiated by either cpu core"}, #define PME_MONT_BUS_IO_IO 125 { "BUS_IO_IO", {0x11890}, 0x03f0, 1, {0xffff0000}, "IA-32 Compatible IO Bus Transactions -- transactions initiated by non-CPU priority agents"}, #define PME_MONT_BUS_IO_SELF 126 { "BUS_IO_SELF", {0x21890}, 0x03f0, 1, {0xffff0000}, "IA-32 Compatible IO Bus Transactions -- transactions initiated by 'this' cpu core"}, #define PME_MONT_BUS_MEMORY_ALL_ANY 127 { "BUS_MEMORY_ALL_ANY", {0xf188a}, 0x03f0, 1, {0xffff0000}, "Bus Memory Transactions -- All bus transactions from CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_MEMORY_ALL_EITHER 128 { "BUS_MEMORY_ALL_EITHER", {0xc188a}, 0x03f0, 1, {0xffff0000}, "Bus Memory Transactions -- All bus transactions from non-CPU priority agents"}, #define PME_MONT_BUS_MEMORY_ALL_IO 129 { "BUS_MEMORY_ALL_IO", {0xd188a}, 0x03f0, 1, {0xffff0000}, "Bus Memory Transactions -- All bus transactions from 'this' local processor"}, #define PME_MONT_BUS_MEMORY_ALL_SELF 130 { "BUS_MEMORY_ALL_SELF", {0xe188a}, 0x03f0, 1, {0xffff0000}, "Bus Memory Transactions -- All bus transactions from CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_MEMORY_EQ_128BYTE_ANY 131 { "BUS_MEMORY_EQ_128BYTE_ANY", {0x7188a}, 0x03f0, 1, {0xffff0000}, "Bus Memory Transactions -- number of less than full cache line transactions (BRP, BWP, BIL) from either local processor"}, #define PME_MONT_BUS_MEMORY_EQ_128BYTE_EITHER 132 { "BUS_MEMORY_EQ_128BYTE_EITHER", {0x4188a}, 0x03f0, 1, {0xffff0000}, "Bus Memory Transactions -- number of full cache line transactions (BRL, BRIL, BWL, BRC, BCR, BCCL) from non-CPU priority agents"}, #define PME_MONT_BUS_MEMORY_EQ_128BYTE_IO 133 { "BUS_MEMORY_EQ_128BYTE_IO", {0x5188a}, 0x03f0, 1, {0xffff0000}, "Bus Memory Transactions -- number of full cache line transactions (BRL, BRIL, BWL, BRC, BCR, BCCL) from 'this' processor"}, #define PME_MONT_BUS_MEMORY_EQ_128BYTE_SELF 134 { "BUS_MEMORY_EQ_128BYTE_SELF", {0x6188a}, 0x03f0, 1, {0xffff0000}, "Bus Memory Transactions -- number of full cache line transactions (BRL, BRIL, BWL, BRC, BCR, BCCL) from CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_MEMORY_LT_128BYTE_ANY 135 { "BUS_MEMORY_LT_128BYTE_ANY", {0xb188a}, 0x03f0, 1, {0xffff0000}, "Bus Memory Transactions -- All bus transactions from either local processor"}, #define PME_MONT_BUS_MEMORY_LT_128BYTE_EITHER 136 { "BUS_MEMORY_LT_128BYTE_EITHER", {0x8188a}, 0x03f0, 1, {0xffff0000}, "Bus Memory Transactions -- number of less than full cache line transactions (BRP, BWP, BIL) from non-CPU priority agents"}, #define PME_MONT_BUS_MEMORY_LT_128BYTE_IO 137 { "BUS_MEMORY_LT_128BYTE_IO", {0x9188a}, 0x03f0, 1, {0xffff0000}, "Bus Memory Transactions -- number of less than full cache line transactions (BRP, BWP, BIL) from 'this' processor"}, #define PME_MONT_BUS_MEMORY_LT_128BYTE_SELF 138 { "BUS_MEMORY_LT_128BYTE_SELF", {0xa188a}, 0x03f0, 1, {0xffff0000}, "Bus Memory Transactions -- number of less than full cache line transactions (BRP, BWP, BIL) CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_MEM_READ_ALL_ANY 139 { "BUS_MEM_READ_ALL_ANY", {0xf188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- All memory read transactions from CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_MEM_READ_ALL_EITHER 140 { "BUS_MEM_READ_ALL_EITHER", {0xc188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- All memory read transactions from either local processor"}, #define PME_MONT_BUS_MEM_READ_ALL_IO 141 { "BUS_MEM_READ_ALL_IO", {0xd188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- All memory read transactions from non-CPU priority agents"}, #define PME_MONT_BUS_MEM_READ_ALL_SELF 142 { "BUS_MEM_READ_ALL_SELF", {0xe188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- All memory read transactions from local processor"}, #define PME_MONT_BUS_MEM_READ_BIL_ANY 143 { "BUS_MEM_READ_BIL_ANY", {0x3188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of BIL 0-byte memory read invalidate transactions from CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_MEM_READ_BIL_EITHER 144 { "BUS_MEM_READ_BIL_EITHER", {0x188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of BIL 0-byte memory read invalidate transactions from either local processor"}, #define PME_MONT_BUS_MEM_READ_BIL_IO 145 { "BUS_MEM_READ_BIL_IO", {0x1188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of BIL 0-byte memory read invalidate transactions from non-CPU priority agents"}, #define PME_MONT_BUS_MEM_READ_BIL_SELF 146 { "BUS_MEM_READ_BIL_SELF", {0x2188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of BIL 0-byte memory read invalidate transactions from local processor"}, #define PME_MONT_BUS_MEM_READ_BRIL_ANY 147 { "BUS_MEM_READ_BRIL_ANY", {0xb188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read invalidate transactions from CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_MEM_READ_BRIL_EITHER 148 { "BUS_MEM_READ_BRIL_EITHER", {0x8188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read invalidate transactions from either local processor"}, #define PME_MONT_BUS_MEM_READ_BRIL_IO 149 { "BUS_MEM_READ_BRIL_IO", {0x9188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read invalidate transactions from non-CPU priority agents"}, #define PME_MONT_BUS_MEM_READ_BRIL_SELF 150 { "BUS_MEM_READ_BRIL_SELF", {0xa188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read invalidate transactions from local processor"}, #define PME_MONT_BUS_MEM_READ_BRL_ANY 151 { "BUS_MEM_READ_BRL_ANY", {0x7188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read transactions from CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_MEM_READ_BRL_EITHER 152 { "BUS_MEM_READ_BRL_EITHER", {0x4188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read transactions from either local processor"}, #define PME_MONT_BUS_MEM_READ_BRL_IO 153 { "BUS_MEM_READ_BRL_IO", {0x5188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read transactions from non-CPU priority agents"}, #define PME_MONT_BUS_MEM_READ_BRL_SELF 154 { "BUS_MEM_READ_BRL_SELF", {0x6188b}, 0x03f0, 1, {0xffff0000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read transactions from local processor"}, #define PME_MONT_BUS_RD_DATA_ANY 155 { "BUS_RD_DATA_ANY", {0x3188c}, 0x03f0, 1, {0xffff0000}, "Bus Read Data Transactions -- CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_RD_DATA_EITHER 156 { "BUS_RD_DATA_EITHER", {0x188c}, 0x03f0, 1, {0xffff0000}, "Bus Read Data Transactions -- transactions initiated by either cpu core"}, #define PME_MONT_BUS_RD_DATA_IO 157 { "BUS_RD_DATA_IO", {0x1188c}, 0x03f0, 1, {0xffff0000}, "Bus Read Data Transactions -- transactions initiated by non-CPU priority agents"}, #define PME_MONT_BUS_RD_DATA_SELF 158 { "BUS_RD_DATA_SELF", {0x2188c}, 0x03f0, 1, {0xffff0000}, "Bus Read Data Transactions -- transactions initiated by 'this' cpu core"}, #define PME_MONT_BUS_RD_HIT_ANY 159 { "BUS_RD_HIT_ANY", {0x31880}, 0x03f0, 1, {0xffff0000}, "Bus Read Hit Clean Non-local Cache Transactions -- CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_RD_HIT_EITHER 160 { "BUS_RD_HIT_EITHER", {0x1880}, 0x03f0, 1, {0xffff0000}, "Bus Read Hit Clean Non-local Cache Transactions -- transactions initiated by either cpu core"}, #define PME_MONT_BUS_RD_HIT_IO 161 { "BUS_RD_HIT_IO", {0x11880}, 0x03f0, 1, {0xffff0000}, "Bus Read Hit Clean Non-local Cache Transactions -- transactions initiated by non-CPU priority agents"}, #define PME_MONT_BUS_RD_HIT_SELF 162 { "BUS_RD_HIT_SELF", {0x21880}, 0x03f0, 1, {0xffff0000}, "Bus Read Hit Clean Non-local Cache Transactions -- transactions initiated by 'this' cpu core"}, #define PME_MONT_BUS_RD_HITM_ANY 163 { "BUS_RD_HITM_ANY", {0x31881}, 0x03f0, 1, {0xffff0000}, "Bus Read Hit Modified Non-local Cache Transactions -- CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_RD_HITM_EITHER 164 { "BUS_RD_HITM_EITHER", {0x1881}, 0x03f0, 1, {0xffff0000}, "Bus Read Hit Modified Non-local Cache Transactions -- transactions initiated by either cpu core"}, #define PME_MONT_BUS_RD_HITM_IO 165 { "BUS_RD_HITM_IO", {0x11881}, 0x03f0, 1, {0xffff0000}, "Bus Read Hit Modified Non-local Cache Transactions -- transactions initiated by non-CPU priority agents"}, #define PME_MONT_BUS_RD_HITM_SELF 166 { "BUS_RD_HITM_SELF", {0x21881}, 0x03f0, 1, {0xffff0000}, "Bus Read Hit Modified Non-local Cache Transactions -- transactions initiated by 'this' cpu core"}, #define PME_MONT_BUS_RD_INVAL_BST_HITM_ANY 167 { "BUS_RD_INVAL_BST_HITM_ANY", {0x31883}, 0x03f0, 1, {0xffff0000}, "Bus BRIL Transaction Results in HITM -- CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_RD_INVAL_BST_HITM_EITHER 168 { "BUS_RD_INVAL_BST_HITM_EITHER", {0x1883}, 0x03f0, 1, {0xffff0000}, "Bus BRIL Transaction Results in HITM -- transactions initiated by either cpu core"}, #define PME_MONT_BUS_RD_INVAL_BST_HITM_IO 169 { "BUS_RD_INVAL_BST_HITM_IO", {0x11883}, 0x03f0, 1, {0xffff0000}, "Bus BRIL Transaction Results in HITM -- transactions initiated by non-CPU priority agents"}, #define PME_MONT_BUS_RD_INVAL_BST_HITM_SELF 170 { "BUS_RD_INVAL_BST_HITM_SELF", {0x21883}, 0x03f0, 1, {0xffff0000}, "Bus BRIL Transaction Results in HITM -- transactions initiated by 'this' cpu core"}, #define PME_MONT_BUS_RD_INVAL_HITM_ANY 171 { "BUS_RD_INVAL_HITM_ANY", {0x31882}, 0x03f0, 1, {0xffff0000}, "Bus BIL Transaction Results in HITM -- CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_RD_INVAL_HITM_EITHER 172 { "BUS_RD_INVAL_HITM_EITHER", {0x1882}, 0x03f0, 1, {0xffff0000}, "Bus BIL Transaction Results in HITM -- transactions initiated by either cpu core"}, #define PME_MONT_BUS_RD_INVAL_HITM_IO 173 { "BUS_RD_INVAL_HITM_IO", {0x11882}, 0x03f0, 1, {0xffff0000}, "Bus BIL Transaction Results in HITM -- transactions initiated by non-CPU priority agents"}, #define PME_MONT_BUS_RD_INVAL_HITM_SELF 174 { "BUS_RD_INVAL_HITM_SELF", {0x21882}, 0x03f0, 1, {0xffff0000}, "Bus BIL Transaction Results in HITM -- transactions initiated by 'this' cpu core"}, #define PME_MONT_BUS_RD_IO_ANY 175 { "BUS_RD_IO_ANY", {0x31891}, 0x03f0, 1, {0xffff0000}, "IA-32 Compatible IO Read Transactions -- CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_RD_IO_EITHER 176 { "BUS_RD_IO_EITHER", {0x1891}, 0x03f0, 1, {0xffff0000}, "IA-32 Compatible IO Read Transactions -- transactions initiated by either cpu core"}, #define PME_MONT_BUS_RD_IO_IO 177 { "BUS_RD_IO_IO", {0x11891}, 0x03f0, 1, {0xffff0000}, "IA-32 Compatible IO Read Transactions -- transactions initiated by non-CPU priority agents"}, #define PME_MONT_BUS_RD_IO_SELF 178 { "BUS_RD_IO_SELF", {0x21891}, 0x03f0, 1, {0xffff0000}, "IA-32 Compatible IO Read Transactions -- transactions initiated by 'this' cpu core"}, #define PME_MONT_BUS_RD_PRTL_ANY 179 { "BUS_RD_PRTL_ANY", {0x3188d}, 0x03f0, 1, {0xffff0000}, "Bus Read Partial Transactions -- CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_RD_PRTL_EITHER 180 { "BUS_RD_PRTL_EITHER", {0x188d}, 0x03f0, 1, {0xffff0000}, "Bus Read Partial Transactions -- transactions initiated by either cpu core"}, #define PME_MONT_BUS_RD_PRTL_IO 181 { "BUS_RD_PRTL_IO", {0x1188d}, 0x03f0, 1, {0xffff0000}, "Bus Read Partial Transactions -- transactions initiated by non-CPU priority agents"}, #define PME_MONT_BUS_RD_PRTL_SELF 182 { "BUS_RD_PRTL_SELF", {0x2188d}, 0x03f0, 1, {0xffff0000}, "Bus Read Partial Transactions -- transactions initiated by 'this' cpu core"}, #define PME_MONT_BUS_SNOOP_STALL_CYCLES_ANY 183 { "BUS_SNOOP_STALL_CYCLES_ANY", {0x3188f}, 0x03f0, 1, {0xffff0000}, "Bus Snoop Stall Cycles (from any agent) -- CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_SNOOP_STALL_CYCLES_EITHER 184 { "BUS_SNOOP_STALL_CYCLES_EITHER", {0x188f}, 0x03f0, 1, {0xffff0000}, "Bus Snoop Stall Cycles (from any agent) -- transactions initiated by either cpu core"}, #define PME_MONT_BUS_SNOOP_STALL_CYCLES_SELF 185 { "BUS_SNOOP_STALL_CYCLES_SELF", {0x2188f}, 0x03f0, 1, {0xffff0000}, "Bus Snoop Stall Cycles (from any agent) -- local processor"}, #define PME_MONT_BUS_WR_WB_ALL_ANY 186 { "BUS_WR_WB_ALL_ANY", {0xf1892}, 0x03f0, 1, {0xffff0000}, "Bus Write Back Transactions -- CPU or non-CPU (all transactions)."}, #define PME_MONT_BUS_WR_WB_ALL_IO 187 { "BUS_WR_WB_ALL_IO", {0xd1892}, 0x03f0, 1, {0xffff0000}, "Bus Write Back Transactions -- non-CPU priority agents"}, #define PME_MONT_BUS_WR_WB_ALL_SELF 188 { "BUS_WR_WB_ALL_SELF", {0xe1892}, 0x03f0, 1, {0xffff0000}, "Bus Write Back Transactions -- this' processor"}, #define PME_MONT_BUS_WR_WB_CCASTOUT_ANY 189 { "BUS_WR_WB_CCASTOUT_ANY", {0xb1892}, 0x03f0, 1, {0xffff0000}, "Bus Write Back Transactions -- CPU or non-CPU (all transactions)/Only 0-byte transactions with write back attribute (clean cast outs) will be counted"}, #define PME_MONT_BUS_WR_WB_CCASTOUT_SELF 190 { "BUS_WR_WB_CCASTOUT_SELF", {0xa1892}, 0x03f0, 1, {0xffff0000}, "Bus Write Back Transactions -- this' processor/Only 0-byte transactions with write back attribute (clean cast outs) will be counted"}, #define PME_MONT_BUS_WR_WB_EQ_128BYTE_ANY 191 { "BUS_WR_WB_EQ_128BYTE_ANY", {0x71892}, 0x03f0, 1, {0xffff0000}, "Bus Write Back Transactions -- CPU or non-CPU (all transactions)./Only cache line transactions with write back or write coalesce attributes will be counted."}, #define PME_MONT_BUS_WR_WB_EQ_128BYTE_IO 192 { "BUS_WR_WB_EQ_128BYTE_IO", {0x51892}, 0x03f0, 1, {0xffff0000}, "Bus Write Back Transactions -- non-CPU priority agents/Only cache line transactions with write back or write coalesce attributes will be counted."}, #define PME_MONT_BUS_WR_WB_EQ_128BYTE_SELF 193 { "BUS_WR_WB_EQ_128BYTE_SELF", {0x61892}, 0x03f0, 1, {0xffff0000}, "Bus Write Back Transactions -- this' processor/Only cache line transactions with write back or write coalesce attributes will be counted."}, #define PME_MONT_CPU_CPL_CHANGES_ALL 194 { "CPU_CPL_CHANGES_ALL", {0xf0013}, 0xfff0, 1, {0xffff0000}, "Privilege Level Changes -- All changes in cpl counted"}, #define PME_MONT_CPU_CPL_CHANGES_LVL0 195 { "CPU_CPL_CHANGES_LVL0", {0x10013}, 0xfff0, 1, {0xffff0000}, "Privilege Level Changes -- All changes to/from privilege level0 are counted"}, #define PME_MONT_CPU_CPL_CHANGES_LVL1 196 { "CPU_CPL_CHANGES_LVL1", {0x20013}, 0xfff0, 1, {0xffff0000}, "Privilege Level Changes -- All changes to/from privilege level1 are counted"}, #define PME_MONT_CPU_CPL_CHANGES_LVL2 197 { "CPU_CPL_CHANGES_LVL2", {0x40013}, 0xfff0, 1, {0xffff0000}, "Privilege Level Changes -- All changes to/from privilege level2 are counted"}, #define PME_MONT_CPU_CPL_CHANGES_LVL3 198 { "CPU_CPL_CHANGES_LVL3", {0x80013}, 0xfff0, 1, {0xffff0000}, "Privilege Level Changes -- All changes to/from privilege level3 are counted"}, #define PME_MONT_CPU_OP_CYCLES_ALL 199 { "CPU_OP_CYCLES_ALL", {0x1012}, 0xfff0, 1, {0xffff0000}, "CPU Operating Cycles -- All CPU cycles counted"}, #define PME_MONT_CPU_OP_CYCLES_QUAL 200 { "CPU_OP_CYCLES_QUAL", {0x11012}, 0xfff0, 1, {0xffff0003}, "CPU Operating Cycles -- Qualified cycles only"}, #define PME_MONT_CPU_OP_CYCLES_HALTED 201 { "CPU_OP_CYCLES_HALTED", {0x1018}, 0x0400, 7, {0xffff0000}, "CPU Operating Cycles Halted"}, #define PME_MONT_DATA_DEBUG_REGISTER_FAULT 202 { "DATA_DEBUG_REGISTER_FAULT", {0x52}, 0xfff0, 1, {0xffff0000}, "Fault Due to Data Debug Reg. Match to Load/Store Instruction"}, #define PME_MONT_DATA_DEBUG_REGISTER_MATCHES 203 { "DATA_DEBUG_REGISTER_MATCHES", {0xc6}, 0xfff0, 1, {0xffff0007}, "Data Debug Register Matches Data Address of Memory Reference."}, #define PME_MONT_DATA_EAR_ALAT 204 { "DATA_EAR_ALAT", {0xec8}, 0xfff0, 1, {0xffff0007}, "Data EAR ALAT"}, #define PME_MONT_DATA_EAR_CACHE_LAT1024 205 { "DATA_EAR_CACHE_LAT1024", {0x80dc8}, 0xfff0, 1, {0xffff0007}, "Data EAR Cache -- >= 1024 Cycles"}, #define PME_MONT_DATA_EAR_CACHE_LAT128 206 { "DATA_EAR_CACHE_LAT128", {0x50dc8}, 0xfff0, 1, {0xffff0007}, "Data EAR Cache -- >= 128 Cycles"}, #define PME_MONT_DATA_EAR_CACHE_LAT16 207 { "DATA_EAR_CACHE_LAT16", {0x20dc8}, 0xfff0, 1, {0xffff0007}, "Data EAR Cache -- >= 16 Cycles"}, #define PME_MONT_DATA_EAR_CACHE_LAT2048 208 { "DATA_EAR_CACHE_LAT2048", {0x90dc8}, 0xfff0, 1, {0xffff0007}, "Data EAR Cache -- >= 2048 Cycles"}, #define PME_MONT_DATA_EAR_CACHE_LAT256 209 { "DATA_EAR_CACHE_LAT256", {0x60dc8}, 0xfff0, 1, {0xffff0007}, "Data EAR Cache -- >= 256 Cycles"}, #define PME_MONT_DATA_EAR_CACHE_LAT32 210 { "DATA_EAR_CACHE_LAT32", {0x30dc8}, 0xfff0, 1, {0xffff0007}, "Data EAR Cache -- >= 32 Cycles"}, #define PME_MONT_DATA_EAR_CACHE_LAT4 211 { "DATA_EAR_CACHE_LAT4", {0xdc8}, 0xfff0, 1, {0xffff0007}, "Data EAR Cache -- >= 4 Cycles"}, #define PME_MONT_DATA_EAR_CACHE_LAT4096 212 { "DATA_EAR_CACHE_LAT4096", {0xa0dc8}, 0xfff0, 1, {0xffff0007}, "Data EAR Cache -- >= 4096 Cycles"}, #define PME_MONT_DATA_EAR_CACHE_LAT512 213 { "DATA_EAR_CACHE_LAT512", {0x70dc8}, 0xfff0, 1, {0xffff0007}, "Data EAR Cache -- >= 512 Cycles"}, #define PME_MONT_DATA_EAR_CACHE_LAT64 214 { "DATA_EAR_CACHE_LAT64", {0x40dc8}, 0xfff0, 1, {0xffff0007}, "Data EAR Cache -- >= 64 Cycles"}, #define PME_MONT_DATA_EAR_CACHE_LAT8 215 { "DATA_EAR_CACHE_LAT8", {0x10dc8}, 0xfff0, 1, {0xffff0007}, "Data EAR Cache -- >= 8 Cycles"}, #define PME_MONT_DATA_EAR_EVENTS 216 { "DATA_EAR_EVENTS", {0x8c8}, 0xfff0, 1, {0xffff0007}, "L1 Data Cache EAR Events"}, #define PME_MONT_DATA_EAR_TLB_ALL 217 { "DATA_EAR_TLB_ALL", {0xe0cc8}, 0xfff0, 1, {0xffff0007}, "Data EAR TLB -- All L1 DTLB Misses"}, #define PME_MONT_DATA_EAR_TLB_FAULT 218 { "DATA_EAR_TLB_FAULT", {0x80cc8}, 0xfff0, 1, {0xffff0007}, "Data EAR TLB -- DTLB Misses which produce a software fault"}, #define PME_MONT_DATA_EAR_TLB_L2DTLB 219 { "DATA_EAR_TLB_L2DTLB", {0x20cc8}, 0xfff0, 1, {0xffff0007}, "Data EAR TLB -- L1 DTLB Misses which hit L2 DTLB"}, #define PME_MONT_DATA_EAR_TLB_L2DTLB_OR_FAULT 220 { "DATA_EAR_TLB_L2DTLB_OR_FAULT", {0xa0cc8}, 0xfff0, 1, {0xffff0007}, "Data EAR TLB -- L1 DTLB Misses which hit L2 DTLB or produce a software fault"}, #define PME_MONT_DATA_EAR_TLB_L2DTLB_OR_VHPT 221 { "DATA_EAR_TLB_L2DTLB_OR_VHPT", {0x60cc8}, 0xfff0, 1, {0xffff0007}, "Data EAR TLB -- L1 DTLB Misses which hit L2 DTLB or VHPT"}, #define PME_MONT_DATA_EAR_TLB_VHPT 222 { "DATA_EAR_TLB_VHPT", {0x40cc8}, 0xfff0, 1, {0xffff0007}, "Data EAR TLB -- L1 DTLB Misses which hit VHPT"}, #define PME_MONT_DATA_EAR_TLB_VHPT_OR_FAULT 223 { "DATA_EAR_TLB_VHPT_OR_FAULT", {0xc0cc8}, 0xfff0, 1, {0xffff0007}, "Data EAR TLB -- L1 DTLB Misses which hit VHPT or produce a software fault"}, #define PME_MONT_DATA_REFERENCES_SET0 224 { "DATA_REFERENCES_SET0", {0xc3}, 0xfff0, 4, {0x5010007}, "Data Memory References Issued to Memory Pipeline"}, #define PME_MONT_DATA_REFERENCES_SET1 225 { "DATA_REFERENCES_SET1", {0xc5}, 0xfff0, 4, {0x5110007}, "Data Memory References Issued to Memory Pipeline"}, #define PME_MONT_DISP_STALLED 226 { "DISP_STALLED", {0x49}, 0xfff0, 1, {0xffff0000}, "Number of Cycles Dispersal Stalled"}, #define PME_MONT_DTLB_INSERTS_HPW 227 { "DTLB_INSERTS_HPW", {0x8c9}, 0xfff0, 4, {0xffff0000}, "Hardware Page Walker Installs to DTLB"}, #define PME_MONT_ENCBR_MISPRED_DETAIL_ALL_ALL_PRED 228 { "ENCBR_MISPRED_DETAIL_ALL_ALL_PRED", {0x63}, 0xfff0, 3, {0xffff0003}, "Number of Encoded Branches Retired -- All encoded branches regardless of prediction result"}, #define PME_MONT_ENCBR_MISPRED_DETAIL_ALL_CORRECT_PRED 229 { "ENCBR_MISPRED_DETAIL_ALL_CORRECT_PRED", {0x10063}, 0xfff0, 3, {0xffff0003}, "Number of Encoded Branches Retired -- All encoded branches, correctly predicted branches (outcome and target)"}, #define PME_MONT_ENCBR_MISPRED_DETAIL_ALL_WRONG_PATH 230 { "ENCBR_MISPRED_DETAIL_ALL_WRONG_PATH", {0x20063}, 0xfff0, 3, {0xffff0003}, "Number of Encoded Branches Retired -- All encoded branches, mispredicted branches due to wrong branch direction"}, #define PME_MONT_ENCBR_MISPRED_DETAIL_ALL_WRONG_TARGET 231 { "ENCBR_MISPRED_DETAIL_ALL_WRONG_TARGET", {0x30063}, 0xfff0, 3, {0xffff0003}, "Number of Encoded Branches Retired -- All encoded branches, mispredicted branches due to wrong target for taken branches"}, #define PME_MONT_ENCBR_MISPRED_DETAIL_ALL2_ALL_PRED 232 { "ENCBR_MISPRED_DETAIL_ALL2_ALL_PRED", {0xc0063}, 0xfff0, 3, {0xffff0003}, "Number of Encoded Branches Retired -- Only non-return indirect branches, regardless of prediction result"}, #define PME_MONT_ENCBR_MISPRED_DETAIL_ALL2_CORRECT_PRED 233 { "ENCBR_MISPRED_DETAIL_ALL2_CORRECT_PRED", {0xd0063}, 0xfff0, 3, {0xffff0003}, "Number of Encoded Branches Retired -- Only non-return indirect branches, correctly predicted branches (outcome and target)"}, #define PME_MONT_ENCBR_MISPRED_DETAIL_ALL2_WRONG_PATH 234 { "ENCBR_MISPRED_DETAIL_ALL2_WRONG_PATH", {0xe0063}, 0xfff0, 3, {0xffff0003}, "Number of Encoded Branches Retired -- Only non-return indirect branches, mispredicted branches due to wrong branch direction"}, #define PME_MONT_ENCBR_MISPRED_DETAIL_ALL2_WRONG_TARGET 235 { "ENCBR_MISPRED_DETAIL_ALL2_WRONG_TARGET", {0xf0063}, 0xfff0, 3, {0xffff0003}, "Number of Encoded Branches Retired -- Only non-return indirect branches, mispredicted branches due to wrong target for taken branches"}, #define PME_MONT_ENCBR_MISPRED_DETAIL_OVERSUB_ALL_PRED 236 { "ENCBR_MISPRED_DETAIL_OVERSUB_ALL_PRED", {0x80063}, 0xfff0, 3, {0xffff0003}, "Number of Encoded Branches Retired -- Only return type branches, regardless of prediction result"}, #define PME_MONT_ENCBR_MISPRED_DETAIL_OVERSUB_CORRECT_PRED 237 { "ENCBR_MISPRED_DETAIL_OVERSUB_CORRECT_PRED", {0x90063}, 0xfff0, 3, {0xffff0003}, "Number of Encoded Branches Retired -- Only return type branches, correctly predicted branches (outcome and target)"}, #define PME_MONT_ENCBR_MISPRED_DETAIL_OVERSUB_WRONG_PATH 238 { "ENCBR_MISPRED_DETAIL_OVERSUB_WRONG_PATH", {0xa0063}, 0xfff0, 3, {0xffff0003}, "Number of Encoded Branches Retired -- Only return type branches, mispredicted branches due to wrong branch direction"}, #define PME_MONT_ENCBR_MISPRED_DETAIL_OVERSUB_WRONG_TARGET 239 { "ENCBR_MISPRED_DETAIL_OVERSUB_WRONG_TARGET", {0xb0063}, 0xfff0, 3, {0xffff0003}, "Number of Encoded Branches Retired -- Only return type branches, mispredicted branches due to wrong target for taken branches"}, #define PME_MONT_ER_BKSNP_ME_ACCEPTED 240 { "ER_BKSNP_ME_ACCEPTED", {0x10bb}, 0x03f0, 2, {0xffff0000}, "Backsnoop Me Accepted"}, #define PME_MONT_ER_BRQ_LIVE_REQ_HI 241 { "ER_BRQ_LIVE_REQ_HI", {0x10b8}, 0x03f0, 2, {0xffff0000}, "BRQ Live Requests (upper 2 bits)"}, #define PME_MONT_ER_BRQ_LIVE_REQ_LO 242 { "ER_BRQ_LIVE_REQ_LO", {0x10b9}, 0x03f0, 7, {0xffff0000}, "BRQ Live Requests (lower 3 bits)"}, #define PME_MONT_ER_BRQ_REQ_INSERTED 243 { "ER_BRQ_REQ_INSERTED", {0x8ba}, 0x03f0, 1, {0xffff0000}, "BRQ Requests Inserted"}, #define PME_MONT_ER_MEM_READ_OUT_HI 244 { "ER_MEM_READ_OUT_HI", {0x8b4}, 0x03f0, 2, {0xffff0000}, "Outstanding Memory Read Transactions (upper 2 bits)"}, #define PME_MONT_ER_MEM_READ_OUT_LO 245 { "ER_MEM_READ_OUT_LO", {0x8b5}, 0x03f0, 7, {0xffff0000}, "Outstanding Memory Read Transactions (lower 3 bits)"}, #define PME_MONT_ER_REJECT_ALL_L1D_REQ 246 { "ER_REJECT_ALL_L1D_REQ", {0x10bd}, 0x03f0, 1, {0xffff0000}, "Reject All L1D Requests"}, #define PME_MONT_ER_REJECT_ALL_L1I_REQ 247 { "ER_REJECT_ALL_L1I_REQ", {0x10be}, 0x03f0, 1, {0xffff0000}, "Reject All L1I Requests"}, #define PME_MONT_ER_REJECT_ALL_L1_REQ 248 { "ER_REJECT_ALL_L1_REQ", {0x10bc}, 0x03f0, 1, {0xffff0000}, "Reject All L1 Requests"}, #define PME_MONT_ER_SNOOPQ_REQ_HI 249 { "ER_SNOOPQ_REQ_HI", {0x10b6}, 0x03f0, 2, {0xffff0000}, "Outstanding Snoops (upper bit)"}, #define PME_MONT_ER_SNOOPQ_REQ_LO 250 { "ER_SNOOPQ_REQ_LO", {0x10b7}, 0x03f0, 7, {0xffff0000}, "Outstanding Snoops (lower 3 bits)"}, #define PME_MONT_ETB_EVENT 251 { "ETB_EVENT", {0x111}, 0xfff0, 1, {0xffff0003}, "Execution Trace Buffer Event Captured"}, #define PME_MONT_FE_BUBBLE_ALL 252 { "FE_BUBBLE_ALL", {0x71}, 0xfff0, 1, {0xffff0000}, "Bubbles Seen by FE -- count regardless of cause"}, #define PME_MONT_FE_BUBBLE_ALLBUT_FEFLUSH_BUBBLE 253 { "FE_BUBBLE_ALLBUT_FEFLUSH_BUBBLE", {0xb0071}, 0xfff0, 1, {0xffff0000}, "Bubbles Seen by FE -- ALL except FEFLUSH and BUBBLE"}, #define PME_MONT_FE_BUBBLE_ALLBUT_IBFULL 254 { "FE_BUBBLE_ALLBUT_IBFULL", {0xc0071}, 0xfff0, 1, {0xffff0000}, "Bubbles Seen by FE -- ALL except IBFULl"}, #define PME_MONT_FE_BUBBLE_BRANCH 255 { "FE_BUBBLE_BRANCH", {0x90071}, 0xfff0, 1, {0xffff0000}, "Bubbles Seen by FE -- only if caused by any of 4 branch recirculates"}, #define PME_MONT_FE_BUBBLE_BUBBLE 256 { "FE_BUBBLE_BUBBLE", {0xd0071}, 0xfff0, 1, {0xffff0000}, "Bubbles Seen by FE -- only if caused by branch bubble stall"}, #define PME_MONT_FE_BUBBLE_FEFLUSH 257 { "FE_BUBBLE_FEFLUSH", {0x10071}, 0xfff0, 1, {0xffff0000}, "Bubbles Seen by FE -- only if caused by a front-end flush"}, #define PME_MONT_FE_BUBBLE_FILL_RECIRC 258 { "FE_BUBBLE_FILL_RECIRC", {0x80071}, 0xfff0, 1, {0xffff0000}, "Bubbles Seen by FE -- only if caused by a recirculate for a cache line fill operation"}, #define PME_MONT_FE_BUBBLE_GROUP1 259 { "FE_BUBBLE_GROUP1", {0x30071}, 0xfff0, 1, {0xffff0000}, "Bubbles Seen by FE -- BUBBLE or BRANCH"}, #define PME_MONT_FE_BUBBLE_GROUP2 260 { "FE_BUBBLE_GROUP2", {0x40071}, 0xfff0, 1, {0xffff0000}, "Bubbles Seen by FE -- IMISS or TLBMISS"}, #define PME_MONT_FE_BUBBLE_GROUP3 261 { "FE_BUBBLE_GROUP3", {0xa0071}, 0xfff0, 1, {0xffff0000}, "Bubbles Seen by FE -- FILL_RECIRC or BRANCH"}, #define PME_MONT_FE_BUBBLE_IBFULL 262 { "FE_BUBBLE_IBFULL", {0x50071}, 0xfff0, 1, {0xffff0000}, "Bubbles Seen by FE -- only if caused by instruction buffer full stall"}, #define PME_MONT_FE_BUBBLE_IMISS 263 { "FE_BUBBLE_IMISS", {0x60071}, 0xfff0, 1, {0xffff0000}, "Bubbles Seen by FE -- only if caused by instruction cache miss stall"}, #define PME_MONT_FE_BUBBLE_TLBMISS 264 { "FE_BUBBLE_TLBMISS", {0x70071}, 0xfff0, 1, {0xffff0000}, "Bubbles Seen by FE -- only if caused by TLB stall"}, #define PME_MONT_FE_LOST_BW_ALL 265 { "FE_LOST_BW_ALL", {0x70}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Entrance to IB -- count regardless of cause"}, #define PME_MONT_FE_LOST_BW_BI 266 { "FE_LOST_BW_BI", {0x90070}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Entrance to IB -- only if caused by branch initialization stall"}, #define PME_MONT_FE_LOST_BW_BRQ 267 { "FE_LOST_BW_BRQ", {0xa0070}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Entrance to IB -- only if caused by branch retirement queue stall"}, #define PME_MONT_FE_LOST_BW_BR_ILOCK 268 { "FE_LOST_BW_BR_ILOCK", {0xc0070}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Entrance to IB -- only if caused by branch interlock stall"}, #define PME_MONT_FE_LOST_BW_BUBBLE 269 { "FE_LOST_BW_BUBBLE", {0xd0070}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Entrance to IB -- only if caused by branch resteer bubble stall"}, #define PME_MONT_FE_LOST_BW_FEFLUSH 270 { "FE_LOST_BW_FEFLUSH", {0x10070}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Entrance to IB -- only if caused by a front-end flush"}, #define PME_MONT_FE_LOST_BW_FILL_RECIRC 271 { "FE_LOST_BW_FILL_RECIRC", {0x80070}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Entrance to IB -- only if caused by a recirculate for a cache line fill operation"}, #define PME_MONT_FE_LOST_BW_IBFULL 272 { "FE_LOST_BW_IBFULL", {0x50070}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Entrance to IB -- only if caused by instruction buffer full stall"}, #define PME_MONT_FE_LOST_BW_IMISS 273 { "FE_LOST_BW_IMISS", {0x60070}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Entrance to IB -- only if caused by instruction cache miss stall"}, #define PME_MONT_FE_LOST_BW_PLP 274 { "FE_LOST_BW_PLP", {0xb0070}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Entrance to IB -- only if caused by perfect loop prediction stall"}, #define PME_MONT_FE_LOST_BW_TLBMISS 275 { "FE_LOST_BW_TLBMISS", {0x70070}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Entrance to IB -- only if caused by TLB stall"}, #define PME_MONT_FE_LOST_BW_UNREACHED 276 { "FE_LOST_BW_UNREACHED", {0x40070}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Entrance to IB -- only if caused by unreachable bundle"}, #define PME_MONT_FP_FAILED_FCHKF 277 { "FP_FAILED_FCHKF", {0x6}, 0xfff0, 1, {0xffff0001}, "Failed fchkf"}, #define PME_MONT_FP_FALSE_SIRSTALL 278 { "FP_FALSE_SIRSTALL", {0x5}, 0xfff0, 1, {0xffff0001}, "SIR Stall Without a Trap"}, #define PME_MONT_FP_FLUSH_TO_ZERO_FTZ_POSS 279 { "FP_FLUSH_TO_ZERO_FTZ_POSS", {0x1000b}, 0xfff0, 2, {0xffff0001}, "FP Result Flushed to Zero -- "}, #define PME_MONT_FP_FLUSH_TO_ZERO_FTZ_REAL 280 { "FP_FLUSH_TO_ZERO_FTZ_REAL", {0xb}, 0xfff0, 2, {0xffff0001}, "FP Result Flushed to Zero -- Times FTZ"}, #define PME_MONT_FP_OPS_RETIRED 281 { "FP_OPS_RETIRED", {0x9}, 0xfff0, 6, {0xffff0001}, "Retired FP Operations"}, #define PME_MONT_FP_TRUE_SIRSTALL 282 { "FP_TRUE_SIRSTALL", {0x3}, 0xfff0, 1, {0xffff0001}, "SIR stall asserted and leads to a trap"}, #define PME_MONT_HPW_DATA_REFERENCES 283 { "HPW_DATA_REFERENCES", {0x2d}, 0xfff0, 4, {0xffff0000}, "Data Memory References to VHPT"}, #define PME_MONT_IA64_INST_RETIRED_THIS 284 { "IA64_INST_RETIRED_THIS", {0x8}, 0xfff0, 6, {0xffff0003}, "Retired IA-64 Instructions -- Retired IA-64 Instructions"}, #define PME_MONT_IA64_TAGGED_INST_RETIRED_IBRP0_PMC32_33 285 { "IA64_TAGGED_INST_RETIRED_IBRP0_PMC32_33", {0x8}, 0xfff0, 6, {0xffff0003}, "Retired Tagged Instructions -- Instruction tagged by Instruction Breakpoint Pair 0 and the opcode matcher pair PMC32 and PMC33."}, #define PME_MONT_IA64_TAGGED_INST_RETIRED_IBRP1_PMC34_35 286 { "IA64_TAGGED_INST_RETIRED_IBRP1_PMC34_35", {0x10008}, 0xfff0, 6, {0xffff0003}, "Retired Tagged Instructions -- Instruction tagged by Instruction Breakpoint Pair 1 and the opcode matcher pair PMC34 and PMC35."}, #define PME_MONT_IA64_TAGGED_INST_RETIRED_IBRP2_PMC32_33 287 { "IA64_TAGGED_INST_RETIRED_IBRP2_PMC32_33", {0x20008}, 0xfff0, 6, {0xffff0003}, "Retired Tagged Instructions -- Instruction tagged by Instruction Breakpoint Pair 2 and the opcode matcher pair PMC32 and PMC33."}, #define PME_MONT_IA64_TAGGED_INST_RETIRED_IBRP3_PMC34_35 288 { "IA64_TAGGED_INST_RETIRED_IBRP3_PMC34_35", {0x30008}, 0xfff0, 6, {0xffff0003}, "Retired Tagged Instructions -- Instruction tagged by Instruction Breakpoint Pair 3 and the opcode matcher pair PMC34 and PMC35."}, #define PME_MONT_IDEAL_BE_LOST_BW_DUE_TO_FE_ALL 289 { "IDEAL_BE_LOST_BW_DUE_TO_FE_ALL", {0x73}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Exit from IB -- count regardless of cause"}, #define PME_MONT_IDEAL_BE_LOST_BW_DUE_TO_FE_BI 290 { "IDEAL_BE_LOST_BW_DUE_TO_FE_BI", {0x90073}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Exit from IB -- only if caused by branch initialization stall"}, #define PME_MONT_IDEAL_BE_LOST_BW_DUE_TO_FE_BRQ 291 { "IDEAL_BE_LOST_BW_DUE_TO_FE_BRQ", {0xa0073}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Exit from IB -- only if caused by branch retirement queue stall"}, #define PME_MONT_IDEAL_BE_LOST_BW_DUE_TO_FE_BR_ILOCK 292 { "IDEAL_BE_LOST_BW_DUE_TO_FE_BR_ILOCK", {0xc0073}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Exit from IB -- only if caused by branch interlock stall"}, #define PME_MONT_IDEAL_BE_LOST_BW_DUE_TO_FE_BUBBLE 293 { "IDEAL_BE_LOST_BW_DUE_TO_FE_BUBBLE", {0xd0073}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Exit from IB -- only if caused by branch resteer bubble stall"}, #define PME_MONT_IDEAL_BE_LOST_BW_DUE_TO_FE_FEFLUSH 294 { "IDEAL_BE_LOST_BW_DUE_TO_FE_FEFLUSH", {0x10073}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Exit from IB -- only if caused by a front-end flush"}, #define PME_MONT_IDEAL_BE_LOST_BW_DUE_TO_FE_FILL_RECIRC 295 { "IDEAL_BE_LOST_BW_DUE_TO_FE_FILL_RECIRC", {0x80073}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Exit from IB -- only if caused by a recirculate for a cache line fill operation"}, #define PME_MONT_IDEAL_BE_LOST_BW_DUE_TO_FE_IBFULL 296 { "IDEAL_BE_LOST_BW_DUE_TO_FE_IBFULL", {0x50073}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Exit from IB -- (* meaningless for this event *)"}, #define PME_MONT_IDEAL_BE_LOST_BW_DUE_TO_FE_IMISS 297 { "IDEAL_BE_LOST_BW_DUE_TO_FE_IMISS", {0x60073}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Exit from IB -- only if caused by instruction cache miss stall"}, #define PME_MONT_IDEAL_BE_LOST_BW_DUE_TO_FE_PLP 298 { "IDEAL_BE_LOST_BW_DUE_TO_FE_PLP", {0xb0073}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Exit from IB -- only if caused by perfect loop prediction stall"}, #define PME_MONT_IDEAL_BE_LOST_BW_DUE_TO_FE_TLBMISS 299 { "IDEAL_BE_LOST_BW_DUE_TO_FE_TLBMISS", {0x70073}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Exit from IB -- only if caused by TLB stall"}, #define PME_MONT_IDEAL_BE_LOST_BW_DUE_TO_FE_UNREACHED 300 { "IDEAL_BE_LOST_BW_DUE_TO_FE_UNREACHED", {0x40073}, 0xfff0, 2, {0xffff0000}, "Invalid Bundles at the Exit from IB -- only if caused by unreachable bundle"}, #define PME_MONT_INST_CHKA_LDC_ALAT_ALL 301 { "INST_CHKA_LDC_ALAT_ALL", {0x30056}, 0xfff0, 2, {0xffff0007}, "Retired chk.a and ld.c Instructions -- both integer and floating point instructions"}, #define PME_MONT_INST_CHKA_LDC_ALAT_FP 302 { "INST_CHKA_LDC_ALAT_FP", {0x20056}, 0xfff0, 2, {0xffff0007}, "Retired chk.a and ld.c Instructions -- only floating point instructions"}, #define PME_MONT_INST_CHKA_LDC_ALAT_INT 303 { "INST_CHKA_LDC_ALAT_INT", {0x10056}, 0xfff0, 2, {0xffff0007}, "Retired chk.a and ld.c Instructions -- only integer instructions"}, #define PME_MONT_INST_DISPERSED 304 { "INST_DISPERSED", {0x4d}, 0xfff0, 6, {0xffff0001}, "Syllables Dispersed from REN to REG stage"}, #define PME_MONT_INST_FAILED_CHKA_LDC_ALAT_ALL 305 { "INST_FAILED_CHKA_LDC_ALAT_ALL", {0x30057}, 0xfff0, 1, {0xffff0007}, "Failed chk.a and ld.c Instructions -- both integer and floating point instructions"}, #define PME_MONT_INST_FAILED_CHKA_LDC_ALAT_FP 306 { "INST_FAILED_CHKA_LDC_ALAT_FP", {0x20057}, 0xfff0, 1, {0xffff0007}, "Failed chk.a and ld.c Instructions -- only floating point instructions"}, #define PME_MONT_INST_FAILED_CHKA_LDC_ALAT_INT 307 { "INST_FAILED_CHKA_LDC_ALAT_INT", {0x10057}, 0xfff0, 1, {0xffff0007}, "Failed chk.a and ld.c Instructions -- only integer instructions"}, #define PME_MONT_INST_FAILED_CHKS_RETIRED_ALL 308 { "INST_FAILED_CHKS_RETIRED_ALL", {0x30055}, 0xfff0, 1, {0xffff0000}, "Failed chk.s Instructions -- both integer and floating point instructions"}, #define PME_MONT_INST_FAILED_CHKS_RETIRED_FP 309 { "INST_FAILED_CHKS_RETIRED_FP", {0x20055}, 0xfff0, 1, {0xffff0000}, "Failed chk.s Instructions -- only floating point instructions"}, #define PME_MONT_INST_FAILED_CHKS_RETIRED_INT 310 { "INST_FAILED_CHKS_RETIRED_INT", {0x10055}, 0xfff0, 1, {0xffff0000}, "Failed chk.s Instructions -- only integer instructions"}, #define PME_MONT_ISB_BUNPAIRS_IN 311 { "ISB_BUNPAIRS_IN", {0x46}, 0xfff0, 1, {0xffff0001}, "Bundle Pairs Written from L2I into FE"}, #define PME_MONT_ITLB_MISSES_FETCH_ALL 312 { "ITLB_MISSES_FETCH_ALL", {0x30047}, 0xfff0, 1, {0xffff0001}, "ITLB Misses Demand Fetch -- All tlb misses will be counted. Note that this is not equal to sum of the L1ITLB and L2ITLB umasks because any access could be a miss in L1ITLB and L2ITLB."}, #define PME_MONT_ITLB_MISSES_FETCH_L1ITLB 313 { "ITLB_MISSES_FETCH_L1ITLB", {0x10047}, 0xfff0, 1, {0xffff0001}, "ITLB Misses Demand Fetch -- All misses in L1ITLB will be counted. even if L1ITLB is not updated for an access (Uncacheable/nat page/not present page/faulting/some flushed), it will be counted here."}, #define PME_MONT_ITLB_MISSES_FETCH_L2ITLB 314 { "ITLB_MISSES_FETCH_L2ITLB", {0x20047}, 0xfff0, 1, {0xffff0001}, "ITLB Misses Demand Fetch -- All misses in L1ITLB which also missed in L2ITLB will be counted."}, #define PME_MONT_L1DTLB_TRANSFER 315 { "L1DTLB_TRANSFER", {0xc0}, 0xfff0, 1, {0x5010007}, "L1DTLB Misses That Hit in the L2DTLB for Accesses Counted in L1D_READS"}, #define PME_MONT_L1D_READS_SET0 316 { "L1D_READS_SET0", {0xc2}, 0xfff0, 2, {0x5010007}, "L1 Data Cache Reads"}, #define PME_MONT_L1D_READS_SET1 317 { "L1D_READS_SET1", {0xc4}, 0xfff0, 2, {0x5110007}, "L1 Data Cache Reads"}, #define PME_MONT_L1D_READ_MISSES_ALL 318 { "L1D_READ_MISSES_ALL", {0xc7}, 0xfff0, 2, {0x5110007}, "L1 Data Cache Read Misses -- all L1D read misses will be counted."}, #define PME_MONT_L1D_READ_MISSES_RSE_FILL 319 { "L1D_READ_MISSES_RSE_FILL", {0x100c7}, 0xfff0, 2, {0x5110007}, "L1 Data Cache Read Misses -- only L1D read misses caused by RSE fills will be counted"}, #define PME_MONT_L1ITLB_INSERTS_HPW 320 { "L1ITLB_INSERTS_HPW", {0x48}, 0xfff0, 1, {0xffff0001}, "L1ITLB Hardware Page Walker Inserts"}, #define PME_MONT_L1I_EAR_CACHE_LAT0 321 { "L1I_EAR_CACHE_LAT0", {0x400b43}, 0xfff0, 1, {0xffff0001}, "L1I EAR Cache -- > 0 Cycles (All L1 Misses)"}, #define PME_MONT_L1I_EAR_CACHE_LAT1024 322 { "L1I_EAR_CACHE_LAT1024", {0xc00b43}, 0xfff0, 1, {0xffff0001}, "L1I EAR Cache -- >= 1024 Cycles"}, #define PME_MONT_L1I_EAR_CACHE_LAT128 323 { "L1I_EAR_CACHE_LAT128", {0xf00b43}, 0xfff0, 1, {0xffff0001}, "L1I EAR Cache -- >= 128 Cycles"}, #define PME_MONT_L1I_EAR_CACHE_LAT16 324 { "L1I_EAR_CACHE_LAT16", {0xfc0b43}, 0xfff0, 1, {0xffff0001}, "L1I EAR Cache -- >= 16 Cycles"}, #define PME_MONT_L1I_EAR_CACHE_LAT256 325 { "L1I_EAR_CACHE_LAT256", {0xe00b43}, 0xfff0, 1, {0xffff0001}, "L1I EAR Cache -- >= 256 Cycles"}, #define PME_MONT_L1I_EAR_CACHE_LAT32 326 { "L1I_EAR_CACHE_LAT32", {0xf80b43}, 0xfff0, 1, {0xffff0001}, "L1I EAR Cache -- >= 32 Cycles"}, #define PME_MONT_L1I_EAR_CACHE_LAT4 327 { "L1I_EAR_CACHE_LAT4", {0xff0b43}, 0xfff0, 1, {0xffff0001}, "L1I EAR Cache -- >= 4 Cycles"}, #define PME_MONT_L1I_EAR_CACHE_LAT4096 328 { "L1I_EAR_CACHE_LAT4096", {0x800b43}, 0xfff0, 1, {0xffff0001}, "L1I EAR Cache -- >= 4096 Cycles"}, #define PME_MONT_L1I_EAR_CACHE_LAT8 329 { "L1I_EAR_CACHE_LAT8", {0xfe0b43}, 0xfff0, 1, {0xffff0001}, "L1I EAR Cache -- >= 8 Cycles"}, #define PME_MONT_L1I_EAR_CACHE_RAB 330 { "L1I_EAR_CACHE_RAB", {0xb43}, 0xfff0, 1, {0xffff0001}, "L1I EAR Cache -- RAB HIT"}, #define PME_MONT_L1I_EAR_EVENTS 331 { "L1I_EAR_EVENTS", {0x843}, 0xfff0, 1, {0xffff0001}, "Instruction EAR Events"}, #define PME_MONT_L1I_EAR_TLB_ALL 332 { "L1I_EAR_TLB_ALL", {0x70a43}, 0xfff0, 1, {0xffff0001}, "L1I EAR TLB -- All L1 ITLB Misses"}, #define PME_MONT_L1I_EAR_TLB_FAULT 333 { "L1I_EAR_TLB_FAULT", {0x40a43}, 0xfff0, 1, {0xffff0001}, "L1I EAR TLB -- ITLB Misses which produced a fault"}, #define PME_MONT_L1I_EAR_TLB_L2TLB 334 { "L1I_EAR_TLB_L2TLB", {0x10a43}, 0xfff0, 1, {0xffff0001}, "L1I EAR TLB -- L1 ITLB Misses which hit L2 ITLB"}, #define PME_MONT_L1I_EAR_TLB_L2TLB_OR_FAULT 335 { "L1I_EAR_TLB_L2TLB_OR_FAULT", {0x50a43}, 0xfff0, 1, {0xffff0001}, "L1I EAR TLB -- L1 ITLB Misses which hit L2 ITLB or produce a software fault"}, #define PME_MONT_L1I_EAR_TLB_L2TLB_OR_VHPT 336 { "L1I_EAR_TLB_L2TLB_OR_VHPT", {0x30a43}, 0xfff0, 1, {0xffff0001}, "L1I EAR TLB -- L1 ITLB Misses which hit L2 ITLB or VHPT"}, #define PME_MONT_L1I_EAR_TLB_VHPT 337 { "L1I_EAR_TLB_VHPT", {0x20a43}, 0xfff0, 1, {0xffff0001}, "L1I EAR TLB -- L1 ITLB Misses which hit VHPT"}, #define PME_MONT_L1I_EAR_TLB_VHPT_OR_FAULT 338 { "L1I_EAR_TLB_VHPT_OR_FAULT", {0x60a43}, 0xfff0, 1, {0xffff0001}, "L1I EAR TLB -- L1 ITLB Misses which hit VHPT or produce a software fault"}, #define PME_MONT_L1I_FETCH_ISB_HIT 339 { "L1I_FETCH_ISB_HIT", {0x66}, 0xfff0, 1, {0xffff0001}, "\"Just-In-Time\" Instruction Fetch Hitting in and Being Bypassed from ISB"}, #define PME_MONT_L1I_FETCH_RAB_HIT 340 { "L1I_FETCH_RAB_HIT", {0x65}, 0xfff0, 1, {0xffff0001}, "Instruction Fetch Hitting in RAB"}, #define PME_MONT_L1I_FILLS 341 { "L1I_FILLS", {0x841}, 0xfff0, 1, {0xffff0001}, "L1 Instruction Cache Fills"}, #define PME_MONT_L1I_PREFETCHES 342 { "L1I_PREFETCHES", {0x44}, 0xfff0, 1, {0xffff0001}, "L1 Instruction Prefetch Requests"}, #define PME_MONT_L1I_PREFETCH_STALL_ALL 343 { "L1I_PREFETCH_STALL_ALL", {0x30067}, 0xfff0, 1, {0xffff0000}, "Prefetch Pipeline Stalls -- Number of clocks prefetch pipeline is stalled"}, #define PME_MONT_L1I_PREFETCH_STALL_FLOW 344 { "L1I_PREFETCH_STALL_FLOW", {0x20067}, 0xfff0, 1, {0xffff0000}, "Prefetch Pipeline Stalls -- Asserted when the streaming prefetcher is working close to the instructions being fetched for demand reads, and is not asserted when the streaming prefetcher is ranging way ahead of the demand reads."}, #define PME_MONT_L1I_PURGE 345 { "L1I_PURGE", {0x104b}, 0xfff0, 1, {0xffff0001}, "L1ITLB Purges Handled by L1I"}, #define PME_MONT_L1I_PVAB_OVERFLOW 346 { "L1I_PVAB_OVERFLOW", {0x69}, 0xfff0, 1, {0xffff0000}, "PVAB Overflow"}, #define PME_MONT_L1I_RAB_ALMOST_FULL 347 { "L1I_RAB_ALMOST_FULL", {0x1064}, 0xfff0, 1, {0xffff0000}, "Is RAB Almost Full?"}, #define PME_MONT_L1I_RAB_FULL 348 { "L1I_RAB_FULL", {0x1060}, 0xfff0, 1, {0xffff0000}, "Is RAB Full?"}, #define PME_MONT_L1I_READS 349 { "L1I_READS", {0x40}, 0xfff0, 1, {0xffff0001}, "L1 Instruction Cache Reads"}, #define PME_MONT_L1I_SNOOP 350 { "L1I_SNOOP", {0x104a}, 0xfff0, 1, {0xffff0007}, "Snoop Requests Handled by L1I"}, #define PME_MONT_L1I_STRM_PREFETCHES 351 { "L1I_STRM_PREFETCHES", {0x5f}, 0xfff0, 1, {0xffff0001}, "L1 Instruction Cache Line Prefetch Requests"}, #define PME_MONT_L2DTLB_MISSES 352 { "L2DTLB_MISSES", {0xc1}, 0xfff0, 4, {0x5010007}, "L2DTLB Misses"}, #define PME_MONT_L2D_BAD_LINES_SELECTED_ANY 353 { "L2D_BAD_LINES_SELECTED_ANY", {0x8ec}, 0xfff0, 4, {0x4520007}, "Valid Line Replaced When Invalid Line Is Available -- Valid line replaced when invalid line is available"}, #define PME_MONT_L2D_BYPASS_L2_DATA1 354 { "L2D_BYPASS_L2_DATA1", {0x8e4}, 0xfff0, 1, {0x4120007}, "Count L2D Bypasses -- Count only L2D data bypasses (L1D to L2A)"}, #define PME_MONT_L2D_BYPASS_L2_DATA2 355 { "L2D_BYPASS_L2_DATA2", {0x108e4}, 0xfff0, 1, {0x4120007}, "Count L2D Bypasses -- Count only L2D data bypasses (L1W to L2I)"}, #define PME_MONT_L2D_BYPASS_L3_DATA1 356 { "L2D_BYPASS_L3_DATA1", {0x208e4}, 0xfff0, 1, {0x4120007}, "Count L2D Bypasses -- Count only L3 data bypasses (L1D to L2A)"}, #define PME_MONT_L2D_FILLB_FULL_THIS 357 { "L2D_FILLB_FULL_THIS", {0x8f1}, 0xfff0, 1, {0x4720000}, "L2D Fill Buffer Is Full -- L2D Fill buffer is full"}, #define PME_MONT_L2D_FILL_MESI_STATE_E 358 { "L2D_FILL_MESI_STATE_E", {0x108f2}, 0xfff0, 1, {0x4820000}, "L2D Cache Fills with MESI state -- "}, #define PME_MONT_L2D_FILL_MESI_STATE_I 359 { "L2D_FILL_MESI_STATE_I", {0x308f2}, 0xfff0, 1, {0x4820000}, "L2D Cache Fills with MESI state -- "}, #define PME_MONT_L2D_FILL_MESI_STATE_M 360 { "L2D_FILL_MESI_STATE_M", {0x8f2}, 0xfff0, 1, {0x4820000}, "L2D Cache Fills with MESI state -- "}, #define PME_MONT_L2D_FILL_MESI_STATE_P 361 { "L2D_FILL_MESI_STATE_P", {0x408f2}, 0xfff0, 1, {0x4820000}, "L2D Cache Fills with MESI state -- "}, #define PME_MONT_L2D_FILL_MESI_STATE_S 362 { "L2D_FILL_MESI_STATE_S", {0x208f2}, 0xfff0, 1, {0x4820000}, "L2D Cache Fills with MESI state -- "}, #define PME_MONT_L2D_FORCE_RECIRC_FILL_HIT 363 { "L2D_FORCE_RECIRC_FILL_HIT", {0x808ea}, 0xfff0, 4, {0x4420007}, "Forced Recirculates -- Count only those caused by an L2D miss which hit in the fill buffer."}, #define PME_MONT_L2D_FORCE_RECIRC_FRC_RECIRC 364 { "L2D_FORCE_RECIRC_FRC_RECIRC", {0x908ea}, 0xfff0, 4, {0x4420007}, "Forced Recirculates -- Caused by an L2D miss when a force recirculate already existed in the Ozq."}, #define PME_MONT_L2D_FORCE_RECIRC_L1W 365 { "L2D_FORCE_RECIRC_L1W", {0xc08ea}, 0xfff0, 4, {0x4420007}, "Forced Recirculates -- Count only those caused by a L2D miss one cycle ahead of the current op."}, #define PME_MONT_L2D_FORCE_RECIRC_LIMBO 366 { "L2D_FORCE_RECIRC_LIMBO", {0x108ea}, 0xfff0, 4, {0x4420007}, "Forced Recirculates -- Count operations that went into the LIMBO Ozq state. This state is entered when the the op sees a FILL_HIT or OZQ_MISS event."}, #define PME_MONT_L2D_FORCE_RECIRC_OZQ_MISS 367 { "L2D_FORCE_RECIRC_OZQ_MISS", {0xb08ea}, 0xfff0, 4, {0x4420007}, "Forced Recirculates -- Caused by an L2D miss when an L2D miss was already in the OZQ."}, #define PME_MONT_L2D_FORCE_RECIRC_RECIRC 368 { "L2D_FORCE_RECIRC_RECIRC", {0x8ea}, 0xfff0, 4, {0x4420007}, "Forced Recirculates -- Counts inserts into OzQ due to a recirculate. The recirculate due to secondary misses or various other conflicts"}, #define PME_MONT_L2D_FORCE_RECIRC_SAME_INDEX 369 { "L2D_FORCE_RECIRC_SAME_INDEX", {0xa08ea}, 0xfff0, 4, {0x4420007}, "Forced Recirculates -- Caused by an L2D miss when a miss to the same index was in the same issue group."}, #define PME_MONT_L2D_FORCE_RECIRC_SECONDARY_ALL 370 { "L2D_FORCE_RECIRC_SECONDARY_ALL", {0xf08ea}, 0xfff0, 4, {0x4420007}, "Forced Recirculates -- CSaused by any L2D op that saw a miss to the same address in OZQ, L2 fill buffer, or one cycle ahead in the main pipeline."}, #define PME_MONT_L2D_FORCE_RECIRC_SECONDARY_READ 371 { "L2D_FORCE_RECIRC_SECONDARY_READ", {0xd08ea}, 0xfff0, 4, {0x4420007}, "Forced Recirculates -- Caused by L2D read op that saw a miss to the same address in OZQ, L2 fill buffer, or one cycle ahead in the main pipeline."}, #define PME_MONT_L2D_FORCE_RECIRC_SECONDARY_WRITE 372 { "L2D_FORCE_RECIRC_SECONDARY_WRITE", {0xe08ea}, 0xfff0, 4, {0x4420007}, "Forced Recirculates -- Caused by L2D write op that saw a miss to the same address in OZQ, L2 fill buffer, or one cycle ahead in the main pipeline."}, #define PME_MONT_L2D_FORCE_RECIRC_SNP_OR_L3 373 { "L2D_FORCE_RECIRC_SNP_OR_L3", {0x608ea}, 0xfff0, 4, {0x4420007}, "Forced Recirculates -- Count only those caused by a snoop or L3 issue."}, #define PME_MONT_L2D_FORCE_RECIRC_TAG_NOTOK 374 { "L2D_FORCE_RECIRC_TAG_NOTOK", {0x408ea}, 0xfff0, 4, {0x4420007}, "Forced Recirculates -- Count only those caused by L2D hits caused by in flight snoops, stores with a sibling miss to the same index, sibling probe to the same line or a pending mf.a instruction. This count can usually be ignored since its events are rare, unpredictable, and/or show up in one of the other events."}, #define PME_MONT_L2D_FORCE_RECIRC_TAG_OK 375 { "L2D_FORCE_RECIRC_TAG_OK", {0x708ea}, 0xfff0, 4, {0x4420007}, "Forced Recirculates -- Count operations that inserted to Ozq as a hit. Thus it was NOT forced to recirculate. Likely identical to L2D_INSERT_HITS."}, #define PME_MONT_L2D_FORCE_RECIRC_TRAN_PREF 376 { "L2D_FORCE_RECIRC_TRAN_PREF", {0x508ea}, 0xfff0, 4, {0x4420007}, "Forced Recirculates -- Count only those caused by L2D miss requests that transformed to prefetches"}, #define PME_MONT_L2D_INSERT_HITS 377 { "L2D_INSERT_HITS", {0x8b1}, 0xfff0, 4, {0xffff0007}, "Count Number of Times an Inserting Data Request Hit in the L2D."}, #define PME_MONT_L2D_INSERT_MISSES 378 { "L2D_INSERT_MISSES", {0x8b0}, 0xfff0, 4, {0xffff0007}, "Count Number of Times an Inserting Data Request Missed the L2D."}, #define PME_MONT_L2D_ISSUED_RECIRC_OZQ_ACC 379 { "L2D_ISSUED_RECIRC_OZQ_ACC", {0x8eb}, 0xfff0, 1, {0x4420007}, "Count Number of Times a Recirculate Issue Was Attempted and Not Preempted"}, #define PME_MONT_L2D_L3ACCESS_CANCEL_ANY 380 { "L2D_L3ACCESS_CANCEL_ANY", {0x208e8}, 0xfff0, 1, {0x4320007}, "L2D Access Cancelled by L2D -- count cancels due to any reason. This umask will count more than the sum of all the other umasks. It will count things that weren't committed accesses when they reached L1w, but the L2D attempted to bypass them to the L3 anyway (speculatively). This will include accesses made repeatedly while the main pipeline is stalled and the L1D is attempting to recirculate an access down the L1D pipeline. Thus, an access could get counted many times before it really does get bypassed to the L3. It is a measure of how many times we asserted a request to the L3 but didn't confirm it."}, #define PME_MONT_L2D_L3ACCESS_CANCEL_ER_REJECT 381 { "L2D_L3ACCESS_CANCEL_ER_REJECT", {0x308e8}, 0xfff0, 1, {0x4320007}, "L2D Access Cancelled by L2D -- Count only requests that were rejected by ER"}, #define PME_MONT_L2D_L3ACCESS_CANCEL_INV_L3_BYP 382 { "L2D_L3ACCESS_CANCEL_INV_L3_BYP", {0x8e8}, 0xfff0, 1, {0x4320007}, "L2D Access Cancelled by L2D -- L2D cancelled a bypass because it did not commit, or was not a valid opcode to bypass, or was not a true miss of L2D (either hit,recirc,or limbo)."}, #define PME_MONT_L2D_L3ACCESS_CANCEL_P2_COV_SNP_FILL_NOSNP 383 { "L2D_L3ACCESS_CANCEL_P2_COV_SNP_FILL_NOSNP", {0x608e8}, 0xfff0, 1, {0x4320007}, "L2D Access Cancelled by L2D -- A snoop and a fill to the same address reached the L2D within a 3 cycle window of each other or a snoop hit a nosnoops entry in Ozq."}, #define PME_MONT_L2D_L3ACCESS_CANCEL_P2_COV_SNP_TEM 384 { "L2D_L3ACCESS_CANCEL_P2_COV_SNP_TEM", {0x408e8}, 0xfff0, 1, {0x4320007}, "L2D Access Cancelled by L2D -- A snoop saw an L2D tag error and missed/"}, #define PME_MONT_L2D_L3ACCESS_CANCEL_P2_COV_SNP_VIC 385 { "L2D_L3ACCESS_CANCEL_P2_COV_SNP_VIC", {0x508e8}, 0xfff0, 1, {0x4320007}, "L2D Access Cancelled by L2D -- A snoop hit in the L1D victim buffer"}, #define PME_MONT_L2D_L3ACCESS_CANCEL_SPEC_L3_BYP 386 { "L2D_L3ACCESS_CANCEL_SPEC_L3_BYP", {0x108e8}, 0xfff0, 1, {0x4320007}, "L2D Access Cancelled by L2D -- L2D cancelled speculative L3 bypasses because it was not a WB memory attribute or it was an effective release."}, #define PME_MONT_L2D_L3ACCESS_CANCEL_TAIL_TRANS_DIS 387 { "L2D_L3ACCESS_CANCEL_TAIL_TRANS_DIS", {0x708e8}, 0xfff0, 1, {0x4320007}, "L2D Access Cancelled by L2D -- Count the number of cycles that either transform to prefetches or Ozq tail collapse have been dynamically disabled. This would indicate that memory contention has lead the L2D to throttle request to prevent livelock scenarios."}, #define PME_MONT_L2D_MISSES 388 { "L2D_MISSES", {0x8cb}, 0xfff0, 1, {0xffff0007}, "L2 Misses"}, #define PME_MONT_L2D_OPS_ISSUED_FP_LOAD 389 { "L2D_OPS_ISSUED_FP_LOAD", {0x108f0}, 0xfff0, 4, {0xffff0007}, "Operations Issued By L2D -- Count only valid floating-point loads"}, #define PME_MONT_L2D_OPS_ISSUED_INT_LOAD 390 { "L2D_OPS_ISSUED_INT_LOAD", {0x8f0}, 0xfff0, 4, {0xffff0007}, "Operations Issued By L2D -- Count only valid integer loads, including ld16."}, #define PME_MONT_L2D_OPS_ISSUED_LFETCH 391 { "L2D_OPS_ISSUED_LFETCH", {0x408f0}, 0xfff0, 4, {0xffff0007}, "Operations Issued By L2D -- Count only lfetch operations."}, #define PME_MONT_L2D_OPS_ISSUED_OTHER 392 { "L2D_OPS_ISSUED_OTHER", {0x508f0}, 0xfff0, 4, {0xffff0007}, "Operations Issued By L2D -- Count only valid non-load, no-store accesses that are not in any of the above sections."}, #define PME_MONT_L2D_OPS_ISSUED_RMW 393 { "L2D_OPS_ISSUED_RMW", {0x208f0}, 0xfff0, 4, {0xffff0007}, "Operations Issued By L2D -- Count only valid read_modify_write stores and semaphores including cmp8xchg16."}, #define PME_MONT_L2D_OPS_ISSUED_STORE 394 { "L2D_OPS_ISSUED_STORE", {0x308f0}, 0xfff0, 4, {0xffff0007}, "Operations Issued By L2D -- Count only valid non-read_modify_write stores, including st16."}, #define PME_MONT_L2D_OZDB_FULL_THIS 395 { "L2D_OZDB_FULL_THIS", {0x8e9}, 0xfff0, 1, {0x4320000}, "L2D OZ Data Buffer Is Full -- L2 OZ Data Buffer is full"}, #define PME_MONT_L2D_OZQ_ACQUIRE 396 { "L2D_OZQ_ACQUIRE", {0x8ef}, 0xfff0, 1, {0x4620000}, "Acquire Ordering Attribute Exists in L2D OZQ"}, #define PME_MONT_L2D_OZQ_CANCELS0_ACQ 397 { "L2D_OZQ_CANCELS0_ACQ", {0x608e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- caused by an acquire somewhere in Ozq or ER."}, #define PME_MONT_L2D_OZQ_CANCELS0_BANK_CONF 398 { "L2D_OZQ_CANCELS0_BANK_CONF", {0x808e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- a bypassed L2D hit operation had a bank conflict with an older sibling bypass or an older operation in the L2D pipeline."}, #define PME_MONT_L2D_OZQ_CANCELS0_CANC_L2M_TO_L2C_ST 399 { "L2D_OZQ_CANCELS0_CANC_L2M_TO_L2C_ST", {0x108e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- caused by a canceled store in L2M,L2D or L2C. This is the combination of following subevents that were available separately in Itanium2: CANC_L2M_ST=caused by canceled store in L2M, CANC_L2D_ST=caused by canceled store in L2D, CANC_L2C_ST=caused by canceled store in L2C"}, #define PME_MONT_L2D_OZQ_CANCELS0_FILL_ST_CONF 400 { "L2D_OZQ_CANCELS0_FILL_ST_CONF", {0xe08e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- an OZQ store conflicted with a returning L2D fill"}, #define PME_MONT_L2D_OZQ_CANCELS0_L2A_ST_MAT 401 { "L2D_OZQ_CANCELS0_L2A_ST_MAT", {0x208e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- canceled due to an uncanceled store match in L2A"}, #define PME_MONT_L2D_OZQ_CANCELS0_L2C_ST_MAT 402 { "L2D_OZQ_CANCELS0_L2C_ST_MAT", {0x508e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- canceled due to an uncanceled store match in L2C"}, #define PME_MONT_L2D_OZQ_CANCELS0_L2D_ST_MAT 403 { "L2D_OZQ_CANCELS0_L2D_ST_MAT", {0x408e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- canceled due to an uncanceled store match in L2D"}, #define PME_MONT_L2D_OZQ_CANCELS0_L2M_ST_MAT 404 { "L2D_OZQ_CANCELS0_L2M_ST_MAT", {0x308e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- canceled due to an uncanceled store match in L2M"}, #define PME_MONT_L2D_OZQ_CANCELS0_MISC_ORDER 405 { "L2D_OZQ_CANCELS0_MISC_ORDER", {0xd08e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- a sync.i or mf.a . This is the combination of following subevents that were available separately in Itanium2: SYNC=caused by sync.i, MFA=a memory fence instruction"}, #define PME_MONT_L2D_OZQ_CANCELS0_OVER_SUB 406 { "L2D_OZQ_CANCELS0_OVER_SUB", {0xa08e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- a high Ozq issue rate resulted in the L2D having to cancel due to hardware restrictions. This is the combination of following subevents that were available separately in Itanium2: OVER_SUB=oversubscription, L1DF_L2M=L1D fill in L2M"}, #define PME_MONT_L2D_OZQ_CANCELS0_OZDATA_CONF 407 { "L2D_OZQ_CANCELS0_OZDATA_CONF", {0xf08e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- an OZQ operation that needed to read the OZQ data buffer conflicted with a fill return that needed to do the same."}, #define PME_MONT_L2D_OZQ_CANCELS0_OZQ_PREEMPT 408 { "L2D_OZQ_CANCELS0_OZQ_PREEMPT", {0xb08e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- an L2D fill return conflicted with, and cancelled, an ozq request for various reasons. Formerly known as L1_FILL_CONF."}, #define PME_MONT_L2D_OZQ_CANCELS0_RECIRC 409 { "L2D_OZQ_CANCELS0_RECIRC", {0x8e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- a recirculate was cancelled due h/w limitations on recirculate issue rate. This is the combination of following subevents that were available separately in Itanium2: RECIRC_OVER_SUB=caused by a recirculate oversubscription, DIDNT_RECIRC=caused because it did not recirculate, WEIRD=counts the cancels caused by attempted 5-cycle bypasses for non-aligned accesses and bypasses blocking recirculates for too long"}, #define PME_MONT_L2D_OZQ_CANCELS0_REL 410 { "L2D_OZQ_CANCELS0_REL", {0x708e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- a release was cancelled due to some other operation"}, #define PME_MONT_L2D_OZQ_CANCELS0_SEMA 411 { "L2D_OZQ_CANCELS0_SEMA", {0x908e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- a semaphore op was cancelled for various ordering or h/w restriction reasons. This is the combination of following subevents that were available separately in Itanium 2: SEM=a semaphore, CCV=a CCV"}, #define PME_MONT_L2D_OZQ_CANCELS0_WB_CONF 412 { "L2D_OZQ_CANCELS0_WB_CONF", {0xc08e0}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Specific Reason Set 0) -- an OZQ request conflicted with an L2D data array read for a writeback. This is the combination of following subevents that were available separately in Itanium2: READ_WB_CONF=a write back conflict, ST_FILL_CONF=a store fill conflict"}, #define PME_MONT_L2D_OZQ_CANCELS1_ANY 413 { "L2D_OZQ_CANCELS1_ANY", {0x8e2}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Late or Any) -- counts the total OZ Queue cancels"}, #define PME_MONT_L2D_OZQ_CANCELS1_LATE_BYP_EFFRELEASE 414 { "L2D_OZQ_CANCELS1_LATE_BYP_EFFRELEASE", {0x308e2}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Late or Any) -- counts the late cancels caused by L1D to L2A bypass effective releases"}, #define PME_MONT_L2D_OZQ_CANCELS1_LATE_SPEC_BYP 415 { "L2D_OZQ_CANCELS1_LATE_SPEC_BYP", {0x108e2}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Late or Any) -- counts the late cancels caused by speculative bypasses"}, #define PME_MONT_L2D_OZQ_CANCELS1_SIBLING_ACQ_REL 416 { "L2D_OZQ_CANCELS1_SIBLING_ACQ_REL", {0x208e2}, 0xfff0, 4, {0x4020007}, "L2D OZQ Cancels (Late or Any) -- counts the late cancels caused by releases and acquires in the same issue group. This is the combination of following subevents that were available separately in Itanium2: LATE_ACQUIRE=late cancels caused by acquires, LATE_RELEASE=late cancles caused by releases"}, #define PME_MONT_L2D_OZQ_FULL_THIS 417 { "L2D_OZQ_FULL_THIS", {0x8bc}, 0xfff0, 1, {0x4520000}, "L2D OZQ Is Full -- L2D OZQ is full"}, #define PME_MONT_L2D_OZQ_RELEASE 418 { "L2D_OZQ_RELEASE", {0x8e5}, 0xfff0, 1, {0x4120000}, "Release Ordering Attribute Exists in L2D OZQ"}, #define PME_MONT_L2D_REFERENCES_ALL 419 { "L2D_REFERENCES_ALL", {0x308e6}, 0xfff0, 4, {0x4220007}, "Data Read/Write Access to L2D -- count both read and write operations (semaphores will count as 2)"}, #define PME_MONT_L2D_REFERENCES_READS 420 { "L2D_REFERENCES_READS", {0x108e6}, 0xfff0, 4, {0x4220007}, "Data Read/Write Access to L2D -- count only data read and semaphore operations."}, #define PME_MONT_L2D_REFERENCES_WRITES 421 { "L2D_REFERENCES_WRITES", {0x208e6}, 0xfff0, 4, {0x4220007}, "Data Read/Write Access to L2D -- count only data write and semaphore operations"}, #define PME_MONT_L2D_STORE_HIT_SHARED_ANY 422 { "L2D_STORE_HIT_SHARED_ANY", {0x8ed}, 0xfff0, 2, {0x4520007}, "Store Hit a Shared Line -- Store hit a shared line"}, #define PME_MONT_L2D_VICTIMB_FULL_THIS 423 { "L2D_VICTIMB_FULL_THIS", {0x8f3}, 0xfff0, 1, {0x4820000}, "L2D Victim Buffer Is Full -- L2D victim buffer is full"}, #define PME_MONT_L2I_DEMAND_READS 424 { "L2I_DEMAND_READS", {0x42}, 0xfff0, 1, {0xffff0001}, "L2 Instruction Demand Fetch Requests"}, #define PME_MONT_L2I_HIT_CONFLICTS_ALL_ALL 425 { "L2I_HIT_CONFLICTS_ALL_ALL", {0xf087d}, 0xfff0, 1, {0xffff0001}, "L2I hit conflicts -- All fetches that reference L2I are counted"}, #define PME_MONT_L2I_HIT_CONFLICTS_ALL_DMND 426 { "L2I_HIT_CONFLICTS_ALL_DMND", {0xd087d}, 0xfff0, 1, {0xffff0001}, "L2I hit conflicts -- Only demand fetches that reference L2I are counted"}, #define PME_MONT_L2I_HIT_CONFLICTS_ALL_PFTCH 427 { "L2I_HIT_CONFLICTS_ALL_PFTCH", {0xe087d}, 0xfff0, 1, {0xffff0001}, "L2I hit conflicts -- Only prefetches that reference L2I are counted"}, #define PME_MONT_L2I_HIT_CONFLICTS_HIT_ALL 428 { "L2I_HIT_CONFLICTS_HIT_ALL", {0x7087d}, 0xfff0, 1, {0xffff0001}, "L2I hit conflicts -- All fetches that hit in L2I counted"}, #define PME_MONT_L2I_HIT_CONFLICTS_HIT_DMND 429 { "L2I_HIT_CONFLICTS_HIT_DMND", {0x5087d}, 0xfff0, 1, {0xffff0001}, "L2I hit conflicts -- Only demand fetches that hit in L2I are counted"}, #define PME_MONT_L2I_HIT_CONFLICTS_HIT_PFTCH 430 { "L2I_HIT_CONFLICTS_HIT_PFTCH", {0x6087d}, 0xfff0, 1, {0xffff0001}, "L2I hit conflicts -- Only prefetches that hit in L2I are counted"}, #define PME_MONT_L2I_HIT_CONFLICTS_MISS_ALL 431 { "L2I_HIT_CONFLICTS_MISS_ALL", {0xb087d}, 0xfff0, 1, {0xffff0001}, "L2I hit conflicts -- All fetches that miss in L2I are counted"}, #define PME_MONT_L2I_HIT_CONFLICTS_MISS_DMND 432 { "L2I_HIT_CONFLICTS_MISS_DMND", {0x9087d}, 0xfff0, 1, {0xffff0001}, "L2I hit conflicts -- Only demand fetches that miss in L2I are counted"}, #define PME_MONT_L2I_HIT_CONFLICTS_MISS_PFTCH 433 { "L2I_HIT_CONFLICTS_MISS_PFTCH", {0xa087d}, 0xfff0, 1, {0xffff0001}, "L2I hit conflicts -- Only prefetches that miss in L2I are counted"}, #define PME_MONT_L2I_L3_REJECTS_ALL_ALL 434 { "L2I_L3_REJECTS_ALL_ALL", {0xf087c}, 0xfff0, 1, {0xffff0001}, "L3 rejects -- All fetches that reference L2I are counted"}, #define PME_MONT_L2I_L3_REJECTS_ALL_DMND 435 { "L2I_L3_REJECTS_ALL_DMND", {0xd087c}, 0xfff0, 1, {0xffff0001}, "L3 rejects -- Only demand fetches that reference L2I are counted"}, #define PME_MONT_L2I_L3_REJECTS_ALL_PFTCH 436 { "L2I_L3_REJECTS_ALL_PFTCH", {0xe087c}, 0xfff0, 1, {0xffff0001}, "L3 rejects -- Only prefetches that reference L2I are counted"}, #define PME_MONT_L2I_L3_REJECTS_HIT_ALL 437 { "L2I_L3_REJECTS_HIT_ALL", {0x7087c}, 0xfff0, 1, {0xffff0001}, "L3 rejects -- All fetches that hit in L2I counted"}, #define PME_MONT_L2I_L3_REJECTS_HIT_DMND 438 { "L2I_L3_REJECTS_HIT_DMND", {0x5087c}, 0xfff0, 1, {0xffff0001}, "L3 rejects -- Only demand fetches that hit in L2I are counted"}, #define PME_MONT_L2I_L3_REJECTS_HIT_PFTCH 439 { "L2I_L3_REJECTS_HIT_PFTCH", {0x6087c}, 0xfff0, 1, {0xffff0001}, "L3 rejects -- Only prefetches that hit in L2I are counted"}, #define PME_MONT_L2I_L3_REJECTS_MISS_ALL 440 { "L2I_L3_REJECTS_MISS_ALL", {0xb087c}, 0xfff0, 1, {0xffff0001}, "L3 rejects -- All fetches that miss in L2I are counted"}, #define PME_MONT_L2I_L3_REJECTS_MISS_DMND 441 { "L2I_L3_REJECTS_MISS_DMND", {0x9087c}, 0xfff0, 1, {0xffff0001}, "L3 rejects -- Only demand fetches that miss in L2I are counted"}, #define PME_MONT_L2I_L3_REJECTS_MISS_PFTCH 442 { "L2I_L3_REJECTS_MISS_PFTCH", {0xa087c}, 0xfff0, 1, {0xffff0001}, "L3 rejects -- Only prefetches that miss in L2I are counted"}, #define PME_MONT_L2I_PREFETCHES 443 { "L2I_PREFETCHES", {0x45}, 0xfff0, 1, {0xffff0001}, "L2 Instruction Prefetch Requests"}, #define PME_MONT_L2I_READS_ALL_ALL 444 { "L2I_READS_ALL_ALL", {0xf0878}, 0xfff0, 1, {0xffff0001}, "L2I Cacheable Reads -- All fetches that reference L2I are counted"}, #define PME_MONT_L2I_READS_ALL_DMND 445 { "L2I_READS_ALL_DMND", {0xd0878}, 0xfff0, 1, {0xffff0001}, "L2I Cacheable Reads -- Only demand fetches that reference L2I are counted"}, #define PME_MONT_L2I_READS_ALL_PFTCH 446 { "L2I_READS_ALL_PFTCH", {0xe0878}, 0xfff0, 1, {0xffff0001}, "L2I Cacheable Reads -- Only prefetches that reference L2I are counted"}, #define PME_MONT_L2I_READS_HIT_ALL 447 { "L2I_READS_HIT_ALL", {0x70878}, 0xfff0, 1, {0xffff0001}, "L2I Cacheable Reads -- All fetches that hit in L2I counted"}, #define PME_MONT_L2I_READS_HIT_DMND 448 { "L2I_READS_HIT_DMND", {0x50878}, 0xfff0, 1, {0xffff0001}, "L2I Cacheable Reads -- Only demand fetches that hit in L2I are counted"}, #define PME_MONT_L2I_READS_HIT_PFTCH 449 { "L2I_READS_HIT_PFTCH", {0x60878}, 0xfff0, 1, {0xffff0001}, "L2I Cacheable Reads -- Only prefetches that hit in L2I are counted"}, #define PME_MONT_L2I_READS_MISS_ALL 450 { "L2I_READS_MISS_ALL", {0xb0878}, 0xfff0, 1, {0xffff0001}, "L2I Cacheable Reads -- All fetches that miss in L2I are counted"}, #define PME_MONT_L2I_READS_MISS_DMND 451 { "L2I_READS_MISS_DMND", {0x90878}, 0xfff0, 1, {0xffff0001}, "L2I Cacheable Reads -- Only demand fetches that miss in L2I are counted"}, #define PME_MONT_L2I_READS_MISS_PFTCH 452 { "L2I_READS_MISS_PFTCH", {0xa0878}, 0xfff0, 1, {0xffff0001}, "L2I Cacheable Reads -- Only prefetches that miss in L2I are counted"}, #define PME_MONT_L2I_RECIRCULATES_ALL_ALL 453 { "L2I_RECIRCULATES_ALL_ALL", {0xf087b}, 0xfff0, 1, {0xffff0001}, "L2I recirculates -- All fetches that reference L2I are counted"}, #define PME_MONT_L2I_RECIRCULATES_ALL_DMND 454 { "L2I_RECIRCULATES_ALL_DMND", {0xd087b}, 0xfff0, 1, {0xffff0001}, "L2I recirculates -- Only demand fetches that reference L2I are counted"}, #define PME_MONT_L2I_RECIRCULATES_ALL_PFTCH 455 { "L2I_RECIRCULATES_ALL_PFTCH", {0xe087b}, 0xfff0, 1, {0xffff0001}, "L2I recirculates -- Only prefetches that reference L2I are counted"}, #define PME_MONT_L2I_RECIRCULATES_HIT_ALL 456 { "L2I_RECIRCULATES_HIT_ALL", {0x7087b}, 0xfff0, 1, {0xffff0001}, "L2I recirculates -- All fetches that hit in L2I counted"}, #define PME_MONT_L2I_RECIRCULATES_HIT_DMND 457 { "L2I_RECIRCULATES_HIT_DMND", {0x5087b}, 0xfff0, 1, {0xffff0001}, "L2I recirculates -- Only demand fetches that hit in L2I are counted"}, #define PME_MONT_L2I_RECIRCULATES_HIT_PFTCH 458 { "L2I_RECIRCULATES_HIT_PFTCH", {0x6087b}, 0xfff0, 1, {0xffff0001}, "L2I recirculates -- Only prefetches that hit in L2I are counted"}, #define PME_MONT_L2I_RECIRCULATES_MISS_ALL 459 { "L2I_RECIRCULATES_MISS_ALL", {0xb087b}, 0xfff0, 1, {0xffff0001}, "L2I recirculates -- All fetches that miss in L2I are counted"}, #define PME_MONT_L2I_RECIRCULATES_MISS_DMND 460 { "L2I_RECIRCULATES_MISS_DMND", {0x9087b}, 0xfff0, 1, {0xffff0001}, "L2I recirculates -- Only demand fetches that miss in L2I are counted"}, #define PME_MONT_L2I_RECIRCULATES_MISS_PFTCH 461 { "L2I_RECIRCULATES_MISS_PFTCH", {0xa087b}, 0xfff0, 1, {0xffff0001}, "L2I recirculates -- Only prefetches that miss in L2I are counted"}, #define PME_MONT_L2I_SNOOP_HITS 462 { "L2I_SNOOP_HITS", {0x107f}, 0xfff0, 1, {0xffff0000}, "L2I snoop hits"}, #define PME_MONT_L2I_SPEC_ABORTS 463 { "L2I_SPEC_ABORTS", {0x87e}, 0xfff0, 1, {0xffff0001}, "L2I speculative aborts"}, #define PME_MONT_L2I_UC_READS_ALL_ALL 464 { "L2I_UC_READS_ALL_ALL", {0xf0879}, 0xfff0, 1, {0xffff0001}, "L2I Uncacheable reads -- All fetches that reference L2I are counted"}, #define PME_MONT_L2I_UC_READS_ALL_DMND 465 { "L2I_UC_READS_ALL_DMND", {0xd0879}, 0xfff0, 1, {0xffff0001}, "L2I Uncacheable reads -- Only demand fetches that reference L2I are counted"}, #define PME_MONT_L2I_UC_READS_ALL_PFTCH 466 { "L2I_UC_READS_ALL_PFTCH", {0xe0879}, 0xfff0, 1, {0xffff0001}, "L2I Uncacheable reads -- Only prefetches that reference L2I are counted"}, #define PME_MONT_L2I_UC_READS_HIT_ALL 467 { "L2I_UC_READS_HIT_ALL", {0x70879}, 0xfff0, 1, {0xffff0001}, "L2I Uncacheable reads -- All fetches that hit in L2I counted"}, #define PME_MONT_L2I_UC_READS_HIT_DMND 468 { "L2I_UC_READS_HIT_DMND", {0x50879}, 0xfff0, 1, {0xffff0001}, "L2I Uncacheable reads -- Only demand fetches that hit in L2I are counted"}, #define PME_MONT_L2I_UC_READS_HIT_PFTCH 469 { "L2I_UC_READS_HIT_PFTCH", {0x60879}, 0xfff0, 1, {0xffff0001}, "L2I Uncacheable reads -- Only prefetches that hit in L2I are counted"}, #define PME_MONT_L2I_UC_READS_MISS_ALL 470 { "L2I_UC_READS_MISS_ALL", {0xb0879}, 0xfff0, 1, {0xffff0001}, "L2I Uncacheable reads -- All fetches that miss in L2I are counted"}, #define PME_MONT_L2I_UC_READS_MISS_DMND 471 { "L2I_UC_READS_MISS_DMND", {0x90879}, 0xfff0, 1, {0xffff0001}, "L2I Uncacheable reads -- Only demand fetches that miss in L2I are counted"}, #define PME_MONT_L2I_UC_READS_MISS_PFTCH 472 { "L2I_UC_READS_MISS_PFTCH", {0xa0879}, 0xfff0, 1, {0xffff0001}, "L2I Uncacheable reads -- Only prefetches that miss in L2I are counted"}, #define PME_MONT_L2I_VICTIMIZATION 473 { "L2I_VICTIMIZATION", {0x87a}, 0xfff0, 1, {0xffff0001}, "L2I victimizations"}, #define PME_MONT_L3_INSERTS 474 { "L3_INSERTS", {0x8da}, 0xfff0, 1, {0xffff0017}, "L3 Cache Lines inserts"}, #define PME_MONT_L3_LINES_REPLACED 475 { "L3_LINES_REPLACED", {0x8df}, 0xfff0, 1, {0xffff0010}, "L3 Cache Lines Replaced"}, #define PME_MONT_L3_MISSES 476 { "L3_MISSES", {0x8dc}, 0xfff0, 1, {0xffff0007}, "L3 Misses"}, #define PME_MONT_L3_READS_ALL_ALL 477 { "L3_READS_ALL_ALL", {0xf08dd}, 0xfff0, 1, {0xffff0017}, "L3 Reads -- L3 Read References"}, #define PME_MONT_L3_READS_ALL_HIT 478 { "L3_READS_ALL_HIT", {0xd08dd}, 0xfff0, 1, {0xffff0017}, "L3 Reads -- L3 Read Hits"}, #define PME_MONT_L3_READS_ALL_MISS 479 { "L3_READS_ALL_MISS", {0xe08dd}, 0xfff0, 1, {0xffff0017}, "L3 Reads -- L3 Read Misses"}, #define PME_MONT_L3_READS_DATA_READ_ALL 480 { "L3_READS_DATA_READ_ALL", {0xb08dd}, 0xfff0, 1, {0xffff0017}, "L3 Reads -- L3 Load References (excludes reads for ownership used to satisfy stores)"}, #define PME_MONT_L3_READS_DATA_READ_HIT 481 { "L3_READS_DATA_READ_HIT", {0x908dd}, 0xfff0, 1, {0xffff0017}, "L3 Reads -- L3 Load Hits (excludes reads for ownership used to satisfy stores)"}, #define PME_MONT_L3_READS_DATA_READ_MISS 482 { "L3_READS_DATA_READ_MISS", {0xa08dd}, 0xfff0, 1, {0xffff0017}, "L3 Reads -- L3 Load Misses (excludes reads for ownership used to satisfy stores)"}, #define PME_MONT_L3_READS_DINST_FETCH_ALL 483 { "L3_READS_DINST_FETCH_ALL", {0x308dd}, 0xfff0, 1, {0xffff0017}, "L3 Reads -- L3 Demand Instruction References"}, #define PME_MONT_L3_READS_DINST_FETCH_HIT 484 { "L3_READS_DINST_FETCH_HIT", {0x108dd}, 0xfff0, 1, {0xffff0017}, "L3 Reads -- L3 Demand Instruction Fetch Hits"}, #define PME_MONT_L3_READS_DINST_FETCH_MISS 485 { "L3_READS_DINST_FETCH_MISS", {0x208dd}, 0xfff0, 1, {0xffff0017}, "L3 Reads -- L3 Demand Instruction Fetch Misses"}, #define PME_MONT_L3_READS_INST_FETCH_ALL 486 { "L3_READS_INST_FETCH_ALL", {0x708dd}, 0xfff0, 1, {0xffff0017}, "L3 Reads -- L3 Instruction Fetch and Prefetch References"}, #define PME_MONT_L3_READS_INST_FETCH_HIT 487 { "L3_READS_INST_FETCH_HIT", {0x508dd}, 0xfff0, 1, {0xffff0017}, "L3 Reads -- L3 Instruction Fetch and Prefetch Hits"}, #define PME_MONT_L3_READS_INST_FETCH_MISS 488 { "L3_READS_INST_FETCH_MISS", {0x608dd}, 0xfff0, 1, {0xffff0017}, "L3 Reads -- L3 Instruction Fetch and Prefetch Misses"}, #define PME_MONT_L3_REFERENCES 489 { "L3_REFERENCES", {0x8db}, 0xfff0, 1, {0xffff0007}, "L3 References"}, #define PME_MONT_L3_WRITES_ALL_ALL 490 { "L3_WRITES_ALL_ALL", {0xf08de}, 0xfff0, 1, {0xffff0017}, "L3 Writes -- L3 Write References"}, #define PME_MONT_L3_WRITES_ALL_HIT 491 { "L3_WRITES_ALL_HIT", {0xd08de}, 0xfff0, 1, {0xffff0017}, "L3 Writes -- L3 Write Hits"}, #define PME_MONT_L3_WRITES_ALL_MISS 492 { "L3_WRITES_ALL_MISS", {0xe08de}, 0xfff0, 1, {0xffff0017}, "L3 Writes -- L3 Write Misses"}, #define PME_MONT_L3_WRITES_DATA_WRITE_ALL 493 { "L3_WRITES_DATA_WRITE_ALL", {0x708de}, 0xfff0, 1, {0xffff0017}, "L3 Writes -- L3 Store References (excludes L2 write backs, includes L3 read for ownership requests that satisfy stores)"}, #define PME_MONT_L3_WRITES_DATA_WRITE_HIT 494 { "L3_WRITES_DATA_WRITE_HIT", {0x508de}, 0xfff0, 1, {0xffff0017}, "L3 Writes -- L3 Store Hits (excludes L2 write backs, includes L3 read for ownership requests that satisfy stores)"}, #define PME_MONT_L3_WRITES_DATA_WRITE_MISS 495 { "L3_WRITES_DATA_WRITE_MISS", {0x608de}, 0xfff0, 1, {0xffff0017}, "L3 Writes -- L3 Store Misses (excludes L2 write backs, includes L3 read for ownership requests that satisfy stores)"}, #define PME_MONT_L3_WRITES_L2_WB_ALL 496 { "L3_WRITES_L2_WB_ALL", {0xb08de}, 0xfff0, 1, {0xffff0017}, "L3 Writes -- L2 Write Back References"}, #define PME_MONT_L3_WRITES_L2_WB_HIT 497 { "L3_WRITES_L2_WB_HIT", {0x908de}, 0xfff0, 1, {0xffff0017}, "L3 Writes -- L2 Write Back Hits"}, #define PME_MONT_L3_WRITES_L2_WB_MISS 498 { "L3_WRITES_L2_WB_MISS", {0xa08de}, 0xfff0, 1, {0xffff0017}, "L3 Writes -- L2 Write Back Misses"}, #define PME_MONT_LOADS_RETIRED 499 { "LOADS_RETIRED", {0xcd}, 0xfff0, 4, {0x5310007}, "Retired Loads"}, #define PME_MONT_LOADS_RETIRED_INTG 500 { "LOADS_RETIRED_INTG", {0xd8}, 0xfff0, 2, {0x5610007}, "Integer loads retired"}, #define PME_MONT_MEM_READ_CURRENT_ANY 501 { "MEM_READ_CURRENT_ANY", {0x31089}, 0xfff0, 1, {0xffff0000}, "Current Mem Read Transactions On Bus -- CPU or non-CPU (all transactions)."}, #define PME_MONT_MEM_READ_CURRENT_IO 502 { "MEM_READ_CURRENT_IO", {0x11089}, 0xfff0, 1, {0xffff0000}, "Current Mem Read Transactions On Bus -- non-CPU priority agents"}, #define PME_MONT_MISALIGNED_LOADS_RETIRED 503 { "MISALIGNED_LOADS_RETIRED", {0xce}, 0xfff0, 4, {0x5310007}, "Retired Misaligned Load Instructions"}, #define PME_MONT_MISALIGNED_STORES_RETIRED 504 { "MISALIGNED_STORES_RETIRED", {0xd2}, 0xfff0, 2, {0x5410007}, "Retired Misaligned Store Instructions"}, #define PME_MONT_NOPS_RETIRED 505 { "NOPS_RETIRED", {0x50}, 0xfff0, 6, {0xffff0003}, "Retired NOP Instructions"}, #define PME_MONT_PREDICATE_SQUASHED_RETIRED 506 { "PREDICATE_SQUASHED_RETIRED", {0x51}, 0xfff0, 6, {0xffff0003}, "Instructions Squashed Due to Predicate Off"}, #define PME_MONT_RSE_CURRENT_REGS_2_TO_0 507 { "RSE_CURRENT_REGS_2_TO_0", {0x2b}, 0xfff0, 7, {0xffff0000}, "Current RSE Registers (Bits 2:0)"}, #define PME_MONT_RSE_CURRENT_REGS_5_TO_3 508 { "RSE_CURRENT_REGS_5_TO_3", {0x2a}, 0xfff0, 7, {0xffff0000}, "Current RSE Registers (Bits 5:3)"}, #define PME_MONT_RSE_CURRENT_REGS_6 509 { "RSE_CURRENT_REGS_6", {0x26}, 0xfff0, 1, {0xffff0000}, "Current RSE Registers (Bit 6)"}, #define PME_MONT_RSE_DIRTY_REGS_2_TO_0 510 { "RSE_DIRTY_REGS_2_TO_0", {0x29}, 0xfff0, 7, {0xffff0000}, "Dirty RSE Registers (Bits 2:0)"}, #define PME_MONT_RSE_DIRTY_REGS_5_TO_3 511 { "RSE_DIRTY_REGS_5_TO_3", {0x28}, 0xfff0, 7, {0xffff0000}, "Dirty RSE Registers (Bits 5:3)"}, #define PME_MONT_RSE_DIRTY_REGS_6 512 { "RSE_DIRTY_REGS_6", {0x24}, 0xfff0, 1, {0xffff0000}, "Dirty RSE Registers (Bit 6)"}, #define PME_MONT_RSE_EVENT_RETIRED 513 { "RSE_EVENT_RETIRED", {0x32}, 0xfff0, 1, {0xffff0000}, "Retired RSE operations"}, #define PME_MONT_RSE_REFERENCES_RETIRED_ALL 514 { "RSE_REFERENCES_RETIRED_ALL", {0x30020}, 0xfff0, 2, {0xffff0007}, "RSE Accesses -- Both RSE loads and stores will be counted."}, #define PME_MONT_RSE_REFERENCES_RETIRED_LOAD 515 { "RSE_REFERENCES_RETIRED_LOAD", {0x10020}, 0xfff0, 2, {0xffff0007}, "RSE Accesses -- Only RSE loads will be counted."}, #define PME_MONT_RSE_REFERENCES_RETIRED_STORE 516 { "RSE_REFERENCES_RETIRED_STORE", {0x20020}, 0xfff0, 2, {0xffff0007}, "RSE Accesses -- Only RSE stores will be counted."}, #define PME_MONT_SERIALIZATION_EVENTS 517 { "SERIALIZATION_EVENTS", {0x53}, 0xfff0, 1, {0xffff0000}, "Number of srlz.i Instructions"}, #define PME_MONT_SI_CCQ_COLLISIONS_EITHER 518 { "SI_CCQ_COLLISIONS_EITHER", {0x10a8}, 0xfff0, 2, {0xffff0000}, "Clean Castout Queue Collisions -- transactions initiated by either cpu core"}, #define PME_MONT_SI_CCQ_COLLISIONS_SELF 519 { "SI_CCQ_COLLISIONS_SELF", {0x110a8}, 0xfff0, 2, {0xffff0000}, "Clean Castout Queue Collisions -- transactions initiated by 'this' cpu core"}, #define PME_MONT_SI_CCQ_INSERTS_EITHER 520 { "SI_CCQ_INSERTS_EITHER", {0x18a5}, 0xfff0, 2, {0xffff0000}, "Clean Castout Queue Insertions -- transactions initiated by either cpu core"}, #define PME_MONT_SI_CCQ_INSERTS_SELF 521 { "SI_CCQ_INSERTS_SELF", {0x118a5}, 0xfff0, 2, {0xffff0000}, "Clean Castout Queue Insertions -- transactions initiated by 'this' cpu core"}, #define PME_MONT_SI_CCQ_LIVE_REQ_HI_EITHER 522 { "SI_CCQ_LIVE_REQ_HI_EITHER", {0x10a7}, 0xfff0, 1, {0xffff0000}, "Clean Castout Queue Requests (upper bit) -- transactions initiated by either cpu core"}, #define PME_MONT_SI_CCQ_LIVE_REQ_HI_SELF 523 { "SI_CCQ_LIVE_REQ_HI_SELF", {0x110a7}, 0xfff0, 1, {0xffff0000}, "Clean Castout Queue Requests (upper bit) -- transactions initiated by 'this' cpu core"}, #define PME_MONT_SI_CCQ_LIVE_REQ_LO_EITHER 524 { "SI_CCQ_LIVE_REQ_LO_EITHER", {0x10a6}, 0xfff0, 7, {0xffff0000}, "Clean Castout Queue Requests (lower three bits) -- transactions initiated by either cpu core"}, #define PME_MONT_SI_CCQ_LIVE_REQ_LO_SELF 525 { "SI_CCQ_LIVE_REQ_LO_SELF", {0x110a6}, 0xfff0, 7, {0xffff0000}, "Clean Castout Queue Requests (lower three bits) -- transactions initiated by 'this' cpu core"}, #define PME_MONT_SI_CYCLES 526 { "SI_CYCLES", {0x108e}, 0xfff0, 1, {0xffff0000}, "SI Cycles"}, #define PME_MONT_SI_IOQ_COLLISIONS 527 { "SI_IOQ_COLLISIONS", {0x10aa}, 0xfff0, 2, {0xffff0000}, "In Order Queue Collisions"}, #define PME_MONT_SI_IOQ_LIVE_REQ_HI 528 { "SI_IOQ_LIVE_REQ_HI", {0x1098}, 0xfff0, 2, {0xffff0000}, "Inorder Bus Queue Requests (upper bit)"}, #define PME_MONT_SI_IOQ_LIVE_REQ_LO 529 { "SI_IOQ_LIVE_REQ_LO", {0x1097}, 0xfff0, 3, {0xffff0000}, "Inorder Bus Queue Requests (lower three bits)"}, #define PME_MONT_SI_RQ_INSERTS_EITHER 530 { "SI_RQ_INSERTS_EITHER", {0x189e}, 0xfff0, 2, {0xffff0000}, "Request Queue Insertions -- transactions initiated by either cpu core"}, #define PME_MONT_SI_RQ_INSERTS_SELF 531 { "SI_RQ_INSERTS_SELF", {0x1189e}, 0xfff0, 2, {0xffff0000}, "Request Queue Insertions -- transactions initiated by 'this' cpu core"}, #define PME_MONT_SI_RQ_LIVE_REQ_HI_EITHER 532 { "SI_RQ_LIVE_REQ_HI_EITHER", {0x10a0}, 0xfff0, 1, {0xffff0000}, "Request Queue Requests (upper bit) -- transactions initiated by either cpu core"}, #define PME_MONT_SI_RQ_LIVE_REQ_HI_SELF 533 { "SI_RQ_LIVE_REQ_HI_SELF", {0x110a0}, 0xfff0, 1, {0xffff0000}, "Request Queue Requests (upper bit) -- transactions initiated by 'this' cpu core"}, #define PME_MONT_SI_RQ_LIVE_REQ_LO_EITHER 534 { "SI_RQ_LIVE_REQ_LO_EITHER", {0x109f}, 0xfff0, 7, {0xffff0000}, "Request Queue Requests (lower three bits) -- transactions initiated by either cpu core"}, #define PME_MONT_SI_RQ_LIVE_REQ_LO_SELF 535 { "SI_RQ_LIVE_REQ_LO_SELF", {0x1109f}, 0xfff0, 7, {0xffff0000}, "Request Queue Requests (lower three bits) -- transactions initiated by 'this' cpu core"}, #define PME_MONT_SI_SCB_INSERTS_ALL_EITHER 536 { "SI_SCB_INSERTS_ALL_EITHER", {0xc10ab}, 0xfff0, 4, {0xffff0000}, "Snoop Coalescing Buffer Insertions -- count all snoop signoffs (plus backsnoop inserts) from either cpu core"}, #define PME_MONT_SI_SCB_INSERTS_ALL_SELF 537 { "SI_SCB_INSERTS_ALL_SELF", {0xd10ab}, 0xfff0, 4, {0xffff0000}, "Snoop Coalescing Buffer Insertions -- count all snoop signoffs (plus backsnoop inserts) from 'this' cpu core"}, #define PME_MONT_SI_SCB_INSERTS_HIT_EITHER 538 { "SI_SCB_INSERTS_HIT_EITHER", {0x410ab}, 0xfff0, 4, {0xffff0000}, "Snoop Coalescing Buffer Insertions -- count HIT snoop signoffs from either cpu core"}, #define PME_MONT_SI_SCB_INSERTS_HIT_SELF 539 { "SI_SCB_INSERTS_HIT_SELF", {0x510ab}, 0xfff0, 4, {0xffff0000}, "Snoop Coalescing Buffer Insertions -- count HIT snoop signoffs from 'this' cpu core"}, #define PME_MONT_SI_SCB_INSERTS_HITM_EITHER 540 { "SI_SCB_INSERTS_HITM_EITHER", {0x810ab}, 0xfff0, 4, {0xffff0000}, "Snoop Coalescing Buffer Insertions -- count HITM snoop signoffs from either cpu core"}, #define PME_MONT_SI_SCB_INSERTS_HITM_SELF 541 { "SI_SCB_INSERTS_HITM_SELF", {0x910ab}, 0xfff0, 4, {0xffff0000}, "Snoop Coalescing Buffer Insertions -- count HITM snoop signoffs from 'this' cpu core"}, #define PME_MONT_SI_SCB_INSERTS_MISS_EITHER 542 { "SI_SCB_INSERTS_MISS_EITHER", {0x10ab}, 0xfff0, 4, {0xffff0000}, "Snoop Coalescing Buffer Insertions -- count MISS snoop signoffs (plus backsnoop inserts) from either cpu core"}, #define PME_MONT_SI_SCB_INSERTS_MISS_SELF 543 { "SI_SCB_INSERTS_MISS_SELF", {0x110ab}, 0xfff0, 4, {0xffff0000}, "Snoop Coalescing Buffer Insertions -- count MISS snoop signoffs (plus backsnoop inserts) from 'this' cpu core"}, #define PME_MONT_SI_SCB_LIVE_REQ_HI_EITHER 544 { "SI_SCB_LIVE_REQ_HI_EITHER", {0x10ad}, 0xfff0, 1, {0xffff0000}, "Snoop Coalescing Buffer Requests (upper bit) -- transactions initiated by either cpu core"}, #define PME_MONT_SI_SCB_LIVE_REQ_HI_SELF 545 { "SI_SCB_LIVE_REQ_HI_SELF", {0x110ad}, 0xfff0, 1, {0xffff0000}, "Snoop Coalescing Buffer Requests (upper bit) -- transactions initiated by 'this' cpu core"}, #define PME_MONT_SI_SCB_LIVE_REQ_LO_EITHER 546 { "SI_SCB_LIVE_REQ_LO_EITHER", {0x10ac}, 0xfff0, 7, {0xffff0000}, "Snoop Coalescing Buffer Requests (lower three bits) -- transactions initiated by either cpu core"}, #define PME_MONT_SI_SCB_LIVE_REQ_LO_SELF 547 { "SI_SCB_LIVE_REQ_LO_SELF", {0x110ac}, 0xfff0, 7, {0xffff0000}, "Snoop Coalescing Buffer Requests (lower three bits) -- transactions initiated by 'this' cpu core"}, #define PME_MONT_SI_SCB_SIGNOFFS_ALL 548 { "SI_SCB_SIGNOFFS_ALL", {0xc10ae}, 0xfff0, 1, {0xffff0000}, "Snoop Coalescing Buffer Coherency Signoffs -- count all snoop signoffs"}, #define PME_MONT_SI_SCB_SIGNOFFS_HIT 549 { "SI_SCB_SIGNOFFS_HIT", {0x410ae}, 0xfff0, 1, {0xffff0000}, "Snoop Coalescing Buffer Coherency Signoffs -- count HIT snoop signoffs"}, #define PME_MONT_SI_SCB_SIGNOFFS_HITM 550 { "SI_SCB_SIGNOFFS_HITM", {0x810ae}, 0xfff0, 1, {0xffff0000}, "Snoop Coalescing Buffer Coherency Signoffs -- count HITM snoop signoffs"}, #define PME_MONT_SI_SCB_SIGNOFFS_MISS 551 { "SI_SCB_SIGNOFFS_MISS", {0x10ae}, 0xfff0, 1, {0xffff0000}, "Snoop Coalescing Buffer Coherency Signoffs -- count MISS snoop signoffs"}, #define PME_MONT_SI_WAQ_COLLISIONS_EITHER 552 { "SI_WAQ_COLLISIONS_EITHER", {0x10a4}, 0xfff0, 1, {0xffff0000}, "Write Address Queue Collisions -- transactions initiated by either cpu core"}, #define PME_MONT_SI_WAQ_COLLISIONS_SELF 553 { "SI_WAQ_COLLISIONS_SELF", {0x110a4}, 0xfff0, 1, {0xffff0000}, "Write Address Queue Collisions -- transactions initiated by 'this' cpu core"}, #define PME_MONT_SI_WDQ_ECC_ERRORS_ALL_EITHER 554 { "SI_WDQ_ECC_ERRORS_ALL_EITHER", {0x810af}, 0xfff0, 2, {0xffff0000}, "Write Data Queue ECC Errors -- count all ECC errors from either cpu core"}, #define PME_MONT_SI_WDQ_ECC_ERRORS_ALL_SELF 555 { "SI_WDQ_ECC_ERRORS_ALL_SELF", {0x910af}, 0xfff0, 2, {0xffff0000}, "Write Data Queue ECC Errors -- count all ECC errors from 'this' cpu core"}, #define PME_MONT_SI_WDQ_ECC_ERRORS_DBL_EITHER 556 { "SI_WDQ_ECC_ERRORS_DBL_EITHER", {0x410af}, 0xfff0, 2, {0xffff0000}, "Write Data Queue ECC Errors -- count double-bit ECC errors from either cpu core"}, #define PME_MONT_SI_WDQ_ECC_ERRORS_DBL_SELF 557 { "SI_WDQ_ECC_ERRORS_DBL_SELF", {0x510af}, 0xfff0, 2, {0xffff0000}, "Write Data Queue ECC Errors -- count double-bit ECC errors from 'this' cpu core"}, #define PME_MONT_SI_WDQ_ECC_ERRORS_SGL_EITHER 558 { "SI_WDQ_ECC_ERRORS_SGL_EITHER", {0x10af}, 0xfff0, 2, {0xffff0000}, "Write Data Queue ECC Errors -- count single-bit ECC errors from either cpu core"}, #define PME_MONT_SI_WDQ_ECC_ERRORS_SGL_SELF 559 { "SI_WDQ_ECC_ERRORS_SGL_SELF", {0x110af}, 0xfff0, 2, {0xffff0000}, "Write Data Queue ECC Errors -- count single-bit ECC errors from 'this' cpu core"}, #define PME_MONT_SI_WRITEQ_INSERTS_ALL_EITHER 560 { "SI_WRITEQ_INSERTS_ALL_EITHER", {0x18a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_ALL_SELF 561 { "SI_WRITEQ_INSERTS_ALL_SELF", {0x118a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_EWB_EITHER 562 { "SI_WRITEQ_INSERTS_EWB_EITHER", {0x418a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_EWB_SELF 563 { "SI_WRITEQ_INSERTS_EWB_SELF", {0x518a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_IWB_EITHER 564 { "SI_WRITEQ_INSERTS_IWB_EITHER", {0x218a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_IWB_SELF 565 { "SI_WRITEQ_INSERTS_IWB_SELF", {0x318a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_NEWB_EITHER 566 { "SI_WRITEQ_INSERTS_NEWB_EITHER", {0xc18a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_NEWB_SELF 567 { "SI_WRITEQ_INSERTS_NEWB_SELF", {0xd18a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_WC16_EITHER 568 { "SI_WRITEQ_INSERTS_WC16_EITHER", {0x818a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_WC16_SELF 569 { "SI_WRITEQ_INSERTS_WC16_SELF", {0x918a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_WC1_8A_EITHER 570 { "SI_WRITEQ_INSERTS_WC1_8A_EITHER", {0x618a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_WC1_8A_SELF 571 { "SI_WRITEQ_INSERTS_WC1_8A_SELF", {0x718a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_WC1_8B_EITHER 572 { "SI_WRITEQ_INSERTS_WC1_8B_EITHER", {0xe18a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_WC1_8B_SELF 573 { "SI_WRITEQ_INSERTS_WC1_8B_SELF", {0xf18a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_WC32_EITHER 574 { "SI_WRITEQ_INSERTS_WC32_EITHER", {0xa18a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_INSERTS_WC32_SELF 575 { "SI_WRITEQ_INSERTS_WC32_SELF", {0xb18a1}, 0xfff0, 2, {0xffff0000}, "Write Queue Insertions -- "}, #define PME_MONT_SI_WRITEQ_LIVE_REQ_HI_EITHER 576 { "SI_WRITEQ_LIVE_REQ_HI_EITHER", {0x10a3}, 0xfff0, 1, {0xffff0000}, "Write Queue Requests (upper bit) -- transactions initiated by either cpu core"}, #define PME_MONT_SI_WRITEQ_LIVE_REQ_HI_SELF 577 { "SI_WRITEQ_LIVE_REQ_HI_SELF", {0x110a3}, 0xfff0, 1, {0xffff0000}, "Write Queue Requests (upper bit) -- transactions initiated by 'this' cpu core"}, #define PME_MONT_SI_WRITEQ_LIVE_REQ_LO_EITHER 578 { "SI_WRITEQ_LIVE_REQ_LO_EITHER", {0x10a2}, 0xfff0, 7, {0xffff0000}, "Write Queue Requests (lower three bits) -- transactions initiated by either cpu core"}, #define PME_MONT_SI_WRITEQ_LIVE_REQ_LO_SELF 579 { "SI_WRITEQ_LIVE_REQ_LO_SELF", {0x110a2}, 0xfff0, 7, {0xffff0000}, "Write Queue Requests (lower three bits) -- transactions initiated by 'this' cpu core"}, #define PME_MONT_SPEC_LOADS_NATTED_ALL 580 { "SPEC_LOADS_NATTED_ALL", {0xd9}, 0xfff0, 2, {0xffff0005}, "Number of speculative inter loads that are NaTd -- Count all NaT'd loads"}, #define PME_MONT_SPEC_LOADS_NATTED_DEF_PSR_ED 581 { "SPEC_LOADS_NATTED_DEF_PSR_ED", {0x500d9}, 0xfff0, 2, {0xffff0005}, "Number of speculative inter loads that are NaTd -- Only loads NaT'd due to effect of PSR.ed"}, #define PME_MONT_SPEC_LOADS_NATTED_DEF_TLB_FAULT 582 { "SPEC_LOADS_NATTED_DEF_TLB_FAULT", {0x300d9}, 0xfff0, 2, {0xffff0005}, "Number of speculative inter loads that are NaTd -- Only loads NaT'd due to deferred TLB faults"}, #define PME_MONT_SPEC_LOADS_NATTED_DEF_TLB_MISS 583 { "SPEC_LOADS_NATTED_DEF_TLB_MISS", {0x200d9}, 0xfff0, 2, {0xffff0005}, "Number of speculative inter loads that are NaTd -- Only loads NaT'd due to deferred TLB misses"}, #define PME_MONT_SPEC_LOADS_NATTED_NAT_CNSM 584 { "SPEC_LOADS_NATTED_NAT_CNSM", {0x400d9}, 0xfff0, 2, {0xffff0005}, "Number of speculative inter loads that are NaTd -- Only loads NaT'd due to NaT consumption"}, #define PME_MONT_SPEC_LOADS_NATTED_VHPT_MISS 585 { "SPEC_LOADS_NATTED_VHPT_MISS", {0x100d9}, 0xfff0, 2, {0xffff0005}, "Number of speculative inter loads that are NaTd -- Only loads NaT'd due to VHPT miss"}, #define PME_MONT_STORES_RETIRED 586 { "STORES_RETIRED", {0xd1}, 0xfff0, 2, {0x5410007}, "Retired Stores"}, #define PME_MONT_SYLL_NOT_DISPERSED_ALL 587 { "SYLL_NOT_DISPERSED_ALL", {0xf004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Counts all syllables not dispersed. NOTE: Any combination of b0000-b1111 is valid."}, #define PME_MONT_SYLL_NOT_DISPERSED_EXPL 588 { "SYLL_NOT_DISPERSED_EXPL", {0x1004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Count syllables not dispersed due to explicit stop bits. These consist of programmer specified architected S-bit and templates 1 and 5. Dispersal takes a 6-syllable (3-syllable) hit for every template 1/5 in bundle 0(1). Dispersal takes a 3-syllable (0 syllable) hit for every S-bit in bundle 0(1)"}, #define PME_MONT_SYLL_NOT_DISPERSED_EXPL_OR_FE 589 { "SYLL_NOT_DISPERSED_EXPL_OR_FE", {0x5004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Count syllables not dispersed due to explicit stop bits or front-end not providing valid bundles or providing valid illegal templates."}, #define PME_MONT_SYLL_NOT_DISPERSED_EXPL_OR_FE_OR_MLX 590 { "SYLL_NOT_DISPERSED_EXPL_OR_FE_OR_MLX", {0xd004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Count syllables not dispersed due to explicit stop bits or due to front-end not providing valid bundles or providing valid illegal templates or due to MLX bundle and resteers to non-0 syllable."}, #define PME_MONT_SYLL_NOT_DISPERSED_EXPL_OR_IMPL 591 { "SYLL_NOT_DISPERSED_EXPL_OR_IMPL", {0x3004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Count syllables not dispersed due to explicit/implicit stop bits."}, #define PME_MONT_SYLL_NOT_DISPERSED_EXPL_OR_IMPL_OR_FE 592 { "SYLL_NOT_DISPERSED_EXPL_OR_IMPL_OR_FE", {0x7004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Count syllables not dispersed due to explicit or implicit stop bits or due to front-end not providing valid bundles or providing valid illegal template."}, #define PME_MONT_SYLL_NOT_DISPERSED_EXPL_OR_IMPL_OR_MLX 593 { "SYLL_NOT_DISPERSED_EXPL_OR_IMPL_OR_MLX", {0xb004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Count syllables not dispersed due to explicit or implicit stop bits or due to MLX bundle and resteers to non-0 syllable."}, #define PME_MONT_SYLL_NOT_DISPERSED_EXPL_OR_MLX 594 { "SYLL_NOT_DISPERSED_EXPL_OR_MLX", {0x9004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Count syllables not dispersed due to explicit stop bits or to MLX bundle and resteers to non-0 syllable."}, #define PME_MONT_SYLL_NOT_DISPERSED_FE 595 { "SYLL_NOT_DISPERSED_FE", {0x4004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Count syllables not dispersed due to front-end not providing valid bundles or providing valid illegal templates. Dispersal takes a 3-syllable hit for every invalid bundle or valid illegal template from front-end. Bundle 1 with front-end fault, is counted here (3-syllable hit).."}, #define PME_MONT_SYLL_NOT_DISPERSED_FE_OR_MLX 596 { "SYLL_NOT_DISPERSED_FE_OR_MLX", {0xc004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Count syllables not dispersed due to MLI bundle and resteers to non-0 syllable or due to front-end not providing valid bundles or providing valid illegal templates."}, #define PME_MONT_SYLL_NOT_DISPERSED_IMPL 597 { "SYLL_NOT_DISPERSED_IMPL", {0x2004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Count syllables not dispersed due to implicit stop bits. These consist of all of the non-architected stop bits (asymmetry, oversubscription, implicit). Dispersal takes a 6-syllable(3-syllable) hit for every implicit stop bits in bundle 0(1)."}, #define PME_MONT_SYLL_NOT_DISPERSED_IMPL_OR_FE 598 { "SYLL_NOT_DISPERSED_IMPL_OR_FE", {0x6004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Count syllables not dispersed due to implicit stop bits or to front-end not providing valid bundles or providing valid illegal templates."}, #define PME_MONT_SYLL_NOT_DISPERSED_IMPL_OR_FE_OR_MLX 599 { "SYLL_NOT_DISPERSED_IMPL_OR_FE_OR_MLX", {0xe004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Count syllables not dispersed due to implicit stop bits or due to front-end not providing valid bundles or providing valid illegal templates or due to MLX bundle and resteers to non-0 syllable."}, #define PME_MONT_SYLL_NOT_DISPERSED_IMPL_OR_MLX 600 { "SYLL_NOT_DISPERSED_IMPL_OR_MLX", {0xa004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Count syllables not dispersed due to implicit stop bits or to MLX bundle and resteers to non-0 syllable."}, #define PME_MONT_SYLL_NOT_DISPERSED_MLX 601 { "SYLL_NOT_DISPERSED_MLX", {0x8004e}, 0xfff0, 5, {0xffff0001}, "Syllables Not Dispersed -- Count syllables not dispersed due to MLX bundle and resteers to non-0 syllable. Dispersal takes a 1 syllable hit for each MLX bundle . Dispersal could take 0-2 syllable hit depending on which syllable we resteer to. Bundle 1 with front-end fault which is split, is counted here (0-2 syllable hit)."}, #define PME_MONT_SYLL_OVERCOUNT_ALL 602 { "SYLL_OVERCOUNT_ALL", {0x3004f}, 0xfff0, 2, {0xffff0001}, "Syllables Overcounted -- syllables overcounted in implicit & explicit bucket"}, #define PME_MONT_SYLL_OVERCOUNT_EXPL 603 { "SYLL_OVERCOUNT_EXPL", {0x1004f}, 0xfff0, 2, {0xffff0001}, "Syllables Overcounted -- Only syllables overcounted in the explicit bucket"}, #define PME_MONT_SYLL_OVERCOUNT_IMPL 604 { "SYLL_OVERCOUNT_IMPL", {0x2004f}, 0xfff0, 2, {0xffff0001}, "Syllables Overcounted -- Only syllables overcounted in the implicit bucket"}, #define PME_MONT_THREAD_SWITCH_CYCLE_ALL_GATED 605 { "THREAD_SWITCH_CYCLE_ALL_GATED", {0x6000e}, 0xfff0, 1, {0xffff0000}, "Thread switch overhead cycles. -- Cycles TSs are gated due to any reason"}, #define PME_MONT_THREAD_SWITCH_CYCLE_ANYSTALL 606 { "THREAD_SWITCH_CYCLE_ANYSTALL", {0x3000e}, 0xfff0, 1, {0xffff0000}, "Thread switch overhead cycles. -- Cycles TSs are stalled due to any reason"}, #define PME_MONT_THREAD_SWITCH_CYCLE_CRAB 607 { "THREAD_SWITCH_CYCLE_CRAB", {0x1000e}, 0xfff0, 1, {0xffff0000}, "Thread switch overhead cycles. -- Cycles TSs are stalled due to CRAB operation"}, #define PME_MONT_THREAD_SWITCH_CYCLE_L2D 608 { "THREAD_SWITCH_CYCLE_L2D", {0x2000e}, 0xfff0, 1, {0xffff0000}, "Thread switch overhead cycles. -- Cycles TSs are stalled due to L2D return operation"}, #define PME_MONT_THREAD_SWITCH_CYCLE_PCR 609 { "THREAD_SWITCH_CYCLE_PCR", {0x4000e}, 0xfff0, 1, {0xffff0000}, "Thread switch overhead cycles. -- Cycles we run with PCR.sd set"}, #define PME_MONT_THREAD_SWITCH_CYCLE_TOTAL 610 { "THREAD_SWITCH_CYCLE_TOTAL", {0x7000e}, 0xfff0, 1, {0xffff0000}, "Thread switch overhead cycles. -- Total time from TS opportunity is seized to TS happens."}, #define PME_MONT_THREAD_SWITCH_EVENTS_ALL 611 { "THREAD_SWITCH_EVENTS_ALL", {0x7000c}, 0xfff0, 1, {0xffff0000}, "Thread switch events. -- All taken TSs"}, #define PME_MONT_THREAD_SWITCH_EVENTS_DBG 612 { "THREAD_SWITCH_EVENTS_DBG", {0x5000c}, 0xfff0, 1, {0xffff0000}, "Thread switch events. -- TSs due to debug operations"}, #define PME_MONT_THREAD_SWITCH_EVENTS_HINT 613 { "THREAD_SWITCH_EVENTS_HINT", {0x3000c}, 0xfff0, 1, {0xffff0000}, "Thread switch events. -- TSs due to hint instruction"}, #define PME_MONT_THREAD_SWITCH_EVENTS_L3MISS 614 { "THREAD_SWITCH_EVENTS_L3MISS", {0x1000c}, 0xfff0, 1, {0xffff0000}, "Thread switch events. -- TSs due to L3 miss"}, #define PME_MONT_THREAD_SWITCH_EVENTS_LP 615 { "THREAD_SWITCH_EVENTS_LP", {0x4000c}, 0xfff0, 1, {0xffff0000}, "Thread switch events. -- TSs due to low power operation"}, #define PME_MONT_THREAD_SWITCH_EVENTS_MISSED 616 { "THREAD_SWITCH_EVENTS_MISSED", {0xc}, 0xfff0, 1, {0xffff0000}, "Thread switch events. -- TS opportunities missed"}, #define PME_MONT_THREAD_SWITCH_EVENTS_TIMER 617 { "THREAD_SWITCH_EVENTS_TIMER", {0x2000c}, 0xfff0, 1, {0xffff0000}, "Thread switch events. -- TSs due to time out"}, #define PME_MONT_THREAD_SWITCH_GATED_ALL 618 { "THREAD_SWITCH_GATED_ALL", {0x7000d}, 0xfff0, 1, {0xffff0000}, "Thread switches gated -- TSs gated for any reason"}, #define PME_MONT_THREAD_SWITCH_GATED_FWDPRO 619 { "THREAD_SWITCH_GATED_FWDPRO", {0x5000d}, 0xfff0, 1, {0xffff0000}, "Thread switches gated -- Gated due to forward progress reasons"}, #define PME_MONT_THREAD_SWITCH_GATED_LP 620 { "THREAD_SWITCH_GATED_LP", {0x1000d}, 0xfff0, 1, {0xffff0000}, "Thread switches gated -- TSs gated due to LP"}, #define PME_MONT_THREAD_SWITCH_GATED_PIPE 621 { "THREAD_SWITCH_GATED_PIPE", {0x4000d}, 0xfff0, 1, {0xffff0000}, "Thread switches gated -- Gated due to pipeline operations"}, #define PME_MONT_THREAD_SWITCH_STALL_GTE_1024 622 { "THREAD_SWITCH_STALL_GTE_1024", {0x8000f}, 0xfff0, 1, {0xffff0000}, "Thread switch stall -- Thread switch stall >= 1024 cycles"}, #define PME_MONT_THREAD_SWITCH_STALL_GTE_128 623 { "THREAD_SWITCH_STALL_GTE_128", {0x5000f}, 0xfff0, 1, {0xffff0000}, "Thread switch stall -- Thread switch stall >= 128 cycles"}, #define PME_MONT_THREAD_SWITCH_STALL_GTE_16 624 { "THREAD_SWITCH_STALL_GTE_16", {0x2000f}, 0xfff0, 1, {0xffff0000}, "Thread switch stall -- Thread switch stall >= 16 cycles"}, #define PME_MONT_THREAD_SWITCH_STALL_GTE_2048 625 { "THREAD_SWITCH_STALL_GTE_2048", {0x9000f}, 0xfff0, 1, {0xffff0000}, "Thread switch stall -- Thread switch stall >= 2048 cycles"}, #define PME_MONT_THREAD_SWITCH_STALL_GTE_256 626 { "THREAD_SWITCH_STALL_GTE_256", {0x6000f}, 0xfff0, 1, {0xffff0000}, "Thread switch stall -- Thread switch stall >= 256 cycles"}, #define PME_MONT_THREAD_SWITCH_STALL_GTE_32 627 { "THREAD_SWITCH_STALL_GTE_32", {0x3000f}, 0xfff0, 1, {0xffff0000}, "Thread switch stall -- Thread switch stall >= 32 cycles"}, #define PME_MONT_THREAD_SWITCH_STALL_GTE_4 628 { "THREAD_SWITCH_STALL_GTE_4", {0xf}, 0xfff0, 1, {0xffff0000}, "Thread switch stall -- Thread switch stall >= 4 cycles"}, #define PME_MONT_THREAD_SWITCH_STALL_GTE_4096 629 { "THREAD_SWITCH_STALL_GTE_4096", {0xa000f}, 0xfff0, 1, {0xffff0000}, "Thread switch stall -- Thread switch stall >= 4096 cycles"}, #define PME_MONT_THREAD_SWITCH_STALL_GTE_512 630 { "THREAD_SWITCH_STALL_GTE_512", {0x7000f}, 0xfff0, 1, {0xffff0000}, "Thread switch stall -- Thread switch stall >= 512 cycles"}, #define PME_MONT_THREAD_SWITCH_STALL_GTE_64 631 { "THREAD_SWITCH_STALL_GTE_64", {0x4000f}, 0xfff0, 1, {0xffff0000}, "Thread switch stall -- Thread switch stall >= 64 cycles"}, #define PME_MONT_THREAD_SWITCH_STALL_GTE_8 632 { "THREAD_SWITCH_STALL_GTE_8", {0x1000f}, 0xfff0, 1, {0xffff0000}, "Thread switch stall -- Thread switch stall >= 8 cycles"}, #define PME_MONT_UC_LOADS_RETIRED 633 { "UC_LOADS_RETIRED", {0xcf}, 0xfff0, 4, {0x5310007}, "Retired Uncacheable Loads"}, #define PME_MONT_UC_STORES_RETIRED 634 { "UC_STORES_RETIRED", {0xd0}, 0xfff0, 2, {0x5410007}, "Retired Uncacheable Stores"}, #define PME_MONT_IA64_INST_RETIRED 635 { "IA64_INST_RETIRED", {0x8}, 0xfff0, 6, {0xffff0003}, "Retired IA-64 Instructions -- Retired IA-64 Instructions -- Alias to IA64_INST_RETIRED_THIS"}, #define PME_MONT_BRANCH_EVENT 636 { "BRANCH_EVENT", {0x111}, 0xfff0, 1, {0xffff0003}, "Execution Trace Buffer Event Captured. Alias to ETB_EVENT"}, }; #define PME_MONT_EVENT_COUNT (sizeof(montecito_pe)/sizeof(pme_mont_entry_t)) papi-5.5.1/src/libpfm-3.y/lib/power6_events.h0000644000307100002310000140152213013651450020654 0ustar yarkhangraduate/****************************/ /* THIS IS OPEN SOURCE CODE */ /****************************/ #ifndef __POWER6_EVENTS_H__ #define __POWER6_EVENTS_H__ /* * File: power6_events.h * CVS: * Author: Corey Ashford * cjashfor@us.ibm.com * Mods: * * * (C) Copyright IBM Corporation, 2007. All Rights Reserved. * Contributed by Corey Ashford * * Note: This code was automatically generated and should not be modified by * hand. * */ #define POWER6_PME_PM_LSU_REJECT_STQ_FULL 0 #define POWER6_PME_PM_DPU_HELD_FXU_MULTI 1 #define POWER6_PME_PM_VMX1_STALL 2 #define POWER6_PME_PM_PMC2_SAVED 3 #define POWER6_PME_PM_L2SB_IC_INV 4 #define POWER6_PME_PM_IERAT_MISS_64K 5 #define POWER6_PME_PM_THRD_PRIO_DIFF_3or4_CYC 6 #define POWER6_PME_PM_LD_REF_L1_BOTH 7 #define POWER6_PME_PM_FPU1_FCONV 8 #define POWER6_PME_PM_IBUF_FULL_COUNT 9 #define POWER6_PME_PM_MRK_LSU_DERAT_MISS 10 #define POWER6_PME_PM_MRK_ST_CMPL 11 #define POWER6_PME_PM_L2_CASTOUT_MOD 12 #define POWER6_PME_PM_FPU1_ST_FOLDED 13 #define POWER6_PME_PM_MRK_INST_TIMEO 14 #define POWER6_PME_PM_DPU_WT 15 #define POWER6_PME_PM_DPU_HELD_RESTART 16 #define POWER6_PME_PM_IERAT_MISS 17 #define POWER6_PME_PM_FPU_SINGLE 18 #define POWER6_PME_PM_MRK_PTEG_FROM_LMEM 19 #define POWER6_PME_PM_HV_COUNT 20 #define POWER6_PME_PM_L2SA_ST_HIT 21 #define POWER6_PME_PM_L2_LD_MISS_INST 22 #define POWER6_PME_PM_EXT_INT 23 #define POWER6_PME_PM_LSU1_LDF 24 #define POWER6_PME_PM_FAB_CMD_ISSUED 25 #define POWER6_PME_PM_PTEG_FROM_L21 26 #define POWER6_PME_PM_L2SA_MISS 27 #define POWER6_PME_PM_PTEG_FROM_RL2L3_MOD 28 #define POWER6_PME_PM_DPU_WT_COUNT 29 #define POWER6_PME_PM_MRK_PTEG_FROM_L25_MOD 30 #define POWER6_PME_PM_LD_HIT_L2 31 #define POWER6_PME_PM_PTEG_FROM_DL2L3_SHR 32 #define POWER6_PME_PM_MEM_DP_RQ_GLOB_LOC 33 #define POWER6_PME_PM_L3SA_MISS 34 #define POWER6_PME_PM_NO_ITAG_COUNT 35 #define POWER6_PME_PM_DSLB_MISS 36 #define POWER6_PME_PM_LSU_FLUSH_ALIGN 37 #define POWER6_PME_PM_DPU_HELD_FPU_CR 38 #define POWER6_PME_PM_PTEG_FROM_L2MISS 39 #define POWER6_PME_PM_MRK_DATA_FROM_DMEM 40 #define POWER6_PME_PM_PTEG_FROM_LMEM 41 #define POWER6_PME_PM_MRK_DERAT_REF_64K 42 #define POWER6_PME_PM_L2SA_LD_REQ_INST 43 #define POWER6_PME_PM_MRK_DERAT_MISS_16M 44 #define POWER6_PME_PM_DATA_FROM_DL2L3_MOD 45 #define POWER6_PME_PM_FPU0_FXMULT 46 #define POWER6_PME_PM_L3SB_MISS 47 #define POWER6_PME_PM_STCX_CANCEL 48 #define POWER6_PME_PM_L2SA_LD_MISS_DATA 49 #define POWER6_PME_PM_IC_INV_L2 50 #define POWER6_PME_PM_DPU_HELD 51 #define POWER6_PME_PM_PMC1_OVERFLOW 52 #define POWER6_PME_PM_THRD_PRIO_6_CYC 53 #define POWER6_PME_PM_MRK_PTEG_FROM_L3MISS 54 #define POWER6_PME_PM_MRK_LSU0_REJECT_UST 55 #define POWER6_PME_PM_MRK_INST_DISP 56 #define POWER6_PME_PM_LARX 57 #define POWER6_PME_PM_INST_CMPL 58 #define POWER6_PME_PM_FXU_IDLE 59 #define POWER6_PME_PM_MRK_DATA_FROM_DL2L3_MOD 60 #define POWER6_PME_PM_L2_LD_REQ_DATA 61 #define POWER6_PME_PM_LSU_DERAT_MISS_CYC 62 #define POWER6_PME_PM_DPU_HELD_POWER_COUNT 63 #define POWER6_PME_PM_INST_FROM_RL2L3_MOD 64 #define POWER6_PME_PM_DATA_FROM_DMEM_CYC 65 #define POWER6_PME_PM_DATA_FROM_DMEM 66 #define POWER6_PME_PM_LSU_REJECT_PARTIAL_SECTOR 67 #define POWER6_PME_PM_LSU_REJECT_DERAT_MPRED 68 #define POWER6_PME_PM_LSU1_REJECT_ULD 69 #define POWER6_PME_PM_DATA_FROM_L3_CYC 70 #define POWER6_PME_PM_FXU1_BUSY_FXU0_IDLE 71 #define POWER6_PME_PM_INST_FROM_MEM_DP 72 #define POWER6_PME_PM_LSU_FLUSH_DSI 73 #define POWER6_PME_PM_MRK_DERAT_REF_16G 74 #define POWER6_PME_PM_LSU_LDF_BOTH 75 #define POWER6_PME_PM_FPU1_1FLOP 76 #define POWER6_PME_PM_DATA_FROM_RMEM_CYC 77 #define POWER6_PME_PM_INST_PTEG_SECONDARY 78 #define POWER6_PME_PM_L1_ICACHE_MISS 79 #define POWER6_PME_PM_INST_DISP_LLA 80 #define POWER6_PME_PM_THRD_BOTH_RUN_CYC 81 #define POWER6_PME_PM_LSU_ST_CHAINED 82 #define POWER6_PME_PM_FPU1_FXDIV 83 #define POWER6_PME_PM_FREQ_UP 84 #define POWER6_PME_PM_FAB_RETRY_SYS_PUMP 85 #define POWER6_PME_PM_DATA_FROM_LMEM 86 #define POWER6_PME_PM_PMC3_OVERFLOW 87 #define POWER6_PME_PM_LSU0_REJECT_SET_MPRED 88 #define POWER6_PME_PM_LSU0_REJECT_DERAT_MPRED 89 #define POWER6_PME_PM_LSU1_REJECT_STQ_FULL 90 #define POWER6_PME_PM_MRK_BR_MPRED 91 #define POWER6_PME_PM_L2SA_ST_MISS 92 #define POWER6_PME_PM_LSU0_REJECT_EXTERN 93 #define POWER6_PME_PM_MRK_BR_TAKEN 94 #define POWER6_PME_PM_ISLB_MISS 95 #define POWER6_PME_PM_CYC 96 #define POWER6_PME_PM_FPU_FXDIV 97 #define POWER6_PME_PM_DPU_HELD_LLA_END 98 #define POWER6_PME_PM_MEM0_DP_CL_WR_LOC 99 #define POWER6_PME_PM_MRK_LSU_REJECT_ULD 100 #define POWER6_PME_PM_1PLUS_PPC_CMPL 101 #define POWER6_PME_PM_PTEG_FROM_DMEM 102 #define POWER6_PME_PM_DPU_WT_BR_MPRED_COUNT 103 #define POWER6_PME_PM_GCT_FULL_CYC 104 #define POWER6_PME_PM_INST_FROM_L25_SHR 105 #define POWER6_PME_PM_MRK_DERAT_MISS_4K 106 #define POWER6_PME_PM_DC_PREF_STREAM_ALLOC 107 #define POWER6_PME_PM_FPU1_FIN 108 #define POWER6_PME_PM_BR_MPRED_TA 109 #define POWER6_PME_PM_DPU_HELD_POWER 110 #define POWER6_PME_PM_RUN_INST_CMPL 111 #define POWER6_PME_PM_GCT_EMPTY_CYC 112 #define POWER6_PME_PM_LLA_COUNT 113 #define POWER6_PME_PM_LSU0_REJECT_NO_SCRATCH 114 #define POWER6_PME_PM_DPU_WT_IC_MISS 115 #define POWER6_PME_PM_DATA_FROM_L3MISS 116 #define POWER6_PME_PM_FPU_FPSCR 117 #define POWER6_PME_PM_VMX1_INST_ISSUED 118 #define POWER6_PME_PM_FLUSH 119 #define POWER6_PME_PM_ST_HIT_L2 120 #define POWER6_PME_PM_SYNC_CYC 121 #define POWER6_PME_PM_FAB_SYS_PUMP 122 #define POWER6_PME_PM_IC_PREF_REQ 123 #define POWER6_PME_PM_MEM0_DP_RQ_GLOB_LOC 124 #define POWER6_PME_PM_FPU_ISSUE_0 125 #define POWER6_PME_PM_THRD_PRIO_2_CYC 126 #define POWER6_PME_PM_VMX_SIMPLE_ISSUED 127 #define POWER6_PME_PM_MRK_FPU1_FIN 128 #define POWER6_PME_PM_DPU_HELD_CW 129 #define POWER6_PME_PM_L3SA_REF 130 #define POWER6_PME_PM_STCX 131 #define POWER6_PME_PM_L2SB_MISS 132 #define POWER6_PME_PM_LSU0_REJECT 133 #define POWER6_PME_PM_TB_BIT_TRANS 134 #define POWER6_PME_PM_THERMAL_MAX 135 #define POWER6_PME_PM_FPU0_STF 136 #define POWER6_PME_PM_FPU1_FMA 137 #define POWER6_PME_PM_LSU1_REJECT_LHS 138 #define POWER6_PME_PM_DPU_HELD_INT 139 #define POWER6_PME_PM_THRD_LLA_BOTH_CYC 140 #define POWER6_PME_PM_DPU_HELD_THERMAL_COUNT 141 #define POWER6_PME_PM_PMC4_REWIND 142 #define POWER6_PME_PM_DERAT_REF_16M 143 #define POWER6_PME_PM_FPU0_FCONV 144 #define POWER6_PME_PM_L2SA_LD_REQ_DATA 145 #define POWER6_PME_PM_DATA_FROM_MEM_DP 146 #define POWER6_PME_PM_MRK_VMX_FLOAT_ISSUED 147 #define POWER6_PME_PM_MRK_PTEG_FROM_L2MISS 148 #define POWER6_PME_PM_THRD_PRIO_DIFF_1or2_CYC 149 #define POWER6_PME_PM_VMX0_STALL 150 #define POWER6_PME_PM_IC_DEMAND_L2_BHT_REDIRECT 151 #define POWER6_PME_PM_LSU_DERAT_MISS 152 #define POWER6_PME_PM_FPU0_SINGLE 153 #define POWER6_PME_PM_FPU_ISSUE_STEERING 154 #define POWER6_PME_PM_THRD_PRIO_1_CYC 155 #define POWER6_PME_PM_VMX_COMPLEX_ISSUED 156 #define POWER6_PME_PM_FPU_ISSUE_ST_FOLDED 157 #define POWER6_PME_PM_DFU_FIN 158 #define POWER6_PME_PM_BR_PRED_CCACHE 159 #define POWER6_PME_PM_MRK_ST_CMPL_INT 160 #define POWER6_PME_PM_FAB_MMIO 161 #define POWER6_PME_PM_MRK_VMX_SIMPLE_ISSUED 162 #define POWER6_PME_PM_FPU_STF 163 #define POWER6_PME_PM_MEM1_DP_CL_WR_GLOB 164 #define POWER6_PME_PM_MRK_DATA_FROM_L3MISS 165 #define POWER6_PME_PM_GCT_NOSLOT_CYC 166 #define POWER6_PME_PM_L2_ST_REQ_DATA 167 #define POWER6_PME_PM_INST_TABLEWALK_COUNT 168 #define POWER6_PME_PM_PTEG_FROM_L35_SHR 169 #define POWER6_PME_PM_DPU_HELD_ISYNC 170 #define POWER6_PME_PM_MRK_DATA_FROM_L25_SHR 171 #define POWER6_PME_PM_L3SA_HIT 172 #define POWER6_PME_PM_DERAT_MISS_16G 173 #define POWER6_PME_PM_DATA_PTEG_2ND_HALF 174 #define POWER6_PME_PM_L2SA_ST_REQ 175 #define POWER6_PME_PM_INST_FROM_LMEM 176 #define POWER6_PME_PM_IC_DEMAND_L2_BR_REDIRECT 177 #define POWER6_PME_PM_PTEG_FROM_L2 178 #define POWER6_PME_PM_DATA_PTEG_1ST_HALF 179 #define POWER6_PME_PM_BR_MPRED_COUNT 180 #define POWER6_PME_PM_IERAT_MISS_4K 181 #define POWER6_PME_PM_THRD_BOTH_RUN_COUNT 182 #define POWER6_PME_PM_LSU_REJECT_ULD 183 #define POWER6_PME_PM_DATA_FROM_DL2L3_MOD_CYC 184 #define POWER6_PME_PM_MRK_PTEG_FROM_RL2L3_MOD 185 #define POWER6_PME_PM_FPU0_FLOP 186 #define POWER6_PME_PM_FPU0_FEST 187 #define POWER6_PME_PM_MRK_LSU0_REJECT_LHS 188 #define POWER6_PME_PM_VMX_RESULT_SAT_1 189 #define POWER6_PME_PM_NO_ITAG_CYC 190 #define POWER6_PME_PM_LSU1_REJECT_NO_SCRATCH 191 #define POWER6_PME_PM_0INST_FETCH 192 #define POWER6_PME_PM_DPU_WT_BR_MPRED 193 #define POWER6_PME_PM_L1_PREF 194 #define POWER6_PME_PM_VMX_FLOAT_MULTICYCLE 195 #define POWER6_PME_PM_DATA_FROM_L25_SHR_CYC 196 #define POWER6_PME_PM_DATA_FROM_L3 197 #define POWER6_PME_PM_PMC2_OVERFLOW 198 #define POWER6_PME_PM_VMX0_LD_WRBACK 199 #define POWER6_PME_PM_FPU0_DENORM 200 #define POWER6_PME_PM_INST_FETCH_CYC 201 #define POWER6_PME_PM_LSU_LDF 202 #define POWER6_PME_PM_LSU_REJECT_L2_CORR 203 #define POWER6_PME_PM_DERAT_REF_64K 204 #define POWER6_PME_PM_THRD_PRIO_3_CYC 205 #define POWER6_PME_PM_FPU_FMA 206 #define POWER6_PME_PM_INST_FROM_L35_MOD 207 #define POWER6_PME_PM_DFU_CONV 208 #define POWER6_PME_PM_INST_FROM_L25_MOD 209 #define POWER6_PME_PM_PTEG_FROM_L35_MOD 210 #define POWER6_PME_PM_MRK_VMX_ST_ISSUED 211 #define POWER6_PME_PM_VMX_FLOAT_ISSUED 212 #define POWER6_PME_PM_LSU0_REJECT_L2_CORR 213 #define POWER6_PME_PM_THRD_L2MISS 214 #define POWER6_PME_PM_FPU_FCONV 215 #define POWER6_PME_PM_FPU_FXMULT 216 #define POWER6_PME_PM_FPU1_FRSP 217 #define POWER6_PME_PM_MRK_DERAT_REF_16M 218 #define POWER6_PME_PM_L2SB_CASTOUT_SHR 219 #define POWER6_PME_PM_THRD_ONE_RUN_COUNT 220 #define POWER6_PME_PM_INST_FROM_RMEM 221 #define POWER6_PME_PM_LSU_BOTH_BUS 222 #define POWER6_PME_PM_FPU1_FSQRT_FDIV 223 #define POWER6_PME_PM_L2_LD_REQ_INST 224 #define POWER6_PME_PM_MRK_PTEG_FROM_L35_SHR 225 #define POWER6_PME_PM_BR_PRED_CR 226 #define POWER6_PME_PM_MRK_LSU0_REJECT_ULD 227 #define POWER6_PME_PM_LSU_REJECT 228 #define POWER6_PME_PM_LSU_REJECT_LHS_BOTH 229 #define POWER6_PME_PM_GXO_ADDR_CYC_BUSY 230 #define POWER6_PME_PM_LSU_SRQ_EMPTY_COUNT 231 #define POWER6_PME_PM_PTEG_FROM_L3 232 #define POWER6_PME_PM_VMX0_LD_ISSUED 233 #define POWER6_PME_PM_FXU_PIPELINED_MULT_DIV 234 #define POWER6_PME_PM_FPU1_STF 235 #define POWER6_PME_PM_DFU_ADD 236 #define POWER6_PME_PM_MEM_DP_CL_WR_GLOB 237 #define POWER6_PME_PM_MRK_LSU1_REJECT_ULD 238 #define POWER6_PME_PM_ITLB_REF 239 #define POWER6_PME_PM_LSU0_REJECT_L2MISS 240 #define POWER6_PME_PM_DATA_FROM_L35_SHR 241 #define POWER6_PME_PM_MRK_DATA_FROM_RL2L3_MOD 242 #define POWER6_PME_PM_FPU0_FPSCR 243 #define POWER6_PME_PM_DATA_FROM_L2 244 #define POWER6_PME_PM_DPU_HELD_XER 245 #define POWER6_PME_PM_FAB_NODE_PUMP 246 #define POWER6_PME_PM_VMX_RESULT_SAT_0_1 247 #define POWER6_PME_PM_LD_REF_L1 248 #define POWER6_PME_PM_TLB_REF 249 #define POWER6_PME_PM_DC_PREF_OUT_OF_STREAMS 250 #define POWER6_PME_PM_FLUSH_FPU 251 #define POWER6_PME_PM_MEM1_DP_CL_WR_LOC 252 #define POWER6_PME_PM_L2SB_LD_HIT 253 #define POWER6_PME_PM_FAB_DCLAIM 254 #define POWER6_PME_PM_MEM_DP_CL_WR_LOC 255 #define POWER6_PME_PM_BR_MPRED_CR 256 #define POWER6_PME_PM_LSU_REJECT_EXTERN 257 #define POWER6_PME_PM_DATA_FROM_RL2L3_MOD 258 #define POWER6_PME_PM_DPU_HELD_RU_WQ 259 #define POWER6_PME_PM_LD_MISS_L1 260 #define POWER6_PME_PM_DC_INV_L2 261 #define POWER6_PME_PM_MRK_PTEG_FROM_RMEM 262 #define POWER6_PME_PM_FPU_FIN 263 #define POWER6_PME_PM_FXU0_FIN 264 #define POWER6_PME_PM_DPU_HELD_FPQ 265 #define POWER6_PME_PM_GX_DMA_READ 266 #define POWER6_PME_PM_LSU1_REJECT_PARTIAL_SECTOR 267 #define POWER6_PME_PM_0INST_FETCH_COUNT 268 #define POWER6_PME_PM_PMC5_OVERFLOW 269 #define POWER6_PME_PM_L2SB_LD_REQ 270 #define POWER6_PME_PM_THRD_PRIO_DIFF_0_CYC 271 #define POWER6_PME_PM_DATA_FROM_RMEM 272 #define POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_BOTH_CYC 273 #define POWER6_PME_PM_ST_REF_L1_BOTH 274 #define POWER6_PME_PM_VMX_PERMUTE_ISSUED 275 #define POWER6_PME_PM_BR_TAKEN 276 #define POWER6_PME_PM_FAB_DMA 277 #define POWER6_PME_PM_GCT_EMPTY_COUNT 278 #define POWER6_PME_PM_FPU1_SINGLE 279 #define POWER6_PME_PM_L2SA_CASTOUT_SHR 280 #define POWER6_PME_PM_L3SB_REF 281 #define POWER6_PME_PM_FPU0_FRSP 282 #define POWER6_PME_PM_PMC4_SAVED 283 #define POWER6_PME_PM_L2SA_DC_INV 284 #define POWER6_PME_PM_GXI_ADDR_CYC_BUSY 285 #define POWER6_PME_PM_FPU0_FMA 286 #define POWER6_PME_PM_SLB_MISS 287 #define POWER6_PME_PM_MRK_ST_GPS 288 #define POWER6_PME_PM_DERAT_REF_4K 289 #define POWER6_PME_PM_L2_CASTOUT_SHR 290 #define POWER6_PME_PM_DPU_HELD_STCX_CR 291 #define POWER6_PME_PM_FPU0_ST_FOLDED 292 #define POWER6_PME_PM_MRK_DATA_FROM_L21 293 #define POWER6_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC 294 #define POWER6_PME_PM_DATA_FROM_L35_MOD 295 #define POWER6_PME_PM_DATA_FROM_DL2L3_SHR 296 #define POWER6_PME_PM_GXI_DATA_CYC_BUSY 297 #define POWER6_PME_PM_LSU_REJECT_STEAL 298 #define POWER6_PME_PM_ST_FIN 299 #define POWER6_PME_PM_DPU_HELD_CR_LOGICAL 300 #define POWER6_PME_PM_THRD_SEL_T0 301 #define POWER6_PME_PM_PTEG_RELOAD_VALID 302 #define POWER6_PME_PM_L2_PREF_ST 303 #define POWER6_PME_PM_MRK_STCX_FAIL 304 #define POWER6_PME_PM_LSU0_REJECT_LHS 305 #define POWER6_PME_PM_DFU_EXP_EQ 306 #define POWER6_PME_PM_DPU_HELD_FP_FX_MULT 307 #define POWER6_PME_PM_L2_LD_MISS_DATA 308 #define POWER6_PME_PM_DATA_FROM_L35_MOD_CYC 309 #define POWER6_PME_PM_FLUSH_FXU 310 #define POWER6_PME_PM_FPU_ISSUE_1 311 #define POWER6_PME_PM_DATA_FROM_LMEM_CYC 312 #define POWER6_PME_PM_DPU_HELD_LSU_SOPS 313 #define POWER6_PME_PM_INST_PTEG_2ND_HALF 314 #define POWER6_PME_PM_THRESH_TIMEO 315 #define POWER6_PME_PM_LSU_REJECT_UST_BOTH 316 #define POWER6_PME_PM_LSU_REJECT_FAST 317 #define POWER6_PME_PM_DPU_HELD_THRD_PRIO 318 #define POWER6_PME_PM_L2_PREF_LD 319 #define POWER6_PME_PM_FPU_FEST 320 #define POWER6_PME_PM_MRK_DATA_FROM_RMEM 321 #define POWER6_PME_PM_LD_MISS_L1_CYC 322 #define POWER6_PME_PM_DERAT_MISS_4K 323 #define POWER6_PME_PM_DPU_HELD_COMPLETION 324 #define POWER6_PME_PM_FPU_ISSUE_STALL_ST 325 #define POWER6_PME_PM_L2SB_DC_INV 326 #define POWER6_PME_PM_PTEG_FROM_L25_SHR 327 #define POWER6_PME_PM_PTEG_FROM_DL2L3_MOD 328 #define POWER6_PME_PM_FAB_CMD_RETRIED 329 #define POWER6_PME_PM_BR_PRED_LSTACK 330 #define POWER6_PME_PM_GXO_DATA_CYC_BUSY 331 #define POWER6_PME_PM_DFU_SUBNORM 332 #define POWER6_PME_PM_FPU_ISSUE_OOO 333 #define POWER6_PME_PM_LSU_REJECT_ULD_BOTH 334 #define POWER6_PME_PM_L2SB_ST_MISS 335 #define POWER6_PME_PM_DATA_FROM_L25_MOD_CYC 336 #define POWER6_PME_PM_INST_PTEG_1ST_HALF 337 #define POWER6_PME_PM_DERAT_MISS_16M 338 #define POWER6_PME_PM_GX_DMA_WRITE 339 #define POWER6_PME_PM_MRK_PTEG_FROM_DL2L3_MOD 340 #define POWER6_PME_PM_MEM1_DP_RQ_GLOB_LOC 341 #define POWER6_PME_PM_L2SB_LD_REQ_DATA 342 #define POWER6_PME_PM_L2SA_LD_MISS_INST 343 #define POWER6_PME_PM_MRK_LSU0_REJECT_L2MISS 344 #define POWER6_PME_PM_MRK_IFU_FIN 345 #define POWER6_PME_PM_INST_FROM_L3 346 #define POWER6_PME_PM_FXU1_FIN 347 #define POWER6_PME_PM_THRD_PRIO_4_CYC 348 #define POWER6_PME_PM_MRK_DATA_FROM_L35_MOD 349 #define POWER6_PME_PM_LSU_REJECT_SET_MPRED 350 #define POWER6_PME_PM_MRK_DERAT_MISS_16G 351 #define POWER6_PME_PM_FPU0_FXDIV 352 #define POWER6_PME_PM_MRK_LSU1_REJECT_UST 353 #define POWER6_PME_PM_FPU_ISSUE_DIV_SQRT_OVERLAP 354 #define POWER6_PME_PM_INST_FROM_L35_SHR 355 #define POWER6_PME_PM_MRK_LSU_REJECT_LHS 356 #define POWER6_PME_PM_LSU_LMQ_FULL_CYC 357 #define POWER6_PME_PM_SYNC_COUNT 358 #define POWER6_PME_PM_MEM0_DP_RQ_LOC_GLOB 359 #define POWER6_PME_PM_L2SA_CASTOUT_MOD 360 #define POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_BOTH_COUNT 361 #define POWER6_PME_PM_PTEG_FROM_MEM_DP 362 #define POWER6_PME_PM_LSU_REJECT_SLOW 363 #define POWER6_PME_PM_PTEG_FROM_L25_MOD 364 #define POWER6_PME_PM_THRD_PRIO_7_CYC 365 #define POWER6_PME_PM_MRK_PTEG_FROM_RL2L3_SHR 366 #define POWER6_PME_PM_ST_REQ_L2 367 #define POWER6_PME_PM_ST_REF_L1 368 #define POWER6_PME_PM_FPU_ISSUE_STALL_THRD 369 #define POWER6_PME_PM_RUN_COUNT 370 #define POWER6_PME_PM_RUN_CYC 371 #define POWER6_PME_PM_PTEG_FROM_RMEM 372 #define POWER6_PME_PM_LSU0_LDF 373 #define POWER6_PME_PM_ST_MISS_L1 374 #define POWER6_PME_PM_INST_FROM_DL2L3_SHR 375 #define POWER6_PME_PM_L2SA_IC_INV 376 #define POWER6_PME_PM_THRD_ONE_RUN_CYC 377 #define POWER6_PME_PM_L2SB_LD_REQ_INST 378 #define POWER6_PME_PM_MRK_DATA_FROM_L25_MOD 379 #define POWER6_PME_PM_DPU_HELD_XTHRD 380 #define POWER6_PME_PM_L2SB_ST_REQ 381 #define POWER6_PME_PM_INST_FROM_L21 382 #define POWER6_PME_PM_INST_FROM_L3MISS 383 #define POWER6_PME_PM_L3SB_HIT 384 #define POWER6_PME_PM_EE_OFF_EXT_INT 385 #define POWER6_PME_PM_INST_FROM_DL2L3_MOD 386 #define POWER6_PME_PM_PMC6_OVERFLOW 387 #define POWER6_PME_PM_FPU_FLOP 388 #define POWER6_PME_PM_FXU_BUSY 389 #define POWER6_PME_PM_FPU1_FLOP 390 #define POWER6_PME_PM_IC_RELOAD_SHR 391 #define POWER6_PME_PM_INST_TABLEWALK_CYC 392 #define POWER6_PME_PM_DATA_FROM_RL2L3_MOD_CYC 393 #define POWER6_PME_PM_THRD_PRIO_DIFF_5or6_CYC 394 #define POWER6_PME_PM_IBUF_FULL_CYC 395 #define POWER6_PME_PM_L2SA_LD_REQ 396 #define POWER6_PME_PM_VMX1_LD_WRBACK 397 #define POWER6_PME_PM_MRK_FPU_FIN 398 #define POWER6_PME_PM_THRD_PRIO_5_CYC 399 #define POWER6_PME_PM_DFU_BACK2BACK 400 #define POWER6_PME_PM_MRK_DATA_FROM_LMEM 401 #define POWER6_PME_PM_LSU_REJECT_LHS 402 #define POWER6_PME_PM_DPU_HELD_SPR 403 #define POWER6_PME_PM_FREQ_DOWN 404 #define POWER6_PME_PM_DFU_ENC_BCD_DPD 405 #define POWER6_PME_PM_DPU_HELD_GPR 406 #define POWER6_PME_PM_LSU0_NCST 407 #define POWER6_PME_PM_MRK_INST_ISSUED 408 #define POWER6_PME_PM_INST_FROM_RL2L3_SHR 409 #define POWER6_PME_PM_FPU_DENORM 410 #define POWER6_PME_PM_PTEG_FROM_L3MISS 411 #define POWER6_PME_PM_RUN_PURR 412 #define POWER6_PME_PM_MRK_VMX0_LD_WRBACK 413 #define POWER6_PME_PM_L2_MISS 414 #define POWER6_PME_PM_MRK_DATA_FROM_L3 415 #define POWER6_PME_PM_MRK_LSU1_REJECT_LHS 416 #define POWER6_PME_PM_L2SB_LD_MISS_INST 417 #define POWER6_PME_PM_PTEG_FROM_RL2L3_SHR 418 #define POWER6_PME_PM_MRK_DERAT_MISS_64K 419 #define POWER6_PME_PM_LWSYNC 420 #define POWER6_PME_PM_FPU1_FXMULT 421 #define POWER6_PME_PM_MEM0_DP_CL_WR_GLOB 422 #define POWER6_PME_PM_LSU0_REJECT_PARTIAL_SECTOR 423 #define POWER6_PME_PM_INST_IMC_MATCH_CMPL 424 #define POWER6_PME_PM_DPU_HELD_THERMAL 425 #define POWER6_PME_PM_FPU_FRSP 426 #define POWER6_PME_PM_MRK_INST_FIN 427 #define POWER6_PME_PM_MRK_PTEG_FROM_DL2L3_SHR 428 #define POWER6_PME_PM_MRK_DTLB_REF 429 #define POWER6_PME_PM_MRK_PTEG_FROM_L25_SHR 430 #define POWER6_PME_PM_DPU_HELD_LSU 431 #define POWER6_PME_PM_FPU_FSQRT_FDIV 432 #define POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_COUNT 433 #define POWER6_PME_PM_DATA_PTEG_SECONDARY 434 #define POWER6_PME_PM_FPU1_FEST 435 #define POWER6_PME_PM_L2SA_LD_HIT 436 #define POWER6_PME_PM_DATA_FROM_MEM_DP_CYC 437 #define POWER6_PME_PM_BR_MPRED_CCACHE 438 #define POWER6_PME_PM_DPU_HELD_COUNT 439 #define POWER6_PME_PM_LSU1_REJECT_SET_MPRED 440 #define POWER6_PME_PM_FPU_ISSUE_2 441 #define POWER6_PME_PM_LSU1_REJECT_L2_CORR 442 #define POWER6_PME_PM_MRK_PTEG_FROM_DMEM 443 #define POWER6_PME_PM_MEM1_DP_RQ_LOC_GLOB 444 #define POWER6_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC 445 #define POWER6_PME_PM_THRD_PRIO_0_CYC 446 #define POWER6_PME_PM_FXU0_BUSY_FXU1_IDLE 447 #define POWER6_PME_PM_LSU1_REJECT_DERAT_MPRED 448 #define POWER6_PME_PM_MRK_VMX1_LD_WRBACK 449 #define POWER6_PME_PM_DATA_FROM_RL2L3_SHR_CYC 450 #define POWER6_PME_PM_IERAT_MISS_16M 451 #define POWER6_PME_PM_MRK_DATA_FROM_MEM_DP 452 #define POWER6_PME_PM_LARX_L1HIT 453 #define POWER6_PME_PM_L2_ST_MISS_DATA 454 #define POWER6_PME_PM_FPU_ST_FOLDED 455 #define POWER6_PME_PM_MRK_DATA_FROM_L35_SHR 456 #define POWER6_PME_PM_DPU_HELD_MULT_GPR 457 #define POWER6_PME_PM_FPU0_1FLOP 458 #define POWER6_PME_PM_IERAT_MISS_16G 459 #define POWER6_PME_PM_IC_PREF_WRITE 460 #define POWER6_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC 461 #define POWER6_PME_PM_FPU0_FIN 462 #define POWER6_PME_PM_DATA_FROM_L2_CYC 463 #define POWER6_PME_PM_DERAT_REF_16G 464 #define POWER6_PME_PM_BR_PRED 465 #define POWER6_PME_PM_VMX1_LD_ISSUED 466 #define POWER6_PME_PM_L2SB_CASTOUT_MOD 467 #define POWER6_PME_PM_INST_FROM_DMEM 468 #define POWER6_PME_PM_DATA_FROM_L35_SHR_CYC 469 #define POWER6_PME_PM_LSU0_NCLD 470 #define POWER6_PME_PM_FAB_RETRY_NODE_PUMP 471 #define POWER6_PME_PM_VMX0_INST_ISSUED 472 #define POWER6_PME_PM_DATA_FROM_L25_MOD 473 #define POWER6_PME_PM_DPU_HELD_ITLB_ISLB 474 #define POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 475 #define POWER6_PME_PM_THRD_CONC_RUN_INST 476 #define POWER6_PME_PM_MRK_PTEG_FROM_L2 477 #define POWER6_PME_PM_PURR 478 #define POWER6_PME_PM_DERAT_MISS_64K 479 #define POWER6_PME_PM_PMC2_REWIND 480 #define POWER6_PME_PM_INST_FROM_L2 481 #define POWER6_PME_PM_INST_DISP 482 #define POWER6_PME_PM_DATA_FROM_L25_SHR 483 #define POWER6_PME_PM_L1_DCACHE_RELOAD_VALID 484 #define POWER6_PME_PM_LSU1_REJECT_UST 485 #define POWER6_PME_PM_FAB_ADDR_COLLISION 486 #define POWER6_PME_PM_MRK_FXU_FIN 487 #define POWER6_PME_PM_LSU0_REJECT_UST 488 #define POWER6_PME_PM_PMC4_OVERFLOW 489 #define POWER6_PME_PM_MRK_PTEG_FROM_L3 490 #define POWER6_PME_PM_INST_FROM_L2MISS 491 #define POWER6_PME_PM_L2SB_ST_HIT 492 #define POWER6_PME_PM_DPU_WT_IC_MISS_COUNT 493 #define POWER6_PME_PM_MRK_DATA_FROM_DL2L3_SHR 494 #define POWER6_PME_PM_MRK_PTEG_FROM_L35_MOD 495 #define POWER6_PME_PM_FPU1_FPSCR 496 #define POWER6_PME_PM_LSU_REJECT_UST 497 #define POWER6_PME_PM_LSU0_DERAT_MISS 498 #define POWER6_PME_PM_MRK_PTEG_FROM_MEM_DP 499 #define POWER6_PME_PM_MRK_DATA_FROM_L2 500 #define POWER6_PME_PM_FPU0_FSQRT_FDIV 501 #define POWER6_PME_PM_DPU_HELD_FXU_SOPS 502 #define POWER6_PME_PM_MRK_FPU0_FIN 503 #define POWER6_PME_PM_L2SB_LD_MISS_DATA 504 #define POWER6_PME_PM_LSU_SRQ_EMPTY_CYC 505 #define POWER6_PME_PM_1PLUS_PPC_DISP 506 #define POWER6_PME_PM_VMX_ST_ISSUED 507 #define POWER6_PME_PM_DATA_FROM_L2MISS 508 #define POWER6_PME_PM_LSU0_REJECT_ULD 509 #define POWER6_PME_PM_SUSPENDED 510 #define POWER6_PME_PM_DFU_ADD_SHIFTED_BOTH 511 #define POWER6_PME_PM_LSU_REJECT_NO_SCRATCH 512 #define POWER6_PME_PM_STCX_FAIL 513 #define POWER6_PME_PM_FPU1_DENORM 514 #define POWER6_PME_PM_GCT_NOSLOT_COUNT 515 #define POWER6_PME_PM_DATA_FROM_DL2L3_SHR_CYC 516 #define POWER6_PME_PM_DATA_FROM_L21 517 #define POWER6_PME_PM_FPU_1FLOP 518 #define POWER6_PME_PM_LSU1_REJECT 519 #define POWER6_PME_PM_IC_REQ 520 #define POWER6_PME_PM_MRK_DFU_FIN 521 #define POWER6_PME_PM_NOT_LLA_CYC 522 #define POWER6_PME_PM_INST_FROM_L1 523 #define POWER6_PME_PM_MRK_VMX_COMPLEX_ISSUED 524 #define POWER6_PME_PM_BRU_FIN 525 #define POWER6_PME_PM_LSU1_REJECT_EXTERN 526 #define POWER6_PME_PM_DATA_FROM_L21_CYC 527 #define POWER6_PME_PM_GXI_CYC_BUSY 528 #define POWER6_PME_PM_MRK_LD_MISS_L1 529 #define POWER6_PME_PM_L1_WRITE_CYC 530 #define POWER6_PME_PM_LLA_CYC 531 #define POWER6_PME_PM_MRK_DATA_FROM_L2MISS 532 #define POWER6_PME_PM_GCT_FULL_COUNT 533 #define POWER6_PME_PM_MEM_DP_RQ_LOC_GLOB 534 #define POWER6_PME_PM_DATA_FROM_RL2L3_SHR 535 #define POWER6_PME_PM_MRK_LSU_REJECT_UST 536 #define POWER6_PME_PM_MRK_VMX_PERMUTE_ISSUED 537 #define POWER6_PME_PM_MRK_PTEG_FROM_L21 538 #define POWER6_PME_PM_THRD_GRP_CMPL_BOTH_CYC 539 #define POWER6_PME_PM_BR_MPRED 540 #define POWER6_PME_PM_LD_REQ_L2 541 #define POWER6_PME_PM_FLUSH_ASYNC 542 #define POWER6_PME_PM_HV_CYC 543 #define POWER6_PME_PM_LSU1_DERAT_MISS 544 #define POWER6_PME_PM_DPU_HELD_SMT 545 #define POWER6_PME_PM_MRK_LSU_FIN 546 #define POWER6_PME_PM_MRK_DATA_FROM_RL2L3_SHR 547 #define POWER6_PME_PM_LSU0_REJECT_STQ_FULL 548 #define POWER6_PME_PM_MRK_DERAT_REF_4K 549 #define POWER6_PME_PM_FPU_ISSUE_STALL_FPR 550 #define POWER6_PME_PM_IFU_FIN 551 #define POWER6_PME_PM_GXO_CYC_BUSY 552 static const int power6_event_ids[][POWER6_NUM_EVENT_COUNTERS] = { [ POWER6_PME_PM_LSU_REJECT_STQ_FULL ] = { 243, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_DPU_HELD_FXU_MULTI ] = { 37, 45, 36, 44, -1, -1 }, [ POWER6_PME_PM_VMX1_STALL ] = { 328, 335, 322, 320, -1, -1 }, [ POWER6_PME_PM_PMC2_SAVED ] = { 291, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_L2SB_IC_INV ] = { 174, 183, 174, 180, -1, -1 }, [ POWER6_PME_PM_IERAT_MISS_64K ] = { -1, -1, 344, -1, -1, -1 }, [ POWER6_PME_PM_THRD_PRIO_DIFF_3or4_CYC ] = { -1, -1, 310, -1, -1, -1 }, [ POWER6_PME_PM_LD_REF_L1_BOTH ] = { 202, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_FPU1_FCONV ] = { 88, 97, 86, 94, -1, -1 }, [ POWER6_PME_PM_IBUF_FULL_COUNT ] = { 338, 345, 332, 330, -1, -1 }, [ POWER6_PME_PM_MRK_LSU_DERAT_MISS ] = { -1, -1, -1, 271, -1, -1 }, [ POWER6_PME_PM_MRK_ST_CMPL ] = { 282, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_L2_CASTOUT_MOD ] = { 185, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_FPU1_ST_FOLDED ] = { 100, 109, 98, 106, -1, -1 }, [ POWER6_PME_PM_MRK_INST_TIMEO ] = { -1, -1, -1, 263, -1, -1 }, [ POWER6_PME_PM_DPU_WT ] = { -1, -1, 54, -1, -1, -1 }, [ POWER6_PME_PM_DPU_HELD_RESTART ] = { 47, 56, 46, 54, -1, -1 }, [ POWER6_PME_PM_IERAT_MISS ] = { 137, 146, 136, 143, -1, -1 }, [ POWER6_PME_PM_FPU_SINGLE ] = { -1, -1, -1, 122, -1, -1 }, [ POWER6_PME_PM_MRK_PTEG_FROM_LMEM ] = { -1, -1, -1, 278, -1, -1 }, [ POWER6_PME_PM_HV_COUNT ] = { -1, 351, -1, -1, -1, -1 }, [ POWER6_PME_PM_L2SA_ST_HIT ] = { 168, 177, 168, 174, -1, -1 }, [ POWER6_PME_PM_L2_LD_MISS_INST ] = { -1, 196, -1, -1, -1, -1 }, [ POWER6_PME_PM_EXT_INT ] = { -1, 67, 57, -1, -1, -1 }, [ POWER6_PME_PM_LSU1_LDF ] = { 221, 230, 216, 221, -1, -1 }, [ POWER6_PME_PM_FAB_CMD_ISSUED ] = { 59, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_PTEG_FROM_L21 ] = { -1, 305, -1, -1, -1, -1 }, [ POWER6_PME_PM_L2SA_MISS ] = { 167, 176, 167, 173, -1, -1 }, [ POWER6_PME_PM_PTEG_FROM_RL2L3_MOD ] = { 299, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_DPU_WT_COUNT ] = { -1, -1, 340, -1, -1, -1 }, [ POWER6_PME_PM_MRK_PTEG_FROM_L25_MOD ] = { -1, -1, 272, -1, -1, -1 }, [ POWER6_PME_PM_LD_HIT_L2 ] = { -1, 209, -1, -1, -1, -1 }, [ POWER6_PME_PM_PTEG_FROM_DL2L3_SHR ] = { -1, -1, 290, -1, -1, -1 }, [ POWER6_PME_PM_MEM_DP_RQ_GLOB_LOC ] = { 257, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_L3SA_MISS ] = { 192, 202, 190, 195, -1, -1 }, [ POWER6_PME_PM_NO_ITAG_COUNT ] = { 340, 347, 334, 332, -1, -1 }, [ POWER6_PME_PM_DSLB_MISS ] = { 56, 65, 55, 63, -1, -1 }, [ POWER6_PME_PM_LSU_FLUSH_ALIGN ] = { 235, 244, 229, 235, -1, -1 }, [ POWER6_PME_PM_DPU_HELD_FPU_CR ] = { 35, 43, 34, 42, -1, -1 }, [ POWER6_PME_PM_PTEG_FROM_L2MISS ] = { 296, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_MRK_DATA_FROM_DMEM ] = { -1, 269, -1, -1, -1, -1 }, [ POWER6_PME_PM_PTEG_FROM_LMEM ] = { -1, -1, -1, 291, -1, -1 }, [ POWER6_PME_PM_MRK_DERAT_REF_64K ] = { 353, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_L2SA_LD_REQ_INST ] = { 166, 175, 166, 172, -1, -1 }, [ POWER6_PME_PM_MRK_DERAT_MISS_16M ] = { -1, -1, 346, -1, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_DL2L3_MOD ] = { -1, -1, -1, 13, -1, -1 }, [ POWER6_PME_PM_FPU0_FXMULT ] = { 82, 91, 80, 88, -1, -1 }, [ POWER6_PME_PM_L3SB_MISS ] = { 195, 205, 193, 198, -1, -1 }, [ POWER6_PME_PM_STCX_CANCEL ] = { 305, 311, 297, 296, -1, -1 }, [ POWER6_PME_PM_L2SA_LD_MISS_DATA ] = { 162, 171, 162, 168, -1, -1 }, [ POWER6_PME_PM_IC_INV_L2 ] = { -1, 141, 131, -1, -1, -1 }, [ POWER6_PME_PM_DPU_HELD ] = { -1, 38, -1, -1, -1, -1 }, [ POWER6_PME_PM_PMC1_OVERFLOW ] = { -1, 303, -1, -1, -1, -1 }, [ POWER6_PME_PM_THRD_PRIO_6_CYC ] = { -1, 323, -1, -1, -1, -1 }, [ POWER6_PME_PM_MRK_PTEG_FROM_L3MISS ] = { -1, -1, 274, -1, -1, -1 }, [ POWER6_PME_PM_MRK_LSU0_REJECT_UST ] = { 272, 284, 266, 267, -1, -1 }, [ POWER6_PME_PM_MRK_INST_DISP ] = { 267, 279, -1, -1, -1, -1 }, [ POWER6_PME_PM_LARX ] = { 197, 207, 195, 200, -1, -1 }, [ POWER6_PME_PM_INST_CMPL ] = { 139, 148, 138, 145, -1, -1 }, [ POWER6_PME_PM_FXU_IDLE ] = { 117, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_MRK_DATA_FROM_DL2L3_MOD ] = { -1, -1, -1, 256, -1, -1 }, [ POWER6_PME_PM_L2_LD_REQ_DATA ] = { 186, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_LSU_DERAT_MISS_CYC ] = { 234, -1, -1, 234, -1, -1 }, [ POWER6_PME_PM_DPU_HELD_POWER_COUNT ] = { -1, 356, -1, -1, -1, -1 }, [ POWER6_PME_PM_INST_FROM_RL2L3_MOD ] = { 146, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_DMEM_CYC ] = { -1, 14, -1, -1, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_DMEM ] = { -1, 13, -1, -1, -1, -1 }, [ POWER6_PME_PM_LSU_REJECT_PARTIAL_SECTOR ] = { 241, -1, -1, 242, -1, -1 }, [ POWER6_PME_PM_LSU_REJECT_DERAT_MPRED ] = { -1, 249, -1, -1, -1, -1 }, [ POWER6_PME_PM_LSU1_REJECT_ULD ] = { 231, 240, 226, 231, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_L3_CYC ] = { -1, 21, -1, -1, -1, -1 }, [ POWER6_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { -1, -1, -1, 124, -1, -1 }, [ POWER6_PME_PM_INST_FROM_MEM_DP ] = { 145, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_LSU_FLUSH_DSI ] = { 236, 245, 230, 236, -1, -1 }, [ POWER6_PME_PM_MRK_DERAT_REF_16G ] = { -1, -1, -1, 345, -1, -1 }, [ POWER6_PME_PM_LSU_LDF_BOTH ] = { 237, -1, 232, -1, -1, -1 }, [ POWER6_PME_PM_FPU1_1FLOP ] = { 86, 95, 84, 92, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_RMEM_CYC ] = { -1, -1, -1, 23, -1, -1 }, [ POWER6_PME_PM_INST_PTEG_SECONDARY ] = { 150, 159, 150, 156, -1, -1 }, [ POWER6_PME_PM_L1_ICACHE_MISS ] = { 154, 163, -1, -1, -1, -1 }, [ POWER6_PME_PM_INST_DISP_LLA ] = { 140, 150, 140, 146, -1, -1 }, [ POWER6_PME_PM_THRD_BOTH_RUN_CYC ] = { -1, -1, -1, 304, -1, -1 }, [ POWER6_PME_PM_LSU_ST_CHAINED ] = { 246, 257, 240, 245, -1, -1 }, [ POWER6_PME_PM_FPU1_FXDIV ] = { 96, 105, 94, 102, -1, -1 }, [ POWER6_PME_PM_FREQ_UP ] = { -1, -1, -1, 123, -1, -1 }, [ POWER6_PME_PM_FAB_RETRY_SYS_PUMP ] = { 65, 75, 64, 71, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_LMEM ] = { -1, -1, -1, 20, -1, -1 }, [ POWER6_PME_PM_PMC3_OVERFLOW ] = { -1, -1, -1, 288, -1, -1 }, [ POWER6_PME_PM_LSU0_REJECT_SET_MPRED ] = { 216, 225, 211, 216, -1, -1 }, [ POWER6_PME_PM_LSU0_REJECT_DERAT_MPRED ] = { 209, 218, 204, 209, -1, -1 }, [ POWER6_PME_PM_LSU1_REJECT_STQ_FULL ] = { 230, 239, 225, 230, -1, -1 }, [ POWER6_PME_PM_MRK_BR_MPRED ] = { -1, -1, 251, -1, -1, -1 }, [ POWER6_PME_PM_L2SA_ST_MISS ] = { 169, 178, 169, 175, -1, -1 }, [ POWER6_PME_PM_LSU0_REJECT_EXTERN ] = { 210, 219, 205, 210, -1, -1 }, [ POWER6_PME_PM_MRK_BR_TAKEN ] = { 258, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_ISLB_MISS ] = { 152, 161, 152, 158, -1, -1 }, [ POWER6_PME_PM_CYC ] = { 12, 11, 10, 12, -1, -1 }, [ POWER6_PME_PM_FPU_FXDIV ] = { 105, -1, -1, 110, -1, -1 }, [ POWER6_PME_PM_DPU_HELD_LLA_END ] = { 43, 51, 42, 50, -1, -1 }, [ POWER6_PME_PM_MEM0_DP_CL_WR_LOC ] = { 249, 260, 243, 248, -1, -1 }, [ POWER6_PME_PM_MRK_LSU_REJECT_ULD ] = { 276, -1, -1, 274, -1, -1 }, [ POWER6_PME_PM_1PLUS_PPC_CMPL ] = { 1, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_PTEG_FROM_DMEM ] = { -1, 304, -1, -1, -1, -1 }, [ POWER6_PME_PM_DPU_WT_BR_MPRED_COUNT ] = { -1, -1, -1, 340, -1, -1 }, [ POWER6_PME_PM_GCT_FULL_CYC ] = { 120, 128, 119, 127, -1, -1 }, [ POWER6_PME_PM_INST_FROM_L25_SHR ] = { -1, -1, -1, 150, -1, -1 }, [ POWER6_PME_PM_MRK_DERAT_MISS_4K ] = { -1, 364, -1, -1, -1, -1 }, [ POWER6_PME_PM_DC_PREF_STREAM_ALLOC ] = { 22, 29, 21, 29, -1, -1 }, [ POWER6_PME_PM_FPU1_FIN ] = { 90, 99, 88, 96, -1, -1 }, [ POWER6_PME_PM_BR_MPRED_TA ] = { 7, 5, 5, 7, -1, -1 }, [ POWER6_PME_PM_DPU_HELD_POWER ] = { -1, 55, -1, -1, -1, -1 }, [ POWER6_PME_PM_RUN_INST_CMPL ] = { -1, -1, -1, -1, 0, -1 }, [ POWER6_PME_PM_GCT_EMPTY_CYC ] = { 119, 127, -1, -1, -1, -1 }, [ POWER6_PME_PM_LLA_COUNT ] = { 347, 354, 339, 339, -1, -1 }, [ POWER6_PME_PM_LSU0_REJECT_NO_SCRATCH ] = { 214, 223, 209, 214, -1, -1 }, [ POWER6_PME_PM_DPU_WT_IC_MISS ] = { -1, 64, -1, -1, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_L3MISS ] = { -1, -1, 15, 19, -1, -1 }, [ POWER6_PME_PM_FPU_FPSCR ] = { -1, 112, 100, -1, -1, -1 }, [ POWER6_PME_PM_VMX1_INST_ISSUED ] = { 325, 332, 319, 317, -1, -1 }, [ POWER6_PME_PM_FLUSH ] = { 67, -1, -1, 73, -1, -1 }, [ POWER6_PME_PM_ST_HIT_L2 ] = { 308, -1, -1, 298, -1, -1 }, [ POWER6_PME_PM_SYNC_CYC ] = { 312, 319, 303, 303, -1, -1 }, [ POWER6_PME_PM_FAB_SYS_PUMP ] = { 66, 76, 65, 72, -1, -1 }, [ POWER6_PME_PM_IC_PREF_REQ ] = { 133, 142, 132, 139, -1, -1 }, [ POWER6_PME_PM_MEM0_DP_RQ_GLOB_LOC ] = { 250, 261, 244, 249, -1, -1 }, [ POWER6_PME_PM_FPU_ISSUE_0 ] = { 107, 115, 103, 112, -1, -1 }, [ POWER6_PME_PM_THRD_PRIO_2_CYC ] = { -1, -1, 308, -1, -1, -1 }, [ POWER6_PME_PM_VMX_SIMPLE_ISSUED ] = { 335, 342, 329, 327, -1, -1 }, [ POWER6_PME_PM_MRK_FPU1_FIN ] = { 266, 275, 260, 261, -1, -1 }, [ POWER6_PME_PM_DPU_HELD_CW ] = { 33, 41, 32, 40, -1, -1 }, [ POWER6_PME_PM_L3SA_REF ] = { 193, 203, 191, 196, -1, -1 }, [ POWER6_PME_PM_STCX ] = { 304, 310, 296, 295, -1, -1 }, [ POWER6_PME_PM_L2SB_MISS ] = { 181, 190, 181, 187, -1, -1 }, [ POWER6_PME_PM_LSU0_REJECT ] = { 208, 217, 203, 208, -1, -1 }, [ POWER6_PME_PM_TB_BIT_TRANS ] = { 313, -1, 304, -1, -1, -1 }, [ POWER6_PME_PM_THERMAL_MAX ] = { -1, -1, 305, -1, -1, -1 }, [ POWER6_PME_PM_FPU0_STF ] = { 84, 93, 82, 90, -1, -1 }, [ POWER6_PME_PM_FPU1_FMA ] = { 92, 101, 90, 98, -1, -1 }, [ POWER6_PME_PM_LSU1_REJECT_LHS ] = { 226, 235, 221, 226, -1, -1 }, [ POWER6_PME_PM_DPU_HELD_INT ] = { 40, 48, 39, 47, -1, -1 }, [ POWER6_PME_PM_THRD_LLA_BOTH_CYC ] = { -1, -1, -1, 306, -1, -1 }, [ POWER6_PME_PM_DPU_HELD_THERMAL_COUNT ] = { 348, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_PMC4_REWIND ] = { 293, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_DERAT_REF_16M ] = { -1, -1, 342, -1, -1, -1 }, [ POWER6_PME_PM_FPU0_FCONV ] = { 73, 82, 71, 79, -1, -1 }, [ POWER6_PME_PM_L2SA_LD_REQ_DATA ] = { 165, 174, 165, 171, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_MEM_DP ] = { 15, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_MRK_VMX_FLOAT_ISSUED ] = { 286, 298, 281, 283, -1, -1 }, [ POWER6_PME_PM_MRK_PTEG_FROM_L2MISS ] = { -1, -1, -1, 277, -1, -1 }, [ POWER6_PME_PM_THRD_PRIO_DIFF_1or2_CYC ] = { -1, 324, -1, -1, -1, -1 }, [ POWER6_PME_PM_VMX0_STALL ] = { 324, 331, 318, 316, -1, -1 }, [ POWER6_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = { 131, 139, 129, 137, -1, -1 }, [ POWER6_PME_PM_LSU_DERAT_MISS ] = { -1, 243, -1, 335, -1, -1 }, [ POWER6_PME_PM_FPU0_SINGLE ] = { 83, 92, 81, 89, -1, -1 }, [ POWER6_PME_PM_FPU_ISSUE_STEERING ] = { 115, 123, 111, 120, -1, -1 }, [ POWER6_PME_PM_THRD_PRIO_1_CYC ] = { -1, 322, -1, -1, -1, -1 }, [ POWER6_PME_PM_VMX_COMPLEX_ISSUED ] = { 329, 336, 323, 321, -1, -1 }, [ POWER6_PME_PM_FPU_ISSUE_ST_FOLDED ] = { 116, 124, 112, 121, -1, -1 }, [ POWER6_PME_PM_DFU_FIN ] = { 29, 36, 28, 36, -1, -1 }, [ POWER6_PME_PM_BR_PRED_CCACHE ] = { 9, 7, 7, 9, -1, -1 }, [ POWER6_PME_PM_MRK_ST_CMPL_INT ] = { -1, -1, 277, -1, -1, -1 }, [ POWER6_PME_PM_FAB_MMIO ] = { 62, 72, 61, 68, -1, -1 }, [ POWER6_PME_PM_MRK_VMX_SIMPLE_ISSUED ] = { 288, 300, 283, 285, -1, -1 }, [ POWER6_PME_PM_FPU_STF ] = { -1, -1, 113, -1, -1, -1 }, [ POWER6_PME_PM_MEM1_DP_CL_WR_GLOB ] = { 252, 263, 246, 251, -1, -1 }, [ POWER6_PME_PM_MRK_DATA_FROM_L3MISS ] = { -1, -1, 255, -1, -1, -1 }, [ POWER6_PME_PM_GCT_NOSLOT_CYC ] = { 121, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_L2_ST_REQ_DATA ] = { -1, 200, 188, -1, -1, -1 }, [ POWER6_PME_PM_INST_TABLEWALK_COUNT ] = { 341, 348, 335, 333, -1, -1 }, [ POWER6_PME_PM_PTEG_FROM_L35_SHR ] = { -1, 306, -1, -1, -1, -1 }, [ POWER6_PME_PM_DPU_HELD_ISYNC ] = { 41, 49, 40, 48, -1, -1 }, [ POWER6_PME_PM_MRK_DATA_FROM_L25_SHR ] = { -1, -1, -1, 257, -1, -1 }, [ POWER6_PME_PM_L3SA_HIT ] = { 191, 201, 189, 194, -1, -1 }, [ POWER6_PME_PM_DERAT_MISS_16G ] = { -1, -1, -1, 343, -1, -1 }, [ POWER6_PME_PM_DATA_PTEG_2ND_HALF ] = { 18, 26, 18, 25, -1, -1 }, [ POWER6_PME_PM_L2SA_ST_REQ ] = { 170, 179, 170, 176, -1, -1 }, [ POWER6_PME_PM_INST_FROM_LMEM ] = { -1, -1, -1, 152, -1, -1 }, [ POWER6_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = { 132, 140, 130, 138, -1, -1 }, [ POWER6_PME_PM_PTEG_FROM_L2 ] = { 295, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_DATA_PTEG_1ST_HALF ] = { 17, 25, 17, 24, -1, -1 }, [ POWER6_PME_PM_BR_MPRED_COUNT ] = { 5, 3, 3, 5, -1, -1 }, [ POWER6_PME_PM_IERAT_MISS_4K ] = { -1, -1, -1, 344, -1, -1 }, [ POWER6_PME_PM_THRD_BOTH_RUN_COUNT ] = { -1, -1, -1, 336, -1, -1 }, [ POWER6_PME_PM_LSU_REJECT_ULD ] = { 244, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_DL2L3_MOD_CYC ] = { -1, -1, -1, 14, -1, -1 }, [ POWER6_PME_PM_MRK_PTEG_FROM_RL2L3_MOD ] = { 280, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_FPU0_FLOP ] = { 76, 85, 74, 82, -1, -1 }, [ POWER6_PME_PM_FPU0_FEST ] = { 74, 83, 72, 80, -1, -1 }, [ POWER6_PME_PM_MRK_LSU0_REJECT_LHS ] = { 270, 282, 264, 265, -1, -1 }, [ POWER6_PME_PM_VMX_RESULT_SAT_1 ] = { 334, 341, 328, 326, -1, -1 }, [ POWER6_PME_PM_NO_ITAG_CYC ] = { 290, 302, 285, 287, -1, -1 }, [ POWER6_PME_PM_LSU1_REJECT_NO_SCRATCH ] = { 227, 236, 222, 227, -1, -1 }, [ POWER6_PME_PM_0INST_FETCH ] = { 0, 0, 0, 0, -1, -1 }, [ POWER6_PME_PM_DPU_WT_BR_MPRED ] = { -1, -1, -1, 62, -1, -1 }, [ POWER6_PME_PM_L1_PREF ] = { 155, 164, 155, 161, -1, -1 }, [ POWER6_PME_PM_VMX_FLOAT_MULTICYCLE ] = { 331, 338, 325, 323, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_L25_SHR_CYC ] = { -1, 16, -1, -1, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_L3 ] = { -1, -1, 14, -1, -1, -1 }, [ POWER6_PME_PM_PMC2_OVERFLOW ] = { -1, -1, 286, -1, -1, -1 }, [ POWER6_PME_PM_VMX0_LD_WRBACK ] = { 323, 330, 317, 315, -1, -1 }, [ POWER6_PME_PM_FPU0_DENORM ] = { 72, 81, 70, 78, -1, -1 }, [ POWER6_PME_PM_INST_FETCH_CYC ] = { 141, 151, 141, 147, -1, -1 }, [ POWER6_PME_PM_LSU_LDF ] = { -1, 246, 231, -1, -1, -1 }, [ POWER6_PME_PM_LSU_REJECT_L2_CORR ] = { 239, -1, -1, 239, -1, -1 }, [ POWER6_PME_PM_DERAT_REF_64K ] = { -1, 360, -1, -1, -1, -1 }, [ POWER6_PME_PM_THRD_PRIO_3_CYC ] = { -1, -1, -1, 307, -1, -1 }, [ POWER6_PME_PM_FPU_FMA ] = { -1, 111, -1, -1, -1, -1 }, [ POWER6_PME_PM_INST_FROM_L35_MOD ] = { 144, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_DFU_CONV ] = { 26, 33, 25, 33, -1, -1 }, [ POWER6_PME_PM_INST_FROM_L25_MOD ] = { -1, -1, 144, -1, -1, -1 }, [ POWER6_PME_PM_PTEG_FROM_L35_MOD ] = { 297, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_MRK_VMX_ST_ISSUED ] = { 289, 301, 284, 286, -1, -1 }, [ POWER6_PME_PM_VMX_FLOAT_ISSUED ] = { 330, 337, 324, 322, -1, -1 }, [ POWER6_PME_PM_LSU0_REJECT_L2_CORR ] = { 212, 221, 207, 212, -1, -1 }, [ POWER6_PME_PM_THRD_L2MISS ] = { 314, 321, 307, 305, -1, -1 }, [ POWER6_PME_PM_FPU_FCONV ] = { 102, -1, -1, 107, -1, -1 }, [ POWER6_PME_PM_FPU_FXMULT ] = { 106, -1, -1, 111, -1, -1 }, [ POWER6_PME_PM_FPU1_FRSP ] = { 94, 103, 92, 100, -1, -1 }, [ POWER6_PME_PM_MRK_DERAT_REF_16M ] = { -1, -1, 345, -1, -1, -1 }, [ POWER6_PME_PM_L2SB_CASTOUT_SHR ] = { 172, 181, 172, 178, -1, -1 }, [ POWER6_PME_PM_THRD_ONE_RUN_COUNT ] = { 344, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_INST_FROM_RMEM ] = { -1, -1, 147, -1, -1, -1 }, [ POWER6_PME_PM_LSU_BOTH_BUS ] = { 233, 242, 228, 233, -1, -1 }, [ POWER6_PME_PM_FPU1_FSQRT_FDIV ] = { 95, 104, 93, 101, -1, -1 }, [ POWER6_PME_PM_L2_LD_REQ_INST ] = { 187, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_MRK_PTEG_FROM_L35_SHR ] = { -1, 291, -1, -1, -1, -1 }, [ POWER6_PME_PM_BR_PRED_CR ] = { 10, 8, 8, 10, -1, -1 }, [ POWER6_PME_PM_MRK_LSU0_REJECT_ULD ] = { 271, 283, 265, 266, -1, -1 }, [ POWER6_PME_PM_LSU_REJECT ] = { -1, -1, -1, 238, -1, -1 }, [ POWER6_PME_PM_LSU_REJECT_LHS_BOTH ] = { -1, 250, -1, 241, -1, -1 }, [ POWER6_PME_PM_GXO_ADDR_CYC_BUSY ] = { 125, 132, 123, 131, -1, -1 }, [ POWER6_PME_PM_LSU_SRQ_EMPTY_COUNT ] = { -1, -1, -1, 341, -1, -1 }, [ POWER6_PME_PM_PTEG_FROM_L3 ] = { -1, -1, 292, -1, -1, -1 }, [ POWER6_PME_PM_VMX0_LD_ISSUED ] = { 322, 329, 316, 314, -1, -1 }, [ POWER6_PME_PM_FXU_PIPELINED_MULT_DIV ] = { 118, 126, 118, 126, -1, -1 }, [ POWER6_PME_PM_FPU1_STF ] = { 99, 108, 97, 105, -1, -1 }, [ POWER6_PME_PM_DFU_ADD ] = { 23, 30, 22, 30, -1, -1 }, [ POWER6_PME_PM_MEM_DP_CL_WR_GLOB ] = { -1, 267, 250, -1, -1, -1 }, [ POWER6_PME_PM_MRK_LSU1_REJECT_ULD ] = { 274, 286, 268, 269, -1, -1 }, [ POWER6_PME_PM_ITLB_REF ] = { 153, 162, 153, 159, -1, -1 }, [ POWER6_PME_PM_LSU0_REJECT_L2MISS ] = { 211, 220, 206, 211, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_L35_SHR ] = { -1, 19, -1, -1, -1, -1 }, [ POWER6_PME_PM_MRK_DATA_FROM_RL2L3_MOD ] = { 263, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_FPU0_FPSCR ] = { 78, 87, 76, 84, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_L2 ] = { 13, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_DPU_HELD_XER ] = { 54, 62, 52, 60, -1, -1 }, [ POWER6_PME_PM_FAB_NODE_PUMP ] = { 63, 73, 62, 69, -1, -1 }, [ POWER6_PME_PM_VMX_RESULT_SAT_0_1 ] = { 333, 340, 327, 325, -1, -1 }, [ POWER6_PME_PM_LD_REF_L1 ] = { 201, 212, 198, 203, -1, -1 }, [ POWER6_PME_PM_TLB_REF ] = { 320, 327, 314, 312, -1, -1 }, [ POWER6_PME_PM_DC_PREF_OUT_OF_STREAMS ] = { 21, 28, 20, 28, -1, -1 }, [ POWER6_PME_PM_FLUSH_FPU ] = { 69, 78, 67, 75, -1, -1 }, [ POWER6_PME_PM_MEM1_DP_CL_WR_LOC ] = { 253, 264, 247, 252, -1, -1 }, [ POWER6_PME_PM_L2SB_LD_HIT ] = { 175, 184, 175, 181, -1, -1 }, [ POWER6_PME_PM_FAB_DCLAIM ] = { 60, 70, 59, 66, -1, -1 }, [ POWER6_PME_PM_MEM_DP_CL_WR_LOC ] = { 256, -1, -1, 255, -1, -1 }, [ POWER6_PME_PM_BR_MPRED_CR ] = { 6, 4, 4, 6, -1, -1 }, [ POWER6_PME_PM_LSU_REJECT_EXTERN ] = { -1, -1, 235, -1, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_RL2L3_MOD ] = { 16, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_DPU_HELD_RU_WQ ] = { 48, 57, 47, 55, -1, -1 }, [ POWER6_PME_PM_LD_MISS_L1 ] = { 199, 210, 197, 202, -1, -1 }, [ POWER6_PME_PM_DC_INV_L2 ] = { 20, -1, -1, 27, -1, -1 }, [ POWER6_PME_PM_MRK_PTEG_FROM_RMEM ] = { -1, -1, 275, -1, -1, -1 }, [ POWER6_PME_PM_FPU_FIN ] = { 103, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_FXU0_FIN ] = { -1, -1, 117, -1, -1, -1 }, [ POWER6_PME_PM_DPU_HELD_FPQ ] = { 34, 42, 33, 41, -1, -1 }, [ POWER6_PME_PM_GX_DMA_READ ] = { 128, 135, 126, 134, -1, -1 }, [ POWER6_PME_PM_LSU1_REJECT_PARTIAL_SECTOR ] = { 228, 237, 223, 228, -1, -1 }, [ POWER6_PME_PM_0INST_FETCH_COUNT ] = { 337, 344, 331, 329, -1, -1 }, [ POWER6_PME_PM_PMC5_OVERFLOW ] = { 294, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_L2SB_LD_REQ ] = { 178, 187, 178, 184, -1, -1 }, [ POWER6_PME_PM_THRD_PRIO_DIFF_0_CYC ] = { 318, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_RMEM ] = { -1, -1, 16, -1, -1, -1 }, [ POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_BOTH_CYC ] = { -1, -1, 234, -1, -1, -1 }, [ POWER6_PME_PM_ST_REF_L1_BOTH ] = { -1, 316, -1, 301, -1, -1 }, [ POWER6_PME_PM_VMX_PERMUTE_ISSUED ] = { 332, 339, 326, 324, -1, -1 }, [ POWER6_PME_PM_BR_TAKEN ] = { -1, 10, -1, -1, -1, -1 }, [ POWER6_PME_PM_FAB_DMA ] = { 61, 71, 60, 67, -1, -1 }, [ POWER6_PME_PM_GCT_EMPTY_COUNT ] = { -1, 358, -1, -1, -1, -1 }, [ POWER6_PME_PM_FPU1_SINGLE ] = { 98, 107, 96, 104, -1, -1 }, [ POWER6_PME_PM_L2SA_CASTOUT_SHR ] = { 158, 167, 158, 164, -1, -1 }, [ POWER6_PME_PM_L3SB_REF ] = { 196, 206, 194, 199, -1, -1 }, [ POWER6_PME_PM_FPU0_FRSP ] = { 79, 88, 77, 85, -1, -1 }, [ POWER6_PME_PM_PMC4_SAVED ] = { -1, -1, 288, -1, -1, -1 }, [ POWER6_PME_PM_L2SA_DC_INV ] = { 159, 168, 159, 165, -1, -1 }, [ POWER6_PME_PM_GXI_ADDR_CYC_BUSY ] = { 122, 129, 120, 128, -1, -1 }, [ POWER6_PME_PM_FPU0_FMA ] = { 77, 86, 75, 83, -1, -1 }, [ POWER6_PME_PM_SLB_MISS ] = { 303, -1, -1, 294, -1, -1 }, [ POWER6_PME_PM_MRK_ST_GPS ] = { -1, 294, -1, -1, -1, -1 }, [ POWER6_PME_PM_DERAT_REF_4K ] = { 350, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_L2_CASTOUT_SHR ] = { -1, 194, -1, -1, -1, -1 }, [ POWER6_PME_PM_DPU_HELD_STCX_CR ] = { 51, 60, 50, 58, -1, -1 }, [ POWER6_PME_PM_FPU0_ST_FOLDED ] = { 85, 94, 83, 91, -1, -1 }, [ POWER6_PME_PM_MRK_DATA_FROM_L21 ] = { -1, 270, -1, -1, -1, -1 }, [ POWER6_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC ] = { -1, -1, 311, -1, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_L35_MOD ] = { 14, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_DL2L3_SHR ] = { -1, -1, 11, -1, -1, -1 }, [ POWER6_PME_PM_GXI_DATA_CYC_BUSY ] = { 124, 131, 122, 130, -1, -1 }, [ POWER6_PME_PM_LSU_REJECT_STEAL ] = { 242, 254, 239, 243, -1, -1 }, [ POWER6_PME_PM_ST_FIN ] = { 307, 313, -1, -1, -1, -1 }, [ POWER6_PME_PM_DPU_HELD_CR_LOGICAL ] = { 32, 40, 31, 39, -1, -1 }, [ POWER6_PME_PM_THRD_SEL_T0 ] = { 319, 326, 312, 311, -1, -1 }, [ POWER6_PME_PM_PTEG_RELOAD_VALID ] = { 300, 308, 295, 292, -1, -1 }, [ POWER6_PME_PM_L2_PREF_ST ] = { 189, 199, 187, 192, -1, -1 }, [ POWER6_PME_PM_MRK_STCX_FAIL ] = { 281, 293, 276, 279, -1, -1 }, [ POWER6_PME_PM_LSU0_REJECT_LHS ] = { 213, 222, 208, 213, -1, -1 }, [ POWER6_PME_PM_DFU_EXP_EQ ] = { 28, 35, 27, 35, -1, -1 }, [ POWER6_PME_PM_DPU_HELD_FP_FX_MULT ] = { 36, 44, 35, 43, -1, -1 }, [ POWER6_PME_PM_L2_LD_MISS_DATA ] = { -1, 195, -1, -1, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_L35_MOD_CYC ] = { -1, -1, -1, 18, -1, -1 }, [ POWER6_PME_PM_FLUSH_FXU ] = { 70, 79, 68, 76, -1, -1 }, [ POWER6_PME_PM_FPU_ISSUE_1 ] = { 108, 116, 104, 113, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_LMEM_CYC ] = { -1, 22, -1, -1, -1, -1 }, [ POWER6_PME_PM_DPU_HELD_LSU_SOPS ] = { 45, 53, 44, 52, -1, -1 }, [ POWER6_PME_PM_INST_PTEG_2ND_HALF ] = { 149, 158, 149, 155, -1, -1 }, [ POWER6_PME_PM_THRESH_TIMEO ] = { -1, -1, 313, -1, -1, -1 }, [ POWER6_PME_PM_LSU_REJECT_UST_BOTH ] = { 245, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_LSU_REJECT_FAST ] = { -1, -1, 236, -1, -1, -1 }, [ POWER6_PME_PM_DPU_HELD_THRD_PRIO ] = { 53, 61, 51, 59, -1, -1 }, [ POWER6_PME_PM_L2_PREF_LD ] = { 188, 198, 186, 191, -1, -1 }, [ POWER6_PME_PM_FPU_FEST ] = { -1, -1, -1, 108, -1, -1 }, [ POWER6_PME_PM_MRK_DATA_FROM_RMEM ] = { -1, -1, 256, -1, -1, -1 }, [ POWER6_PME_PM_LD_MISS_L1_CYC ] = { 200, 211, -1, -1, -1, -1 }, [ POWER6_PME_PM_DERAT_MISS_4K ] = { 351, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_DPU_HELD_COMPLETION ] = { 31, 39, 30, 38, -1, -1 }, [ POWER6_PME_PM_FPU_ISSUE_STALL_ST ] = { 113, 121, 109, 118, -1, -1 }, [ POWER6_PME_PM_L2SB_DC_INV ] = { 173, 182, 173, 179, -1, -1 }, [ POWER6_PME_PM_PTEG_FROM_L25_SHR ] = { -1, -1, -1, 290, -1, -1 }, [ POWER6_PME_PM_PTEG_FROM_DL2L3_MOD ] = { -1, -1, -1, 289, -1, -1 }, [ POWER6_PME_PM_FAB_CMD_RETRIED ] = { -1, 69, -1, -1, -1, -1 }, [ POWER6_PME_PM_BR_PRED_LSTACK ] = { 11, 9, 9, 11, -1, -1 }, [ POWER6_PME_PM_GXO_DATA_CYC_BUSY ] = { 127, 134, 125, 133, -1, -1 }, [ POWER6_PME_PM_DFU_SUBNORM ] = { 30, 37, 29, 37, -1, -1 }, [ POWER6_PME_PM_FPU_ISSUE_OOO ] = { 111, 119, 107, 116, -1, -1 }, [ POWER6_PME_PM_LSU_REJECT_ULD_BOTH ] = { -1, 255, -1, -1, -1, -1 }, [ POWER6_PME_PM_L2SB_ST_MISS ] = { 183, 192, 183, 189, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_L25_MOD_CYC ] = { -1, -1, -1, 17, -1, -1 }, [ POWER6_PME_PM_INST_PTEG_1ST_HALF ] = { 148, 157, 148, 154, -1, -1 }, [ POWER6_PME_PM_DERAT_MISS_16M ] = { -1, -1, 343, -1, -1, -1 }, [ POWER6_PME_PM_GX_DMA_WRITE ] = { 129, 136, 127, 135, -1, -1 }, [ POWER6_PME_PM_MRK_PTEG_FROM_DL2L3_MOD ] = { -1, -1, -1, 275, -1, -1 }, [ POWER6_PME_PM_MEM1_DP_RQ_GLOB_LOC ] = { 254, 265, 248, 253, -1, -1 }, [ POWER6_PME_PM_L2SB_LD_REQ_DATA ] = { 179, 188, 179, 185, -1, -1 }, [ POWER6_PME_PM_L2SA_LD_MISS_INST ] = { 163, 172, 163, 169, -1, -1 }, [ POWER6_PME_PM_MRK_LSU0_REJECT_L2MISS ] = { 269, 281, 263, 264, -1, -1 }, [ POWER6_PME_PM_MRK_IFU_FIN ] = { -1, 278, -1, -1, -1, -1 }, [ POWER6_PME_PM_INST_FROM_L3 ] = { -1, -1, 145, -1, -1, -1 }, [ POWER6_PME_PM_FXU1_FIN ] = { -1, -1, -1, 125, -1, -1 }, [ POWER6_PME_PM_THRD_PRIO_4_CYC ] = { -1, -1, -1, 308, -1, -1 }, [ POWER6_PME_PM_MRK_DATA_FROM_L35_MOD ] = { 261, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_LSU_REJECT_SET_MPRED ] = { -1, 252, 238, -1, -1, -1 }, [ POWER6_PME_PM_MRK_DERAT_MISS_16G ] = { -1, -1, -1, 346, -1, -1 }, [ POWER6_PME_PM_FPU0_FXDIV ] = { 81, 90, 79, 87, -1, -1 }, [ POWER6_PME_PM_MRK_LSU1_REJECT_UST ] = { 275, 287, 269, 270, -1, -1 }, [ POWER6_PME_PM_FPU_ISSUE_DIV_SQRT_OVERLAP ] = { 110, 118, 106, 115, -1, -1 }, [ POWER6_PME_PM_INST_FROM_L35_SHR ] = { -1, 155, -1, -1, -1, -1 }, [ POWER6_PME_PM_MRK_LSU_REJECT_LHS ] = { -1, -1, -1, 273, -1, -1 }, [ POWER6_PME_PM_LSU_LMQ_FULL_CYC ] = { 238, 247, 233, 237, -1, -1 }, [ POWER6_PME_PM_SYNC_COUNT ] = { 342, 349, 336, 334, -1, -1 }, [ POWER6_PME_PM_MEM0_DP_RQ_LOC_GLOB ] = { 251, 262, 245, 250, -1, -1 }, [ POWER6_PME_PM_L2SA_CASTOUT_MOD ] = { 157, 166, 157, 163, -1, -1 }, [ POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_BOTH_COUNT ] = { -1, -1, 341, -1, -1, -1 }, [ POWER6_PME_PM_PTEG_FROM_MEM_DP ] = { 298, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_LSU_REJECT_SLOW ] = { -1, 253, -1, -1, -1, -1 }, [ POWER6_PME_PM_PTEG_FROM_L25_MOD ] = { -1, -1, 291, -1, -1, -1 }, [ POWER6_PME_PM_THRD_PRIO_7_CYC ] = { 317, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_MRK_PTEG_FROM_RL2L3_SHR ] = { -1, 292, -1, -1, -1, -1 }, [ POWER6_PME_PM_ST_REQ_L2 ] = { -1, 317, 301, -1, -1, -1 }, [ POWER6_PME_PM_ST_REF_L1 ] = { 310, 315, 300, 300, -1, -1 }, [ POWER6_PME_PM_FPU_ISSUE_STALL_THRD ] = { 114, 122, 110, 119, -1, -1 }, [ POWER6_PME_PM_RUN_COUNT ] = { 343, 350, -1, -1, -1, -1 }, [ POWER6_PME_PM_RUN_CYC ] = { 302, 309, -1, -1, -1, 0 }, [ POWER6_PME_PM_PTEG_FROM_RMEM ] = { -1, -1, 294, -1, -1, -1 }, [ POWER6_PME_PM_LSU0_LDF ] = { 205, 214, 200, 205, -1, -1 }, [ POWER6_PME_PM_ST_MISS_L1 ] = { 309, 314, 299, 299, -1, -1 }, [ POWER6_PME_PM_INST_FROM_DL2L3_SHR ] = { -1, -1, 142, -1, -1, -1 }, [ POWER6_PME_PM_L2SA_IC_INV ] = { 160, 169, 160, 166, -1, -1 }, [ POWER6_PME_PM_THRD_ONE_RUN_CYC ] = { 315, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_L2SB_LD_REQ_INST ] = { 180, 189, 180, 186, -1, -1 }, [ POWER6_PME_PM_MRK_DATA_FROM_L25_MOD ] = { -1, -1, 253, -1, -1, -1 }, [ POWER6_PME_PM_DPU_HELD_XTHRD ] = { 55, 63, 53, 61, -1, -1 }, [ POWER6_PME_PM_L2SB_ST_REQ ] = { 184, 193, 184, 190, -1, -1 }, [ POWER6_PME_PM_INST_FROM_L21 ] = { -1, 154, -1, -1, -1, -1 }, [ POWER6_PME_PM_INST_FROM_L3MISS ] = { -1, -1, 146, -1, -1, -1 }, [ POWER6_PME_PM_L3SB_HIT ] = { 194, 204, 192, 197, -1, -1 }, [ POWER6_PME_PM_EE_OFF_EXT_INT ] = { 57, 66, 56, 64, -1, -1 }, [ POWER6_PME_PM_INST_FROM_DL2L3_MOD ] = { -1, -1, -1, 148, -1, -1 }, [ POWER6_PME_PM_PMC6_OVERFLOW ] = { -1, -1, 289, -1, -1, -1 }, [ POWER6_PME_PM_FPU_FLOP ] = { 104, -1, -1, 109, -1, -1 }, [ POWER6_PME_PM_FXU_BUSY ] = { -1, 125, -1, -1, -1, -1 }, [ POWER6_PME_PM_FPU1_FLOP ] = { 91, 100, 89, 97, -1, -1 }, [ POWER6_PME_PM_IC_RELOAD_SHR ] = { 135, 144, 134, 141, -1, -1 }, [ POWER6_PME_PM_INST_TABLEWALK_CYC ] = { 151, 160, 151, 157, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_RL2L3_MOD_CYC ] = { -1, -1, -1, 22, -1, -1 }, [ POWER6_PME_PM_THRD_PRIO_DIFF_5or6_CYC ] = { -1, -1, -1, 309, -1, -1 }, [ POWER6_PME_PM_IBUF_FULL_CYC ] = { 130, 138, 128, 136, -1, -1 }, [ POWER6_PME_PM_L2SA_LD_REQ ] = { 164, 173, 164, 170, -1, -1 }, [ POWER6_PME_PM_VMX1_LD_WRBACK ] = { 327, 334, 321, 319, -1, -1 }, [ POWER6_PME_PM_MRK_FPU_FIN ] = { -1, 276, 261, -1, -1, -1 }, [ POWER6_PME_PM_THRD_PRIO_5_CYC ] = { -1, -1, 309, -1, -1, -1 }, [ POWER6_PME_PM_DFU_BACK2BACK ] = { 25, 32, 24, 32, -1, -1 }, [ POWER6_PME_PM_MRK_DATA_FROM_LMEM ] = { -1, -1, -1, 258, -1, -1 }, [ POWER6_PME_PM_LSU_REJECT_LHS ] = { 240, -1, -1, 240, -1, -1 }, [ POWER6_PME_PM_DPU_HELD_SPR ] = { 50, 59, 49, 57, -1, -1 }, [ POWER6_PME_PM_FREQ_DOWN ] = { -1, -1, 115, -1, -1, -1 }, [ POWER6_PME_PM_DFU_ENC_BCD_DPD ] = { 27, 34, 26, 34, -1, -1 }, [ POWER6_PME_PM_DPU_HELD_GPR ] = { 39, 47, 38, 46, -1, -1 }, [ POWER6_PME_PM_LSU0_NCST ] = { 207, 216, 202, 207, -1, -1 }, [ POWER6_PME_PM_MRK_INST_ISSUED ] = { 268, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_INST_FROM_RL2L3_SHR ] = { -1, 156, -1, -1, -1, -1 }, [ POWER6_PME_PM_FPU_DENORM ] = { -1, 110, 99, -1, -1, -1 }, [ POWER6_PME_PM_PTEG_FROM_L3MISS ] = { -1, -1, 293, -1, -1, -1 }, [ POWER6_PME_PM_RUN_PURR ] = { -1, -1, -1, 347, -1, -1 }, [ POWER6_PME_PM_MRK_VMX0_LD_WRBACK ] = { 283, 295, 278, 280, -1, -1 }, [ POWER6_PME_PM_L2_MISS ] = { -1, 197, 185, -1, -1, -1 }, [ POWER6_PME_PM_MRK_DATA_FROM_L3 ] = { -1, -1, 254, -1, -1, -1 }, [ POWER6_PME_PM_MRK_LSU1_REJECT_LHS ] = { 273, 285, 267, 268, -1, -1 }, [ POWER6_PME_PM_L2SB_LD_MISS_INST ] = { 177, 186, 177, 183, -1, -1 }, [ POWER6_PME_PM_PTEG_FROM_RL2L3_SHR ] = { -1, 307, -1, -1, -1, -1 }, [ POWER6_PME_PM_MRK_DERAT_MISS_64K ] = { 354, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_LWSYNC ] = { 247, 258, 241, 246, -1, -1 }, [ POWER6_PME_PM_FPU1_FXMULT ] = { 97, 106, 95, 103, -1, -1 }, [ POWER6_PME_PM_MEM0_DP_CL_WR_GLOB ] = { 248, 259, 242, 247, -1, -1 }, [ POWER6_PME_PM_LSU0_REJECT_PARTIAL_SECTOR ] = { 215, 224, 210, 215, -1, -1 }, [ POWER6_PME_PM_INST_IMC_MATCH_CMPL ] = { 147, -1, -1, 153, -1, -1 }, [ POWER6_PME_PM_DPU_HELD_THERMAL ] = { 52, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_FPU_FRSP ] = { -1, 113, 101, -1, -1, -1 }, [ POWER6_PME_PM_MRK_INST_FIN ] = { -1, -1, 262, 262, -1, -1 }, [ POWER6_PME_PM_MRK_PTEG_FROM_DL2L3_SHR ] = { -1, -1, 271, -1, -1, -1 }, [ POWER6_PME_PM_MRK_DTLB_REF ] = { 264, 273, 258, 259, -1, -1 }, [ POWER6_PME_PM_MRK_PTEG_FROM_L25_SHR ] = { -1, -1, -1, 276, -1, -1 }, [ POWER6_PME_PM_DPU_HELD_LSU ] = { 44, 52, 43, 51, -1, -1 }, [ POWER6_PME_PM_FPU_FSQRT_FDIV ] = { -1, 114, 102, -1, -1, -1 }, [ POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_COUNT ] = { -1, 359, -1, -1, -1, -1 }, [ POWER6_PME_PM_DATA_PTEG_SECONDARY ] = { 19, 27, 19, 26, -1, -1 }, [ POWER6_PME_PM_FPU1_FEST ] = { 89, 98, 87, 95, -1, -1 }, [ POWER6_PME_PM_L2SA_LD_HIT ] = { 161, 170, 161, 167, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_MEM_DP_CYC ] = { -1, -1, -1, 21, -1, -1 }, [ POWER6_PME_PM_BR_MPRED_CCACHE ] = { 4, 2, 2, 4, -1, -1 }, [ POWER6_PME_PM_DPU_HELD_COUNT ] = { -1, 355, -1, -1, -1, -1 }, [ POWER6_PME_PM_LSU1_REJECT_SET_MPRED ] = { 229, 238, 224, 229, -1, -1 }, [ POWER6_PME_PM_FPU_ISSUE_2 ] = { 109, 117, 105, 114, -1, -1 }, [ POWER6_PME_PM_LSU1_REJECT_L2_CORR ] = { 225, 234, 220, 225, -1, -1 }, [ POWER6_PME_PM_MRK_PTEG_FROM_DMEM ] = { -1, 289, -1, -1, -1, -1 }, [ POWER6_PME_PM_MEM1_DP_RQ_LOC_GLOB ] = { 255, 266, 249, 254, -1, -1 }, [ POWER6_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC ] = { -1, 325, -1, -1, -1, -1 }, [ POWER6_PME_PM_THRD_PRIO_0_CYC ] = { 316, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { -1, -1, 116, -1, -1, -1 }, [ POWER6_PME_PM_LSU1_REJECT_DERAT_MPRED ] = { 223, 232, 218, 223, -1, -1 }, [ POWER6_PME_PM_MRK_VMX1_LD_WRBACK ] = { 284, 296, 279, 281, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_RL2L3_SHR_CYC ] = { -1, 24, -1, -1, -1, -1 }, [ POWER6_PME_PM_IERAT_MISS_16M ] = { -1, 362, -1, -1, -1, -1 }, [ POWER6_PME_PM_MRK_DATA_FROM_MEM_DP ] = { 262, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_LARX_L1HIT ] = { 198, 208, 196, 201, -1, -1 }, [ POWER6_PME_PM_L2_ST_MISS_DATA ] = { 190, -1, -1, 193, -1, -1 }, [ POWER6_PME_PM_FPU_ST_FOLDED ] = { -1, -1, 114, -1, -1, -1 }, [ POWER6_PME_PM_MRK_DATA_FROM_L35_SHR ] = { -1, 271, -1, -1, -1, -1 }, [ POWER6_PME_PM_DPU_HELD_MULT_GPR ] = { 46, 54, 45, 53, -1, -1 }, [ POWER6_PME_PM_FPU0_1FLOP ] = { 71, 80, 69, 77, -1, -1 }, [ POWER6_PME_PM_IERAT_MISS_16G ] = { 352, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_IC_PREF_WRITE ] = { 134, 143, 133, 140, -1, -1 }, [ POWER6_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC ] = { -1, -1, -1, 310, -1, -1 }, [ POWER6_PME_PM_FPU0_FIN ] = { 75, 84, 73, 81, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_L2_CYC ] = { -1, 18, -1, -1, -1, -1 }, [ POWER6_PME_PM_DERAT_REF_16G ] = { -1, -1, -1, 342, -1, -1 }, [ POWER6_PME_PM_BR_PRED ] = { 8, 6, 6, 8, -1, -1 }, [ POWER6_PME_PM_VMX1_LD_ISSUED ] = { 326, 333, 320, 318, -1, -1 }, [ POWER6_PME_PM_L2SB_CASTOUT_MOD ] = { 171, 180, 171, 177, -1, -1 }, [ POWER6_PME_PM_INST_FROM_DMEM ] = { -1, 152, -1, -1, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_L35_SHR_CYC ] = { -1, 20, -1, -1, -1, -1 }, [ POWER6_PME_PM_LSU0_NCLD ] = { 206, 215, 201, 206, -1, -1 }, [ POWER6_PME_PM_FAB_RETRY_NODE_PUMP ] = { 64, 74, 63, 70, -1, -1 }, [ POWER6_PME_PM_VMX0_INST_ISSUED ] = { 321, 328, 315, 313, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_L25_MOD ] = { -1, -1, 12, -1, -1, -1 }, [ POWER6_PME_PM_DPU_HELD_ITLB_ISLB ] = { 42, 50, 41, 49, -1, -1 }, [ POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { -1, 248, -1, -1, -1, -1 }, [ POWER6_PME_PM_THRD_CONC_RUN_INST ] = { -1, -1, 306, -1, -1, -1 }, [ POWER6_PME_PM_MRK_PTEG_FROM_L2 ] = { 277, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_PURR ] = { 301, -1, -1, 293, -1, -1 }, [ POWER6_PME_PM_DERAT_MISS_64K ] = { -1, 361, -1, -1, -1, -1 }, [ POWER6_PME_PM_PMC2_REWIND ] = { -1, -1, 287, -1, -1, -1 }, [ POWER6_PME_PM_INST_FROM_L2 ] = { 143, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_INST_DISP ] = { -1, 149, 139, -1, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_L25_SHR ] = { -1, -1, -1, 16, -1, -1 }, [ POWER6_PME_PM_L1_DCACHE_RELOAD_VALID ] = { -1, -1, 154, 160, -1, -1 }, [ POWER6_PME_PM_LSU1_REJECT_UST ] = { 232, 241, 227, 232, -1, -1 }, [ POWER6_PME_PM_FAB_ADDR_COLLISION ] = { 58, 68, 58, 65, -1, -1 }, [ POWER6_PME_PM_MRK_FXU_FIN ] = { -1, 277, -1, -1, -1, -1 }, [ POWER6_PME_PM_LSU0_REJECT_UST ] = { 219, 228, 214, 219, -1, -1 }, [ POWER6_PME_PM_PMC4_OVERFLOW ] = { 292, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_MRK_PTEG_FROM_L3 ] = { -1, -1, 273, -1, -1, -1 }, [ POWER6_PME_PM_INST_FROM_L2MISS ] = { -1, -1, -1, 151, -1, -1 }, [ POWER6_PME_PM_L2SB_ST_HIT ] = { 182, 191, 182, 188, -1, -1 }, [ POWER6_PME_PM_DPU_WT_IC_MISS_COUNT ] = { -1, 357, -1, -1, -1, -1 }, [ POWER6_PME_PM_MRK_DATA_FROM_DL2L3_SHR ] = { -1, -1, 252, -1, -1, -1 }, [ POWER6_PME_PM_MRK_PTEG_FROM_L35_MOD ] = { 278, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_FPU1_FPSCR ] = { 93, 102, 91, 99, -1, -1 }, [ POWER6_PME_PM_LSU_REJECT_UST ] = { -1, 256, -1, -1, -1, -1 }, [ POWER6_PME_PM_LSU0_DERAT_MISS ] = { 204, 213, 199, 204, -1, -1 }, [ POWER6_PME_PM_MRK_PTEG_FROM_MEM_DP ] = { 279, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_MRK_DATA_FROM_L2 ] = { 259, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_FPU0_FSQRT_FDIV ] = { 80, 89, 78, 86, -1, -1 }, [ POWER6_PME_PM_DPU_HELD_FXU_SOPS ] = { 38, 46, 37, 45, -1, -1 }, [ POWER6_PME_PM_MRK_FPU0_FIN ] = { 265, 274, 259, 260, -1, -1 }, [ POWER6_PME_PM_L2SB_LD_MISS_DATA ] = { 176, 185, 176, 182, -1, -1 }, [ POWER6_PME_PM_LSU_SRQ_EMPTY_CYC ] = { -1, -1, -1, 244, -1, -1 }, [ POWER6_PME_PM_1PLUS_PPC_DISP ] = { 2, -1, -1, 1, -1, -1 }, [ POWER6_PME_PM_VMX_ST_ISSUED ] = { 336, 343, 330, 328, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_L2MISS ] = { -1, 17, 13, -1, -1, -1 }, [ POWER6_PME_PM_LSU0_REJECT_ULD ] = { 218, 227, 213, 218, -1, -1 }, [ POWER6_PME_PM_SUSPENDED ] = { 311, 318, 302, 302, -1, -1 }, [ POWER6_PME_PM_DFU_ADD_SHIFTED_BOTH ] = { 24, 31, 23, 31, -1, -1 }, [ POWER6_PME_PM_LSU_REJECT_NO_SCRATCH ] = { -1, 251, 237, -1, -1, -1 }, [ POWER6_PME_PM_STCX_FAIL ] = { 306, 312, 298, 297, -1, -1 }, [ POWER6_PME_PM_FPU1_DENORM ] = { 87, 96, 85, 93, -1, -1 }, [ POWER6_PME_PM_GCT_NOSLOT_COUNT ] = { 349, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_DL2L3_SHR_CYC ] = { -1, 12, -1, -1, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_L21 ] = { -1, 15, -1, -1, -1, -1 }, [ POWER6_PME_PM_FPU_1FLOP ] = { 101, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_LSU1_REJECT ] = { 222, 231, 217, 222, -1, -1 }, [ POWER6_PME_PM_IC_REQ ] = { 136, 145, 135, 142, -1, -1 }, [ POWER6_PME_PM_MRK_DFU_FIN ] = { -1, -1, 257, -1, -1, -1 }, [ POWER6_PME_PM_NOT_LLA_CYC ] = { 346, 353, 338, 338, -1, -1 }, [ POWER6_PME_PM_INST_FROM_L1 ] = { 142, 153, 143, 149, -1, -1 }, [ POWER6_PME_PM_MRK_VMX_COMPLEX_ISSUED ] = { 285, 297, 280, 282, -1, -1 }, [ POWER6_PME_PM_BRU_FIN ] = { 3, 1, 1, 2, -1, -1 }, [ POWER6_PME_PM_LSU1_REJECT_EXTERN ] = { 224, 233, 219, 224, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_L21_CYC ] = { -1, -1, -1, 15, -1, -1 }, [ POWER6_PME_PM_GXI_CYC_BUSY ] = { 123, 130, 121, 129, -1, -1 }, [ POWER6_PME_PM_MRK_LD_MISS_L1 ] = { -1, 280, -1, -1, -1, -1 }, [ POWER6_PME_PM_L1_WRITE_CYC ] = { 156, 165, 156, 162, -1, -1 }, [ POWER6_PME_PM_LLA_CYC ] = { 345, 352, 337, 337, -1, -1 }, [ POWER6_PME_PM_MRK_DATA_FROM_L2MISS ] = { 260, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_GCT_FULL_COUNT ] = { 339, 346, 333, 331, -1, -1 }, [ POWER6_PME_PM_MEM_DP_RQ_LOC_GLOB ] = { -1, 268, -1, -1, -1, -1 }, [ POWER6_PME_PM_DATA_FROM_RL2L3_SHR ] = { -1, 23, -1, -1, -1, -1 }, [ POWER6_PME_PM_MRK_LSU_REJECT_UST ] = { -1, 288, 270, -1, -1, -1 }, [ POWER6_PME_PM_MRK_VMX_PERMUTE_ISSUED ] = { 287, 299, 282, 284, -1, -1 }, [ POWER6_PME_PM_MRK_PTEG_FROM_L21 ] = { -1, 290, -1, -1, -1, -1 }, [ POWER6_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = { -1, 320, -1, -1, -1, -1 }, [ POWER6_PME_PM_BR_MPRED ] = { -1, -1, -1, 3, -1, -1 }, [ POWER6_PME_PM_LD_REQ_L2 ] = { 203, -1, -1, -1, -1, -1 }, [ POWER6_PME_PM_FLUSH_ASYNC ] = { 68, 77, 66, 74, -1, -1 }, [ POWER6_PME_PM_HV_CYC ] = { -1, 137, -1, -1, -1, -1 }, [ POWER6_PME_PM_LSU1_DERAT_MISS ] = { 220, 229, 215, 220, -1, -1 }, [ POWER6_PME_PM_DPU_HELD_SMT ] = { 49, 58, 48, 56, -1, -1 }, [ POWER6_PME_PM_MRK_LSU_FIN ] = { -1, -1, -1, 272, -1, -1 }, [ POWER6_PME_PM_MRK_DATA_FROM_RL2L3_SHR ] = { -1, 272, -1, -1, -1, -1 }, [ POWER6_PME_PM_LSU0_REJECT_STQ_FULL ] = { 217, 226, 212, 217, -1, -1 }, [ POWER6_PME_PM_MRK_DERAT_REF_4K ] = { -1, 363, -1, -1, -1, -1 }, [ POWER6_PME_PM_FPU_ISSUE_STALL_FPR ] = { 112, 120, 108, 117, -1, -1 }, [ POWER6_PME_PM_IFU_FIN ] = { 138, 147, 137, 144, -1, -1 }, [ POWER6_PME_PM_GXO_CYC_BUSY ] = { 126, 133, 124, 132, -1, -1 } }; static const unsigned long long power6_group_vecs[][POWER6_NUM_GROUP_VEC] = { [ POWER6_PME_PM_LSU_REJECT_STQ_FULL ] = { 0x2000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DPU_HELD_FXU_MULTI ] = { 0x0000008000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_VMX1_STALL ] = { 0x0000000000000000ULL, 0x0000000001000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_PMC2_SAVED ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_L2SB_IC_INV ] = { 0x0000000000000000ULL, 0x0000400000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_IERAT_MISS_64K ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000100ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_THRD_PRIO_DIFF_3or4_CYC ] = { 0x0000000000000000ULL, 0x0000000000010000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LD_REF_L1_BOTH ] = { 0x0000400000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FPU1_FCONV ] = { 0x0000000000000000ULL, 0x4000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_IBUF_FULL_COUNT ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000100000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_LSU_DERAT_MISS ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000800000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_ST_CMPL ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000002000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_L2_CASTOUT_MOD ] = { 0x0000000000000000ULL, 0x0000008000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FPU1_ST_FOLDED ] = { 0x0000000000000000ULL, 0x4000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_INST_TIMEO ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000400000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DPU_WT ] = { 0x0000000800000000ULL, 0x0000000000000000ULL, 0x0004000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DPU_HELD_RESTART ] = { 0x0000020000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_IERAT_MISS ] = { 0x0400000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FPU_SINGLE ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000002ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_PTEG_FROM_LMEM ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000040000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_HV_COUNT ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000800000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_L2SA_ST_HIT ] = { 0x0000000000000000ULL, 0x0001000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_L2_LD_MISS_INST ] = { 0x0000000000000000ULL, 0x0000004000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_EXT_INT ] = { 0x0080000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU1_LDF ] = { 0x0000000000000000ULL, 0x0000000000000100ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FAB_CMD_ISSUED ] = { 0x0000000000000000ULL, 0x0000000028000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_PTEG_FROM_L21 ] = { 0x0000000018000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_L2SA_MISS ] = { 0x0000000000000000ULL, 0x0000100000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_PTEG_FROM_RL2L3_MOD ] = { 0x0000000080000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DPU_WT_COUNT ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0002040000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_PTEG_FROM_L25_MOD ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000008000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LD_HIT_L2 ] = { 0x0000000000000000ULL, 0x0000010000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_PTEG_FROM_DL2L3_SHR ] = { 0x0000000080000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MEM_DP_RQ_GLOB_LOC ] = { 0x0000000000000000ULL, 0x0000000040000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_L3SA_MISS ] = { 0x0000000000000000ULL, 0x0004000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_NO_ITAG_COUNT ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000400000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DSLB_MISS ] = { 0x0600000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU_FLUSH_ALIGN ] = { 0x0000000000000000ULL, 0x0000000000000800ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DPU_HELD_FPU_CR ] = { 0x0000188000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_PTEG_FROM_L2MISS ] = { 0x0000000010000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_DATA_FROM_DMEM ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000400ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_PTEG_FROM_LMEM ] = { 0x0000000060000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_DERAT_REF_64K ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000001000000000ULL, 0x0000000000000010ULL }, [ POWER6_PME_PM_L2SA_LD_REQ_INST ] = { 0x0000000000000000ULL, 0x0000040000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_DERAT_MISS_16M ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000002000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DATA_FROM_DL2L3_MOD ] = { 0x0000000000000400ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FPU0_FXMULT ] = { 0x0000000000000000ULL, 0x0200000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_L3SB_MISS ] = { 0x0000000000000000ULL, 0x0008000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_STCX_CANCEL ] = { 0x0008000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_L2SA_LD_MISS_DATA ] = { 0x0000000000000000ULL, 0x0000020000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_IC_INV_L2 ] = { 0x0000000000000000ULL, 0x0000008000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DPU_HELD ] = { 0x0000002000000000ULL, 0x0000000000000000ULL, 0x0004000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_PMC1_OVERFLOW ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_THRD_PRIO_6_CYC ] = { 0x0000000000000000ULL, 0x0000000000008000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_PTEG_FROM_L3MISS ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000040000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_LSU0_REJECT_UST ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000020000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_INST_DISP ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000080000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LARX ] = { 0x0018000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_INST_CMPL ] = { 0x0100000000006001ULL, 0x0000000000000000ULL, 0x3800003ffffffe18ULL, 0x0000000000000038ULL }, [ POWER6_PME_PM_FXU_IDLE ] = { 0x0000000000000000ULL, 0x0000000000040000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_DATA_FROM_DL2L3_MOD ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000400ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_L2_LD_REQ_DATA ] = { 0x0000000000000000ULL, 0x0000002000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU_DERAT_MISS_CYC ] = { 0x0000000000000000ULL, 0x0000000000000800ULL, 0x0040000000000020ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DPU_HELD_POWER_COUNT ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0100020000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_INST_FROM_RL2L3_MOD ] = { 0x0000000001000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DATA_FROM_DMEM_CYC ] = { 0x0000000000004000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DATA_FROM_DMEM ] = { 0x0000000000000800ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU_REJECT_PARTIAL_SECTOR ] = { 0x2000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU_REJECT_DERAT_MPRED ] = { 0x0800000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU1_REJECT_ULD ] = { 0x8000000000000000ULL, 0x0000000000000002ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DATA_FROM_L3_CYC ] = { 0x0000000000010000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { 0x0000000000000000ULL, 0x0000000000040000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_INST_FROM_MEM_DP ] = { 0x0000000002000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU_FLUSH_DSI ] = { 0x0000000000000000ULL, 0x0000000000000800ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_DERAT_REF_16G ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000010ULL }, [ POWER6_PME_PM_LSU_LDF_BOTH ] = { 0x0000000000000000ULL, 0x0000000000000100ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FPU1_1FLOP ] = { 0x0000000000000000ULL, 0x0800000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DATA_FROM_RMEM_CYC ] = { 0x0000000000004000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_INST_PTEG_SECONDARY ] = { 0x0000000200000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_L1_ICACHE_MISS ] = { 0x0000000800000000ULL, 0x0000000000000000ULL, 0x0000040000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_INST_DISP_LLA ] = { 0x0000000000000000ULL, 0x0000000000001000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_THRD_BOTH_RUN_CYC ] = { 0x0020000000000000ULL, 0x0000000000000000ULL, 0x0200000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU_ST_CHAINED ] = { 0x0000000000000000ULL, 0x0000000000000200ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FPU1_FXDIV ] = { 0x0000000000000000ULL, 0x1000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FREQ_UP ] = { 0x0000000400000000ULL, 0x0000000000000000ULL, 0x0000020000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FAB_RETRY_SYS_PUMP ] = { 0x0000000000000000ULL, 0x0000000010000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DATA_FROM_LMEM ] = { 0x0000000000100800ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_PMC3_OVERFLOW ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU0_REJECT_SET_MPRED ] = { 0x0000000000000000ULL, 0x0000000000000001ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU0_REJECT_DERAT_MPRED ] = { 0x0000000000000000ULL, 0x0000000000000084ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU1_REJECT_STQ_FULL ] = { 0x0000000000000000ULL, 0x0000000000000040ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_BR_MPRED ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000200ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_L2SA_ST_MISS ] = { 0x0000000000000000ULL, 0x0000080000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU0_REJECT_EXTERN ] = { 0x0000000000000000ULL, 0x0000000000000008ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_BR_TAKEN ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000200ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_ISLB_MISS ] = { 0x0600000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_CYC ] = { 0x0100200000283003ULL, 0x0000000000000000ULL, 0x5c00000481000018ULL, 0x0000000000000005ULL }, [ POWER6_PME_PM_FPU_FXDIV ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000002ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DPU_HELD_LLA_END ] = { 0x0000020000000000ULL, 0x0000000000001000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MEM0_DP_CL_WR_LOC ] = { 0x0000000000000000ULL, 0x0000000080000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_LSU_REJECT_ULD ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000210000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_1PLUS_PPC_CMPL ] = { 0x0040000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_PTEG_FROM_DMEM ] = { 0x0000000040000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DPU_WT_BR_MPRED_COUNT ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0002040000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_GCT_FULL_CYC ] = { 0x0000000000000000ULL, 0x0000000000002000ULL, 0x0000400000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_INST_FROM_L25_SHR ] = { 0x0000000000800000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_DERAT_MISS_4K ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000002000000000ULL, 0x0000000000000020ULL }, [ POWER6_PME_PM_DC_PREF_STREAM_ALLOC ] = { 0x0001000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FPU1_FIN ] = { 0x0000000000000000ULL, 0x2000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_BR_MPRED_TA ] = { 0x0000000000000028ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DPU_HELD_POWER ] = { 0x0000001400000000ULL, 0x0000000000000000ULL, 0x0200000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_RUN_INST_CMPL ] = { 0xffffffffffffffffULL, 0xffffffffffffffffULL, 0xffffffffffffffffULL, 0x000000000000003fULL }, [ POWER6_PME_PM_GCT_EMPTY_CYC ] = { 0x0000000000000000ULL, 0x0000000000002000ULL, 0x0010000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LLA_COUNT ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000080000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU0_REJECT_NO_SCRATCH ] = { 0x0000000000000000ULL, 0x0000000000000010ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DPU_WT_IC_MISS ] = { 0x0000000800000000ULL, 0x0000000000000000ULL, 0x0000080000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DATA_FROM_L3MISS ] = { 0x0000000000000180ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000008ULL }, [ POWER6_PME_PM_FPU_FPSCR ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000001ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_VMX1_INST_ISSUED ] = { 0x0000000000000000ULL, 0x0000000000200000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FLUSH ] = { 0x0002000000080000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_ST_HIT_L2 ] = { 0x0000000000000000ULL, 0x0000010000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_SYNC_CYC ] = { 0x0000200000000000ULL, 0x0000000000000000ULL, 0x0061800000000010ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FAB_SYS_PUMP ] = { 0x0000000000000000ULL, 0x0000000010000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_IC_PREF_REQ ] = { 0x0004000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MEM0_DP_RQ_GLOB_LOC ] = { 0x0000000000000000ULL, 0x0000000080000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FPU_ISSUE_0 ] = { 0x0000000000000000ULL, 0x0010000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_THRD_PRIO_2_CYC ] = { 0x0000000000000000ULL, 0x0000000000004000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_VMX_SIMPLE_ISSUED ] = { 0x0000000000000000ULL, 0x0000000000100000ULL, 0x0000000400000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_FPU1_FIN ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000800100000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DPU_HELD_CW ] = { 0x0000002000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_L3SA_REF ] = { 0x0000000000000000ULL, 0x0004000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_STCX ] = { 0x0018000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_L2SB_MISS ] = { 0x0000000000000000ULL, 0x0000100000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU0_REJECT ] = { 0x0000000000000000ULL, 0x0000000000000044ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_TB_BIT_TRANS ] = { 0x0080000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_THERMAL_MAX ] = { 0x0000001000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FPU0_STF ] = { 0x0000000000000000ULL, 0x0080000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FPU1_FMA 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POWER6_PME_PM_L2_PREF_ST ] = { 0x0000000000000000ULL, 0x0002000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_STCX_FAIL ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000400000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU0_REJECT_LHS ] = { 0x0000000000000000ULL, 0x0000000000000020ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DFU_EXP_EQ ] = { 0x0000000000000000ULL, 0x0000000004000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DPU_HELD_FP_FX_MULT ] = { 0x0000010000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_L2_LD_MISS_DATA ] = { 0x0000000000000000ULL, 0x0000002000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DATA_FROM_L35_MOD_CYC ] = { 0x0000000000208000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FLUSH_FXU ] = { 0x0002000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FPU_ISSUE_1 ] = { 0x0000000000000000ULL, 0x0010000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DATA_FROM_LMEM_CYC ] = { 0x0000000000102000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DPU_HELD_LSU_SOPS ] = { 0x0000200000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_INST_PTEG_2ND_HALF ] = { 0x0000000200000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_THRESH_TIMEO ] = { 0x0040000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU_REJECT_UST_BOTH ] = { 0x4000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU_REJECT_FAST ] = { 0x0800000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DPU_HELD_THRD_PRIO ] = { 0x0000040000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_L2_PREF_LD ] = { 0x0000000000000000ULL, 0x0002004000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FPU_FEST ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000004ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_DATA_FROM_RMEM ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000008000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LD_MISS_L1_CYC ] = { 0x0000000000001000ULL, 0x0000000000000000ULL, 0x0000000000000020ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DERAT_MISS_4K ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000040ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DPU_HELD_COMPLETION ] = { 0x0000110000000000ULL, 0x0000000000000000ULL, 0x0300000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FPU_ISSUE_STALL_ST ] = { 0x0000000000000000ULL, 0x0060000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_L2SB_DC_INV ] = { 0x0000000000000000ULL, 0x0000400000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_PTEG_FROM_L25_SHR ] = { 0x0000000008000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_PTEG_FROM_DL2L3_MOD ] = { 0x0000000010000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FAB_CMD_RETRIED ] = { 0x0000000000000000ULL, 0x0000000028000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_BR_PRED_LSTACK ] = { 0x0000000000000018ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_GXO_DATA_CYC_BUSY ] = { 0x0000000000000000ULL, 0x0000000200000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DFU_SUBNORM ] = { 0x0000000000000000ULL, 0x0000000004000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FPU_ISSUE_OOO ] = { 0x0000000000000000ULL, 0x0020000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU_REJECT_ULD_BOTH ] = { 0x8000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_L2SB_ST_MISS ] = { 0x0000000000000000ULL, 0x0000080000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DATA_FROM_L25_MOD_CYC ] = { 0x0000000000001000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_INST_PTEG_1ST_HALF ] = { 0x0000000200000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DERAT_MISS_16M ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000040ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_GX_DMA_WRITE ] = { 0x0000000000000000ULL, 0x0000000800000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_PTEG_FROM_DL2L3_MOD ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000008000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MEM1_DP_RQ_GLOB_LOC ] = { 0x0000000000000000ULL, 0x0000000100000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_L2SB_LD_REQ_DATA ] = { 0x0000000000000000ULL, 0x0000020000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_L2SA_LD_MISS_INST ] = { 0x0000000000000000ULL, 0x0000040000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_LSU0_REJECT_L2MISS ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000800000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_IFU_FIN ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000400000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_INST_FROM_L3 ] = { 0x0000000000800000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FXU1_FIN ] = { 0x0000000000000000ULL, 0x0000000000080000ULL, 0x4000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_THRD_PRIO_4_CYC ] = { 0x0000000000000000ULL, 0x0000000000008000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_DATA_FROM_L35_MOD ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000002000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU_REJECT_SET_MPRED ] = { 0x0000000000000000ULL, 0x0000000000000001ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_DERAT_MISS_16G ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000020ULL }, [ POWER6_PME_PM_FPU0_FXDIV ] = { 0x0000000000000000ULL, 0x0100000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_LSU1_REJECT_UST ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000040000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FPU_ISSUE_DIV_SQRT_OVERLAP ] = { 0x0000000000000000ULL, 0x0060000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_INST_FROM_L35_SHR ] = { 0x0000000000800000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_LSU_REJECT_LHS ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000010000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU_LMQ_FULL_CYC ] = { 0x0000000000000000ULL, 0x0000000000000400ULL, 0x0000008000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_SYNC_COUNT ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0061800000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MEM0_DP_RQ_LOC_GLOB ] = { 0x0000000000000000ULL, 0x0000000080000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_L2SA_CASTOUT_MOD ] = { 0x0000000000000000ULL, 0x0000200000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_BOTH_COUNT ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0008008000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_PTEG_FROM_MEM_DP ] = { 0x0000000040000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU_REJECT_SLOW ] = { 0x2000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_PTEG_FROM_L25_MOD ] = { 0x0000000008000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_THRD_PRIO_7_CYC ] = { 0x0000000000000000ULL, 0x0000000000008000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_PTEG_FROM_RL2L3_SHR ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000080000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_ST_REQ_L2 ] = { 0x0000000000000000ULL, 0x0000010000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_ST_REF_L1 ] = { 0x0000c00000000000ULL, 0x0000000000000000ULL, 0x2000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FPU_ISSUE_STALL_THRD ] = { 0x0000000000000000ULL, 0x0040000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_RUN_COUNT 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0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_INST_FROM_DL2L3_MOD ] = { 0x0000000001000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_PMC6_OVERFLOW ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FPU_FLOP ] = { 0x0000000000000000ULL, 0x8000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FXU_BUSY ] = { 0x0000000000000000ULL, 0x0000000000040000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FPU1_FLOP ] = { 0x0000000000000000ULL, 0x1000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_IC_RELOAD_SHR ] = { 0x0004000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_INST_TABLEWALK_CYC ] = { 0x0000000200000000ULL, 0x0000000000000000ULL, 0x0000200000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DATA_FROM_RL2L3_MOD_CYC ] = { 0x0000000000010000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_THRD_PRIO_DIFF_5or6_CYC ] = { 0x0000000000000000ULL, 0x0000000000010000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_IBUF_FULL_CYC ] = { 0x0001000000000000ULL, 0x0000000000000000ULL, 0x0000100000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_L2SA_LD_REQ ] = { 0x0000000000000000ULL, 0x0000800000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_VMX1_LD_WRBACK ] = { 0x0000000000000000ULL, 0x0000000000400000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_FPU_FIN ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000800100000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_THRD_PRIO_5_CYC ] = { 0x0000000000000000ULL, 0x0000000000008000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DFU_BACK2BACK ] = { 0x0000000000000000ULL, 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0x0000000000001000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_LSU1_REJECT_LHS ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000040000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_L2SB_LD_MISS_INST ] = { 0x0000000000000000ULL, 0x0000040000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_PTEG_FROM_RL2L3_SHR ] = { 0x0000000080000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_DERAT_MISS_64K ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000002000000000ULL, 0x0000000000000020ULL }, [ POWER6_PME_PM_LWSYNC ] = { 0x0000200000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FPU1_FXMULT ] = { 0x0000000000000000ULL, 0x2000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MEM0_DP_CL_WR_GLOB ] = { 0x0000000000000000ULL, 0x0000000080000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ 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0x0000000000000000ULL, 0x0000000000020000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_THRD_PRIO_0_CYC ] = { 0x0000000000000000ULL, 0x0000000000004000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { 0x0000000000000000ULL, 0x0000000000040000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU1_REJECT_DERAT_MPRED ] = { 0x0000000000000000ULL, 0x0000000000000080ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_VMX1_LD_WRBACK ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000200000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DATA_FROM_RL2L3_SHR_CYC ] = { 0x0000000000001000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_IERAT_MISS_16M ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000100ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_DATA_FROM_MEM_DP ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000004000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LARX_L1HIT ] = { 0x0010000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_L2_ST_MISS_DATA ] = { 0x0000000000000000ULL, 0x0000002000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FPU_ST_FOLDED ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000004ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_DATA_FROM_L35_SHR ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000002000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DPU_HELD_MULT_GPR ] = { 0x0000110000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FPU0_1FLOP ] = { 0x0000000000000000ULL, 0x0080000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_IERAT_MISS_16G ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000100ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_IC_PREF_WRITE ] = { 0x0004000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC ] = { 0x0000000000000000ULL, 0x0000000000020000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FPU0_FIN ] = { 0x0000000000000000ULL, 0x0200000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DATA_FROM_L2_CYC ] = { 0x0000000000040000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DERAT_REF_16G ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000080ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_BR_PRED ] = { 0x0000000000000054ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_VMX1_LD_ISSUED ] = { 0x0000000000000000ULL, 0x0000000000600000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_L2SB_CASTOUT_MOD ] = { 0x0000000000000000ULL, 0x0000200000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_INST_FROM_DMEM ] = { 0x0000000002000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DATA_FROM_L35_SHR_CYC ] = { 0x0000000000200000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU0_NCLD ] = { 0x0000000000000000ULL, 0x0000000000000200ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FAB_RETRY_NODE_PUMP ] = { 0x0000000000000000ULL, 0x0000000010000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_VMX0_INST_ISSUED ] = { 0x0000000000000000ULL, 0x0000000000200000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DATA_FROM_L25_MOD ] = { 0x0000000000020200ULL, 0x0000000000000000ULL, 0x8000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DPU_HELD_ITLB_ISLB ] = { 0x0000008000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { 0x0000000000000000ULL, 0x0000000000000400ULL, 0x0040000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_THRD_CONC_RUN_INST ] = { 0x0020000000000002ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_PTEG_FROM_L2 ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000004000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_PURR ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000008ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DERAT_MISS_64K ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000040ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_PMC2_REWIND ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_INST_FROM_L2 ] = { 0x0000000004400000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_INST_DISP ] = { 0x0000000000140001ULL, 0x0000000000001000ULL, 0x2000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DATA_FROM_L25_SHR ] = { 0x0000000000000200ULL, 0x0000000000000000ULL, 0x8000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_L1_DCACHE_RELOAD_VALID ] = { 0x0000000000040000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU1_REJECT_UST ] = { 0x4000000000000000ULL, 0x0000000000000002ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FAB_ADDR_COLLISION ] = { 0x0000000000000000ULL, 0x0000000020000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_FXU_FIN ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000200000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU0_REJECT_UST ] = { 0x4000000000000000ULL, 0x0000000000000002ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_PMC4_OVERFLOW ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_PTEG_FROM_L3 ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000020000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_INST_FROM_L2MISS ] = { 0x0000000004400000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_L2SB_ST_HIT ] = { 0x0000000000000000ULL, 0x0001000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DPU_WT_IC_MISS_COUNT ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0080040000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_DATA_FROM_DL2L3_SHR ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000400ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_PTEG_FROM_L35_MOD ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000010000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FPU1_FPSCR ] = { 0x0000000000000000ULL, 0x2000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU_REJECT_UST ] = { 0x4000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU0_DERAT_MISS ] = { 0x0000000000000000ULL, 0x00000000000000a0ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_PTEG_FROM_MEM_DP ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000020000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_DATA_FROM_L2 ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000800ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FPU0_FSQRT_FDIV ] = { 0x0000000000000000ULL, 0x0080000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DPU_HELD_FXU_SOPS ] = { 0x0000040000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_FPU0_FIN ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000800100000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_L2SB_LD_MISS_DATA ] = { 0x0000000000000000ULL, 0x0000020000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU_SRQ_EMPTY_CYC ] = { 0x0000000000000000ULL, 0x0000000000000001ULL, 0x0010000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_1PLUS_PPC_DISP ] = { 0x0000000000100000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_VMX_ST_ISSUED ] = { 0x0000000000000000ULL, 0x0000000001800000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DATA_FROM_L2MISS ] = { 0x0000000000000080ULL, 0x0000100000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU0_REJECT_ULD ] = { 0x8000000000000000ULL, 0x0000000000000002ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_SUSPENDED ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000010ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DFU_ADD_SHIFTED_BOTH ] = { 0x0000000000000000ULL, 0x0000000002000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU_REJECT_NO_SCRATCH ] = { 0x2000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_STCX_FAIL ] = { 0x0018000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FPU1_DENORM ] = { 0x0000000000000000ULL, 0x1000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_GCT_NOSLOT_COUNT ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0008010000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DATA_FROM_DL2L3_SHR_CYC ] = { 0x0000000000008000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DATA_FROM_L21 ] = { 0x0000000000080080ULL, 0x0000000000000000ULL, 0x8000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FPU_1FLOP ] = { 0x0000000000000000ULL, 0x8000000000000000ULL, 0x0400000000000000ULL, 0x0000000000000002ULL }, [ POWER6_PME_PM_LSU1_REJECT ] = { 0x0000000000000000ULL, 0x0000000000000044ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_IC_REQ ] = { 0x0004000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_DFU_FIN ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000200000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_NOT_LLA_CYC ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_INST_FROM_L1 ] = { 0x0000000000000000ULL, 0x0000001000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_VMX_COMPLEX_ISSUED ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000100000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_BRU_FIN ] = { 0x0000000000000040ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU1_REJECT_EXTERN ] = { 0x0000000000000000ULL, 0x0000000000000008ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DATA_FROM_L21_CYC ] = { 0x0000000000080000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_GXI_CYC_BUSY ] = { 0x0000000000000000ULL, 0x0000000e00000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_LD_MISS_L1 ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000200ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_L1_WRITE_CYC ] = { 0x0000000000000000ULL, 0x0000001000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LLA_CYC ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000080000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_DATA_FROM_L2MISS ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000001000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_GCT_FULL_COUNT ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000410000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MEM_DP_RQ_LOC_GLOB ] = { 0x0000000000000000ULL, 0x0000000040000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DATA_FROM_RL2L3_SHR ] = { 0x0000000000000400ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_LSU_REJECT_UST ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000010000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_VMX_PERMUTE_ISSUED ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000100000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_PTEG_FROM_L21 ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000008000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = { 0x0020000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_BR_MPRED ] = { 0x0000000000000040ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LD_REQ_L2 ] = { 0x0000000000000000ULL, 0x0000010000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_FLUSH_ASYNC ] = { 0x0002000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_HV_CYC ] = { 0x0040000000000000ULL, 0x0000000000000000ULL, 0x0001000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU1_DERAT_MISS ] = { 0x0000000000000000ULL, 0x00000000000000a0ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_DPU_HELD_SMT ] = { 0x0000001000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_LSU_FIN ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000001000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_DATA_FROM_RL2L3_SHR ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x000000000000c000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_LSU0_REJECT_STQ_FULL ] = { 0x0000000000000000ULL, 0x0000000000000040ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_MRK_DERAT_REF_4K ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000001000000000ULL, 0x0000000000000010ULL }, [ POWER6_PME_PM_FPU_ISSUE_STALL_FPR ] = { 0x0000000000000000ULL, 0x0040000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_IFU_FIN ] = { 0x0000000000000000ULL, 0x0000000000080000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER6_PME_PM_GXO_CYC_BUSY ] = { 0x0000000000000000ULL, 0x0000000e00000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL } }; static const pme_power_entry_t power6_pe[] = { [ POWER6_PME_PM_LSU_REJECT_STQ_FULL ] = { .pme_name = "PM_LSU_REJECT_STQ_FULL", .pme_code = 0x1a0030, .pme_short_desc = "LSU reject due to store queue full", .pme_long_desc = "LSU reject due to store queue full", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_STQ_FULL], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_STQ_FULL] }, [ POWER6_PME_PM_DPU_HELD_FXU_MULTI ] = { .pme_name = "PM_DPU_HELD_FXU_MULTI", .pme_code = 0x210a6, .pme_short_desc = "DISP unit held due to FXU multicycle", .pme_long_desc = "DISP unit held due to FXU multicycle", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_FXU_MULTI], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_FXU_MULTI] }, [ POWER6_PME_PM_VMX1_STALL ] = { .pme_name = "PM_VMX1_STALL", .pme_code = 0xb008c, .pme_short_desc = "VMX1 stall", .pme_long_desc = "VMX1 stall", .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX1_STALL], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX1_STALL] }, [ POWER6_PME_PM_PMC2_SAVED ] = { .pme_name = "PM_PMC2_SAVED", .pme_code = 0x100022, .pme_short_desc = "PMC2 rewind value saved", .pme_long_desc = "PMC2 rewind value saved", .pme_event_ids = power6_event_ids[POWER6_PME_PM_PMC2_SAVED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PMC2_SAVED] }, [ POWER6_PME_PM_L2SB_IC_INV ] = { .pme_name = "PM_L2SB_IC_INV", .pme_code = 0x5068c, .pme_short_desc = "L2 slice B I cache invalidate", .pme_long_desc = "L2 slice B I cache invalidate", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SB_IC_INV], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SB_IC_INV] }, [ POWER6_PME_PM_IERAT_MISS_64K ] = { .pme_name = "PM_IERAT_MISS_64K", .pme_code = 0x392076, .pme_short_desc = "IERAT misses for 64K page", .pme_long_desc = "IERAT misses for 64K page", .pme_event_ids = power6_event_ids[POWER6_PME_PM_IERAT_MISS_64K], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IERAT_MISS_64K] }, [ POWER6_PME_PM_THRD_PRIO_DIFF_3or4_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_3or4_CYC", .pme_code = 0x323040, .pme_short_desc = "Cycles thread priority difference is 3 or 4", .pme_long_desc = "Cycles thread priority difference is 3 or 4", .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_DIFF_3or4_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_DIFF_3or4_CYC] }, [ POWER6_PME_PM_LD_REF_L1_BOTH ] = { .pme_name = "PM_LD_REF_L1_BOTH", .pme_code = 0x180036, .pme_short_desc = "Both units L1 D cache load reference", .pme_long_desc = "Both units L1 D cache load reference", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LD_REF_L1_BOTH], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LD_REF_L1_BOTH] }, [ POWER6_PME_PM_FPU1_FCONV ] = { .pme_name = "PM_FPU1_FCONV", .pme_code = 0xd10a8, .pme_short_desc = "FPU1 executed FCONV instruction", .pme_long_desc = "FPU1 executed FCONV instruction", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_FCONV], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_FCONV] }, [ POWER6_PME_PM_IBUF_FULL_COUNT ] = { .pme_name = "PM_IBUF_FULL_COUNT", .pme_code = 0x40085, .pme_short_desc = "Periods instruction buffer full", .pme_long_desc = "Periods instruction buffer full", .pme_event_ids = power6_event_ids[POWER6_PME_PM_IBUF_FULL_COUNT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IBUF_FULL_COUNT] }, [ POWER6_PME_PM_MRK_LSU_DERAT_MISS ] = { .pme_name = "PM_MRK_LSU_DERAT_MISS", .pme_code = 0x400012, .pme_short_desc = "Marked DERAT miss", .pme_long_desc = "Marked DERAT miss", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_LSU_DERAT_MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_LSU_DERAT_MISS] }, [ POWER6_PME_PM_MRK_ST_CMPL ] = { .pme_name = "PM_MRK_ST_CMPL", .pme_code = 0x100006, .pme_short_desc = "Marked store instruction completed", .pme_long_desc = "A sampled store has completed (data home)", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_ST_CMPL], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_ST_CMPL] }, [ POWER6_PME_PM_L2_CASTOUT_MOD ] = { .pme_name = "PM_L2_CASTOUT_MOD", .pme_code = 0x150630, .pme_short_desc = "L2 castouts - Modified (M", .pme_long_desc = " Mu", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2_CASTOUT_MOD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2_CASTOUT_MOD] }, [ POWER6_PME_PM_FPU1_ST_FOLDED ] = { .pme_name = "PM_FPU1_ST_FOLDED", .pme_code = 0xd10ac, .pme_short_desc = "FPU1 folded store", .pme_long_desc = "FPU1 folded store", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_ST_FOLDED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_ST_FOLDED] }, [ POWER6_PME_PM_MRK_INST_TIMEO ] = { .pme_name = "PM_MRK_INST_TIMEO", .pme_code = 0x40003e, .pme_short_desc = "Marked Instruction finish timeout ", .pme_long_desc = "Marked Instruction finish timeout ", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_INST_TIMEO], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_INST_TIMEO] }, [ POWER6_PME_PM_DPU_WT ] = { .pme_name = "PM_DPU_WT", .pme_code = 0x300004, .pme_short_desc = "Cycles DISP unit is stalled waiting for instructions", .pme_long_desc = "Cycles DISP unit is stalled waiting for instructions", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_WT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_WT] }, [ POWER6_PME_PM_DPU_HELD_RESTART ] = { .pme_name = "PM_DPU_HELD_RESTART", .pme_code = 0x30086, .pme_short_desc = "DISP unit held after restart coming", .pme_long_desc = "DISP unit held after restart coming", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_RESTART], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_RESTART] }, [ POWER6_PME_PM_IERAT_MISS ] = { .pme_name = "PM_IERAT_MISS", .pme_code = 0x420ce, .pme_short_desc = "IERAT miss count", .pme_long_desc = "IERAT miss count", .pme_event_ids = power6_event_ids[POWER6_PME_PM_IERAT_MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IERAT_MISS] }, [ POWER6_PME_PM_FPU_SINGLE ] = { .pme_name = "PM_FPU_SINGLE", .pme_code = 0x4c1030, .pme_short_desc = "FPU executed single precision instruction", .pme_long_desc = "FPU is executing single precision instruction. Combined Unit 0 + Unit 1", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_SINGLE], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_SINGLE] }, [ POWER6_PME_PM_MRK_PTEG_FROM_LMEM ] = { .pme_name = "PM_MRK_PTEG_FROM_LMEM", .pme_code = 0x412042, .pme_short_desc = "Marked PTEG loaded from local memory", .pme_long_desc = "Marked PTEG loaded from local memory", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_LMEM], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_LMEM] }, [ POWER6_PME_PM_HV_COUNT ] = { .pme_name = "PM_HV_COUNT", .pme_code = 0x200017, .pme_short_desc = "Hypervisor Periods", .pme_long_desc = "Periods when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0)", .pme_event_ids = power6_event_ids[POWER6_PME_PM_HV_COUNT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_HV_COUNT] }, [ POWER6_PME_PM_L2SA_ST_HIT ] = { .pme_name = "PM_L2SA_ST_HIT", .pme_code = 0x50786, .pme_short_desc = "L2 slice A store hits", .pme_long_desc = "A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A,B, and C.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SA_ST_HIT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SA_ST_HIT] }, [ POWER6_PME_PM_L2_LD_MISS_INST ] = { .pme_name = "PM_L2_LD_MISS_INST", .pme_code = 0x250530, .pme_short_desc = "L2 instruction load misses", .pme_long_desc = "L2 instruction load misses", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2_LD_MISS_INST], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2_LD_MISS_INST] }, [ POWER6_PME_PM_EXT_INT ] = { .pme_name = "PM_EXT_INT", .pme_code = 0x2000f8, .pme_short_desc = "External interrupts", .pme_long_desc = "An external interrupt occurred", .pme_event_ids = power6_event_ids[POWER6_PME_PM_EXT_INT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_EXT_INT] }, [ POWER6_PME_PM_LSU1_LDF ] = { .pme_name = "PM_LSU1_LDF", .pme_code = 0x8008c, .pme_short_desc = "LSU1 executed Floating Point load instruction", .pme_long_desc = "A floating point load was executed from LSU unit 1", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU1_LDF], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU1_LDF] }, [ POWER6_PME_PM_FAB_CMD_ISSUED ] = { .pme_name = "PM_FAB_CMD_ISSUED", .pme_code = 0x150130, .pme_short_desc = "Fabric command issued", .pme_long_desc = "Fabric command issued", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FAB_CMD_ISSUED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FAB_CMD_ISSUED] }, [ POWER6_PME_PM_PTEG_FROM_L21 ] = { .pme_name = "PM_PTEG_FROM_L21", .pme_code = 0x213048, .pme_short_desc = "PTEG loaded from private L2 other core", .pme_long_desc = "PTEG loaded from private L2 other core", .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_L21], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_L21] }, [ POWER6_PME_PM_L2SA_MISS ] = { .pme_name = "PM_L2SA_MISS", .pme_code = 0x50584, .pme_short_desc = "L2 slice A misses", .pme_long_desc = "L2 slice A misses", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SA_MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SA_MISS] }, [ POWER6_PME_PM_PTEG_FROM_RL2L3_MOD ] = { .pme_name = "PM_PTEG_FROM_RL2L3_MOD", .pme_code = 0x11304c, .pme_short_desc = "PTEG loaded from remote L2 or L3 modified", .pme_long_desc = "PTEG loaded from remote L2 or L3 modified", .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_RL2L3_MOD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_RL2L3_MOD] }, [ POWER6_PME_PM_DPU_WT_COUNT ] = { .pme_name = "PM_DPU_WT_COUNT", .pme_code = 0x300005, .pme_short_desc = "Periods DISP unit is stalled waiting for instructions", .pme_long_desc = "Periods DISP unit is stalled waiting for instructions", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_WT_COUNT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_WT_COUNT] }, [ POWER6_PME_PM_MRK_PTEG_FROM_L25_MOD ] = { .pme_name = "PM_MRK_PTEG_FROM_L25_MOD", .pme_code = 0x312046, .pme_short_desc = "Marked PTEG loaded from L2.5 modified", .pme_long_desc = "Marked PTEG loaded from L2.5 modified", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_L25_MOD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_L25_MOD] }, [ POWER6_PME_PM_LD_HIT_L2 ] = { .pme_name = "PM_LD_HIT_L2", .pme_code = 0x250730, .pme_short_desc = "L2 D cache load hits", .pme_long_desc = "L2 D cache load hits", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LD_HIT_L2], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LD_HIT_L2] }, [ POWER6_PME_PM_PTEG_FROM_DL2L3_SHR ] = { .pme_name = "PM_PTEG_FROM_DL2L3_SHR", .pme_code = 0x31304c, .pme_short_desc = "PTEG loaded from distant L2 or L3 shared", .pme_long_desc = "PTEG loaded from distant L2 or L3 shared", .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_DL2L3_SHR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_DL2L3_SHR] }, [ POWER6_PME_PM_MEM_DP_RQ_GLOB_LOC ] = { .pme_name = "PM_MEM_DP_RQ_GLOB_LOC", .pme_code = 0x150230, .pme_short_desc = "Memory read queue marking cache line double pump state from global to local", .pme_long_desc = "Memory read queue marking cache line double pump state from global to local", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MEM_DP_RQ_GLOB_LOC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MEM_DP_RQ_GLOB_LOC] }, [ POWER6_PME_PM_L3SA_MISS ] = { .pme_name = "PM_L3SA_MISS", .pme_code = 0x50084, .pme_short_desc = "L3 slice A misses", .pme_long_desc = "L3 slice A misses", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L3SA_MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L3SA_MISS] }, [ POWER6_PME_PM_NO_ITAG_COUNT ] = { .pme_name = "PM_NO_ITAG_COUNT", .pme_code = 0x40089, .pme_short_desc = "Periods no ITAG available", .pme_long_desc = "Periods no ITAG available", .pme_event_ids = power6_event_ids[POWER6_PME_PM_NO_ITAG_COUNT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_NO_ITAG_COUNT] }, [ POWER6_PME_PM_DSLB_MISS ] = { .pme_name = "PM_DSLB_MISS", .pme_code = 0x830e8, .pme_short_desc = "Data SLB misses", .pme_long_desc = "A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DSLB_MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DSLB_MISS] }, [ POWER6_PME_PM_LSU_FLUSH_ALIGN ] = { .pme_name = "PM_LSU_FLUSH_ALIGN", .pme_code = 0x220cc, .pme_short_desc = "Flush caused by alignement exception", .pme_long_desc = "Flush caused by alignement exception", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_FLUSH_ALIGN], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_FLUSH_ALIGN] }, [ POWER6_PME_PM_DPU_HELD_FPU_CR ] = { .pme_name = "PM_DPU_HELD_FPU_CR", .pme_code = 0x210a0, .pme_short_desc = "DISP unit held due to FPU updating CR", .pme_long_desc = "DISP unit held due to FPU updating CR", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_FPU_CR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_FPU_CR] }, [ POWER6_PME_PM_PTEG_FROM_L2MISS ] = { .pme_name = "PM_PTEG_FROM_L2MISS", .pme_code = 0x113028, .pme_short_desc = "PTEG loaded from L2 miss", .pme_long_desc = "PTEG loaded from L2 miss", .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_L2MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_L2MISS] }, [ POWER6_PME_PM_MRK_DATA_FROM_DMEM ] = { .pme_name = "PM_MRK_DATA_FROM_DMEM", .pme_code = 0x20304a, .pme_short_desc = "Marked data loaded from distant memory", .pme_long_desc = "Marked data loaded from distant memory", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_DMEM], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_DMEM] }, [ POWER6_PME_PM_PTEG_FROM_LMEM ] = { .pme_name = "PM_PTEG_FROM_LMEM", .pme_code = 0x41304a, .pme_short_desc = "PTEG loaded from local memory", .pme_long_desc = "PTEG loaded from local memory", .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_LMEM], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_LMEM] }, [ POWER6_PME_PM_MRK_DERAT_REF_64K ] = { .pme_name = "PM_MRK_DERAT_REF_64K", .pme_code = 0x182044, .pme_short_desc = "Marked DERAT reference for 64K page", .pme_long_desc = "Marked DERAT reference for 64K page", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DERAT_REF_64K], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DERAT_REF_64K] }, [ POWER6_PME_PM_L2SA_LD_REQ_INST ] = { .pme_name = "PM_L2SA_LD_REQ_INST", .pme_code = 0x50580, .pme_short_desc = "L2 slice A instruction load requests", .pme_long_desc = "L2 slice A instruction load requests", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SA_LD_REQ_INST], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SA_LD_REQ_INST] }, [ POWER6_PME_PM_MRK_DERAT_MISS_16M ] = { .pme_name = "PM_MRK_DERAT_MISS_16M", .pme_code = 0x392044, .pme_short_desc = "Marked DERAT misses for 16M page", .pme_long_desc = "A marked data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DERAT_MISS_16M], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DERAT_MISS_16M] }, [ POWER6_PME_PM_DATA_FROM_DL2L3_MOD ] = { .pme_name = "PM_DATA_FROM_DL2L3_MOD", .pme_code = 0x40005c, .pme_short_desc = "Data loaded from distant L2 or L3 modified", .pme_long_desc = "Data loaded from distant L2 or L3 modified", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_DL2L3_MOD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_DL2L3_MOD] }, [ POWER6_PME_PM_FPU0_FXMULT ] = { .pme_name = "PM_FPU0_FXMULT", .pme_code = 0xd0086, .pme_short_desc = "FPU0 executed fixed point multiplication", .pme_long_desc = "FPU0 executed fixed point multiplication", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_FXMULT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_FXMULT] }, [ POWER6_PME_PM_L3SB_MISS ] = { .pme_name = "PM_L3SB_MISS", .pme_code = 0x5008c, .pme_short_desc = "L3 slice B misses", .pme_long_desc = "L3 slice B misses", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L3SB_MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L3SB_MISS] }, [ POWER6_PME_PM_STCX_CANCEL ] = { .pme_name = "PM_STCX_CANCEL", .pme_code = 0x830ec, .pme_short_desc = "stcx cancel by core", .pme_long_desc = "stcx cancel by core", .pme_event_ids = power6_event_ids[POWER6_PME_PM_STCX_CANCEL], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_STCX_CANCEL] }, [ POWER6_PME_PM_L2SA_LD_MISS_DATA ] = { .pme_name = "PM_L2SA_LD_MISS_DATA", .pme_code = 0x50482, .pme_short_desc = "L2 slice A data load misses", .pme_long_desc = "L2 slice A data load misses", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SA_LD_MISS_DATA], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SA_LD_MISS_DATA] }, [ POWER6_PME_PM_IC_INV_L2 ] = { .pme_name = "PM_IC_INV_L2", .pme_code = 0x250632, .pme_short_desc = "L1 I cache entries invalidated from L2", .pme_long_desc = "L1 I cache entries invalidated from L2", .pme_event_ids = power6_event_ids[POWER6_PME_PM_IC_INV_L2], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IC_INV_L2] }, [ POWER6_PME_PM_DPU_HELD ] = { .pme_name = "PM_DPU_HELD", .pme_code = 0x200004, .pme_short_desc = "DISP unit held", .pme_long_desc = "DISP unit held", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD] }, [ POWER6_PME_PM_PMC1_OVERFLOW ] = { .pme_name = "PM_PMC1_OVERFLOW", .pme_code = 0x200014, .pme_short_desc = "PMC1 Overflow", .pme_long_desc = "PMC1 Overflow", .pme_event_ids = power6_event_ids[POWER6_PME_PM_PMC1_OVERFLOW], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PMC1_OVERFLOW] }, [ POWER6_PME_PM_THRD_PRIO_6_CYC ] = { .pme_name = "PM_THRD_PRIO_6_CYC", .pme_code = 0x222046, .pme_short_desc = "Cycles thread running at priority level 6", .pme_long_desc = "Cycles thread running at priority level 6", .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_6_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_6_CYC] }, [ POWER6_PME_PM_MRK_PTEG_FROM_L3MISS ] = { .pme_name = "PM_MRK_PTEG_FROM_L3MISS", .pme_code = 0x312054, .pme_short_desc = "Marked PTEG loaded from L3 miss", .pme_long_desc = "Marked PTEG loaded from L3 miss", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_L3MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_L3MISS] }, [ POWER6_PME_PM_MRK_LSU0_REJECT_UST ] = { .pme_name = "PM_MRK_LSU0_REJECT_UST", .pme_code = 0x930e2, .pme_short_desc = "LSU0 marked unaligned store reject", .pme_long_desc = "LSU0 marked unaligned store reject", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_LSU0_REJECT_UST], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_LSU0_REJECT_UST] }, [ POWER6_PME_PM_MRK_INST_DISP ] = { .pme_name = "PM_MRK_INST_DISP", .pme_code = 0x10001a, .pme_short_desc = "Marked instruction dispatched", .pme_long_desc = "Marked instruction dispatched", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_INST_DISP], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_INST_DISP] }, [ POWER6_PME_PM_LARX ] = { .pme_name = "PM_LARX", .pme_code = 0x830ea, .pme_short_desc = "Larx executed", .pme_long_desc = "Larx executed", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LARX], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LARX] }, [ POWER6_PME_PM_INST_CMPL ] = { .pme_name = "PM_INST_CMPL", .pme_code = 0x2, .pme_short_desc = "Instructions completed", .pme_long_desc = "Number of PPC instructions completed. ", .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_CMPL], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_CMPL] }, [ POWER6_PME_PM_FXU_IDLE ] = { .pme_name = "PM_FXU_IDLE", .pme_code = 0x100050, .pme_short_desc = "FXU idle", .pme_long_desc = "FXU0 and FXU1 are both idle", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FXU_IDLE], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FXU_IDLE] }, [ POWER6_PME_PM_MRK_DATA_FROM_DL2L3_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_DL2L3_MOD", .pme_code = 0x40304c, .pme_short_desc = "Marked data loaded from distant L2 or L3 modified", .pme_long_desc = "Marked data loaded from distant L2 or L3 modified", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_DL2L3_MOD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_DL2L3_MOD] }, [ POWER6_PME_PM_L2_LD_REQ_DATA ] = { .pme_name = "PM_L2_LD_REQ_DATA", .pme_code = 0x150430, .pme_short_desc = "L2 data load requests", .pme_long_desc = "L2 data load requests", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2_LD_REQ_DATA], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2_LD_REQ_DATA] }, [ POWER6_PME_PM_LSU_DERAT_MISS_CYC ] = { .pme_name = "PM_LSU_DERAT_MISS_CYC", .pme_code = 0x1000fc, .pme_short_desc = "DERAT miss latency", .pme_long_desc = "DERAT miss latency", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_DERAT_MISS_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_DERAT_MISS_CYC] }, [ POWER6_PME_PM_DPU_HELD_POWER_COUNT ] = { .pme_name = "PM_DPU_HELD_POWER_COUNT", .pme_code = 0x20003d, .pme_short_desc = "Periods DISP unit held due to Power Management", .pme_long_desc = "Periods DISP unit held due to Power Management", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_POWER_COUNT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_POWER_COUNT] }, [ POWER6_PME_PM_INST_FROM_RL2L3_MOD ] = { .pme_name = "PM_INST_FROM_RL2L3_MOD", .pme_code = 0x142044, .pme_short_desc = "Instruction fetched from remote L2 or L3 modified", .pme_long_desc = "Instruction fetched from remote L2 or L3 modified", .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_RL2L3_MOD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_RL2L3_MOD] }, [ POWER6_PME_PM_DATA_FROM_DMEM_CYC ] = { .pme_name = "PM_DATA_FROM_DMEM_CYC", .pme_code = 0x20002e, .pme_short_desc = "Load latency from distant memory", .pme_long_desc = "Load latency from distant memory", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_DMEM_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_DMEM_CYC] }, [ POWER6_PME_PM_DATA_FROM_DMEM ] = { .pme_name = "PM_DATA_FROM_DMEM", .pme_code = 0x20005e, .pme_short_desc = "Data loaded from distant memory", .pme_long_desc = "Data loaded from distant memory", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_DMEM], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_DMEM] }, [ POWER6_PME_PM_LSU_REJECT_PARTIAL_SECTOR ] = { .pme_name = "PM_LSU_REJECT_PARTIAL_SECTOR", .pme_code = 0x1a0032, .pme_short_desc = "LSU reject due to partial sector valid", .pme_long_desc = "LSU reject due to partial sector valid", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_PARTIAL_SECTOR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_PARTIAL_SECTOR] }, [ POWER6_PME_PM_LSU_REJECT_DERAT_MPRED ] = { .pme_name = "PM_LSU_REJECT_DERAT_MPRED", .pme_code = 0x2a0030, .pme_short_desc = "LSU reject due to mispredicted DERAT", .pme_long_desc = "LSU reject due to mispredicted DERAT", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_DERAT_MPRED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_DERAT_MPRED] }, [ POWER6_PME_PM_LSU1_REJECT_ULD ] = { .pme_name = "PM_LSU1_REJECT_ULD", .pme_code = 0x90088, .pme_short_desc = "LSU1 unaligned load reject", .pme_long_desc = "LSU1 unaligned load reject", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU1_REJECT_ULD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU1_REJECT_ULD] }, [ POWER6_PME_PM_DATA_FROM_L3_CYC ] = { .pme_name = "PM_DATA_FROM_L3_CYC", .pme_code = 0x200022, .pme_short_desc = "Load latency from L3", .pme_long_desc = "Load latency from L3", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L3_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L3_CYC] }, [ POWER6_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { .pme_name = "PM_FXU1_BUSY_FXU0_IDLE", .pme_code = 0x400050, .pme_short_desc = "FXU1 busy FXU0 idle", .pme_long_desc = "FXU0 was idle while FXU1 was busy", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FXU1_BUSY_FXU0_IDLE], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FXU1_BUSY_FXU0_IDLE] }, [ POWER6_PME_PM_INST_FROM_MEM_DP ] = { .pme_name = "PM_INST_FROM_MEM_DP", .pme_code = 0x142042, .pme_short_desc = "Instruction fetched from double pump memory", .pme_long_desc = "Instruction fetched from double pump memory", .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_MEM_DP], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_MEM_DP] }, [ POWER6_PME_PM_LSU_FLUSH_DSI ] = { .pme_name = "PM_LSU_FLUSH_DSI", .pme_code = 0x220ce, .pme_short_desc = "Flush caused by DSI", .pme_long_desc = "Flush caused by DSI", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_FLUSH_DSI], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_FLUSH_DSI] }, [ POWER6_PME_PM_MRK_DERAT_REF_16G ] = { .pme_name = "PM_MRK_DERAT_REF_16G", .pme_code = 0x482044, .pme_short_desc = "Marked DERAT reference for 16G page", .pme_long_desc = "Marked DERAT reference for 16G page", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DERAT_REF_16G], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DERAT_REF_16G] }, [ POWER6_PME_PM_LSU_LDF_BOTH ] = { .pme_name = "PM_LSU_LDF_BOTH", .pme_code = 0x180038, .pme_short_desc = "Both LSU units executed Floating Point load instruction", .pme_long_desc = "Both LSU units executed Floating Point load instruction", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_LDF_BOTH], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_LDF_BOTH] }, [ POWER6_PME_PM_FPU1_1FLOP ] = { .pme_name = "PM_FPU1_1FLOP", .pme_code = 0xc0088, .pme_short_desc = "FPU1 executed add", .pme_long_desc = " mult", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_1FLOP], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_1FLOP] }, [ POWER6_PME_PM_DATA_FROM_RMEM_CYC ] = { .pme_name = "PM_DATA_FROM_RMEM_CYC", .pme_code = 0x40002c, .pme_short_desc = "Load latency from remote memory", .pme_long_desc = "Load latency from remote memory", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_RMEM_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_RMEM_CYC] }, [ POWER6_PME_PM_INST_PTEG_SECONDARY ] = { .pme_name = "PM_INST_PTEG_SECONDARY", .pme_code = 0x910ac, .pme_short_desc = "Instruction table walk matched in secondary PTEG", .pme_long_desc = "Instruction table walk matched in secondary PTEG", .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_PTEG_SECONDARY], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_PTEG_SECONDARY] }, [ POWER6_PME_PM_L1_ICACHE_MISS ] = { .pme_name = "PM_L1_ICACHE_MISS", .pme_code = 0x100056, .pme_short_desc = "L1 I cache miss count", .pme_long_desc = "L1 I cache miss count", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L1_ICACHE_MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L1_ICACHE_MISS] }, [ POWER6_PME_PM_INST_DISP_LLA ] = { .pme_name = "PM_INST_DISP_LLA", .pme_code = 0x310a2, .pme_short_desc = "Instruction dispatched under load look ahead", .pme_long_desc = "Instruction dispatched under load look ahead", .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_DISP_LLA], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_DISP_LLA] }, [ POWER6_PME_PM_THRD_BOTH_RUN_CYC ] = { .pme_name = "PM_THRD_BOTH_RUN_CYC", .pme_code = 0x400004, .pme_short_desc = "Both threads in run cycles", .pme_long_desc = "Both threads in run cycles", .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_BOTH_RUN_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_BOTH_RUN_CYC] }, [ POWER6_PME_PM_LSU_ST_CHAINED ] = { .pme_name = "PM_LSU_ST_CHAINED", .pme_code = 0x820ce, .pme_short_desc = "number of chained stores", .pme_long_desc = "number of chained stores", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_ST_CHAINED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_ST_CHAINED] }, [ POWER6_PME_PM_FPU1_FXDIV ] = { .pme_name = "PM_FPU1_FXDIV", .pme_code = 0xc10a8, .pme_short_desc = "FPU1 executed fixed point division", .pme_long_desc = "FPU1 executed fixed point division", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_FXDIV], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_FXDIV] }, [ POWER6_PME_PM_FREQ_UP ] = { .pme_name = "PM_FREQ_UP", .pme_code = 0x40003c, .pme_short_desc = "Frequency is being slewed up due to Power Management", .pme_long_desc = "Frequency is being slewed up due to Power Management", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FREQ_UP], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FREQ_UP] }, [ POWER6_PME_PM_FAB_RETRY_SYS_PUMP ] = { .pme_name = "PM_FAB_RETRY_SYS_PUMP", .pme_code = 0x50182, .pme_short_desc = "Retry of a system pump", .pme_long_desc = " locally mastered ", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FAB_RETRY_SYS_PUMP], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FAB_RETRY_SYS_PUMP] }, [ POWER6_PME_PM_DATA_FROM_LMEM ] = { .pme_name = "PM_DATA_FROM_LMEM", .pme_code = 0x40005e, .pme_short_desc = "Data loaded from local memory", .pme_long_desc = "Data loaded from local memory", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_LMEM], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_LMEM] }, [ POWER6_PME_PM_PMC3_OVERFLOW ] = { .pme_name = "PM_PMC3_OVERFLOW", .pme_code = 0x400014, .pme_short_desc = "PMC3 Overflow", .pme_long_desc = "PMC3 Overflow", .pme_event_ids = power6_event_ids[POWER6_PME_PM_PMC3_OVERFLOW], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PMC3_OVERFLOW] }, [ POWER6_PME_PM_LSU0_REJECT_SET_MPRED ] = { .pme_name = "PM_LSU0_REJECT_SET_MPRED", .pme_code = 0xa0084, .pme_short_desc = "LSU0 reject due to mispredicted set", .pme_long_desc = "LSU0 reject due to mispredicted set", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_REJECT_SET_MPRED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_REJECT_SET_MPRED] }, [ POWER6_PME_PM_LSU0_REJECT_DERAT_MPRED ] = { .pme_name = "PM_LSU0_REJECT_DERAT_MPRED", .pme_code = 0xa0082, .pme_short_desc = "LSU0 reject due to mispredicted DERAT", .pme_long_desc = "LSU0 reject due to mispredicted DERAT", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_REJECT_DERAT_MPRED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_REJECT_DERAT_MPRED] }, [ POWER6_PME_PM_LSU1_REJECT_STQ_FULL ] = { .pme_name = "PM_LSU1_REJECT_STQ_FULL", .pme_code = 0xa0088, .pme_short_desc = "LSU1 reject due to store queue full", .pme_long_desc = "LSU1 reject due to store queue full", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU1_REJECT_STQ_FULL], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU1_REJECT_STQ_FULL] }, [ POWER6_PME_PM_MRK_BR_MPRED ] = { .pme_name = "PM_MRK_BR_MPRED", .pme_code = 0x300052, .pme_short_desc = "Marked branch mispredicted", .pme_long_desc = "Marked branch mispredicted", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_BR_MPRED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_BR_MPRED] }, [ POWER6_PME_PM_L2SA_ST_MISS ] = { .pme_name = "PM_L2SA_ST_MISS", .pme_code = 0x50486, .pme_short_desc = "L2 slice A store misses", .pme_long_desc = "L2 slice A store misses", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SA_ST_MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SA_ST_MISS] }, [ POWER6_PME_PM_LSU0_REJECT_EXTERN ] = { .pme_name = "PM_LSU0_REJECT_EXTERN", .pme_code = 0xa10a4, .pme_short_desc = "LSU0 external reject request ", .pme_long_desc = "LSU0 external reject request ", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_REJECT_EXTERN], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_REJECT_EXTERN] }, [ POWER6_PME_PM_MRK_BR_TAKEN ] = { .pme_name = "PM_MRK_BR_TAKEN", .pme_code = 0x100052, .pme_short_desc = "Marked branch taken", .pme_long_desc = "Marked branch taken", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_BR_TAKEN], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_BR_TAKEN] }, [ POWER6_PME_PM_ISLB_MISS ] = { .pme_name = "PM_ISLB_MISS", .pme_code = 0x830e0, .pme_short_desc = "Instruction SLB misses", .pme_long_desc = "A SLB miss for an instruction fetch as occurred", .pme_event_ids = power6_event_ids[POWER6_PME_PM_ISLB_MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_ISLB_MISS] }, [ POWER6_PME_PM_CYC ] = { .pme_name = "PM_CYC", .pme_code = 0x1e, .pme_short_desc = "Processor cycles", .pme_long_desc = "Processor cycles", .pme_event_ids = power6_event_ids[POWER6_PME_PM_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_CYC] }, [ POWER6_PME_PM_FPU_FXDIV ] = { .pme_name = "PM_FPU_FXDIV", .pme_code = 0x1c1034, .pme_short_desc = "FPU executed fixed point division", .pme_long_desc = "FPU executed fixed point division", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_FXDIV], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_FXDIV] }, [ POWER6_PME_PM_DPU_HELD_LLA_END ] = { .pme_name = "PM_DPU_HELD_LLA_END", .pme_code = 0x30084, .pme_short_desc = "DISP unit held due to load look ahead ended", .pme_long_desc = "DISP unit held due to load look ahead ended", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_LLA_END], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_LLA_END] }, [ POWER6_PME_PM_MEM0_DP_CL_WR_LOC ] = { .pme_name = "PM_MEM0_DP_CL_WR_LOC", .pme_code = 0x50286, .pme_short_desc = "cacheline write setting dp to local side 0", .pme_long_desc = "cacheline write setting dp to local side 0", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MEM0_DP_CL_WR_LOC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MEM0_DP_CL_WR_LOC] }, [ POWER6_PME_PM_MRK_LSU_REJECT_ULD ] = { .pme_name = "PM_MRK_LSU_REJECT_ULD", .pme_code = 0x193034, .pme_short_desc = "Marked unaligned load reject", .pme_long_desc = "Marked unaligned load reject", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_LSU_REJECT_ULD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_LSU_REJECT_ULD] }, [ POWER6_PME_PM_1PLUS_PPC_CMPL ] = { .pme_name = "PM_1PLUS_PPC_CMPL", .pme_code = 0x100004, .pme_short_desc = "One or more PPC instruction completed", .pme_long_desc = "A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_1PLUS_PPC_CMPL], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_1PLUS_PPC_CMPL] }, [ POWER6_PME_PM_PTEG_FROM_DMEM ] = { .pme_name = "PM_PTEG_FROM_DMEM", .pme_code = 0x21304a, .pme_short_desc = "PTEG loaded from distant memory", .pme_long_desc = "PTEG loaded from distant memory", .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_DMEM], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_DMEM] }, [ POWER6_PME_PM_DPU_WT_BR_MPRED_COUNT ] = { .pme_name = "PM_DPU_WT_BR_MPRED_COUNT", .pme_code = 0x40000d, .pme_short_desc = "Periods DISP unit is stalled due to branch misprediction", .pme_long_desc = "Periods DISP unit is stalled due to branch misprediction", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_WT_BR_MPRED_COUNT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_WT_BR_MPRED_COUNT] }, [ POWER6_PME_PM_GCT_FULL_CYC ] = { .pme_name = "PM_GCT_FULL_CYC", .pme_code = 0x40086, .pme_short_desc = "Cycles GCT full", .pme_long_desc = "The ISU sends a signal indicating the gct is full. ", .pme_event_ids = power6_event_ids[POWER6_PME_PM_GCT_FULL_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_GCT_FULL_CYC] }, [ POWER6_PME_PM_INST_FROM_L25_SHR ] = { .pme_name = "PM_INST_FROM_L25_SHR", .pme_code = 0x442046, .pme_short_desc = "Instruction fetched from L2.5 shared", .pme_long_desc = "Instruction fetched from L2.5 shared", .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_L25_SHR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_L25_SHR] }, [ POWER6_PME_PM_MRK_DERAT_MISS_4K ] = { .pme_name = "PM_MRK_DERAT_MISS_4K", .pme_code = 0x292044, .pme_short_desc = "Marked DERAT misses for 4K page", .pme_long_desc = "A marked data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DERAT_MISS_4K], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DERAT_MISS_4K] }, [ POWER6_PME_PM_DC_PREF_STREAM_ALLOC ] = { .pme_name = "PM_DC_PREF_STREAM_ALLOC", .pme_code = 0x810a2, .pme_short_desc = "D cache new prefetch stream allocated", .pme_long_desc = "A new Prefetch Stream was allocated", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DC_PREF_STREAM_ALLOC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DC_PREF_STREAM_ALLOC] }, [ POWER6_PME_PM_FPU1_FIN ] = { .pme_name = "PM_FPU1_FIN", .pme_code = 0xd0088, .pme_short_desc = "FPU1 produced a result", .pme_long_desc = "fp1 finished, produced a result. This only indicates finish, not completion. ", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_FIN], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_FIN] }, [ POWER6_PME_PM_BR_MPRED_TA ] = { .pme_name = "PM_BR_MPRED_TA", .pme_code = 0x410ac, .pme_short_desc = "Branch mispredictions due to target address", .pme_long_desc = "branch miss predict due to a target address prediction. This signal will be asserted each time the branch execution unit detects an incorrect target address prediction. This signal will be asserted after a valid branch execution unit issue and will cause a branch mispredict flush unless a flush is detected from an older instruction.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_BR_MPRED_TA], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_BR_MPRED_TA] }, [ POWER6_PME_PM_DPU_HELD_POWER ] = { .pme_name = "PM_DPU_HELD_POWER", .pme_code = 0x20003c, .pme_short_desc = "DISP unit held due to Power Management", .pme_long_desc = "DISP unit held due to Power Management", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_POWER], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_POWER] }, [ POWER6_PME_PM_RUN_INST_CMPL ] = { .pme_name = "PM_RUN_INST_CMPL", .pme_code = 0x500009, .pme_short_desc = "Run instructions completed", .pme_long_desc = "Number of run instructions completed. ", .pme_event_ids = power6_event_ids[POWER6_PME_PM_RUN_INST_CMPL], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_RUN_INST_CMPL] }, [ POWER6_PME_PM_GCT_EMPTY_CYC ] = { .pme_name = "PM_GCT_EMPTY_CYC", .pme_code = 0x1000f8, .pme_short_desc = "Cycles GCT empty", .pme_long_desc = "The Global Completion Table is completely empty", .pme_event_ids = power6_event_ids[POWER6_PME_PM_GCT_EMPTY_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_GCT_EMPTY_CYC] }, [ POWER6_PME_PM_LLA_COUNT ] = { .pme_name = "PM_LLA_COUNT", .pme_code = 0xc01f, .pme_short_desc = "Transitions into Load Look Ahead mode", .pme_long_desc = "Transitions into Load Look Ahead mode", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LLA_COUNT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LLA_COUNT] }, [ POWER6_PME_PM_LSU0_REJECT_NO_SCRATCH ] = { .pme_name = "PM_LSU0_REJECT_NO_SCRATCH", .pme_code = 0xa10a2, .pme_short_desc = "LSU0 reject due to scratch register not available", .pme_long_desc = "LSU0 reject due to scratch register not available", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_REJECT_NO_SCRATCH], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_REJECT_NO_SCRATCH] }, [ POWER6_PME_PM_DPU_WT_IC_MISS ] = { .pme_name = "PM_DPU_WT_IC_MISS", .pme_code = 0x20000c, .pme_short_desc = "Cycles DISP unit is stalled due to I cache miss", .pme_long_desc = "Cycles DISP unit is stalled due to I cache miss", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_WT_IC_MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_WT_IC_MISS] }, [ POWER6_PME_PM_DATA_FROM_L3MISS ] = { .pme_name = "PM_DATA_FROM_L3MISS", .pme_code = 0x3000fe, .pme_short_desc = "Data loaded from private L3 miss", .pme_long_desc = "Data loaded from private L3 miss", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L3MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L3MISS] }, [ POWER6_PME_PM_FPU_FPSCR ] = { .pme_name = "PM_FPU_FPSCR", .pme_code = 0x2d0032, .pme_short_desc = "FPU executed FPSCR instruction", .pme_long_desc = "FPU executed FPSCR instruction", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_FPSCR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_FPSCR] }, [ POWER6_PME_PM_VMX1_INST_ISSUED ] = { .pme_name = "PM_VMX1_INST_ISSUED", .pme_code = 0x60088, .pme_short_desc = "VMX1 instruction issued", .pme_long_desc = "VMX1 instruction issued", .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX1_INST_ISSUED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX1_INST_ISSUED] }, [ POWER6_PME_PM_FLUSH ] = { .pme_name = "PM_FLUSH", .pme_code = 0x100010, .pme_short_desc = "Flushes", .pme_long_desc = "Flushes", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FLUSH], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FLUSH] }, [ POWER6_PME_PM_ST_HIT_L2 ] = { .pme_name = "PM_ST_HIT_L2", .pme_code = 0x150732, .pme_short_desc = "L2 D cache store hits", .pme_long_desc = "L2 D cache store hits", .pme_event_ids = power6_event_ids[POWER6_PME_PM_ST_HIT_L2], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_ST_HIT_L2] }, [ POWER6_PME_PM_SYNC_CYC ] = { .pme_name = "PM_SYNC_CYC", .pme_code = 0x920cc, .pme_short_desc = "Sync duration", .pme_long_desc = "Sync duration", .pme_event_ids = power6_event_ids[POWER6_PME_PM_SYNC_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_SYNC_CYC] }, [ POWER6_PME_PM_FAB_SYS_PUMP ] = { .pme_name = "PM_FAB_SYS_PUMP", .pme_code = 0x50180, .pme_short_desc = "System pump operation", .pme_long_desc = " locally mastered", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FAB_SYS_PUMP], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FAB_SYS_PUMP] }, [ POWER6_PME_PM_IC_PREF_REQ ] = { .pme_name = "PM_IC_PREF_REQ", .pme_code = 0x4008c, .pme_short_desc = "Instruction prefetch requests", .pme_long_desc = "Asserted when a non-canceled prefetch is made to the cache interface unit (CIU).", .pme_event_ids = power6_event_ids[POWER6_PME_PM_IC_PREF_REQ], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IC_PREF_REQ] }, [ POWER6_PME_PM_MEM0_DP_RQ_GLOB_LOC ] = { .pme_name = "PM_MEM0_DP_RQ_GLOB_LOC", .pme_code = 0x50280, .pme_short_desc = "Memory read queue marking cache line double pump state from global to local side 0", .pme_long_desc = "Memory read queue marking cache line double pump state from global to local side 0", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MEM0_DP_RQ_GLOB_LOC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MEM0_DP_RQ_GLOB_LOC] }, [ POWER6_PME_PM_FPU_ISSUE_0 ] = { .pme_name = "PM_FPU_ISSUE_0", .pme_code = 0x320c6, .pme_short_desc = "FPU issue 0 per cycle", .pme_long_desc = "FPU issue 0 per cycle", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_ISSUE_0], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_ISSUE_0] }, [ POWER6_PME_PM_THRD_PRIO_2_CYC ] = { .pme_name = "PM_THRD_PRIO_2_CYC", .pme_code = 0x322040, .pme_short_desc = "Cycles thread running at priority level 2", .pme_long_desc = "Cycles thread running at priority level 2", .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_2_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_2_CYC] }, [ POWER6_PME_PM_VMX_SIMPLE_ISSUED ] = { .pme_name = "PM_VMX_SIMPLE_ISSUED", .pme_code = 0x70082, .pme_short_desc = "VMX instruction issued to simple", .pme_long_desc = "VMX instruction issued to simple", .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX_SIMPLE_ISSUED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX_SIMPLE_ISSUED] }, [ POWER6_PME_PM_MRK_FPU1_FIN ] = { .pme_name = "PM_MRK_FPU1_FIN", .pme_code = 0xd008a, .pme_short_desc = "Marked instruction FPU1 processing finished", .pme_long_desc = "Marked instruction FPU1 processing finished", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_FPU1_FIN], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_FPU1_FIN] }, [ POWER6_PME_PM_DPU_HELD_CW ] = { .pme_name = "PM_DPU_HELD_CW", .pme_code = 0x20084, .pme_short_desc = "DISP unit held due to cache writes ", .pme_long_desc = "DISP unit held due to cache writes ", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_CW], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_CW] }, [ POWER6_PME_PM_L3SA_REF ] = { .pme_name = "PM_L3SA_REF", .pme_code = 0x50080, .pme_short_desc = "L3 slice A references", .pme_long_desc = "L3 slice A references", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L3SA_REF], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L3SA_REF] }, [ POWER6_PME_PM_STCX ] = { .pme_name = "PM_STCX", .pme_code = 0x830e6, .pme_short_desc = "STCX executed", .pme_long_desc = "STCX executed", .pme_event_ids = power6_event_ids[POWER6_PME_PM_STCX], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_STCX] }, [ POWER6_PME_PM_L2SB_MISS ] = { .pme_name = "PM_L2SB_MISS", .pme_code = 0x5058c, .pme_short_desc = "L2 slice B misses", .pme_long_desc = "L2 slice B misses", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SB_MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SB_MISS] }, [ POWER6_PME_PM_LSU0_REJECT ] = { .pme_name = "PM_LSU0_REJECT", .pme_code = 0xa10a6, .pme_short_desc = "LSU0 reject", .pme_long_desc = "LSU0 reject", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_REJECT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_REJECT] }, [ POWER6_PME_PM_TB_BIT_TRANS ] = { .pme_name = "PM_TB_BIT_TRANS", .pme_code = 0x100026, .pme_short_desc = "Time Base bit transition", .pme_long_desc = "When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 ", .pme_event_ids = power6_event_ids[POWER6_PME_PM_TB_BIT_TRANS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_TB_BIT_TRANS] }, [ POWER6_PME_PM_THERMAL_MAX ] = { .pme_name = "PM_THERMAL_MAX", .pme_code = 0x30002a, .pme_short_desc = "Processor in thermal MAX", .pme_long_desc = "Processor in thermal MAX", .pme_event_ids = power6_event_ids[POWER6_PME_PM_THERMAL_MAX], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THERMAL_MAX] }, [ POWER6_PME_PM_FPU0_STF ] = { .pme_name = "PM_FPU0_STF", .pme_code = 0xc10a4, .pme_short_desc = "FPU0 executed store instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing a store instruction.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_STF], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_STF] }, [ POWER6_PME_PM_FPU1_FMA ] = { .pme_name = "PM_FPU1_FMA", .pme_code = 0xc008a, .pme_short_desc = "FPU1 executed multiply-add instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_FMA], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_FMA] }, [ POWER6_PME_PM_LSU1_REJECT_LHS ] = { .pme_name = "PM_LSU1_REJECT_LHS", .pme_code = 0x9008e, .pme_short_desc = "LSU1 load hit store reject", .pme_long_desc = "LSU1 load hit store reject", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU1_REJECT_LHS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU1_REJECT_LHS] }, [ POWER6_PME_PM_DPU_HELD_INT ] = { .pme_name = "PM_DPU_HELD_INT", .pme_code = 0x310a8, .pme_short_desc = "DISP unit held due to exception", .pme_long_desc = "DISP unit held due to exception", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_INT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_INT] }, [ POWER6_PME_PM_THRD_LLA_BOTH_CYC ] = { .pme_name = "PM_THRD_LLA_BOTH_CYC", .pme_code = 0x400008, .pme_short_desc = "Both threads in Load Look Ahead", .pme_long_desc = "Both threads in Load Look Ahead", .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_LLA_BOTH_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_LLA_BOTH_CYC] }, [ POWER6_PME_PM_DPU_HELD_THERMAL_COUNT ] = { .pme_name = "PM_DPU_HELD_THERMAL_COUNT", .pme_code = 0x10002b, .pme_short_desc = "Periods DISP unit held due to thermal condition", .pme_long_desc = "Periods DISP unit held due to thermal condition", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_THERMAL_COUNT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_THERMAL_COUNT] }, [ POWER6_PME_PM_PMC4_REWIND ] = { .pme_name = "PM_PMC4_REWIND", .pme_code = 0x100020, .pme_short_desc = "PMC4 rewind event", .pme_long_desc = "PMC4 rewind event", .pme_event_ids = power6_event_ids[POWER6_PME_PM_PMC4_REWIND], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PMC4_REWIND] }, [ POWER6_PME_PM_DERAT_REF_16M ] = { .pme_name = "PM_DERAT_REF_16M", .pme_code = 0x382070, .pme_short_desc = "DERAT reference for 16M page", .pme_long_desc = "DERAT reference for 16M page", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DERAT_REF_16M], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DERAT_REF_16M] }, [ POWER6_PME_PM_FPU0_FCONV ] = { .pme_name = "PM_FPU0_FCONV", .pme_code = 0xd10a0, .pme_short_desc = "FPU0 executed FCONV instruction", .pme_long_desc = "FPU0 executed FCONV instruction", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_FCONV], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_FCONV] }, [ POWER6_PME_PM_L2SA_LD_REQ_DATA ] = { .pme_name = "PM_L2SA_LD_REQ_DATA", .pme_code = 0x50480, .pme_short_desc = "L2 slice A data load requests", .pme_long_desc = "L2 slice A data load requests", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SA_LD_REQ_DATA], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SA_LD_REQ_DATA] }, [ POWER6_PME_PM_DATA_FROM_MEM_DP ] = { .pme_name = "PM_DATA_FROM_MEM_DP", .pme_code = 0x10005e, .pme_short_desc = "Data loaded from double pump memory", .pme_long_desc = "Data loaded from double pump memory", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_MEM_DP], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_MEM_DP] }, [ POWER6_PME_PM_MRK_VMX_FLOAT_ISSUED ] = { .pme_name = "PM_MRK_VMX_FLOAT_ISSUED", .pme_code = 0x70088, .pme_short_desc = "Marked VMX instruction issued to float", .pme_long_desc = "Marked VMX instruction issued to float", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_VMX_FLOAT_ISSUED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_VMX_FLOAT_ISSUED] }, [ POWER6_PME_PM_MRK_PTEG_FROM_L2MISS ] = { .pme_name = "PM_MRK_PTEG_FROM_L2MISS", .pme_code = 0x412054, .pme_short_desc = "Marked PTEG loaded from L2 miss", .pme_long_desc = "Marked PTEG loaded from L2 miss", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_L2MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_L2MISS] }, [ POWER6_PME_PM_THRD_PRIO_DIFF_1or2_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_1or2_CYC", .pme_code = 0x223040, .pme_short_desc = "Cycles thread priority difference is 1 or 2", .pme_long_desc = "Cycles thread priority difference is 1 or 2", .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_DIFF_1or2_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_DIFF_1or2_CYC] }, [ POWER6_PME_PM_VMX0_STALL ] = { .pme_name = "PM_VMX0_STALL", .pme_code = 0xb0084, .pme_short_desc = "VMX0 stall", .pme_long_desc = "VMX0 stall", .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX0_STALL], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX0_STALL] }, [ POWER6_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = { .pme_name = "PM_IC_DEMAND_L2_BHT_REDIRECT", .pme_code = 0x420ca, .pme_short_desc = "L2 I cache demand request due to BHT redirect", .pme_long_desc = "L2 I cache demand request due to BHT redirect", .pme_event_ids = power6_event_ids[POWER6_PME_PM_IC_DEMAND_L2_BHT_REDIRECT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IC_DEMAND_L2_BHT_REDIRECT] }, [ POWER6_PME_PM_LSU_DERAT_MISS ] = { .pme_name = "PM_LSU_DERAT_MISS", .pme_code = 0x20000e, .pme_short_desc = "DERAT misses", .pme_long_desc = "Total DERAT Misses (Unit 0 + Unit 1). Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_DERAT_MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_DERAT_MISS] }, [ POWER6_PME_PM_FPU0_SINGLE ] = { .pme_name = "PM_FPU0_SINGLE", .pme_code = 0xc10a6, .pme_short_desc = "FPU0 executed single precision instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing single precision instruction.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_SINGLE], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_SINGLE] }, [ POWER6_PME_PM_FPU_ISSUE_STEERING ] = { .pme_name = "PM_FPU_ISSUE_STEERING", .pme_code = 0x320c4, .pme_short_desc = "FPU issue steering", .pme_long_desc = "FPU issue steering", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_ISSUE_STEERING], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_ISSUE_STEERING] }, [ POWER6_PME_PM_THRD_PRIO_1_CYC ] = { .pme_name = "PM_THRD_PRIO_1_CYC", .pme_code = 0x222040, .pme_short_desc = "Cycles thread running at priority level 1", .pme_long_desc = "Cycles thread running at priority level 1", .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_1_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_1_CYC] }, [ POWER6_PME_PM_VMX_COMPLEX_ISSUED ] = { .pme_name = "PM_VMX_COMPLEX_ISSUED", .pme_code = 0x70084, .pme_short_desc = "VMX instruction issued to complex", .pme_long_desc = "VMX instruction issued to complex", .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX_COMPLEX_ISSUED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX_COMPLEX_ISSUED] }, [ POWER6_PME_PM_FPU_ISSUE_ST_FOLDED ] = { .pme_name = "PM_FPU_ISSUE_ST_FOLDED", .pme_code = 0x320c2, .pme_short_desc = "FPU issue a folded store", .pme_long_desc = "FPU issue a folded store", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_ISSUE_ST_FOLDED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_ISSUE_ST_FOLDED] }, [ POWER6_PME_PM_DFU_FIN ] = { .pme_name = "PM_DFU_FIN", .pme_code = 0xe0080, .pme_short_desc = "DFU instruction finish", .pme_long_desc = "DFU instruction finish", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DFU_FIN], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DFU_FIN] }, [ POWER6_PME_PM_BR_PRED_CCACHE ] = { .pme_name = "PM_BR_PRED_CCACHE", .pme_code = 0x410a4, .pme_short_desc = "Branch count cache prediction", .pme_long_desc = "Branch count cache prediction", .pme_event_ids = power6_event_ids[POWER6_PME_PM_BR_PRED_CCACHE], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_BR_PRED_CCACHE] }, [ POWER6_PME_PM_MRK_ST_CMPL_INT ] = { .pme_name = "PM_MRK_ST_CMPL_INT", .pme_code = 0x300006, .pme_short_desc = "Marked store completed with intervention", .pme_long_desc = "A marked store previously sent to the memory subsystem completed (data home) after requiring intervention", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_ST_CMPL_INT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_ST_CMPL_INT] }, [ POWER6_PME_PM_FAB_MMIO ] = { .pme_name = "PM_FAB_MMIO", .pme_code = 0x50186, .pme_short_desc = "MMIO operation", .pme_long_desc = " locally mastered", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FAB_MMIO], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FAB_MMIO] }, [ POWER6_PME_PM_MRK_VMX_SIMPLE_ISSUED ] = { .pme_name = "PM_MRK_VMX_SIMPLE_ISSUED", .pme_code = 0x7008a, .pme_short_desc = "Marked VMX instruction issued to simple", .pme_long_desc = "Marked VMX instruction issued to simple", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_VMX_SIMPLE_ISSUED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_VMX_SIMPLE_ISSUED] }, [ POWER6_PME_PM_FPU_STF ] = { .pme_name = "PM_FPU_STF", .pme_code = 0x3c1030, .pme_short_desc = "FPU executed store instruction", .pme_long_desc = "FPU is executing a store instruction. Combined Unit 0 + Unit 1", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_STF], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_STF] }, [ POWER6_PME_PM_MEM1_DP_CL_WR_GLOB ] = { .pme_name = "PM_MEM1_DP_CL_WR_GLOB", .pme_code = 0x5028c, .pme_short_desc = "cacheline write setting dp to global side 1", .pme_long_desc = "cacheline write setting dp to global side 1", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MEM1_DP_CL_WR_GLOB], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MEM1_DP_CL_WR_GLOB] }, [ POWER6_PME_PM_MRK_DATA_FROM_L3MISS ] = { .pme_name = "PM_MRK_DATA_FROM_L3MISS", .pme_code = 0x303028, .pme_short_desc = "Marked data loaded from L3 miss", .pme_long_desc = "Marked data loaded from L3 miss", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_L3MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_L3MISS] }, [ POWER6_PME_PM_GCT_NOSLOT_CYC ] = { .pme_name = "PM_GCT_NOSLOT_CYC", .pme_code = 0x100008, .pme_short_desc = "Cycles no GCT slot allocated", .pme_long_desc = "Cycles this thread does not have any slots allocated in the GCT.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_GCT_NOSLOT_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_GCT_NOSLOT_CYC] }, [ POWER6_PME_PM_L2_ST_REQ_DATA ] = { .pme_name = "PM_L2_ST_REQ_DATA", .pme_code = 0x250432, .pme_short_desc = "L2 data store requests", .pme_long_desc = "L2 data store requests", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2_ST_REQ_DATA], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2_ST_REQ_DATA] }, [ POWER6_PME_PM_INST_TABLEWALK_COUNT ] = { .pme_name = "PM_INST_TABLEWALK_COUNT", .pme_code = 0x920cb, .pme_short_desc = "Periods doing instruction tablewalks", .pme_long_desc = "Periods doing instruction tablewalks", .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_TABLEWALK_COUNT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_TABLEWALK_COUNT] }, [ POWER6_PME_PM_PTEG_FROM_L35_SHR ] = { .pme_name = "PM_PTEG_FROM_L35_SHR", .pme_code = 0x21304e, .pme_short_desc = "PTEG loaded from L3.5 shared", .pme_long_desc = "PTEG loaded from L3.5 shared", .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_L35_SHR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_L35_SHR] }, [ POWER6_PME_PM_DPU_HELD_ISYNC ] = { .pme_name = "PM_DPU_HELD_ISYNC", .pme_code = 0x2008a, .pme_short_desc = "DISP unit held due to ISYNC ", .pme_long_desc = "DISP unit held due to ISYNC ", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_ISYNC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_ISYNC] }, [ POWER6_PME_PM_MRK_DATA_FROM_L25_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L25_SHR", .pme_code = 0x40304e, .pme_short_desc = "Marked data loaded from L2.5 shared", .pme_long_desc = "DL1 was reloaded with shared (T or SL) data from the L2 of a chip on this MCM due to a marked demand load", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_L25_SHR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_L25_SHR] }, [ POWER6_PME_PM_L3SA_HIT ] = { .pme_name = "PM_L3SA_HIT", .pme_code = 0x50082, .pme_short_desc = "L3 slice A hits", .pme_long_desc = "L3 slice A hits", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L3SA_HIT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L3SA_HIT] }, [ POWER6_PME_PM_DERAT_MISS_16G ] = { .pme_name = "PM_DERAT_MISS_16G", .pme_code = 0x492070, .pme_short_desc = "DERAT misses for 16G page", .pme_long_desc = "A data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DERAT_MISS_16G], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DERAT_MISS_16G] }, [ POWER6_PME_PM_DATA_PTEG_2ND_HALF ] = { .pme_name = "PM_DATA_PTEG_2ND_HALF", .pme_code = 0x910a2, .pme_short_desc = "Data table walk matched in second half pri­mary PTEG", .pme_long_desc = "Data table walk matched in second half pri­mary PTEG", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_PTEG_2ND_HALF], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_PTEG_2ND_HALF] }, [ POWER6_PME_PM_L2SA_ST_REQ ] = { .pme_name = "PM_L2SA_ST_REQ", .pme_code = 0x50484, .pme_short_desc = "L2 slice A store requests", .pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A,B,and C.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SA_ST_REQ], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SA_ST_REQ] }, [ POWER6_PME_PM_INST_FROM_LMEM ] = { .pme_name = "PM_INST_FROM_LMEM", .pme_code = 0x442042, .pme_short_desc = "Instruction fetched from local memory", .pme_long_desc = "Instruction fetched from local memory", .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_LMEM], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_LMEM] }, [ POWER6_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = { .pme_name = "PM_IC_DEMAND_L2_BR_REDIRECT", .pme_code = 0x420cc, .pme_short_desc = "L2 I cache demand request due to branch redirect", .pme_long_desc = "L2 I cache demand request due to branch redirect", .pme_event_ids = power6_event_ids[POWER6_PME_PM_IC_DEMAND_L2_BR_REDIRECT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IC_DEMAND_L2_BR_REDIRECT] }, [ POWER6_PME_PM_PTEG_FROM_L2 ] = { .pme_name = "PM_PTEG_FROM_L2", .pme_code = 0x113048, .pme_short_desc = "PTEG loaded from L2", .pme_long_desc = "PTEG loaded from L2", .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_L2], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_L2] }, [ POWER6_PME_PM_DATA_PTEG_1ST_HALF ] = { .pme_name = "PM_DATA_PTEG_1ST_HALF", .pme_code = 0x910a0, .pme_short_desc = "Data table walk matched in first half primary PTEG", .pme_long_desc = "Data table walk matched in first half primary PTEG", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_PTEG_1ST_HALF], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_PTEG_1ST_HALF] }, [ POWER6_PME_PM_BR_MPRED_COUNT ] = { .pme_name = "PM_BR_MPRED_COUNT", .pme_code = 0x410aa, .pme_short_desc = "Branch misprediction due to count prediction", .pme_long_desc = "Branch misprediction due to count prediction", .pme_event_ids = power6_event_ids[POWER6_PME_PM_BR_MPRED_COUNT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_BR_MPRED_COUNT] }, [ POWER6_PME_PM_IERAT_MISS_4K ] = { .pme_name = "PM_IERAT_MISS_4K", .pme_code = 0x492076, .pme_short_desc = "IERAT misses for 4K page", .pme_long_desc = "IERAT misses for 4K page", .pme_event_ids = power6_event_ids[POWER6_PME_PM_IERAT_MISS_4K], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IERAT_MISS_4K] }, [ POWER6_PME_PM_THRD_BOTH_RUN_COUNT ] = { .pme_name = "PM_THRD_BOTH_RUN_COUNT", .pme_code = 0x400005, .pme_short_desc = "Periods both threads in run cycles", .pme_long_desc = "Periods both threads in run cycles", .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_BOTH_RUN_COUNT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_BOTH_RUN_COUNT] }, [ POWER6_PME_PM_LSU_REJECT_ULD ] = { .pme_name = "PM_LSU_REJECT_ULD", .pme_code = 0x190030, .pme_short_desc = "Unaligned load reject", .pme_long_desc = "Unaligned load reject", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_ULD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_ULD] }, [ POWER6_PME_PM_DATA_FROM_DL2L3_MOD_CYC ] = { .pme_name = "PM_DATA_FROM_DL2L3_MOD_CYC", .pme_code = 0x40002a, .pme_short_desc = "Load latency from distant L2 or L3 modified", .pme_long_desc = "Load latency from distant L2 or L3 modified", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_DL2L3_MOD_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_DL2L3_MOD_CYC] }, [ POWER6_PME_PM_MRK_PTEG_FROM_RL2L3_MOD ] = { .pme_name = "PM_MRK_PTEG_FROM_RL2L3_MOD", .pme_code = 0x112044, .pme_short_desc = "Marked PTEG loaded from remote L2 or L3 modified", .pme_long_desc = "Marked PTEG loaded from remote L2 or L3 modified", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_RL2L3_MOD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_RL2L3_MOD] }, [ POWER6_PME_PM_FPU0_FLOP ] = { .pme_name = "PM_FPU0_FLOP", .pme_code = 0xc0086, .pme_short_desc = "FPU0 executed 1FLOP", .pme_long_desc = " FMA", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_FLOP], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_FLOP] }, [ POWER6_PME_PM_FPU0_FEST ] = { .pme_name = "PM_FPU0_FEST", .pme_code = 0xd10a6, .pme_short_desc = "FPU0 executed FEST instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. ", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_FEST], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_FEST] }, [ POWER6_PME_PM_MRK_LSU0_REJECT_LHS ] = { .pme_name = "PM_MRK_LSU0_REJECT_LHS", .pme_code = 0x930e6, .pme_short_desc = "LSU0 marked load hit store reject", .pme_long_desc = "LSU0 marked load hit store reject", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_LSU0_REJECT_LHS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_LSU0_REJECT_LHS] }, [ POWER6_PME_PM_VMX_RESULT_SAT_1 ] = { .pme_name = "PM_VMX_RESULT_SAT_1", .pme_code = 0xb0086, .pme_short_desc = "VMX valid result with sat=1", .pme_long_desc = "VMX valid result with sat=1", .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX_RESULT_SAT_1], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX_RESULT_SAT_1] }, [ POWER6_PME_PM_NO_ITAG_CYC ] = { .pme_name = "PM_NO_ITAG_CYC", .pme_code = 0x40088, .pme_short_desc = "Cyles no ITAG available", .pme_long_desc = "Cyles no ITAG available", .pme_event_ids = power6_event_ids[POWER6_PME_PM_NO_ITAG_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_NO_ITAG_CYC] }, [ POWER6_PME_PM_LSU1_REJECT_NO_SCRATCH ] = { .pme_name = "PM_LSU1_REJECT_NO_SCRATCH", .pme_code = 0xa10aa, .pme_short_desc = "LSU1 reject due to scratch register not available", .pme_long_desc = "LSU1 reject due to scratch register not available", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU1_REJECT_NO_SCRATCH], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU1_REJECT_NO_SCRATCH] }, [ POWER6_PME_PM_0INST_FETCH ] = { .pme_name = "PM_0INST_FETCH", .pme_code = 0x40080, .pme_short_desc = "No instructions fetched", .pme_long_desc = "No instructions were fetched this cycles (due to IFU hold, redirect, or icache miss)", .pme_event_ids = power6_event_ids[POWER6_PME_PM_0INST_FETCH], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_0INST_FETCH] }, [ POWER6_PME_PM_DPU_WT_BR_MPRED ] = { .pme_name = "PM_DPU_WT_BR_MPRED", .pme_code = 0x40000c, .pme_short_desc = "Cycles DISP unit is stalled due to branch misprediction", .pme_long_desc = "Cycles DISP unit is stalled due to branch misprediction", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_WT_BR_MPRED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_WT_BR_MPRED] }, [ POWER6_PME_PM_L1_PREF ] = { .pme_name = "PM_L1_PREF", .pme_code = 0x810a4, .pme_short_desc = "L1 cache data prefetches", .pme_long_desc = "A request to prefetch data into the L1 was made", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L1_PREF], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L1_PREF] }, [ POWER6_PME_PM_VMX_FLOAT_MULTICYCLE ] = { .pme_name = "PM_VMX_FLOAT_MULTICYCLE", .pme_code = 0xb0082, .pme_short_desc = "VMX multi-cycle floating point instruction issued", .pme_long_desc = "VMX multi-cycle floating point instruction issued", .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX_FLOAT_MULTICYCLE], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX_FLOAT_MULTICYCLE] }, [ POWER6_PME_PM_DATA_FROM_L25_SHR_CYC ] = { .pme_name = "PM_DATA_FROM_L25_SHR_CYC", .pme_code = 0x200024, .pme_short_desc = "Load latency from L2.5 shared", .pme_long_desc = "Load latency from L2.5 shared", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L25_SHR_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L25_SHR_CYC] }, [ POWER6_PME_PM_DATA_FROM_L3 ] = { .pme_name = "PM_DATA_FROM_L3", .pme_code = 0x300058, .pme_short_desc = "Data loaded from L3", .pme_long_desc = "DL1 was reloaded from the local L3 due to a demand load", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L3], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L3] }, [ POWER6_PME_PM_PMC2_OVERFLOW ] = { .pme_name = "PM_PMC2_OVERFLOW", .pme_code = 0x300014, .pme_short_desc = "PMC2 Overflow", .pme_long_desc = "PMC2 Overflow", .pme_event_ids = power6_event_ids[POWER6_PME_PM_PMC2_OVERFLOW], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PMC2_OVERFLOW] }, [ POWER6_PME_PM_VMX0_LD_WRBACK ] = { .pme_name = "PM_VMX0_LD_WRBACK", .pme_code = 0x60084, .pme_short_desc = "VMX0 load writeback valid", .pme_long_desc = "VMX0 load writeback valid", .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX0_LD_WRBACK], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX0_LD_WRBACK] }, [ POWER6_PME_PM_FPU0_DENORM ] = { .pme_name = "PM_FPU0_DENORM", .pme_code = 0xc10a2, .pme_short_desc = "FPU0 received denormalized data", .pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_DENORM], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_DENORM] }, [ POWER6_PME_PM_INST_FETCH_CYC ] = { .pme_name = "PM_INST_FETCH_CYC", .pme_code = 0x420c8, .pme_short_desc = "Cycles at least 1 instruction fetched", .pme_long_desc = "Asserted each cycle when the IFU sends at least one instruction to the IDU. ", .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FETCH_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FETCH_CYC] }, [ POWER6_PME_PM_LSU_LDF ] = { .pme_name = "PM_LSU_LDF", .pme_code = 0x280032, .pme_short_desc = "LSU executed Floating Point load instruction", .pme_long_desc = "LSU executed Floating Point load instruction", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_LDF], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_LDF] }, [ POWER6_PME_PM_LSU_REJECT_L2_CORR ] = { .pme_name = "PM_LSU_REJECT_L2_CORR", .pme_code = 0x1a1034, .pme_short_desc = "LSU reject due to L2 correctable error", .pme_long_desc = "LSU reject due to L2 correctable error", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_L2_CORR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_L2_CORR] }, [ POWER6_PME_PM_DERAT_REF_64K ] = { .pme_name = "PM_DERAT_REF_64K", .pme_code = 0x282070, .pme_short_desc = "DERAT reference for 64K page", .pme_long_desc = "DERAT reference for 64K page", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DERAT_REF_64K], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DERAT_REF_64K] }, [ POWER6_PME_PM_THRD_PRIO_3_CYC ] = { .pme_name = "PM_THRD_PRIO_3_CYC", .pme_code = 0x422040, .pme_short_desc = "Cycles thread running at priority level 3", .pme_long_desc = "Cycles thread running at priority level 3", .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_3_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_3_CYC] }, [ POWER6_PME_PM_FPU_FMA ] = { .pme_name = "PM_FPU_FMA", .pme_code = 0x2c0030, .pme_short_desc = "FPU executed multiply-add instruction", .pme_long_desc = "This signal is active for one cycle when FPU is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_FMA], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_FMA] }, [ POWER6_PME_PM_INST_FROM_L35_MOD ] = { .pme_name = "PM_INST_FROM_L35_MOD", .pme_code = 0x142046, .pme_short_desc = "Instruction fetched from L3.5 modified", .pme_long_desc = "Instruction fetched from L3.5 modified", .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_L35_MOD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_L35_MOD] }, [ POWER6_PME_PM_DFU_CONV ] = { .pme_name = "PM_DFU_CONV", .pme_code = 0xe008e, .pme_short_desc = "DFU convert from fixed op", .pme_long_desc = "DFU convert from fixed op", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DFU_CONV], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DFU_CONV] }, [ POWER6_PME_PM_INST_FROM_L25_MOD ] = { .pme_name = "PM_INST_FROM_L25_MOD", .pme_code = 0x342046, .pme_short_desc = "Instruction fetched from L2.5 modified", .pme_long_desc = "Instruction fetched from L2.5 modified", .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_L25_MOD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_L25_MOD] }, [ POWER6_PME_PM_PTEG_FROM_L35_MOD ] = { .pme_name = "PM_PTEG_FROM_L35_MOD", .pme_code = 0x11304e, .pme_short_desc = "PTEG loaded from L3.5 modified", .pme_long_desc = "PTEG loaded from L3.5 modified", .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_L35_MOD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_L35_MOD] }, [ POWER6_PME_PM_MRK_VMX_ST_ISSUED ] = { .pme_name = "PM_MRK_VMX_ST_ISSUED", .pme_code = 0xb0088, .pme_short_desc = "Marked VMX store issued", .pme_long_desc = "Marked VMX store issued", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_VMX_ST_ISSUED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_VMX_ST_ISSUED] }, [ POWER6_PME_PM_VMX_FLOAT_ISSUED ] = { .pme_name = "PM_VMX_FLOAT_ISSUED", .pme_code = 0x70080, .pme_short_desc = "VMX instruction issued to float", .pme_long_desc = "VMX instruction issued to float", .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX_FLOAT_ISSUED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX_FLOAT_ISSUED] }, [ POWER6_PME_PM_LSU0_REJECT_L2_CORR ] = { .pme_name = "PM_LSU0_REJECT_L2_CORR", .pme_code = 0xa10a0, .pme_short_desc = "LSU0 reject due to L2 correctable error", .pme_long_desc = "LSU0 reject due to L2 correctable error", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_REJECT_L2_CORR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_REJECT_L2_CORR] }, [ POWER6_PME_PM_THRD_L2MISS ] = { .pme_name = "PM_THRD_L2MISS", .pme_code = 0x310a0, .pme_short_desc = "Thread in L2 miss", .pme_long_desc = "Thread in L2 miss", .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_L2MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_L2MISS] }, [ POWER6_PME_PM_FPU_FCONV ] = { .pme_name = "PM_FPU_FCONV", .pme_code = 0x1d1034, .pme_short_desc = "FPU executed FCONV instruction", .pme_long_desc = "FPU executed FCONV instruction", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_FCONV], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_FCONV] }, [ POWER6_PME_PM_FPU_FXMULT ] = { .pme_name = "PM_FPU_FXMULT", .pme_code = 0x1d0032, .pme_short_desc = "FPU executed fixed point multiplication", .pme_long_desc = "FPU executed fixed point multiplication", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_FXMULT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_FXMULT] }, [ POWER6_PME_PM_FPU1_FRSP ] = { .pme_name = "PM_FPU1_FRSP", .pme_code = 0xd10aa, .pme_short_desc = "FPU1 executed FRSP instruction", .pme_long_desc = "FPU1 executed FRSP instruction", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_FRSP], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_FRSP] }, [ POWER6_PME_PM_MRK_DERAT_REF_16M ] = { .pme_name = "PM_MRK_DERAT_REF_16M", .pme_code = 0x382044, .pme_short_desc = "Marked DERAT reference for 16M page", .pme_long_desc = "Marked DERAT reference for 16M page", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DERAT_REF_16M], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DERAT_REF_16M] }, [ POWER6_PME_PM_L2SB_CASTOUT_SHR ] = { .pme_name = "PM_L2SB_CASTOUT_SHR", .pme_code = 0x5068a, .pme_short_desc = "L2 slice B castouts - Shared", .pme_long_desc = "L2 slice B castouts - Shared", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SB_CASTOUT_SHR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SB_CASTOUT_SHR] }, [ POWER6_PME_PM_THRD_ONE_RUN_COUNT ] = { .pme_name = "PM_THRD_ONE_RUN_COUNT", .pme_code = 0x1000fb, .pme_short_desc = "Periods one of the threads in run cycles", .pme_long_desc = "Periods one of the threads in run cycles", .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_ONE_RUN_COUNT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_ONE_RUN_COUNT] }, [ POWER6_PME_PM_INST_FROM_RMEM ] = { .pme_name = "PM_INST_FROM_RMEM", .pme_code = 0x342042, .pme_short_desc = "Instruction fetched from remote memory", .pme_long_desc = "Instruction fetched from remote memory", .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_RMEM], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_RMEM] }, [ POWER6_PME_PM_LSU_BOTH_BUS ] = { .pme_name = "PM_LSU_BOTH_BUS", .pme_code = 0x810aa, .pme_short_desc = "Both data return buses busy simultaneously", .pme_long_desc = "Both data return buses busy simultaneously", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_BOTH_BUS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_BOTH_BUS] }, [ POWER6_PME_PM_FPU1_FSQRT_FDIV ] = { .pme_name = "PM_FPU1_FSQRT_FDIV", .pme_code = 0xc008c, .pme_short_desc = "FPU1 executed FSQRT or FDIV instruction", .pme_long_desc = "FPU1 executed FSQRT or FDIV instruction", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_FSQRT_FDIV], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_FSQRT_FDIV] }, [ POWER6_PME_PM_L2_LD_REQ_INST ] = { .pme_name = "PM_L2_LD_REQ_INST", .pme_code = 0x150530, .pme_short_desc = "L2 instruction load requests", .pme_long_desc = "L2 instruction load requests", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2_LD_REQ_INST], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2_LD_REQ_INST] }, [ POWER6_PME_PM_MRK_PTEG_FROM_L35_SHR ] = { .pme_name = "PM_MRK_PTEG_FROM_L35_SHR", .pme_code = 0x212046, .pme_short_desc = "Marked PTEG loaded from L3.5 shared", .pme_long_desc = "Marked PTEG loaded from L3.5 shared", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_L35_SHR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_L35_SHR] }, [ POWER6_PME_PM_BR_PRED_CR ] = { .pme_name = "PM_BR_PRED_CR", .pme_code = 0x410a2, .pme_short_desc = "A conditional branch was predicted", .pme_long_desc = " CR prediction", .pme_event_ids = power6_event_ids[POWER6_PME_PM_BR_PRED_CR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_BR_PRED_CR] }, [ POWER6_PME_PM_MRK_LSU0_REJECT_ULD ] = { .pme_name = "PM_MRK_LSU0_REJECT_ULD", .pme_code = 0x930e0, .pme_short_desc = "LSU0 marked unaligned load reject", .pme_long_desc = "LSU0 marked unaligned load reject", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_LSU0_REJECT_ULD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_LSU0_REJECT_ULD] }, [ POWER6_PME_PM_LSU_REJECT ] = { .pme_name = "PM_LSU_REJECT", .pme_code = 0x4a1030, .pme_short_desc = "LSU reject", .pme_long_desc = "LSU reject", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT] }, [ POWER6_PME_PM_LSU_REJECT_LHS_BOTH ] = { .pme_name = "PM_LSU_REJECT_LHS_BOTH", .pme_code = 0x290038, .pme_short_desc = "Load hit store reject both units", .pme_long_desc = "Load hit store reject both units", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_LHS_BOTH], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_LHS_BOTH] }, [ POWER6_PME_PM_GXO_ADDR_CYC_BUSY ] = { .pme_name = "PM_GXO_ADDR_CYC_BUSY", .pme_code = 0x50382, .pme_short_desc = "Outbound GX address utilization (# of cycles address out is valid)", .pme_long_desc = "Outbound GX address utilization (# of cycles address out is valid)", .pme_event_ids = power6_event_ids[POWER6_PME_PM_GXO_ADDR_CYC_BUSY], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_GXO_ADDR_CYC_BUSY] }, [ POWER6_PME_PM_LSU_SRQ_EMPTY_COUNT ] = { .pme_name = "PM_LSU_SRQ_EMPTY_COUNT", .pme_code = 0x40001d, .pme_short_desc = "Periods SRQ empty", .pme_long_desc = "The Store Request Queue is empty", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_SRQ_EMPTY_COUNT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_SRQ_EMPTY_COUNT] }, [ POWER6_PME_PM_PTEG_FROM_L3 ] = { .pme_name = "PM_PTEG_FROM_L3", .pme_code = 0x313048, .pme_short_desc = "PTEG loaded from L3", .pme_long_desc = "PTEG loaded from L3", .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_L3], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_L3] }, [ POWER6_PME_PM_VMX0_LD_ISSUED ] = { .pme_name = "PM_VMX0_LD_ISSUED", .pme_code = 0x60082, .pme_short_desc = "VMX0 load issued", .pme_long_desc = "VMX0 load issued", .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX0_LD_ISSUED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX0_LD_ISSUED] }, [ POWER6_PME_PM_FXU_PIPELINED_MULT_DIV ] = { .pme_name = "PM_FXU_PIPELINED_MULT_DIV", .pme_code = 0x210ae, .pme_short_desc = "Fix point multiply/divide pipelined", .pme_long_desc = "Fix point multiply/divide pipelined", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FXU_PIPELINED_MULT_DIV], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FXU_PIPELINED_MULT_DIV] }, [ POWER6_PME_PM_FPU1_STF ] = { .pme_name = "PM_FPU1_STF", .pme_code = 0xc10ac, .pme_short_desc = "FPU1 executed store instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing a store instruction.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_STF], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_STF] }, [ POWER6_PME_PM_DFU_ADD ] = { .pme_name = "PM_DFU_ADD", .pme_code = 0xe008c, .pme_short_desc = "DFU add type instruction", .pme_long_desc = "DFU add type instruction", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DFU_ADD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DFU_ADD] }, [ POWER6_PME_PM_MEM_DP_CL_WR_GLOB ] = { .pme_name = "PM_MEM_DP_CL_WR_GLOB", .pme_code = 0x250232, .pme_short_desc = "cache line write setting double pump state to global", .pme_long_desc = "cache line write setting double pump state to global", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MEM_DP_CL_WR_GLOB], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MEM_DP_CL_WR_GLOB] }, [ POWER6_PME_PM_MRK_LSU1_REJECT_ULD ] = { .pme_name = "PM_MRK_LSU1_REJECT_ULD", .pme_code = 0x930e8, .pme_short_desc = "LSU1 marked unaligned load reject", .pme_long_desc = "LSU1 marked unaligned load reject", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_LSU1_REJECT_ULD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_LSU1_REJECT_ULD] }, [ POWER6_PME_PM_ITLB_REF ] = { .pme_name = "PM_ITLB_REF", .pme_code = 0x920c2, .pme_short_desc = "Instruction TLB reference", .pme_long_desc = "Instruction TLB reference", .pme_event_ids = power6_event_ids[POWER6_PME_PM_ITLB_REF], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_ITLB_REF] }, [ POWER6_PME_PM_LSU0_REJECT_L2MISS ] = { .pme_name = "PM_LSU0_REJECT_L2MISS", .pme_code = 0x90084, .pme_short_desc = "LSU0 L2 miss reject", .pme_long_desc = "LSU0 L2 miss reject", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_REJECT_L2MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_REJECT_L2MISS] }, [ POWER6_PME_PM_DATA_FROM_L35_SHR ] = { .pme_name = "PM_DATA_FROM_L35_SHR", .pme_code = 0x20005a, .pme_short_desc = "Data loaded from L3.5 shared", .pme_long_desc = "Data loaded from L3.5 shared", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L35_SHR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L35_SHR] }, [ POWER6_PME_PM_MRK_DATA_FROM_RL2L3_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_RL2L3_MOD", .pme_code = 0x10304c, .pme_short_desc = "Marked data loaded from remote L2 or L3 modified", .pme_long_desc = "Marked data loaded from remote L2 or L3 modified", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_RL2L3_MOD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_RL2L3_MOD] }, [ POWER6_PME_PM_FPU0_FPSCR ] = { .pme_name = "PM_FPU0_FPSCR", .pme_code = 0xd0084, .pme_short_desc = "FPU0 executed FPSCR instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing fpscr move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*. mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_FPSCR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_FPSCR] }, [ POWER6_PME_PM_DATA_FROM_L2 ] = { .pme_name = "PM_DATA_FROM_L2", .pme_code = 0x100058, .pme_short_desc = "Data loaded from L2", .pme_long_desc = "DL1 was reloaded from the local L2 due to a demand load", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L2], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L2] }, [ POWER6_PME_PM_DPU_HELD_XER ] = { .pme_name = "PM_DPU_HELD_XER", .pme_code = 0x20088, .pme_short_desc = "DISP unit held due to XER dependency", .pme_long_desc = "DISP unit held due to XER dependency", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_XER], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_XER] }, [ POWER6_PME_PM_FAB_NODE_PUMP ] = { .pme_name = "PM_FAB_NODE_PUMP", .pme_code = 0x50188, .pme_short_desc = "Node pump operation", .pme_long_desc = " locally mastered", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FAB_NODE_PUMP], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FAB_NODE_PUMP] }, [ POWER6_PME_PM_VMX_RESULT_SAT_0_1 ] = { .pme_name = "PM_VMX_RESULT_SAT_0_1", .pme_code = 0xb008e, .pme_short_desc = "VMX valid result with sat bit is set (0->1)", .pme_long_desc = "VMX valid result with sat bit is set (0->1)", .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX_RESULT_SAT_0_1], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX_RESULT_SAT_0_1] }, [ POWER6_PME_PM_LD_REF_L1 ] = { .pme_name = "PM_LD_REF_L1", .pme_code = 0x80082, .pme_short_desc = "L1 D cache load references", .pme_long_desc = "Total DL1 Load references", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LD_REF_L1], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LD_REF_L1] }, [ POWER6_PME_PM_TLB_REF ] = { .pme_name = "PM_TLB_REF", .pme_code = 0x920c8, .pme_short_desc = "TLB reference", .pme_long_desc = "TLB reference", .pme_event_ids = power6_event_ids[POWER6_PME_PM_TLB_REF], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_TLB_REF] }, [ POWER6_PME_PM_DC_PREF_OUT_OF_STREAMS ] = { .pme_name = "PM_DC_PREF_OUT_OF_STREAMS", .pme_code = 0x810a0, .pme_short_desc = "D cache out of streams", .pme_long_desc = "out of streams", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DC_PREF_OUT_OF_STREAMS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DC_PREF_OUT_OF_STREAMS] }, [ POWER6_PME_PM_FLUSH_FPU ] = { .pme_name = "PM_FLUSH_FPU", .pme_code = 0x230ec, .pme_short_desc = "Flush caused by FPU exception", .pme_long_desc = "Flush caused by FPU exception", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FLUSH_FPU], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FLUSH_FPU] }, [ POWER6_PME_PM_MEM1_DP_CL_WR_LOC ] = { .pme_name = "PM_MEM1_DP_CL_WR_LOC", .pme_code = 0x5028e, .pme_short_desc = "cacheline write setting dp to local side 1", .pme_long_desc = "cacheline write setting dp to local side 1", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MEM1_DP_CL_WR_LOC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MEM1_DP_CL_WR_LOC] }, [ POWER6_PME_PM_L2SB_LD_HIT ] = { .pme_name = "PM_L2SB_LD_HIT", .pme_code = 0x5078a, .pme_short_desc = "L2 slice B load hits", .pme_long_desc = "L2 slice B load hits", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SB_LD_HIT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SB_LD_HIT] }, [ POWER6_PME_PM_FAB_DCLAIM ] = { .pme_name = "PM_FAB_DCLAIM", .pme_code = 0x50184, .pme_short_desc = "Dclaim operation", .pme_long_desc = " locally mastered", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FAB_DCLAIM], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FAB_DCLAIM] }, [ POWER6_PME_PM_MEM_DP_CL_WR_LOC ] = { .pme_name = "PM_MEM_DP_CL_WR_LOC", .pme_code = 0x150232, .pme_short_desc = "cache line write setting double pump state to local", .pme_long_desc = "cache line write setting double pump state to local", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MEM_DP_CL_WR_LOC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MEM_DP_CL_WR_LOC] }, [ POWER6_PME_PM_BR_MPRED_CR ] = { .pme_name = "PM_BR_MPRED_CR", .pme_code = 0x410a8, .pme_short_desc = "Branch mispredictions due to CR bit setting", .pme_long_desc = "This signal is asserted when the branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This signal is asserted after a branch issue event and will result in a branch redirect flush if not overridden by a flush of an older instruction.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_BR_MPRED_CR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_BR_MPRED_CR] }, [ POWER6_PME_PM_LSU_REJECT_EXTERN ] = { .pme_name = "PM_LSU_REJECT_EXTERN", .pme_code = 0x3a1030, .pme_short_desc = "LSU external reject request ", .pme_long_desc = "LSU external reject request ", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_EXTERN], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_EXTERN] }, [ POWER6_PME_PM_DATA_FROM_RL2L3_MOD ] = { .pme_name = "PM_DATA_FROM_RL2L3_MOD", .pme_code = 0x10005c, .pme_short_desc = "Data loaded from remote L2 or L3 modified", .pme_long_desc = "Data loaded from remote L2 or L3 modified", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_RL2L3_MOD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_RL2L3_MOD] }, [ POWER6_PME_PM_DPU_HELD_RU_WQ ] = { .pme_name = "PM_DPU_HELD_RU_WQ", .pme_code = 0x2008e, .pme_short_desc = "DISP unit held due to RU FXU write queue full", .pme_long_desc = "DISP unit held due to RU FXU write queue full", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_RU_WQ], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_RU_WQ] }, [ POWER6_PME_PM_LD_MISS_L1 ] = { .pme_name = "PM_LD_MISS_L1", .pme_code = 0x80080, .pme_short_desc = "L1 D cache load misses", .pme_long_desc = "Total DL1 Load references that miss the DL1", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LD_MISS_L1], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LD_MISS_L1] }, [ POWER6_PME_PM_DC_INV_L2 ] = { .pme_name = "PM_DC_INV_L2", .pme_code = 0x150632, .pme_short_desc = "L1 D cache entries invalidated from L2", .pme_long_desc = "A dcache invalidated was received from the L2 because a line in L2 was castout.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DC_INV_L2], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DC_INV_L2] }, [ POWER6_PME_PM_MRK_PTEG_FROM_RMEM ] = { .pme_name = "PM_MRK_PTEG_FROM_RMEM", .pme_code = 0x312042, .pme_short_desc = "Marked PTEG loaded from remote memory", .pme_long_desc = "Marked PTEG loaded from remote memory", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_RMEM], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_RMEM] }, [ POWER6_PME_PM_FPU_FIN ] = { .pme_name = "PM_FPU_FIN", .pme_code = 0x1d0030, .pme_short_desc = "FPU produced a result", .pme_long_desc = "FPU finished, produced a result This only indicates finish, not completion. Combined Unit 0 + Unit 1", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_FIN], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_FIN] }, [ POWER6_PME_PM_FXU0_FIN ] = { .pme_name = "PM_FXU0_FIN", .pme_code = 0x300016, .pme_short_desc = "FXU0 produced a result", .pme_long_desc = "The Fixed Point unit 0 finished an instruction and produced a result", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FXU0_FIN], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FXU0_FIN] }, [ POWER6_PME_PM_DPU_HELD_FPQ ] = { .pme_name = "PM_DPU_HELD_FPQ", .pme_code = 0x20086, .pme_short_desc = "DISP unit held due to FPU issue queue full", .pme_long_desc = "DISP unit held due to FPU issue queue full", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_FPQ], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_FPQ] }, [ POWER6_PME_PM_GX_DMA_READ ] = { .pme_name = "PM_GX_DMA_READ", .pme_code = 0x5038c, .pme_short_desc = "DMA Read Request", .pme_long_desc = "DMA Read Request", .pme_event_ids = power6_event_ids[POWER6_PME_PM_GX_DMA_READ], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_GX_DMA_READ] }, [ POWER6_PME_PM_LSU1_REJECT_PARTIAL_SECTOR ] = { .pme_name = "PM_LSU1_REJECT_PARTIAL_SECTOR", .pme_code = 0xa008e, .pme_short_desc = "LSU1 reject due to partial sector valid", .pme_long_desc = "LSU1 reject due to partial sector valid", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU1_REJECT_PARTIAL_SECTOR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU1_REJECT_PARTIAL_SECTOR] }, [ POWER6_PME_PM_0INST_FETCH_COUNT ] = { .pme_name = "PM_0INST_FETCH_COUNT", .pme_code = 0x40081, .pme_short_desc = "Periods with no instructions fetched", .pme_long_desc = "No instructions were fetched this periods (due to IFU hold, redirect, or icache miss)", .pme_event_ids = power6_event_ids[POWER6_PME_PM_0INST_FETCH_COUNT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_0INST_FETCH_COUNT] }, [ POWER6_PME_PM_PMC5_OVERFLOW ] = { .pme_name = "PM_PMC5_OVERFLOW", .pme_code = 0x100024, .pme_short_desc = "PMC5 Overflow", .pme_long_desc = "PMC5 Overflow", .pme_event_ids = power6_event_ids[POWER6_PME_PM_PMC5_OVERFLOW], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PMC5_OVERFLOW] }, [ POWER6_PME_PM_L2SB_LD_REQ ] = { .pme_name = "PM_L2SB_LD_REQ", .pme_code = 0x50788, .pme_short_desc = "L2 slice B load requests ", .pme_long_desc = "L2 slice B load requests ", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SB_LD_REQ], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SB_LD_REQ] }, [ POWER6_PME_PM_THRD_PRIO_DIFF_0_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_0_CYC", .pme_code = 0x123040, .pme_short_desc = "Cycles no thread priority difference", .pme_long_desc = "Cycles no thread priority difference", .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_DIFF_0_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_DIFF_0_CYC] }, [ POWER6_PME_PM_DATA_FROM_RMEM ] = { .pme_name = "PM_DATA_FROM_RMEM", .pme_code = 0x30005e, .pme_short_desc = "Data loaded from remote memory", .pme_long_desc = "Data loaded from remote memory", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_RMEM], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_RMEM] }, [ POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_BOTH_CYC ] = { .pme_name = "PM_LSU_LMQ_SRQ_EMPTY_BOTH_CYC", .pme_code = 0x30001c, .pme_short_desc = "Cycles both threads LMQ and SRQ empty", .pme_long_desc = "Cycles both threads LMQ and SRQ empty", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_BOTH_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_BOTH_CYC] }, [ POWER6_PME_PM_ST_REF_L1_BOTH ] = { .pme_name = "PM_ST_REF_L1_BOTH", .pme_code = 0x280038, .pme_short_desc = "Both units L1 D cache store reference", .pme_long_desc = "Both units L1 D cache store reference", .pme_event_ids = power6_event_ids[POWER6_PME_PM_ST_REF_L1_BOTH], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_ST_REF_L1_BOTH] }, [ POWER6_PME_PM_VMX_PERMUTE_ISSUED ] = { .pme_name = "PM_VMX_PERMUTE_ISSUED", .pme_code = 0x70086, .pme_short_desc = "VMX instruction issued to permute", .pme_long_desc = "VMX instruction issued to permute", .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX_PERMUTE_ISSUED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX_PERMUTE_ISSUED] }, [ POWER6_PME_PM_BR_TAKEN ] = { .pme_name = "PM_BR_TAKEN", .pme_code = 0x200052, .pme_short_desc = "Branches taken", .pme_long_desc = "Branches taken", .pme_event_ids = power6_event_ids[POWER6_PME_PM_BR_TAKEN], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_BR_TAKEN] }, [ POWER6_PME_PM_FAB_DMA ] = { .pme_name = "PM_FAB_DMA", .pme_code = 0x5018c, .pme_short_desc = "DMA operation", .pme_long_desc = " locally mastered", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FAB_DMA], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FAB_DMA] }, [ POWER6_PME_PM_GCT_EMPTY_COUNT ] = { .pme_name = "PM_GCT_EMPTY_COUNT", .pme_code = 0x200009, .pme_short_desc = "Periods GCT empty", .pme_long_desc = "The Global Completion Table is completely empty.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_GCT_EMPTY_COUNT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_GCT_EMPTY_COUNT] }, [ POWER6_PME_PM_FPU1_SINGLE ] = { .pme_name = "PM_FPU1_SINGLE", .pme_code = 0xc10ae, .pme_short_desc = "FPU1 executed single precision instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing single precision instruction.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_SINGLE], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_SINGLE] }, [ POWER6_PME_PM_L2SA_CASTOUT_SHR ] = { .pme_name = "PM_L2SA_CASTOUT_SHR", .pme_code = 0x50682, .pme_short_desc = "L2 slice A castouts - Shared", .pme_long_desc = "L2 slice A castouts - Shared", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SA_CASTOUT_SHR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SA_CASTOUT_SHR] }, [ POWER6_PME_PM_L3SB_REF ] = { .pme_name = "PM_L3SB_REF", .pme_code = 0x50088, .pme_short_desc = "L3 slice B references", .pme_long_desc = "L3 slice B references", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L3SB_REF], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L3SB_REF] }, [ POWER6_PME_PM_FPU0_FRSP ] = { .pme_name = "PM_FPU0_FRSP", .pme_code = 0xd10a2, .pme_short_desc = "FPU0 executed FRSP instruction", .pme_long_desc = "FPU0 executed FRSP instruction", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_FRSP], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_FRSP] }, [ POWER6_PME_PM_PMC4_SAVED ] = { .pme_name = "PM_PMC4_SAVED", .pme_code = 0x300022, .pme_short_desc = "PMC4 rewind value saved", .pme_long_desc = "PMC4 rewind value saved", .pme_event_ids = power6_event_ids[POWER6_PME_PM_PMC4_SAVED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PMC4_SAVED] }, [ POWER6_PME_PM_L2SA_DC_INV ] = { .pme_name = "PM_L2SA_DC_INV", .pme_code = 0x50686, .pme_short_desc = "L2 slice A D cache invalidate", .pme_long_desc = "L2 slice A D cache invalidate", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SA_DC_INV], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SA_DC_INV] }, [ POWER6_PME_PM_GXI_ADDR_CYC_BUSY ] = { .pme_name = "PM_GXI_ADDR_CYC_BUSY", .pme_code = 0x50388, .pme_short_desc = "Inbound GX address utilization (# of cycle address is in valid)", .pme_long_desc = "Inbound GX address utilization (# of cycle address is in valid)", .pme_event_ids = power6_event_ids[POWER6_PME_PM_GXI_ADDR_CYC_BUSY], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_GXI_ADDR_CYC_BUSY] }, [ POWER6_PME_PM_FPU0_FMA ] = { .pme_name = "PM_FPU0_FMA", .pme_code = 0xc0082, .pme_short_desc = "FPU0 executed multiply-add instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_FMA], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_FMA] }, [ POWER6_PME_PM_SLB_MISS ] = { .pme_name = "PM_SLB_MISS", .pme_code = 0x183034, .pme_short_desc = "SLB misses", .pme_long_desc = "SLB misses", .pme_event_ids = power6_event_ids[POWER6_PME_PM_SLB_MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_SLB_MISS] }, [ POWER6_PME_PM_MRK_ST_GPS ] = { .pme_name = "PM_MRK_ST_GPS", .pme_code = 0x200006, .pme_short_desc = "Marked store sent to GPS", .pme_long_desc = "A sampled store has been sent to the memory subsystem", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_ST_GPS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_ST_GPS] }, [ POWER6_PME_PM_DERAT_REF_4K ] = { .pme_name = "PM_DERAT_REF_4K", .pme_code = 0x182070, .pme_short_desc = "DERAT reference for 4K page", .pme_long_desc = "DERAT reference for 4K page", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DERAT_REF_4K], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DERAT_REF_4K] }, [ POWER6_PME_PM_L2_CASTOUT_SHR ] = { .pme_name = "PM_L2_CASTOUT_SHR", .pme_code = 0x250630, .pme_short_desc = "L2 castouts - Shared (T", .pme_long_desc = " Te", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2_CASTOUT_SHR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2_CASTOUT_SHR] }, [ POWER6_PME_PM_DPU_HELD_STCX_CR ] = { .pme_name = "PM_DPU_HELD_STCX_CR", .pme_code = 0x2008c, .pme_short_desc = "DISP unit held due to STCX updating CR ", .pme_long_desc = "DISP unit held due to STCX updating CR ", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_STCX_CR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_STCX_CR] }, [ POWER6_PME_PM_FPU0_ST_FOLDED ] = { .pme_name = "PM_FPU0_ST_FOLDED", .pme_code = 0xd10a4, .pme_short_desc = "FPU0 folded store", .pme_long_desc = "FPU0 folded store", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_ST_FOLDED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_ST_FOLDED] }, [ POWER6_PME_PM_MRK_DATA_FROM_L21 ] = { .pme_name = "PM_MRK_DATA_FROM_L21", .pme_code = 0x203048, .pme_short_desc = "Marked data loaded from private L2 other core", .pme_long_desc = "Marked data loaded from private L2 other core", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_L21], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_L21] }, [ POWER6_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_minus3or4_CYC", .pme_code = 0x323046, .pme_short_desc = "Cycles thread priority difference is -3 or -4", .pme_long_desc = "Cycles thread priority difference is -3 or -4", .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC] }, [ POWER6_PME_PM_DATA_FROM_L35_MOD ] = { .pme_name = "PM_DATA_FROM_L35_MOD", .pme_code = 0x10005a, .pme_short_desc = "Data loaded from L3.5 modified", .pme_long_desc = "Data loaded from L3.5 modified", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L35_MOD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L35_MOD] }, [ POWER6_PME_PM_DATA_FROM_DL2L3_SHR ] = { .pme_name = "PM_DATA_FROM_DL2L3_SHR", .pme_code = 0x30005c, .pme_short_desc = "Data loaded from distant L2 or L3 shared", .pme_long_desc = "Data loaded from distant L2 or L3 shared", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_DL2L3_SHR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_DL2L3_SHR] }, [ POWER6_PME_PM_GXI_DATA_CYC_BUSY ] = { .pme_name = "PM_GXI_DATA_CYC_BUSY", .pme_code = 0x5038a, .pme_short_desc = "Inbound GX Data utilization (# of cycle data in is valid)", .pme_long_desc = "Inbound GX Data utilization (# of cycle data in is valid)", .pme_event_ids = power6_event_ids[POWER6_PME_PM_GXI_DATA_CYC_BUSY], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_GXI_DATA_CYC_BUSY] }, [ POWER6_PME_PM_LSU_REJECT_STEAL ] = { .pme_name = "PM_LSU_REJECT_STEAL", .pme_code = 0x9008c, .pme_short_desc = "LSU reject due to steal", .pme_long_desc = "LSU reject due to steal", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_STEAL], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_STEAL] }, [ POWER6_PME_PM_ST_FIN ] = { .pme_name = "PM_ST_FIN", .pme_code = 0x100054, .pme_short_desc = "Store instructions finished", .pme_long_desc = "Store instructions finished", .pme_event_ids = power6_event_ids[POWER6_PME_PM_ST_FIN], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_ST_FIN] }, [ POWER6_PME_PM_DPU_HELD_CR_LOGICAL ] = { .pme_name = "PM_DPU_HELD_CR_LOGICAL", .pme_code = 0x3008e, .pme_short_desc = "DISP unit held due to CR", .pme_long_desc = " LR or CTR updated by CR logical", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_CR_LOGICAL], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_CR_LOGICAL] }, [ POWER6_PME_PM_THRD_SEL_T0 ] = { .pme_name = "PM_THRD_SEL_T0", .pme_code = 0x310a6, .pme_short_desc = "Decode selected thread 0", .pme_long_desc = "Decode selected thread 0", .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_SEL_T0], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_SEL_T0] }, [ POWER6_PME_PM_PTEG_RELOAD_VALID ] = { .pme_name = "PM_PTEG_RELOAD_VALID", .pme_code = 0x130e8, .pme_short_desc = "TLB reload valid", .pme_long_desc = "TLB reload valid", .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_RELOAD_VALID], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_RELOAD_VALID] }, [ POWER6_PME_PM_L2_PREF_ST ] = { .pme_name = "PM_L2_PREF_ST", .pme_code = 0x810a8, .pme_short_desc = "L2 cache prefetches", .pme_long_desc = "L2 cache prefetches", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2_PREF_ST], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2_PREF_ST] }, [ POWER6_PME_PM_MRK_STCX_FAIL ] = { .pme_name = "PM_MRK_STCX_FAIL", .pme_code = 0x830e4, .pme_short_desc = "Marked STCX failed", .pme_long_desc = "A marked stcx (stwcx or stdcx) failed", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_STCX_FAIL], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_STCX_FAIL] }, [ POWER6_PME_PM_LSU0_REJECT_LHS ] = { .pme_name = "PM_LSU0_REJECT_LHS", .pme_code = 0x90086, .pme_short_desc = "LSU0 load hit store reject", .pme_long_desc = "LSU0 load hit store reject", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_REJECT_LHS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_REJECT_LHS] }, [ POWER6_PME_PM_DFU_EXP_EQ ] = { .pme_name = "PM_DFU_EXP_EQ", .pme_code = 0xe0084, .pme_short_desc = "DFU operand exponents are equal for add type", .pme_long_desc = "DFU operand exponents are equal for add type", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DFU_EXP_EQ], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DFU_EXP_EQ] }, [ POWER6_PME_PM_DPU_HELD_FP_FX_MULT ] = { .pme_name = "PM_DPU_HELD_FP_FX_MULT", .pme_code = 0x210a8, .pme_short_desc = "DISP unit held due to non fixed multiple/divide after fixed multiply/divide", .pme_long_desc = "DISP unit held due to non fixed multiple/divide after fixed multiply/divide", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_FP_FX_MULT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_FP_FX_MULT] }, [ POWER6_PME_PM_L2_LD_MISS_DATA ] = { .pme_name = "PM_L2_LD_MISS_DATA", .pme_code = 0x250430, .pme_short_desc = "L2 data load misses", .pme_long_desc = "L2 data load misses", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2_LD_MISS_DATA], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2_LD_MISS_DATA] }, [ POWER6_PME_PM_DATA_FROM_L35_MOD_CYC ] = { .pme_name = "PM_DATA_FROM_L35_MOD_CYC", .pme_code = 0x400026, .pme_short_desc = "Load latency from L3.5 modified", .pme_long_desc = "Load latency from L3.5 modified", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L35_MOD_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L35_MOD_CYC] }, [ POWER6_PME_PM_FLUSH_FXU ] = { .pme_name = "PM_FLUSH_FXU", .pme_code = 0x230ea, .pme_short_desc = "Flush caused by FXU exception", .pme_long_desc = "Flush caused by FXU exception", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FLUSH_FXU], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FLUSH_FXU] }, [ POWER6_PME_PM_FPU_ISSUE_1 ] = { .pme_name = "PM_FPU_ISSUE_1", .pme_code = 0x320c8, .pme_short_desc = "FPU issue 1 per cycle", .pme_long_desc = "FPU issue 1 per cycle", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_ISSUE_1], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_ISSUE_1] }, [ POWER6_PME_PM_DATA_FROM_LMEM_CYC ] = { .pme_name = "PM_DATA_FROM_LMEM_CYC", .pme_code = 0x20002c, .pme_short_desc = "Load latency from local memory", .pme_long_desc = "Load latency from local memory", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_LMEM_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_LMEM_CYC] }, [ POWER6_PME_PM_DPU_HELD_LSU_SOPS ] = { .pme_name = "PM_DPU_HELD_LSU_SOPS", .pme_code = 0x30080, .pme_short_desc = "DISP unit held due to LSU slow ops (sync", .pme_long_desc = " tlbie", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_LSU_SOPS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_LSU_SOPS] }, [ POWER6_PME_PM_INST_PTEG_2ND_HALF ] = { .pme_name = "PM_INST_PTEG_2ND_HALF", .pme_code = 0x910aa, .pme_short_desc = "Instruction table walk matched in second half primary PTEG", .pme_long_desc = "Instruction table walk matched in second half primary PTEG", .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_PTEG_2ND_HALF], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_PTEG_2ND_HALF] }, [ POWER6_PME_PM_THRESH_TIMEO ] = { .pme_name = "PM_THRESH_TIMEO", .pme_code = 0x300018, .pme_short_desc = "Threshold timeout", .pme_long_desc = "The threshold timer expired", .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRESH_TIMEO], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRESH_TIMEO] }, [ POWER6_PME_PM_LSU_REJECT_UST_BOTH ] = { .pme_name = "PM_LSU_REJECT_UST_BOTH", .pme_code = 0x190036, .pme_short_desc = "Unaligned store reject both units", .pme_long_desc = "Unaligned store reject both units", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_UST_BOTH], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_UST_BOTH] }, [ POWER6_PME_PM_LSU_REJECT_FAST ] = { .pme_name = "PM_LSU_REJECT_FAST", .pme_code = 0x30003e, .pme_short_desc = "LSU fast reject", .pme_long_desc = "LSU fast reject", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_FAST], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_FAST] }, [ POWER6_PME_PM_DPU_HELD_THRD_PRIO ] = { .pme_name = "PM_DPU_HELD_THRD_PRIO", .pme_code = 0x3008a, .pme_short_desc = "DISP unit held due to lower priority thread", .pme_long_desc = "DISP unit held due to lower priority thread", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_THRD_PRIO], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_THRD_PRIO] }, [ POWER6_PME_PM_L2_PREF_LD ] = { .pme_name = "PM_L2_PREF_LD", .pme_code = 0x810a6, .pme_short_desc = "L2 cache prefetches", .pme_long_desc = "L2 cache prefetches", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2_PREF_LD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2_PREF_LD] }, [ POWER6_PME_PM_FPU_FEST ] = { .pme_name = "PM_FPU_FEST", .pme_code = 0x4d1030, .pme_short_desc = "FPU executed FEST instruction", .pme_long_desc = "This signal is active for one cycle when executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. Combined Unit 0 + Unit 1.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_FEST], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_FEST] }, [ POWER6_PME_PM_MRK_DATA_FROM_RMEM ] = { .pme_name = "PM_MRK_DATA_FROM_RMEM", .pme_code = 0x30304a, .pme_short_desc = "Marked data loaded from remote memory", .pme_long_desc = "Marked data loaded from remote memory", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_RMEM], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_RMEM] }, [ POWER6_PME_PM_LD_MISS_L1_CYC ] = { .pme_name = "PM_LD_MISS_L1_CYC", .pme_code = 0x10000c, .pme_short_desc = "L1 data load miss cycles", .pme_long_desc = "L1 data load miss cycles", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LD_MISS_L1_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LD_MISS_L1_CYC] }, [ POWER6_PME_PM_DERAT_MISS_4K ] = { .pme_name = "PM_DERAT_MISS_4K", .pme_code = 0x192070, .pme_short_desc = "DERAT misses for 4K page", .pme_long_desc = "A data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DERAT_MISS_4K], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DERAT_MISS_4K] }, [ POWER6_PME_PM_DPU_HELD_COMPLETION ] = { .pme_name = "PM_DPU_HELD_COMPLETION", .pme_code = 0x210ac, .pme_short_desc = "DISP unit held due to completion holding dispatch ", .pme_long_desc = "DISP unit held due to completion holding dispatch ", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_COMPLETION], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_COMPLETION] }, [ POWER6_PME_PM_FPU_ISSUE_STALL_ST ] = { .pme_name = "PM_FPU_ISSUE_STALL_ST", .pme_code = 0x320ce, .pme_short_desc = "FPU issue stalled due to store", .pme_long_desc = "FPU issue stalled due to store", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_ISSUE_STALL_ST], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_ISSUE_STALL_ST] }, [ POWER6_PME_PM_L2SB_DC_INV ] = { .pme_name = "PM_L2SB_DC_INV", .pme_code = 0x5068e, .pme_short_desc = "L2 slice B D cache invalidate", .pme_long_desc = "L2 slice B D cache invalidate", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SB_DC_INV], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SB_DC_INV] }, [ POWER6_PME_PM_PTEG_FROM_L25_SHR ] = { .pme_name = "PM_PTEG_FROM_L25_SHR", .pme_code = 0x41304e, .pme_short_desc = "PTEG loaded from L2.5 shared", .pme_long_desc = "PTEG loaded from L2.5 shared", .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_L25_SHR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_L25_SHR] }, [ POWER6_PME_PM_PTEG_FROM_DL2L3_MOD ] = { .pme_name = "PM_PTEG_FROM_DL2L3_MOD", .pme_code = 0x41304c, .pme_short_desc = "PTEG loaded from distant L2 or L3 modified", .pme_long_desc = "PTEG loaded from distant L2 or L3 modified", .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_DL2L3_MOD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_DL2L3_MOD] }, [ POWER6_PME_PM_FAB_CMD_RETRIED ] = { .pme_name = "PM_FAB_CMD_RETRIED", .pme_code = 0x250130, .pme_short_desc = "Fabric command retried", .pme_long_desc = "Fabric command retried", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FAB_CMD_RETRIED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FAB_CMD_RETRIED] }, [ POWER6_PME_PM_BR_PRED_LSTACK ] = { .pme_name = "PM_BR_PRED_LSTACK", .pme_code = 0x410a6, .pme_short_desc = "A conditional branch was predicted", .pme_long_desc = " link stack", .pme_event_ids = power6_event_ids[POWER6_PME_PM_BR_PRED_LSTACK], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_BR_PRED_LSTACK] }, [ POWER6_PME_PM_GXO_DATA_CYC_BUSY ] = { .pme_name = "PM_GXO_DATA_CYC_BUSY", .pme_code = 0x50384, .pme_short_desc = "Outbound GX Data utilization (# of cycles data out is valid)", .pme_long_desc = "Outbound GX Data utilization (# of cycles data out is valid)", .pme_event_ids = power6_event_ids[POWER6_PME_PM_GXO_DATA_CYC_BUSY], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_GXO_DATA_CYC_BUSY] }, [ POWER6_PME_PM_DFU_SUBNORM ] = { .pme_name = "PM_DFU_SUBNORM", .pme_code = 0xe0086, .pme_short_desc = "DFU result is a subnormal", .pme_long_desc = "DFU result is a subnormal", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DFU_SUBNORM], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DFU_SUBNORM] }, [ POWER6_PME_PM_FPU_ISSUE_OOO ] = { .pme_name = "PM_FPU_ISSUE_OOO", .pme_code = 0x320c0, .pme_short_desc = "FPU issue out-of-order", .pme_long_desc = "FPU issue out-of-order", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_ISSUE_OOO], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_ISSUE_OOO] }, [ POWER6_PME_PM_LSU_REJECT_ULD_BOTH ] = { .pme_name = "PM_LSU_REJECT_ULD_BOTH", .pme_code = 0x290036, .pme_short_desc = "Unaligned load reject both units", .pme_long_desc = "Unaligned load reject both units", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_ULD_BOTH], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_ULD_BOTH] }, [ POWER6_PME_PM_L2SB_ST_MISS ] = { .pme_name = "PM_L2SB_ST_MISS", .pme_code = 0x5048e, .pme_short_desc = "L2 slice B store misses", .pme_long_desc = "L2 slice B store misses", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SB_ST_MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SB_ST_MISS] }, [ POWER6_PME_PM_DATA_FROM_L25_MOD_CYC ] = { .pme_name = "PM_DATA_FROM_L25_MOD_CYC", .pme_code = 0x400024, .pme_short_desc = "Load latency from L2.5 modified", .pme_long_desc = "Load latency from L2.5 modified", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L25_MOD_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L25_MOD_CYC] }, [ POWER6_PME_PM_INST_PTEG_1ST_HALF ] = { .pme_name = "PM_INST_PTEG_1ST_HALF", .pme_code = 0x910a8, .pme_short_desc = "Instruction table walk matched in first half primary PTEG", .pme_long_desc = "Instruction table walk matched in first half primary PTEG", .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_PTEG_1ST_HALF], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_PTEG_1ST_HALF] }, [ POWER6_PME_PM_DERAT_MISS_16M ] = { .pme_name = "PM_DERAT_MISS_16M", .pme_code = 0x392070, .pme_short_desc = "DERAT misses for 16M page", .pme_long_desc = "A data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DERAT_MISS_16M], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DERAT_MISS_16M] }, [ POWER6_PME_PM_GX_DMA_WRITE ] = { .pme_name = "PM_GX_DMA_WRITE", .pme_code = 0x5038e, .pme_short_desc = "All DMA Write Requests (including dma wrt lgcy)", .pme_long_desc = "All DMA Write Requests (including dma wrt lgcy)", .pme_event_ids = power6_event_ids[POWER6_PME_PM_GX_DMA_WRITE], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_GX_DMA_WRITE] }, [ POWER6_PME_PM_MRK_PTEG_FROM_DL2L3_MOD ] = { .pme_name = "PM_MRK_PTEG_FROM_DL2L3_MOD", .pme_code = 0x412044, .pme_short_desc = "Marked PTEG loaded from distant L2 or L3 modified", .pme_long_desc = "Marked PTEG loaded from distant L2 or L3 modified", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_DL2L3_MOD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_DL2L3_MOD] }, [ POWER6_PME_PM_MEM1_DP_RQ_GLOB_LOC ] = { .pme_name = "PM_MEM1_DP_RQ_GLOB_LOC", .pme_code = 0x50288, .pme_short_desc = "Memory read queue marking cache line double pump state from global to local side 1", .pme_long_desc = "Memory read queue marking cache line double pump state from global to local side 1", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MEM1_DP_RQ_GLOB_LOC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MEM1_DP_RQ_GLOB_LOC] }, [ POWER6_PME_PM_L2SB_LD_REQ_DATA ] = { .pme_name = "PM_L2SB_LD_REQ_DATA", .pme_code = 0x50488, .pme_short_desc = "L2 slice B data load requests", .pme_long_desc = "L2 slice B data load requests", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SB_LD_REQ_DATA], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SB_LD_REQ_DATA] }, [ POWER6_PME_PM_L2SA_LD_MISS_INST ] = { .pme_name = "PM_L2SA_LD_MISS_INST", .pme_code = 0x50582, .pme_short_desc = "L2 slice A instruction load misses", .pme_long_desc = "L2 slice A instruction load misses", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SA_LD_MISS_INST], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SA_LD_MISS_INST] }, [ POWER6_PME_PM_MRK_LSU0_REJECT_L2MISS ] = { .pme_name = "PM_MRK_LSU0_REJECT_L2MISS", .pme_code = 0x930e4, .pme_short_desc = "LSU0 marked L2 miss reject", .pme_long_desc = "LSU0 marked L2 miss reject", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_LSU0_REJECT_L2MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_LSU0_REJECT_L2MISS] }, [ POWER6_PME_PM_MRK_IFU_FIN ] = { .pme_name = "PM_MRK_IFU_FIN", .pme_code = 0x20000a, .pme_short_desc = "Marked instruction IFU processing finished", .pme_long_desc = "Marked instruction IFU processing finished", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_IFU_FIN], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_IFU_FIN] }, [ POWER6_PME_PM_INST_FROM_L3 ] = { .pme_name = "PM_INST_FROM_L3", .pme_code = 0x342040, .pme_short_desc = "Instruction fetched from L3", .pme_long_desc = "An instruction fetch group was fetched from L3. Fetch Groups can contain up to 8 instructions", .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_L3], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_L3] }, [ POWER6_PME_PM_FXU1_FIN ] = { .pme_name = "PM_FXU1_FIN", .pme_code = 0x400016, .pme_short_desc = "FXU1 produced a result", .pme_long_desc = "The Fixed Point unit 1 finished an instruction and produced a result", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FXU1_FIN], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FXU1_FIN] }, [ POWER6_PME_PM_THRD_PRIO_4_CYC ] = { .pme_name = "PM_THRD_PRIO_4_CYC", .pme_code = 0x422046, .pme_short_desc = "Cycles thread running at priority level 4", .pme_long_desc = "Cycles thread running at priority level 4", .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_4_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_4_CYC] }, [ POWER6_PME_PM_MRK_DATA_FROM_L35_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L35_MOD", .pme_code = 0x10304e, .pme_short_desc = "Marked data loaded from L3.5 modified", .pme_long_desc = "Marked data loaded from L3.5 modified", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_L35_MOD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_L35_MOD] }, [ POWER6_PME_PM_LSU_REJECT_SET_MPRED ] = { .pme_name = "PM_LSU_REJECT_SET_MPRED", .pme_code = 0x2a0032, .pme_short_desc = "LSU reject due to mispredicted set", .pme_long_desc = "LSU reject due to mispredicted set", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_SET_MPRED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_SET_MPRED] }, [ POWER6_PME_PM_MRK_DERAT_MISS_16G ] = { .pme_name = "PM_MRK_DERAT_MISS_16G", .pme_code = 0x492044, .pme_short_desc = "Marked DERAT misses for 16G page", .pme_long_desc = "A marked data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DERAT_MISS_16G], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DERAT_MISS_16G] }, [ POWER6_PME_PM_FPU0_FXDIV ] = { .pme_name = "PM_FPU0_FXDIV", .pme_code = 0xc10a0, .pme_short_desc = "FPU0 executed fixed point division", .pme_long_desc = "FPU0 executed fixed point division", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_FXDIV], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_FXDIV] }, [ POWER6_PME_PM_MRK_LSU1_REJECT_UST ] = { .pme_name = "PM_MRK_LSU1_REJECT_UST", .pme_code = 0x930ea, .pme_short_desc = "LSU1 marked unaligned store reject", .pme_long_desc = "LSU1 marked unaligned store reject", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_LSU1_REJECT_UST], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_LSU1_REJECT_UST] }, [ POWER6_PME_PM_FPU_ISSUE_DIV_SQRT_OVERLAP ] = { .pme_name = "PM_FPU_ISSUE_DIV_SQRT_OVERLAP", .pme_code = 0x320cc, .pme_short_desc = "FPU divide/sqrt overlapped with other divide/sqrt", .pme_long_desc = "FPU divide/sqrt overlapped with other divide/sqrt", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_ISSUE_DIV_SQRT_OVERLAP], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_ISSUE_DIV_SQRT_OVERLAP] }, [ POWER6_PME_PM_INST_FROM_L35_SHR ] = { .pme_name = "PM_INST_FROM_L35_SHR", .pme_code = 0x242046, .pme_short_desc = "Instruction fetched from L3.5 shared", .pme_long_desc = "Instruction fetched from L3.5 shared", .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_L35_SHR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_L35_SHR] }, [ POWER6_PME_PM_MRK_LSU_REJECT_LHS ] = { .pme_name = "PM_MRK_LSU_REJECT_LHS", .pme_code = 0x493030, .pme_short_desc = "Marked load hit store reject", .pme_long_desc = "Marked load hit store reject", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_LSU_REJECT_LHS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_LSU_REJECT_LHS] }, [ POWER6_PME_PM_LSU_LMQ_FULL_CYC ] = { .pme_name = "PM_LSU_LMQ_FULL_CYC", .pme_code = 0x810ac, .pme_short_desc = "Cycles LMQ full", .pme_long_desc = "The LMQ was full", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_LMQ_FULL_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_LMQ_FULL_CYC] }, [ POWER6_PME_PM_SYNC_COUNT ] = { .pme_name = "PM_SYNC_COUNT", .pme_code = 0x920cd, .pme_short_desc = "SYNC instructions completed", .pme_long_desc = "SYNC instructions completed", .pme_event_ids = power6_event_ids[POWER6_PME_PM_SYNC_COUNT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_SYNC_COUNT] }, [ POWER6_PME_PM_MEM0_DP_RQ_LOC_GLOB ] = { .pme_name = "PM_MEM0_DP_RQ_LOC_GLOB", .pme_code = 0x50282, .pme_short_desc = "Memory read queue marking cache line double pump state from local to global side 0", .pme_long_desc = "Memory read queue marking cache line double pump state from local to global side 0", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MEM0_DP_RQ_LOC_GLOB], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MEM0_DP_RQ_LOC_GLOB] }, [ POWER6_PME_PM_L2SA_CASTOUT_MOD ] = { .pme_name = "PM_L2SA_CASTOUT_MOD", .pme_code = 0x50680, .pme_short_desc = "L2 slice A castouts - Modified", .pme_long_desc = "L2 slice A castouts - Modified", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SA_CASTOUT_MOD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SA_CASTOUT_MOD] }, [ POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_BOTH_COUNT ] = { .pme_name = "PM_LSU_LMQ_SRQ_EMPTY_BOTH_COUNT", .pme_code = 0x30001d, .pme_short_desc = "Periods both threads LMQ and SRQ empty", .pme_long_desc = "Periods both threads LMQ and SRQ empty", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_BOTH_COUNT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_BOTH_COUNT] }, [ POWER6_PME_PM_PTEG_FROM_MEM_DP ] = { .pme_name = "PM_PTEG_FROM_MEM_DP", .pme_code = 0x11304a, .pme_short_desc = "PTEG loaded from double pump memory", .pme_long_desc = "PTEG loaded from double pump memory", .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_MEM_DP], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_MEM_DP] }, [ POWER6_PME_PM_LSU_REJECT_SLOW ] = { .pme_name = "PM_LSU_REJECT_SLOW", .pme_code = 0x20003e, .pme_short_desc = "LSU slow reject", .pme_long_desc = "LSU slow reject", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_SLOW], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_SLOW] }, [ POWER6_PME_PM_PTEG_FROM_L25_MOD ] = { .pme_name = "PM_PTEG_FROM_L25_MOD", .pme_code = 0x31304e, .pme_short_desc = "PTEG loaded from L2.5 modified", .pme_long_desc = "PTEG loaded from L2.5 modified", .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_L25_MOD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_L25_MOD] }, [ POWER6_PME_PM_THRD_PRIO_7_CYC ] = { .pme_name = "PM_THRD_PRIO_7_CYC", .pme_code = 0x122046, .pme_short_desc = "Cycles thread running at priority level 7", .pme_long_desc = "Cycles thread running at priority level 7", .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_7_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_7_CYC] }, [ POWER6_PME_PM_MRK_PTEG_FROM_RL2L3_SHR ] = { .pme_name = "PM_MRK_PTEG_FROM_RL2L3_SHR", .pme_code = 0x212044, .pme_short_desc = "Marked PTEG loaded from remote L2 or L3 shared", .pme_long_desc = "Marked PTEG loaded from remote L2 or L3 shared", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_RL2L3_SHR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_RL2L3_SHR] }, [ POWER6_PME_PM_ST_REQ_L2 ] = { .pme_name = "PM_ST_REQ_L2", .pme_code = 0x250732, .pme_short_desc = "L2 store requests", .pme_long_desc = "L2 store requests", .pme_event_ids = power6_event_ids[POWER6_PME_PM_ST_REQ_L2], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_ST_REQ_L2] }, [ POWER6_PME_PM_ST_REF_L1 ] = { .pme_name = "PM_ST_REF_L1", .pme_code = 0x80086, .pme_short_desc = "L1 D cache store references", .pme_long_desc = "Total DL1 Store references", .pme_event_ids = power6_event_ids[POWER6_PME_PM_ST_REF_L1], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_ST_REF_L1] }, [ POWER6_PME_PM_FPU_ISSUE_STALL_THRD ] = { .pme_name = "PM_FPU_ISSUE_STALL_THRD", .pme_code = 0x330e0, .pme_short_desc = "FPU issue stalled due to thread resource conflict", .pme_long_desc = "FPU issue stalled due to thread resource conflict", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_ISSUE_STALL_THRD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_ISSUE_STALL_THRD] }, [ POWER6_PME_PM_RUN_COUNT ] = { .pme_name = "PM_RUN_COUNT", .pme_code = 0x10000b, .pme_short_desc = "Run Periods", .pme_long_desc = "Processor Periods gated by the run latch", .pme_event_ids = power6_event_ids[POWER6_PME_PM_RUN_COUNT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_RUN_COUNT] }, [ POWER6_PME_PM_RUN_CYC ] = { .pme_name = "PM_RUN_CYC", .pme_code = 0x10000a, .pme_short_desc = "Run cycles", .pme_long_desc = "Processor Cycles gated by the run latch", .pme_event_ids = power6_event_ids[POWER6_PME_PM_RUN_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_RUN_CYC] }, [ POWER6_PME_PM_PTEG_FROM_RMEM ] = { .pme_name = "PM_PTEG_FROM_RMEM", .pme_code = 0x31304a, .pme_short_desc = "PTEG loaded from remote memory", .pme_long_desc = "PTEG loaded from remote memory", .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_RMEM], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_RMEM] }, [ POWER6_PME_PM_LSU0_LDF ] = { .pme_name = "PM_LSU0_LDF", .pme_code = 0x80084, .pme_short_desc = "LSU0 executed Floating Point load instruction", .pme_long_desc = "A floating point load was executed from LSU unit 0", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_LDF], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_LDF] }, [ POWER6_PME_PM_ST_MISS_L1 ] = { .pme_name = "PM_ST_MISS_L1", .pme_code = 0x80088, .pme_short_desc = "L1 D cache store misses", .pme_long_desc = "A store missed the dcache", .pme_event_ids = power6_event_ids[POWER6_PME_PM_ST_MISS_L1], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_ST_MISS_L1] }, [ POWER6_PME_PM_INST_FROM_DL2L3_SHR ] = { .pme_name = "PM_INST_FROM_DL2L3_SHR", .pme_code = 0x342044, .pme_short_desc = "Instruction fetched from distant L2 or L3 shared", .pme_long_desc = "Instruction fetched from distant L2 or L3 shared", .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_DL2L3_SHR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_DL2L3_SHR] }, [ POWER6_PME_PM_L2SA_IC_INV ] = { .pme_name = "PM_L2SA_IC_INV", .pme_code = 0x50684, .pme_short_desc = "L2 slice A I cache invalidate", .pme_long_desc = "L2 slice A I cache invalidate", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SA_IC_INV], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SA_IC_INV] }, [ POWER6_PME_PM_THRD_ONE_RUN_CYC ] = { .pme_name = "PM_THRD_ONE_RUN_CYC", .pme_code = 0x100016, .pme_short_desc = "One of the threads in run cycles", .pme_long_desc = "One of the threads in run cycles", .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_ONE_RUN_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_ONE_RUN_CYC] }, [ POWER6_PME_PM_L2SB_LD_REQ_INST ] = { .pme_name = "PM_L2SB_LD_REQ_INST", .pme_code = 0x50588, .pme_short_desc = "L2 slice B instruction load requests", .pme_long_desc = "L2 slice B instruction load requests", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SB_LD_REQ_INST], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SB_LD_REQ_INST] }, [ POWER6_PME_PM_MRK_DATA_FROM_L25_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L25_MOD", .pme_code = 0x30304e, .pme_short_desc = "Marked data loaded from L2.5 modified", .pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a marked demand load", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_L25_MOD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_L25_MOD] }, [ POWER6_PME_PM_DPU_HELD_XTHRD ] = { .pme_name = "PM_DPU_HELD_XTHRD", .pme_code = 0x30082, .pme_short_desc = "DISP unit held due to cross thread resource conflicts", .pme_long_desc = "DISP unit held due to cross thread resource conflicts", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_XTHRD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_XTHRD] }, [ POWER6_PME_PM_L2SB_ST_REQ ] = { .pme_name = "PM_L2SB_ST_REQ", .pme_code = 0x5048c, .pme_short_desc = "L2 slice B store requests", .pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A,B,and C.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SB_ST_REQ], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SB_ST_REQ] }, [ POWER6_PME_PM_INST_FROM_L21 ] = { .pme_name = "PM_INST_FROM_L21", .pme_code = 0x242040, .pme_short_desc = "Instruction fetched from private L2 other core", .pme_long_desc = "Instruction fetched from private L2 other core", .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_L21], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_L21] }, [ POWER6_PME_PM_INST_FROM_L3MISS ] = { .pme_name = "PM_INST_FROM_L3MISS", .pme_code = 0x342054, .pme_short_desc = "Instruction fetched missed L3", .pme_long_desc = "Instruction fetched missed L3", .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_L3MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_L3MISS] }, [ POWER6_PME_PM_L3SB_HIT ] = { .pme_name = "PM_L3SB_HIT", .pme_code = 0x5008a, .pme_short_desc = "L3 slice B hits", .pme_long_desc = "L3 slice B hits", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L3SB_HIT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L3SB_HIT] }, [ POWER6_PME_PM_EE_OFF_EXT_INT ] = { .pme_name = "PM_EE_OFF_EXT_INT", .pme_code = 0x230ee, .pme_short_desc = "Cycles MSR(EE) bit off and external interrupt pending", .pme_long_desc = "Cycles MSR(EE) bit off and external interrupt pending", .pme_event_ids = power6_event_ids[POWER6_PME_PM_EE_OFF_EXT_INT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_EE_OFF_EXT_INT] }, [ POWER6_PME_PM_INST_FROM_DL2L3_MOD ] = { .pme_name = "PM_INST_FROM_DL2L3_MOD", .pme_code = 0x442044, .pme_short_desc = "Instruction fetched from distant L2 or L3 modified", .pme_long_desc = "Instruction fetched from distant L2 or L3 modified", .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_DL2L3_MOD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_DL2L3_MOD] }, [ POWER6_PME_PM_PMC6_OVERFLOW ] = { .pme_name = "PM_PMC6_OVERFLOW", .pme_code = 0x300024, .pme_short_desc = "PMC6 Overflow", .pme_long_desc = "PMC6 Overflow", .pme_event_ids = power6_event_ids[POWER6_PME_PM_PMC6_OVERFLOW], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PMC6_OVERFLOW] }, [ POWER6_PME_PM_FPU_FLOP ] = { .pme_name = "PM_FPU_FLOP", .pme_code = 0x1c0032, .pme_short_desc = "FPU executed 1FLOP", .pme_long_desc = " FMA", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_FLOP], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_FLOP] }, [ POWER6_PME_PM_FXU_BUSY ] = { .pme_name = "PM_FXU_BUSY", .pme_code = 0x200050, .pme_short_desc = "FXU busy", .pme_long_desc = "FXU0 and FXU1 are both busy", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FXU_BUSY], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FXU_BUSY] }, [ POWER6_PME_PM_FPU1_FLOP ] = { .pme_name = "PM_FPU1_FLOP", .pme_code = 0xc008e, .pme_short_desc = "FPU1 executed 1FLOP", .pme_long_desc = " FMA", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_FLOP], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_FLOP] }, [ POWER6_PME_PM_IC_RELOAD_SHR ] = { .pme_name = "PM_IC_RELOAD_SHR", .pme_code = 0x4008e, .pme_short_desc = "I cache line reloading to be shared by threads", .pme_long_desc = "I cache line reloading to be shared by threads", .pme_event_ids = power6_event_ids[POWER6_PME_PM_IC_RELOAD_SHR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IC_RELOAD_SHR] }, [ POWER6_PME_PM_INST_TABLEWALK_CYC ] = { .pme_name = "PM_INST_TABLEWALK_CYC", .pme_code = 0x920ca, .pme_short_desc = "Cycles doing instruction tablewalks", .pme_long_desc = "Cycles doing instruction tablewalks", .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_TABLEWALK_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_TABLEWALK_CYC] }, [ POWER6_PME_PM_DATA_FROM_RL2L3_MOD_CYC ] = { .pme_name = "PM_DATA_FROM_RL2L3_MOD_CYC", .pme_code = 0x400028, .pme_short_desc = "Load latency from remote L2 or L3 modified", .pme_long_desc = "Load latency from remote L2 or L3 modified", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_RL2L3_MOD_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_RL2L3_MOD_CYC] }, [ POWER6_PME_PM_THRD_PRIO_DIFF_5or6_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_5or6_CYC", .pme_code = 0x423040, .pme_short_desc = "Cycles thread priority difference is 5 or 6", .pme_long_desc = "Cycles thread priority difference is 5 or 6", .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_DIFF_5or6_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_DIFF_5or6_CYC] }, [ POWER6_PME_PM_IBUF_FULL_CYC ] = { .pme_name = "PM_IBUF_FULL_CYC", .pme_code = 0x40084, .pme_short_desc = "Cycles instruction buffer full", .pme_long_desc = "Cycles instruction buffer full", .pme_event_ids = power6_event_ids[POWER6_PME_PM_IBUF_FULL_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IBUF_FULL_CYC] }, [ POWER6_PME_PM_L2SA_LD_REQ ] = { .pme_name = "PM_L2SA_LD_REQ", .pme_code = 0x50780, .pme_short_desc = "L2 slice A load requests ", .pme_long_desc = "L2 slice A load requests ", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SA_LD_REQ], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SA_LD_REQ] }, [ POWER6_PME_PM_VMX1_LD_WRBACK ] = { .pme_name = "PM_VMX1_LD_WRBACK", .pme_code = 0x6008c, .pme_short_desc = "VMX1 load writeback valid", .pme_long_desc = "VMX1 load writeback valid", .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX1_LD_WRBACK], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX1_LD_WRBACK] }, [ POWER6_PME_PM_MRK_FPU_FIN ] = { .pme_name = "PM_MRK_FPU_FIN", .pme_code = 0x2d0030, .pme_short_desc = "Marked instruction FPU processing finished", .pme_long_desc = "One of the Floating Point Units finished a marked instruction. Instructions that finish may not necessary complete", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_FPU_FIN], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_FPU_FIN] }, [ POWER6_PME_PM_THRD_PRIO_5_CYC ] = { .pme_name = "PM_THRD_PRIO_5_CYC", .pme_code = 0x322046, .pme_short_desc = "Cycles thread running at priority level 5", .pme_long_desc = "Cycles thread running at priority level 5", .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_5_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_5_CYC] }, [ POWER6_PME_PM_DFU_BACK2BACK ] = { .pme_name = "PM_DFU_BACK2BACK", .pme_code = 0xe0082, .pme_short_desc = "DFU back to back operations executed", .pme_long_desc = "DFU back to back operations executed", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DFU_BACK2BACK], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DFU_BACK2BACK] }, [ POWER6_PME_PM_MRK_DATA_FROM_LMEM ] = { .pme_name = "PM_MRK_DATA_FROM_LMEM", .pme_code = 0x40304a, .pme_short_desc = "Marked data loaded from local memory", .pme_long_desc = "Marked data loaded from local memory", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_LMEM], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_LMEM] }, [ POWER6_PME_PM_LSU_REJECT_LHS ] = { .pme_name = "PM_LSU_REJECT_LHS", .pme_code = 0x190032, .pme_short_desc = "Load hit store reject", .pme_long_desc = "Load hit store reject", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_LHS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_LHS] }, [ POWER6_PME_PM_DPU_HELD_SPR ] = { .pme_name = "PM_DPU_HELD_SPR", .pme_code = 0x3008c, .pme_short_desc = "DISP unit held due to MTSPR/MFSPR", .pme_long_desc = "DISP unit held due to MTSPR/MFSPR", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_SPR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_SPR] }, [ POWER6_PME_PM_FREQ_DOWN ] = { .pme_name = "PM_FREQ_DOWN", .pme_code = 0x30003c, .pme_short_desc = "Frequency is being slewed down due to Power Management", .pme_long_desc = "Frequency is being slewed down due to Power Management", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FREQ_DOWN], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FREQ_DOWN] }, [ POWER6_PME_PM_DFU_ENC_BCD_DPD ] = { .pme_name = "PM_DFU_ENC_BCD_DPD", .pme_code = 0xe008a, .pme_short_desc = "DFU Encode BCD to DPD", .pme_long_desc = "DFU Encode BCD to DPD", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DFU_ENC_BCD_DPD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DFU_ENC_BCD_DPD] }, [ POWER6_PME_PM_DPU_HELD_GPR ] = { .pme_name = "PM_DPU_HELD_GPR", .pme_code = 0x20080, .pme_short_desc = "DISP unit held due to GPR dependencies", .pme_long_desc = "DISP unit held due to GPR dependencies", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_GPR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_GPR] }, [ POWER6_PME_PM_LSU0_NCST ] = { .pme_name = "PM_LSU0_NCST", .pme_code = 0x820cc, .pme_short_desc = "LSU0 non-cachable stores", .pme_long_desc = "LSU0 non-cachable stores", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_NCST], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_NCST] }, [ POWER6_PME_PM_MRK_INST_ISSUED ] = { .pme_name = "PM_MRK_INST_ISSUED", .pme_code = 0x10001c, .pme_short_desc = "Marked instruction issued", .pme_long_desc = "Marked instruction issued", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_INST_ISSUED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_INST_ISSUED] }, [ POWER6_PME_PM_INST_FROM_RL2L3_SHR ] = { .pme_name = "PM_INST_FROM_RL2L3_SHR", .pme_code = 0x242044, .pme_short_desc = "Instruction fetched from remote L2 or L3 shared", .pme_long_desc = "Instruction fetched from remote L2 or L3 shared", .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_RL2L3_SHR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_RL2L3_SHR] }, [ POWER6_PME_PM_FPU_DENORM ] = { .pme_name = "PM_FPU_DENORM", .pme_code = 0x2c1034, .pme_short_desc = "FPU received denormalized data", .pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized. Combined Unit 0 + Unit 1", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_DENORM], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_DENORM] }, [ POWER6_PME_PM_PTEG_FROM_L3MISS ] = { .pme_name = "PM_PTEG_FROM_L3MISS", .pme_code = 0x313028, .pme_short_desc = "PTEG loaded from L3 miss", .pme_long_desc = "PTEG loaded from L3 miss", .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_L3MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_L3MISS] }, [ POWER6_PME_PM_RUN_PURR ] = { .pme_name = "PM_RUN_PURR", .pme_code = 0x4000f4, .pme_short_desc = "Run PURR Event", .pme_long_desc = "Run PURR Event", .pme_event_ids = power6_event_ids[POWER6_PME_PM_RUN_PURR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_RUN_PURR] }, [ POWER6_PME_PM_MRK_VMX0_LD_WRBACK ] = { .pme_name = "PM_MRK_VMX0_LD_WRBACK", .pme_code = 0x60086, .pme_short_desc = "Marked VMX0 load writeback valid", .pme_long_desc = "Marked VMX0 load writeback valid", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_VMX0_LD_WRBACK], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_VMX0_LD_WRBACK] }, [ POWER6_PME_PM_L2_MISS ] = { .pme_name = "PM_L2_MISS", .pme_code = 0x250532, .pme_short_desc = "L2 cache misses", .pme_long_desc = "L2 cache misses", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2_MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2_MISS] }, [ POWER6_PME_PM_MRK_DATA_FROM_L3 ] = { .pme_name = "PM_MRK_DATA_FROM_L3", .pme_code = 0x303048, .pme_short_desc = "Marked data loaded from L3", .pme_long_desc = "DL1 was reloaded from the local L3 due to a marked demand load", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_L3], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_L3] }, [ POWER6_PME_PM_MRK_LSU1_REJECT_LHS ] = { .pme_name = "PM_MRK_LSU1_REJECT_LHS", .pme_code = 0x930ee, .pme_short_desc = "LSU1 marked load hit store reject", .pme_long_desc = "LSU1 marked load hit store reject", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_LSU1_REJECT_LHS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_LSU1_REJECT_LHS] }, [ POWER6_PME_PM_L2SB_LD_MISS_INST ] = { .pme_name = "PM_L2SB_LD_MISS_INST", .pme_code = 0x5058a, .pme_short_desc = "L2 slice B instruction load misses", .pme_long_desc = "L2 slice B instruction load misses", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SB_LD_MISS_INST], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SB_LD_MISS_INST] }, [ POWER6_PME_PM_PTEG_FROM_RL2L3_SHR ] = { .pme_name = "PM_PTEG_FROM_RL2L3_SHR", .pme_code = 0x21304c, .pme_short_desc = "PTEG loaded from remote L2 or L3 shared", .pme_long_desc = "PTEG loaded from remote L2 or L3 shared", .pme_event_ids = power6_event_ids[POWER6_PME_PM_PTEG_FROM_RL2L3_SHR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PTEG_FROM_RL2L3_SHR] }, [ POWER6_PME_PM_MRK_DERAT_MISS_64K ] = { .pme_name = "PM_MRK_DERAT_MISS_64K", .pme_code = 0x192044, .pme_short_desc = "Marked DERAT misses for 64K page", .pme_long_desc = "A marked data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DERAT_MISS_64K], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DERAT_MISS_64K] }, [ POWER6_PME_PM_LWSYNC ] = { .pme_name = "PM_LWSYNC", .pme_code = 0x810ae, .pme_short_desc = "Isync instruction completed", .pme_long_desc = "Isync instruction completed", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LWSYNC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LWSYNC] }, [ POWER6_PME_PM_FPU1_FXMULT ] = { .pme_name = "PM_FPU1_FXMULT", .pme_code = 0xd008e, .pme_short_desc = "FPU1 executed fixed point multiplication", .pme_long_desc = "FPU1 executed fixed point multiplication", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_FXMULT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_FXMULT] }, [ POWER6_PME_PM_MEM0_DP_CL_WR_GLOB ] = { .pme_name = "PM_MEM0_DP_CL_WR_GLOB", .pme_code = 0x50284, .pme_short_desc = "cacheline write setting dp to global side 0", .pme_long_desc = "cacheline write setting dp to global side 0", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MEM0_DP_CL_WR_GLOB], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MEM0_DP_CL_WR_GLOB] }, [ POWER6_PME_PM_LSU0_REJECT_PARTIAL_SECTOR ] = { .pme_name = "PM_LSU0_REJECT_PARTIAL_SECTOR", .pme_code = 0xa0086, .pme_short_desc = "LSU0 reject due to partial sector valid", .pme_long_desc = "LSU0 reject due to partial sector valid", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_REJECT_PARTIAL_SECTOR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_REJECT_PARTIAL_SECTOR] }, [ POWER6_PME_PM_INST_IMC_MATCH_CMPL ] = { .pme_name = "PM_INST_IMC_MATCH_CMPL", .pme_code = 0x1000f0, .pme_short_desc = "IMC matched instructions completed", .pme_long_desc = "Number of instructions resulting from the marked instructions expansion that completed.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_IMC_MATCH_CMPL], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_IMC_MATCH_CMPL] }, [ POWER6_PME_PM_DPU_HELD_THERMAL ] = { .pme_name = "PM_DPU_HELD_THERMAL", .pme_code = 0x10002a, .pme_short_desc = "DISP unit held due to thermal condition", .pme_long_desc = "DISP unit held due to thermal condition", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_THERMAL], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_THERMAL] }, [ POWER6_PME_PM_FPU_FRSP ] = { .pme_name = "PM_FPU_FRSP", .pme_code = 0x2d1034, .pme_short_desc = "FPU executed FRSP instruction", .pme_long_desc = "FPU executed FRSP instruction", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_FRSP], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_FRSP] }, [ POWER6_PME_PM_MRK_INST_FIN ] = { .pme_name = "PM_MRK_INST_FIN", .pme_code = 0x30000a, .pme_short_desc = "Marked instruction finished", .pme_long_desc = "One of the execution units finished a marked instruction. Instructions that finish may not necessary complete", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_INST_FIN], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_INST_FIN] }, [ POWER6_PME_PM_MRK_PTEG_FROM_DL2L3_SHR ] = { .pme_name = "PM_MRK_PTEG_FROM_DL2L3_SHR", .pme_code = 0x312044, .pme_short_desc = "Marked PTEG loaded from distant L2 or L3 shared", .pme_long_desc = "Marked PTEG loaded from distant L2 or L3 shared", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_DL2L3_SHR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_DL2L3_SHR] }, [ POWER6_PME_PM_MRK_DTLB_REF ] = { .pme_name = "PM_MRK_DTLB_REF", .pme_code = 0x920c0, .pme_short_desc = "Marked Data TLB reference", .pme_long_desc = "Marked Data TLB reference", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DTLB_REF], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DTLB_REF] }, [ POWER6_PME_PM_MRK_PTEG_FROM_L25_SHR ] = { .pme_name = "PM_MRK_PTEG_FROM_L25_SHR", .pme_code = 0x412046, .pme_short_desc = "Marked PTEG loaded from L2.5 shared", .pme_long_desc = "Marked PTEG loaded from L2.5 shared", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_L25_SHR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_L25_SHR] }, [ POWER6_PME_PM_DPU_HELD_LSU ] = { .pme_name = "PM_DPU_HELD_LSU", .pme_code = 0x210a2, .pme_short_desc = "DISP unit held due to LSU move or invalidate SLB and SR", .pme_long_desc = "DISP unit held due to LSU move or invalidate SLB and SR", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_LSU], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_LSU] }, [ POWER6_PME_PM_FPU_FSQRT_FDIV ] = { .pme_name = "PM_FPU_FSQRT_FDIV", .pme_code = 0x2c0032, .pme_short_desc = "FPU executed FSQRT or FDIV instruction", .pme_long_desc = "FPU executed FSQRT or FDIV instruction", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_FSQRT_FDIV], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_FSQRT_FDIV] }, [ POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_COUNT ] = { .pme_name = "PM_LSU_LMQ_SRQ_EMPTY_COUNT", .pme_code = 0x20001d, .pme_short_desc = "Periods LMQ and SRQ empty", .pme_long_desc = "Periods when both the LMQ and SRQ are empty (LSU is idle)", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_COUNT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_COUNT] }, [ POWER6_PME_PM_DATA_PTEG_SECONDARY ] = { .pme_name = "PM_DATA_PTEG_SECONDARY", .pme_code = 0x910a4, .pme_short_desc = "Data table walk matched in secondary PTEG", .pme_long_desc = "Data table walk matched in secondary PTEG", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_PTEG_SECONDARY], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_PTEG_SECONDARY] }, [ POWER6_PME_PM_FPU1_FEST ] = { .pme_name = "PM_FPU1_FEST", .pme_code = 0xd10ae, .pme_short_desc = "FPU1 executed FEST instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. ", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_FEST], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_FEST] }, [ POWER6_PME_PM_L2SA_LD_HIT ] = { .pme_name = "PM_L2SA_LD_HIT", .pme_code = 0x50782, .pme_short_desc = "L2 slice A load hits", .pme_long_desc = "L2 slice A load hits", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SA_LD_HIT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SA_LD_HIT] }, [ POWER6_PME_PM_DATA_FROM_MEM_DP_CYC ] = { .pme_name = "PM_DATA_FROM_MEM_DP_CYC", .pme_code = 0x40002e, .pme_short_desc = "Load latency from double pump memory", .pme_long_desc = "Load latency from double pump memory", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_MEM_DP_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_MEM_DP_CYC] }, [ POWER6_PME_PM_BR_MPRED_CCACHE ] = { .pme_name = "PM_BR_MPRED_CCACHE", .pme_code = 0x410ae, .pme_short_desc = "Branch misprediction due to count cache prediction", .pme_long_desc = "Branch misprediction due to count cache prediction", .pme_event_ids = power6_event_ids[POWER6_PME_PM_BR_MPRED_CCACHE], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_BR_MPRED_CCACHE] }, [ POWER6_PME_PM_DPU_HELD_COUNT ] = { .pme_name = "PM_DPU_HELD_COUNT", .pme_code = 0x200005, .pme_short_desc = "Periods DISP unit held", .pme_long_desc = "Dispatch unit held", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_COUNT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_COUNT] }, [ POWER6_PME_PM_LSU1_REJECT_SET_MPRED ] = { .pme_name = "PM_LSU1_REJECT_SET_MPRED", .pme_code = 0xa008c, .pme_short_desc = "LSU1 reject due to mispredicted set", .pme_long_desc = "LSU1 reject due to mispredicted set", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU1_REJECT_SET_MPRED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU1_REJECT_SET_MPRED] }, [ POWER6_PME_PM_FPU_ISSUE_2 ] = { .pme_name = "PM_FPU_ISSUE_2", .pme_code = 0x320ca, .pme_short_desc = "FPU issue 2 per cycle", .pme_long_desc = "FPU issue 2 per cycle", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_ISSUE_2], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_ISSUE_2] }, [ POWER6_PME_PM_LSU1_REJECT_L2_CORR ] = { .pme_name = "PM_LSU1_REJECT_L2_CORR", .pme_code = 0xa10a8, .pme_short_desc = "LSU1 reject due to L2 correctable error", .pme_long_desc = "LSU1 reject due to L2 correctable error", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU1_REJECT_L2_CORR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU1_REJECT_L2_CORR] }, [ POWER6_PME_PM_MRK_PTEG_FROM_DMEM ] = { .pme_name = "PM_MRK_PTEG_FROM_DMEM", .pme_code = 0x212042, .pme_short_desc = "Marked PTEG loaded from distant memory", .pme_long_desc = "Marked PTEG loaded from distant memory", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_DMEM], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_DMEM] }, [ POWER6_PME_PM_MEM1_DP_RQ_LOC_GLOB ] = { .pme_name = "PM_MEM1_DP_RQ_LOC_GLOB", .pme_code = 0x5028a, .pme_short_desc = "Memory read queue marking cache line double pump state from local to global side 1", .pme_long_desc = "Memory read queue marking cache line double pump state from local to global side 1", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MEM1_DP_RQ_LOC_GLOB], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MEM1_DP_RQ_LOC_GLOB] }, [ POWER6_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_minus1or2_CYC", .pme_code = 0x223046, .pme_short_desc = "Cycles thread priority difference is -1 or -2", .pme_long_desc = "Cycles thread priority difference is -1 or -2", .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC] }, [ POWER6_PME_PM_THRD_PRIO_0_CYC ] = { .pme_name = "PM_THRD_PRIO_0_CYC", .pme_code = 0x122040, .pme_short_desc = "Cycles thread running at priority level 0", .pme_long_desc = "Cycles thread running at priority level 0", .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_0_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_0_CYC] }, [ POWER6_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { .pme_name = "PM_FXU0_BUSY_FXU1_IDLE", .pme_code = 0x300050, .pme_short_desc = "FXU0 busy FXU1 idle", .pme_long_desc = "FXU0 is busy while FXU1 was idle", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FXU0_BUSY_FXU1_IDLE], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FXU0_BUSY_FXU1_IDLE] }, [ POWER6_PME_PM_LSU1_REJECT_DERAT_MPRED ] = { .pme_name = "PM_LSU1_REJECT_DERAT_MPRED", .pme_code = 0xa008a, .pme_short_desc = "LSU1 reject due to mispredicted DERAT", .pme_long_desc = "LSU1 reject due to mispredicted DERAT", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU1_REJECT_DERAT_MPRED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU1_REJECT_DERAT_MPRED] }, [ POWER6_PME_PM_MRK_VMX1_LD_WRBACK ] = { .pme_name = "PM_MRK_VMX1_LD_WRBACK", .pme_code = 0x6008e, .pme_short_desc = "Marked VMX1 load writeback valid", .pme_long_desc = "Marked VMX1 load writeback valid", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_VMX1_LD_WRBACK], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_VMX1_LD_WRBACK] }, [ POWER6_PME_PM_DATA_FROM_RL2L3_SHR_CYC ] = { .pme_name = "PM_DATA_FROM_RL2L3_SHR_CYC", .pme_code = 0x200028, .pme_short_desc = "Load latency from remote L2 or L3 shared", .pme_long_desc = "Load latency from remote L2 or L3 shared", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_RL2L3_SHR_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_RL2L3_SHR_CYC] }, [ POWER6_PME_PM_IERAT_MISS_16M ] = { .pme_name = "PM_IERAT_MISS_16M", .pme_code = 0x292076, .pme_short_desc = "IERAT misses for 16M page", .pme_long_desc = "IERAT misses for 16M page", .pme_event_ids = power6_event_ids[POWER6_PME_PM_IERAT_MISS_16M], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IERAT_MISS_16M] }, [ POWER6_PME_PM_MRK_DATA_FROM_MEM_DP ] = { .pme_name = "PM_MRK_DATA_FROM_MEM_DP", .pme_code = 0x10304a, .pme_short_desc = "Marked data loaded from double pump memory", .pme_long_desc = "Marked data loaded from double pump memory", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_MEM_DP], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_MEM_DP] }, [ POWER6_PME_PM_LARX_L1HIT ] = { .pme_name = "PM_LARX_L1HIT", .pme_code = 0x830e2, .pme_short_desc = "larx hits in L1", .pme_long_desc = "larx hits in L1", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LARX_L1HIT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LARX_L1HIT] }, [ POWER6_PME_PM_L2_ST_MISS_DATA ] = { .pme_name = "PM_L2_ST_MISS_DATA", .pme_code = 0x150432, .pme_short_desc = "L2 data store misses", .pme_long_desc = "L2 data store misses", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2_ST_MISS_DATA], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2_ST_MISS_DATA] }, [ POWER6_PME_PM_FPU_ST_FOLDED ] = { .pme_name = "PM_FPU_ST_FOLDED", .pme_code = 0x3d1030, .pme_short_desc = "FPU folded store", .pme_long_desc = "FPU folded store", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_ST_FOLDED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_ST_FOLDED] }, [ POWER6_PME_PM_MRK_DATA_FROM_L35_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L35_SHR", .pme_code = 0x20304e, .pme_short_desc = "Marked data loaded from L3.5 shared", .pme_long_desc = "Marked data loaded from L3.5 shared", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_L35_SHR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_L35_SHR] }, [ POWER6_PME_PM_DPU_HELD_MULT_GPR ] = { .pme_name = "PM_DPU_HELD_MULT_GPR", .pme_code = 0x210aa, .pme_short_desc = "DISP unit held due to multiple/divide multiply/divide GPR dependencies", .pme_long_desc = "DISP unit held due to multiple/divide multiply/divide GPR dependencies", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_MULT_GPR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_MULT_GPR] }, [ POWER6_PME_PM_FPU0_1FLOP ] = { .pme_name = "PM_FPU0_1FLOP", .pme_code = 0xc0080, .pme_short_desc = "FPU0 executed add", .pme_long_desc = " mult", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_1FLOP], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_1FLOP] }, [ POWER6_PME_PM_IERAT_MISS_16G ] = { .pme_name = "PM_IERAT_MISS_16G", .pme_code = 0x192076, .pme_short_desc = "IERAT misses for 16G page", .pme_long_desc = "IERAT misses for 16G page", .pme_event_ids = power6_event_ids[POWER6_PME_PM_IERAT_MISS_16G], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IERAT_MISS_16G] }, [ POWER6_PME_PM_IC_PREF_WRITE ] = { .pme_name = "PM_IC_PREF_WRITE", .pme_code = 0x430e0, .pme_short_desc = "Instruction prefetch written into I cache", .pme_long_desc = "Instruction prefetch written into I cache", .pme_event_ids = power6_event_ids[POWER6_PME_PM_IC_PREF_WRITE], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IC_PREF_WRITE] }, [ POWER6_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_minus5or6_CYC", .pme_code = 0x423046, .pme_short_desc = "Cycles thread priority difference is -5 or -6", .pme_long_desc = "Cycles thread priority difference is -5 or -6", .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC] }, [ POWER6_PME_PM_FPU0_FIN ] = { .pme_name = "PM_FPU0_FIN", .pme_code = 0xd0080, .pme_short_desc = "FPU0 produced a result", .pme_long_desc = "fp0 finished, produced a result This only indicates finish, not completion. ", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_FIN], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_FIN] }, [ POWER6_PME_PM_DATA_FROM_L2_CYC ] = { .pme_name = "PM_DATA_FROM_L2_CYC", .pme_code = 0x200020, .pme_short_desc = "Load latency from L2", .pme_long_desc = "Load latency from L2", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L2_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L2_CYC] }, [ POWER6_PME_PM_DERAT_REF_16G ] = { .pme_name = "PM_DERAT_REF_16G", .pme_code = 0x482070, .pme_short_desc = "DERAT reference for 16G page", .pme_long_desc = "DERAT reference for 16G page", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DERAT_REF_16G], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DERAT_REF_16G] }, [ POWER6_PME_PM_BR_PRED ] = { .pme_name = "PM_BR_PRED", .pme_code = 0x410a0, .pme_short_desc = "A conditional branch was predicted", .pme_long_desc = "A conditional branch was predicted", .pme_event_ids = power6_event_ids[POWER6_PME_PM_BR_PRED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_BR_PRED] }, [ POWER6_PME_PM_VMX1_LD_ISSUED ] = { .pme_name = "PM_VMX1_LD_ISSUED", .pme_code = 0x6008a, .pme_short_desc = "VMX1 load issued", .pme_long_desc = "VMX1 load issued", .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX1_LD_ISSUED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX1_LD_ISSUED] }, [ POWER6_PME_PM_L2SB_CASTOUT_MOD ] = { .pme_name = "PM_L2SB_CASTOUT_MOD", .pme_code = 0x50688, .pme_short_desc = "L2 slice B castouts - Modified", .pme_long_desc = "L2 slice B castouts - Modified", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SB_CASTOUT_MOD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SB_CASTOUT_MOD] }, [ POWER6_PME_PM_INST_FROM_DMEM ] = { .pme_name = "PM_INST_FROM_DMEM", .pme_code = 0x242042, .pme_short_desc = "Instruction fetched from distant memory", .pme_long_desc = "Instruction fetched from distant memory", .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_DMEM], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_DMEM] }, [ POWER6_PME_PM_DATA_FROM_L35_SHR_CYC ] = { .pme_name = "PM_DATA_FROM_L35_SHR_CYC", .pme_code = 0x200026, .pme_short_desc = "Load latency from L3.5 shared", .pme_long_desc = "Load latency from L3.5 shared", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L35_SHR_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L35_SHR_CYC] }, [ POWER6_PME_PM_LSU0_NCLD ] = { .pme_name = "PM_LSU0_NCLD", .pme_code = 0x820ca, .pme_short_desc = "LSU0 non-cacheable loads", .pme_long_desc = "LSU0 non-cacheable loads", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_NCLD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_NCLD] }, [ POWER6_PME_PM_FAB_RETRY_NODE_PUMP ] = { .pme_name = "PM_FAB_RETRY_NODE_PUMP", .pme_code = 0x5018a, .pme_short_desc = "Retry of a node pump", .pme_long_desc = " locally mastered", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FAB_RETRY_NODE_PUMP], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FAB_RETRY_NODE_PUMP] }, [ POWER6_PME_PM_VMX0_INST_ISSUED ] = { .pme_name = "PM_VMX0_INST_ISSUED", .pme_code = 0x60080, .pme_short_desc = "VMX0 instruction issued", .pme_long_desc = "VMX0 instruction issued", .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX0_INST_ISSUED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX0_INST_ISSUED] }, [ POWER6_PME_PM_DATA_FROM_L25_MOD ] = { .pme_name = "PM_DATA_FROM_L25_MOD", .pme_code = 0x30005a, .pme_short_desc = "Data loaded from L2.5 modified", .pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a demand load", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L25_MOD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L25_MOD] }, [ POWER6_PME_PM_DPU_HELD_ITLB_ISLB ] = { .pme_name = "PM_DPU_HELD_ITLB_ISLB", .pme_code = 0x210a4, .pme_short_desc = "DISP unit held due to SLB or TLB invalidates ", .pme_long_desc = "DISP unit held due to SLB or TLB invalidates ", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_ITLB_ISLB], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_ITLB_ISLB] }, [ POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_LMQ_SRQ_EMPTY_CYC", .pme_code = 0x20001c, .pme_short_desc = "Cycles LMQ and SRQ empty", .pme_long_desc = "Cycles when both the LMQ and SRQ are empty (LSU is idle)", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC] }, [ POWER6_PME_PM_THRD_CONC_RUN_INST ] = { .pme_name = "PM_THRD_CONC_RUN_INST", .pme_code = 0x300026, .pme_short_desc = "Concurrent run instructions", .pme_long_desc = "Concurrent run instructions", .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_CONC_RUN_INST], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_CONC_RUN_INST] }, [ POWER6_PME_PM_MRK_PTEG_FROM_L2 ] = { .pme_name = "PM_MRK_PTEG_FROM_L2", .pme_code = 0x112040, .pme_short_desc = "Marked PTEG loaded from L2.5 modified", .pme_long_desc = "Marked PTEG loaded from L2.5 modified", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_L2], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_L2] }, [ POWER6_PME_PM_PURR ] = { .pme_name = "PM_PURR", .pme_code = 0x10000e, .pme_short_desc = "PURR Event", .pme_long_desc = "PURR Event", .pme_event_ids = power6_event_ids[POWER6_PME_PM_PURR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PURR] }, [ POWER6_PME_PM_DERAT_MISS_64K ] = { .pme_name = "PM_DERAT_MISS_64K", .pme_code = 0x292070, .pme_short_desc = "DERAT misses for 64K page", .pme_long_desc = "A data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DERAT_MISS_64K], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DERAT_MISS_64K] }, [ POWER6_PME_PM_PMC2_REWIND ] = { .pme_name = "PM_PMC2_REWIND", .pme_code = 0x300020, .pme_short_desc = "PMC2 rewind event", .pme_long_desc = "PMC2 rewind event", .pme_event_ids = power6_event_ids[POWER6_PME_PM_PMC2_REWIND], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PMC2_REWIND] }, [ POWER6_PME_PM_INST_FROM_L2 ] = { .pme_name = "PM_INST_FROM_L2", .pme_code = 0x142040, .pme_short_desc = "Instructions fetched from L2", .pme_long_desc = "An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions", .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_L2], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_L2] }, [ POWER6_PME_PM_INST_DISP ] = { .pme_name = "PM_INST_DISP", .pme_code = 0x200012, .pme_short_desc = "Instructions dispatched", .pme_long_desc = "The ISU sends the number of instructions dispatched.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_DISP], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_DISP] }, [ POWER6_PME_PM_DATA_FROM_L25_SHR ] = { .pme_name = "PM_DATA_FROM_L25_SHR", .pme_code = 0x40005a, .pme_short_desc = "Data loaded from L2.5 shared", .pme_long_desc = "DL1 was reloaded with shared (T or SL) data from the L2 of a chip on this MCM due to a demand load", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L25_SHR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L25_SHR] }, [ POWER6_PME_PM_L1_DCACHE_RELOAD_VALID ] = { .pme_name = "PM_L1_DCACHE_RELOAD_VALID", .pme_code = 0x3000f6, .pme_short_desc = "L1 reload data source valid", .pme_long_desc = "The data source information is valid", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L1_DCACHE_RELOAD_VALID], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L1_DCACHE_RELOAD_VALID] }, [ POWER6_PME_PM_LSU1_REJECT_UST ] = { .pme_name = "PM_LSU1_REJECT_UST", .pme_code = 0x9008a, .pme_short_desc = "LSU1 unaligned store reject", .pme_long_desc = "LSU1 unaligned store reject", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU1_REJECT_UST], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU1_REJECT_UST] }, [ POWER6_PME_PM_FAB_ADDR_COLLISION ] = { .pme_name = "PM_FAB_ADDR_COLLISION", .pme_code = 0x5018e, .pme_short_desc = "local node launch collision with off-node address ", .pme_long_desc = "local node launch collision with off-node address ", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FAB_ADDR_COLLISION], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FAB_ADDR_COLLISION] }, [ POWER6_PME_PM_MRK_FXU_FIN ] = { .pme_name = "PM_MRK_FXU_FIN", .pme_code = 0x20001a, .pme_short_desc = "Marked instruction FXU processing finished", .pme_long_desc = "The fixed point units (Unit 0 + Unit 1) finished a marked instruction. Instructions that finish may not necessary complete.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_FXU_FIN], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_FXU_FIN] }, [ POWER6_PME_PM_LSU0_REJECT_UST ] = { .pme_name = "PM_LSU0_REJECT_UST", .pme_code = 0x90082, .pme_short_desc = "LSU0 unaligned store reject", .pme_long_desc = "LSU0 unaligned store reject", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_REJECT_UST], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_REJECT_UST] }, [ POWER6_PME_PM_PMC4_OVERFLOW ] = { .pme_name = "PM_PMC4_OVERFLOW", .pme_code = 0x100014, .pme_short_desc = "PMC4 Overflow", .pme_long_desc = "PMC4 Overflow", .pme_event_ids = power6_event_ids[POWER6_PME_PM_PMC4_OVERFLOW], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_PMC4_OVERFLOW] }, [ POWER6_PME_PM_MRK_PTEG_FROM_L3 ] = { .pme_name = "PM_MRK_PTEG_FROM_L3", .pme_code = 0x312040, .pme_short_desc = "Marked PTEG loaded from L3", .pme_long_desc = "Marked PTEG loaded from L3", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_L3], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_L3] }, [ POWER6_PME_PM_INST_FROM_L2MISS ] = { .pme_name = "PM_INST_FROM_L2MISS", .pme_code = 0x442054, .pme_short_desc = "Instructions fetched missed L2", .pme_long_desc = "An instruction fetch group was fetched from beyond L2.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_L2MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_L2MISS] }, [ POWER6_PME_PM_L2SB_ST_HIT ] = { .pme_name = "PM_L2SB_ST_HIT", .pme_code = 0x5078e, .pme_short_desc = "L2 slice B store hits", .pme_long_desc = "A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A,B, and C.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SB_ST_HIT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SB_ST_HIT] }, [ POWER6_PME_PM_DPU_WT_IC_MISS_COUNT ] = { .pme_name = "PM_DPU_WT_IC_MISS_COUNT", .pme_code = 0x20000d, .pme_short_desc = "Periods DISP unit is stalled due to I cache miss", .pme_long_desc = "Periods DISP unit is stalled due to I cache miss", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_WT_IC_MISS_COUNT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_WT_IC_MISS_COUNT] }, [ POWER6_PME_PM_MRK_DATA_FROM_DL2L3_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_DL2L3_SHR", .pme_code = 0x30304c, .pme_short_desc = "Marked data loaded from distant L2 or L3 shared", .pme_long_desc = "Marked data loaded from distant L2 or L3 shared", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_DL2L3_SHR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_DL2L3_SHR] }, [ POWER6_PME_PM_MRK_PTEG_FROM_L35_MOD ] = { .pme_name = "PM_MRK_PTEG_FROM_L35_MOD", .pme_code = 0x112046, .pme_short_desc = "Marked PTEG loaded from L3.5 modified", .pme_long_desc = "Marked PTEG loaded from L3.5 modified", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_L35_MOD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_L35_MOD] }, [ POWER6_PME_PM_FPU1_FPSCR ] = { .pme_name = "PM_FPU1_FPSCR", .pme_code = 0xd008c, .pme_short_desc = "FPU1 executed FPSCR instruction", .pme_long_desc = "FPU1 executed FPSCR instruction", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_FPSCR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_FPSCR] }, [ POWER6_PME_PM_LSU_REJECT_UST ] = { .pme_name = "PM_LSU_REJECT_UST", .pme_code = 0x290030, .pme_short_desc = "Unaligned store reject", .pme_long_desc = "Unaligned store reject", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_UST], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_UST] }, [ POWER6_PME_PM_LSU0_DERAT_MISS ] = { .pme_name = "PM_LSU0_DERAT_MISS", .pme_code = 0x910a6, .pme_short_desc = "LSU0 DERAT misses", .pme_long_desc = "A data request (load or store) from LSU Unit 0 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_DERAT_MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_DERAT_MISS] }, [ POWER6_PME_PM_MRK_PTEG_FROM_MEM_DP ] = { .pme_name = "PM_MRK_PTEG_FROM_MEM_DP", .pme_code = 0x112042, .pme_short_desc = "Marked PTEG loaded from double pump memory", .pme_long_desc = "Marked PTEG loaded from double pump memory", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_MEM_DP], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_MEM_DP] }, [ POWER6_PME_PM_MRK_DATA_FROM_L2 ] = { .pme_name = "PM_MRK_DATA_FROM_L2", .pme_code = 0x103048, .pme_short_desc = "Marked data loaded from L2", .pme_long_desc = "DL1 was reloaded from the local L2 due to a marked demand load", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_L2], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_L2] }, [ POWER6_PME_PM_FPU0_FSQRT_FDIV ] = { .pme_name = "PM_FPU0_FSQRT_FDIV", .pme_code = 0xc0084, .pme_short_desc = "FPU0 executed FSQRT or FDIV instruction", .pme_long_desc = "FPU0 executed FSQRT or FDIV instruction", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU0_FSQRT_FDIV], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU0_FSQRT_FDIV] }, [ POWER6_PME_PM_DPU_HELD_FXU_SOPS ] = { .pme_name = "PM_DPU_HELD_FXU_SOPS", .pme_code = 0x30088, .pme_short_desc = "DISP unit held due to FXU slow ops (mtmsr", .pme_long_desc = " scv", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_FXU_SOPS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_FXU_SOPS] }, [ POWER6_PME_PM_MRK_FPU0_FIN ] = { .pme_name = "PM_MRK_FPU0_FIN", .pme_code = 0xd0082, .pme_short_desc = "Marked instruction FPU0 processing finished", .pme_long_desc = "Marked instruction FPU0 processing finished", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_FPU0_FIN], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_FPU0_FIN] }, [ POWER6_PME_PM_L2SB_LD_MISS_DATA ] = { .pme_name = "PM_L2SB_LD_MISS_DATA", .pme_code = 0x5048a, .pme_short_desc = "L2 slice B data load misses", .pme_long_desc = "L2 slice B data load misses", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L2SB_LD_MISS_DATA], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L2SB_LD_MISS_DATA] }, [ POWER6_PME_PM_LSU_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_SRQ_EMPTY_CYC", .pme_code = 0x40001c, .pme_short_desc = "Cycles SRQ empty", .pme_long_desc = "The Store Request Queue is empty", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_SRQ_EMPTY_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_SRQ_EMPTY_CYC] }, [ POWER6_PME_PM_1PLUS_PPC_DISP ] = { .pme_name = "PM_1PLUS_PPC_DISP", .pme_code = 0x100012, .pme_short_desc = "Cycles at least one instruction dispatched", .pme_long_desc = "Cycles at least one instruction dispatched", .pme_event_ids = power6_event_ids[POWER6_PME_PM_1PLUS_PPC_DISP], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_1PLUS_PPC_DISP] }, [ POWER6_PME_PM_VMX_ST_ISSUED ] = { .pme_name = "PM_VMX_ST_ISSUED", .pme_code = 0xb0080, .pme_short_desc = "VMX store issued", .pme_long_desc = "VMX store issued", .pme_event_ids = power6_event_ids[POWER6_PME_PM_VMX_ST_ISSUED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_VMX_ST_ISSUED] }, [ POWER6_PME_PM_DATA_FROM_L2MISS ] = { .pme_name = "PM_DATA_FROM_L2MISS", .pme_code = 0x2000fe, .pme_short_desc = "Data loaded missed L2", .pme_long_desc = "DL1 was reloaded from beyond L2.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L2MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L2MISS] }, [ POWER6_PME_PM_LSU0_REJECT_ULD ] = { .pme_name = "PM_LSU0_REJECT_ULD", .pme_code = 0x90080, .pme_short_desc = "LSU0 unaligned load reject", .pme_long_desc = "LSU0 unaligned load reject", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_REJECT_ULD], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_REJECT_ULD] }, [ POWER6_PME_PM_SUSPENDED ] = { .pme_name = "PM_SUSPENDED", .pme_code = 0x0, .pme_short_desc = "Suspended", .pme_long_desc = "Suspended", .pme_event_ids = power6_event_ids[POWER6_PME_PM_SUSPENDED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_SUSPENDED] }, [ POWER6_PME_PM_DFU_ADD_SHIFTED_BOTH ] = { .pme_name = "PM_DFU_ADD_SHIFTED_BOTH", .pme_code = 0xe0088, .pme_short_desc = "DFU add type with both operands shifted", .pme_long_desc = "DFU add type with both operands shifted", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DFU_ADD_SHIFTED_BOTH], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DFU_ADD_SHIFTED_BOTH] }, [ POWER6_PME_PM_LSU_REJECT_NO_SCRATCH ] = { .pme_name = "PM_LSU_REJECT_NO_SCRATCH", .pme_code = 0x2a1034, .pme_short_desc = "LSU reject due to scratch register not available", .pme_long_desc = "LSU reject due to scratch register not available", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU_REJECT_NO_SCRATCH], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU_REJECT_NO_SCRATCH] }, [ POWER6_PME_PM_STCX_FAIL ] = { .pme_name = "PM_STCX_FAIL", .pme_code = 0x830ee, .pme_short_desc = "STCX failed", .pme_long_desc = "A stcx (stwcx or stdcx) failed", .pme_event_ids = power6_event_ids[POWER6_PME_PM_STCX_FAIL], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_STCX_FAIL] }, [ POWER6_PME_PM_FPU1_DENORM ] = { .pme_name = "PM_FPU1_DENORM", .pme_code = 0xc10aa, .pme_short_desc = "FPU1 received denormalized data", .pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU1_DENORM], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU1_DENORM] }, [ POWER6_PME_PM_GCT_NOSLOT_COUNT ] = { .pme_name = "PM_GCT_NOSLOT_COUNT", .pme_code = 0x100009, .pme_short_desc = "Periods no GCT slot allocated", .pme_long_desc = "Periods this thread does not have any slots allocated in the GCT.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_GCT_NOSLOT_COUNT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_GCT_NOSLOT_COUNT] }, [ POWER6_PME_PM_DATA_FROM_DL2L3_SHR_CYC ] = { .pme_name = "PM_DATA_FROM_DL2L3_SHR_CYC", .pme_code = 0x20002a, .pme_short_desc = "Load latency from distant L2 or L3 shared", .pme_long_desc = "Load latency from distant L2 or L3 shared", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_DL2L3_SHR_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_DL2L3_SHR_CYC] }, [ POWER6_PME_PM_DATA_FROM_L21 ] = { .pme_name = "PM_DATA_FROM_L21", .pme_code = 0x200058, .pme_short_desc = "Data loaded from private L2 other core", .pme_long_desc = "Data loaded from private L2 other core", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L21], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L21] }, [ POWER6_PME_PM_FPU_1FLOP ] = { .pme_name = "PM_FPU_1FLOP", .pme_code = 0x1c0030, .pme_short_desc = "FPU executed one flop instruction ", .pme_long_desc = "This event counts the number of one flop instructions. These could be fadd*, fmul*, fsub*, fneg+, fabs+, fnabs+, fres+, frsqrte+, fcmp**, or fsel where XYZ* means XYZ, XYZs, XYZ., XYZs., XYZ+ means XYZ, XYZ., and XYZ** means XYZu, XYZo.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_1FLOP], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_1FLOP] }, [ POWER6_PME_PM_LSU1_REJECT ] = { .pme_name = "PM_LSU1_REJECT", .pme_code = 0xa10ae, .pme_short_desc = "LSU1 reject", .pme_long_desc = "LSU1 reject", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU1_REJECT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU1_REJECT] }, [ POWER6_PME_PM_IC_REQ ] = { .pme_name = "PM_IC_REQ", .pme_code = 0x4008a, .pme_short_desc = "I cache demand of prefetch request", .pme_long_desc = "I cache demand of prefetch request", .pme_event_ids = power6_event_ids[POWER6_PME_PM_IC_REQ], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IC_REQ] }, [ POWER6_PME_PM_MRK_DFU_FIN ] = { .pme_name = "PM_MRK_DFU_FIN", .pme_code = 0x300008, .pme_short_desc = "DFU marked instruction finish", .pme_long_desc = "DFU marked instruction finish", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DFU_FIN], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DFU_FIN] }, [ POWER6_PME_PM_NOT_LLA_CYC ] = { .pme_name = "PM_NOT_LLA_CYC", .pme_code = 0x401e, .pme_short_desc = "Load Look Ahead not Active", .pme_long_desc = "Load Look Ahead not Active", .pme_event_ids = power6_event_ids[POWER6_PME_PM_NOT_LLA_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_NOT_LLA_CYC] }, [ POWER6_PME_PM_INST_FROM_L1 ] = { .pme_name = "PM_INST_FROM_L1", .pme_code = 0x40082, .pme_short_desc = "Instruction fetched from L1", .pme_long_desc = "An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions", .pme_event_ids = power6_event_ids[POWER6_PME_PM_INST_FROM_L1], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_INST_FROM_L1] }, [ POWER6_PME_PM_MRK_VMX_COMPLEX_ISSUED ] = { .pme_name = "PM_MRK_VMX_COMPLEX_ISSUED", .pme_code = 0x7008c, .pme_short_desc = "Marked VMX instruction issued to complex", .pme_long_desc = "Marked VMX instruction issued to complex", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_VMX_COMPLEX_ISSUED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_VMX_COMPLEX_ISSUED] }, [ POWER6_PME_PM_BRU_FIN ] = { .pme_name = "PM_BRU_FIN", .pme_code = 0x430e6, .pme_short_desc = "BRU produced a result", .pme_long_desc = "BRU produced a result", .pme_event_ids = power6_event_ids[POWER6_PME_PM_BRU_FIN], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_BRU_FIN] }, [ POWER6_PME_PM_LSU1_REJECT_EXTERN ] = { .pme_name = "PM_LSU1_REJECT_EXTERN", .pme_code = 0xa10ac, .pme_short_desc = "LSU1 external reject request ", .pme_long_desc = "LSU1 external reject request ", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU1_REJECT_EXTERN], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU1_REJECT_EXTERN] }, [ POWER6_PME_PM_DATA_FROM_L21_CYC ] = { .pme_name = "PM_DATA_FROM_L21_CYC", .pme_code = 0x400020, .pme_short_desc = "Load latency from private L2 other core", .pme_long_desc = "Load latency from private L2 other core", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_L21_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_L21_CYC] }, [ POWER6_PME_PM_GXI_CYC_BUSY ] = { .pme_name = "PM_GXI_CYC_BUSY", .pme_code = 0x50386, .pme_short_desc = "Inbound GX bus utilizations (# of cycles in use)", .pme_long_desc = "Inbound GX bus utilizations (# of cycles in use)", .pme_event_ids = power6_event_ids[POWER6_PME_PM_GXI_CYC_BUSY], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_GXI_CYC_BUSY] }, [ POWER6_PME_PM_MRK_LD_MISS_L1 ] = { .pme_name = "PM_MRK_LD_MISS_L1", .pme_code = 0x200056, .pme_short_desc = "Marked L1 D cache load misses", .pme_long_desc = "Marked L1 D cache load misses", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_LD_MISS_L1], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_LD_MISS_L1] }, [ POWER6_PME_PM_L1_WRITE_CYC ] = { .pme_name = "PM_L1_WRITE_CYC", .pme_code = 0x430e2, .pme_short_desc = "Cycles writing to instruction L1", .pme_long_desc = "This signal is asserted each cycle a cache write is active.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_L1_WRITE_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_L1_WRITE_CYC] }, [ POWER6_PME_PM_LLA_CYC ] = { .pme_name = "PM_LLA_CYC", .pme_code = 0xc01e, .pme_short_desc = "Load Look Ahead Active", .pme_long_desc = "Load Look Ahead Active", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LLA_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LLA_CYC] }, [ POWER6_PME_PM_MRK_DATA_FROM_L2MISS ] = { .pme_name = "PM_MRK_DATA_FROM_L2MISS", .pme_code = 0x103028, .pme_short_desc = "Marked data loaded missed L2", .pme_long_desc = "DL1 was reloaded from beyond L2 due to a marked demand load.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_L2MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_L2MISS] }, [ POWER6_PME_PM_GCT_FULL_COUNT ] = { .pme_name = "PM_GCT_FULL_COUNT", .pme_code = 0x40087, .pme_short_desc = "Periods GCT full", .pme_long_desc = "The ISU sends a signal indicating the gct is full.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_GCT_FULL_COUNT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_GCT_FULL_COUNT] }, [ POWER6_PME_PM_MEM_DP_RQ_LOC_GLOB ] = { .pme_name = "PM_MEM_DP_RQ_LOC_GLOB", .pme_code = 0x250230, .pme_short_desc = "Memory read queue marking cache line double pump state from local to global", .pme_long_desc = "Memory read queue marking cache line double pump state from local to global", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MEM_DP_RQ_LOC_GLOB], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MEM_DP_RQ_LOC_GLOB] }, [ POWER6_PME_PM_DATA_FROM_RL2L3_SHR ] = { .pme_name = "PM_DATA_FROM_RL2L3_SHR", .pme_code = 0x20005c, .pme_short_desc = "Data loaded from remote L2 or L3 shared", .pme_long_desc = "Data loaded from remote L2 or L3 shared", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DATA_FROM_RL2L3_SHR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DATA_FROM_RL2L3_SHR] }, [ POWER6_PME_PM_MRK_LSU_REJECT_UST ] = { .pme_name = "PM_MRK_LSU_REJECT_UST", .pme_code = 0x293034, .pme_short_desc = "Marked unaligned store reject", .pme_long_desc = "Marked unaligned store reject", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_LSU_REJECT_UST], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_LSU_REJECT_UST] }, [ POWER6_PME_PM_MRK_VMX_PERMUTE_ISSUED ] = { .pme_name = "PM_MRK_VMX_PERMUTE_ISSUED", .pme_code = 0x7008e, .pme_short_desc = "Marked VMX instruction issued to permute", .pme_long_desc = "Marked VMX instruction issued to permute", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_VMX_PERMUTE_ISSUED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_VMX_PERMUTE_ISSUED] }, [ POWER6_PME_PM_MRK_PTEG_FROM_L21 ] = { .pme_name = "PM_MRK_PTEG_FROM_L21", .pme_code = 0x212040, .pme_short_desc = "Marked PTEG loaded from private L2 other core", .pme_long_desc = "Marked PTEG loaded from private L2 other core", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_PTEG_FROM_L21], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_PTEG_FROM_L21] }, [ POWER6_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = { .pme_name = "PM_THRD_GRP_CMPL_BOTH_CYC", .pme_code = 0x200018, .pme_short_desc = "Cycles group completed by both threads", .pme_long_desc = "Cycles group completed by both threads", .pme_event_ids = power6_event_ids[POWER6_PME_PM_THRD_GRP_CMPL_BOTH_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_THRD_GRP_CMPL_BOTH_CYC] }, [ POWER6_PME_PM_BR_MPRED ] = { .pme_name = "PM_BR_MPRED", .pme_code = 0x400052, .pme_short_desc = "Branches incorrectly predicted", .pme_long_desc = "Branches incorrectly predicted", .pme_event_ids = power6_event_ids[POWER6_PME_PM_BR_MPRED], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_BR_MPRED] }, [ POWER6_PME_PM_LD_REQ_L2 ] = { .pme_name = "PM_LD_REQ_L2", .pme_code = 0x150730, .pme_short_desc = "L2 load requests ", .pme_long_desc = "L2 load requests ", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LD_REQ_L2], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LD_REQ_L2] }, [ POWER6_PME_PM_FLUSH_ASYNC ] = { .pme_name = "PM_FLUSH_ASYNC", .pme_code = 0x220ca, .pme_short_desc = "Flush caused by asynchronous exception", .pme_long_desc = "Flush caused by asynchronous exception", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FLUSH_ASYNC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FLUSH_ASYNC] }, [ POWER6_PME_PM_HV_CYC ] = { .pme_name = "PM_HV_CYC", .pme_code = 0x200016, .pme_short_desc = "Hypervisor Cycles", .pme_long_desc = "Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0)", .pme_event_ids = power6_event_ids[POWER6_PME_PM_HV_CYC], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_HV_CYC] }, [ POWER6_PME_PM_LSU1_DERAT_MISS ] = { .pme_name = "PM_LSU1_DERAT_MISS", .pme_code = 0x910ae, .pme_short_desc = "LSU1 DERAT misses", .pme_long_desc = "A data request (load or store) from LSU Unit 1 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU1_DERAT_MISS], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU1_DERAT_MISS] }, [ POWER6_PME_PM_DPU_HELD_SMT ] = { .pme_name = "PM_DPU_HELD_SMT", .pme_code = 0x20082, .pme_short_desc = "DISP unit held due to SMT conflicts ", .pme_long_desc = "DISP unit held due to SMT conflicts ", .pme_event_ids = power6_event_ids[POWER6_PME_PM_DPU_HELD_SMT], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_DPU_HELD_SMT] }, [ POWER6_PME_PM_MRK_LSU_FIN ] = { .pme_name = "PM_MRK_LSU_FIN", .pme_code = 0x40001a, .pme_short_desc = "Marked instruction LSU processing finished", .pme_long_desc = "One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_LSU_FIN], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_LSU_FIN] }, [ POWER6_PME_PM_MRK_DATA_FROM_RL2L3_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_RL2L3_SHR", .pme_code = 0x20304c, .pme_short_desc = "Marked data loaded from remote L2 or L3 shared", .pme_long_desc = "Marked data loaded from remote L2 or L3 shared", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DATA_FROM_RL2L3_SHR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DATA_FROM_RL2L3_SHR] }, [ POWER6_PME_PM_LSU0_REJECT_STQ_FULL ] = { .pme_name = "PM_LSU0_REJECT_STQ_FULL", .pme_code = 0xa0080, .pme_short_desc = "LSU0 reject due to store queue full", .pme_long_desc = "LSU0 reject due to store queue full", .pme_event_ids = power6_event_ids[POWER6_PME_PM_LSU0_REJECT_STQ_FULL], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_LSU0_REJECT_STQ_FULL] }, [ POWER6_PME_PM_MRK_DERAT_REF_4K ] = { .pme_name = "PM_MRK_DERAT_REF_4K", .pme_code = 0x282044, .pme_short_desc = "Marked DERAT reference for 4K page", .pme_long_desc = "Marked DERAT reference for 4K page", .pme_event_ids = power6_event_ids[POWER6_PME_PM_MRK_DERAT_REF_4K], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_MRK_DERAT_REF_4K] }, [ POWER6_PME_PM_FPU_ISSUE_STALL_FPR ] = { .pme_name = "PM_FPU_ISSUE_STALL_FPR", .pme_code = 0x330e2, .pme_short_desc = "FPU issue stalled due to FPR dependencies", .pme_long_desc = "FPU issue stalled due to FPR dependencies", .pme_event_ids = power6_event_ids[POWER6_PME_PM_FPU_ISSUE_STALL_FPR], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_FPU_ISSUE_STALL_FPR] }, [ POWER6_PME_PM_IFU_FIN ] = { .pme_name = "PM_IFU_FIN", .pme_code = 0x430e4, .pme_short_desc = "IFU finished an instruction", .pme_long_desc = "IFU finished an instruction", .pme_event_ids = power6_event_ids[POWER6_PME_PM_IFU_FIN], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_IFU_FIN] }, [ POWER6_PME_PM_GXO_CYC_BUSY ] = { .pme_name = "PM_GXO_CYC_BUSY", .pme_code = 0x50380, .pme_short_desc = "Outbound GX bus utilizations (# of cycles in use)", .pme_long_desc = "Outbound GX bus utilizations (# of cycles in use)", .pme_event_ids = power6_event_ids[POWER6_PME_PM_GXO_CYC_BUSY], .pme_group_vector = power6_group_vecs[POWER6_PME_PM_GXO_CYC_BUSY] } }; #define POWER6_PME_EVENT_COUNT 553 static const int power6_group_event_ids[][POWER6_NUM_EVENT_COUNTERS] = { [ 0 ] = { 302, 148, 139, 12, 0, 0 }, [ 1 ] = { 315, 11, 306, 347, 0, 0 }, [ 2 ] = { 10, 4, 6, 5, 0, 0 }, [ 3 ] = { 9, 9, 2, 7, 0, 0 }, [ 4 ] = { 8, 8, 7, 11, 0, 0 }, [ 5 ] = { 6, 3, 5, 4, 0, 0 }, [ 6 ] = { 8, 10, 1, 3, 0, 0 }, [ 7 ] = { 13, 15, 13, 19, 0, 0 }, [ 8 ] = { 14, 19, 14, 19, 0, 0 }, [ 9 ] = { 14, 19, 12, 16, 0, 0 }, [ 10 ] = { 16, 23, 11, 13, 0, 0 }, [ 11 ] = { 15, 13, 16, 20, 0, 0 }, [ 12 ] = { 200, 24, 10, 17, 0, 0 }, [ 13 ] = { 139, 22, 10, 14, 0, 0 }, [ 14 ] = { 139, 14, 16, 23, 0, 0 }, [ 15 ] = { 14, 12, 11, 18, 0, 0 }, [ 16 ] = { 16, 21, 14, 22, 0, 0 }, [ 17 ] = { 15, 16, 12, 21, 0, 0 }, [ 18 ] = { 13, 18, 139, 160, 0, 0 }, [ 19 ] = { 67, 15, 10, 15, 0, 0 }, [ 20 ] = { 2, 22, 139, 20, 0, 0 }, [ 21 ] = { 14, 20, 10, 18, 0, 0 }, [ 22 ] = { 143, 154, 144, 151, 0, 0 }, [ 23 ] = { 144, 155, 145, 150, 0, 0 }, [ 24 ] = { 146, 156, 142, 148, 0, 0 }, [ 25 ] = { 145, 152, 147, 152, 0, 0 }, [ 26 ] = { 143, 154, 146, 151, 0, 0 }, [ 27 ] = { 295, 305, 291, 290, 0, 0 }, [ 28 ] = { 296, 305, 292, 289, 0, 0 }, [ 29 ] = { 297, 306, 293, 291, 0, 0 }, [ 30 ] = { 298, 304, 294, 291, 0, 0 }, [ 31 ] = { 299, 307, 290, 292, 0, 0 }, [ 32 ] = { 17, 26, 19, 312, 0, 0 }, [ 33 ] = { 148, 158, 150, 157, 0, 0 }, [ 34 ] = { 52, 55, 115, 123, 0, 0 }, [ 35 ] = { 154, 64, 54, 62, 0, 0 }, [ 36 ] = { 52, 55, 305, 56, 0, 0 }, [ 37 ] = { 39, 38, 32, 41, 0, 0 }, [ 38 ] = { 54, 49, 50, 55, 0, 0 }, [ 39 ] = { 35, 52, 41, 44, 0, 0 }, [ 40 ] = { 36, 54, 30, 46, 0, 0 }, [ 41 ] = { 40, 63, 42, 54, 0, 0 }, [ 42 ] = { 38, 61, 49, 39, 0, 0 }, [ 43 ] = { 41, 60, 47, 42, 0, 0 }, [ 44 ] = { 41, 43, 45, 38, 0, 0 }, [ 45 ] = { 247, 11, 303, 52, 0, 0 }, [ 46 ] = { 202, 212, 300, 301, 0, 0 }, [ 47 ] = { 310, 212, 299, 202, 0, 0 }, [ 48 ] = { 21, 29, 155, 136, 0, 0 }, [ 49 ] = { 67, 77, 67, 76, 0, 0 }, [ 50 ] = { 136, 142, 134, 140, 0, 0 }, [ 51 ] = { 304, 311, 298, 200, 0, 0 }, [ 52 ] = { 197, 208, 296, 297, 0, 0 }, [ 53 ] = { 315, 320, 306, 304, 0, 0 }, [ 54 ] = { 1, 137, 313, 306, 0, 0 }, [ 55 ] = { 57, 67, 304, 0, 0, 0 }, [ 56 ] = { 307, 321, 10, 145, 0, 0 }, [ 57 ] = { 152, 65, 314, 159, 0, 0 }, [ 58 ] = { 152, 65, 136, 294, 0, 0 }, [ 59 ] = { 239, 249, 236, 238, 0, 0 }, [ 60 ] = { 240, 250, 235, 243, 0, 0 }, [ 61 ] = { 243, 253, 237, 242, 0, 0 }, [ 62 ] = { 245, 256, 214, 232, 0, 0 }, [ 63 ] = { 244, 255, 213, 231, 0, 0 }, [ 64 ] = { 216, 238, 238, 244, 0, 0 }, [ 65 ] = { 218, 241, 214, 231, 0, 0 }, [ 66 ] = { 208, 218, 217, 227, 0, 0 }, [ 67 ] = { 210, 221, 219, 225, 0, 0 }, [ 68 ] = { 214, 224, 222, 228, 0, 0 }, [ 69 ] = { 213, 213, 221, 220, 0, 0 }, [ 70 ] = { 217, 217, 225, 222, 0, 0 }, [ 71 ] = { 209, 213, 218, 220, 0, 0 }, [ 72 ] = { 237, 246, 200, 221, 0, 0 }, [ 73 ] = { 206, 216, 240, 233, 0, 0 }, [ 74 ] = { 238, 248, 234, 211, 0, 0 }, [ 75 ] = { 234, 243, 229, 236, 0, 0 }, [ 76 ] = { 140, 51, 139, 306, 0, 0 }, [ 77 ] = { 121, 127, 119, 147, 0, 0 }, [ 78 ] = { 316, 322, 308, 307, 0, 0 }, [ 79 ] = { 317, 323, 309, 308, 0, 0 }, [ 80 ] = { 318, 324, 310, 309, 0, 0 }, [ 81 ] = { 319, 325, 311, 310, 0, 0 }, [ 82 ] = { 117, 125, 116, 124, 0, 0 }, [ 83 ] = { 118, 147, 117, 125, 0, 0 }, [ 84 ] = { 329, 337, 329, 324, 0, 0 }, [ 85 ] = { 321, 332, 316, 318, 0, 0 }, [ 86 ] = { 322, 330, 320, 319, 0, 0 }, [ 87 ] = { 331, 340, 328, 328, 0, 0 }, [ 88 ] = { 336, 331, 322, 323, 0, 0 }, [ 89 ] = { 23, 31, 24, 33, 0, 0 }, [ 90 ] = { 27, 35, 28, 37, 0, 0 }, [ 91 ] = { 59, 69, 59, 67, 0, 0 }, [ 92 ] = { 63, 74, 64, 72, 0, 0 }, [ 93 ] = { 59, 69, 58, 68, 0, 0 }, [ 94 ] = { 257, 268, 250, 255, 0, 0 }, [ 95 ] = { 250, 262, 242, 248, 0, 0 }, [ 96 ] = { 254, 266, 246, 252, 0, 0 }, [ 97 ] = { 126, 132, 125, 129, 0, 0 }, [ 98 ] = { 123, 129, 122, 132, 0, 0 }, [ 99 ] = { 126, 130, 126, 135, 0, 0 }, [ 100 ] = { 142, 165, 285, 153, 0, 0 }, [ 101 ] = { 186, 195, 188, 193, 0, 0 }, [ 102 ] = { 187, 196, 185, 191, 0, 0 }, [ 103 ] = { 185, 194, 131, 27, 0, 0 }, [ 104 ] = { 203, 209, 301, 298, 0, 0 }, [ 105 ] = { 165, 171, 179, 182, 0, 0 }, [ 106 ] = { 166, 172, 180, 183, 0, 0 }, [ 107 ] = { 170, 178, 184, 189, 0, 0 }, [ 108 ] = { 167, 197, 13, 187, 0, 0 }, [ 109 ] = { 157, 167, 171, 178, 0, 0 }, [ 110 ] = { 160, 168, 174, 179, 0, 0 }, [ 111 ] = { 164, 170, 178, 181, 0, 0 }, [ 112 ] = { 170, 177, 184, 188, 0, 0 }, [ 113 ] = { 131, 140, 187, 191, 0, 0 }, [ 114 ] = { 193, 201, 14, 195, 0, 0 }, [ 115 ] = { 196, 204, 14, 198, 0, 0 }, [ 116 ] = { 107, 116, 105, 120, 0, 0 }, [ 117 ] = { 111, 124, 106, 118, 0, 0 }, [ 118 ] = { 114, 120, 106, 118, 0, 0 }, [ 119 ] = { 71, 86, 78, 90, 0, 0 }, [ 120 ] = { 76, 90, 70, 89, 0, 0 }, [ 121 ] = { 75, 83, 76, 88, 0, 0 }, [ 122 ] = { 73, 88, 83, 80, 0, 0 }, [ 123 ] = { 86, 101, 93, 105, 0, 0 }, [ 124 ] = { 91, 105, 85, 104, 0, 0 }, [ 125 ] = { 90, 98, 91, 103, 0, 0 }, [ 126 ] = { 88, 103, 98, 95, 0, 0 }, [ 127 ] = { 101, 111, 102, 109, 0, 0 }, [ 128 ] = { 103, 113, 100, 111, 0, 0 }, [ 129 ] = { 105, 110, 113, 122, 0, 0 }, [ 130 ] = { 102, 113, 114, 108, 0, 0 }, [ 131 ] = { 301, 309, 10, 145, 0, 0 }, [ 132 ] = { 311, 11, 303, 145, 0, 0 }, [ 133 ] = { 200, 243, 197, 234, 0, 0 }, [ 134 ] = { 351, 361, 343, 343, 0, 0 }, [ 135 ] = { 350, 360, 342, 342, 0, 0 }, [ 136 ] = { 352, 362, 344, 344, 0, 0 }, [ 137 ] = { 258, 280, 251, 145, 0, 0 }, [ 138 ] = { 139, 269, 252, 256, 0, 0 }, [ 139 ] = { 259, 270, 253, 145, 0, 0 }, [ 140 ] = { 260, 148, 254, 257, 0, 0 }, [ 141 ] = { 261, 271, 255, 145, 0, 0 }, [ 142 ] = { 262, 272, 138, 258, 0, 0 }, [ 143 ] = { 263, 272, 256, 145, 0, 0 }, [ 144 ] = { 276, 288, 138, 273, 0, 0 }, [ 145 ] = { 270, 283, 266, 145, 0, 0 }, [ 146 ] = { 273, 286, 269, 145, 0, 0 }, [ 147 ] = { 268, 279, 262, 145, 0, 0 }, [ 148 ] = { 265, 275, 261, 145, 0, 0 }, [ 149 ] = { 276, 277, 257, 145, 0, 0 }, [ 150 ] = { 281, 278, 138, 263, 0, 0 }, [ 151 ] = { 289, 281, 138, 271, 0, 0 }, [ 152 ] = { 12, 11, 138, 272, 0, 0 }, [ 153 ] = { 282, 294, 277, 145, 0, 0 }, [ 154 ] = { 277, 289, 271, 145, 0, 0 }, [ 155 ] = { 139, 290, 272, 275, 0, 0 }, [ 156 ] = { 278, 291, 138, 276, 0, 0 }, [ 157 ] = { 279, 148, 273, 277, 0, 0 }, [ 158 ] = { 280, 148, 274, 278, 0, 0 }, [ 159 ] = { 12, 292, 275, 145, 0, 0 }, [ 160 ] = { 285, 298, 282, 145, 0, 0 }, [ 161 ] = { 283, 296, 258, 145, 0, 0 }, [ 162 ] = { 288, 342, 10, 145, 0, 0 }, [ 163 ] = { 265, 276, 260, 145, 0, 0 }, [ 164 ] = { 353, 363, 345, 145, 0, 0 }, [ 165 ] = { 354, 364, 346, 145, 0, 0 }, [ 166 ] = { 199, 243, 197, 335, 0, 0 }, [ 167 ] = { 238, 359, 341, 211, 0, 0 }, [ 168 ] = { 349, 358, 333, 147, 0, 0 }, [ 169 ] = { 348, 356, 115, 123, 0, 0 }, [ 170 ] = { 154, 357, 340, 340, 0, 0 }, [ 171 ] = { 199, 64, 339, 337, 0, 0 }, [ 172 ] = { 337, 0, 332, 136, 0, 0 }, [ 173 ] = { 343, 309, 335, 157, 0, 0 }, [ 174 ] = { 339, 128, 334, 287, 0, 0 }, [ 175 ] = { 344, 351, 336, 303, 0, 0 }, [ 176 ] = { 315, 137, 336, 303, 0, 0 }, [ 177 ] = { 348, 355, 340, 340, 0, 0 }, [ 178 ] = { 52, 38, 54, 62, 0, 0 }, [ 179 ] = { 349, 358, 341, 341, 0, 0 }, [ 180 ] = { 121, 127, 234, 244, 0, 0 }, [ 181 ] = { 342, 359, 303, 335, 0, 0 }, [ 182 ] = { 312, 248, 336, 234, 0, 0 }, [ 183 ] = { 309, 357, 197, 203, 0, 0 }, [ 184 ] = { 31, 356, 31, 336, 0, 0 }, [ 185 ] = { 31, 55, 31, 304, 0, 0 }, [ 186 ] = { 101, 111, 102, 12, 0, 0 }, [ 187 ] = { 139, 246, 113, 12, 0, 0 }, [ 188 ] = { 12, 210, 299, 145, 0, 0 }, [ 189 ] = { 139, 149, 198, 300, 0, 0 }, [ 190 ] = { 103, 11, 117, 125, 0, 0 }, [ 191 ] = { 13, 15, 12, 16, 0, 0 }, [ 192 ] = { 14, 19, 14, 12, 0, 0 }, [ 193 ] = { 101, 111, 113, 202, 0, 0 }, [ 194 ] = { 199, 11, 231, 299, 0, 0 }, [ 195 ] = { 139, 197, 146, 19, 0, 0 }, [ 196 ] = { 353, 363, 138, 345, 0, 0 }, [ 197 ] = { 354, 364, 138, 346, 0, 0 } }; static const pmg_power_group_t power6_groups[] = { [ 0 ] = { .pmg_name = "pm_utilization", .pmg_desc = "CPI and utilization data", .pmg_event_ids = power6_group_event_ids[0], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000000a02121eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 1 ] = { .pmg_name = "pm_utilization_capacity", .pmg_desc = "CPU utilization and capacity", .pmg_event_ids = power6_group_event_ids[1], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000fa1ef4f4ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 2 ] = { .pmg_name = "pm_branch", .pmg_desc = "Branch operations", .pmg_event_ids = power6_group_event_ids[2], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x04000000a2a8808aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 3 ] = { .pmg_name = "pm_branch2", .pmg_desc = "Branch operations", .pmg_event_ids = power6_group_event_ids[3], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x04000000a4a68e8cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 4 ] = { .pmg_name = "pm_branch3", .pmg_desc = "Branch operations", .pmg_event_ids = power6_group_event_ids[4], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x04000000a0a28486ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 5 ] = { .pmg_name = "pm_branch4", .pmg_desc = "Branch operations", .pmg_event_ids = power6_group_event_ids[5], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x04000000a8aa8c8eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 6 ] = { .pmg_name = "pm_branch5", .pmg_desc = "Branch operations", .pmg_event_ids = power6_group_event_ids[6], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x04040000a052c652ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 7 ] = { .pmg_name = "pm_dsource", .pmg_desc = "Data source", .pmg_event_ids = power6_group_event_ids[7], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000058585656ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 8 ] = { .pmg_name = "pm_dsource2", .pmg_desc = "Data sources", .pmg_event_ids = power6_group_event_ids[8], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000005a5a5856ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 9 ] = { .pmg_name = "pm_dsource3", .pmg_desc = "Data sources", .pmg_event_ids = power6_group_event_ids[9], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000005a5a5a5aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 10 ] = { .pmg_name = "pm_dsource4", .pmg_desc = "Data sources", .pmg_event_ids = power6_group_event_ids[10], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000005c5c5c5cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 11 ] = { .pmg_name = "pm_dsource5", .pmg_desc = "Data sources", .pmg_event_ids = power6_group_event_ids[11], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000005e5e5e5eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 12 ] = { .pmg_name = "pm_dlatencies", .pmg_desc = "Data latencies", .pmg_event_ids = power6_group_event_ids[12], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000000c281e24ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 13 ] = { .pmg_name = "pm_dlatencies2", .pmg_desc = "Data latencies", .pmg_event_ids = power6_group_event_ids[13], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000022c1e2aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 14 ] = { .pmg_name = "pm_dlatencies3", .pmg_desc = "Data latencies", .pmg_event_ids = power6_group_event_ids[14], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000022e5e2cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 15 ] = { .pmg_name = "pm_dlatencies4", .pmg_desc = "Data latencies", .pmg_event_ids = power6_group_event_ids[15], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000005a2a5c26ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 16 ] = { .pmg_name = "pm_dlatencies5", .pmg_desc = "Data latencies", .pmg_event_ids = power6_group_event_ids[16], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000005c225828ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 17 ] = { .pmg_name = "pm_dlatencies6", .pmg_desc = "Data latencies", .pmg_event_ids = power6_group_event_ids[17], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000005e245a2eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 18 ] = { .pmg_name = "pm_dlatencies7", .pmg_desc = "Data latencies", .pmg_event_ids = power6_group_event_ids[18], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000005820120eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 19 ] = { .pmg_name = "pm_dlatencies8", .pmg_desc = "Data latencies", .pmg_event_ids = power6_group_event_ids[19], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000010581e20ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 20 ] = { .pmg_name = "pm_dlatencies9", .pmg_desc = "Data latencies", .pmg_event_ids = power6_group_event_ids[20], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000122c125eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 21 ] = { .pmg_name = "pm_dlatencies10", .pmg_desc = "Data latencies", .pmg_event_ids = power6_group_event_ids[21], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000005a261e26ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 22 ] = { .pmg_name = "pm_isource", .pmg_desc = "Instruction sources", .pmg_event_ids = power6_group_event_ids[22], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0040000040404654ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 23 ] = { .pmg_name = "pm_isource2", .pmg_desc = "Instruction sources", .pmg_event_ids = power6_group_event_ids[23], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0040000046464046ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 24 ] = { .pmg_name = "pm_isource3", .pmg_desc = "Instruction sources", .pmg_event_ids = power6_group_event_ids[24], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0040000044444444ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 25 ] = { .pmg_name = "pm_isource4", .pmg_desc = "Instruction sources", .pmg_event_ids = power6_group_event_ids[25], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0040000042424242ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 26 ] = { .pmg_name = "pm_isource5", .pmg_desc = "Instruction sources", .pmg_event_ids = power6_group_event_ids[26], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0040000040405454ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 27 ] = { .pmg_name = "pm_pteg", .pmg_desc = "PTEG sources", .pmg_event_ids = power6_group_event_ids[27], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0001000048484e4eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 28 ] = { .pmg_name = "pm_pteg2", .pmg_desc = "PTEG sources", .pmg_event_ids = power6_group_event_ids[28], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000100002848484cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 29 ] = { .pmg_name = "pm_pteg3", .pmg_desc = "PTEG sources", .pmg_event_ids = power6_group_event_ids[29], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000100004e4e284aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 30 ] = { .pmg_name = "pm_pteg4", .pmg_desc = "PTEG sources", .pmg_event_ids = power6_group_event_ids[30], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000100004a4a4a4aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 31 ] = { .pmg_name = "pm_pteg5", .pmg_desc = "PTEG sources", .pmg_event_ids = power6_group_event_ids[31], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000100004c4c4cc8ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 32 ] = { .pmg_name = "pm_data_tablewalk", .pmg_desc = "Data tablewalks", .pmg_event_ids = power6_group_event_ids[32], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x09900000a0a284e8ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 33 ] = { .pmg_name = "pm_inst_tablewalk", .pmg_desc = "Instruction tablewalks", .pmg_event_ids = power6_group_event_ids[33], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x09900000a8aa8ceaULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 34 ] = { .pmg_name = "pm_freq", .pmg_desc = "Frequency events", .pmg_event_ids = power6_group_event_ids[34], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000002a3c3c3cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 35 ] = { .pmg_name = "pm_disp_wait", .pmg_desc = "Dispatch stalls", .pmg_event_ids = power6_group_event_ids[35], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000560c040cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 36 ] = { .pmg_name = "pm_disp_held", .pmg_desc = "Dispatch held conditions", .pmg_event_ids = power6_group_event_ids[36], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x200000002a3c2aa2ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 37 ] = { .pmg_name = "pm_disp_held2", .pmg_desc = "Dispatch held conditions", .pmg_event_ids = power6_group_event_ids[37], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x200000008004a4a6ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 38 ] = { .pmg_name = "pm_disp_held3", .pmg_desc = "Dispatch held conditions", .pmg_event_ids = power6_group_event_ids[38], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x20000000888aacaeULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 39 ] = { .pmg_name = "pm_disp_held4", .pmg_desc = "Dispatch held conditions", .pmg_event_ids = power6_group_event_ids[39], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x02000000a0a28486ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 40 ] = { .pmg_name = "pm_disp_held5", .pmg_desc = "Dispatch held conditions", .pmg_event_ids = power6_group_event_ids[40], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x22000000a8aa8ca0ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 41 ] = { .pmg_name = "pm_disp_held6", .pmg_desc = "Dispatch held conditions", .pmg_event_ids = power6_group_event_ids[41], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x33000000a882a4a6ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 42 ] = { .pmg_name = "pm_disp_held7", .pmg_desc = "Dispatch held conditions", .pmg_event_ids = power6_group_event_ids[42], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x30000000888aacaeULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 43 ] = { .pmg_name = "pm_disp_held8", .pmg_desc = "Dispatch held conditions", .pmg_event_ids = power6_group_event_ids[43], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x220000008a8cae80ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 44 ] = { .pmg_name = "pm_disp_held9", .pmg_desc = "Dispatch held conditions", .pmg_event_ids = power6_group_event_ids[44], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x220000008aa08a8cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 45 ] = { .pmg_name = "pm_sync", .pmg_desc = "Sync events", .pmg_event_ids = power6_group_event_ids[45], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x38900000ae1eeca0ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 46 ] = { .pmg_name = "pm_L1_ref", .pmg_desc = "L1 references", .pmg_event_ids = power6_group_event_ids[46], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x80000000368aa63aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 47 ] = { .pmg_name = "pm_L1_ldst", .pmg_desc = "L1 load/store ref/miss", .pmg_event_ids = power6_group_event_ids[47], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x800000003230a8a0ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 48 ] = { .pmg_name = "pm_streams", .pmg_desc = "Streams", .pmg_event_ids = power6_group_event_ids[48], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x48000000a0a284a4ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 49 ] = { .pmg_name = "pm_flush", .pmg_desc = "Flushes", .pmg_event_ids = power6_group_event_ids[49], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0022000010cacccaULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 50 ] = { .pmg_name = "pm_prefetch", .pmg_desc = "I cache Prefetches", .pmg_event_ids = power6_group_event_ids[50], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x400400008a8caec0ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 51 ] = { .pmg_name = "pm_stcx", .pmg_desc = "STCX", .pmg_event_ids = power6_group_event_ids[51], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00080000e6eccecaULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 52 ] = { .pmg_name = "pm_larx", .pmg_desc = "LARX", .pmg_event_ids = power6_group_event_ids[52], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00080000eae2c6ceULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 53 ] = { .pmg_name = "pm_thread_cyc", .pmg_desc = "Thread cycles", .pmg_event_ids = power6_group_event_ids[53], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000016182604ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 54 ] = { .pmg_name = "pm_misc", .pmg_desc = "Misc", .pmg_event_ids = power6_group_event_ids[54], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000004161808ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 55 ] = { .pmg_name = "pm_misc2", .pmg_desc = "Misc", .pmg_event_ids = power6_group_event_ids[55], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x40020000eef8f8a0ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 56 ] = { .pmg_name = "pm_misc3", .pmg_desc = "Misc", .pmg_event_ids = power6_group_event_ids[56], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0300000054a01e02ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 57 ] = { .pmg_name = "pm_tlb_slb", .pmg_desc = "TLB and SLB events", .pmg_event_ids = power6_group_event_ids[57], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00980000e0e8e8e2ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 58 ] = { .pmg_name = "pm_slb_miss", .pmg_desc = "SLB Misses", .pmg_event_ids = power6_group_event_ids[58], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00480001e0e8ee32ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 59 ] = { .pmg_name = "pm_rejects", .pmg_desc = "Reject events", .pmg_event_ids = power6_group_event_ids[59], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xaa00000034303e30ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 60 ] = { .pmg_name = "pm_rejects2", .pmg_desc = "Reject events", .pmg_event_ids = power6_group_event_ids[60], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x9a000000323830acULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 61 ] = { .pmg_name = "pm_rejects3", .pmg_desc = "Reject events", .pmg_event_ids = power6_group_event_ids[61], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xaa000000303e3234ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 62 ] = { .pmg_name = "pm_rejects4", .pmg_desc = "Unaligned store rejects", .pmg_event_ids = power6_group_event_ids[62], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x900000003630a2aaULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 63 ] = { .pmg_name = "pm_rejects5", .pmg_desc = "Unaligned load rejects", .pmg_event_ids = power6_group_event_ids[63], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x900000003036a0a8ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 64 ] = { .pmg_name = "pm_rejects6", .pmg_desc = "Set mispredictions rejects", .pmg_event_ids = power6_group_event_ids[64], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xa0000000848c341cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 65 ] = { .pmg_name = "pm_rejects_unit", .pmg_desc = "Unaligned reject events by unit", .pmg_event_ids = power6_group_event_ids[65], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x90000000808aa2a8ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 66 ] = { .pmg_name = "pm_rejects_unit2", .pmg_desc = "Reject events by unit", .pmg_event_ids = power6_group_event_ids[66], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xaa000000a6828e8aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 67 ] = { .pmg_name = "pm_rejects_unit3", .pmg_desc = "Reject events by unit", .pmg_event_ids = power6_group_event_ids[67], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0a000000a4a08c88ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 68 ] = { .pmg_name = "pm_rejects_unit4", .pmg_desc = "Reject events by unit", .pmg_event_ids = power6_group_event_ids[68], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xaa000000a2868aaeULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 69 ] = { .pmg_name = "pm_rejects_unit5", .pmg_desc = "Reject events by unit", .pmg_event_ids = power6_group_event_ids[69], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x9900000086a6ae8eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 70 ] = { .pmg_name = "pm_rejects_unit6", .pmg_desc = "Reject events by unit", .pmg_event_ids = power6_group_event_ids[70], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xaa00000080a6a88eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 71 ] = { .pmg_name = "pm_rejects_unit7", .pmg_desc = "Reject events by unit", .pmg_event_ids = power6_group_event_ids[71], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xa900000082a6aa8eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 72 ] = { .pmg_name = "pm_ldf", .pmg_desc = "Floating Point loads", .pmg_event_ids = power6_group_event_ids[72], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x800000003832a4acULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 73 ] = { .pmg_name = "pm_lsu_misc", .pmg_desc = "LSU events", .pmg_event_ids = power6_group_event_ids[73], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x08800000caccee8aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 74 ] = { .pmg_name = "pm_lsu_lmq", .pmg_desc = "LSU LMQ events", .pmg_event_ids = power6_group_event_ids[74], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x98000000ac1c1ca4ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 75 ] = { .pmg_name = "pm_lsu_flush_derat_miss", .pmg_desc = "LSU flush and DERAT misses", .pmg_event_ids = power6_group_event_ids[75], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00200000fc0eeceeULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 76 ] = { .pmg_name = "pm_lla", .pmg_desc = "Look Load Ahead events", .pmg_event_ids = power6_group_event_ids[76], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x33000000a2841208ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 77 ] = { .pmg_name = "pm_gct", .pmg_desc = "GCT events", .pmg_event_ids = power6_group_event_ids[77], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x404000000808a6e8ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 78 ] = { .pmg_name = "pm_smt_priorities", .pmg_desc = "Thread priority events", .pmg_event_ids = power6_group_event_ids[78], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0020000040404040ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 79 ] = { .pmg_name = "pm_smt_priorities2", .pmg_desc = "Thread priority events", .pmg_event_ids = power6_group_event_ids[79], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0020000046464646ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 80 ] = { .pmg_name = "pm_smt_priorities3", .pmg_desc = "Thread priority differences events", .pmg_event_ids = power6_group_event_ids[80], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0002000040404040ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 81 ] = { .pmg_name = "pm_smt_priorities4", .pmg_desc = "Thread priority differences events", .pmg_event_ids = power6_group_event_ids[81], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x03020000a6464646ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 82 ] = { .pmg_name = "pm_fxu", .pmg_desc = "FXU events", .pmg_event_ids = power6_group_event_ids[82], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000050505050ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 83 ] = { .pmg_name = "pm_fxu2", .pmg_desc = "FXU events", .pmg_event_ids = power6_group_event_ids[83], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x02040000aee41616ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 84 ] = { .pmg_name = "pm_vmx", .pmg_desc = "VMX events", .pmg_event_ids = power6_group_event_ids[84], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x700000008480a2a6ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 85 ] = { .pmg_name = "pm_vmx2", .pmg_desc = "VMX events", .pmg_event_ids = power6_group_event_ids[85], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x600000008088a2aaULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 86 ] = { .pmg_name = "pm_vmx3", .pmg_desc = "VMX events", .pmg_event_ids = power6_group_event_ids[86], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x600000008284aaacULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 87 ] = { .pmg_name = "pm_vmx4", .pmg_desc = "VMX events", .pmg_event_ids = power6_group_event_ids[87], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xb0000000828ea6a0ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 88 ] = { .pmg_name = "pm_vmx5", .pmg_desc = "VMX events", .pmg_event_ids = power6_group_event_ids[88], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xb00000008084aca2ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 89 ] = { .pmg_name = "pm_dfu", .pmg_desc = "DFU events", .pmg_event_ids = power6_group_event_ids[89], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xe00000008c88a2aeULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 90 ] = { .pmg_name = "pm_dfu2", .pmg_desc = "DFU events", .pmg_event_ids = power6_group_event_ids[90], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xe00000008a84a0a6ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 91 ] = { .pmg_name = "pm_fab", .pmg_desc = "Fabric events", .pmg_event_ids = power6_group_event_ids[91], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x500020003030a4acULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 92 ] = { .pmg_name = "pm_fab2", .pmg_desc = "Fabric events", .pmg_event_ids = power6_group_event_ids[92], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x50002000888aa2a0ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 93 ] = { .pmg_name = "pm_fab3", .pmg_desc = "Fabric events", .pmg_event_ids = power6_group_event_ids[93], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x500020003030aea6ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 94 ] = { .pmg_name = "pm_mem_dblpump", .pmg_desc = "Double pump", .pmg_event_ids = power6_group_event_ids[94], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x5000400030303434ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 95 ] = { .pmg_name = "pm_mem0_dblpump", .pmg_desc = "MCS0 Double pump", .pmg_event_ids = power6_group_event_ids[95], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x500040008082a4a6ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 96 ] = { .pmg_name = "pm_mem1_dblpump", .pmg_desc = "MCS1 Double pump", .pmg_event_ids = power6_group_event_ids[96], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x50004000888aacaeULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 97 ] = { .pmg_name = "pm_gxo", .pmg_desc = "GX outbound", .pmg_event_ids = power6_group_event_ids[97], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x500060008082a4a6ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 98 ] = { .pmg_name = "pm_gxi", .pmg_desc = "GX inbound", .pmg_event_ids = power6_group_event_ids[98], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x500060008688aaa0ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 99 ] = { .pmg_name = "pm_gx_dma", .pmg_desc = "DMA events", .pmg_event_ids = power6_group_event_ids[99], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x500060008086acaeULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 100 ] = { .pmg_name = "pm_L1_misc", .pmg_desc = "L1 misc events", .pmg_event_ids = power6_group_event_ids[100], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4004000082e2a80aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 101 ] = { .pmg_name = "pm_L2_data", .pmg_desc = "L2 load and store data", .pmg_event_ids = power6_group_event_ids[101], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x5000800030303434ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 102 ] = { .pmg_name = "pm_L2_ld_inst", .pmg_desc = "L2 Load instructions", .pmg_event_ids = power6_group_event_ids[102], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x5800a00030303486ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 103 ] = { .pmg_name = "pm_L2_castout_invalidate", .pmg_desc = "L2 castout and invalidate events", .pmg_event_ids = power6_group_event_ids[103], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x5000c00030303434ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 104 ] = { .pmg_name = "pm_L2_ldst_reqhit", .pmg_desc = "L2 load and store requests and hits", .pmg_event_ids = power6_group_event_ids[104], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x5000e00030303434ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 105 ] = { .pmg_name = "pm_L2_ld_data_slice", .pmg_desc = "L2 data loads by slice", .pmg_event_ids = power6_group_event_ids[105], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x500080008082a8aaULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 106 ] = { .pmg_name = "pm_L2_ld_inst_slice", .pmg_desc = "L2 instruction loads by slice", .pmg_event_ids = power6_group_event_ids[106], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x5000a0008082a8aaULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 107 ] = { .pmg_name = "pm_L2_st_slice", .pmg_desc = "L2 slice stores by slice", .pmg_event_ids = power6_group_event_ids[107], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x500080008486acaeULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 108 ] = { .pmg_name = "pm_L2miss_slice", .pmg_desc = "L2 misses by slice", .pmg_event_ids = power6_group_event_ids[108], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x5000a000843256acULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 109 ] = { .pmg_name = "pm_L2_castout_slice", .pmg_desc = "L2 castouts by slice", .pmg_event_ids = power6_group_event_ids[109], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x5000c0008082a8aaULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 110 ] = { .pmg_name = "pm_L2_invalidate_slice", .pmg_desc = "L2 invalidate by slice", .pmg_event_ids = power6_group_event_ids[110], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x5000c0008486acaeULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 111 ] = { .pmg_name = "pm_L2_ld_reqhit_slice", .pmg_desc = "L2 load requests and hist by slice", .pmg_event_ids = power6_group_event_ids[111], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x5000e0008082a8aaULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 112 ] = { .pmg_name = "pm_L2_st_reqhit_slice", .pmg_desc = "L2 store requests and hist by slice", .pmg_event_ids = power6_group_event_ids[112], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x5000e0008486acaeULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 113 ] = { .pmg_name = "pm_L2_redir_pref", .pmg_desc = "L2 redirect and prefetch", .pmg_event_ids = power6_group_event_ids[113], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x08400000cacc8886ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 114 ] = { .pmg_name = "pm_L3_SliceA", .pmg_desc = "L3 slice A events", .pmg_event_ids = power6_group_event_ids[114], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x50000000303058a4ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 115 ] = { .pmg_name = "pm_L3_SliceB", .pmg_desc = "L3 slice B events", .pmg_event_ids = power6_group_event_ids[115], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x50000000888a58acULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 116 ] = { .pmg_name = "pm_fpu_issue", .pmg_desc = "FPU issue events", .pmg_event_ids = power6_group_event_ids[116], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00300000c6c8eae4ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 117 ] = { .pmg_name = "pm_fpu_issue2", .pmg_desc = "FPU issue events", .pmg_event_ids = power6_group_event_ids[117], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00300000c0c2eceeULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 118 ] = { .pmg_name = "pm_fpu_issue3", .pmg_desc = "FPU issue events", .pmg_event_ids = power6_group_event_ids[118], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00330000e0e2eceeULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 119 ] = { .pmg_name = "pm_fpu0_flop", .pmg_desc = "FPU0 flop events", .pmg_event_ids = power6_group_event_ids[119], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xcc0000008082a484ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 120 ] = { .pmg_name = "pm_fpu0_misc", .pmg_desc = "FPU0 events", .pmg_event_ids = power6_group_event_ids[120], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xcc00000086a08286ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 121 ] = { .pmg_name = "pm_fpu0_misc2", .pmg_desc = "FPU0 events", .pmg_event_ids = power6_group_event_ids[121], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xdd00000080a6a4a6ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 122 ] = { .pmg_name = "pm_fpu0_misc3", .pmg_desc = "FPU0 events", .pmg_event_ids = power6_group_event_ids[122], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0d000000a0a28486ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 123 ] = { .pmg_name = "pm_fpu1_flop", .pmg_desc = "FPU1 flop events", .pmg_event_ids = power6_group_event_ids[123], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xcc000000888aac8cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 124 ] = { .pmg_name = "pm_fpu1_misc", .pmg_desc = "FPU1 events", .pmg_event_ids = power6_group_event_ids[124], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xcc0000008ea88a8eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 125 ] = { .pmg_name = "pm_fpu1_misc2", .pmg_desc = "FPU1 events", .pmg_event_ids = power6_group_event_ids[125], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xdd00000088aeacaeULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 126 ] = { .pmg_name = "pm_fpu1_misc3", .pmg_desc = "FPU1 events", .pmg_event_ids = power6_group_event_ids[126], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0d000000a8aa8c8eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 127 ] = { .pmg_name = "pm_fpu_flop", .pmg_desc = "FPU flop events", .pmg_event_ids = power6_group_event_ids[127], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xc000000030303434ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 128 ] = { .pmg_name = "pm_fpu_misc", .pmg_desc = "FPU events", .pmg_event_ids = power6_group_event_ids[128], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xdd00000030343434ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 129 ] = { .pmg_name = "pm_fpu_misc2", .pmg_desc = "FPU events", .pmg_event_ids = power6_group_event_ids[129], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0c00000034343030ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 130 ] = { .pmg_name = "pm_fpu_misc3", .pmg_desc = "FPU events", .pmg_event_ids = power6_group_event_ids[130], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0d00000034343030ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 131 ] = { .pmg_name = "pm_purr", .pmg_desc = "PURR events", .pmg_event_ids = power6_group_event_ids[131], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000000ef41e02ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 132 ] = { .pmg_name = "pm_suspend", .pmg_desc = "SUSPENDED events", .pmg_event_ids = power6_group_event_ids[132], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00900000001eec02ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 133 ] = { .pmg_name = "pm_dcache", .pmg_desc = "D cache", .pmg_event_ids = power6_group_event_ids[133], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000000c0e0c06ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 134 ] = { .pmg_name = "pm_derat_miss", .pmg_desc = "DERAT miss", .pmg_event_ids = power6_group_event_ids[134], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0090000f40404040ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 135 ] = { .pmg_name = "pm_derat_ref", .pmg_desc = "DERAT ref", .pmg_event_ids = power6_group_event_ids[135], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0080000f40404040ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 136 ] = { .pmg_name = "pm_ierat_miss", .pmg_desc = "IERAT miss", .pmg_event_ids = power6_group_event_ids[136], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0090000f46464646ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 137 ] = { .pmg_name = "pm_mrk_br", .pmg_desc = "Marked Branch events", .pmg_event_ids = power6_group_event_ids[137], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000052565202ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 138 ] = { .pmg_name = "pm_mrk_dsource", .pmg_desc = "Marked data sources", .pmg_event_ids = power6_group_event_ids[138], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000024a4c4cULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 139 ] = { .pmg_name = "pm_mrk_dsource2", .pmg_desc = "Marked data sources", .pmg_event_ids = power6_group_event_ids[139], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000048484e02ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 140 ] = { .pmg_name = "pm_mrk_dsource3", .pmg_desc = "Marked data sources", .pmg_event_ids = power6_group_event_ids[140], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000002802484eULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 141 ] = { .pmg_name = "pm_mrk_dsource4", .pmg_desc = "Marked data sources", .pmg_event_ids = power6_group_event_ids[141], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000004e4e2802ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 142 ] = { .pmg_name = "pm_mrk_dsource5", .pmg_desc = "Marked data sources", .pmg_event_ids = power6_group_event_ids[142], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000004a4c024aULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 143 ] = { .pmg_name = "pm_mrk_dsource6", .pmg_desc = "Marked data sources", .pmg_event_ids = power6_group_event_ids[143], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000004c4c4a02ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 144 ] = { .pmg_name = "pm_mrk_rejects", .pmg_desc = "Marked rejects", .pmg_event_ids = power6_group_event_ids[144], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0009000d34340230ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 145 ] = { .pmg_name = "pm_mrk_rejects2", .pmg_desc = "Marked rejects LSU0", .pmg_event_ids = power6_group_event_ids[145], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00090000e6e0c202ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 146 ] = { .pmg_name = "pm_mrk_rejects3", .pmg_desc = "Marked rejects LSU1", .pmg_event_ids = power6_group_event_ids[146], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00090000eee8ca02ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 147 ] = { .pmg_name = "pm_mrk_inst", .pmg_desc = "Marked instruction events", .pmg_event_ids = power6_group_event_ids[147], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000001c100a02ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 148 ] = { .pmg_name = "pm_mrk_fpu_fin", .pmg_desc = "Marked Floating Point instructions finished", .pmg_event_ids = power6_group_event_ids[148], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xd0000000828a1a02ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 149 ] = { .pmg_name = "pm_mrk_misc", .pmg_desc = "Marked misc events", .pmg_event_ids = power6_group_event_ids[149], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00090008341a0802ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 150 ] = { .pmg_name = "pm_mrk_misc2", .pmg_desc = "Marked misc events", .pmg_event_ids = power6_group_event_ids[150], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00080000e40a023eULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 151 ] = { .pmg_name = "pm_mrk_misc3", .pmg_desc = "Marked misc events", .pmg_event_ids = power6_group_event_ids[151], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xb009000088e40212ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 152 ] = { .pmg_name = "pm_mrk_misc4", .pmg_desc = "Marked misc events", .pmg_event_ids = power6_group_event_ids[152], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000001e1e021aULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 153 ] = { .pmg_name = "pm_mrk_st", .pmg_desc = "Marked stores events", .pmg_event_ids = power6_group_event_ids[153], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000006060602ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 154 ] = { .pmg_name = "pm_mrk_pteg", .pmg_desc = "Marked PTEG", .pmg_event_ids = power6_group_event_ids[154], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0010000040424402ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 155 ] = { .pmg_name = "pm_mrk_pteg2", .pmg_desc = "Marked PTEG", .pmg_event_ids = power6_group_event_ids[155], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0010000002404644ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 156 ] = { .pmg_name = "pm_mrk_pteg3", .pmg_desc = "Marked PTEG", .pmg_event_ids = power6_group_event_ids[156], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0010000046460246ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 157 ] = { .pmg_name = "pm_mrk_pteg4", .pmg_desc = "Marked PTEG", .pmg_event_ids = power6_group_event_ids[157], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0010000042024054ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 158 ] = { .pmg_name = "pm_mrk_pteg5", .pmg_desc = "Marked PTEG", .pmg_event_ids = power6_group_event_ids[158], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0010000044025442ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 159 ] = { .pmg_name = "pm_mrk_pteg6", .pmg_desc = "Marked PTEG", .pmg_event_ids = power6_group_event_ids[159], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x001000001e444202ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 160 ] = { .pmg_name = "pm_mrk_vmx", .pmg_desc = "Marked VMX", .pmg_event_ids = power6_group_event_ids[160], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x700000008c88ae02ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 161 ] = { .pmg_name = "pm_mrk_vmx2", .pmg_desc = "Marked VMX", .pmg_event_ids = power6_group_event_ids[161], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x60900000868ee002ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 162 ] = { .pmg_name = "pm_mrk_vmx3", .pmg_desc = "Marked VMX", .pmg_event_ids = power6_group_event_ids[162], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x700000008a821e02ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 163 ] = { .pmg_name = "pm_mrk_fp", .pmg_desc = "Marked FP events", .pmg_event_ids = power6_group_event_ids[163], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xd00000008230aa02ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 164 ] = { .pmg_name = "pm_mrk_derat_ref", .pmg_desc = "Marked DERAT ref", .pmg_event_ids = power6_group_event_ids[164], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0080000044444402ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 165 ] = { .pmg_name = "pm_mrk_derat_miss", .pmg_desc = "Marked DERAT miss", .pmg_event_ids = power6_group_event_ids[165], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0090000044444402ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 166 ] = { .pmg_name = "pm_dcache_edge", .pmg_desc = "D cache - edge", .pmg_event_ids = power6_group_event_ids[166], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000000d0e0c07ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 167 ] = { .pmg_name = "pm_lsu_lmq_edge", .pmg_desc = "LSU LMQ events - edge", .pmg_event_ids = power6_group_event_ids[167], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x98000000ac1d1da4ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 168 ] = { .pmg_name = "pm_gct_edge", .pmg_desc = "GCT events - edge", .pmg_event_ids = power6_group_event_ids[168], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x404000000909a7e8ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 169 ] = { .pmg_name = "pm_freq_edge", .pmg_desc = "Frequency events - edge", .pmg_event_ids = power6_group_event_ids[169], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000002b3d3c3cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 170 ] = { .pmg_name = "pm_disp_wait_edge", .pmg_desc = "Dispatch stalls - edge", .pmg_event_ids = power6_group_event_ids[170], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000560d050dULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 171 ] = { .pmg_name = "pm_edge1", .pmg_desc = "EDGE event group", .pmg_event_ids = power6_group_event_ids[171], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000006300d0c1f1eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 172 ] = { .pmg_name = "pm_edge2", .pmg_desc = "EDGE event group", .pmg_event_ids = power6_group_event_ids[172], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x400000008180a5a4ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 173 ] = { .pmg_name = "pm_edge3", .pmg_desc = "EDGE event group", .pmg_event_ids = power6_group_event_ids[173], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x009000000bf4ebeaULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 174 ] = { .pmg_name = "pm_edge4", .pmg_desc = "EDGE event group", .pmg_event_ids = power6_group_event_ids[174], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x400000008786a9a8ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 175 ] = { .pmg_name = "pm_edge5", .pmg_desc = "EDGE event group", .pmg_event_ids = power6_group_event_ids[175], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00900000fb17edecULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 176 ] = { .pmg_name = "pm_noedge5", .pmg_desc = "EDGE event group", .pmg_event_ids = power6_group_event_ids[176], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00900000fa16edecULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 177 ] = { .pmg_name = "pm_edge6", .pmg_desc = "EDGE event group", .pmg_event_ids = power6_group_event_ids[177], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000002b05050dULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 178 ] = { .pmg_name = "pm_noedge6", .pmg_desc = "EDGE event group", .pmg_event_ids = power6_group_event_ids[178], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000002a04040cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 179 ] = { .pmg_name = "pm_edge7", .pmg_desc = "EDGE event group", .pmg_event_ids = power6_group_event_ids[179], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000009091d1dULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 180 ] = { .pmg_name = "pm_noedge7", .pmg_desc = "NOEDGE event group", .pmg_event_ids = power6_group_event_ids[180], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000008081c1cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 181 ] = { .pmg_name = "pm_edge8", .pmg_desc = "EDGE event group", .pmg_event_ids = power6_group_event_ids[181], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00900000cd1dec07ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 182 ] = { .pmg_name = "pm_noedge8", .pmg_desc = "NOEDGE event group", .pmg_event_ids = power6_group_event_ids[182], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00900000cc1ced06ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 183 ] = { .pmg_name = "pm_edge9", .pmg_desc = "EDGE event group", .pmg_event_ids = power6_group_event_ids[183], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x80000000880d0ca2ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 184 ] = { .pmg_name = "pm_edge10", .pmg_desc = "EDGE event group", .pmg_event_ids = power6_group_event_ids[184], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x32000000ac3dae05ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 185 ] = { .pmg_name = "pm_noedge10", .pmg_desc = "NOEDGE event group", .pmg_event_ids = power6_group_event_ids[185], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x32000000ac3cae04ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 186 ] = { .pmg_name = "pm_hpm1", .pmg_desc = "HPM group", .pmg_event_ids = power6_group_event_ids[186], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xc00000003030341eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 187 ] = { .pmg_name = "pm_hpm2", .pmg_desc = "HPM group", .pmg_event_ids = power6_group_event_ids[187], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x8c0000000232301eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 188 ] = { .pmg_name = "pm_hpm3", .pmg_desc = "HPM group", .pmg_event_ids = power6_group_event_ids[188], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x800000001e80f002ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 189 ] = { .pmg_name = "pm_hpm4", .pmg_desc = "HPM group", .pmg_event_ids = power6_group_event_ids[189], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x800000000212a234ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 190 ] = { .pmg_name = "pm_hpm5", .pmg_desc = "HPM group", .pmg_event_ids = power6_group_event_ids[190], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xd0000000301e1616ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 191 ] = { .pmg_name = "pm_hpm6", .pmg_desc = "HPM group", .pmg_event_ids = power6_group_event_ids[191], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000058585a5aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 192 ] = { .pmg_name = "pm_hpm7", .pmg_desc = "HPM group", .pmg_event_ids = power6_group_event_ids[192], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000005a5a581eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 193 ] = { .pmg_name = "pm_hpm8", .pmg_desc = "HPM group", .pmg_event_ids = power6_group_event_ids[193], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xcc000000303030f0ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 194 ] = { .pmg_name = "pm_hpm9", .pmg_desc = "HPM group", .pmg_event_ids = power6_group_event_ids[194], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x80000000801e34a8ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 195 ] = { .pmg_name = "pm_hpm10", .pmg_desc = "HPM group", .pmg_event_ids = power6_group_event_ids[195], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x5040a00002325456ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 196 ] = { .pmg_name = "pm_mrk_derat_ref2", .pmg_desc = "Marked DERAT ref", .pmg_event_ids = power6_group_event_ids[196], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0080000044440244ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 197 ] = { .pmg_name = "pm_mrk_derat_miss2", .pmg_desc = "Marked DERAT miss", .pmg_event_ids = power6_group_event_ids[197], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0090000044440244ULL, .pmg_mmcra = 0x0000000000000001ULL } }; #endif papi-5.5.1/src/libpfm-3.y/lib/amd64_events_k8.h0000644000307100002310000010157313013651450020751 0ustar yarkhangraduate/* * Copyright (c) 2006, 2007 Advanced Micro Devices, Inc. * Contributed by Ray Bryant * Contributed by Robert Richter * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ /* History * * Feb 10 2006 -- Ray Bryant, raybry@mpdtxmail.amd.com * * Brought event table up-to-date with the 3.85 (October 2005) version of the * "BIOS and Kernel Developer's Guide for the AMD Athlon[tm] 64 and * AMD Opteron[tm] Processors," AMD Publication # 26094. * * Dec 12 2007 -- Robert Richter, robert.richter@amd.com * * Updated to: BIOS and Kernel Developer's Guide for AMD NPT Family * 0Fh Processors, Publication # 32559, Revision: 3.08, Issue Date: * July 2007 * * Feb 26 2009 -- Robert Richter, robert.richter@amd.com * * Updates and fixes of some revision flags and descriptions according * to these documents: * BIOS and Kernel Developer's Guide, #26094, Revision: 3.30 * BIOS and Kernel Developer's Guide, #32559, Revision: 3.12 */ static pme_amd64_entry_t amd64_k8_pe[]={ /* 0 */{.pme_name = "DISPATCHED_FPU", .pme_code = 0x00, .pme_desc = "Dispatched FPU Operations", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 7, .pme_umasks = { { .pme_uname = "OPS_ADD", .pme_udesc = "Add pipe ops", .pme_ucode = 0x01, }, { .pme_uname = "OPS_MULTIPLY", .pme_udesc = "Multiply pipe ops", .pme_ucode = 0x02, }, { .pme_uname = "OPS_STORE", .pme_udesc = "Store pipe ops", .pme_ucode = 0x04, }, { .pme_uname = "OPS_ADD_PIPE_LOAD_OPS", .pme_udesc = "Add pipe load ops", .pme_ucode = 0x08, }, { .pme_uname = "OPS_MULTIPLY_PIPE_LOAD_OPS", .pme_udesc = "Multiply pipe load ops", .pme_ucode = 0x10, }, { .pme_uname = "OPS_STORE_PIPE_LOAD_OPS", .pme_udesc = "Store pipe load ops", .pme_ucode = 0x20, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x3F, }, }, }, /* 1 */{.pme_name = "CYCLES_NO_FPU_OPS_RETIRED", .pme_code = 0x01, .pme_desc = "Cycles with no FPU Ops Retired", }, /* 2 */{.pme_name = "DISPATCHED_FPU_OPS_FAST_FLAG", .pme_code = 0x02, .pme_desc = "Dispatched Fast Flag FPU Operations", }, /* 3 */{.pme_name = "SEGMENT_REGISTER_LOADS", .pme_code = 0x20, .pme_desc = "Segment Register Loads", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 8, .pme_umasks = { { .pme_uname = "ES", .pme_udesc = "ES", .pme_ucode = 0x01, }, { .pme_uname = "CS", .pme_udesc = "CS", .pme_ucode = 0x02, }, { .pme_uname = "SS", .pme_udesc = "SS", .pme_ucode = 0x04, }, { .pme_uname = "DS", .pme_udesc = "DS", .pme_ucode = 0x08, }, { .pme_uname = "FS", .pme_udesc = "FS", .pme_ucode = 0x10, }, { .pme_uname = "GS", .pme_udesc = "GS", .pme_ucode = 0x20, }, { .pme_uname = "HS", .pme_udesc = "HS", .pme_ucode = 0x40, }, { .pme_uname = "ALL", .pme_udesc = "All segments", .pme_ucode = 0x7F, }, }, }, /* 4 */{.pme_name = "PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE", .pme_code = 0x21, .pme_desc = "Pipeline restart due to self-modifying code", }, /* 5 */{.pme_name = "PIPELINE_RESTART_DUE_TO_PROBE_HIT", .pme_code = 0x22, .pme_desc = "Pipeline restart due to probe hit", }, /* 6 */{.pme_name = "LS_BUFFER_2_FULL_CYCLES", .pme_code = 0x23, .pme_desc = "LS Buffer 2 Full", }, /* 7 */{.pme_name = "LOCKED_OPS", .pme_code = 0x24, .pme_desc = "Locked Operations", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 4, .pme_umasks = { { .pme_uname = "EXECUTED", .pme_udesc = "The number of locked instructions executed", .pme_ucode = 0x01, }, { .pme_uname = "CYCLES_SPECULATIVE_PHASE", .pme_udesc = "The number of cycles spent in speculative phase", .pme_ucode = 0x02, }, { .pme_uname = "CYCLES_NON_SPECULATIVE_PHASE", .pme_udesc = "The number of cycles spent in non-speculative phase (including cache miss penalty)", .pme_ucode = 0x04, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x07, }, }, }, /* 8 */{.pme_name = "MEMORY_REQUESTS", .pme_code = 0x65, .pme_desc = "Memory Requests by Type", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 4, .pme_umasks = { { .pme_uname = "NON_CACHEABLE", .pme_udesc = "Requests to non-cacheable (UC) memory", .pme_ucode = 0x01, }, { .pme_uname = "WRITE_COMBINING", .pme_udesc = "Requests to write-combining (WC) memory or WC buffer flushes to WB memory", .pme_ucode = 0x02, }, { .pme_uname = "STREAMING_STORE", .pme_udesc = "Streaming store (SS) requests", .pme_ucode = 0x80, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x83, }, }, }, /* 9 */{.pme_name = "DATA_CACHE_ACCESSES", .pme_code = 0x40, .pme_desc = "Data Cache Accesses", }, /* 10 */{.pme_name = "DATA_CACHE_MISSES", .pme_code = 0x41, .pme_desc = "Data Cache Misses", }, /* 11 */{.pme_name = "DATA_CACHE_REFILLS", .pme_code = 0x42, .pme_desc = "Data Cache Refills from L2 or System", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 6, .pme_umasks = { { .pme_uname = "SYSTEM", .pme_udesc = "Refill from System", .pme_ucode = 0x01, }, { .pme_uname = "L2_SHARED", .pme_udesc = "Shared-state line from L2", .pme_ucode = 0x02, }, { .pme_uname = "L2_EXCLUSIVE", .pme_udesc = "Exclusive-state line from L2", .pme_ucode = 0x04, }, { .pme_uname = "L2_OWNED", .pme_udesc = "Owned-state line from L2", .pme_ucode = 0x08, }, { .pme_uname = "L2_MODIFIED", .pme_udesc = "Modified-state line from L2", .pme_ucode = 0x10, }, { .pme_uname = "ALL", .pme_udesc = "Shared, Exclusive, Owned, Modified State Refills", .pme_ucode = 0x1F, }, }, }, /* 12 */{.pme_name = "DATA_CACHE_REFILLS_FROM_SYSTEM", .pme_code = 0x43, .pme_desc = "Data Cache Refills from System", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 6, .pme_umasks = { { .pme_uname = "INVALID", .pme_udesc = "Invalid", .pme_ucode = 0x01, }, { .pme_uname = "SHARED", .pme_udesc = "Shared", .pme_ucode = 0x02, }, { .pme_uname = "EXCLUSIVE", .pme_udesc = "Exclusive", .pme_ucode = 0x04, }, { .pme_uname = "OWNED", .pme_udesc = "Owned", .pme_ucode = 0x08, }, { .pme_uname = "MODIFIED", .pme_udesc = "Modified", .pme_ucode = 0x10, }, { .pme_uname = "ALL", .pme_udesc = "Invalid, Shared, Exclusive, Owned, Modified", .pme_ucode = 0x1F, }, }, }, /* 13 */{.pme_name = "DATA_CACHE_LINES_EVICTED", .pme_code = 0x44, .pme_desc = "Data Cache Lines Evicted", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 6, .pme_umasks = { { .pme_uname = "INVALID", .pme_udesc = "Invalid", .pme_ucode = 0x01, }, { .pme_uname = "SHARED", .pme_udesc = "Shared", .pme_ucode = 0x02, }, { .pme_uname = "EXCLUSIVE", .pme_udesc = "Exclusive", .pme_ucode = 0x04, }, { .pme_uname = "OWNED", .pme_udesc = "Owned", .pme_ucode = 0x08, }, { .pme_uname = "MODIFIED", .pme_udesc = "Modified", .pme_ucode = 0x10, }, { .pme_uname = "ALL", .pme_udesc = "Invalid, Shared, Exclusive, Owned, Modified", .pme_ucode = 0x1F, }, }, }, /* 14 */{.pme_name = "L1_DTLB_MISS_AND_L2_DTLB_HIT", .pme_code = 0x45, .pme_desc = "L1 DTLB Miss and L2 DTLB Hit", }, /* 15 */{.pme_name = "L1_DTLB_AND_L2_DTLB_MISS", .pme_code = 0x46, .pme_desc = "L1 DTLB and L2 DTLB Miss", }, /* 16 */{.pme_name = "MISALIGNED_ACCESSES", .pme_code = 0x47, .pme_desc = "Misaligned Accesses", }, /* 17 */{.pme_name = "MICROARCHITECTURAL_LATE_CANCEL_OF_AN_ACCESS", .pme_code = 0x48, .pme_desc = "Microarchitectural Late Cancel of an Access", }, /* 18 */{.pme_name = "MICROARCHITECTURAL_EARLY_CANCEL_OF_AN_ACCESS", .pme_code = 0x49, .pme_desc = "Microarchitectural Early Cancel of an Access", }, /* 19 */{.pme_name = "SCRUBBER_SINGLE_BIT_ECC_ERRORS", .pme_code = 0x4A, .pme_desc = "Single-bit ECC Errors Recorded by Scrubber", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 3, .pme_umasks = { { .pme_uname = "SCRUBBER_ERROR", .pme_udesc = "Scrubber error", .pme_ucode = 0x01, }, { .pme_uname = "PIGGYBACK_ERROR", .pme_udesc = "Piggyback scrubber errors", .pme_ucode = 0x02, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x03, }, }, }, /* 20 */{.pme_name = "PREFETCH_INSTRUCTIONS_DISPATCHED", .pme_code = 0x4B, .pme_desc = "Prefetch Instructions Dispatched", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 4, .pme_umasks = { { .pme_uname = "LOAD", .pme_udesc = "Load (Prefetch, PrefetchT0/T1/T2)", .pme_ucode = 0x01, }, { .pme_uname = "STORE", .pme_udesc = "Store (PrefetchW)", .pme_ucode = 0x02, }, { .pme_uname = "NTA", .pme_udesc = "NTA (PrefetchNTA)", .pme_ucode = 0x04, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x07, }, }, }, /* 21 */{.pme_name = "DCACHE_MISSES_BY_LOCKED_INSTRUCTIONS", .pme_code = 0x4C, .pme_desc = "DCACHE Misses by Locked Instructions", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 2, .pme_umasks = { { .pme_uname = "DATA_CACHE_MISSES_BY_LOCKED_INSTRUCTIONS", .pme_udesc = "Data cache misses by locked instructions", .pme_ucode = 0x02, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x02, }, }, }, /* 22 */{.pme_name = "DATA_PREFETCHES", .pme_code = 0x67, .pme_desc = "Data Prefetcher", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 3, .pme_umasks = { { .pme_uname = "CANCELLED", .pme_udesc = "Cancelled prefetches", .pme_ucode = 0x01, }, { .pme_uname = "ATTEMPTED", .pme_udesc = "Prefetch attempts", .pme_ucode = 0x02, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x03, }, }, }, /* 23 */{.pme_name = "SYSTEM_READ_RESPONSES", .pme_code = 0x6C, .pme_desc = "System Read Responses by Coherency State", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 4, .pme_umasks = { { .pme_uname = "EXCLUSIVE", .pme_udesc = "Exclusive", .pme_ucode = 0x01, }, { .pme_uname = "MODIFIED", .pme_udesc = "Modified", .pme_ucode = 0x02, }, { .pme_uname = "SHARED", .pme_udesc = "Shared", .pme_ucode = 0x04, }, { .pme_uname = "ALL", .pme_udesc = "Exclusive, Modified, Shared", .pme_ucode = 0x07, }, }, }, /* 24 */{.pme_name = "QUADWORDS_WRITTEN_TO_SYSTEM", .pme_code = 0x6D, .pme_desc = "Quadwords Written to System", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 2, .pme_umasks = { { .pme_uname = "QUADWORD_WRITE_TRANSFER", .pme_udesc = "Quadword write transfer", .pme_ucode = 0x01, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x01, }, }, }, /* 25 */{.pme_name = "REQUESTS_TO_L2", .pme_code = 0x7D, .pme_desc = "Requests to L2 Cache", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 6, .pme_umasks = { { .pme_uname = "INSTRUCTIONS", .pme_udesc = "IC fill", .pme_ucode = 0x01, }, { .pme_uname = "DATA", .pme_udesc = "DC fill", .pme_ucode = 0x02, }, { .pme_uname = "TLB_WALK", .pme_udesc = "TLB fill (page table walks)", .pme_ucode = 0x04, }, { .pme_uname = "SNOOP", .pme_udesc = "Tag snoop request", .pme_ucode = 0x08, }, { .pme_uname = "CANCELLED", .pme_udesc = "Cancelled request", .pme_ucode = 0x10, }, { .pme_uname = "ALL", .pme_udesc = "All non-cancelled requests", .pme_ucode = 0x1F, }, }, }, /* 26 */{.pme_name = "L2_CACHE_MISS", .pme_code = 0x7E, .pme_desc = "L2 Cache Misses", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 4, .pme_umasks = { { .pme_uname = "INSTRUCTIONS", .pme_udesc = "IC fill", .pme_ucode = 0x01, }, { .pme_uname = "DATA", .pme_udesc = "DC fill (includes possible replays, whereas event 41h does not)", .pme_ucode = 0x02, }, { .pme_uname = "TLB_WALK", .pme_udesc = "TLB page table walk", .pme_ucode = 0x04, }, { .pme_uname = "ALL", .pme_udesc = "Instructions, Data, TLB walk", .pme_ucode = 0x07, }, }, }, /* 27 */{.pme_name = "L2_FILL_WRITEBACK", .pme_code = 0x7F, .pme_desc = "L2 Fill/Writeback", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 4, .pme_umasks = { { .pme_uname = "L2_FILLS", .pme_udesc = "L2 fills (victims from L1 caches, TLB page table walks and data prefetches)", .pme_ucode = 0x01, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x01, .pme_uflags = PFMLIB_AMD64_TILL_K8_REV_E, }, { .pme_uname = "L2_WRITEBACKS", .pme_udesc = "L2 Writebacks to system.", .pme_ucode = 0x02, .pme_uflags = PFMLIB_AMD64_K8_REV_F, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x03, .pme_uflags = PFMLIB_AMD64_K8_REV_F, }, }, }, /* 28 */{.pme_name = "INSTRUCTION_CACHE_FETCHES", .pme_code = 0x80, .pme_desc = "Instruction Cache Fetches", }, /* 29 */{.pme_name = "INSTRUCTION_CACHE_MISSES", .pme_code = 0x81, .pme_desc = "Instruction Cache Misses", }, /* 30 */{.pme_name = "INSTRUCTION_CACHE_REFILLS_FROM_L2", .pme_code = 0x82, .pme_desc = "Instruction Cache Refills from L2", }, /* 31 */{.pme_name = "INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM", .pme_code = 0x83, .pme_desc = "Instruction Cache Refills from System", }, /* 32 */{.pme_name = "L1_ITLB_MISS_AND_L2_ITLB_HIT", .pme_code = 0x84, .pme_desc = "L1 ITLB Miss and L2 ITLB Hit", }, /* 33 */{.pme_name = "L1_ITLB_MISS_AND_L2_ITLB_MISS", .pme_code = 0x85, .pme_desc = "L1 ITLB Miss and L2 ITLB Miss", }, /* 34 */{.pme_name = "PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE", .pme_code = 0x86, .pme_desc = "Pipeline Restart Due to Instruction Stream Probe", }, /* 35 */{.pme_name = "INSTRUCTION_FETCH_STALL", .pme_code = 0x87, .pme_desc = "Instruction Fetch Stall", }, /* 36 */{.pme_name = "RETURN_STACK_HITS", .pme_code = 0x88, .pme_desc = "Return Stack Hits", }, /* 37 */{.pme_name = "RETURN_STACK_OVERFLOWS", .pme_code = 0x89, .pme_desc = "Return Stack Overflows", }, /* 38 */{.pme_name = "RETIRED_CLFLUSH_INSTRUCTIONS", .pme_code = 0x26, .pme_desc = "Retired CLFLUSH Instructions", }, /* 39 */{.pme_name = "RETIRED_CPUID_INSTRUCTIONS", .pme_code = 0x27, .pme_desc = "Retired CPUID Instructions", }, /* 40 */{.pme_name = "CPU_CLK_UNHALTED", .pme_code = 0x76, .pme_desc = "CPU Clocks not Halted", }, /* 41 */{.pme_name = "RETIRED_INSTRUCTIONS", .pme_code = 0xC0, .pme_desc = "Retired Instructions", }, /* 42 */{.pme_name = "RETIRED_UOPS", .pme_code = 0xC1, .pme_desc = "Retired uops", }, /* 43 */{.pme_name = "RETIRED_BRANCH_INSTRUCTIONS", .pme_code = 0xC2, .pme_desc = "Retired Branch Instructions", }, /* 44 */{.pme_name = "RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS", .pme_code = 0xC3, .pme_desc = "Retired Mispredicted Branch Instructions", }, /* 45 */{.pme_name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS", .pme_code = 0xC4, .pme_desc = "Retired Taken Branch Instructions", }, /* 46 */{.pme_name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED", .pme_code = 0xC5, .pme_desc = "Retired Taken Branch Instructions Mispredicted", }, /* 47 */{.pme_name = "RETIRED_FAR_CONTROL_TRANSFERS", .pme_code = 0xC6, .pme_desc = "Retired Far Control Transfers", }, /* 48 */{.pme_name = "RETIRED_BRANCH_RESYNCS", .pme_code = 0xC7, .pme_desc = "Retired Branch Resyncs", }, /* 49 */{.pme_name = "RETIRED_NEAR_RETURNS", .pme_code = 0xC8, .pme_desc = "Retired Near Returns", }, /* 50 */{.pme_name = "RETIRED_NEAR_RETURNS_MISPREDICTED", .pme_code = 0xC9, .pme_desc = "Retired Near Returns Mispredicted", }, /* 51 */{.pme_name = "RETIRED_INDIRECT_BRANCHES_MISPREDICTED", .pme_code = 0xCA, .pme_desc = "Retired Indirect Branches Mispredicted", }, /* 52 */{.pme_name = "RETIRED_MMX_AND_FP_INSTRUCTIONS", .pme_code = 0xCB, .pme_desc = "Retired MMX/FP Instructions", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 5, .pme_umasks = { { .pme_uname = "X87", .pme_udesc = "x87 instructions", .pme_ucode = 0x01, }, { .pme_uname = "MMX_AND_3DNOW", .pme_udesc = "MMX and 3DNow! instructions", .pme_ucode = 0x02, }, { .pme_uname = "PACKED_SSE_AND_SSE2", .pme_udesc = "Packed SSE and SSE2 instructions", .pme_ucode = 0x04, }, { .pme_uname = "SCALAR_SSE_AND_SSE2", .pme_udesc = "Scalar SSE and SSE2 instructions", .pme_ucode = 0x08, }, { .pme_uname = "ALL", .pme_udesc = "X87, MMX(TM), 3DNow!(TM), Scalar and Packed SSE and SSE2 instructions", .pme_ucode = 0x0F, }, }, }, /* 53 */{.pme_name = "RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS", .pme_code = 0xCC, .pme_desc = "Retired Fastpath Double Op Instructions", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 4, .pme_umasks = { { .pme_uname = "POSITION_0", .pme_udesc = "With low op in position 0", .pme_ucode = 0x01, }, { .pme_uname = "POSITION_1", .pme_udesc = "With low op in position 1", .pme_ucode = 0x02, }, { .pme_uname = "POSITION_2", .pme_udesc = "With low op in position 2", .pme_ucode = 0x04, }, { .pme_uname = "ALL", .pme_udesc = "With low op in position 0, 1, or 2", .pme_ucode = 0x07, }, }, }, /* 54 */{.pme_name = "INTERRUPTS_MASKED_CYCLES", .pme_code = 0xCD, .pme_desc = "Interrupts-Masked Cycles", }, /* 55 */{.pme_name = "INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING", .pme_code = 0xCE, .pme_desc = "Interrupts-Masked Cycles with Interrupt Pending", }, /* 56 */{.pme_name = "INTERRUPTS_TAKEN", .pme_code = 0xCF, .pme_desc = "Interrupts Taken", }, /* 57 */{.pme_name = "DECODER_EMPTY", .pme_code = 0xD0, .pme_desc = "Decoder Empty", }, /* 58 */{.pme_name = "DISPATCH_STALLS", .pme_code = 0xD1, .pme_desc = "Dispatch Stalls", }, /* 59 */{.pme_name = "DISPATCH_STALL_FOR_BRANCH_ABORT", .pme_code = 0xD2, .pme_desc = "Dispatch Stall for Branch Abort to Retire", }, /* 60 */{.pme_name = "DISPATCH_STALL_FOR_SERIALIZATION", .pme_code = 0xD3, .pme_desc = "Dispatch Stall for Serialization", }, /* 61 */{.pme_name = "DISPATCH_STALL_FOR_SEGMENT_LOAD", .pme_code = 0xD4, .pme_desc = "Dispatch Stall for Segment Load", }, /* 62 */{.pme_name = "DISPATCH_STALL_FOR_REORDER_BUFFER_FULL", .pme_code = 0xD5, .pme_desc = "Dispatch Stall for Reorder Buffer Full", }, /* 63 */{.pme_name = "DISPATCH_STALL_FOR_RESERVATION_STATION_FULL", .pme_code = 0xD6, .pme_desc = "Dispatch Stall for Reservation Station Full", }, /* 64 */{.pme_name = "DISPATCH_STALL_FOR_FPU_FULL", .pme_code = 0xD7, .pme_desc = "Dispatch Stall for FPU Full", }, /* 65 */{.pme_name = "DISPATCH_STALL_FOR_LS_FULL", .pme_code = 0xD8, .pme_desc = "Dispatch Stall for LS Full", }, /* 66 */{.pme_name = "DISPATCH_STALL_WAITING_FOR_ALL_QUIET", .pme_code = 0xD9, .pme_desc = "Dispatch Stall Waiting for All Quiet", }, /* 67 */{.pme_name = "DISPATCH_STALL_FOR_FAR_TRANSFER_OR_RSYNC", .pme_code = 0xDA, .pme_desc = "Dispatch Stall for Far Transfer or Resync to Retire", }, /* 68 */{.pme_name = "FPU_EXCEPTIONS", .pme_code = 0xDB, .pme_desc = "FPU Exceptions", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 5, .pme_umasks = { { .pme_uname = "X87_RECLASS_MICROFAULTS", .pme_udesc = "x87 reclass microfaults", .pme_ucode = 0x01, }, { .pme_uname = "SSE_RETYPE_MICROFAULTS", .pme_udesc = "SSE retype microfaults", .pme_ucode = 0x02, }, { .pme_uname = "SSE_RECLASS_MICROFAULTS", .pme_udesc = "SSE reclass microfaults", .pme_ucode = 0x04, }, { .pme_uname = "SSE_AND_X87_MICROTRAPS", .pme_udesc = "SSE and x87 microtraps", .pme_ucode = 0x08, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x0F, }, }, }, /* 69 */{.pme_name = "DR0_BREAKPOINT_MATCHES", .pme_code = 0xDC, .pme_desc = "DR0 Breakpoint Matches", }, /* 70 */{.pme_name = "DR1_BREAKPOINT_MATCHES", .pme_code = 0xDD, .pme_desc = "DR1 Breakpoint Matches", }, /* 71 */{.pme_name = "DR2_BREAKPOINT_MATCHES", .pme_code = 0xDE, .pme_desc = "DR2 Breakpoint Matches", }, /* 72 */{.pme_name = "DR3_BREAKPOINT_MATCHES", .pme_code = 0xDF, .pme_desc = "DR3 Breakpoint Matches", }, /* 73 */{.pme_name = "DRAM_ACCESSES_PAGE", .pme_code = 0xE0, .pme_desc = "DRAM Accesses", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 4, .pme_umasks = { { .pme_uname = "HIT", .pme_udesc = "Page hit", .pme_ucode = 0x01, }, { .pme_uname = "MISS", .pme_udesc = "Page Miss", .pme_ucode = 0x02, }, { .pme_uname = "CONFLICT", .pme_udesc = "Page Conflict", .pme_ucode = 0x04, }, { .pme_uname = "ALL", .pme_udesc = "Page Hit, Miss, or Conflict", .pme_ucode = 0x07, }, }, }, /* 74 */{.pme_name = "MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOWS", .pme_code = 0xE1, .pme_desc = "Memory Controller Page Table Overflows", }, /* 75 */{.pme_name = "MEMORY_CONTROLLER_TURNAROUNDS", .pme_code = 0xE3, .pme_desc = "Memory Controller Turnarounds", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 4, .pme_umasks = { { .pme_uname = "CHIP_SELECT", .pme_udesc = "DIMM (chip select) turnaround", .pme_ucode = 0x01, }, { .pme_uname = "READ_TO_WRITE", .pme_udesc = "Read to write turnaround", .pme_ucode = 0x02, }, { .pme_uname = "WRITE_TO_READ", .pme_udesc = "Write to read turnaround", .pme_ucode = 0x04, }, { .pme_uname = "ALL", .pme_udesc = "All Memory Controller Turnarounds", .pme_ucode = 0x07, }, }, }, /* 76 */{.pme_name = "MEMORY_CONTROLLER_BYPASS", .pme_code = 0xE4, .pme_desc = "Memory Controller Bypass Counter Saturation", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 5, .pme_umasks = { { .pme_uname = "HIGH_PRIORITY", .pme_udesc = "Memory controller high priority bypass", .pme_ucode = 0x01, }, { .pme_uname = "LOW_PRIORITY", .pme_udesc = "Memory controller low priority bypass", .pme_ucode = 0x02, }, { .pme_uname = "DRAM_INTERFACE", .pme_udesc = "DRAM controller interface bypass", .pme_ucode = 0x04, }, { .pme_uname = "DRAM_QUEUE", .pme_udesc = "DRAM controller queue bypass", .pme_ucode = 0x08, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x0F, }, }, }, /* 77 */{.pme_name = "SIZED_BLOCKS", .pme_code = 0xE5, .pme_desc = "Sized Blocks", .pme_flags = PFMLIB_AMD64_UMASK_COMBO | PFMLIB_AMD64_K8_REV_D, .pme_numasks = 5, .pme_umasks = { { .pme_uname = "32_BYTE_WRITES", .pme_udesc = "32-byte Sized Writes", .pme_ucode = 0x04, }, { .pme_uname = "64_BYTE_WRITES", .pme_udesc = "64-byte Sized Writes", .pme_ucode = 0x08, }, { .pme_uname = "32_BYTE_READS", .pme_udesc = "32-byte Sized Reads", .pme_ucode = 0x10, }, { .pme_uname = "64_BYTE_READS", .pme_udesc = "64-byte Sized Reads", .pme_ucode = 0x20, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x3C, }, }, }, /* 78 */{.pme_name = "THERMAL_STATUS_AND_ECC_ERRORS", .pme_code = 0xE8, .pme_desc = "Thermal Status and ECC Errors", .pme_flags = PFMLIB_AMD64_UMASK_COMBO | PFMLIB_AMD64_K8_REV_E, .pme_numasks = 7, .pme_umasks = { { .pme_uname = "CLKS_CPU_ACTIVE", .pme_udesc = "Number of clocks CPU is active when HTC is active", .pme_ucode = 0x01, .pme_uflags = PFMLIB_AMD64_K8_REV_F, }, { .pme_uname = "CLKS_CPU_INACTIVE", .pme_udesc = "Number of clocks CPU clock is inactive when HTC is active", .pme_ucode = 0x02, .pme_uflags = PFMLIB_AMD64_K8_REV_F, }, { .pme_uname = "CLKS_DIE_TEMP_TOO_HIGH", .pme_udesc = "Number of clocks when die temperature is higher than the software high temperature threshold", .pme_ucode = 0x04, .pme_uflags = PFMLIB_AMD64_K8_REV_F, }, { .pme_uname = "CLKS_TEMP_THRESHOLD_EXCEEDED", .pme_udesc = "Number of clocks when high temperature threshold was exceeded", .pme_ucode = 0x08, .pme_uflags = PFMLIB_AMD64_K8_REV_F, }, { .pme_uname = "DRAM_ECC_ERRORS", .pme_udesc = "Number of correctable and Uncorrectable DRAM ECC errors", .pme_ucode = 0x80, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x80, .pme_uflags = PFMLIB_AMD64_TILL_K8_REV_E, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x8F, .pme_uflags = PFMLIB_AMD64_K8_REV_F, }, }, }, /* 79 */{.pme_name = "CPU_IO_REQUESTS_TO_MEMORY_IO", .pme_code = 0xE9, .pme_desc = "CPU/IO Requests to Memory/IO", .pme_flags = PFMLIB_AMD64_UMASK_COMBO | PFMLIB_AMD64_K8_REV_E, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "I_O_TO_I_O", .pme_udesc = "I/O to I/O", .pme_ucode = 0x01, }, { .pme_uname = "I_O_TO_MEM", .pme_udesc = "I/O to Mem", .pme_ucode = 0x02, }, { .pme_uname = "CPU_TO_I_O", .pme_udesc = "CPU to I/O", .pme_ucode = 0x04, }, { .pme_uname = "CPU_TO_MEM", .pme_udesc = "CPU to Mem", .pme_ucode = 0x08, }, { .pme_uname = "TO_REMOTE_NODE", .pme_udesc = "To remote node", .pme_ucode = 0x10, }, { .pme_uname = "TO_LOCAL_NODE", .pme_udesc = "To local node", .pme_ucode = 0x20, }, { .pme_uname = "FROM_REMOTE_NODE", .pme_udesc = "From remote node", .pme_ucode = 0x40, }, { .pme_uname = "FROM_LOCAL_NODE", .pme_udesc = "From local node", .pme_ucode = 0x80, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0xFF, }, }, }, /* 80 */{.pme_name = "CACHE_BLOCK", .pme_code = 0xEA, .pme_desc = "Cache Block Commands", .pme_flags = PFMLIB_AMD64_UMASK_COMBO | PFMLIB_AMD64_K8_REV_E, .pme_numasks = 6, .pme_umasks = { { .pme_uname = "VICTIM_WRITEBACK", .pme_udesc = "Victim Block (Writeback)", .pme_ucode = 0x01, }, { .pme_uname = "DCACHE_LOAD_MISS", .pme_udesc = "Read Block (Dcache load miss refill)", .pme_ucode = 0x04, }, { .pme_uname = "SHARED_ICACHE_REFILL", .pme_udesc = "Read Block Shared (Icache refill)", .pme_ucode = 0x08, }, { .pme_uname = "READ_BLOCK_MODIFIED", .pme_udesc = "Read Block Modified (Dcache store miss refill)", .pme_ucode = 0x10, }, { .pme_uname = "READ_TO_DIRTY", .pme_udesc = "Change to Dirty (first store to clean block already in cache)", .pme_ucode = 0x20, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x3D, }, }, }, /* 81 */{.pme_name = "SIZED_COMMANDS", .pme_code = 0xEB, .pme_desc = "Sized Commands", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 8, .pme_umasks = { { .pme_uname = "NON_POSTED_WRITE_BYTE", .pme_udesc = "NonPosted SzWr Byte (1-32 bytes) Legacy or mapped I/O, typically 1-4 bytes", .pme_ucode = 0x01, }, { .pme_uname = "NON_POSTED_WRITE_DWORD", .pme_udesc = "NonPosted SzWr Dword (1-16 dwords) Legacy or mapped I/O, typically 1 dword", .pme_ucode = 0x02, }, { .pme_uname = "POSTED_WRITE_BYTE", .pme_udesc = "Posted SzWr Byte (1-32 bytes) Sub-cache-line DMA writes, size varies; also flushes of partially-filled Write Combining buffer", .pme_ucode = 0x04, }, { .pme_uname = "POSTED_WRITE_DWORD", .pme_udesc = "Posted SzWr Dword (1-16 dwords) Block-oriented DMA writes, often cache-line sized; also processor Write Combining buffer flushes", .pme_ucode = 0x08, }, { .pme_uname = "READ_BYTE_4_BYTES", .pme_udesc = "SzRd Byte (4 bytes) Legacy or mapped I/O", .pme_ucode = 0x10, }, { .pme_uname = "READ_DWORD_1_16_DWORDS", .pme_udesc = "SzRd Dword (1-16 dwords) Block-oriented DMA reads, typically cache-line size", .pme_ucode = 0x20, }, { .pme_uname = "READ_MODIFY_WRITE", .pme_udesc = "RdModWr", .pme_ucode = 0x40, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x7F, }, }, }, /* 82 */{.pme_name = "PROBE", .pme_code = 0xEC, .pme_desc = "Probe Responses and Upstream Requests", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 9, .pme_umasks = { { .pme_uname = "MISS", .pme_udesc = "Probe miss", .pme_ucode = 0x01, }, { .pme_uname = "HIT_CLEAN", .pme_udesc = "Probe hit clean", .pme_ucode = 0x02, }, { .pme_uname = "HIT_DIRTY_NO_MEMORY_CANCEL", .pme_udesc = "Probe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)", .pme_ucode = 0x04, }, { .pme_uname = "HIT_DIRTY_WITH_MEMORY_CANCEL", .pme_udesc = "Probe hit dirty with memory cancel (probed by DMA read or cache refill request)", .pme_ucode = 0x08, }, { .pme_uname = "UPSTREAM_DISPLAY_REFRESH_READS", .pme_udesc = "Upstream display refresh reads", .pme_ucode = 0x10, }, { .pme_uname = "UPSTREAM_NON_DISPLAY_REFRESH_READS", .pme_udesc = "Upstream non-display refresh reads", .pme_ucode = 0x20, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x3F, .pme_uflags = PFMLIB_AMD64_TILL_K8_REV_C, }, { .pme_uname = "UPSTREAM_WRITES", .pme_udesc = "Upstream writes", .pme_ucode = 0x40, .pme_uflags = PFMLIB_AMD64_K8_REV_D, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x7F, .pme_uflags = PFMLIB_AMD64_K8_REV_D, }, }, }, /* 83 */{.pme_name = "GART", .pme_code = 0xEE, .pme_desc = "GART Events", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 4, .pme_umasks = { { .pme_uname = "APERTURE_HIT_FROM_CPU", .pme_udesc = "GART aperture hit on access from CPU", .pme_ucode = 0x01, }, { .pme_uname = "APERTURE_HIT_FROM_IO", .pme_udesc = "GART aperture hit on access from I/O", .pme_ucode = 0x02, }, { .pme_uname = "MISS", .pme_udesc = "GART miss", .pme_ucode = 0x04, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x07, }, }, }, /* 84 */{.pme_name = "HYPERTRANSPORT_LINK0", .pme_code = 0xF6, .pme_desc = "HyperTransport Link 0 Transmit Bandwidth", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 5, .pme_umasks = { { .pme_uname = "COMMAND_DWORD_SENT", .pme_udesc = "Command dword sent", .pme_ucode = 0x01, }, { .pme_uname = "DATA_DWORD_SENT", .pme_udesc = "Data dword sent", .pme_ucode = 0x02, }, { .pme_uname = "BUFFER_RELEASE_DWORD_SENT", .pme_udesc = "Buffer release dword sent", .pme_ucode = 0x04, }, { .pme_uname = "NOP_DWORD_SENT", .pme_udesc = "Nop dword sent (idle)", .pme_ucode = 0x08, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x0F, }, }, }, /* 85 */{.pme_name = "HYPERTRANSPORT_LINK1", .pme_code = 0xF7, .pme_desc = "HyperTransport Link 1 Transmit Bandwidth", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 5, .pme_umasks = { { .pme_uname = "COMMAND_DWORD_SENT", .pme_udesc = "Command dword sent", .pme_ucode = 0x01, }, { .pme_uname = "DATA_DWORD_SENT", .pme_udesc = "Data dword sent", .pme_ucode = 0x02, }, { .pme_uname = "BUFFER_RELEASE_DWORD_SENT", .pme_udesc = "Buffer release dword sent", .pme_ucode = 0x04, }, { .pme_uname = "NOP_DWORD_SENT", .pme_udesc = "Nop dword sent (idle)", .pme_ucode = 0x08, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x0F, }, }, }, /* 86 */{.pme_name = "HYPERTRANSPORT_LINK2", .pme_code = 0xF8, .pme_desc = "HyperTransport Link 2 Transmit Bandwidth", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 5, .pme_umasks = { { .pme_uname = "COMMAND_DWORD_SENT", .pme_udesc = "Command dword sent", .pme_ucode = 0x01, }, { .pme_uname = "DATA_DWORD_SENT", .pme_udesc = "Data dword sent", .pme_ucode = 0x02, }, { .pme_uname = "BUFFER_RELEASE_DWORD_SENT", .pme_udesc = "Buffer release dword sent", .pme_ucode = 0x04, }, { .pme_uname = "NOP_DWORD_SENT", .pme_udesc = "Nop dword sent (idle)", .pme_ucode = 0x08, }, { .pme_uname = "ALL", .pme_udesc = "All sub-events selected", .pme_ucode = 0x0F, }, }, }, }; #define PME_AMD64_K8_EVENT_COUNT (sizeof(amd64_k8_pe)/sizeof(pme_amd64_entry_t)) #define PME_AMD64_K8_CPU_CLK_UNHALTED 40 #define PME_AMD64_K8_RETIRED_INSTRUCTIONS 41 papi-5.5.1/src/libpfm-3.y/lib/pfmlib_pentium4.c0000644000307100002310000005372713013651450021150 0ustar yarkhangraduate/* * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. * Copyright (c) 2006 IBM Corp. * Contributed by Kevin Corry * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * pfmlib_pentium4.c * * Support for libpfm for the Pentium4/Xeon/EM64T processor family (family=15). */ #ifndef _GNU_SOURCE #define _GNU_SOURCE /* for getline */ #endif #include #include #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_pentium4_priv.h" #include "pentium4_events.h" typedef struct { unsigned long addr; char *name; } p4_regmap_t; #define P4_REGMAP(a, n) { .addr = a, .name = n } static p4_regmap_t p4_pmc_regmap[]={ /* 0 */ P4_REGMAP(0x3b2, "BPU_ESCR0"), /* 1 */ P4_REGMAP(0x3ba, "IS_ESCR0"), /* 2 */ P4_REGMAP(0x3aa, "MOB_ESCR0"), /* 3 */ P4_REGMAP(0x3b6, "ITLB_ESCR0"), /* 4 */ P4_REGMAP(0x3ac, "PMH_ESCR0"), /* 5 */ P4_REGMAP(0x3c8, "IX_ESCR0"), /* 6 */ P4_REGMAP(0x3a2, "FSB_ESCR0"), /* 7 */ P4_REGMAP(0x3a0, "BSU_ESCR0"), /* 8 */ P4_REGMAP(0x3c0, "MS_ESCR0"), /* 9 */ P4_REGMAP(0x3c4, "TC_ESCR0"), /* 10 */ P4_REGMAP(0x3c2, "TBPU_ESCR0"), /* 11 */ P4_REGMAP(0x3a6, "FLAME_ESCR0"), /* 12 */ P4_REGMAP(0x3a4, "FIRM_ESCR0"), /* 13 */ P4_REGMAP(0x3ae, "SAAT_ESCR0"), /* 14 */ P4_REGMAP(0x3b0, "U2L_ESCR0"), /* 15 */ P4_REGMAP(0x3a8, "DAC_ESCR0"), /* 16 */ P4_REGMAP(0x3ba, "IQ_ESCR0"), /* 17 */ P4_REGMAP(0x3ca, "ALF_ESCR0"), /* 18 */ P4_REGMAP(0x3bc, "RAT_ESCR0"), /* 19 */ P4_REGMAP(0x3be, "SSU_ESCR0"), /* 20 */ P4_REGMAP(0x3b8, "CRU_ESCR0"), /* 21 */ P4_REGMAP(0x3cc, "CRU_ESCR2"), /* 22 */ P4_REGMAP(0x3e0, "CRU_ESCR4"), /* 23 */ P4_REGMAP(0x360, "BPU_CCCR0"), /* 24 */ P4_REGMAP(0x361, "BPU_CCCR1"), /* 25 */ P4_REGMAP(0x364, "MS_CCCR0"), /* 26 */ P4_REGMAP(0x365, "MS_CCCR1"), /* 27 */ P4_REGMAP(0x368, "FLAME_CCCR0"), /* 28 */ P4_REGMAP(0x369, "FLAME_CCCR1"), /* 29 */ P4_REGMAP(0x36c, "IQ_CCCR0"), /* 30 */ P4_REGMAP(0x36d, "IQ_CCCR1"), /* 31 */ P4_REGMAP(0x370, "IQ_CCCR4"), /* 32 */ P4_REGMAP(0x3b3, "BPU_ESCR1"), /* 33 */ P4_REGMAP(0x3b5, "IS_ESCR1"), /* 34 */ P4_REGMAP(0x3ab, "MOB_ESCR1"), /* 35 */ P4_REGMAP(0x3b7, "ITLB_ESCR1"), /* 36 */ P4_REGMAP(0x3ad, "PMH_ESCR1"), /* 37 */ P4_REGMAP(0x3c9, "IX_ESCR1"), /* 38 */ P4_REGMAP(0x3a3, "FSB_ESCR1"), /* 39 */ P4_REGMAP(0x3a1, "BSU_ESCR1"), /* 40 */ P4_REGMAP(0x3c1, "MS_ESCR1"), /* 41 */ P4_REGMAP(0x3c5, "TC_ESCR1"), /* 42 */ P4_REGMAP(0x3c3, "TBPU_ESCR1"), /* 43 */ P4_REGMAP(0x3a7, "FLAME_ESCR1"), /* 44 */ P4_REGMAP(0x3a5, "FIRM_ESCR1"), /* 45 */ P4_REGMAP(0x3af, "SAAT_ESCR1"), /* 46 */ P4_REGMAP(0x3b1, "U2L_ESCR1"), /* 47 */ P4_REGMAP(0x3a9, "DAC_ESCR1"), /* 48 */ P4_REGMAP(0x3bb, "IQ_ESCR1"), /* 49 */ P4_REGMAP(0x3cb, "ALF_ESCR1"), /* 50 */ P4_REGMAP(0x3bd, "RAT_ESCR1"), /* 51 */ P4_REGMAP(0x3b9, "CRU_ESCR1"), /* 52 */ P4_REGMAP(0x3cd, "CRU_ESCR3"), /* 53 */ P4_REGMAP(0x3e1, "CRU_ESCR5"), /* 54 */ P4_REGMAP(0x362, "BPU_CCCR2"), /* 55 */ P4_REGMAP(0x363, "BPU_CCCR3"), /* 56 */ P4_REGMAP(0x366, "MS_CCCR2"), /* 57 */ P4_REGMAP(0x367, "MS_CCCR3"), /* 58 */ P4_REGMAP(0x36a, "FLAME_CCCR2"), /* 59 */ P4_REGMAP(0x36b, "FLAME_CCCR3"), /* 60 */ P4_REGMAP(0x36e, "IQ_CCCR2"), /* 61 */ P4_REGMAP(0x36f, "IQ_CCCR3"), /* 62 */ P4_REGMAP(0x371, "IQ_CCCR5"), /* 63 */ P4_REGMAP(0x3f2, "PEBS_MATRIX_VERT"), /* 64 */ P4_REGMAP(0x3f1, "PEBS_ENABLE"), }; #define PMC_PEBS_MATRIX_VERT 63 #define PMC_PEBS_ENABLE 64 static p4_regmap_t p4_pmd_regmap[]={ /* 0 */ P4_REGMAP(0x300, "BPU_CTR0"), /* 1 */ P4_REGMAP(0x301, "BPU_CTR1"), /* 2 */ P4_REGMAP(0x304, "MS_CTR0"), /* 3 */ P4_REGMAP(0x305, "MS_CTR1"), /* 4 */ P4_REGMAP(0x308, "FLAME_CTR0"), /* 5 */ P4_REGMAP(0x309, "FLAME_CTR1"), /* 6 */ P4_REGMAP(0x30c, "IQ_CTR0"), /* 7 */ P4_REGMAP(0x30d, "IQ_CTR1"), /* 8 */ P4_REGMAP(0x310, "IQ_CTR4"), /* 9 */ P4_REGMAP(0x302, "BPU_CTR2"), /* 10 */ P4_REGMAP(0x303, "BPU_CTR3"), /* 11 */ P4_REGMAP(0x306, "MS_CTR2"), /* 12 */ P4_REGMAP(0x307, "MS_CTR3"), /* 13 */ P4_REGMAP(0x30a, "FLAME_CTR2"), /* 14 */ P4_REGMAP(0x30b, "FLAME_CTR3"), /* 15 */ P4_REGMAP(0x30d, "IQ_CTR2"), /* 16 */ P4_REGMAP(0x30f, "IQ_CTR3"), /* 17 */ P4_REGMAP(0x311, "IQ_CTR5"), }; /* This array provides values for the PEBS_ENABLE and PEBS_MATRIX_VERT registers to support a series of metric for replay_event. The first two entries are dummies; the remaining 9 correspond to virtual bit masks in the replay_event definition and map onto Intel documentation. */ #define P4_REPLAY_REAL_MASK 0x00000003 #define P4_REPLAY_VIRT_MASK 0x00000FFC static pentium4_replay_regs_t p4_replay_regs[]={ /* 0 */ {.enb = 0, /* dummy */ .mat_vert = 0, }, /* 1 */ {.enb = 0, /* dummy */ .mat_vert = 0, }, /* 2 */ {.enb = 0x01000001, /* 1stL_cache_load_miss_retired */ .mat_vert = 0x00000001, }, /* 3 */ {.enb = 0x01000002, /* 2ndL_cache_load_miss_retired */ .mat_vert = 0x00000001, }, /* 4 */ {.enb = 0x01000004, /* DTLB_load_miss_retired */ .mat_vert = 0x00000001, }, /* 5 */ {.enb = 0x01000004, /* DTLB_store_miss_retired */ .mat_vert = 0x00000002, }, /* 6 */ {.enb = 0x01000004, /* DTLB_all_miss_retired */ .mat_vert = 0x00000003, }, /* 7 */ {.enb = 0x01018001, /* Tagged_mispred_branch */ .mat_vert = 0x00000010, }, /* 8 */ {.enb = 0x01000200, /* MOB_load_replay_retired */ .mat_vert = 0x00000001, }, /* 9 */ {.enb = 0x01000400, /* split_load_retired */ .mat_vert = 0x00000001, }, /* 10 */ {.enb = 0x01000400, /* split_store_retired */ .mat_vert = 0x00000002, }, }; static int p4_model; /** * pentium4_get_event_code * * Return the event-select value for the specified event as * needed for the specified PMD counter. **/ static int pentium4_get_event_code(unsigned int event, unsigned int pmd, int *code) { int i, j, escr, cccr; int rc = PFMLIB_ERR_INVAL; if (pmd >= PENTIUM4_NUM_PMDS && pmd != PFMLIB_CNT_FIRST) { goto out; } /* Check that the specified event is allowed for the specified PMD. * Each event has a specific set of ESCRs it can use, which implies * a specific set of CCCRs (and thus PMDs). A specified PMD of -1 * means assume any allowable PMD. */ if (pmd == PFMLIB_CNT_FIRST) { *code = pentium4_events[event].event_select; rc = PFMLIB_SUCCESS; goto out; } for (i = 0; i < MAX_ESCRS_PER_EVENT; i++) { escr = pentium4_events[event].allowed_escrs[i]; if (escr < 0) { continue; } for (j = 0; j < MAX_CCCRS_PER_ESCR; j++) { cccr = pentium4_escrs[escr].allowed_cccrs[j]; if (cccr < 0) { continue; } if (pmd == pentium4_cccrs[cccr].pmd) { *code = pentium4_events[event].event_select; rc = PFMLIB_SUCCESS; goto out; } } } out: return rc; } /** * pentium4_get_event_name * * Return the name of the specified event. **/ static char *pentium4_get_event_name(unsigned int event) { return pentium4_events[event].name; } /** * pentium4_get_event_mask_name * * Return the name of the specified event-mask. **/ static char *pentium4_get_event_mask_name(unsigned int event, unsigned int mask) { if (mask >= EVENT_MASK_BITS || pentium4_events[event].event_masks[mask].name == NULL) return NULL; return pentium4_events[event].event_masks[mask].name; } /** * pentium4_get_event_counters * * Fill in the 'counters' bitmask with all possible PMDs that could be * used to count the specified event. **/ static void pentium4_get_event_counters(unsigned int event, pfmlib_regmask_t *counters) { int i, j, escr, cccr; memset(counters, 0, sizeof(*counters)); for (i = 0; i < MAX_ESCRS_PER_EVENT; i++) { escr = pentium4_events[event].allowed_escrs[i]; if (escr < 0) { continue; } for (j = 0; j < MAX_CCCRS_PER_ESCR; j++) { cccr = pentium4_escrs[escr].allowed_cccrs[j]; if (cccr < 0) { continue; } pfm_regmask_set(counters, pentium4_cccrs[cccr].pmd); } } } /** * pentium4_get_num_event_masks * * Count the number of available event-masks for the specified event. All * valid masks in pentium4_events[].event_masks are contiguous in the array * and have a non-NULL name. **/ static unsigned int pentium4_get_num_event_masks(unsigned int event) { unsigned int i = 0; while (pentium4_events[event].event_masks[i].name) { i++; } return i; } /** * pentium4_dispatch_events * * Examine each desired event specified in "input" and find an appropriate * ESCR/CCCR pair that can be used to count them. **/ static int pentium4_dispatch_events(pfmlib_input_param_t *input, void *model_input, pfmlib_output_param_t *output, void *model_output) { unsigned int assigned_pmcs[PENTIUM4_NUM_PMCS] = {0}; unsigned int event, event_mask, mask; unsigned int bit, tag_value, tag_enable; unsigned int plm; unsigned int i, j, k, m, n; int escr, escr_pmc; int cccr, cccr_pmc, cccr_pmd; int assigned; pentium4_escr_value_t escr_value; pentium4_cccr_value_t cccr_value; if (input->pfp_event_count > PENTIUM4_NUM_PMDS) { /* Can't specify more events than we have counters. */ return PFMLIB_ERR_TOOMANY; } if (input->pfp_dfl_plm & (PFM_PLM1|PFM_PLM2)) { /* Can't specify privilege levels 1 or 2. */ return PFMLIB_ERR_INVAL; } /* Examine each event specified in input->pfp_events. i counts * through the input->pfp_events array, and j counts through the * PMCs in output->pfp_pmcs as they are set up. */ for (i = 0, j = 0; i < input->pfp_event_count; i++) { if (input->pfp_events[i].plm & (PFM_PLM1|PFM_PLM2)) { /* Can't specify privilege levels 1 or 2. */ return PFMLIB_ERR_INVAL; } /* * INSTR_COMPLETED event only exist for model 3, 4, 6 (Prescott) */ if (input->pfp_events[i].event == PME_INSTR_COMPLETED && p4_model != 3 && p4_model != 4 && p4_model != 6) return PFMLIB_ERR_EVTINCOMP; event = input->pfp_events[i].event; assigned = 0; /* Use the event-specific privilege mask if set. * Otherwise use the default privilege mask. */ plm = input->pfp_events[i].plm ? input->pfp_events[i].plm : input->pfp_dfl_plm; /* Examine each ESCR that this event could be assigned to. */ for (k = 0; k < MAX_ESCRS_PER_EVENT && !assigned; k++) { escr = pentium4_events[event].allowed_escrs[k]; if (escr < 0) continue; /* Make sure this ESCR isn't already assigned * and isn't on the "unavailable" list. */ escr_pmc = pentium4_escrs[escr].pmc; if (assigned_pmcs[escr_pmc] || pfm_regmask_isset(&input->pfp_unavail_pmcs, escr_pmc)) { continue; } /* Examine each CCCR that can be used with this ESCR. */ for (m = 0; m < MAX_CCCRS_PER_ESCR && !assigned; m++) { cccr = pentium4_escrs[escr].allowed_cccrs[m]; if (cccr < 0) { continue; } /* Make sure this CCCR isn't already assigned * and isn't on the "unavailable" list. */ cccr_pmc = pentium4_cccrs[cccr].pmc; cccr_pmd = pentium4_cccrs[cccr].pmd; if (assigned_pmcs[cccr_pmc] || pfm_regmask_isset(&input->pfp_unavail_pmcs, cccr_pmc)) { continue; } /* Found an available ESCR/CCCR pair. */ assigned = 1; assigned_pmcs[escr_pmc] = 1; assigned_pmcs[cccr_pmc] = 1; /* Calculate the event-mask value. Invalid masks * specified by the caller are ignored. */ event_mask = 0; tag_value = 0; tag_enable = 0; for (n = 0; n < input->pfp_events[i].num_masks; n++) { mask = input->pfp_events[i].unit_masks[n]; bit = pentium4_events[event].event_masks[mask].bit; if (bit < EVENT_MASK_BITS && pentium4_events[event].event_masks[mask].name) { event_mask |= (1 << bit); } if (bit >= EVENT_MASK_BITS && pentium4_events[event].event_masks[mask].name) { tag_value |= (1 << (bit - EVENT_MASK_BITS)); tag_enable = 1; } } /* Set up the ESCR and CCCR register values. */ escr_value.val = 0; escr_value.bits.t1_usr = 0; /* controlled by kernel */ escr_value.bits.t1_os = 0; /* controlled by kernel */ escr_value.bits.t0_usr = (plm & PFM_PLM3) ? 1 : 0; escr_value.bits.t0_os = (plm & PFM_PLM0) ? 1 : 0; escr_value.bits.tag_enable = tag_enable; escr_value.bits.tag_value = tag_value; escr_value.bits.event_mask = event_mask; escr_value.bits.event_select = pentium4_events[event].event_select; escr_value.bits.reserved = 0; cccr_value.val = 0; cccr_value.bits.reserved1 = 0; cccr_value.bits.enable = 1; cccr_value.bits.escr_select = pentium4_events[event].escr_select; cccr_value.bits.active_thread = 3; /* FIXME: This is set to count when either logical * CPU is active. Need a way to distinguish * between logical CPUs when HT is enabled. */ cccr_value.bits.compare = 0; /* FIXME: What do we do with "threshold" settings? */ cccr_value.bits.complement = 0; /* FIXME: What do we do with "threshold" settings? */ cccr_value.bits.threshold = 0; /* FIXME: What do we do with "threshold" settings? */ cccr_value.bits.force_ovf = 0; /* FIXME: Do we want to allow "forcing" overflow * interrupts on all counter increments? */ cccr_value.bits.ovf_pmi_t0 = 1; cccr_value.bits.ovf_pmi_t1 = 0; /* PMI taken care of by kernel typically */ cccr_value.bits.reserved2 = 0; cccr_value.bits.cascade = 0; /* FIXME: How do we handle "cascading" counters? */ cccr_value.bits.overflow = 0; /* Special processing for the replay event: Remove virtual mask bits from actual mask; scan mask bit list and OR bit values for each virtual mask into the PEBS ENABLE and PEBS MATRIX VERT registers */ if (event == PME_REPLAY_EVENT) { escr_value.bits.event_mask &= P4_REPLAY_REAL_MASK; /* remove virtual mask bits */ if (event_mask & P4_REPLAY_VIRT_MASK) { /* find a valid virtual mask */ output->pfp_pmcs[j].reg_value = 0; output->pfp_pmcs[j].reg_num = PMC_PEBS_ENABLE; output->pfp_pmcs[j].reg_addr = p4_pmc_regmap[PMC_PEBS_ENABLE].addr; output->pfp_pmcs[j+1].reg_value = 0; output->pfp_pmcs[j+1].reg_num = PMC_PEBS_MATRIX_VERT; output->pfp_pmcs[j+1].reg_addr = p4_pmc_regmap[PMC_PEBS_MATRIX_VERT].addr; for (n = 0; n < input->pfp_events[i].num_masks; n++) { mask = input->pfp_events[i].unit_masks[n]; if (mask > 1 && mask < 11) { /* process each valid mask we find */ output->pfp_pmcs[j].reg_value |= p4_replay_regs[mask].enb; output->pfp_pmcs[j+1].reg_value |= p4_replay_regs[mask].mat_vert; } } j += 2; output->pfp_pmc_count += 2; } } /* Set up the PMCs in the * output->pfp_pmcs array. */ output->pfp_pmcs[j].reg_num = escr_pmc; output->pfp_pmcs[j].reg_value = escr_value.val; output->pfp_pmcs[j].reg_addr = p4_pmc_regmap[escr_pmc].addr; j++; __pfm_vbprintf("[%s(pmc%u)=0x%lx os=%u usr=%u tag=%u tagval=0x%x mask=%u sel=0x%x] %s\n", p4_pmc_regmap[escr_pmc].name, escr_pmc, escr_value.val, escr_value.bits.t0_os, escr_value.bits.t0_usr, escr_value.bits.tag_enable, escr_value.bits.tag_value, escr_value.bits.event_mask, escr_value.bits.event_select, pentium4_events[event].name); output->pfp_pmcs[j].reg_num = cccr_pmc; output->pfp_pmcs[j].reg_value = cccr_value.val; output->pfp_pmcs[j].reg_addr = p4_pmc_regmap[cccr_pmc].addr; output->pfp_pmds[i].reg_num = cccr_pmd; output->pfp_pmds[i].reg_addr = p4_pmd_regmap[cccr_pmd].addr; __pfm_vbprintf("[%s(pmc%u)=0x%lx ena=1 sel=0x%x cmp=%u cmpl=%u thres=%u edg=%u cas=%u] %s\n", p4_pmc_regmap[cccr_pmc].name, cccr_pmc, cccr_value.val, cccr_value.bits.escr_select, cccr_value.bits.compare, cccr_value.bits.complement, cccr_value.bits.threshold, cccr_value.bits.edge, cccr_value.bits.cascade, pentium4_events[event].name); __pfm_vbprintf("[%s(pmd%u)]\n", p4_pmd_regmap[output->pfp_pmds[i].reg_num].name, output->pfp_pmds[i].reg_num); j++; output->pfp_pmc_count += 2; } } if (k == MAX_ESCRS_PER_EVENT && !assigned) { /* Couldn't find an available ESCR and/or CCCR. */ return PFMLIB_ERR_NOASSIGN; } } output->pfp_pmd_count = input->pfp_event_count; return PFMLIB_SUCCESS; } /** * pentium4_pmu_detect * * Determine whether the system we're running on is a Pentium4 * (or other CPU that uses the same PMU). **/ static int pentium4_pmu_detect(void) { int ret, family; char buffer[128]; ret = __pfm_getcpuinfo_attr("vendor_id", buffer, sizeof(buffer)); if (ret == -1) return PFMLIB_ERR_NOTSUPP; if (strcmp(buffer, "GenuineIntel")) return PFMLIB_ERR_NOTSUPP; ret = __pfm_getcpuinfo_attr("cpu family", buffer, sizeof(buffer)); if (ret == -1) return PFMLIB_ERR_NOTSUPP; family = atoi(buffer); ret = __pfm_getcpuinfo_attr("model", buffer, sizeof(buffer)); if (ret == -1) return PFMLIB_ERR_NOTSUPP; /* * we use model to detect model 2 which has one more counter IQ_ESCR1 */ p4_model = atoi(buffer); if (family != 15) return PFMLIB_ERR_NOTSUPP; /* * IQ_ESCR0, IQ_ESCR1 only for model 1 and 2 */ if (p4_model >2) pentium4_support.pmc_count -= 2; return family == 15 ? PFMLIB_SUCCESS : PFMLIB_ERR_NOTSUPP; } /** * pentium4_get_impl_pmcs * * Set the appropriate bit in the impl_pmcs bitmask for each PMC that's * available on Pentium4. * * FIXME: How can we detect when HyperThreading is enabled? **/ static void pentium4_get_impl_pmcs(pfmlib_regmask_t *impl_pmcs) { unsigned int i; for(i = 0; i < PENTIUM4_NUM_PMCS; i++) { pfm_regmask_set(impl_pmcs, i); } /* * IQ_ESCR0, IQ_ESCR1 only available on model 1 and 2 */ if (p4_model > 2) { pfm_regmask_clr(impl_pmcs, 16); pfm_regmask_clr(impl_pmcs, 48); } } /** * pentium4_get_impl_pmds * * Set the appropriate bit in the impl_pmcs bitmask for each PMD that's * available on Pentium4. * * FIXME: How can we detect when HyperThreading is enabled? **/ static void pentium4_get_impl_pmds(pfmlib_regmask_t *impl_pmds) { unsigned int i; for(i = 0; i < PENTIUM4_NUM_PMDS; i++) { pfm_regmask_set(impl_pmds, i); } } /** * pentium4_get_impl_counters * * Set the appropriate bit in the impl_counters bitmask for each counter * that's available on Pentium4. * * For now, all PMDs are counters, so just call get_impl_pmds(). **/ static void pentium4_get_impl_counters(pfmlib_regmask_t *impl_counters) { pentium4_get_impl_pmds(impl_counters); } /** * pentium4_get_hw_counter_width * * Return the number of usable bits in the PMD counters. **/ static void pentium4_get_hw_counter_width(unsigned int *width) { *width = PENTIUM4_COUNTER_WIDTH; } /** * pentium4_get_event_desc * * Return the description for the specified event (if it has one). * * FIXME: In this routine, we make a copy of the description string to * return. But in get_event_name(), we just return the string * directly. Why the difference? **/ static int pentium4_get_event_desc(unsigned int event, char **desc) { if (pentium4_events[event].desc) { *desc = strdup(pentium4_events[event].desc); } else { *desc = NULL; } return PFMLIB_SUCCESS; } /** * pentium4_get_event_mask_desc * * Return the description for the specified event-mask (if it has one). **/ static int pentium4_get_event_mask_desc(unsigned int event, unsigned int mask, char **desc) { if (mask >= EVENT_MASK_BITS || pentium4_events[event].event_masks[mask].desc == NULL) return PFMLIB_ERR_INVAL; *desc = strdup(pentium4_events[event].event_masks[mask].desc); return PFMLIB_SUCCESS; } static int pentium4_get_event_mask_code(unsigned int event, unsigned int mask, unsigned int *code) { *code = 1U << pentium4_events[event].event_masks[mask].bit; return PFMLIB_SUCCESS; } static int pentium4_get_cycle_event(pfmlib_event_t *e) { e->event = PENTIUM4_CPU_CLK_UNHALTED; e->num_masks = 1; e->unit_masks[0] = 0; return PFMLIB_SUCCESS; } static int pentium4_get_inst_retired(pfmlib_event_t *e) { /* * some models do not implement INSTR_COMPLETED */ if (p4_model != 3 && p4_model != 4 && p4_model != 6) { e->event = PENTIUM4_INST_RETIRED; e->num_masks = 2; e->unit_masks[0] = 0; e->unit_masks[1] = 1; } else { e->event = PME_INSTR_COMPLETED; e->num_masks = 1; e->unit_masks[0] = 0; } return PFMLIB_SUCCESS; } /** * pentium4_support **/ pfm_pmu_support_t pentium4_support = { .pmu_name = "Pentium4/Xeon/EM64T", .pmu_type = PFMLIB_PENTIUM4_PMU, .pme_count = PENTIUM4_EVENT_COUNT, .pmd_count = PENTIUM4_NUM_PMDS, .pmc_count = PENTIUM4_NUM_PMCS, .num_cnt = PENTIUM4_NUM_PMDS, .get_event_code = pentium4_get_event_code, .get_event_name = pentium4_get_event_name, .get_event_mask_name = pentium4_get_event_mask_name, .get_event_counters = pentium4_get_event_counters, .get_num_event_masks = pentium4_get_num_event_masks, .dispatch_events = pentium4_dispatch_events, .pmu_detect = pentium4_pmu_detect, .get_impl_pmcs = pentium4_get_impl_pmcs, .get_impl_pmds = pentium4_get_impl_pmds, .get_impl_counters = pentium4_get_impl_counters, .get_hw_counter_width = pentium4_get_hw_counter_width, .get_event_desc = pentium4_get_event_desc, .get_event_mask_desc = pentium4_get_event_mask_desc, .get_event_mask_code = pentium4_get_event_mask_code, .get_cycle_event = pentium4_get_cycle_event, .get_inst_retired_event = pentium4_get_inst_retired }; papi-5.5.1/src/libpfm-3.y/lib/pfmlib_gen_ia64.c0000644000307100002310000003250613013651450020767 0ustar yarkhangraduate/* * pfmlib_gen_ia64.c : support default architected IA-64 PMU features * * Copyright (c) 2001-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include "pfmlib_priv.h" /* library private */ #include "pfmlib_priv_ia64.h" /* architecture private */ #define PMU_GEN_IA64_MAX_COUNTERS 4 /* * number of architected events */ #define PME_GEN_COUNT 2 /* * Description of the PMC register mappings use by * this module (as reported in pfmlib_reg_t.reg_num): * * 0 -> PMC0 * 1 -> PMC1 * n -> PMCn */ #define PFMLIB_GEN_IA64_PMC_BASE 0 /* * generic event as described by architecture */ typedef struct { unsigned long pme_code:8; /* major event code */ unsigned long pme_ig:56; /* ignored */ } pme_gen_ia64_code_t; /* * union of all possible entry codes. All encodings must fit in 64bit */ typedef union { unsigned long pme_vcode; pme_gen_ia64_code_t pme_gen_code; } pme_gen_ia64_entry_code_t; /* * entry in the event table (one table per implementation) */ typedef struct pme_entry { char *pme_name; pme_gen_ia64_entry_code_t pme_entry_code; /* event code */ pfmlib_regmask_t pme_counters; /* counter bitmask */ } pme_gen_ia64_entry_t; /* let's define some handy shortcuts ! */ #define pmc_plm pmc_gen_count_reg.pmc_plm #define pmc_ev pmc_gen_count_reg.pmc_ev #define pmc_oi pmc_gen_count_reg.pmc_oi #define pmc_pm pmc_gen_count_reg.pmc_pm #define pmc_es pmc_gen_count_reg.pmc_es /* * this table is patched by initialization code */ static pme_gen_ia64_entry_t generic_pe[PME_GEN_COUNT]={ #define PME_IA64_GEN_CPU_CYCLES 0 { "CPU_CYCLES", }, #define PME_IA64_GEN_INST_RETIRED 1 { "IA64_INST_RETIRED", }, }; static int pfm_gen_ia64_counter_width; static int pfm_gen_ia64_counters; static pfmlib_regmask_t pfm_gen_ia64_impl_pmcs; static pfmlib_regmask_t pfm_gen_ia64_impl_pmds; /* * Description of the PMC register mappings use by * this module (as reported in pfmlib_reg_t.reg_num): * * 0 -> PMC0 * 1 -> PMC1 * n -> PMCn * We do not use a mapping table, instead we make up the * values on the fly given the base. */ #define PFMLIB_GEN_IA64_PMC_BASE 0 /* * convert text range (e.g. 4-15 18 12-26) into actual bitmask * range argument is modified */ static int parse_counter_range(char *range, pfmlib_regmask_t *b) { char *p, c; int start, end; if (range[strlen(range)-1] == '\n') range[strlen(range)-1] = '\0'; while(range) { p = range; while (*p && *p != ' ' && *p != '-') p++; if (*p == '\0') break; c = *p; *p = '\0'; start = atoi(range); range = p+1; if (c == '-') { p++; while (*p && *p != ' ' && *p != '-') p++; if (*p) *p++ = '\0'; end = atoi(range); range = p; } else { end = start; } if (end >= PFMLIB_REG_MAX|| start >= PFMLIB_REG_MAX) goto invalid; for (; start <= end; start++) pfm_regmask_set(b, start); } return 0; invalid: fprintf(stderr, "%s.%s : bitmask too small need %d bits\n", __FILE__, __FUNCTION__, start); return -1; } static int pfm_gen_ia64_initialize(void) { FILE *fp; char *p; char buffer[64]; int matches = 0; fp = fopen("/proc/pal/cpu0/perfmon_info", "r"); if (fp == NULL) return PFMLIB_ERR_NOTSUPP; for (;;) { p = fgets(buffer, sizeof(buffer)-1, fp); if (p == NULL) break; if ((p = strchr(buffer, ':')) == NULL) break; *p = '\0'; if (!strncmp("Counter width", buffer, 13)) { pfm_gen_ia64_counter_width = atoi(p+2); matches++; continue; } if (!strncmp("PMC/PMD pairs", buffer, 13)) { pfm_gen_ia64_counters = atoi(p+2); matches++; continue; } if (!strncmp("Cycle event number", buffer, 18)) { generic_pe[0].pme_entry_code.pme_vcode = atoi(p+2); matches++; continue; } if (!strncmp("Retired event number", buffer, 20)) { generic_pe[1].pme_entry_code.pme_vcode = atoi(p+2); matches++; continue; } if (!strncmp("Cycles count capable", buffer, 20)) { if (parse_counter_range(p+2, &generic_pe[0].pme_counters) == -1) return -1; matches++; continue; } if (!strncmp("Retired bundles count capable", buffer, 29)) { if (parse_counter_range(p+2, &generic_pe[1].pme_counters) == -1) return -1; matches++; continue; } if (!strncmp("Implemented PMC", buffer, 15)) { if (parse_counter_range(p+2, &pfm_gen_ia64_impl_pmcs) == -1) return -1; matches++; continue; } if (!strncmp("Implemented PMD", buffer, 15)) { if (parse_counter_range(p+2, &pfm_gen_ia64_impl_pmds) == -1) return -1; matches++; continue; } } pfm_regmask_weight(&pfm_gen_ia64_impl_pmcs, &generic_ia64_support.pmc_count); pfm_regmask_weight(&pfm_gen_ia64_impl_pmds, &generic_ia64_support.pmd_count); fclose(fp); return matches == 8 ? PFMLIB_SUCCESS : PFMLIB_ERR_NOTSUPP; } static void pfm_gen_ia64_forced_initialize(void) { unsigned int i; pfm_gen_ia64_counter_width = 47; pfm_gen_ia64_counters = 4; generic_pe[0].pme_entry_code.pme_vcode = 18; generic_pe[1].pme_entry_code.pme_vcode = 8; memset(&pfm_gen_ia64_impl_pmcs, 0, sizeof(pfmlib_regmask_t)); memset(&pfm_gen_ia64_impl_pmds, 0, sizeof(pfmlib_regmask_t)); for(i=0; i < 8; i++) pfm_regmask_set(&pfm_gen_ia64_impl_pmcs, i); for(i=4; i < 8; i++) pfm_regmask_set(&pfm_gen_ia64_impl_pmds, i); memset(&generic_pe[0].pme_counters, 0, sizeof(pfmlib_regmask_t)); memset(&generic_pe[1].pme_counters, 0, sizeof(pfmlib_regmask_t)); for(i=4; i < 8; i++) { pfm_regmask_set(&generic_pe[0].pme_counters, i); pfm_regmask_set(&generic_pe[1].pme_counters, i); } generic_ia64_support.pmc_count = 8; generic_ia64_support.pmd_count = 4; generic_ia64_support.num_cnt = 4; } static int pfm_gen_ia64_detect(void) { /* PMU is architected, so guaranteed to be present */ return PFMLIB_SUCCESS; } static int pfm_gen_ia64_init(void) { if (forced_pmu != PFMLIB_NO_PMU) { pfm_gen_ia64_forced_initialize(); } else if (pfm_gen_ia64_initialize() == -1) return PFMLIB_ERR_NOTSUPP; return PFMLIB_SUCCESS; } static int valid_assign(unsigned int *as, pfmlib_regmask_t *r_pmcs, unsigned int cnt) { unsigned int i; for(i=0; i < cnt; i++) { if (as[i]==0) return 0; /* * take care of restricted PMC registers */ if (pfm_regmask_isset(r_pmcs, as[i])) return 0; } return 1; } /* * Automatically dispatch events to corresponding counters following constraints. * Upon return the pfarg_reg_t structure is ready to be submitted to kernel */ static int pfm_gen_ia64_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_output_param_t *outp) { #define has_counter(e,b) (pfm_regmask_isset(&generic_pe[e].pme_counters, b) ? b : 0) unsigned int max_l0, max_l1, max_l2, max_l3; unsigned int assign[PMU_GEN_IA64_MAX_COUNTERS]; pfm_gen_ia64_pmc_reg_t reg; pfmlib_event_t *e; pfmlib_reg_t *pc, *pd; pfmlib_regmask_t *r_pmcs; unsigned int i,j,k,l; unsigned int cnt; e = inp->pfp_events; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; cnt = inp->pfp_event_count; r_pmcs = &inp->pfp_unavail_pmcs; if (cnt > PMU_GEN_IA64_MAX_COUNTERS) return PFMLIB_ERR_TOOMANY; max_l0 = PMU_GEN_IA64_FIRST_COUNTER + PMU_GEN_IA64_MAX_COUNTERS; max_l1 = PMU_GEN_IA64_FIRST_COUNTER + PMU_GEN_IA64_MAX_COUNTERS*(cnt>1); max_l2 = PMU_GEN_IA64_FIRST_COUNTER + PMU_GEN_IA64_MAX_COUNTERS*(cnt>2); max_l3 = PMU_GEN_IA64_FIRST_COUNTER + PMU_GEN_IA64_MAX_COUNTERS*(cnt>3); if (PFMLIB_DEBUG()) { DPRINT("max_l0=%u max_l1=%u max_l2=%u max_l3=%u\n", max_l0, max_l1, max_l2, max_l3); } /* * This code needs fixing. It is not very pretty and * won't handle more than 4 counters if more become * available ! * For now, worst case in the loop nest: 4! (factorial) */ for (i=PMU_GEN_IA64_FIRST_COUNTER; i < max_l0; i++) { assign[0]= has_counter(e[0].event,i); if (max_l1 == PMU_GEN_IA64_FIRST_COUNTER && valid_assign(assign, r_pmcs, cnt)) goto done; for (j=PMU_GEN_IA64_FIRST_COUNTER; j < max_l1; j++) { if (j == i) continue; assign[1] = has_counter(e[1].event,j); if (max_l2 == PMU_GEN_IA64_FIRST_COUNTER && valid_assign(assign, r_pmcs, cnt)) goto done; for (k=PMU_GEN_IA64_FIRST_COUNTER; k < max_l2; k++) { if(k == i || k == j) continue; assign[2] = has_counter(e[2].event,k); if (max_l3 == PMU_GEN_IA64_FIRST_COUNTER && valid_assign(assign, r_pmcs, cnt)) goto done; for (l=PMU_GEN_IA64_FIRST_COUNTER; l < max_l3; l++) { if(l == i || l == j || l == k) continue; assign[3] = has_counter(e[3].event,l); if (valid_assign(assign, r_pmcs, cnt)) goto done; } } } } /* we cannot satisfy the constraints */ return PFMLIB_ERR_NOASSIGN; done: memset(pc, 0, cnt*sizeof(pfmlib_reg_t)); memset(pd, 0, cnt*sizeof(pfmlib_reg_t)); for (j=0; j < cnt ; j++ ) { reg.pmc_val = 0; /* clear all */ /* if not specified per event, then use default (could be zero: measure nothing) */ reg.pmc_plm = e[j].plm ? e[j].plm: inp->pfp_dfl_plm; reg.pmc_oi = 1; /* overflow interrupt */ reg.pmc_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE? 1 : 0; reg.pmc_es = generic_pe[e[j].event].pme_entry_code.pme_gen_code.pme_code; pc[j].reg_num = assign[j]; pc[j].reg_value = reg.pmc_val; pc[j].reg_addr = PFMLIB_GEN_IA64_PMC_BASE+j; pd[j].reg_num = assign[j]; pd[j].reg_addr = assign[j]; __pfm_vbprintf("[PMC%u(pmc%u)=0x%lx,es=0x%02x,plm=%d pm=%d] %s\n", assign[j], assign[j], reg.pmc_val, reg.pmc_es,reg.pmc_plm, reg.pmc_pm, generic_pe[e[j].event].pme_name); __pfm_vbprintf("[PMD%u(pmd%u)]\n", pd[j].reg_num, pd[j].reg_num); } /* number of PMC programmed */ outp->pfp_pmc_count = cnt; outp->pfp_pmd_count = cnt; return PFMLIB_SUCCESS; } static int pfm_gen_ia64_dispatch_events(pfmlib_input_param_t *inp, void *dummy1, pfmlib_output_param_t *outp, void *dummy2) { return pfm_gen_ia64_dispatch_counters(inp, outp); } static int pfm_gen_ia64_get_event_code(unsigned int i, unsigned int cnt, int *code) { if (cnt != PFMLIB_CNT_FIRST && (cnt < 4 || cnt > 7)) return PFMLIB_ERR_INVAL; *code = (int)generic_pe[i].pme_entry_code.pme_gen_code.pme_code; return PFMLIB_SUCCESS; } static char * pfm_gen_ia64_get_event_name(unsigned int i) { return generic_pe[i].pme_name; } static void pfm_gen_ia64_get_event_counters(unsigned int j, pfmlib_regmask_t *counters) { unsigned int i; memset(counters, 0, sizeof(*counters)); for(i=0; i < pfm_gen_ia64_counters; i++) { if (pfm_regmask_isset(&generic_pe[j].pme_counters, i)) pfm_regmask_set(counters, i); } } static void pfm_gen_ia64_get_impl_pmcs(pfmlib_regmask_t *impl_pmcs) { *impl_pmcs = pfm_gen_ia64_impl_pmcs; } static void pfm_gen_ia64_get_impl_pmds(pfmlib_regmask_t *impl_pmds) { *impl_pmds = pfm_gen_ia64_impl_pmds; } static void pfm_gen_ia64_get_impl_counters(pfmlib_regmask_t *impl_counters) { unsigned int i = 0; /* pmd4-pmd7 */ for(i=4; i < 8; i++) pfm_regmask_set(impl_counters, i); } static void pfm_gen_ia64_get_hw_counter_width(unsigned int *width) { *width = pfm_gen_ia64_counter_width; } static int pfm_gen_ia64_get_event_desc(unsigned int ev, char **str) { switch(ev) { case PME_IA64_GEN_CPU_CYCLES: *str = strdup("CPU cycles"); break; case PME_IA64_GEN_INST_RETIRED: *str = strdup("IA-64 instructions retired"); break; default: *str = NULL; } return PFMLIB_SUCCESS; } static int pfm_gen_ia64_get_cycle_event(pfmlib_event_t *e) { e->event = PME_IA64_GEN_CPU_CYCLES; return PFMLIB_SUCCESS; } static int pfm_gen_ia64_get_inst_retired(pfmlib_event_t *e) { e->event = PME_IA64_GEN_INST_RETIRED; return PFMLIB_SUCCESS; } pfm_pmu_support_t generic_ia64_support={ .pmu_name ="IA-64", .pmu_type = PFMLIB_GEN_IA64_PMU, .pme_count = PME_GEN_COUNT, .pmc_count = 4+4, .pmd_count = PMU_GEN_IA64_MAX_COUNTERS, .num_cnt = PMU_GEN_IA64_MAX_COUNTERS, .get_event_code = pfm_gen_ia64_get_event_code, .get_event_name = pfm_gen_ia64_get_event_name, .get_event_counters = pfm_gen_ia64_get_event_counters, .dispatch_events = pfm_gen_ia64_dispatch_events, .pmu_detect = pfm_gen_ia64_detect, .pmu_init = pfm_gen_ia64_init, .get_impl_pmcs = pfm_gen_ia64_get_impl_pmcs, .get_impl_pmds = pfm_gen_ia64_get_impl_pmds, .get_impl_counters = pfm_gen_ia64_get_impl_counters, .get_hw_counter_width = pfm_gen_ia64_get_hw_counter_width, .get_event_desc = pfm_gen_ia64_get_event_desc, .get_cycle_event = pfm_gen_ia64_get_cycle_event, .get_inst_retired_event = pfm_gen_ia64_get_inst_retired }; papi-5.5.1/src/libpfm-3.y/lib/power5_events.h0000644000307100002310000132330013013651450020650 0ustar yarkhangraduate/****************************/ /* THIS IS OPEN SOURCE CODE */ /****************************/ #ifndef __POWER5_EVENTS_H__ #define __POWER5_EVENTS_H__ /* * File: power5_events.h * CVS: * Author: Corey Ashford * cjashfor@us.ibm.com * Mods: * * * (C) Copyright IBM Corporation, 2007. All Rights Reserved. * Contributed by Corey Ashford * * Note: This code was automatically generated and should not be modified by * hand. * */ #define POWER5_PME_PM_LSU_REJECT_RELOAD_CDF 0 #define POWER5_PME_PM_FPU1_SINGLE 1 #define POWER5_PME_PM_L3SB_REF 2 #define POWER5_PME_PM_THRD_PRIO_DIFF_3or4_CYC 3 #define POWER5_PME_PM_INST_FROM_L275_SHR 4 #define POWER5_PME_PM_MRK_DATA_FROM_L375_MOD 5 #define POWER5_PME_PM_DTLB_MISS_4K 6 #define POWER5_PME_PM_CLB_FULL_CYC 7 #define POWER5_PME_PM_MRK_ST_CMPL 8 #define POWER5_PME_PM_LSU_FLUSH_LRQ_FULL 9 #define POWER5_PME_PM_MRK_DATA_FROM_L275_SHR 10 #define POWER5_PME_PM_1INST_CLB_CYC 11 #define POWER5_PME_PM_MEM_SPEC_RD_CANCEL 12 #define POWER5_PME_PM_MRK_DTLB_MISS_16M 13 #define POWER5_PME_PM_FPU_FDIV 14 #define POWER5_PME_PM_FPU_SINGLE 15 #define POWER5_PME_PM_FPU0_FMA 16 #define POWER5_PME_PM_SLB_MISS 17 #define POWER5_PME_PM_LSU1_FLUSH_LRQ 18 #define POWER5_PME_PM_L2SA_ST_HIT 19 #define POWER5_PME_PM_DTLB_MISS 20 #define POWER5_PME_PM_BR_PRED_TA 21 #define POWER5_PME_PM_MRK_DATA_FROM_L375_MOD_CYC 22 #define POWER5_PME_PM_CMPLU_STALL_FXU 23 #define POWER5_PME_PM_EXT_INT 24 #define POWER5_PME_PM_MRK_LSU1_FLUSH_LRQ 25 #define POWER5_PME_PM_LSU1_LDF 26 #define POWER5_PME_PM_MRK_ST_GPS 27 #define POWER5_PME_PM_FAB_CMD_ISSUED 28 #define POWER5_PME_PM_LSU0_SRQ_STFWD 29 #define POWER5_PME_PM_CR_MAP_FULL_CYC 30 #define POWER5_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL 31 #define POWER5_PME_PM_MRK_LSU0_FLUSH_ULD 32 #define POWER5_PME_PM_LSU_FLUSH_SRQ_FULL 33 #define POWER5_PME_PM_FLUSH_IMBAL 34 #define POWER5_PME_PM_MEM_RQ_DISP_Q16to19 35 #define POWER5_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC 36 #define POWER5_PME_PM_DATA_FROM_L35_MOD 37 #define POWER5_PME_PM_MEM_HI_PRIO_WR_CMPL 38 #define POWER5_PME_PM_FPU1_FDIV 39 #define POWER5_PME_PM_FPU0_FRSP_FCONV 40 #define POWER5_PME_PM_MEM_RQ_DISP 41 #define POWER5_PME_PM_LWSYNC_HELD 42 #define POWER5_PME_PM_FXU_FIN 43 #define POWER5_PME_PM_DSLB_MISS 44 #define POWER5_PME_PM_FXLS1_FULL_CYC 45 #define POWER5_PME_PM_DATA_FROM_L275_SHR 46 #define POWER5_PME_PM_THRD_SEL_T0 47 #define POWER5_PME_PM_PTEG_RELOAD_VALID 48 #define POWER5_PME_PM_LSU_LMQ_LHR_MERGE 49 #define POWER5_PME_PM_MRK_STCX_FAIL 50 #define POWER5_PME_PM_2INST_CLB_CYC 51 #define POWER5_PME_PM_FAB_PNtoVN_DIRECT 52 #define POWER5_PME_PM_PTEG_FROM_L2MISS 53 #define POWER5_PME_PM_CMPLU_STALL_LSU 54 #define POWER5_PME_PM_MRK_DSLB_MISS 55 #define POWER5_PME_PM_LSU_FLUSH_ULD 56 #define POWER5_PME_PM_PTEG_FROM_LMEM 57 #define POWER5_PME_PM_MRK_BRU_FIN 58 #define POWER5_PME_PM_MEM_WQ_DISP_WRITE 59 #define POWER5_PME_PM_MRK_DATA_FROM_L275_MOD_CYC 60 #define POWER5_PME_PM_LSU1_NCLD 61 #define POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER 62 #define POWER5_PME_PM_SNOOP_PW_RETRY_WQ_PWQ 63 #define POWER5_PME_PM_FPR_MAP_FULL_CYC 64 #define POWER5_PME_PM_FPU1_FULL_CYC 65 #define POWER5_PME_PM_L3SA_ALL_BUSY 66 #define POWER5_PME_PM_3INST_CLB_CYC 67 #define POWER5_PME_PM_MEM_PWQ_DISP_Q2or3 68 #define POWER5_PME_PM_L2SA_SHR_INV 69 #define POWER5_PME_PM_THRESH_TIMEO 70 #define POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL 71 #define POWER5_PME_PM_THRD_SEL_OVER_GCT_IMBAL 72 #define POWER5_PME_PM_FPU_FSQRT 73 #define POWER5_PME_PM_MRK_LSU0_FLUSH_LRQ 74 #define POWER5_PME_PM_PMC1_OVERFLOW 75 #define POWER5_PME_PM_L3SC_SNOOP_RETRY 76 #define POWER5_PME_PM_DATA_TABLEWALK_CYC 77 #define POWER5_PME_PM_THRD_PRIO_6_CYC 78 #define POWER5_PME_PM_FPU_FEST 79 #define POWER5_PME_PM_FAB_M1toP1_SIDECAR_EMPTY 80 #define POWER5_PME_PM_MRK_DATA_FROM_RMEM 81 #define POWER5_PME_PM_MRK_DATA_FROM_L35_MOD_CYC 82 #define POWER5_PME_PM_MEM_PWQ_DISP 83 #define POWER5_PME_PM_FAB_P1toM1_SIDECAR_EMPTY 84 #define POWER5_PME_PM_LD_MISS_L1_LSU0 85 #define POWER5_PME_PM_SNOOP_PARTIAL_RTRY_QFULL 86 #define POWER5_PME_PM_FPU1_STALL3 87 #define POWER5_PME_PM_GCT_USAGE_80to99_CYC 88 #define POWER5_PME_PM_WORK_HELD 89 #define POWER5_PME_PM_INST_CMPL 90 #define POWER5_PME_PM_LSU1_FLUSH_UST 91 #define POWER5_PME_PM_FXU_IDLE 92 #define POWER5_PME_PM_LSU0_FLUSH_ULD 93 #define POWER5_PME_PM_LSU1_REJECT_LMQ_FULL 94 #define POWER5_PME_PM_GRP_DISP_REJECT 95 #define POWER5_PME_PM_L2SA_MOD_INV 96 #define POWER5_PME_PM_PTEG_FROM_L25_SHR 97 #define POWER5_PME_PM_FAB_CMD_RETRIED 98 #define POWER5_PME_PM_L3SA_SHR_INV 99 #define POWER5_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL 100 #define POWER5_PME_PM_L2SA_RCST_DISP_FAIL_ADDR 101 #define POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_RC_FULL 102 #define POWER5_PME_PM_PTEG_FROM_L375_MOD 103 #define POWER5_PME_PM_MRK_LSU1_FLUSH_UST 104 #define POWER5_PME_PM_BR_ISSUED 105 #define POWER5_PME_PM_MRK_GRP_BR_REDIR 106 #define POWER5_PME_PM_EE_OFF 107 #define POWER5_PME_PM_MEM_RQ_DISP_Q4to7 108 #define POWER5_PME_PM_MEM_FAST_PATH_RD_DISP 109 #define POWER5_PME_PM_INST_FROM_L3 110 #define POWER5_PME_PM_ITLB_MISS 111 #define POWER5_PME_PM_FXU1_BUSY_FXU0_IDLE 112 #define POWER5_PME_PM_FXLS_FULL_CYC 113 #define POWER5_PME_PM_DTLB_REF_4K 114 #define POWER5_PME_PM_GRP_DISP_VALID 115 #define POWER5_PME_PM_LSU_FLUSH_UST 116 #define POWER5_PME_PM_FXU1_FIN 117 #define POWER5_PME_PM_THRD_PRIO_4_CYC 118 #define POWER5_PME_PM_MRK_DATA_FROM_L35_MOD 119 #define POWER5_PME_PM_4INST_CLB_CYC 120 #define POWER5_PME_PM_MRK_DTLB_REF_16M 121 #define POWER5_PME_PM_INST_FROM_L375_MOD 122 #define POWER5_PME_PM_L2SC_RCST_DISP_FAIL_ADDR 123 #define POWER5_PME_PM_GRP_CMPL 124 #define POWER5_PME_PM_FPU1_1FLOP 125 #define POWER5_PME_PM_FPU_FRSP_FCONV 126 #define POWER5_PME_PM_5INST_CLB_CYC 127 #define POWER5_PME_PM_L3SC_REF 128 #define POWER5_PME_PM_THRD_L2MISS_BOTH_CYC 129 #define POWER5_PME_PM_MEM_PW_GATH 130 #define POWER5_PME_PM_FAB_PNtoNN_SIDECAR 131 #define POWER5_PME_PM_FAB_DCLAIM_ISSUED 132 #define POWER5_PME_PM_GRP_IC_MISS 133 #define POWER5_PME_PM_INST_FROM_L35_SHR 134 #define POWER5_PME_PM_LSU_LMQ_FULL_CYC 135 #define POWER5_PME_PM_MRK_DATA_FROM_L2_CYC 136 #define POWER5_PME_PM_LSU_SRQ_SYNC_CYC 137 #define POWER5_PME_PM_LSU0_BUSY_REJECT 138 #define POWER5_PME_PM_LSU_REJECT_ERAT_MISS 139 #define POWER5_PME_PM_MRK_DATA_FROM_RMEM_CYC 140 #define POWER5_PME_PM_DATA_FROM_L375_SHR 141 #define POWER5_PME_PM_FPU0_FMOV_FEST 142 #define POWER5_PME_PM_PTEG_FROM_L25_MOD 143 #define POWER5_PME_PM_LD_REF_L1_LSU0 144 #define POWER5_PME_PM_THRD_PRIO_7_CYC 145 #define POWER5_PME_PM_LSU1_FLUSH_SRQ 146 #define POWER5_PME_PM_L2SC_RCST_DISP 147 #define POWER5_PME_PM_CMPLU_STALL_DIV 148 #define POWER5_PME_PM_MEM_RQ_DISP_Q12to15 149 #define POWER5_PME_PM_INST_FROM_L375_SHR 150 #define POWER5_PME_PM_ST_REF_L1 151 #define POWER5_PME_PM_L3SB_ALL_BUSY 152 #define POWER5_PME_PM_FAB_P1toVNorNN_SIDECAR_EMPTY 153 #define POWER5_PME_PM_MRK_DATA_FROM_L275_SHR_CYC 154 #define POWER5_PME_PM_FAB_HOLDtoNN_EMPTY 155 #define POWER5_PME_PM_DATA_FROM_LMEM 156 #define POWER5_PME_PM_RUN_CYC 157 #define POWER5_PME_PM_PTEG_FROM_RMEM 158 #define POWER5_PME_PM_L2SC_RCLD_DISP 159 #define POWER5_PME_PM_LSU0_LDF 160 #define POWER5_PME_PM_LSU_LRQ_S0_VALID 161 #define POWER5_PME_PM_PMC3_OVERFLOW 162 #define POWER5_PME_PM_MRK_IMR_RELOAD 163 #define POWER5_PME_PM_MRK_GRP_TIMEO 164 #define POWER5_PME_PM_ST_MISS_L1 165 #define POWER5_PME_PM_STOP_COMPLETION 166 #define POWER5_PME_PM_LSU_BUSY_REJECT 167 #define POWER5_PME_PM_ISLB_MISS 168 #define POWER5_PME_PM_CYC 169 #define POWER5_PME_PM_THRD_ONE_RUN_CYC 170 #define POWER5_PME_PM_GRP_BR_REDIR_NONSPEC 171 #define POWER5_PME_PM_LSU1_SRQ_STFWD 172 #define POWER5_PME_PM_L3SC_MOD_INV 173 #define POWER5_PME_PM_L2_PREF 174 #define POWER5_PME_PM_GCT_NOSLOT_BR_MPRED 175 #define POWER5_PME_PM_MRK_DATA_FROM_L25_MOD 176 #define POWER5_PME_PM_L2SB_MOD_INV 177 #define POWER5_PME_PM_L2SB_ST_REQ 178 #define POWER5_PME_PM_MRK_L1_RELOAD_VALID 179 #define POWER5_PME_PM_L3SB_HIT 180 #define POWER5_PME_PM_L2SB_SHR_MOD 181 #define POWER5_PME_PM_EE_OFF_EXT_INT 182 #define POWER5_PME_PM_1PLUS_PPC_CMPL 183 #define POWER5_PME_PM_L2SC_SHR_MOD 184 #define POWER5_PME_PM_PMC6_OVERFLOW 185 #define POWER5_PME_PM_LSU_LRQ_FULL_CYC 186 #define POWER5_PME_PM_IC_PREF_INSTALL 187 #define POWER5_PME_PM_TLB_MISS 188 #define POWER5_PME_PM_GCT_FULL_CYC 189 #define POWER5_PME_PM_FXU_BUSY 190 #define POWER5_PME_PM_MRK_DATA_FROM_L3_CYC 191 #define POWER5_PME_PM_LSU_REJECT_LMQ_FULL 192 #define POWER5_PME_PM_LSU_SRQ_S0_ALLOC 193 #define POWER5_PME_PM_GRP_MRK 194 #define POWER5_PME_PM_INST_FROM_L25_SHR 195 #define POWER5_PME_PM_FPU1_FIN 196 #define POWER5_PME_PM_DC_PREF_STREAM_ALLOC 197 #define POWER5_PME_PM_BR_MPRED_TA 198 #define POWER5_PME_PM_CRQ_FULL_CYC 199 #define POWER5_PME_PM_L2SA_RCLD_DISP 200 #define POWER5_PME_PM_SNOOP_WR_RETRY_QFULL 201 #define POWER5_PME_PM_MRK_DTLB_REF_4K 202 #define POWER5_PME_PM_LSU_SRQ_S0_VALID 203 #define POWER5_PME_PM_LSU0_FLUSH_LRQ 204 #define POWER5_PME_PM_INST_FROM_L275_MOD 205 #define POWER5_PME_PM_GCT_EMPTY_CYC 206 #define POWER5_PME_PM_LARX_LSU0 207 #define POWER5_PME_PM_THRD_PRIO_DIFF_5or6_CYC 208 #define POWER5_PME_PM_SNOOP_RETRY_1AHEAD 209 #define POWER5_PME_PM_FPU1_FSQRT 210 #define POWER5_PME_PM_MRK_LD_MISS_L1_LSU1 211 #define POWER5_PME_PM_MRK_FPU_FIN 212 #define POWER5_PME_PM_THRD_PRIO_5_CYC 213 #define POWER5_PME_PM_MRK_DATA_FROM_LMEM 214 #define POWER5_PME_PM_FPU1_FRSP_FCONV 215 #define POWER5_PME_PM_SNOOP_TLBIE 216 #define POWER5_PME_PM_L3SB_SNOOP_RETRY 217 #define POWER5_PME_PM_FAB_VBYPASS_EMPTY 218 #define POWER5_PME_PM_MRK_DATA_FROM_L275_MOD 219 #define POWER5_PME_PM_6INST_CLB_CYC 220 #define POWER5_PME_PM_L2SB_RCST_DISP 221 #define POWER5_PME_PM_FLUSH 222 #define POWER5_PME_PM_L2SC_MOD_INV 223 #define POWER5_PME_PM_FPU_DENORM 224 #define POWER5_PME_PM_L3SC_HIT 225 #define POWER5_PME_PM_SNOOP_WR_RETRY_RQ 226 #define POWER5_PME_PM_LSU1_REJECT_SRQ 227 #define POWER5_PME_PM_IC_PREF_REQ 228 #define POWER5_PME_PM_L3SC_ALL_BUSY 229 #define POWER5_PME_PM_MRK_GRP_IC_MISS 230 #define POWER5_PME_PM_GCT_NOSLOT_IC_MISS 231 #define POWER5_PME_PM_MRK_DATA_FROM_L3 232 #define POWER5_PME_PM_GCT_NOSLOT_SRQ_FULL 233 #define POWER5_PME_PM_THRD_SEL_OVER_ISU_HOLD 234 #define POWER5_PME_PM_CMPLU_STALL_DCACHE_MISS 235 #define POWER5_PME_PM_L3SA_MOD_INV 236 #define POWER5_PME_PM_LSU_FLUSH_LRQ 237 #define POWER5_PME_PM_THRD_PRIO_2_CYC 238 #define POWER5_PME_PM_LSU_FLUSH_SRQ 239 #define POWER5_PME_PM_MRK_LSU_SRQ_INST_VALID 240 #define POWER5_PME_PM_L3SA_REF 241 #define POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL 242 #define POWER5_PME_PM_FPU0_STALL3 243 #define POWER5_PME_PM_GPR_MAP_FULL_CYC 244 #define POWER5_PME_PM_TB_BIT_TRANS 245 #define POWER5_PME_PM_MRK_LSU_FLUSH_LRQ 246 #define POWER5_PME_PM_FPU0_STF 247 #define POWER5_PME_PM_MRK_DTLB_MISS 248 #define POWER5_PME_PM_FPU1_FMA 249 #define POWER5_PME_PM_L2SA_MOD_TAG 250 #define POWER5_PME_PM_LSU1_FLUSH_ULD 251 #define POWER5_PME_PM_MRK_LSU0_FLUSH_UST 252 #define POWER5_PME_PM_MRK_INST_FIN 253 #define POWER5_PME_PM_FPU0_FULL_CYC 254 #define POWER5_PME_PM_LSU_LRQ_S0_ALLOC 255 #define POWER5_PME_PM_MRK_LSU1_FLUSH_ULD 256 #define POWER5_PME_PM_MRK_DTLB_REF 257 #define POWER5_PME_PM_BR_UNCOND 258 #define POWER5_PME_PM_THRD_SEL_OVER_L2MISS 259 #define POWER5_PME_PM_L2SB_SHR_INV 260 #define POWER5_PME_PM_MEM_LO_PRIO_WR_CMPL 261 #define POWER5_PME_PM_L3SC_MOD_TAG 262 #define POWER5_PME_PM_MRK_ST_MISS_L1 263 #define POWER5_PME_PM_GRP_DISP_SUCCESS 264 #define POWER5_PME_PM_THRD_PRIO_DIFF_1or2_CYC 265 #define POWER5_PME_PM_IC_DEMAND_L2_BHT_REDIRECT 266 #define POWER5_PME_PM_MEM_WQ_DISP_Q8to15 267 #define POWER5_PME_PM_FPU0_SINGLE 268 #define POWER5_PME_PM_LSU_DERAT_MISS 269 #define POWER5_PME_PM_THRD_PRIO_1_CYC 270 #define POWER5_PME_PM_L2SC_RCST_DISP_FAIL_OTHER 271 #define POWER5_PME_PM_FPU1_FEST 272 #define POWER5_PME_PM_FAB_HOLDtoVN_EMPTY 273 #define POWER5_PME_PM_SNOOP_RD_RETRY_RQ 274 #define POWER5_PME_PM_SNOOP_DCLAIM_RETRY_QFULL 275 #define POWER5_PME_PM_MRK_DATA_FROM_L25_SHR_CYC 276 #define POWER5_PME_PM_MRK_ST_CMPL_INT 277 #define POWER5_PME_PM_FLUSH_BR_MPRED 278 #define POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR 279 #define POWER5_PME_PM_FPU_STF 280 #define POWER5_PME_PM_CMPLU_STALL_FPU 281 #define POWER5_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC 282 #define POWER5_PME_PM_GCT_NOSLOT_CYC 283 #define POWER5_PME_PM_FXU0_BUSY_FXU1_IDLE 284 #define POWER5_PME_PM_PTEG_FROM_L35_SHR 285 #define POWER5_PME_PM_MRK_LSU_FLUSH_UST 286 #define POWER5_PME_PM_L3SA_HIT 287 #define POWER5_PME_PM_MRK_DATA_FROM_L25_SHR 288 #define POWER5_PME_PM_L2SB_RCST_DISP_FAIL_ADDR 289 #define POWER5_PME_PM_MRK_DATA_FROM_L35_SHR 290 #define POWER5_PME_PM_IERAT_XLATE_WR 291 #define POWER5_PME_PM_L2SA_ST_REQ 292 #define POWER5_PME_PM_THRD_SEL_T1 293 #define POWER5_PME_PM_IC_DEMAND_L2_BR_REDIRECT 294 #define POWER5_PME_PM_INST_FROM_LMEM 295 #define POWER5_PME_PM_FPU0_1FLOP 296 #define POWER5_PME_PM_MRK_DATA_FROM_L35_SHR_CYC 297 #define POWER5_PME_PM_PTEG_FROM_L2 298 #define POWER5_PME_PM_MEM_PW_CMPL 299 #define POWER5_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC 300 #define POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER 301 #define POWER5_PME_PM_FPU0_FIN 302 #define POWER5_PME_PM_MRK_DTLB_MISS_4K 303 #define POWER5_PME_PM_L3SC_SHR_INV 304 #define POWER5_PME_PM_GRP_BR_REDIR 305 #define POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL 306 #define POWER5_PME_PM_MRK_LSU_FLUSH_SRQ 307 #define POWER5_PME_PM_PTEG_FROM_L275_SHR 308 #define POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL 309 #define POWER5_PME_PM_SNOOP_RD_RETRY_WQ 310 #define POWER5_PME_PM_LSU0_NCLD 311 #define POWER5_PME_PM_FAB_DCLAIM_RETRIED 312 #define POWER5_PME_PM_LSU1_BUSY_REJECT 313 #define POWER5_PME_PM_FXLS0_FULL_CYC 314 #define POWER5_PME_PM_FPU0_FEST 315 #define POWER5_PME_PM_DTLB_REF_16M 316 #define POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR 317 #define POWER5_PME_PM_LSU0_REJECT_ERAT_MISS 318 #define POWER5_PME_PM_DATA_FROM_L25_MOD 319 #define POWER5_PME_PM_GCT_USAGE_60to79_CYC 320 #define POWER5_PME_PM_DATA_FROM_L375_MOD 321 #define POWER5_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 322 #define POWER5_PME_PM_LSU0_REJECT_RELOAD_CDF 323 #define POWER5_PME_PM_0INST_FETCH 324 #define POWER5_PME_PM_LSU1_REJECT_RELOAD_CDF 325 #define POWER5_PME_PM_L1_PREF 326 #define POWER5_PME_PM_MEM_WQ_DISP_Q0to7 327 #define POWER5_PME_PM_MRK_DATA_FROM_LMEM_CYC 328 #define POWER5_PME_PM_BRQ_FULL_CYC 329 #define POWER5_PME_PM_GRP_IC_MISS_NONSPEC 330 #define POWER5_PME_PM_PTEG_FROM_L275_MOD 331 #define POWER5_PME_PM_MRK_LD_MISS_L1_LSU0 332 #define POWER5_PME_PM_MRK_DATA_FROM_L375_SHR_CYC 333 #define POWER5_PME_PM_LSU_FLUSH 334 #define POWER5_PME_PM_DATA_FROM_L3 335 #define POWER5_PME_PM_INST_FROM_L2 336 #define POWER5_PME_PM_PMC2_OVERFLOW 337 #define POWER5_PME_PM_FPU0_DENORM 338 #define POWER5_PME_PM_FPU1_FMOV_FEST 339 #define POWER5_PME_PM_INST_FETCH_CYC 340 #define POWER5_PME_PM_LSU_LDF 341 #define POWER5_PME_PM_INST_DISP 342 #define POWER5_PME_PM_DATA_FROM_L25_SHR 343 #define POWER5_PME_PM_L1_DCACHE_RELOAD_VALID 344 #define POWER5_PME_PM_MEM_WQ_DISP_DCLAIM 345 #define POWER5_PME_PM_FPU_FULL_CYC 346 #define POWER5_PME_PM_MRK_GRP_ISSUED 347 #define POWER5_PME_PM_THRD_PRIO_3_CYC 348 #define POWER5_PME_PM_FPU_FMA 349 #define POWER5_PME_PM_INST_FROM_L35_MOD 350 #define POWER5_PME_PM_MRK_CRU_FIN 351 #define POWER5_PME_PM_SNOOP_WR_RETRY_WQ 352 #define POWER5_PME_PM_CMPLU_STALL_REJECT 353 #define POWER5_PME_PM_LSU1_REJECT_ERAT_MISS 354 #define POWER5_PME_PM_MRK_FXU_FIN 355 #define POWER5_PME_PM_L2SB_RCST_DISP_FAIL_OTHER 356 #define POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY 357 #define POWER5_PME_PM_PMC4_OVERFLOW 358 #define POWER5_PME_PM_L3SA_SNOOP_RETRY 359 #define POWER5_PME_PM_PTEG_FROM_L35_MOD 360 #define POWER5_PME_PM_INST_FROM_L25_MOD 361 #define POWER5_PME_PM_THRD_SMT_HANG 362 #define POWER5_PME_PM_CMPLU_STALL_ERAT_MISS 363 #define POWER5_PME_PM_L3SA_MOD_TAG 364 #define POWER5_PME_PM_FLUSH_SYNC 365 #define POWER5_PME_PM_INST_FROM_L2MISS 366 #define POWER5_PME_PM_L2SC_ST_HIT 367 #define POWER5_PME_PM_MEM_RQ_DISP_Q8to11 368 #define POWER5_PME_PM_MRK_GRP_DISP 369 #define POWER5_PME_PM_L2SB_MOD_TAG 370 #define POWER5_PME_PM_CLB_EMPTY_CYC 371 #define POWER5_PME_PM_L2SB_ST_HIT 372 #define POWER5_PME_PM_MEM_NONSPEC_RD_CANCEL 373 #define POWER5_PME_PM_BR_PRED_CR_TA 374 #define POWER5_PME_PM_MRK_LSU0_FLUSH_SRQ 375 #define POWER5_PME_PM_MRK_LSU_FLUSH_ULD 376 #define POWER5_PME_PM_INST_DISP_ATTEMPT 377 #define POWER5_PME_PM_INST_FROM_RMEM 378 #define POWER5_PME_PM_ST_REF_L1_LSU0 379 #define POWER5_PME_PM_LSU0_DERAT_MISS 380 #define POWER5_PME_PM_L2SB_RCLD_DISP 381 #define POWER5_PME_PM_FPU_STALL3 382 #define POWER5_PME_PM_BR_PRED_CR 383 #define POWER5_PME_PM_MRK_DATA_FROM_L2 384 #define POWER5_PME_PM_LSU0_FLUSH_SRQ 385 #define POWER5_PME_PM_FAB_PNtoNN_DIRECT 386 #define POWER5_PME_PM_IOPS_CMPL 387 #define POWER5_PME_PM_L2SC_SHR_INV 388 #define POWER5_PME_PM_L2SA_RCST_DISP_FAIL_OTHER 389 #define POWER5_PME_PM_L2SA_RCST_DISP 390 #define POWER5_PME_PM_SNOOP_RETRY_AB_COLLISION 391 #define POWER5_PME_PM_FAB_PNtoVN_SIDECAR 392 #define POWER5_PME_PM_LSU_LMQ_S0_ALLOC 393 #define POWER5_PME_PM_LSU0_REJECT_LMQ_FULL 394 #define POWER5_PME_PM_SNOOP_PW_RETRY_RQ 395 #define POWER5_PME_PM_DTLB_REF 396 #define POWER5_PME_PM_PTEG_FROM_L3 397 #define POWER5_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY 398 #define POWER5_PME_PM_LSU_SRQ_EMPTY_CYC 399 #define POWER5_PME_PM_FPU1_STF 400 #define POWER5_PME_PM_LSU_LMQ_S0_VALID 401 #define POWER5_PME_PM_GCT_USAGE_00to59_CYC 402 #define POWER5_PME_PM_DATA_FROM_L2MISS 403 #define POWER5_PME_PM_GRP_DISP_BLK_SB_CYC 404 #define POWER5_PME_PM_FPU_FMOV_FEST 405 #define POWER5_PME_PM_XER_MAP_FULL_CYC 406 #define POWER5_PME_PM_FLUSH_SB 407 #define POWER5_PME_PM_MRK_DATA_FROM_L375_SHR 408 #define POWER5_PME_PM_MRK_GRP_CMPL 409 #define POWER5_PME_PM_SUSPENDED 410 #define POWER5_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC 411 #define POWER5_PME_PM_SNOOP_RD_RETRY_QFULL 412 #define POWER5_PME_PM_L3SB_MOD_INV 413 #define POWER5_PME_PM_DATA_FROM_L35_SHR 414 #define POWER5_PME_PM_LD_MISS_L1_LSU1 415 #define POWER5_PME_PM_STCX_FAIL 416 #define POWER5_PME_PM_DC_PREF_DST 417 #define POWER5_PME_PM_GRP_DISP 418 #define POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR 419 #define POWER5_PME_PM_FPU0_FPSCR 420 #define POWER5_PME_PM_DATA_FROM_L2 421 #define POWER5_PME_PM_FPU1_DENORM 422 #define POWER5_PME_PM_FPU_1FLOP 423 #define POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER 424 #define POWER5_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL 425 #define POWER5_PME_PM_FPU0_FSQRT 426 #define POWER5_PME_PM_LD_REF_L1 427 #define POWER5_PME_PM_INST_FROM_L1 428 #define POWER5_PME_PM_TLBIE_HELD 429 #define POWER5_PME_PM_DC_PREF_OUT_OF_STREAMS 430 #define POWER5_PME_PM_MRK_DATA_FROM_L25_MOD_CYC 431 #define POWER5_PME_PM_MRK_LSU1_FLUSH_SRQ 432 #define POWER5_PME_PM_MEM_RQ_DISP_Q0to3 433 #define POWER5_PME_PM_ST_REF_L1_LSU1 434 #define POWER5_PME_PM_MRK_LD_MISS_L1 435 #define POWER5_PME_PM_L1_WRITE_CYC 436 #define POWER5_PME_PM_L2SC_ST_REQ 437 #define POWER5_PME_PM_CMPLU_STALL_FDIV 438 #define POWER5_PME_PM_THRD_SEL_OVER_CLB_EMPTY 439 #define POWER5_PME_PM_BR_MPRED_CR 440 #define POWER5_PME_PM_L3SB_MOD_TAG 441 #define POWER5_PME_PM_MRK_DATA_FROM_L2MISS 442 #define POWER5_PME_PM_LSU_REJECT_SRQ 443 #define POWER5_PME_PM_LD_MISS_L1 444 #define POWER5_PME_PM_INST_FROM_PREF 445 #define POWER5_PME_PM_DC_INV_L2 446 #define POWER5_PME_PM_STCX_PASS 447 #define POWER5_PME_PM_LSU_SRQ_FULL_CYC 448 #define POWER5_PME_PM_FPU_FIN 449 #define POWER5_PME_PM_L2SA_SHR_MOD 450 #define POWER5_PME_PM_LSU_SRQ_STFWD 451 #define POWER5_PME_PM_0INST_CLB_CYC 452 #define POWER5_PME_PM_FXU0_FIN 453 #define POWER5_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL 454 #define POWER5_PME_PM_THRD_GRP_CMPL_BOTH_CYC 455 #define POWER5_PME_PM_PMC5_OVERFLOW 456 #define POWER5_PME_PM_FPU0_FDIV 457 #define POWER5_PME_PM_PTEG_FROM_L375_SHR 458 #define POWER5_PME_PM_LD_REF_L1_LSU1 459 #define POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY 460 #define POWER5_PME_PM_HV_CYC 461 #define POWER5_PME_PM_THRD_PRIO_DIFF_0_CYC 462 #define POWER5_PME_PM_LR_CTR_MAP_FULL_CYC 463 #define POWER5_PME_PM_L3SB_SHR_INV 464 #define POWER5_PME_PM_DATA_FROM_RMEM 465 #define POWER5_PME_PM_DATA_FROM_L275_MOD 466 #define POWER5_PME_PM_LSU0_REJECT_SRQ 467 #define POWER5_PME_PM_LSU1_DERAT_MISS 468 #define POWER5_PME_PM_MRK_LSU_FIN 469 #define POWER5_PME_PM_DTLB_MISS_16M 470 #define POWER5_PME_PM_LSU0_FLUSH_UST 471 #define POWER5_PME_PM_L2SC_MOD_TAG 472 #define POWER5_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY 473 static const int power5_event_ids[][POWER5_NUM_EVENT_COUNTERS] = { [ POWER5_PME_PM_LSU_REJECT_RELOAD_CDF ] = { -1, 145, -1, -1, -1, -1 }, [ POWER5_PME_PM_FPU1_SINGLE ] = { 51, 50, -1, -1, -1, -1 }, [ POWER5_PME_PM_L3SB_REF ] = { 111, 109, -1, -1, -1, -1 }, [ POWER5_PME_PM_THRD_PRIO_DIFF_3or4_CYC ] = { -1, -1, 173, 179, -1, -1 }, [ POWER5_PME_PM_INST_FROM_L275_SHR ] = { -1, -1, 57, -1, -1, -1 }, [ POWER5_PME_PM_MRK_DATA_FROM_L375_MOD ] = { 165, -1, -1, 139, -1, -1 }, [ POWER5_PME_PM_DTLB_MISS_4K ] = { 24, 23, -1, -1, -1, -1 }, [ POWER5_PME_PM_CLB_FULL_CYC ] = { 10, 9, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_ST_CMPL ] = { 179, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_LSU_FLUSH_LRQ_FULL ] = { 140, 139, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_DATA_FROM_L275_SHR ] = { -1, -1, 130, -1, -1, -1 }, [ POWER5_PME_PM_1INST_CLB_CYC ] = { 1, 1, -1, -1, -1, -1 }, [ POWER5_PME_PM_MEM_SPEC_RD_CANCEL ] = { 157, 155, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_DTLB_MISS_16M ] = { 167, 168, -1, -1, -1, -1 }, [ POWER5_PME_PM_FPU_FDIV ] = { 55, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_FPU_SINGLE ] = { 58, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_FPU0_FMA ] = { 39, 38, -1, -1, -1, -1 }, [ POWER5_PME_PM_SLB_MISS ] = { -1, 184, -1, -1, -1, -1 }, [ POWER5_PME_PM_LSU1_FLUSH_LRQ ] = { 130, 128, -1, -1, -1, -1 }, [ POWER5_PME_PM_L2SA_ST_HIT ] = { -1, -1, 70, 74, -1, -1 }, [ POWER5_PME_PM_DTLB_MISS ] = { 22, 21, -1, -1, -1, -1 }, [ POWER5_PME_PM_BR_PRED_TA ] = { -1, 8, 4, 6, -1, -1 }, [ POWER5_PME_PM_MRK_DATA_FROM_L375_MOD_CYC ] = { -1, -1, -1, 140, -1, -1 }, [ POWER5_PME_PM_CMPLU_STALL_FXU ] = { -1, 12, -1, -1, -1, -1 }, [ POWER5_PME_PM_EXT_INT ] = { -1, -1, -1, 21, -1, -1 }, [ POWER5_PME_PM_MRK_LSU1_FLUSH_LRQ ] = { -1, -1, 143, 154, -1, -1 }, [ POWER5_PME_PM_LSU1_LDF ] = { -1, -1, 107, 111, -1, -1 }, [ POWER5_PME_PM_MRK_ST_GPS ] = { -1, 178, -1, -1, -1, -1 }, [ POWER5_PME_PM_FAB_CMD_ISSUED ] = { 27, 26, -1, -1, -1, -1 }, [ POWER5_PME_PM_LSU0_SRQ_STFWD ] = { 127, 125, -1, -1, -1, -1 }, [ POWER5_PME_PM_CR_MAP_FULL_CYC ] = { 11, 14, -1, -1, -1, -1 }, [ POWER5_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL ] = { 86, 84, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_LSU0_FLUSH_ULD ] = { -1, -1, 142, 153, -1, -1 }, [ POWER5_PME_PM_LSU_FLUSH_SRQ_FULL ] = { -1, -1, 110, 114, -1, -1 }, [ POWER5_PME_PM_FLUSH_IMBAL ] = { -1, -1, 25, 30, -1, -1 }, [ POWER5_PME_PM_MEM_RQ_DISP_Q16to19 ] = { 151, 149, -1, -1, -1, -1 }, [ POWER5_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC ] = { -1, -1, 176, 182, -1, -1 }, [ POWER5_PME_PM_DATA_FROM_L35_MOD ] = { -1, 17, 9, -1, -1, -1 }, [ POWER5_PME_PM_MEM_HI_PRIO_WR_CMPL ] = { 152, 150, -1, -1, -1, -1 }, [ POWER5_PME_PM_FPU1_FDIV ] = { 47, 46, -1, -1, -1, -1 }, [ POWER5_PME_PM_FPU0_FRSP_FCONV ] = { -1, -1, 33, 38, -1, -1 }, [ POWER5_PME_PM_MEM_RQ_DISP ] = { 156, 154, -1, -1, -1, -1 }, [ POWER5_PME_PM_LWSYNC_HELD ] = { -1, -1, 120, 125, -1, -1 }, [ POWER5_PME_PM_FXU_FIN ] = { -1, -1, 45, -1, -1, -1 }, [ POWER5_PME_PM_DSLB_MISS ] = { 21, 20, -1, -1, -1, -1 }, [ POWER5_PME_PM_FXLS1_FULL_CYC ] = { -1, -1, 41, 46, -1, -1 }, [ POWER5_PME_PM_DATA_FROM_L275_SHR ] = { -1, -1, 8, -1, -1, -1 }, [ POWER5_PME_PM_THRD_SEL_T0 ] = { -1, -1, 182, 188, -1, -1 }, [ POWER5_PME_PM_PTEG_RELOAD_VALID ] = { -1, -1, 191, 195, -1, -1 }, [ POWER5_PME_PM_LSU_LMQ_LHR_MERGE ] = { -1, -1, 112, 117, -1, -1 }, [ POWER5_PME_PM_MRK_STCX_FAIL ] = { 178, 177, -1, -1, -1, -1 }, [ POWER5_PME_PM_2INST_CLB_CYC ] = { 3, 2, -1, -1, -1, -1 }, [ POWER5_PME_PM_FAB_PNtoVN_DIRECT ] = { 34, 33, -1, -1, -1, -1 }, [ POWER5_PME_PM_PTEG_FROM_L2MISS ] = { -1, -1, 189, -1, -1, -1 }, [ POWER5_PME_PM_CMPLU_STALL_LSU ] = { -1, 13, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_DSLB_MISS ] = { -1, -1, 134, 144, -1, -1 }, [ POWER5_PME_PM_LSU_FLUSH_ULD ] = { 142, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_PTEG_FROM_LMEM ] = { -1, 183, 157, -1, -1, -1 }, [ POWER5_PME_PM_MRK_BRU_FIN ] = { -1, 158, -1, -1, -1, -1 }, [ POWER5_PME_PM_MEM_WQ_DISP_WRITE ] = { 159, 157, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_DATA_FROM_L275_MOD_CYC ] = { -1, -1, -1, 137, -1, -1 }, [ POWER5_PME_PM_LSU1_NCLD ] = { -1, -1, 108, 112, -1, -1 }, [ POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER ] = { -1, -1, 65, 69, -1, -1 }, [ POWER5_PME_PM_SNOOP_PW_RETRY_WQ_PWQ ] = { -1, -1, 159, 167, -1, -1 }, [ POWER5_PME_PM_FPR_MAP_FULL_CYC ] = { 35, 34, -1, -1, -1, -1 }, [ POWER5_PME_PM_FPU1_FULL_CYC ] = { 50, 49, -1, -1, -1, -1 }, [ POWER5_PME_PM_L3SA_ALL_BUSY ] = { 106, 104, -1, -1, -1, -1 }, [ POWER5_PME_PM_3INST_CLB_CYC ] = { 4, 3, -1, -1, -1, -1 }, [ POWER5_PME_PM_MEM_PWQ_DISP_Q2or3 ] = { -1, -1, 123, 128, -1, -1 }, [ POWER5_PME_PM_L2SA_SHR_INV ] = { -1, -1, 69, 73, -1, -1 }, [ POWER5_PME_PM_THRESH_TIMEO ] = { -1, -1, 185, -1, -1, -1 }, [ POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL ] = { -1, -1, 68, 72, -1, -1 }, [ POWER5_PME_PM_THRD_SEL_OVER_GCT_IMBAL ] = { -1, -1, 179, 185, -1, -1 }, [ POWER5_PME_PM_FPU_FSQRT ] = { -1, 53, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_LSU0_FLUSH_LRQ ] = { -1, -1, 139, 150, -1, -1 }, [ POWER5_PME_PM_PMC1_OVERFLOW ] = { -1, 180, -1, -1, -1, -1 }, [ POWER5_PME_PM_L3SC_SNOOP_RETRY ] = { -1, -1, 99, 103, -1, -1 }, [ POWER5_PME_PM_DATA_TABLEWALK_CYC ] = { 20, 19, -1, -1, -1, -1 }, [ POWER5_PME_PM_THRD_PRIO_6_CYC ] = { 208, 202, -1, -1, -1, -1 }, [ POWER5_PME_PM_FPU_FEST ] = { -1, -1, -1, 43, -1, -1 }, [ POWER5_PME_PM_FAB_M1toP1_SIDECAR_EMPTY ] = { 31, 30, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_DATA_FROM_RMEM ] = { 166, -1, -1, 142, -1, -1 }, [ POWER5_PME_PM_MRK_DATA_FROM_L35_MOD_CYC ] = { -1, -1, -1, 138, -1, -1 }, [ POWER5_PME_PM_MEM_PWQ_DISP ] = { 153, 151, -1, -1, -1, -1 }, [ POWER5_PME_PM_FAB_P1toM1_SIDECAR_EMPTY ] = { 32, 31, -1, -1, -1, -1 }, [ POWER5_PME_PM_LD_MISS_L1_LSU0 ] = { -1, -1, 101, 104, -1, -1 }, [ POWER5_PME_PM_SNOOP_PARTIAL_RTRY_QFULL ] = { -1, -1, 158, 166, -1, -1 }, [ POWER5_PME_PM_FPU1_STALL3 ] = { 52, 51, -1, -1, -1, -1 }, [ POWER5_PME_PM_GCT_USAGE_80to99_CYC ] = { -1, -1, 47, -1, -1, -1 }, [ POWER5_PME_PM_WORK_HELD ] = { -1, -1, -1, 192, -1, -1 }, [ POWER5_PME_PM_INST_CMPL ] = { 174, 174, -1, -1, 0, -1 }, [ POWER5_PME_PM_LSU1_FLUSH_UST ] = { 133, 131, -1, -1, -1, -1 }, [ POWER5_PME_PM_FXU_IDLE ] = { 59, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_LSU0_FLUSH_ULD ] = { 121, 119, -1, -1, -1, -1 }, [ POWER5_PME_PM_LSU1_REJECT_LMQ_FULL ] = { 135, 133, -1, -1, -1, -1 }, [ POWER5_PME_PM_GRP_DISP_REJECT ] = { 65, 65, -1, 55, -1, -1 }, [ POWER5_PME_PM_L2SA_MOD_INV ] = { -1, -1, 63, 67, -1, -1 }, [ POWER5_PME_PM_PTEG_FROM_L25_SHR ] = { 184, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_FAB_CMD_RETRIED ] = { -1, -1, 17, 22, -1, -1 }, [ POWER5_PME_PM_L3SA_SHR_INV ] = { -1, -1, 90, 94, -1, -1 }, [ POWER5_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL ] = { -1, -1, 76, 80, -1, -1 }, [ POWER5_PME_PM_L2SA_RCST_DISP_FAIL_ADDR ] = { -1, -1, 66, 70, -1, -1 }, [ POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_RC_FULL ] = { 84, 82, -1, -1, -1, -1 }, [ POWER5_PME_PM_PTEG_FROM_L375_MOD ] = { 188, -1, -1, 164, -1, -1 }, [ POWER5_PME_PM_MRK_LSU1_FLUSH_UST ] = { -1, -1, 146, 157, -1, -1 }, [ POWER5_PME_PM_BR_ISSUED ] = { -1, -1, 0, 1, -1, -1 }, [ POWER5_PME_PM_MRK_GRP_BR_REDIR ] = { -1, 172, -1, -1, -1, -1 }, [ POWER5_PME_PM_EE_OFF ] = { -1, -1, 15, 19, -1, -1 }, [ POWER5_PME_PM_MEM_RQ_DISP_Q4to7 ] = { -1, -1, 126, 131, -1, -1 }, [ POWER5_PME_PM_MEM_FAST_PATH_RD_DISP ] = { -1, -1, 190, 193, -1, -1 }, [ POWER5_PME_PM_INST_FROM_L3 ] = { 78, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_ITLB_MISS ] = { 81, 79, -1, -1, -1, -1 }, [ POWER5_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { -1, -1, -1, 49, -1, -1 }, [ POWER5_PME_PM_FXLS_FULL_CYC ] = { -1, -1, -1, 47, -1, -1 }, [ POWER5_PME_PM_DTLB_REF_4K ] = { 26, 25, -1, -1, -1, -1 }, [ POWER5_PME_PM_GRP_DISP_VALID ] = { 66, 66, -1, -1, -1, -1 }, [ POWER5_PME_PM_LSU_FLUSH_UST ] = { -1, 140, -1, -1, -1, -1 }, [ POWER5_PME_PM_FXU1_FIN ] = { -1, -1, 44, 50, -1, -1 }, [ POWER5_PME_PM_THRD_PRIO_4_CYC ] = { 206, 200, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_DATA_FROM_L35_MOD ] = { -1, 163, 131, -1, -1, -1 }, [ POWER5_PME_PM_4INST_CLB_CYC ] = { 5, 4, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_DTLB_REF_16M ] = { 169, 170, -1, -1, -1, -1 }, [ POWER5_PME_PM_INST_FROM_L375_MOD ] = { -1, -1, -1, 62, -1, -1 }, [ POWER5_PME_PM_L2SC_RCST_DISP_FAIL_ADDR ] = { -1, -1, 82, 86, -1, -1 }, [ POWER5_PME_PM_GRP_CMPL ] = { -1, -1, 49, -1, -1, -1 }, [ POWER5_PME_PM_FPU1_1FLOP ] = { 45, 44, -1, -1, -1, -1 }, [ POWER5_PME_PM_FPU_FRSP_FCONV ] = { -1, -1, 39, -1, -1, -1 }, [ POWER5_PME_PM_5INST_CLB_CYC ] = { 6, 5, -1, -1, -1, -1 }, [ POWER5_PME_PM_L3SC_REF ] = { 114, 112, -1, -1, -1, -1 }, [ POWER5_PME_PM_THRD_L2MISS_BOTH_CYC ] = { -1, -1, 170, 176, -1, -1 }, [ POWER5_PME_PM_MEM_PW_GATH ] = { -1, -1, 124, 129, -1, -1 }, [ POWER5_PME_PM_FAB_PNtoNN_SIDECAR ] = { -1, -1, 21, 26, -1, -1 }, [ POWER5_PME_PM_FAB_DCLAIM_ISSUED ] = { 28, 27, -1, -1, -1, -1 }, [ POWER5_PME_PM_GRP_IC_MISS ] = { 67, 67, -1, -1, -1, -1 }, [ POWER5_PME_PM_INST_FROM_L35_SHR ] = { 79, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_LSU_LMQ_FULL_CYC ] = { -1, -1, 111, 116, -1, -1 }, [ POWER5_PME_PM_MRK_DATA_FROM_L2_CYC ] = { -1, 162, -1, -1, -1, -1 }, [ POWER5_PME_PM_LSU_SRQ_SYNC_CYC ] = { -1, -1, 119, 124, -1, -1 }, [ POWER5_PME_PM_LSU0_BUSY_REJECT ] = { 117, 115, -1, -1, -1, -1 }, [ POWER5_PME_PM_LSU_REJECT_ERAT_MISS ] = { 145, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_DATA_FROM_RMEM_CYC ] = { -1, -1, -1, 143, -1, -1 }, [ POWER5_PME_PM_DATA_FROM_L375_SHR ] = { -1, -1, 10, -1, -1, -1 }, [ POWER5_PME_PM_FPU0_FMOV_FEST ] = { -1, -1, 31, 36, -1, -1 }, [ POWER5_PME_PM_PTEG_FROM_L25_MOD ] = { -1, 181, 153, -1, -1, -1 }, [ POWER5_PME_PM_LD_REF_L1_LSU0 ] = { -1, -1, 103, 107, -1, -1 }, [ POWER5_PME_PM_THRD_PRIO_7_CYC ] = { 209, 203, -1, -1, -1, -1 }, [ POWER5_PME_PM_LSU1_FLUSH_SRQ ] = { 131, 129, -1, -1, -1, -1 }, [ POWER5_PME_PM_L2SC_RCST_DISP ] = { 101, 99, -1, -1, -1, -1 }, [ POWER5_PME_PM_CMPLU_STALL_DIV ] = { -1, -1, -1, 7, -1, -1 }, [ POWER5_PME_PM_MEM_RQ_DISP_Q12to15 ] = { -1, -1, 121, 126, -1, -1 }, [ POWER5_PME_PM_INST_FROM_L375_SHR ] = { -1, -1, 58, -1, -1, -1 }, [ POWER5_PME_PM_ST_REF_L1 ] = { -1, -1, 165, -1, -1, -1 }, [ POWER5_PME_PM_L3SB_ALL_BUSY ] = { 109, 107, -1, -1, -1, -1 }, [ POWER5_PME_PM_FAB_P1toVNorNN_SIDECAR_EMPTY ] = { -1, -1, 20, 25, -1, -1 }, [ POWER5_PME_PM_MRK_DATA_FROM_L275_SHR_CYC ] = { -1, 161, -1, -1, -1, -1 }, [ POWER5_PME_PM_FAB_HOLDtoNN_EMPTY ] = { 29, 28, -1, -1, -1, -1 }, [ POWER5_PME_PM_DATA_FROM_LMEM ] = { -1, 18, 11, -1, -1, -1 }, [ POWER5_PME_PM_RUN_CYC ] = { 190, -1, -1, -1, -1, 0 }, [ POWER5_PME_PM_PTEG_FROM_RMEM ] = { 189, -1, -1, 165, -1, -1 }, [ POWER5_PME_PM_L2SC_RCLD_DISP ] = { 99, 97, -1, -1, -1, -1 }, [ POWER5_PME_PM_LSU0_LDF ] = { -1, -1, 105, 109, -1, -1 }, [ POWER5_PME_PM_LSU_LRQ_S0_VALID ] = { 144, 143, -1, -1, -1, -1 }, [ POWER5_PME_PM_PMC3_OVERFLOW ] = { -1, -1, -1, 162, -1, -1 }, [ POWER5_PME_PM_MRK_IMR_RELOAD ] = { 173, 173, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_GRP_TIMEO ] = { -1, -1, -1, 148, -1, -1 }, [ POWER5_PME_PM_ST_MISS_L1 ] = { -1, -1, 164, 171, -1, -1 }, [ POWER5_PME_PM_STOP_COMPLETION ] = { -1, -1, 163, -1, -1, -1 }, [ POWER5_PME_PM_LSU_BUSY_REJECT ] = { 139, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_ISLB_MISS ] = { 80, 78, -1, -1, -1, -1 }, [ POWER5_PME_PM_CYC ] = { 12, 15, 6, 12, -1, -1 }, [ POWER5_PME_PM_THRD_ONE_RUN_CYC ] = { 202, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_GRP_BR_REDIR_NONSPEC ] = { 64, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_LSU1_SRQ_STFWD ] = { 138, 136, -1, -1, -1, -1 }, [ POWER5_PME_PM_L3SC_MOD_INV ] = { -1, -1, 97, 101, -1, -1 }, [ POWER5_PME_PM_L2_PREF ] = { -1, -1, 87, 91, -1, -1 }, [ POWER5_PME_PM_GCT_NOSLOT_BR_MPRED ] = { -1, -1, -1, 51, -1, -1 }, [ POWER5_PME_PM_MRK_DATA_FROM_L25_MOD ] = { -1, 159, 129, -1, -1, -1 }, [ POWER5_PME_PM_L2SB_MOD_INV ] = { -1, -1, 71, 75, -1, -1 }, [ POWER5_PME_PM_L2SB_ST_REQ ] = { 97, 95, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_L1_RELOAD_VALID ] = { -1, -1, 138, 149, -1, -1 }, [ POWER5_PME_PM_L3SB_HIT ] = { -1, -1, 92, 96, -1, -1 }, [ POWER5_PME_PM_L2SB_SHR_MOD ] = { 96, 94, -1, -1, -1, -1 }, [ POWER5_PME_PM_EE_OFF_EXT_INT ] = { -1, -1, 16, 20, -1, -1 }, [ POWER5_PME_PM_1PLUS_PPC_CMPL ] = { 2, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_L2SC_SHR_MOD ] = { 104, 102, -1, -1, -1, -1 }, [ POWER5_PME_PM_PMC6_OVERFLOW ] = { -1, -1, 152, -1, -1, -1 }, [ POWER5_PME_PM_LSU_LRQ_FULL_CYC ] = { -1, -1, 116, 120, -1, -1 }, [ POWER5_PME_PM_IC_PREF_INSTALL ] = { -1, -1, 54, 58, -1, -1 }, [ POWER5_PME_PM_TLB_MISS ] = { 210, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_GCT_FULL_CYC ] = { 61, 60, -1, 52, -1, -1 }, [ POWER5_PME_PM_FXU_BUSY ] = { -1, 57, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_DATA_FROM_L3_CYC ] = { -1, 166, -1, -1, -1, -1 }, [ POWER5_PME_PM_LSU_REJECT_LMQ_FULL ] = { -1, 144, -1, -1, -1, -1 }, [ POWER5_PME_PM_LSU_SRQ_S0_ALLOC ] = { 147, 146, -1, -1, -1, -1 }, [ POWER5_PME_PM_GRP_MRK ] = { 70, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_INST_FROM_L25_SHR ] = { 77, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_FPU1_FIN ] = { -1, -1, 35, 40, -1, -1 }, [ POWER5_PME_PM_DC_PREF_STREAM_ALLOC ] = { -1, -1, 14, 18, -1, -1 }, [ POWER5_PME_PM_BR_MPRED_TA ] = { -1, -1, 2, 3, -1, -1 }, [ POWER5_PME_PM_CRQ_FULL_CYC ] = { -1, -1, 5, 11, -1, -1 }, [ POWER5_PME_PM_L2SA_RCLD_DISP ] = { 83, 81, -1, -1, -1, -1 }, [ POWER5_PME_PM_SNOOP_WR_RETRY_QFULL ] = { -1, -1, 161, 169, -1, -1 }, [ POWER5_PME_PM_MRK_DTLB_REF_4K ] = { 170, 171, -1, -1, -1, -1 }, [ POWER5_PME_PM_LSU_SRQ_S0_VALID ] = { 148, 147, -1, -1, -1, -1 }, [ POWER5_PME_PM_LSU0_FLUSH_LRQ ] = { 119, 117, -1, -1, -1, -1 }, [ POWER5_PME_PM_INST_FROM_L275_MOD ] = { -1, -1, -1, 61, -1, -1 }, [ POWER5_PME_PM_GCT_EMPTY_CYC ] = { -1, 195, -1, -1, -1, -1 }, [ POWER5_PME_PM_LARX_LSU0 ] = { 115, 113, -1, -1, -1, -1 }, [ POWER5_PME_PM_THRD_PRIO_DIFF_5or6_CYC ] = { -1, -1, 174, 180, -1, -1 }, [ POWER5_PME_PM_SNOOP_RETRY_1AHEAD ] = { 195, 189, -1, -1, -1, -1 }, [ POWER5_PME_PM_FPU1_FSQRT ] = { 49, 48, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_LD_MISS_L1_LSU1 ] = { 177, 176, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_FPU_FIN ] = { -1, -1, 136, -1, -1, -1 }, [ POWER5_PME_PM_THRD_PRIO_5_CYC ] = { 207, 201, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_DATA_FROM_LMEM ] = { -1, 167, 133, -1, -1, -1 }, [ POWER5_PME_PM_FPU1_FRSP_FCONV ] = { -1, -1, 37, 42, -1, -1 }, [ POWER5_PME_PM_SNOOP_TLBIE ] = { 196, 190, -1, -1, -1, -1 }, [ POWER5_PME_PM_L3SB_SNOOP_RETRY ] = { -1, -1, 95, 99, -1, -1 }, [ POWER5_PME_PM_FAB_VBYPASS_EMPTY ] = { -1, -1, 23, 28, -1, -1 }, [ POWER5_PME_PM_MRK_DATA_FROM_L275_MOD ] = { 162, -1, -1, 136, -1, -1 }, [ POWER5_PME_PM_6INST_CLB_CYC ] = { 7, 6, -1, -1, -1, -1 }, [ POWER5_PME_PM_L2SB_RCST_DISP ] = { 93, 91, -1, -1, -1, -1 }, [ POWER5_PME_PM_FLUSH ] = { -1, -1, 26, 31, -1, -1 }, [ POWER5_PME_PM_L2SC_MOD_INV ] = { -1, -1, 79, 83, -1, -1 }, [ POWER5_PME_PM_FPU_DENORM ] = { 54, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_L3SC_HIT ] = { -1, -1, 96, 100, -1, -1 }, [ POWER5_PME_PM_SNOOP_WR_RETRY_RQ ] = { 197, 191, -1, -1, -1, -1 }, [ POWER5_PME_PM_LSU1_REJECT_SRQ ] = { 137, 135, -1, -1, -1, -1 }, [ POWER5_PME_PM_IC_PREF_REQ ] = { 71, 69, -1, -1, -1, -1 }, [ POWER5_PME_PM_L3SC_ALL_BUSY ] = { 112, 110, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_GRP_IC_MISS ] = { -1, -1, -1, 147, -1, -1 }, [ POWER5_PME_PM_GCT_NOSLOT_IC_MISS ] = { -1, 59, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_DATA_FROM_L3 ] = { 163, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_GCT_NOSLOT_SRQ_FULL ] = { -1, -1, 46, -1, -1, -1 }, [ POWER5_PME_PM_THRD_SEL_OVER_ISU_HOLD ] = { -1, -1, 180, 186, -1, -1 }, [ POWER5_PME_PM_CMPLU_STALL_DCACHE_MISS ] = { -1, 10, -1, -1, -1, -1 }, [ POWER5_PME_PM_L3SA_MOD_INV ] = { -1, -1, 89, 93, -1, -1 }, [ POWER5_PME_PM_LSU_FLUSH_LRQ ] = { -1, 138, -1, -1, -1, -1 }, [ POWER5_PME_PM_THRD_PRIO_2_CYC ] = { 204, 198, -1, -1, -1, -1 }, [ POWER5_PME_PM_LSU_FLUSH_SRQ ] = { 141, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_LSU_SRQ_INST_VALID ] = { -1, -1, 149, 161, -1, -1 }, [ POWER5_PME_PM_L3SA_REF ] = { 108, 106, -1, -1, -1, -1 }, [ POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL ] = { -1, -1, 84, 88, -1, -1 }, [ POWER5_PME_PM_FPU0_STALL3 ] = { 43, 42, -1, -1, -1, -1 }, [ POWER5_PME_PM_GPR_MAP_FULL_CYC ] = { -1, -1, 48, 53, -1, -1 }, [ POWER5_PME_PM_TB_BIT_TRANS ] = { 201, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_LSU_FLUSH_LRQ ] = { -1, -1, 147, -1, -1, -1 }, [ POWER5_PME_PM_FPU0_STF ] = { 44, 43, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_DTLB_MISS ] = { -1, -1, 135, 145, -1, -1 }, [ POWER5_PME_PM_FPU1_FMA ] = { 48, 47, -1, -1, -1, -1 }, [ POWER5_PME_PM_L2SA_MOD_TAG ] = { 82, 80, -1, -1, -1, -1 }, [ POWER5_PME_PM_LSU1_FLUSH_ULD ] = { 132, 130, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_LSU0_FLUSH_UST ] = { -1, -1, 141, 152, -1, -1 }, [ POWER5_PME_PM_MRK_INST_FIN ] = { -1, -1, 137, -1, -1, -1 }, [ POWER5_PME_PM_FPU0_FULL_CYC ] = { 41, 40, -1, -1, -1, -1 }, [ POWER5_PME_PM_LSU_LRQ_S0_ALLOC ] = { 143, 142, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_LSU1_FLUSH_ULD ] = { -1, -1, 145, 156, -1, -1 }, [ POWER5_PME_PM_MRK_DTLB_REF ] = { 213, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_BR_UNCOND ] = { 9, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_THRD_SEL_OVER_L2MISS ] = { -1, -1, 181, 187, -1, -1 }, [ POWER5_PME_PM_L2SB_SHR_INV ] = { -1, -1, 77, 81, -1, -1 }, [ POWER5_PME_PM_MEM_LO_PRIO_WR_CMPL ] = { -1, -1, 122, 127, -1, -1 }, [ POWER5_PME_PM_L3SC_MOD_TAG ] = { 113, 111, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_ST_MISS_L1 ] = { 180, 179, -1, -1, -1, -1 }, [ POWER5_PME_PM_GRP_DISP_SUCCESS ] = { -1, -1, 51, -1, -1, -1 }, [ POWER5_PME_PM_THRD_PRIO_DIFF_1or2_CYC ] = { -1, -1, 172, 178, -1, -1 }, [ POWER5_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = { -1, -1, 52, 56, -1, -1 }, [ POWER5_PME_PM_MEM_WQ_DISP_Q8to15 ] = { -1, -1, 127, 132, -1, -1 }, [ POWER5_PME_PM_FPU0_SINGLE ] = { 42, 41, -1, -1, -1, -1 }, [ POWER5_PME_PM_LSU_DERAT_MISS ] = { -1, 137, -1, -1, -1, -1 }, [ POWER5_PME_PM_THRD_PRIO_1_CYC ] = { 203, 197, -1, -1, -1, -1 }, [ POWER5_PME_PM_L2SC_RCST_DISP_FAIL_OTHER ] = { -1, -1, 83, 87, -1, -1 }, [ POWER5_PME_PM_FPU1_FEST ] = { -1, -1, 34, 39, -1, -1 }, [ POWER5_PME_PM_FAB_HOLDtoVN_EMPTY ] = { 30, 29, -1, -1, -1, -1 }, [ POWER5_PME_PM_SNOOP_RD_RETRY_RQ ] = { 194, 188, -1, -1, -1, -1 }, [ POWER5_PME_PM_SNOOP_DCLAIM_RETRY_QFULL ] = { 191, 185, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_DATA_FROM_L25_SHR_CYC ] = { -1, 160, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_ST_CMPL_INT ] = { -1, -1, 150, -1, -1, -1 }, [ POWER5_PME_PM_FLUSH_BR_MPRED ] = { -1, -1, 24, 29, -1, -1 }, [ POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR ] = { -1, -1, 72, 76, -1, -1 }, [ POWER5_PME_PM_FPU_STF ] = { -1, 56, -1, -1, -1, -1 }, [ POWER5_PME_PM_CMPLU_STALL_FPU ] = { -1, -1, -1, 9, -1, -1 }, [ POWER5_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC ] = { -1, -1, 175, 181, -1, -1 }, [ POWER5_PME_PM_GCT_NOSLOT_CYC ] = { 60, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { -1, -1, 42, -1, -1, -1 }, [ POWER5_PME_PM_PTEG_FROM_L35_SHR ] = { 187, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_LSU_FLUSH_UST ] = { -1, -1, 148, -1, -1, -1 }, [ POWER5_PME_PM_L3SA_HIT ] = { -1, -1, 88, 92, -1, -1 }, [ POWER5_PME_PM_MRK_DATA_FROM_L25_SHR ] = { 161, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_L2SB_RCST_DISP_FAIL_ADDR ] = { -1, -1, 74, 78, -1, -1 }, [ POWER5_PME_PM_MRK_DATA_FROM_L35_SHR ] = { 164, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_IERAT_XLATE_WR ] = { 72, 70, -1, -1, -1, -1 }, [ POWER5_PME_PM_L2SA_ST_REQ ] = { 89, 87, -1, -1, -1, -1 }, [ POWER5_PME_PM_THRD_SEL_T1 ] = { -1, -1, 183, 189, -1, -1 }, [ POWER5_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = { -1, -1, 53, 57, -1, -1 }, [ POWER5_PME_PM_INST_FROM_LMEM ] = { -1, 77, -1, -1, -1, -1 }, [ POWER5_PME_PM_FPU0_1FLOP ] = { 36, 35, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_DATA_FROM_L35_SHR_CYC ] = { -1, 164, -1, -1, -1, -1 }, [ POWER5_PME_PM_PTEG_FROM_L2 ] = { 183, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_MEM_PW_CMPL ] = { 154, 152, -1, -1, -1, -1 }, [ POWER5_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC ] = { -1, -1, 177, 183, -1, -1 }, [ POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER ] = { -1, -1, 73, 77, -1, -1 }, [ POWER5_PME_PM_FPU0_FIN ] = { -1, -1, 30, 35, -1, -1 }, [ POWER5_PME_PM_MRK_DTLB_MISS_4K ] = { 168, 169, -1, -1, -1, -1 }, [ POWER5_PME_PM_L3SC_SHR_INV ] = { -1, -1, 98, 102, -1, -1 }, [ POWER5_PME_PM_GRP_BR_REDIR ] = { 63, 62, -1, -1, -1, -1 }, [ POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL ] = { 100, 98, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_LSU_FLUSH_SRQ ] = { -1, -1, -1, 159, -1, -1 }, [ POWER5_PME_PM_PTEG_FROM_L275_SHR ] = { -1, -1, 154, -1, -1, -1 }, [ POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL ] = { 92, 90, -1, -1, -1, -1 }, [ POWER5_PME_PM_SNOOP_RD_RETRY_WQ ] = { -1, -1, 160, 168, -1, -1 }, [ POWER5_PME_PM_LSU0_NCLD ] = { -1, -1, 106, 110, -1, -1 }, [ POWER5_PME_PM_FAB_DCLAIM_RETRIED ] = { -1, -1, 18, 23, -1, -1 }, [ POWER5_PME_PM_LSU1_BUSY_REJECT ] = { 128, 126, -1, -1, -1, -1 }, [ POWER5_PME_PM_FXLS0_FULL_CYC ] = { -1, -1, 40, 45, -1, -1 }, [ POWER5_PME_PM_FPU0_FEST ] = { -1, -1, 29, 34, -1, -1 }, [ POWER5_PME_PM_DTLB_REF_16M ] = { 25, 24, -1, -1, -1, -1 }, [ POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR ] = { -1, -1, 80, 84, -1, -1 }, [ POWER5_PME_PM_LSU0_REJECT_ERAT_MISS ] = { 123, 121, -1, -1, -1, -1 }, [ POWER5_PME_PM_DATA_FROM_L25_MOD ] = { -1, 16, 7, -1, -1, -1 }, [ POWER5_PME_PM_GCT_USAGE_60to79_CYC ] = { -1, 61, -1, -1, -1, -1 }, [ POWER5_PME_PM_DATA_FROM_L375_MOD ] = { 18, -1, -1, 14, -1, -1 }, [ POWER5_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { -1, 141, 115, -1, -1, -1 }, [ POWER5_PME_PM_LSU0_REJECT_RELOAD_CDF ] = { 125, 123, -1, -1, -1, -1 }, [ POWER5_PME_PM_0INST_FETCH ] = { -1, -1, -1, 0, -1, -1 }, [ POWER5_PME_PM_LSU1_REJECT_RELOAD_CDF ] = { 136, 134, -1, -1, -1, -1 }, [ POWER5_PME_PM_L1_PREF ] = { -1, -1, 61, 65, -1, -1 }, [ POWER5_PME_PM_MEM_WQ_DISP_Q0to7 ] = { 158, 156, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_DATA_FROM_LMEM_CYC ] = { -1, -1, -1, 141, -1, -1 }, [ POWER5_PME_PM_BRQ_FULL_CYC ] = { 8, 7, -1, -1, -1, -1 }, [ POWER5_PME_PM_GRP_IC_MISS_NONSPEC ] = { 69, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_PTEG_FROM_L275_MOD ] = { 185, -1, -1, 163, -1, -1 }, [ POWER5_PME_PM_MRK_LD_MISS_L1_LSU0 ] = { 176, 175, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_DATA_FROM_L375_SHR_CYC ] = { -1, 165, -1, -1, -1, -1 }, [ POWER5_PME_PM_LSU_FLUSH ] = { -1, -1, 109, 113, -1, -1 }, [ POWER5_PME_PM_DATA_FROM_L3 ] = { 16, -1, 192, -1, -1, -1 }, [ POWER5_PME_PM_INST_FROM_L2 ] = { 76, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_PMC2_OVERFLOW ] = { -1, -1, 151, -1, -1, -1 }, [ POWER5_PME_PM_FPU0_DENORM ] = { 37, 36, -1, -1, -1, -1 }, [ POWER5_PME_PM_FPU1_FMOV_FEST ] = { -1, -1, 36, 41, -1, -1 }, [ POWER5_PME_PM_INST_FETCH_CYC ] = { 75, 73, -1, -1, -1, -1 }, [ POWER5_PME_PM_LSU_LDF ] = { -1, -1, -1, 115, -1, -1 }, [ POWER5_PME_PM_INST_DISP ] = { -1, -1, 56, 60, -1, -1 }, [ POWER5_PME_PM_DATA_FROM_L25_SHR ] = { 14, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_L1_DCACHE_RELOAD_VALID ] = { -1, -1, 60, 64, -1, -1 }, [ POWER5_PME_PM_MEM_WQ_DISP_DCLAIM ] = { -1, -1, 128, 133, -1, -1 }, [ POWER5_PME_PM_FPU_FULL_CYC ] = { 57, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_GRP_ISSUED ] = { 172, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_THRD_PRIO_3_CYC ] = { 205, 199, -1, -1, -1, -1 }, [ POWER5_PME_PM_FPU_FMA ] = { -1, 54, -1, -1, -1, -1 }, [ POWER5_PME_PM_INST_FROM_L35_MOD ] = { -1, 76, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_CRU_FIN ] = { -1, -1, -1, 134, -1, -1 }, [ POWER5_PME_PM_SNOOP_WR_RETRY_WQ ] = { -1, -1, 162, 170, -1, -1 }, [ POWER5_PME_PM_CMPLU_STALL_REJECT ] = { -1, -1, -1, 10, -1, -1 }, [ POWER5_PME_PM_LSU1_REJECT_ERAT_MISS ] = { 134, 132, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_FXU_FIN ] = { -1, 58, -1, -1, -1, -1 }, [ POWER5_PME_PM_L2SB_RCST_DISP_FAIL_OTHER ] = { -1, -1, 75, 79, -1, -1 }, [ POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY ] = { 103, 101, -1, -1, -1, -1 }, [ POWER5_PME_PM_PMC4_OVERFLOW ] = { 181, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_L3SA_SNOOP_RETRY ] = { -1, -1, 91, 95, -1, -1 }, [ POWER5_PME_PM_PTEG_FROM_L35_MOD ] = { -1, 182, 155, -1, -1, -1 }, [ POWER5_PME_PM_INST_FROM_L25_MOD ] = { -1, 75, -1, -1, -1, -1 }, [ POWER5_PME_PM_THRD_SMT_HANG ] = { -1, -1, 184, 190, -1, -1 }, [ POWER5_PME_PM_CMPLU_STALL_ERAT_MISS ] = { -1, -1, -1, 8, -1, -1 }, [ POWER5_PME_PM_L3SA_MOD_TAG ] = { 107, 105, -1, -1, -1, -1 }, [ POWER5_PME_PM_FLUSH_SYNC ] = { -1, -1, 28, 33, -1, -1 }, [ POWER5_PME_PM_INST_FROM_L2MISS ] = { 212, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_L2SC_ST_HIT ] = { -1, -1, 86, 90, -1, -1 }, [ POWER5_PME_PM_MEM_RQ_DISP_Q8to11 ] = { 150, 148, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_GRP_DISP ] = { 171, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_L2SB_MOD_TAG ] = { 90, 88, -1, -1, -1, -1 }, [ POWER5_PME_PM_CLB_EMPTY_CYC ] = { -1, -1, 169, 175, -1, -1 }, [ POWER5_PME_PM_L2SB_ST_HIT ] = { -1, -1, 78, 82, -1, -1 }, [ POWER5_PME_PM_MEM_NONSPEC_RD_CANCEL ] = { -1, -1, 125, 130, -1, -1 }, [ POWER5_PME_PM_BR_PRED_CR_TA ] = { -1, -1, -1, 5, -1, -1 }, [ POWER5_PME_PM_MRK_LSU0_FLUSH_SRQ ] = { -1, -1, 140, 151, -1, -1 }, [ POWER5_PME_PM_MRK_LSU_FLUSH_ULD ] = { -1, -1, -1, 160, -1, -1 }, [ POWER5_PME_PM_INST_DISP_ATTEMPT ] = { 74, 72, -1, -1, -1, -1 }, [ POWER5_PME_PM_INST_FROM_RMEM ] = { -1, -1, -1, 63, -1, -1 }, [ POWER5_PME_PM_ST_REF_L1_LSU0 ] = { -1, -1, 166, 172, -1, -1 }, [ POWER5_PME_PM_LSU0_DERAT_MISS ] = { 118, 116, -1, -1, -1, -1 }, [ POWER5_PME_PM_L2SB_RCLD_DISP ] = { 91, 89, -1, -1, -1, -1 }, [ POWER5_PME_PM_FPU_STALL3 ] = { -1, 55, -1, -1, -1, -1 }, [ POWER5_PME_PM_BR_PRED_CR ] = { -1, -1, 3, 4, -1, -1 }, [ POWER5_PME_PM_MRK_DATA_FROM_L2 ] = { 160, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_LSU0_FLUSH_SRQ ] = { 120, 118, -1, -1, -1, -1 }, [ POWER5_PME_PM_FAB_PNtoNN_DIRECT ] = { 33, 32, -1, -1, -1, -1 }, [ POWER5_PME_PM_IOPS_CMPL ] = { 73, 71, 55, 59, -1, -1 }, [ POWER5_PME_PM_L2SC_SHR_INV ] = { -1, -1, 85, 89, -1, -1 }, [ POWER5_PME_PM_L2SA_RCST_DISP_FAIL_OTHER ] = { -1, -1, 67, 71, -1, -1 }, [ POWER5_PME_PM_L2SA_RCST_DISP ] = { 85, 83, -1, -1, -1, -1 }, [ POWER5_PME_PM_SNOOP_RETRY_AB_COLLISION ] = { -1, -1, -1, 194, -1, -1 }, [ POWER5_PME_PM_FAB_PNtoVN_SIDECAR ] = { -1, -1, 22, 27, -1, -1 }, [ POWER5_PME_PM_LSU_LMQ_S0_ALLOC ] = { -1, -1, 113, 118, -1, -1 }, [ POWER5_PME_PM_LSU0_REJECT_LMQ_FULL ] = { 124, 122, -1, -1, -1, -1 }, [ POWER5_PME_PM_SNOOP_PW_RETRY_RQ ] = { 192, 186, -1, 196, -1, -1 }, [ POWER5_PME_PM_DTLB_REF ] = { -1, 63, -1, -1, -1, -1 }, [ POWER5_PME_PM_PTEG_FROM_L3 ] = { 186, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY ] = { -1, -1, 19, 24, -1, -1 }, [ POWER5_PME_PM_LSU_SRQ_EMPTY_CYC ] = { -1, -1, -1, 122, -1, -1 }, [ POWER5_PME_PM_FPU1_STF ] = { 53, 52, -1, -1, -1, -1 }, [ POWER5_PME_PM_LSU_LMQ_S0_VALID ] = { -1, -1, 114, 119, -1, -1 }, [ POWER5_PME_PM_GCT_USAGE_00to59_CYC ] = { 62, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_DATA_FROM_L2MISS ] = { -1, -1, 187, -1, -1, -1 }, [ POWER5_PME_PM_GRP_DISP_BLK_SB_CYC ] = { -1, -1, 50, 54, -1, -1 }, [ POWER5_PME_PM_FPU_FMOV_FEST ] = { -1, -1, 38, -1, -1, -1 }, [ POWER5_PME_PM_XER_MAP_FULL_CYC ] = { 211, 204, -1, -1, -1, -1 }, [ POWER5_PME_PM_FLUSH_SB ] = { -1, -1, 27, 32, -1, -1 }, [ POWER5_PME_PM_MRK_DATA_FROM_L375_SHR ] = { -1, -1, 132, -1, -1, -1 }, [ POWER5_PME_PM_MRK_GRP_CMPL ] = { -1, -1, -1, 146, -1, -1 }, [ POWER5_PME_PM_SUSPENDED ] = { 200, 194, 168, 174, -1, -1 }, [ POWER5_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC ] = { 68, 205, -1, -1, -1, -1 }, [ POWER5_PME_PM_SNOOP_RD_RETRY_QFULL ] = { 193, 187, -1, -1, -1, -1 }, [ POWER5_PME_PM_L3SB_MOD_INV ] = { -1, -1, 93, 97, -1, -1 }, [ POWER5_PME_PM_DATA_FROM_L35_SHR ] = { 17, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_LD_MISS_L1_LSU1 ] = { -1, -1, 102, 105, -1, -1 }, [ POWER5_PME_PM_STCX_FAIL ] = { 198, 192, -1, -1, -1, -1 }, [ POWER5_PME_PM_DC_PREF_DST ] = { -1, -1, 13, 17, -1, -1 }, [ POWER5_PME_PM_GRP_DISP ] = { -1, 64, -1, -1, -1, -1 }, [ POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR ] = { -1, -1, 64, 68, -1, -1 }, [ POWER5_PME_PM_FPU0_FPSCR ] = { -1, -1, 32, 37, -1, -1 }, [ POWER5_PME_PM_DATA_FROM_L2 ] = { 13, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_FPU1_DENORM ] = { 46, 45, -1, -1, -1, -1 }, [ POWER5_PME_PM_FPU_1FLOP ] = { 56, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER ] = { -1, -1, 81, 85, -1, -1 }, [ POWER5_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL ] = { 102, 100, -1, -1, -1, -1 }, [ POWER5_PME_PM_FPU0_FSQRT ] = { 40, 39, -1, -1, -1, -1 }, [ POWER5_PME_PM_LD_REF_L1 ] = { -1, -1, -1, 106, -1, -1 }, [ POWER5_PME_PM_INST_FROM_L1 ] = { -1, 74, -1, -1, -1, -1 }, [ POWER5_PME_PM_TLBIE_HELD ] = { -1, -1, 186, 191, -1, -1 }, [ POWER5_PME_PM_DC_PREF_OUT_OF_STREAMS ] = { -1, -1, 117, 121, -1, -1 }, [ POWER5_PME_PM_MRK_DATA_FROM_L25_MOD_CYC ] = { -1, -1, -1, 135, -1, -1 }, [ POWER5_PME_PM_MRK_LSU1_FLUSH_SRQ ] = { -1, -1, 144, 155, -1, -1 }, [ POWER5_PME_PM_MEM_RQ_DISP_Q0to3 ] = { 155, 153, -1, -1, -1, -1 }, [ POWER5_PME_PM_ST_REF_L1_LSU1 ] = { -1, -1, 167, 173, -1, -1 }, [ POWER5_PME_PM_MRK_LD_MISS_L1 ] = { 175, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_L1_WRITE_CYC ] = { -1, -1, 62, 66, -1, -1 }, [ POWER5_PME_PM_L2SC_ST_REQ ] = { 105, 103, -1, -1, -1, -1 }, [ POWER5_PME_PM_CMPLU_STALL_FDIV ] = { -1, 11, -1, -1, -1, -1 }, [ POWER5_PME_PM_THRD_SEL_OVER_CLB_EMPTY ] = { -1, -1, 178, 184, -1, -1 }, [ POWER5_PME_PM_BR_MPRED_CR ] = { -1, -1, 1, 2, -1, -1 }, [ POWER5_PME_PM_L3SB_MOD_TAG ] = { 110, 108, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_DATA_FROM_L2MISS ] = { -1, -1, 188, -1, -1, -1 }, [ POWER5_PME_PM_LSU_REJECT_SRQ ] = { 146, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_LD_MISS_L1 ] = { -1, -1, 100, -1, -1, -1 }, [ POWER5_PME_PM_INST_FROM_PREF ] = { -1, -1, 59, -1, -1, -1 }, [ POWER5_PME_PM_DC_INV_L2 ] = { -1, -1, 12, 16, -1, -1 }, [ POWER5_PME_PM_STCX_PASS ] = { 199, 193, -1, -1, -1, -1 }, [ POWER5_PME_PM_LSU_SRQ_FULL_CYC ] = { -1, -1, 118, 123, -1, -1 }, [ POWER5_PME_PM_FPU_FIN ] = { -1, -1, -1, 44, -1, -1 }, [ POWER5_PME_PM_L2SA_SHR_MOD ] = { 88, 86, -1, -1, -1, -1 }, [ POWER5_PME_PM_LSU_SRQ_STFWD ] = { 149, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_0INST_CLB_CYC ] = { 0, 0, -1, -1, -1, -1 }, [ POWER5_PME_PM_FXU0_FIN ] = { -1, -1, 43, 48, -1, -1 }, [ POWER5_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL ] = { 94, 92, -1, -1, -1, -1 }, [ POWER5_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = { -1, 196, -1, -1, -1, -1 }, [ POWER5_PME_PM_PMC5_OVERFLOW ] = { 182, -1, -1, -1, -1, -1 }, [ POWER5_PME_PM_FPU0_FDIV ] = { 38, 37, -1, -1, -1, -1 }, [ POWER5_PME_PM_PTEG_FROM_L375_SHR ] = { -1, -1, 156, -1, -1, -1 }, [ POWER5_PME_PM_LD_REF_L1_LSU1 ] = { -1, -1, 104, 108, -1, -1 }, [ POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY ] = { 87, 85, -1, -1, -1, -1 }, [ POWER5_PME_PM_HV_CYC ] = { -1, 68, -1, -1, -1, -1 }, [ POWER5_PME_PM_THRD_PRIO_DIFF_0_CYC ] = { -1, -1, 171, 177, -1, -1 }, [ POWER5_PME_PM_LR_CTR_MAP_FULL_CYC ] = { 116, 114, -1, -1, -1, -1 }, [ POWER5_PME_PM_L3SB_SHR_INV ] = { -1, -1, 94, 98, -1, -1 }, [ POWER5_PME_PM_DATA_FROM_RMEM ] = { 19, -1, -1, 15, -1, -1 }, [ POWER5_PME_PM_DATA_FROM_L275_MOD ] = { 15, -1, -1, 13, -1, -1 }, [ POWER5_PME_PM_LSU0_REJECT_SRQ ] = { 126, 124, -1, -1, -1, -1 }, [ POWER5_PME_PM_LSU1_DERAT_MISS ] = { 129, 127, -1, -1, -1, -1 }, [ POWER5_PME_PM_MRK_LSU_FIN ] = { -1, -1, -1, 158, -1, -1 }, [ POWER5_PME_PM_DTLB_MISS_16M ] = { 23, 22, -1, -1, -1, -1 }, [ POWER5_PME_PM_LSU0_FLUSH_UST ] = { 122, 120, -1, -1, -1, -1 }, [ POWER5_PME_PM_L2SC_MOD_TAG ] = { 98, 96, -1, -1, -1, -1 }, [ POWER5_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY ] = { 95, 93, -1, -1, -1, -1 } }; static const unsigned long long power5_group_vecs[][POWER5_NUM_GROUP_VEC] = { [ POWER5_PME_PM_LSU_REJECT_RELOAD_CDF ] = { 0x0000000000040000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FPU1_SINGLE ] = { 0x0000000000000000ULL, 0x0000000000400000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L3SB_REF ] = { 0x0000000000000000ULL, 0x0000000000001000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_THRD_PRIO_DIFF_3or4_CYC ] = { 0x0000000000000000ULL, 0x0000000040000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_INST_FROM_L275_SHR ] = { 0x0040000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_DATA_FROM_L375_MOD ] = { 0x0000000000000000ULL, 0x0400000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_DTLB_MISS_4K ] = { 0x0000400000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_CLB_FULL_CYC ] = { 0x0000000000000800ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_ST_CMPL ] = { 0x0000000000000000ULL, 0x4000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU_FLUSH_LRQ_FULL ] = { 0x0000000008000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_DATA_FROM_L275_SHR ] = { 0x0000000000000000ULL, 0x0080000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_1INST_CLB_CYC ] = { 0x0000000000001000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MEM_SPEC_RD_CANCEL ] = { 0x0000000000000000ULL, 0x0000200000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_DTLB_MISS_16M ] = { 0x0000000000000000ULL, 0x0800000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FPU_FDIV ] = { 0x0000000000000000ULL, 0x0000000000004000ULL, 0x0000000000000800ULL }, [ POWER5_PME_PM_FPU_SINGLE ] = { 0x0000000000000000ULL, 0x0000000000020000ULL, 0x0000000000000400ULL }, [ POWER5_PME_PM_FPU0_FMA ] = { 0x0000000000000000ULL, 0x0000000000800000ULL, 0x0000000000000080ULL }, [ POWER5_PME_PM_SLB_MISS ] = { 0x0000010000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU1_FLUSH_LRQ ] = { 0x0000000000400000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L2SA_ST_HIT ] = { 0x4000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_DTLB_MISS ] = { 0x0000080000000000ULL, 0x0000000000000000ULL, 0x0000000000000004ULL }, [ POWER5_PME_PM_BR_PRED_TA ] = { 0x0000020000000000ULL, 0x0000000000000000ULL, 0x0000000000000020ULL }, [ POWER5_PME_PM_MRK_DATA_FROM_L375_MOD_CYC ] = { 0x0000000000000000ULL, 0x0400000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_CMPLU_STALL_FXU ] = { 0x0000000040000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_EXT_INT ] = { 0x0000000000000000ULL, 0x0000400000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_LSU1_FLUSH_LRQ ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU1_LDF ] = { 0x0000000000000000ULL, 0x0000000000400000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_ST_GPS ] = { 0x0000000000000000ULL, 0x8000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FAB_CMD_ISSUED ] = { 0x0000000000000000ULL, 0x0000002000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU0_SRQ_STFWD ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_CR_MAP_FULL_CYC ] = { 0x0000000400000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL ] = { 0x2000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_LSU0_FLUSH_ULD ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU_FLUSH_SRQ_FULL ] = { 0x0000000008000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FLUSH_IMBAL ] = { 0x0000000000084000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MEM_RQ_DISP_Q16to19 ] = { 0x0000000000000000ULL, 0x0000100000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC ] = { 0x0000000000000000ULL, 0x0000000080000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_DATA_FROM_L35_MOD ] = { 0x0008000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MEM_HI_PRIO_WR_CMPL ] = { 0x0000000000000000ULL, 0x0000080000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FPU1_FDIV ] = { 0x0000000000000000ULL, 0x0000000000100000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FPU0_FRSP_FCONV ] = { 0x0000000000000000ULL, 0x0000000000100000ULL, 0x0000000000000080ULL }, [ POWER5_PME_PM_MEM_RQ_DISP ] = { 0x0000000000000000ULL, 0x0000200000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LWSYNC_HELD ] = { 0x0000000000010000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FXU_FIN ] = { 0x0000000000000000ULL, 0x0000000008000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_DSLB_MISS ] = { 0x0000200000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FXLS1_FULL_CYC ] = { 0x0000000200000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_DATA_FROM_L275_SHR ] = { 0x0004000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_THRD_SEL_T0 ] = { 0x0000000000000000ULL, 0x0000000400000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_PTEG_RELOAD_VALID ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU_LMQ_LHR_MERGE ] = { 0x0000000000000200ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_STCX_FAIL ] = { 0x0000000000000000ULL, 0x8000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_2INST_CLB_CYC ] = { 0x0000000000000008ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FAB_PNtoVN_DIRECT ] = { 0x0000000000000000ULL, 0x0000008000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_PTEG_FROM_L2MISS ] = { 0x0400000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_CMPLU_STALL_LSU ] = { 0x0000000010000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_DSLB_MISS ] = { 0x0000000000000000ULL, 0x1800000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU_FLUSH_ULD ] = { 0x0000000001000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_PTEG_FROM_LMEM ] = { 0x0400000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_BRU_FIN ] = { 0x0000000000000000ULL, 0x0008000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MEM_WQ_DISP_WRITE ] = { 0x0000000000000000ULL, 0x0000800000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_DATA_FROM_L275_MOD_CYC ] = { 0x0000000000000000ULL, 0x0200000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU1_NCLD ] = { 0x0000001000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER ] = { 0x1000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_SNOOP_PW_RETRY_WQ_PWQ ] = { 0x0000000000000000ULL, 0x0000100000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FPR_MAP_FULL_CYC ] = { 0x0000000800000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FPU1_FULL_CYC ] = { 0x0000000200000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L3SA_ALL_BUSY ] = { 0x0000000000000000ULL, 0x0000000000000800ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_3INST_CLB_CYC ] = { 0x0000000000000000ULL, 0x0000000010000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MEM_PWQ_DISP_Q2or3 ] = { 0x0000000000000000ULL, 0x0001000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L2SA_SHR_INV ] = { 0x0000000000000000ULL, 0x0000000000000100ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_THRESH_TIMEO ] = { 0x0000000000000000ULL, 0x0002000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL ] = { 0x4000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_THRD_SEL_OVER_GCT_IMBAL ] = { 0x0000000000000000ULL, 0x0000000800000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FPU_FSQRT ] = { 0x0000000000000000ULL, 0x0000000000008000ULL, 0x0000000000000800ULL }, [ POWER5_PME_PM_MRK_LSU0_FLUSH_LRQ ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_PMC1_OVERFLOW ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L3SC_SNOOP_RETRY ] = { 0x0000000000000000ULL, 0x0000000000002000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_DATA_TABLEWALK_CYC ] = { 0x0000080000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_THRD_PRIO_6_CYC ] = { 0x0000000000000000ULL, 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POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL ] = { 0x0000000000000000ULL, 0x0000000000000010ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FPU0_STALL3 ] = { 0x0000000000000000ULL, 0x0000000000200000ULL, 0x0000000000000040ULL }, [ POWER5_PME_PM_GPR_MAP_FULL_CYC ] = { 0x0000000400000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_TB_BIT_TRANS ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_LSU_FLUSH_LRQ ] = { 0x0000000008000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FPU0_STF ] = { 0x0000000000000000ULL, 0x0000000002000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_DTLB_MISS ] = { 0x0000000000000000ULL, 0x0800000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FPU1_FMA ] = { 0x0000000000000000ULL, 0x0000000000800000ULL, 0x0000000000000080ULL }, [ POWER5_PME_PM_L2SA_MOD_TAG ] = { 0x0000000000000000ULL, 0x0000000000000100ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU1_FLUSH_ULD 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0x0000000000000000ULL, 0x0000000000000200ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MEM_LO_PRIO_WR_CMPL ] = { 0x0000000000000000ULL, 0x0000080000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L3SC_MOD_TAG ] = { 0x0000000000000000ULL, 0x0000000000000080ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_ST_MISS_L1 ] = { 0x0000000000000000ULL, 0x4004000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_GRP_DISP_SUCCESS ] = { 0x0800000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_THRD_PRIO_DIFF_1or2_CYC ] = { 0x0000000000000000ULL, 0x0000000020000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = { 0x0000002000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MEM_WQ_DISP_Q8to15 ] = { 0x0000000000000000ULL, 0x0000800000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FPU0_SINGLE ] = { 0x0000000000000000ULL, 0x0000000000400000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU_DERAT_MISS ] = { 0x0000100000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_THRD_PRIO_1_CYC ] = { 0x0000000000000000ULL, 0x0000000100000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L2SC_RCST_DISP_FAIL_OTHER ] = { 0x0000000000000000ULL, 0x0000000000000008ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FPU1_FEST ] = { 0x0000000000000000ULL, 0x0000000000040000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FAB_HOLDtoVN_EMPTY ] = { 0x0000000000000000ULL, 0x0000004000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_SNOOP_RD_RETRY_RQ ] = { 0x0000000000000000ULL, 0x0000040000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_SNOOP_DCLAIM_RETRY_QFULL ] = { 0x0000000000000000ULL, 0x0000020000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_DATA_FROM_L25_SHR_CYC ] = { 0x0000000000000000ULL, 0x0020000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_ST_CMPL_INT ] = { 0x0000000000000000ULL, 0x2000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FLUSH_BR_MPRED ] = { 0x0000040000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR ] = { 0x8000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FPU_STF ] = { 0x0000000000000000ULL, 0x0000000000020000ULL, 0x0000000000002400ULL }, [ POWER5_PME_PM_CMPLU_STALL_FPU ] = { 0x0000000080000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC ] = { 0x0000000000000000ULL, 0x0000000080000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_GCT_NOSLOT_CYC ] = { 0x0000000000000020ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { 0x0000000000000000ULL, 0x0000000004000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_PTEG_FROM_L35_SHR ] = { 0x0200000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_LSU_FLUSH_UST ] = { 0x0000000000000000ULL, 0x4000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L3SA_HIT ] = { 0x0000000000000000ULL, 0x0000000000001000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_DATA_FROM_L25_SHR ] = { 0x0000000000000000ULL, 0x0020000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L2SB_RCST_DISP_FAIL_ADDR ] = { 0x0000000000000000ULL, 0x0000000000000001ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_DATA_FROM_L35_SHR ] = { 0x0000000000000000ULL, 0x0100000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_IERAT_XLATE_WR ] = { 0x0000004000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L2SA_ST_REQ ] = { 0x4000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_THRD_SEL_T1 ] = { 0x0000000000000000ULL, 0x0000000400000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = { 0x0000002000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_INST_FROM_LMEM ] = { 0x0020000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FPU0_1FLOP ] = { 0x0000000000000000ULL, 0x0000000001000000ULL, 0x0000000000000100ULL }, [ POWER5_PME_PM_MRK_DATA_FROM_L35_SHR_CYC ] = { 0x0000000000000000ULL, 0x0100000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_PTEG_FROM_L2 ] = { 0x0400000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MEM_PW_CMPL ] = { 0x0000000000000000ULL, 0x0001000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC ] = { 0x0000000000000000ULL, 0x0000000100000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER ] = { 0x8000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FPU0_FIN ] = { 0x0000000000000000ULL, 0x0000000001010000ULL, 0x0000000000000540ULL }, [ POWER5_PME_PM_MRK_DTLB_MISS_4K ] = { 0x0000000000000000ULL, 0x0800000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L3SC_SHR_INV ] = { 0x0000000000000000ULL, 0x0000000000000080ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_GRP_BR_REDIR ] = { 0x0000040000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL ] = { 0x0000000000000000ULL, 0x0000000000000004ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_LSU_FLUSH_SRQ ] = { 0x0000000000004000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_PTEG_FROM_L275_SHR ] = { 0x0100000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL ] = { 0x8000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_SNOOP_RD_RETRY_WQ ] = { 0x0000000000000000ULL, 0x0000040000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU0_NCLD ] = { 0x0000001000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FAB_DCLAIM_RETRIED ] = { 0x0000000000000000ULL, 0x0000002000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU1_BUSY_REJECT ] = { 0x0000002000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FXLS0_FULL_CYC ] = { 0x0000000200000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FPU0_FEST ] = { 0x0000000000000000ULL, 0x0000000000040000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_DTLB_REF_16M ] = { 0x0000800000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR ] = { 0x0000000000000000ULL, 0x0000000000000004ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU0_REJECT_ERAT_MISS ] = { 0x0000000000010000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_DATA_FROM_L25_MOD ] = { 0x0004000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_GCT_USAGE_60to79_CYC ] = { 0x0000000000000040ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_DATA_FROM_L375_MOD ] = { 0x0008000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { 0x0000000000000200ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU0_REJECT_RELOAD_CDF ] = { 0x0000000000008000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_0INST_FETCH ] = { 0x0020004000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU1_REJECT_RELOAD_CDF ] = { 0x0000000000008000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L1_PREF ] = { 0x0000000000000800ULL, 0x0000000000000000ULL, 0x0000000000000010ULL }, [ POWER5_PME_PM_MEM_WQ_DISP_Q0to7 ] = { 0x0000000000000000ULL, 0x0000800000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_DATA_FROM_LMEM_CYC ] = { 0x0000000000000000ULL, 0x0100000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_BRQ_FULL_CYC ] = { 0x0000000100000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_GRP_IC_MISS_NONSPEC ] = { 0x0000008000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_PTEG_FROM_L275_MOD ] = { 0x0100000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_LD_MISS_L1_LSU0 ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_DATA_FROM_L375_SHR_CYC ] = { 0x0000000000000000ULL, 0x0400000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU_FLUSH ] = { 0x0000000006e40000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_DATA_FROM_L3 ] = { 0x0003000000000000ULL, 0x0000000000000000ULL, 0x000000000000000aULL }, [ POWER5_PME_PM_INST_FROM_L2 ] = { 0x0020000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_PMC2_OVERFLOW ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FPU0_DENORM ] = { 0x0000000000000000ULL, 0x0000000000080000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FPU1_FMOV_FEST ] = { 0x0000000000000000ULL, 0x0000000000080000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_INST_FETCH_CYC ] = { 0x0000000000000400ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU_LDF ] = { 0x0000000000000000ULL, 0x0000000000020000ULL, 0x0000000000002000ULL }, [ POWER5_PME_PM_INST_DISP ] = { 0x0000000000000005ULL, 0x0000000000000000ULL, 0x0000000000002000ULL }, [ POWER5_PME_PM_DATA_FROM_L25_SHR ] = { 0x0004000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L1_DCACHE_RELOAD_VALID ] = { 0x0000008000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MEM_WQ_DISP_DCLAIM ] = { 0x0000000000000000ULL, 0x0000800000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FPU_FULL_CYC ] = { 0x0000000080000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_GRP_ISSUED ] = { 0x0000000000000000ULL, 0x0008000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_THRD_PRIO_3_CYC ] = { 0x0000000000000000ULL, 0x0000000040000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FPU_FMA ] = { 0x0000000000000000ULL, 0x0000000000004000ULL, 0x0000000000010200ULL }, [ POWER5_PME_PM_INST_FROM_L35_MOD ] = { 0x0080000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_CRU_FIN ] = { 0x0000000000000000ULL, 0x2000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_SNOOP_WR_RETRY_WQ ] = { 0x0000000000000000ULL, 0x0000080000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_CMPLU_STALL_REJECT ] = { 0x0000000010000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU1_REJECT_ERAT_MISS ] = { 0x0000000000010000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_FXU_FIN ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000001000ULL }, [ POWER5_PME_PM_L2SB_RCST_DISP_FAIL_OTHER ] = { 0x0000000000000000ULL, 0x0000000000000001ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY ] = { 0x0000000000000000ULL, 0x0000000000000010ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_PMC4_OVERFLOW ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L3SA_SNOOP_RETRY ] = { 0x0000000000000000ULL, 0x0000000000000800ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_PTEG_FROM_L35_MOD ] = { 0x0200000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_INST_FROM_L25_MOD ] = { 0x0040000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_THRD_SMT_HANG ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_CMPLU_STALL_ERAT_MISS ] = { 0x0000000020000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L3SA_MOD_TAG ] = { 0x0000000000000000ULL, 0x0000000000000020ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FLUSH_SYNC ] = { 0x0000000000100000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_INST_FROM_L2MISS ] = { 0x0000000000000400ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L2SC_ST_HIT ] = { 0x0000000000000000ULL, 0x0000000000000010ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MEM_RQ_DISP_Q8to11 ] = { 0x0000000000000000ULL, 0x0000400000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_GRP_DISP ] = { 0x0000000000000000ULL, 0x0006000008000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L2SB_MOD_TAG ] = { 0x0000000000000000ULL, 0x0000000000000200ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_CLB_EMPTY_CYC ] = { 0x0000000000000008ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L2SB_ST_HIT ] = { 0x0000000000000000ULL, 0x0000000000000002ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MEM_NONSPEC_RD_CANCEL ] = { 0x0000000000000000ULL, 0x0000200000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_BR_PRED_CR_TA ] = { 0x0000020000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_LSU0_FLUSH_SRQ ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_LSU_FLUSH_ULD ] = { 0x0000000000000000ULL, 0x4000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_INST_DISP_ATTEMPT ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000004000ULL }, [ POWER5_PME_PM_INST_FROM_RMEM ] = { 0x0010000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_ST_REF_L1_LSU0 ] = { 0x0000800000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU0_DERAT_MISS ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L2SB_RCLD_DISP ] = { 0x8000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FPU_STALL3 ] = { 0x0000000000000000ULL, 0x0000000000010000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_BR_PRED_CR ] = { 0x0000020000000000ULL, 0x0000000000000000ULL, 0x0000000000000020ULL }, [ POWER5_PME_PM_MRK_DATA_FROM_L2 ] = { 0x0000000000000000ULL, 0x0010000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU0_FLUSH_SRQ ] = { 0x0000000000800000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FAB_PNtoNN_DIRECT ] = { 0x0000000000000000ULL, 0x0000008000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_IOPS_CMPL ] = { 0x00210488fffa9811ULL, 0x3220041f03a200e0ULL, 0x0000000000010000ULL }, [ POWER5_PME_PM_L2SC_SHR_INV ] = { 0x0000000000000000ULL, 0x0000000000000400ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L2SA_RCST_DISP_FAIL_OTHER ] = { 0x2000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L2SA_RCST_DISP ] = { 0x2000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_SNOOP_RETRY_AB_COLLISION ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FAB_PNtoVN_SIDECAR ] = { 0x0000000000000000ULL, 0x0000008000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU_LMQ_S0_ALLOC ] = { 0x0000000000000080ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU0_REJECT_LMQ_FULL ] = { 0x0000000000020000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_SNOOP_PW_RETRY_RQ ] = { 0x0000000000000000ULL, 0x0000100000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_DTLB_REF ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_PTEG_FROM_L3 ] = { 0x0800000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY ] = { 0x0000000000000000ULL, 0x0000010000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU_SRQ_EMPTY_CYC ] = { 0x0000000000000200ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FPU1_STF ] = { 0x0000000000000000ULL, 0x0000000002000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU_LMQ_S0_VALID ] = { 0x0000000000000080ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_GCT_USAGE_00to59_CYC ] = { 0x0000000000000040ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_DATA_FROM_L2MISS ] = { 0x0002000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_GRP_DISP_BLK_SB_CYC ] = { 0x0000000000000004ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FPU_FMOV_FEST ] = { 0x0000000000000000ULL, 0x0000000000004000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_XER_MAP_FULL_CYC ] = { 0x0000000800000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FLUSH_SB ] = { 0x0000000000100000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_DATA_FROM_L375_SHR ] = { 0x0000000000000000ULL, 0x0400000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_GRP_CMPL ] = { 0x0000000000000000ULL, 0x0004000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_SUSPENDED ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC ] = { 0x0000000040000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_SNOOP_RD_RETRY_QFULL ] = { 0x0000000000000000ULL, 0x0000020000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L3SB_MOD_INV ] = { 0x0000000000000000ULL, 0x0000000000000040ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_DATA_FROM_L35_SHR ] = { 0x0008000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LD_MISS_L1_LSU1 ] = { 0x0000200000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_STCX_FAIL ] = { 0x0000001000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_DC_PREF_DST ] = { 0x0000000000002000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_GRP_DISP ] = { 0x0800000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR ] = { 0x1000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FPU0_FPSCR ] = { 0x0000000000000000ULL, 0x0000000000200000ULL, 0x0000000000000040ULL }, [ POWER5_PME_PM_DATA_FROM_L2 ] = { 0x0000100000000000ULL, 0x0000000000000000ULL, 0x0000000000000001ULL }, [ POWER5_PME_PM_FPU1_DENORM ] = { 0x0000000000000000ULL, 0x0000000000080000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FPU_1FLOP ] = { 0x0000000000000000ULL, 0x0000000000008000ULL, 0x0000000000010200ULL }, [ POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER ] = { 0x0000000000000000ULL, 0x0000000000000004ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL ] = { 0x0000000000000000ULL, 0x0000000000000008ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FPU0_FSQRT ] = { 0x0000000000000000ULL, 0x0000000000040000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LD_REF_L1 ] = { 0x0000080000000000ULL, 0x0000000000000000ULL, 0x0000000000008207ULL }, [ POWER5_PME_PM_INST_FROM_L1 ] = { 0x0010000000000000ULL, 0x0000000000000000ULL, 0x0000000000000001ULL }, [ POWER5_PME_PM_TLBIE_HELD ] = { 0x0000000000010000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_DC_PREF_OUT_OF_STREAMS ] = { 0x0000000000000400ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_DATA_FROM_L25_MOD_CYC ] = { 0x0000000000000000ULL, 0x0010000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_LSU1_FLUSH_SRQ ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MEM_RQ_DISP_Q0to3 ] = { 0x0000000000000000ULL, 0x0000400000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_ST_REF_L1_LSU1 ] = { 0x0000800000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_LD_MISS_L1 ] = { 0x0000000000000000ULL, 0x2000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L1_WRITE_CYC ] = { 0x0000000000008000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L2SC_ST_REQ ] = { 0x0000000000000000ULL, 0x0000000000000010ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_CMPLU_STALL_FDIV ] = { 0x0000000080000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_THRD_SEL_OVER_CLB_EMPTY ] = { 0x0000000000000000ULL, 0x0000000800000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_BR_MPRED_CR ] = { 0x0000010000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L3SB_MOD_TAG ] = { 0x0000000000000000ULL, 0x0000000000000040ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_DATA_FROM_L2MISS ] = { 0x0000000800000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU_REJECT_SRQ ] = { 0x0000000000040000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LD_MISS_L1 ] = { 0x0000080000000000ULL, 0x0000000000000000ULL, 0x0000000000004008ULL }, [ POWER5_PME_PM_INST_FROM_PREF ] = { 0x0010000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_DC_INV_L2 ] = { 0x0800000000080000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_STCX_PASS ] = { 0x0000001000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU_SRQ_FULL_CYC ] = { 0x0000000000000100ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FPU_FIN ] = { 0x0000000000000000ULL, 0x0020000000008000ULL, 0x0000000000001800ULL }, [ POWER5_PME_PM_L2SA_SHR_MOD ] = { 0x0000000000000000ULL, 0x0000000000000100ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU_SRQ_STFWD ] = { 0x0000000000000200ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_0INST_CLB_CYC ] = { 0x0000000000000008ULL, 0x0000000800000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FXU0_FIN ] = { 0x0000000000000000ULL, 0x0000000010000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL ] = { 0x0000000000000000ULL, 0x0000000000000001ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = { 0x0000000000000000ULL, 0x0000000200000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_PMC5_OVERFLOW ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_FPU0_FDIV ] = { 0x0000000000000000ULL, 0x0000000000100000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_PTEG_FROM_L375_SHR ] = { 0x0200000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LD_REF_L1_LSU1 ] = { 0x0000400000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY ] = { 0x4000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_HV_CYC ] = { 0x0000000000000000ULL, 0x0000000100000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_THRD_PRIO_DIFF_0_CYC ] = { 0x0000000000000000ULL, 0x0000000020000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LR_CTR_MAP_FULL_CYC ] = { 0x0000000400000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L3SB_SHR_INV ] = { 0x0000000000000000ULL, 0x0000000000000040ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_DATA_FROM_RMEM ] = { 0x0002000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_DATA_FROM_L275_MOD ] = { 0x0004000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU0_REJECT_SRQ ] = { 0x0000000000002000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU1_DERAT_MISS ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_MRK_LSU_FIN ] = { 0x0000000000000000ULL, 0x0002000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_DTLB_MISS_16M ] = { 0x0000800000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_LSU0_FLUSH_UST ] = { 0x0000000004000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L2SC_MOD_TAG ] = { 0x0000000000000000ULL, 0x0000000000000400ULL, 0x0000000000000000ULL }, [ POWER5_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY ] = { 0x0000000000000000ULL, 0x0000000000000002ULL, 0x0000000000000000ULL } }; static const pme_power_entry_t power5_pe[] = { [ POWER5_PME_PM_LSU_REJECT_RELOAD_CDF ] = { .pme_name = "PM_LSU_REJECT_RELOAD_CDF", .pme_code = 0x2c6090, .pme_short_desc = "LSU reject due to reload CDF or tag update collision", .pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions because of Critical Data Forward. When critical data arrives from the storage system it is formatted and immediately forwarded, bypassing the data cache, to the destination register using the result bus. Any instruction the requires the result bus in the same cycle is rejected. Tag update rejects are caused when an instruction requires access to the Dcache directory or ERAT in the same system when they are being updated. Combined Unit 0 + 1.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_REJECT_RELOAD_CDF], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_REJECT_RELOAD_CDF] }, [ POWER5_PME_PM_FPU1_SINGLE ] = { .pme_name = "PM_FPU1_SINGLE", .pme_code = 0x20e7, .pme_short_desc = "FPU1 executed single precision instruction", .pme_long_desc = "FPU1 has executed a single precision instruction.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU1_SINGLE], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU1_SINGLE] }, [ POWER5_PME_PM_L3SB_REF ] = { .pme_name = "PM_L3SB_REF", .pme_code = 0x701c4, .pme_short_desc = "L3 slice B references", .pme_long_desc = "Number of attempts made by this chip cores to find data in the L3. Reported per L3 slice ", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SB_REF], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SB_REF] }, [ POWER5_PME_PM_THRD_PRIO_DIFF_3or4_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_3or4_CYC", .pme_code = 0x430e5, .pme_short_desc = "Cycles thread priority difference is 3 or 4", .pme_long_desc = "Cycles when this thread's priority is higher than the other thread's priority by 3 or 4.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_PRIO_DIFF_3or4_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_PRIO_DIFF_3or4_CYC] }, [ POWER5_PME_PM_INST_FROM_L275_SHR ] = { .pme_name = "PM_INST_FROM_L275_SHR", .pme_code = 0x322096, .pme_short_desc = "Instruction fetched from L2.75 shared", .pme_long_desc = "An instruction fetch group was fetched with shared (T) data from the L2 on a different module than this processor is located. Fetch groups can contain up to 8 instructions", .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_L275_SHR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_L275_SHR] }, [ POWER5_PME_PM_MRK_DATA_FROM_L375_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L375_MOD", .pme_code = 0x1c70a7, .pme_short_desc = "Marked data loaded from L3.75 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L3 of a chip on a different module than this processor is located due to a marked load.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L375_MOD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L375_MOD] }, [ POWER5_PME_PM_DTLB_MISS_4K ] = { .pme_name = "PM_DTLB_MISS_4K", .pme_code = 0xc40c0, .pme_short_desc = "Data TLB miss for 4K page", .pme_long_desc = "Data TLB references to 4KB pages that missed the TLB. Page size is determined at TLB reload time.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_DTLB_MISS_4K], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DTLB_MISS_4K] }, [ POWER5_PME_PM_CLB_FULL_CYC ] = { .pme_name = "PM_CLB_FULL_CYC", .pme_code = 0x220e5, .pme_short_desc = "Cycles CLB full", .pme_long_desc = "Cycles when both thread's CLB is full.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_CLB_FULL_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_CLB_FULL_CYC] }, [ POWER5_PME_PM_MRK_ST_CMPL ] = { .pme_name = "PM_MRK_ST_CMPL", .pme_code = 0x100003, .pme_short_desc = "Marked store instruction completed", .pme_long_desc = "A sampled store has completed (data home)", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_ST_CMPL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_ST_CMPL] }, [ POWER5_PME_PM_LSU_FLUSH_LRQ_FULL ] = { .pme_name = "PM_LSU_FLUSH_LRQ_FULL", .pme_code = 0x320e7, .pme_short_desc = "Flush caused by LRQ full", .pme_long_desc = "This thread was flushed at dispatch because its Load Request Queue was full. This allows the other thread to have more machine resources for it to make progress while this thread is stalled.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_FLUSH_LRQ_FULL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_FLUSH_LRQ_FULL] }, [ POWER5_PME_PM_MRK_DATA_FROM_L275_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L275_SHR", .pme_code = 0x3c7097, .pme_short_desc = "Marked data loaded from L2.75 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (T) data from the L2 on a different module than this processor is located due to a marked load.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L275_SHR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L275_SHR] }, [ POWER5_PME_PM_1INST_CLB_CYC ] = { .pme_name = "PM_1INST_CLB_CYC", .pme_code = 0x400c1, .pme_short_desc = "Cycles 1 instruction in CLB", .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_1INST_CLB_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_1INST_CLB_CYC] }, [ POWER5_PME_PM_MEM_SPEC_RD_CANCEL ] = { .pme_name = "PM_MEM_SPEC_RD_CANCEL", .pme_code = 0x721e6, .pme_short_desc = "Speculative memory read cancelled", .pme_long_desc = "Speculative memory read cancelled (i.e. cresp = sourced by L2/L3)", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_SPEC_RD_CANCEL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_SPEC_RD_CANCEL] }, [ POWER5_PME_PM_MRK_DTLB_MISS_16M ] = { .pme_name = "PM_MRK_DTLB_MISS_16M", .pme_code = 0xc40c5, .pme_short_desc = "Marked Data TLB misses for 16M page", .pme_long_desc = "Marked Data TLB misses for 16M page", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DTLB_MISS_16M], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DTLB_MISS_16M] }, [ POWER5_PME_PM_FPU_FDIV ] = { .pme_name = "PM_FPU_FDIV", .pme_code = 0x100088, .pme_short_desc = "FPU executed FDIV instruction", .pme_long_desc = "The floating point unit has executed a divide instruction. This could be fdiv, fdivs, fdiv., fdivs.. Combined Unit 0 + Unit 1.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU_FDIV], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU_FDIV] }, [ POWER5_PME_PM_FPU_SINGLE ] = { .pme_name = "PM_FPU_SINGLE", .pme_code = 0x102090, .pme_short_desc = "FPU executed single precision instruction", .pme_long_desc = "FPU is executing single precision instruction. Combined Unit 0 + Unit 1.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU_SINGLE], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU_SINGLE] }, [ POWER5_PME_PM_FPU0_FMA ] = { .pme_name = "PM_FPU0_FMA", .pme_code = 0xc1, .pme_short_desc = "FPU0 executed multiply-add instruction", .pme_long_desc = "The floating point unit has executed a multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU0_FMA], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU0_FMA] }, [ POWER5_PME_PM_SLB_MISS ] = { .pme_name = "PM_SLB_MISS", .pme_code = 0x280088, .pme_short_desc = "SLB misses", .pme_long_desc = "Total of all Segment Lookaside Buffer (SLB) misses, Instructions + Data.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_SLB_MISS], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SLB_MISS] }, [ POWER5_PME_PM_LSU1_FLUSH_LRQ ] = { .pme_name = "PM_LSU1_FLUSH_LRQ", .pme_code = 0xc00c6, .pme_short_desc = "LSU1 LRQ flushes", .pme_long_desc = "A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU1_FLUSH_LRQ], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU1_FLUSH_LRQ] }, [ POWER5_PME_PM_L2SA_ST_HIT ] = { .pme_name = "PM_L2SA_ST_HIT", .pme_code = 0x733e0, .pme_short_desc = "L2 slice A store hits", .pme_long_desc = "A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A, B, and C.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_ST_HIT], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_ST_HIT] }, [ POWER5_PME_PM_DTLB_MISS ] = { .pme_name = "PM_DTLB_MISS", .pme_code = 0x800c4, .pme_short_desc = "Data TLB misses", .pme_long_desc = "Data TLB misses, all page sizes.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_DTLB_MISS], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DTLB_MISS] }, [ POWER5_PME_PM_BR_PRED_TA ] = { .pme_name = "PM_BR_PRED_TA", .pme_code = 0x230e3, .pme_short_desc = "A conditional branch was predicted", .pme_long_desc = " target prediction", .pme_event_ids = power5_event_ids[POWER5_PME_PM_BR_PRED_TA], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_BR_PRED_TA] }, [ POWER5_PME_PM_MRK_DATA_FROM_L375_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L375_MOD_CYC", .pme_code = 0x4c70a7, .pme_short_desc = "Marked load latency from L3.75 modified", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L375_MOD_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L375_MOD_CYC] }, [ POWER5_PME_PM_CMPLU_STALL_FXU ] = { .pme_name = "PM_CMPLU_STALL_FXU", .pme_code = 0x211099, .pme_short_desc = "Completion stall caused by FXU instruction", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point instruction.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_CMPLU_STALL_FXU], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_CMPLU_STALL_FXU] }, [ POWER5_PME_PM_EXT_INT ] = { .pme_name = "PM_EXT_INT", .pme_code = 0x400003, .pme_short_desc = "External interrupts", .pme_long_desc = "An interrupt due to an external exception occurred", .pme_event_ids = power5_event_ids[POWER5_PME_PM_EXT_INT], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_EXT_INT] }, [ POWER5_PME_PM_MRK_LSU1_FLUSH_LRQ ] = { .pme_name = "PM_MRK_LSU1_FLUSH_LRQ", .pme_code = 0x810c6, .pme_short_desc = "LSU1 marked LRQ flushes", .pme_long_desc = "A marked load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LSU1_FLUSH_LRQ], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LSU1_FLUSH_LRQ] }, [ POWER5_PME_PM_LSU1_LDF ] = { .pme_name = "PM_LSU1_LDF", .pme_code = 0xc50c4, .pme_short_desc = "LSU1 executed Floating Point load instruction", .pme_long_desc = "A floating point load was executed by LSU1", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU1_LDF], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU1_LDF] }, [ POWER5_PME_PM_MRK_ST_GPS ] = { .pme_name = "PM_MRK_ST_GPS", .pme_code = 0x200003, .pme_short_desc = "Marked store sent to GPS", .pme_long_desc = "A sampled store has been sent to the memory subsystem", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_ST_GPS], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_ST_GPS] }, [ POWER5_PME_PM_FAB_CMD_ISSUED ] = { .pme_name = "PM_FAB_CMD_ISSUED", .pme_code = 0x700c7, .pme_short_desc = "Fabric command issued", .pme_long_desc = "Incremented when a chip issues a command on its SnoopA address bus. Each of the two address busses (SnoopA and SnoopB) is capable of one transaction per fabric cycle (one fabric cycle = 2 cpu cycles in normal 2:1 mode), but each chip can only drive the SnoopA bus, and can only drive one transaction every two fabric cycles (i.e., every four cpu cycles). In MCM-based systems, two chips interleave their accesses to each of the two fabric busses (SnoopA, SnoopB) to reach a peak capability of one transaction per cpu clock cycle. The two chips that drive SnoopB are wired so that the chips refer to the bus as SnoopA but it is connected to the other two chips as SnoopB. Note that this event will only be recorded by the FBC on the chip that sourced the operation. The signal is delivered at FBC speed and the count must be scaled.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_CMD_ISSUED], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_CMD_ISSUED] }, [ POWER5_PME_PM_LSU0_SRQ_STFWD ] = { .pme_name = "PM_LSU0_SRQ_STFWD", .pme_code = 0xc20e0, .pme_short_desc = "LSU0 SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load on unit 0. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU0_SRQ_STFWD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU0_SRQ_STFWD] }, [ POWER5_PME_PM_CR_MAP_FULL_CYC ] = { .pme_name = "PM_CR_MAP_FULL_CYC", .pme_code = 0x100c4, .pme_short_desc = "Cycles CR logical operation mapper full", .pme_long_desc = "The Conditional Register mapper cannot accept any more groups. This condition will prevent dispatch groups from being dispatched. This event only indicates that the mapper was full, not that dispatch was prevented.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_CR_MAP_FULL_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_CR_MAP_FULL_CYC] }, [ POWER5_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL ] = { .pme_name = "PM_L2SA_RCST_DISP_FAIL_RC_FULL", .pme_code = 0x722e0, .pme_short_desc = "L2 slice A RC store dispatch attempt failed due to all RC full", .pme_long_desc = "A Read/Claim dispatch for a store failed because all RC machines are busy.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_RCST_DISP_FAIL_RC_FULL] }, [ POWER5_PME_PM_MRK_LSU0_FLUSH_ULD ] = { .pme_name = "PM_MRK_LSU0_FLUSH_ULD", .pme_code = 0x810c0, .pme_short_desc = "LSU0 marked unaligned load flushes", .pme_long_desc = "A marked load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LSU0_FLUSH_ULD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LSU0_FLUSH_ULD] }, [ POWER5_PME_PM_LSU_FLUSH_SRQ_FULL ] = { .pme_name = "PM_LSU_FLUSH_SRQ_FULL", .pme_code = 0x330e0, .pme_short_desc = "Flush caused by SRQ full", .pme_long_desc = "This thread was flushed at dispatch because its Store Request Queue was full. This allows the other thread to have more machine resources for it to make progress while this thread is stalled.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_FLUSH_SRQ_FULL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_FLUSH_SRQ_FULL] }, [ POWER5_PME_PM_FLUSH_IMBAL ] = { .pme_name = "PM_FLUSH_IMBAL", .pme_code = 0x330e3, .pme_short_desc = "Flush caused by thread GCT imbalance", .pme_long_desc = "This thread has been flushed at dispatch because it is stalled and a GCT imbalance exists. GCT thresholds are set in the TSCR register. This allows the other thread to have more machine resources for it to make progress while this thread is stalled.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FLUSH_IMBAL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FLUSH_IMBAL] }, [ POWER5_PME_PM_MEM_RQ_DISP_Q16to19 ] = { .pme_name = "PM_MEM_RQ_DISP_Q16to19", .pme_code = 0x727e6, .pme_short_desc = "Memory read queue dispatched to queues 16-19", .pme_long_desc = "A memory operation was dispatched to read queue 16,17,18 or 19. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_RQ_DISP_Q16to19], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_RQ_DISP_Q16to19] }, [ POWER5_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_minus3or4_CYC", .pme_code = 0x430e1, .pme_short_desc = "Cycles thread priority difference is -3 or -4", .pme_long_desc = "Cycles when this thread's priority is lower than the other thread's priority by 3 or 4.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_PRIO_DIFF_minus3or4_CYC] }, [ POWER5_PME_PM_DATA_FROM_L35_MOD ] = { .pme_name = "PM_DATA_FROM_L35_MOD", .pme_code = 0x2c309e, .pme_short_desc = "Data loaded from L3.5 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L3 of a chip on the same module as this processor is located due to a demand load.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_DATA_FROM_L35_MOD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DATA_FROM_L35_MOD] }, [ POWER5_PME_PM_MEM_HI_PRIO_WR_CMPL ] = { .pme_name = "PM_MEM_HI_PRIO_WR_CMPL", .pme_code = 0x726e6, .pme_short_desc = "High priority write completed", .pme_long_desc = "A memory write, which was upgraded to high priority, completed. Writes can be upgraded to high priority to ensure that read traffic does not lock out writes. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_HI_PRIO_WR_CMPL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_HI_PRIO_WR_CMPL] }, [ POWER5_PME_PM_FPU1_FDIV ] = { .pme_name = "PM_FPU1_FDIV", .pme_code = 0xc4, .pme_short_desc = "FPU1 executed FDIV instruction", .pme_long_desc = "FPU1 has executed a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU1_FDIV], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU1_FDIV] }, [ POWER5_PME_PM_FPU0_FRSP_FCONV ] = { .pme_name = "PM_FPU0_FRSP_FCONV", .pme_code = 0x10c1, .pme_short_desc = "FPU0 executed FRSP or FCONV instructions", .pme_long_desc = "FPU0 has executed a frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU0_FRSP_FCONV], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU0_FRSP_FCONV] }, [ POWER5_PME_PM_MEM_RQ_DISP ] = { .pme_name = "PM_MEM_RQ_DISP", .pme_code = 0x701c6, .pme_short_desc = "Memory read queue dispatched", .pme_long_desc = "A memory read was dispatched. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_RQ_DISP], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_RQ_DISP] }, [ POWER5_PME_PM_LWSYNC_HELD ] = { .pme_name = "PM_LWSYNC_HELD", .pme_code = 0x130e0, .pme_short_desc = "LWSYNC held at dispatch", .pme_long_desc = "Cycles a LWSYNC instruction was held at dispatch. LWSYNC instructions are held at dispatch until all previous loads are done and all previous stores have issued. LWSYNC enters the Store Request Queue and is sent to the storage subsystem but does not wait for a response.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LWSYNC_HELD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LWSYNC_HELD] }, [ POWER5_PME_PM_FXU_FIN ] = { .pme_name = "PM_FXU_FIN", .pme_code = 0x313088, .pme_short_desc = "FXU produced a result", .pme_long_desc = "The fixed point unit (Unit 0 + Unit 1) finished an instruction. Instructions that finish may not necessary complete.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FXU_FIN], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FXU_FIN] }, [ POWER5_PME_PM_DSLB_MISS ] = { .pme_name = "PM_DSLB_MISS", .pme_code = 0x800c5, .pme_short_desc = "Data SLB misses", .pme_long_desc = "A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_DSLB_MISS], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DSLB_MISS] }, [ POWER5_PME_PM_FXLS1_FULL_CYC ] = { .pme_name = "PM_FXLS1_FULL_CYC", .pme_code = 0x110c4, .pme_short_desc = "Cycles FXU1/LS1 queue full", .pme_long_desc = "The issue queue that feeds the Fixed Point unit 1 / Load Store Unit 1 is full. This condition will prevent dispatch groups from being dispatched. This event only indicates that the queue was full, not that dispatch was prevented.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FXLS1_FULL_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FXLS1_FULL_CYC] }, [ POWER5_PME_PM_DATA_FROM_L275_SHR ] = { .pme_name = "PM_DATA_FROM_L275_SHR", .pme_code = 0x3c3097, .pme_short_desc = "Data loaded from L2.75 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (T) data from the L2 on a different module than this processor is located due to a demand load. ", .pme_event_ids = power5_event_ids[POWER5_PME_PM_DATA_FROM_L275_SHR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DATA_FROM_L275_SHR] }, [ POWER5_PME_PM_THRD_SEL_T0 ] = { .pme_name = "PM_THRD_SEL_T0", .pme_code = 0x410c0, .pme_short_desc = "Decode selected thread 0", .pme_long_desc = "Thread selection picked thread 0 for decode.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_SEL_T0], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_SEL_T0] }, [ POWER5_PME_PM_PTEG_RELOAD_VALID ] = { .pme_name = "PM_PTEG_RELOAD_VALID", .pme_code = 0x830e4, .pme_short_desc = "PTEG reload valid", .pme_long_desc = "A Page Table Entry was loaded into the TLB.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_PTEG_RELOAD_VALID], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PTEG_RELOAD_VALID] }, [ POWER5_PME_PM_LSU_LMQ_LHR_MERGE ] = { .pme_name = "PM_LSU_LMQ_LHR_MERGE", .pme_code = 0xc70e5, .pme_short_desc = "LMQ LHR merges", .pme_long_desc = "A data cache miss occurred for the same real cache line address as an earlier request already in the Load Miss Queue and was merged into the LMQ entry.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_LMQ_LHR_MERGE], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_LMQ_LHR_MERGE] }, [ POWER5_PME_PM_MRK_STCX_FAIL ] = { .pme_name = "PM_MRK_STCX_FAIL", .pme_code = 0x820e6, .pme_short_desc = "Marked STCX failed", .pme_long_desc = "A marked stcx (stwcx or stdcx) failed", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_STCX_FAIL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_STCX_FAIL] }, [ POWER5_PME_PM_2INST_CLB_CYC ] = { .pme_name = "PM_2INST_CLB_CYC", .pme_code = 0x400c2, .pme_short_desc = "Cycles 2 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_2INST_CLB_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_2INST_CLB_CYC] }, [ POWER5_PME_PM_FAB_PNtoVN_DIRECT ] = { .pme_name = "PM_FAB_PNtoVN_DIRECT", .pme_code = 0x723e7, .pme_short_desc = "PN to VN beat went straight to its destination", .pme_long_desc = "Fabric Data beats that the base chip takes the inbound PN data and passes it through to the outbound VN bus without going into a sidecar. The signal is delivered at FBC speed and the count must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_PNtoVN_DIRECT], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_PNtoVN_DIRECT] }, [ POWER5_PME_PM_PTEG_FROM_L2MISS ] = { .pme_name = "PM_PTEG_FROM_L2MISS", .pme_code = 0x38309b, .pme_short_desc = "PTEG loaded from L2 miss", .pme_long_desc = "A Page Table Entry was loaded into the TLB but not from the local L2.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_PTEG_FROM_L2MISS], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PTEG_FROM_L2MISS] }, [ POWER5_PME_PM_CMPLU_STALL_LSU ] = { .pme_name = "PM_CMPLU_STALL_LSU", .pme_code = 0x211098, .pme_short_desc = "Completion stall caused by LSU instruction", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a load/store instruction.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_CMPLU_STALL_LSU], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_CMPLU_STALL_LSU] }, [ POWER5_PME_PM_MRK_DSLB_MISS ] = { .pme_name = "PM_MRK_DSLB_MISS", .pme_code = 0xc50c7, .pme_short_desc = "Marked Data SLB misses", .pme_long_desc = "A Data SLB miss was caused by a marked instruction.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DSLB_MISS], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DSLB_MISS] }, [ POWER5_PME_PM_LSU_FLUSH_ULD ] = { .pme_name = "PM_LSU_FLUSH_ULD", .pme_code = 0x1c0088, .pme_short_desc = "LRQ unaligned load flushes", .pme_long_desc = "A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1). Combined Unit 0 + 1.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_FLUSH_ULD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_FLUSH_ULD] }, [ POWER5_PME_PM_PTEG_FROM_LMEM ] = { .pme_name = "PM_PTEG_FROM_LMEM", .pme_code = 0x283087, .pme_short_desc = "PTEG loaded from local memory", .pme_long_desc = "A Page Table Entry was loaded into the TLB from memory attached to the same module this proccessor is located on.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_PTEG_FROM_LMEM], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PTEG_FROM_LMEM] }, [ POWER5_PME_PM_MRK_BRU_FIN ] = { .pme_name = "PM_MRK_BRU_FIN", .pme_code = 0x200005, .pme_short_desc = "Marked instruction BRU processing finished", .pme_long_desc = "The branch unit finished a marked instruction. Instructions that finish may not necessary complete.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_BRU_FIN], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_BRU_FIN] }, [ POWER5_PME_PM_MEM_WQ_DISP_WRITE ] = { .pme_name = "PM_MEM_WQ_DISP_WRITE", .pme_code = 0x703c6, .pme_short_desc = "Memory write queue dispatched due to write", .pme_long_desc = "A memory write was dispatched to a write queue. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_WQ_DISP_WRITE], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_WQ_DISP_WRITE] }, [ POWER5_PME_PM_MRK_DATA_FROM_L275_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L275_MOD_CYC", .pme_code = 0x4c70a3, .pme_short_desc = "Marked load latency from L2.75 modified", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L275_MOD_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L275_MOD_CYC] }, [ POWER5_PME_PM_LSU1_NCLD ] = { .pme_name = "PM_LSU1_NCLD", .pme_code = 0xc50c5, .pme_short_desc = "LSU1 non-cacheable loads", .pme_long_desc = "A non-cacheable load was executed by Unit 0.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU1_NCLD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU1_NCLD] }, [ POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2SA_RCLD_DISP_FAIL_OTHER", .pme_code = 0x731e0, .pme_short_desc = "L2 slice A RC load dispatch attempt failed due to other reasons", .pme_long_desc = "A Read/Claim dispatch for a load failed for some reason other than Full or Collision conditions.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_OTHER] }, [ POWER5_PME_PM_SNOOP_PW_RETRY_WQ_PWQ ] = { .pme_name = "PM_SNOOP_PW_RETRY_WQ_PWQ", .pme_code = 0x717c6, .pme_short_desc = "Snoop partial-write retry due to collision with active write or partial-write queue", .pme_long_desc = "A snoop request for a partial write to memory was retried because it matched the cache line of an active write or partial write. When this happens the snoop request is retried and the active write is changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_SNOOP_PW_RETRY_WQ_PWQ], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SNOOP_PW_RETRY_WQ_PWQ] }, [ POWER5_PME_PM_FPR_MAP_FULL_CYC ] = { .pme_name = "PM_FPR_MAP_FULL_CYC", .pme_code = 0x100c1, .pme_short_desc = "Cycles FPR mapper full", .pme_long_desc = "The floating point unit has executed an add, mult, sub, compare, fsel, fneg, fabs, fnabs, fres, or frsqrte kind of instruction. These are single FLOP operations. ", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPR_MAP_FULL_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPR_MAP_FULL_CYC] }, [ POWER5_PME_PM_FPU1_FULL_CYC ] = { .pme_name = "PM_FPU1_FULL_CYC", .pme_code = 0x100c7, .pme_short_desc = "Cycles FPU1 issue queue full", .pme_long_desc = "The issue queue for FPU1 cannot accept any more instructions. Dispatch to this issue queue is stopped", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU1_FULL_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU1_FULL_CYC] }, [ POWER5_PME_PM_L3SA_ALL_BUSY ] = { .pme_name = "PM_L3SA_ALL_BUSY", .pme_code = 0x721e3, .pme_short_desc = "L3 slice A active for every cycle all CI/CO machines busy", .pme_long_desc = "Cycles All Castin/Castout machines are busy.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SA_ALL_BUSY], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SA_ALL_BUSY] }, [ POWER5_PME_PM_3INST_CLB_CYC ] = { .pme_name = "PM_3INST_CLB_CYC", .pme_code = 0x400c3, .pme_short_desc = "Cycles 3 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_3INST_CLB_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_3INST_CLB_CYC] }, [ POWER5_PME_PM_MEM_PWQ_DISP_Q2or3 ] = { .pme_name = "PM_MEM_PWQ_DISP_Q2or3", .pme_code = 0x734e6, .pme_short_desc = "Memory partial-write queue dispatched to Write Queue 2 or 3", .pme_long_desc = "Memory partial-write queue dispatched to Write Queue 2 or 3. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_PWQ_DISP_Q2or3], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_PWQ_DISP_Q2or3] }, [ POWER5_PME_PM_L2SA_SHR_INV ] = { .pme_name = "PM_L2SA_SHR_INV", .pme_code = 0x710c0, .pme_short_desc = "L2 slice A transition from shared to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A, B, and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_SHR_INV], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_SHR_INV] }, [ POWER5_PME_PM_THRESH_TIMEO ] = { .pme_name = "PM_THRESH_TIMEO", .pme_code = 0x30000b, .pme_short_desc = "Threshold timeout", .pme_long_desc = "The threshold timer expired", .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRESH_TIMEO], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRESH_TIMEO] }, [ POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL ] = { .pme_name = "PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL", .pme_code = 0x713c0, .pme_short_desc = "L2 slice A RC dispatch attempt failed due to all CO busy", .pme_long_desc = "A Read/Claim dispatch was rejected because all Castout machines were busy.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL] }, [ POWER5_PME_PM_THRD_SEL_OVER_GCT_IMBAL ] = { .pme_name = "PM_THRD_SEL_OVER_GCT_IMBAL", .pme_code = 0x410c4, .pme_short_desc = "Thread selection overrides caused by GCT imbalance", .pme_long_desc = "Thread selection was overridden because of a GCT imbalance.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_SEL_OVER_GCT_IMBAL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_SEL_OVER_GCT_IMBAL] }, [ POWER5_PME_PM_FPU_FSQRT ] = { .pme_name = "PM_FPU_FSQRT", .pme_code = 0x200090, .pme_short_desc = "FPU executed FSQRT instruction", .pme_long_desc = "The floating point unit has executed a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU_FSQRT], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU_FSQRT] }, [ POWER5_PME_PM_MRK_LSU0_FLUSH_LRQ ] = { .pme_name = "PM_MRK_LSU0_FLUSH_LRQ", .pme_code = 0x810c2, .pme_short_desc = "LSU0 marked LRQ flushes", .pme_long_desc = "A marked load was flushed by unit 0 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LSU0_FLUSH_LRQ], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LSU0_FLUSH_LRQ] }, [ POWER5_PME_PM_PMC1_OVERFLOW ] = { .pme_name = "PM_PMC1_OVERFLOW", .pme_code = 0x20000a, .pme_short_desc = "PMC1 Overflow", .pme_long_desc = "Overflows from PMC1 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_PMC1_OVERFLOW], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PMC1_OVERFLOW] }, [ POWER5_PME_PM_L3SC_SNOOP_RETRY ] = { .pme_name = "PM_L3SC_SNOOP_RETRY", .pme_code = 0x731e5, .pme_short_desc = "L3 slice C snoop retries", .pme_long_desc = "Number of times an L3 retried a snoop because it got two in at the same time (one on snp_a, one on snp_b)", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SC_SNOOP_RETRY], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SC_SNOOP_RETRY] }, [ POWER5_PME_PM_DATA_TABLEWALK_CYC ] = { .pme_name = "PM_DATA_TABLEWALK_CYC", .pme_code = 0x800c7, .pme_short_desc = "Cycles doing data tablewalks", .pme_long_desc = "Cycles a translation tablewalk is active. While a tablewalk is active any request attempting to access the TLB will be rejected and retried.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_DATA_TABLEWALK_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DATA_TABLEWALK_CYC] }, [ POWER5_PME_PM_THRD_PRIO_6_CYC ] = { .pme_name = "PM_THRD_PRIO_6_CYC", .pme_code = 0x420e5, .pme_short_desc = "Cycles thread running at priority level 6", .pme_long_desc = "Cycles this thread was running at priority level 6.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_PRIO_6_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_PRIO_6_CYC] }, [ POWER5_PME_PM_FPU_FEST ] = { .pme_name = "PM_FPU_FEST", .pme_code = 0x401090, .pme_short_desc = "FPU executed FEST instruction", .pme_long_desc = "The floating point unit has executed an estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. Combined Unit 0 + Unit 1.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU_FEST], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU_FEST] }, [ POWER5_PME_PM_FAB_M1toP1_SIDECAR_EMPTY ] = { .pme_name = "PM_FAB_M1toP1_SIDECAR_EMPTY", .pme_code = 0x702c7, .pme_short_desc = "M1 to P1 sidecar empty", .pme_long_desc = "Fabric cycles when the Minus-1 hip/hop sidecars (sidecars for chip to chip data transfer) are empty. The signal is delivered at FBC speed and the count must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_M1toP1_SIDECAR_EMPTY], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_M1toP1_SIDECAR_EMPTY] }, [ POWER5_PME_PM_MRK_DATA_FROM_RMEM ] = { .pme_name = "PM_MRK_DATA_FROM_RMEM", .pme_code = 0x1c70a1, .pme_short_desc = "Marked data loaded from remote memory", .pme_long_desc = "The processor's Data Cache was reloaded due to a marked load from memory attached to a different module than this proccessor is located on.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_RMEM], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_RMEM] }, [ POWER5_PME_PM_MRK_DATA_FROM_L35_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L35_MOD_CYC", .pme_code = 0x4c70a6, .pme_short_desc = "Marked load latency from L3.5 modified", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L35_MOD_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L35_MOD_CYC] }, [ POWER5_PME_PM_MEM_PWQ_DISP ] = { .pme_name = "PM_MEM_PWQ_DISP", .pme_code = 0x704c6, .pme_short_desc = "Memory partial-write queue dispatched", .pme_long_desc = "Number of Partial Writes dispatched. The MC provides resources to gather partial cacheline writes (Partial line DMA writes & CI-stores) to up to four different cachelines at a time. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_PWQ_DISP], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_PWQ_DISP] }, [ POWER5_PME_PM_FAB_P1toM1_SIDECAR_EMPTY ] = { .pme_name = "PM_FAB_P1toM1_SIDECAR_EMPTY", .pme_code = 0x701c7, .pme_short_desc = "P1 to M1 sidecar empty", .pme_long_desc = "Fabric cycles when the Plus-1 hip/hop sidecars (sidecars for chip to chip data transfer) are empty. The signal is delivered at FBC speed and the count must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_P1toM1_SIDECAR_EMPTY], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_P1toM1_SIDECAR_EMPTY] }, [ POWER5_PME_PM_LD_MISS_L1_LSU0 ] = { .pme_name = "PM_LD_MISS_L1_LSU0", .pme_code = 0xc10c2, .pme_short_desc = "LSU0 L1 D cache load misses", .pme_long_desc = "Load references that miss the Level 1 Data cache, by unit 0.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LD_MISS_L1_LSU0], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LD_MISS_L1_LSU0] }, [ POWER5_PME_PM_SNOOP_PARTIAL_RTRY_QFULL ] = { .pme_name = "PM_SNOOP_PARTIAL_RTRY_QFULL", .pme_code = 0x730e6, .pme_short_desc = "Snoop partial write retry due to partial-write queues full", .pme_long_desc = "A snoop request for a partial write to memory was retried because the write queues that handle partial writes were full. When this happens the active writes are changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_SNOOP_PARTIAL_RTRY_QFULL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SNOOP_PARTIAL_RTRY_QFULL] }, [ POWER5_PME_PM_FPU1_STALL3 ] = { .pme_name = "PM_FPU1_STALL3", .pme_code = 0x20e5, .pme_short_desc = "FPU1 stalled in pipe3", .pme_long_desc = "FPU1 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always).", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU1_STALL3], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU1_STALL3] }, [ POWER5_PME_PM_GCT_USAGE_80to99_CYC ] = { .pme_name = "PM_GCT_USAGE_80to99_CYC", .pme_code = 0x30001f, .pme_short_desc = "Cycles GCT 80-99% full", .pme_long_desc = "Cycles when the Global Completion Table has between 80% and 99% of its slots used. The GCT has 20 entries shared between threads", .pme_event_ids = power5_event_ids[POWER5_PME_PM_GCT_USAGE_80to99_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GCT_USAGE_80to99_CYC] }, [ POWER5_PME_PM_WORK_HELD ] = { .pme_name = "PM_WORK_HELD", .pme_code = 0x40000c, .pme_short_desc = "Work held", .pme_long_desc = "RAS Unit has signaled completion to stop and there are groups waiting to complete", .pme_event_ids = power5_event_ids[POWER5_PME_PM_WORK_HELD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_WORK_HELD] }, [ POWER5_PME_PM_INST_CMPL ] = { .pme_name = "PM_INST_CMPL", .pme_code = 0x100009, .pme_short_desc = "Instructions completed", .pme_long_desc = "Number of PowerPC instructions that completed. ", .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_CMPL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_CMPL] }, [ POWER5_PME_PM_LSU1_FLUSH_UST ] = { .pme_name = "PM_LSU1_FLUSH_UST", .pme_code = 0xc00c5, .pme_short_desc = "LSU1 unaligned store flushes", .pme_long_desc = "A store was flushed from unit 1 because it was unaligned (crossed a 4K boundary)", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU1_FLUSH_UST], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU1_FLUSH_UST] }, [ POWER5_PME_PM_FXU_IDLE ] = { .pme_name = "PM_FXU_IDLE", .pme_code = 0x100012, .pme_short_desc = "FXU idle", .pme_long_desc = "FXU0 and FXU1 are both idle.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FXU_IDLE], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FXU_IDLE] }, [ POWER5_PME_PM_LSU0_FLUSH_ULD ] = { .pme_name = "PM_LSU0_FLUSH_ULD", .pme_code = 0xc00c0, .pme_short_desc = "LSU0 unaligned load flushes", .pme_long_desc = "A load was flushed from unit 0 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1)", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU0_FLUSH_ULD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU0_FLUSH_ULD] }, [ POWER5_PME_PM_LSU1_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU1_REJECT_LMQ_FULL", .pme_code = 0xc60e5, .pme_short_desc = "LSU1 reject due to LMQ full or missed data coming", .pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU1_REJECT_LMQ_FULL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU1_REJECT_LMQ_FULL] }, [ POWER5_PME_PM_GRP_DISP_REJECT ] = { .pme_name = "PM_GRP_DISP_REJECT", .pme_code = 0x120e4, .pme_short_desc = "Group dispatch rejected", .pme_long_desc = "A group that previously attempted dispatch was rejected.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_GRP_DISP_REJECT], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GRP_DISP_REJECT] }, [ POWER5_PME_PM_L2SA_MOD_INV ] = { .pme_name = "PM_L2SA_MOD_INV", .pme_code = 0x730e0, .pme_short_desc = "L2 slice A transition from modified to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_MOD_INV], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_MOD_INV] }, [ POWER5_PME_PM_PTEG_FROM_L25_SHR ] = { .pme_name = "PM_PTEG_FROM_L25_SHR", .pme_code = 0x183097, .pme_short_desc = "PTEG loaded from L2.5 shared", .pme_long_desc = "A Page Table Entry was loaded into the TLB with shared (T or SL) data from the L2 of a chip on the same module as this processor is located due to a demand load.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_PTEG_FROM_L25_SHR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PTEG_FROM_L25_SHR] }, [ POWER5_PME_PM_FAB_CMD_RETRIED ] = { .pme_name = "PM_FAB_CMD_RETRIED", .pme_code = 0x710c7, .pme_short_desc = "Fabric command retried", .pme_long_desc = "Incremented when a command issued by a chip on its SnoopA address bus is retried for any reason. The overwhelming majority of retries are due to running out of memory controller queues but retries can also be caused by trying to reference addresses that are in a transient cache state -- e.g. a line is transient after issuing a DCLAIM instruction to a shared line but before the associated store completes. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_CMD_RETRIED], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_CMD_RETRIED] }, [ POWER5_PME_PM_L3SA_SHR_INV ] = { .pme_name = "PM_L3SA_SHR_INV", .pme_code = 0x710c3, .pme_short_desc = "L3 slice A transition from shared to invalid", .pme_long_desc = "L3 snooper detects someone doing a store to a line that is Sx in this L3(i.e. invalidate hit SX and dispatched).", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SA_SHR_INV], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SA_SHR_INV] }, [ POWER5_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL ] = { .pme_name = "PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL", .pme_code = 0x713c1, .pme_short_desc = "L2 slice B RC dispatch attempt failed due to all CO busy", .pme_long_desc = "A Read/Claim dispatch was rejected because all Castout machines were busy.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL] }, [ POWER5_PME_PM_L2SA_RCST_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2SA_RCST_DISP_FAIL_ADDR", .pme_code = 0x712c0, .pme_short_desc = "L2 slice A RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = "A Read/Claim dispatch for a store failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_RCST_DISP_FAIL_ADDR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_RCST_DISP_FAIL_ADDR] }, [ POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_RC_FULL ] = { .pme_name = "PM_L2SA_RCLD_DISP_FAIL_RC_FULL", .pme_code = 0x721e0, .pme_short_desc = "L2 slice A RC load dispatch attempt failed due to all RC full", .pme_long_desc = "A Read/Claim dispatch for a load failed because all RC machines are busy.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_RC_FULL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_RC_FULL] }, [ POWER5_PME_PM_PTEG_FROM_L375_MOD ] = { .pme_name = "PM_PTEG_FROM_L375_MOD", .pme_code = 0x1830a7, .pme_short_desc = "PTEG loaded from L3.75 modified", .pme_long_desc = "A Page Table Entry was loaded into the TLB with modified (M) data from the L3 of a chip on a different module than this processor is located, due to a demand load.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_PTEG_FROM_L375_MOD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PTEG_FROM_L375_MOD] }, [ POWER5_PME_PM_MRK_LSU1_FLUSH_UST ] = { .pme_name = "PM_MRK_LSU1_FLUSH_UST", .pme_code = 0x810c5, .pme_short_desc = "LSU1 marked unaligned store flushes", .pme_long_desc = "A marked store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LSU1_FLUSH_UST], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LSU1_FLUSH_UST] }, [ POWER5_PME_PM_BR_ISSUED ] = { .pme_name = "PM_BR_ISSUED", .pme_code = 0x230e4, .pme_short_desc = "Branches issued", .pme_long_desc = "A branch instruction was issued to the branch unit. A branch that was incorrectly predicted may issue and execute multiple times.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_BR_ISSUED], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_BR_ISSUED] }, [ POWER5_PME_PM_MRK_GRP_BR_REDIR ] = { .pme_name = "PM_MRK_GRP_BR_REDIR", .pme_code = 0x212091, .pme_short_desc = "Group experienced marked branch redirect", .pme_long_desc = "A group containing a marked (sampled) instruction experienced a branch redirect.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_GRP_BR_REDIR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_GRP_BR_REDIR] }, [ POWER5_PME_PM_EE_OFF ] = { .pme_name = "PM_EE_OFF", .pme_code = 0x130e3, .pme_short_desc = "Cycles MSR(EE) bit off", .pme_long_desc = "Cycles MSR(EE) bit was off indicating that interrupts due to external exceptions were masked.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_EE_OFF], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_EE_OFF] }, [ POWER5_PME_PM_MEM_RQ_DISP_Q4to7 ] = { .pme_name = "PM_MEM_RQ_DISP_Q4to7", .pme_code = 0x712c6, .pme_short_desc = "Memory read queue dispatched to queues 4-7", .pme_long_desc = "A memory operation was dispatched to read queue 4,5,6 or 7. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_RQ_DISP_Q4to7], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_RQ_DISP_Q4to7] }, [ POWER5_PME_PM_MEM_FAST_PATH_RD_DISP ] = { .pme_name = "PM_MEM_FAST_PATH_RD_DISP", .pme_code = 0x713e6, .pme_short_desc = "Fast path memory read dispatched", .pme_long_desc = "Fast path memory read dispatched", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_FAST_PATH_RD_DISP], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_FAST_PATH_RD_DISP] }, [ POWER5_PME_PM_INST_FROM_L3 ] = { .pme_name = "PM_INST_FROM_L3", .pme_code = 0x12208d, .pme_short_desc = "Instruction fetched from L3", .pme_long_desc = "An instruction fetch group was fetched from the local L3. Fetch groups can contain up to 8 instructions", .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_L3], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_L3] }, [ POWER5_PME_PM_ITLB_MISS ] = { .pme_name = "PM_ITLB_MISS", .pme_code = 0x800c0, .pme_short_desc = "Instruction TLB misses", .pme_long_desc = "A TLB miss for an Instruction Fetch has occurred", .pme_event_ids = power5_event_ids[POWER5_PME_PM_ITLB_MISS], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_ITLB_MISS] }, [ POWER5_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { .pme_name = "PM_FXU1_BUSY_FXU0_IDLE", .pme_code = 0x400012, .pme_short_desc = "FXU1 busy FXU0 idle", .pme_long_desc = "FXU0 was idle while FXU1 was busy.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FXU1_BUSY_FXU0_IDLE], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FXU1_BUSY_FXU0_IDLE] }, [ POWER5_PME_PM_FXLS_FULL_CYC ] = { .pme_name = "PM_FXLS_FULL_CYC", .pme_code = 0x411090, .pme_short_desc = "Cycles FXLS queue is full", .pme_long_desc = "Cycles when the issue queues for one or both FXU/LSU units is full. Use with caution since this is the sum of cycles when Unit 0 was full plus Unit 1 full. It does not indicate when both units were full.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FXLS_FULL_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FXLS_FULL_CYC] }, [ POWER5_PME_PM_DTLB_REF_4K ] = { .pme_name = "PM_DTLB_REF_4K", .pme_code = 0xc40c2, .pme_short_desc = "Data TLB reference for 4K page", .pme_long_desc = "Data TLB references for 4KB pages. Includes hits + misses.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_DTLB_REF_4K], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DTLB_REF_4K] }, [ POWER5_PME_PM_GRP_DISP_VALID ] = { .pme_name = "PM_GRP_DISP_VALID", .pme_code = 0x120e3, .pme_short_desc = "Group dispatch valid", .pme_long_desc = "A group is available for dispatch. This does not mean it was successfully dispatched.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_GRP_DISP_VALID], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GRP_DISP_VALID] }, [ POWER5_PME_PM_LSU_FLUSH_UST ] = { .pme_name = "PM_LSU_FLUSH_UST", .pme_code = 0x2c0088, .pme_short_desc = "SRQ unaligned store flushes", .pme_long_desc = "A store was flushed because it was unaligned (crossed a 4K boundary). Combined Unit 0 + 1.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_FLUSH_UST], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_FLUSH_UST] }, [ POWER5_PME_PM_FXU1_FIN ] = { .pme_name = "PM_FXU1_FIN", .pme_code = 0x130e6, .pme_short_desc = "FXU1 produced a result", .pme_long_desc = "The Fixed Point unit 1 finished an instruction and produced a result. Instructions that finish may not necessary complete.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FXU1_FIN], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FXU1_FIN] }, [ POWER5_PME_PM_THRD_PRIO_4_CYC ] = { .pme_name = "PM_THRD_PRIO_4_CYC", .pme_code = 0x420e3, .pme_short_desc = "Cycles thread running at priority level 4", .pme_long_desc = "Cycles this thread was running at priority level 4.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_PRIO_4_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_PRIO_4_CYC] }, [ POWER5_PME_PM_MRK_DATA_FROM_L35_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L35_MOD", .pme_code = 0x2c709e, .pme_short_desc = "Marked data loaded from L3.5 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L3 of a chip on the same module as this processor is located due to a marked load.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L35_MOD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L35_MOD] }, [ POWER5_PME_PM_4INST_CLB_CYC ] = { .pme_name = "PM_4INST_CLB_CYC", .pme_code = 0x400c4, .pme_short_desc = "Cycles 4 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_4INST_CLB_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_4INST_CLB_CYC] }, [ POWER5_PME_PM_MRK_DTLB_REF_16M ] = { .pme_name = "PM_MRK_DTLB_REF_16M", .pme_code = 0xc40c7, .pme_short_desc = "Marked Data TLB reference for 16M page", .pme_long_desc = "Data TLB references by a marked instruction for 16MB pages.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DTLB_REF_16M], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DTLB_REF_16M] }, [ POWER5_PME_PM_INST_FROM_L375_MOD ] = { .pme_name = "PM_INST_FROM_L375_MOD", .pme_code = 0x42209d, .pme_short_desc = "Instruction fetched from L3.75 modified", .pme_long_desc = "An instruction fetch group was fetched with modified (M) data from the L3 of a chip on a different module than this processor is located. Fetch groups can contain up to 8 instructions", .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_L375_MOD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_L375_MOD] }, [ POWER5_PME_PM_L2SC_RCST_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2SC_RCST_DISP_FAIL_ADDR", .pme_code = 0x712c2, .pme_short_desc = "L2 slice C RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = "A Read/Claim dispatch for a store failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_RCST_DISP_FAIL_ADDR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_RCST_DISP_FAIL_ADDR] }, [ POWER5_PME_PM_GRP_CMPL ] = { .pme_name = "PM_GRP_CMPL", .pme_code = 0x300013, .pme_short_desc = "Group completed", .pme_long_desc = "A group completed. Microcoded instructions that span multiple groups will generate this event once per group.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_GRP_CMPL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GRP_CMPL] }, [ POWER5_PME_PM_FPU1_1FLOP ] = { .pme_name = "PM_FPU1_1FLOP", .pme_code = 0xc7, .pme_short_desc = "FPU1 executed add", .pme_long_desc = " mult", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU1_1FLOP], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU1_1FLOP] }, [ POWER5_PME_PM_FPU_FRSP_FCONV ] = { .pme_name = "PM_FPU_FRSP_FCONV", .pme_code = 0x301090, .pme_short_desc = "FPU executed FRSP or FCONV instructions", .pme_long_desc = "The floating point unit has executed a frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU_FRSP_FCONV], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU_FRSP_FCONV] }, [ POWER5_PME_PM_5INST_CLB_CYC ] = { .pme_name = "PM_5INST_CLB_CYC", .pme_code = 0x400c5, .pme_short_desc = "Cycles 5 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_5INST_CLB_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_5INST_CLB_CYC] }, [ POWER5_PME_PM_L3SC_REF ] = { .pme_name = "PM_L3SC_REF", .pme_code = 0x701c5, .pme_short_desc = "L3 slice C references", .pme_long_desc = "Number of attempts made by this chip cores to find data in the L3. Reported per L3 slice.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SC_REF], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SC_REF] }, [ POWER5_PME_PM_THRD_L2MISS_BOTH_CYC ] = { .pme_name = "PM_THRD_L2MISS_BOTH_CYC", .pme_code = 0x410c7, .pme_short_desc = "Cycles both threads in L2 misses", .pme_long_desc = "Cycles that both threads have L2 miss pending. If only one thread has a L2 miss pending the other thread is given priority at decode. If both threads have L2 miss pending decode priority is determined by the number of GCT entries used.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_L2MISS_BOTH_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_L2MISS_BOTH_CYC] }, [ POWER5_PME_PM_MEM_PW_GATH ] = { .pme_name = "PM_MEM_PW_GATH", .pme_code = 0x714c6, .pme_short_desc = "Memory partial-write gathered", .pme_long_desc = "Two or more partial-writes have been merged into a single memory write. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_PW_GATH], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_PW_GATH] }, [ POWER5_PME_PM_FAB_PNtoNN_SIDECAR ] = { .pme_name = "PM_FAB_PNtoNN_SIDECAR", .pme_code = 0x713c7, .pme_short_desc = "PN to NN beat went to sidecar first", .pme_long_desc = "Fabric Data beats that the base chip takes the inbound PN data and forwards it on to the outbound NN data bus after going into a sidecar first. The signal is delivered at FBC speed and the count must be scaled.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_PNtoNN_SIDECAR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_PNtoNN_SIDECAR] }, [ POWER5_PME_PM_FAB_DCLAIM_ISSUED ] = { .pme_name = "PM_FAB_DCLAIM_ISSUED", .pme_code = 0x720e7, .pme_short_desc = "dclaim issued", .pme_long_desc = "A DCLAIM command was issued. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly. ", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_DCLAIM_ISSUED], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_DCLAIM_ISSUED] }, [ POWER5_PME_PM_GRP_IC_MISS ] = { .pme_name = "PM_GRP_IC_MISS", .pme_code = 0x120e7, .pme_short_desc = "Group experienced I cache miss", .pme_long_desc = "Number of groups, counted at dispatch, that have encountered an icache miss redirect. Every group constructed from a fetch group that missed the instruction cache will count.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_GRP_IC_MISS], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GRP_IC_MISS] }, [ POWER5_PME_PM_INST_FROM_L35_SHR ] = { .pme_name = "PM_INST_FROM_L35_SHR", .pme_code = 0x12209d, .pme_short_desc = "Instruction fetched from L3.5 shared", .pme_long_desc = "An instruction fetch group was fetched with shared (S) data from the L3 of a chip on the same module as this processor is located. Fetch groups can contain up to 8 instructions", .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_L35_SHR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_L35_SHR] }, [ POWER5_PME_PM_LSU_LMQ_FULL_CYC ] = { .pme_name = "PM_LSU_LMQ_FULL_CYC", .pme_code = 0xc30e7, .pme_short_desc = "Cycles LMQ full", .pme_long_desc = "The Load Miss Queue was full.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_LMQ_FULL_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_LMQ_FULL_CYC] }, [ POWER5_PME_PM_MRK_DATA_FROM_L2_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L2_CYC", .pme_code = 0x2c70a0, .pme_short_desc = "Marked load latency from L2", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L2_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L2_CYC] }, [ POWER5_PME_PM_LSU_SRQ_SYNC_CYC ] = { .pme_name = "PM_LSU_SRQ_SYNC_CYC", .pme_code = 0x830e5, .pme_short_desc = "SRQ sync duration", .pme_long_desc = "Cycles that a sync instruction is active in the Store Request Queue.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_SRQ_SYNC_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_SRQ_SYNC_CYC] }, [ POWER5_PME_PM_LSU0_BUSY_REJECT ] = { .pme_name = "PM_LSU0_BUSY_REJECT", .pme_code = 0xc20e3, .pme_short_desc = "LSU0 busy due to reject", .pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions. ", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU0_BUSY_REJECT], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU0_BUSY_REJECT] }, [ POWER5_PME_PM_LSU_REJECT_ERAT_MISS ] = { .pme_name = "PM_LSU_REJECT_ERAT_MISS", .pme_code = 0x1c6090, .pme_short_desc = "LSU reject due to ERAT miss", .pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions due to an ERAT miss. Combined unit 0 + 1. Requests that miss the Derat are rejected and retried until the request hits in the Erat.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_REJECT_ERAT_MISS], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_REJECT_ERAT_MISS] }, [ POWER5_PME_PM_MRK_DATA_FROM_RMEM_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_RMEM_CYC", .pme_code = 0x4c70a1, .pme_short_desc = "Marked load latency from remote memory", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_RMEM_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_RMEM_CYC] }, [ POWER5_PME_PM_DATA_FROM_L375_SHR ] = { .pme_name = "PM_DATA_FROM_L375_SHR", .pme_code = 0x3c309e, .pme_short_desc = "Data loaded from L3.75 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (S) data from the L3 of a chip on a different module than this processor is located due to a demand load.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_DATA_FROM_L375_SHR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DATA_FROM_L375_SHR] }, [ POWER5_PME_PM_FPU0_FMOV_FEST ] = { .pme_name = "PM_FPU0_FMOV_FEST", .pme_code = 0x10c0, .pme_short_desc = "FPU0 executed FMOV or FEST instructions", .pme_long_desc = "FPU0 has executed a move kind of instruction or one of the estimate instructions. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU0_FMOV_FEST], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU0_FMOV_FEST] }, [ POWER5_PME_PM_PTEG_FROM_L25_MOD ] = { .pme_name = "PM_PTEG_FROM_L25_MOD", .pme_code = 0x283097, .pme_short_desc = "PTEG loaded from L2.5 modified", .pme_long_desc = "A Page Table Entry was loaded into the TLB with modified (M) data from the L2 of a chip on the same module as this processor is located due to a demand load.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_PTEG_FROM_L25_MOD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PTEG_FROM_L25_MOD] }, [ POWER5_PME_PM_LD_REF_L1_LSU0 ] = { .pme_name = "PM_LD_REF_L1_LSU0", .pme_code = 0xc10c0, .pme_short_desc = "LSU0 L1 D cache load references", .pme_long_desc = "Load references to Level 1 Data Cache, by unit 0.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LD_REF_L1_LSU0], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LD_REF_L1_LSU0] }, [ POWER5_PME_PM_THRD_PRIO_7_CYC ] = { .pme_name = "PM_THRD_PRIO_7_CYC", .pme_code = 0x420e6, .pme_short_desc = "Cycles thread running at priority level 7", .pme_long_desc = "Cycles this thread was running at priority level 7.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_PRIO_7_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_PRIO_7_CYC] }, [ POWER5_PME_PM_LSU1_FLUSH_SRQ ] = { .pme_name = "PM_LSU1_FLUSH_SRQ", .pme_code = 0xc00c7, .pme_short_desc = "LSU1 SRQ lhs flushes", .pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group. ", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU1_FLUSH_SRQ], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU1_FLUSH_SRQ] }, [ POWER5_PME_PM_L2SC_RCST_DISP ] = { .pme_name = "PM_L2SC_RCST_DISP", .pme_code = 0x702c2, .pme_short_desc = "L2 slice C RC store dispatch attempt", .pme_long_desc = "A Read/Claim dispatch for a Store was attempted.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_RCST_DISP], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_RCST_DISP] }, [ POWER5_PME_PM_CMPLU_STALL_DIV ] = { .pme_name = "PM_CMPLU_STALL_DIV", .pme_code = 0x411099, .pme_short_desc = "Completion stall caused by DIV instruction", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point divide instruction. This is a subset of PM_CMPLU_STALL_FXU.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_CMPLU_STALL_DIV], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_CMPLU_STALL_DIV] }, [ POWER5_PME_PM_MEM_RQ_DISP_Q12to15 ] = { .pme_name = "PM_MEM_RQ_DISP_Q12to15", .pme_code = 0x732e6, .pme_short_desc = "Memory read queue dispatched to queues 12-15", .pme_long_desc = "A memory operation was dispatched to read queue 12,13,14 or 15. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_RQ_DISP_Q12to15], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_RQ_DISP_Q12to15] }, [ POWER5_PME_PM_INST_FROM_L375_SHR ] = { .pme_name = "PM_INST_FROM_L375_SHR", .pme_code = 0x32209d, .pme_short_desc = "Instruction fetched from L3.75 shared", .pme_long_desc = "An instruction fetch group was fetched with shared (S) data from the L3 of a chip on a different module than this processor is located. Fetch groups can contain up to 8 instructions", .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_L375_SHR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_L375_SHR] }, [ POWER5_PME_PM_ST_REF_L1 ] = { .pme_name = "PM_ST_REF_L1", .pme_code = 0x3c1090, .pme_short_desc = "L1 D cache store references", .pme_long_desc = "Store references to the Data Cache. Combined Unit 0 + 1.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_ST_REF_L1], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_ST_REF_L1] }, [ POWER5_PME_PM_L3SB_ALL_BUSY ] = { .pme_name = "PM_L3SB_ALL_BUSY", .pme_code = 0x721e4, .pme_short_desc = "L3 slice B active for every cycle all CI/CO machines busy", .pme_long_desc = "Cycles All Castin/Castout machines are busy.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SB_ALL_BUSY], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SB_ALL_BUSY] }, [ POWER5_PME_PM_FAB_P1toVNorNN_SIDECAR_EMPTY ] = { .pme_name = "PM_FAB_P1toVNorNN_SIDECAR_EMPTY", .pme_code = 0x711c7, .pme_short_desc = "P1 to VN/NN sidecar empty", .pme_long_desc = "Fabric cycles when the Plus-1 jump sidecar (sidecars for mcm to mcm data transfer) is empty. The signal is delivered at FBC speed and the count must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_P1toVNorNN_SIDECAR_EMPTY], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_P1toVNorNN_SIDECAR_EMPTY] }, [ POWER5_PME_PM_MRK_DATA_FROM_L275_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L275_SHR_CYC", .pme_code = 0x2c70a3, .pme_short_desc = "Marked load latency from L2.75 shared", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L275_SHR_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L275_SHR_CYC] }, [ POWER5_PME_PM_FAB_HOLDtoNN_EMPTY ] = { .pme_name = "PM_FAB_HOLDtoNN_EMPTY", .pme_code = 0x722e7, .pme_short_desc = "Hold buffer to NN empty", .pme_long_desc = "Fabric cyles when the Next Node out hold-buffers are emtpy. The signal is delivered at FBC speed and the count must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_HOLDtoNN_EMPTY], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_HOLDtoNN_EMPTY] }, [ POWER5_PME_PM_DATA_FROM_LMEM ] = { .pme_name = "PM_DATA_FROM_LMEM", .pme_code = 0x2c3087, .pme_short_desc = "Data loaded from local memory", .pme_long_desc = "The processor's Data Cache was reloaded from memory attached to the same module this proccessor is located on.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_DATA_FROM_LMEM], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DATA_FROM_LMEM] }, [ POWER5_PME_PM_RUN_CYC ] = { .pme_name = "PM_RUN_CYC", .pme_code = 0x100005, .pme_short_desc = "Run cycles", .pme_long_desc = "Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_RUN_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_RUN_CYC] }, [ POWER5_PME_PM_PTEG_FROM_RMEM ] = { .pme_name = "PM_PTEG_FROM_RMEM", .pme_code = 0x1830a1, .pme_short_desc = "PTEG loaded from remote memory", .pme_long_desc = "A Page Table Entry was loaded into the TLB from memory attached to a different module than this proccessor is located on.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_PTEG_FROM_RMEM], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PTEG_FROM_RMEM] }, [ POWER5_PME_PM_L2SC_RCLD_DISP ] = { .pme_name = "PM_L2SC_RCLD_DISP", .pme_code = 0x701c2, .pme_short_desc = "L2 slice C RC load dispatch attempt", .pme_long_desc = "A Read/Claim dispatch for a Load was attempted", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_RCLD_DISP], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_RCLD_DISP] }, [ POWER5_PME_PM_LSU0_LDF ] = { .pme_name = "PM_LSU0_LDF", .pme_code = 0xc50c0, .pme_short_desc = "LSU0 executed Floating Point load instruction", .pme_long_desc = "A floating point load was executed by LSU0", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU0_LDF], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU0_LDF] }, [ POWER5_PME_PM_LSU_LRQ_S0_VALID ] = { .pme_name = "PM_LSU_LRQ_S0_VALID", .pme_code = 0xc20e2, .pme_short_desc = "LRQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the LRQ is split between the two threads (16 entries each).", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_LRQ_S0_VALID], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_LRQ_S0_VALID] }, [ POWER5_PME_PM_PMC3_OVERFLOW ] = { .pme_name = "PM_PMC3_OVERFLOW", .pme_code = 0x40000a, .pme_short_desc = "PMC3 Overflow", .pme_long_desc = "Overflows from PMC3 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_PMC3_OVERFLOW], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PMC3_OVERFLOW] }, [ POWER5_PME_PM_MRK_IMR_RELOAD ] = { .pme_name = "PM_MRK_IMR_RELOAD", .pme_code = 0x820e2, .pme_short_desc = "Marked IMR reloaded", .pme_long_desc = "A DL1 reload occurred due to marked load", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_IMR_RELOAD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_IMR_RELOAD] }, [ POWER5_PME_PM_MRK_GRP_TIMEO ] = { .pme_name = "PM_MRK_GRP_TIMEO", .pme_code = 0x40000b, .pme_short_desc = "Marked group completion timeout", .pme_long_desc = "The sampling timeout expired indicating that the previously sampled instruction is no longer in the processor", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_GRP_TIMEO], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_GRP_TIMEO] }, [ POWER5_PME_PM_ST_MISS_L1 ] = { .pme_name = "PM_ST_MISS_L1", .pme_code = 0xc10c3, .pme_short_desc = "L1 D cache store misses", .pme_long_desc = "A store missed the dcache. Combined Unit 0 + 1.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_ST_MISS_L1], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_ST_MISS_L1] }, [ POWER5_PME_PM_STOP_COMPLETION ] = { .pme_name = "PM_STOP_COMPLETION", .pme_code = 0x300018, .pme_short_desc = "Completion stopped", .pme_long_desc = "RAS Unit has signaled completion to stop", .pme_event_ids = power5_event_ids[POWER5_PME_PM_STOP_COMPLETION], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_STOP_COMPLETION] }, [ POWER5_PME_PM_LSU_BUSY_REJECT ] = { .pme_name = "PM_LSU_BUSY_REJECT", .pme_code = 0x1c2090, .pme_short_desc = "LSU busy due to reject", .pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions. Combined unit 0 + 1.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_BUSY_REJECT], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_BUSY_REJECT] }, [ POWER5_PME_PM_ISLB_MISS ] = { .pme_name = "PM_ISLB_MISS", .pme_code = 0x800c1, .pme_short_desc = "Instruction SLB misses", .pme_long_desc = "A SLB miss for an instruction fetch as occurred", .pme_event_ids = power5_event_ids[POWER5_PME_PM_ISLB_MISS], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_ISLB_MISS] }, [ POWER5_PME_PM_CYC ] = { .pme_name = "PM_CYC", .pme_code = 0xf, .pme_short_desc = "Processor cycles", .pme_long_desc = "Processor cycles", .pme_event_ids = power5_event_ids[POWER5_PME_PM_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_CYC] }, [ POWER5_PME_PM_THRD_ONE_RUN_CYC ] = { .pme_name = "PM_THRD_ONE_RUN_CYC", .pme_code = 0x10000b, .pme_short_desc = "One of the threads in run cycles", .pme_long_desc = "At least one thread has set its run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. This event does not respect FCWAIT.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_ONE_RUN_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_ONE_RUN_CYC] }, [ POWER5_PME_PM_GRP_BR_REDIR_NONSPEC ] = { .pme_name = "PM_GRP_BR_REDIR_NONSPEC", .pme_code = 0x112091, .pme_short_desc = "Group experienced non-speculative branch redirect", .pme_long_desc = "Number of groups, counted at completion, that have encountered a branch redirect.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_GRP_BR_REDIR_NONSPEC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GRP_BR_REDIR_NONSPEC] }, [ POWER5_PME_PM_LSU1_SRQ_STFWD ] = { .pme_name = "PM_LSU1_SRQ_STFWD", .pme_code = 0xc20e4, .pme_short_desc = "LSU1 SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load on unit 1. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU1_SRQ_STFWD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU1_SRQ_STFWD] }, [ POWER5_PME_PM_L3SC_MOD_INV ] = { .pme_name = "PM_L3SC_MOD_INV", .pme_code = 0x730e5, .pme_short_desc = "L3 slice C transition from modified to invalid", .pme_long_desc = "L3 snooper detects someone doing a store to a line that is truly M in this L3 (i.e. L3 going M=>I) Mu|Me are not included since they are formed due to a previous read op Tx is not included since it is considered shared at this point.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SC_MOD_INV], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SC_MOD_INV] }, [ POWER5_PME_PM_L2_PREF ] = { .pme_name = "PM_L2_PREF", .pme_code = 0xc50c3, .pme_short_desc = "L2 cache prefetches", .pme_long_desc = "A request to prefetch data into L2 was made", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2_PREF], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2_PREF] }, [ POWER5_PME_PM_GCT_NOSLOT_BR_MPRED ] = { .pme_name = "PM_GCT_NOSLOT_BR_MPRED", .pme_code = 0x41009c, .pme_short_desc = "No slot in GCT caused by branch mispredict", .pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread because of a branch misprediction.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_GCT_NOSLOT_BR_MPRED], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GCT_NOSLOT_BR_MPRED] }, [ POWER5_PME_PM_MRK_DATA_FROM_L25_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L25_MOD", .pme_code = 0x2c7097, .pme_short_desc = "Marked data loaded from L2.5 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L2 of a chip on the same module as this processor is located due to a marked load.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L25_MOD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L25_MOD] }, [ POWER5_PME_PM_L2SB_MOD_INV ] = { .pme_name = "PM_L2SB_MOD_INV", .pme_code = 0x730e1, .pme_short_desc = "L2 slice B transition from modified to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_MOD_INV], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_MOD_INV] }, [ POWER5_PME_PM_L2SB_ST_REQ ] = { .pme_name = "PM_L2SB_ST_REQ", .pme_code = 0x723e1, .pme_short_desc = "L2 slice B store requests", .pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A, B, and C.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_ST_REQ], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_ST_REQ] }, [ POWER5_PME_PM_MRK_L1_RELOAD_VALID ] = { .pme_name = "PM_MRK_L1_RELOAD_VALID", .pme_code = 0xc70e4, .pme_short_desc = "Marked L1 reload data source valid", .pme_long_desc = "The source information is valid and is for a marked load", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_L1_RELOAD_VALID], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_L1_RELOAD_VALID] }, [ POWER5_PME_PM_L3SB_HIT ] = { .pme_name = "PM_L3SB_HIT", .pme_code = 0x711c4, .pme_short_desc = "L3 slice B hits", .pme_long_desc = "Number of attempts made by this chip cores that resulted in an L3 hit. Reported per L3 slice", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SB_HIT], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SB_HIT] }, [ POWER5_PME_PM_L2SB_SHR_MOD ] = { .pme_name = "PM_L2SB_SHR_MOD", .pme_code = 0x700c1, .pme_short_desc = "L2 slice B transition from shared to modified", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A, B, and C. ", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_SHR_MOD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_SHR_MOD] }, [ POWER5_PME_PM_EE_OFF_EXT_INT ] = { .pme_name = "PM_EE_OFF_EXT_INT", .pme_code = 0x130e7, .pme_short_desc = "Cycles MSR(EE) bit off and external interrupt pending", .pme_long_desc = "Cycles when an interrupt due to an external exception is pending but external exceptions were masked.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_EE_OFF_EXT_INT], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_EE_OFF_EXT_INT] }, [ POWER5_PME_PM_1PLUS_PPC_CMPL ] = { .pme_name = "PM_1PLUS_PPC_CMPL", .pme_code = 0x100013, .pme_short_desc = "One or more PPC instruction completed", .pme_long_desc = "A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_1PLUS_PPC_CMPL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_1PLUS_PPC_CMPL] }, [ POWER5_PME_PM_L2SC_SHR_MOD ] = { .pme_name = "PM_L2SC_SHR_MOD", .pme_code = 0x700c2, .pme_short_desc = "L2 slice C transition from shared to modified", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A, B, and C. ", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_SHR_MOD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_SHR_MOD] }, [ POWER5_PME_PM_PMC6_OVERFLOW ] = { .pme_name = "PM_PMC6_OVERFLOW", .pme_code = 0x30001a, .pme_short_desc = "PMC6 Overflow", .pme_long_desc = "Overflows from PMC6 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_PMC6_OVERFLOW], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PMC6_OVERFLOW] }, [ POWER5_PME_PM_LSU_LRQ_FULL_CYC ] = { .pme_name = "PM_LSU_LRQ_FULL_CYC", .pme_code = 0x110c2, .pme_short_desc = "Cycles LRQ full", .pme_long_desc = "Cycles when the LRQ is full.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_LRQ_FULL_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_LRQ_FULL_CYC] }, [ POWER5_PME_PM_IC_PREF_INSTALL ] = { .pme_name = "PM_IC_PREF_INSTALL", .pme_code = 0x210c7, .pme_short_desc = "Instruction prefetched installed in prefetch buffer", .pme_long_desc = "A prefetch buffer entry (line) is allocated but the request is not a demand fetch.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_IC_PREF_INSTALL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_IC_PREF_INSTALL] }, [ POWER5_PME_PM_TLB_MISS ] = { .pme_name = "PM_TLB_MISS", .pme_code = 0x180088, .pme_short_desc = "TLB misses", .pme_long_desc = "Total of Data TLB mises + Instruction TLB misses", .pme_event_ids = power5_event_ids[POWER5_PME_PM_TLB_MISS], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_TLB_MISS] }, [ POWER5_PME_PM_GCT_FULL_CYC ] = { .pme_name = "PM_GCT_FULL_CYC", .pme_code = 0x100c0, .pme_short_desc = "Cycles GCT full", .pme_long_desc = "The Global Completion Table is completely full.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_GCT_FULL_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GCT_FULL_CYC] }, [ POWER5_PME_PM_FXU_BUSY ] = { .pme_name = "PM_FXU_BUSY", .pme_code = 0x200012, .pme_short_desc = "FXU busy", .pme_long_desc = "Cycles when both FXU0 and FXU1 are busy.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FXU_BUSY], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FXU_BUSY] }, [ POWER5_PME_PM_MRK_DATA_FROM_L3_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L3_CYC", .pme_code = 0x2c70a4, .pme_short_desc = "Marked load latency from L3", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L3_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L3_CYC] }, [ POWER5_PME_PM_LSU_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU_REJECT_LMQ_FULL", .pme_code = 0x2c6088, .pme_short_desc = "LSU reject due to LMQ full or missed data coming", .pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all the eight entries are full, subsequent load instructions are rejected. Combined unit 0 + 1.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_REJECT_LMQ_FULL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_REJECT_LMQ_FULL] }, [ POWER5_PME_PM_LSU_SRQ_S0_ALLOC ] = { .pme_name = "PM_LSU_SRQ_S0_ALLOC", .pme_code = 0xc20e5, .pme_short_desc = "SRQ slot 0 allocated", .pme_long_desc = "SRQ Slot zero was allocated", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_SRQ_S0_ALLOC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_SRQ_S0_ALLOC] }, [ POWER5_PME_PM_GRP_MRK ] = { .pme_name = "PM_GRP_MRK", .pme_code = 0x100014, .pme_short_desc = "Group marked in IDU", .pme_long_desc = "A group was sampled (marked). The group is called a marked group. One instruction within the group is tagged for detailed monitoring. The sampled instruction is called a marked instructions. Events associated with the marked instruction are annotated with the marked term.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_GRP_MRK], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GRP_MRK] }, [ POWER5_PME_PM_INST_FROM_L25_SHR ] = { .pme_name = "PM_INST_FROM_L25_SHR", .pme_code = 0x122096, .pme_short_desc = "Instruction fetched from L2.5 shared", .pme_long_desc = "An instruction fetch group was fetched with shared (T or SL) data from the L2 of a chip on the same module as this processor is located. Fetch groups can contain up to 8 instructions.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_L25_SHR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_L25_SHR] }, [ POWER5_PME_PM_FPU1_FIN ] = { .pme_name = "PM_FPU1_FIN", .pme_code = 0x10c7, .pme_short_desc = "FPU1 produced a result", .pme_long_desc = "FPU1 finished, produced a result. This only indicates finish, not completion. Floating Point Stores are included in this count but not Floating Point Loads., , ", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU1_FIN], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU1_FIN] }, [ POWER5_PME_PM_DC_PREF_STREAM_ALLOC ] = { .pme_name = "PM_DC_PREF_STREAM_ALLOC", .pme_code = 0x830e7, .pme_short_desc = "D cache new prefetch stream allocated", .pme_long_desc = "A new Prefetch Stream was allocated.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_DC_PREF_STREAM_ALLOC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DC_PREF_STREAM_ALLOC] }, [ POWER5_PME_PM_BR_MPRED_TA ] = { .pme_name = "PM_BR_MPRED_TA", .pme_code = 0x230e6, .pme_short_desc = "Branch mispredictions due to target address", .pme_long_desc = "A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_BR_MPRED_TA], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_BR_MPRED_TA] }, [ POWER5_PME_PM_CRQ_FULL_CYC ] = { .pme_name = "PM_CRQ_FULL_CYC", .pme_code = 0x110c1, .pme_short_desc = "Cycles CR issue queue full", .pme_long_desc = "The issue queue that feeds the Conditional Register unit is full. This condition will prevent dispatch groups from being dispatched. This event only indicates that the queue was full, not that dispatch was prevented.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_CRQ_FULL_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_CRQ_FULL_CYC] }, [ POWER5_PME_PM_L2SA_RCLD_DISP ] = { .pme_name = "PM_L2SA_RCLD_DISP", .pme_code = 0x701c0, .pme_short_desc = "L2 slice A RC load dispatch attempt", .pme_long_desc = "A Read/Claim dispatch for a Load was attempted", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_RCLD_DISP], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_RCLD_DISP] }, [ POWER5_PME_PM_SNOOP_WR_RETRY_QFULL ] = { .pme_name = "PM_SNOOP_WR_RETRY_QFULL", .pme_code = 0x710c6, .pme_short_desc = "Snoop read retry due to read queue full", .pme_long_desc = "A snoop request for a write to memory was retried because the write queues were full. When this happens the snoop request is retried and the writes in the write reorder queue are changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_SNOOP_WR_RETRY_QFULL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SNOOP_WR_RETRY_QFULL] }, [ POWER5_PME_PM_MRK_DTLB_REF_4K ] = { .pme_name = "PM_MRK_DTLB_REF_4K", .pme_code = 0xc40c3, .pme_short_desc = "Marked Data TLB reference for 4K page", .pme_long_desc = "Data TLB references by a marked instruction for 4KB pages.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DTLB_REF_4K], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DTLB_REF_4K] }, [ POWER5_PME_PM_LSU_SRQ_S0_VALID ] = { .pme_name = "PM_LSU_SRQ_S0_VALID", .pme_code = 0xc20e1, .pme_short_desc = "SRQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the SRQ is split between the two threads (16 entries each).", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_SRQ_S0_VALID], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_SRQ_S0_VALID] }, [ POWER5_PME_PM_LSU0_FLUSH_LRQ ] = { .pme_name = "PM_LSU0_FLUSH_LRQ", .pme_code = 0xc00c2, .pme_short_desc = "LSU0 LRQ flushes", .pme_long_desc = "A load was flushed by unit 0 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU0_FLUSH_LRQ], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU0_FLUSH_LRQ] }, [ POWER5_PME_PM_INST_FROM_L275_MOD ] = { .pme_name = "PM_INST_FROM_L275_MOD", .pme_code = 0x422096, .pme_short_desc = "Instruction fetched from L2.75 modified", .pme_long_desc = "An instruction fetch group was fetched with modified (M) data from the L2 on a different module than this processor is located. Fetch groups can contain up to 8 instructions ", .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_L275_MOD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_L275_MOD] }, [ POWER5_PME_PM_GCT_EMPTY_CYC ] = { .pme_name = "PM_GCT_EMPTY_CYC", .pme_code = 0x200004, .pme_short_desc = "Cycles GCT empty", .pme_long_desc = "The Global Completion Table is completely empty", .pme_event_ids = power5_event_ids[POWER5_PME_PM_GCT_EMPTY_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GCT_EMPTY_CYC] }, [ POWER5_PME_PM_LARX_LSU0 ] = { .pme_name = "PM_LARX_LSU0", .pme_code = 0x820e7, .pme_short_desc = "Larx executed on LSU0", .pme_long_desc = "A larx (lwarx or ldarx) was executed on side 0 (there is no corresponding unit 1 event since larx instructions can only execute on unit 0)", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LARX_LSU0], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LARX_LSU0] }, [ POWER5_PME_PM_THRD_PRIO_DIFF_5or6_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_5or6_CYC", .pme_code = 0x430e6, .pme_short_desc = "Cycles thread priority difference is 5 or 6", .pme_long_desc = "Cycles when this thread's priority is higher than the other thread's priority by 5 or 6.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_PRIO_DIFF_5or6_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_PRIO_DIFF_5or6_CYC] }, [ POWER5_PME_PM_SNOOP_RETRY_1AHEAD ] = { .pme_name = "PM_SNOOP_RETRY_1AHEAD", .pme_code = 0x725e6, .pme_short_desc = "Snoop retry due to one ahead collision", .pme_long_desc = "Snoop retry due to one ahead collision", .pme_event_ids = power5_event_ids[POWER5_PME_PM_SNOOP_RETRY_1AHEAD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SNOOP_RETRY_1AHEAD] }, [ POWER5_PME_PM_FPU1_FSQRT ] = { .pme_name = "PM_FPU1_FSQRT", .pme_code = 0xc6, .pme_short_desc = "FPU1 executed FSQRT instruction", .pme_long_desc = "FPU1 has executed a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU1_FSQRT], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU1_FSQRT] }, [ POWER5_PME_PM_MRK_LD_MISS_L1_LSU1 ] = { .pme_name = "PM_MRK_LD_MISS_L1_LSU1", .pme_code = 0x820e4, .pme_short_desc = "LSU1 marked L1 D cache load misses", .pme_long_desc = "Load references that miss the Level 1 Data cache, by LSU1.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LD_MISS_L1_LSU1], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LD_MISS_L1_LSU1] }, [ POWER5_PME_PM_MRK_FPU_FIN ] = { .pme_name = "PM_MRK_FPU_FIN", .pme_code = 0x300014, .pme_short_desc = "Marked instruction FPU processing finished", .pme_long_desc = "One of the Floating Point Units finished a marked instruction. Instructions that finish may not necessary complete", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_FPU_FIN], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_FPU_FIN] }, [ POWER5_PME_PM_THRD_PRIO_5_CYC ] = { .pme_name = "PM_THRD_PRIO_5_CYC", .pme_code = 0x420e4, .pme_short_desc = "Cycles thread running at priority level 5", .pme_long_desc = "Cycles this thread was running at priority level 5.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_PRIO_5_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_PRIO_5_CYC] }, [ POWER5_PME_PM_MRK_DATA_FROM_LMEM ] = { .pme_name = "PM_MRK_DATA_FROM_LMEM", .pme_code = 0x2c7087, .pme_short_desc = "Marked data loaded from local memory", .pme_long_desc = "The processor's Data Cache was reloaded due to a marked load from memory attached to the same module this proccessor is located on.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_LMEM], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_LMEM] }, [ POWER5_PME_PM_FPU1_FRSP_FCONV ] = { .pme_name = "PM_FPU1_FRSP_FCONV", .pme_code = 0x10c5, .pme_short_desc = "FPU1 executed FRSP or FCONV instructions", .pme_long_desc = "FPU1 has executed a frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU1_FRSP_FCONV], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU1_FRSP_FCONV] }, [ POWER5_PME_PM_SNOOP_TLBIE ] = { .pme_name = "PM_SNOOP_TLBIE", .pme_code = 0x800c3, .pme_short_desc = "Snoop TLBIE", .pme_long_desc = "A tlbie was snooped from another processor.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_SNOOP_TLBIE], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SNOOP_TLBIE] }, [ POWER5_PME_PM_L3SB_SNOOP_RETRY ] = { .pme_name = "PM_L3SB_SNOOP_RETRY", .pme_code = 0x731e4, .pme_short_desc = "L3 slice B snoop retries", .pme_long_desc = "Number of times an L3 retried a snoop because it got two in at the same time (one on snp_a, one on snp_b)", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SB_SNOOP_RETRY], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SB_SNOOP_RETRY] }, [ POWER5_PME_PM_FAB_VBYPASS_EMPTY ] = { .pme_name = "PM_FAB_VBYPASS_EMPTY", .pme_code = 0x731e7, .pme_short_desc = "Vertical bypass buffer empty", .pme_long_desc = "Fabric cycles when the Middle Bypass sidecar is empty. The signal is delivered at FBC speed and the count must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_VBYPASS_EMPTY], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_VBYPASS_EMPTY] }, [ POWER5_PME_PM_MRK_DATA_FROM_L275_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L275_MOD", .pme_code = 0x1c70a3, .pme_short_desc = "Marked data loaded from L2.75 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L2 on a different module than this processor is located due to a marked load.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L275_MOD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L275_MOD] }, [ POWER5_PME_PM_6INST_CLB_CYC ] = { .pme_name = "PM_6INST_CLB_CYC", .pme_code = 0x400c6, .pme_short_desc = "Cycles 6 instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_6INST_CLB_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_6INST_CLB_CYC] }, [ POWER5_PME_PM_L2SB_RCST_DISP ] = { .pme_name = "PM_L2SB_RCST_DISP", .pme_code = 0x702c1, .pme_short_desc = "L2 slice B RC store dispatch attempt", .pme_long_desc = "A Read/Claim dispatch for a Store was attempted.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_RCST_DISP], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_RCST_DISP] }, [ POWER5_PME_PM_FLUSH ] = { .pme_name = "PM_FLUSH", .pme_code = 0x110c7, .pme_short_desc = "Flushes", .pme_long_desc = "Flushes occurred including LSU and Branch flushes.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FLUSH], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FLUSH] }, [ POWER5_PME_PM_L2SC_MOD_INV ] = { .pme_name = "PM_L2SC_MOD_INV", .pme_code = 0x730e2, .pme_short_desc = "L2 slice C transition from modified to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Invalid state. This transition was caused by any RWITM snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_MOD_INV], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_MOD_INV] }, [ POWER5_PME_PM_FPU_DENORM ] = { .pme_name = "PM_FPU_DENORM", .pme_code = 0x102088, .pme_short_desc = "FPU received denormalized data", .pme_long_desc = "The floating point unit has encountered a denormalized operand. Combined Unit 0 + Unit 1.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU_DENORM], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU_DENORM] }, [ POWER5_PME_PM_L3SC_HIT ] = { .pme_name = "PM_L3SC_HIT", .pme_code = 0x711c5, .pme_short_desc = "L3 slice C hits", .pme_long_desc = "Number of attempts made by this chip cores that resulted in an L3 hit. Reported per L3 Slice", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SC_HIT], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SC_HIT] }, [ POWER5_PME_PM_SNOOP_WR_RETRY_RQ ] = { .pme_name = "PM_SNOOP_WR_RETRY_RQ", .pme_code = 0x706c6, .pme_short_desc = "Snoop write/dclaim retry due to collision with active read queue", .pme_long_desc = "A snoop request for a write or dclaim to memory was retried because it matched the cacheline of an active read. This event is sent from the Memory Controller clock domain and must be scaled accordingly", .pme_event_ids = power5_event_ids[POWER5_PME_PM_SNOOP_WR_RETRY_RQ], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SNOOP_WR_RETRY_RQ] }, [ POWER5_PME_PM_LSU1_REJECT_SRQ ] = { .pme_name = "PM_LSU1_REJECT_SRQ", .pme_code = 0xc60e4, .pme_short_desc = "LSU1 SRQ lhs rejects", .pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions because of Load Hit Store conditions. Loads are rejected when data is needed from a previous store instruction but store forwarding is not possible because the data is not fully contained in the Store Data Queue or is not yet available in the Store Data Queue.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU1_REJECT_SRQ], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU1_REJECT_SRQ] }, [ POWER5_PME_PM_IC_PREF_REQ ] = { .pme_name = "PM_IC_PREF_REQ", .pme_code = 0x220e6, .pme_short_desc = "Instruction prefetch requests", .pme_long_desc = "An instruction prefetch request has been made.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_IC_PREF_REQ], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_IC_PREF_REQ] }, [ POWER5_PME_PM_L3SC_ALL_BUSY ] = { .pme_name = "PM_L3SC_ALL_BUSY", .pme_code = 0x721e5, .pme_short_desc = "L3 slice C active for every cycle all CI/CO machines busy", .pme_long_desc = "Cycles All Castin/Castout machines are busy.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SC_ALL_BUSY], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SC_ALL_BUSY] }, [ POWER5_PME_PM_MRK_GRP_IC_MISS ] = { .pme_name = "PM_MRK_GRP_IC_MISS", .pme_code = 0x412091, .pme_short_desc = "Group experienced marked I cache miss", .pme_long_desc = "A group containing a marked (sampled) instruction experienced an instruction cache miss.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_GRP_IC_MISS], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_GRP_IC_MISS] }, [ POWER5_PME_PM_GCT_NOSLOT_IC_MISS ] = { .pme_name = "PM_GCT_NOSLOT_IC_MISS", .pme_code = 0x21009c, .pme_short_desc = "No slot in GCT caused by I cache miss", .pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread because of an Instruction Cache miss.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_GCT_NOSLOT_IC_MISS], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GCT_NOSLOT_IC_MISS] }, [ POWER5_PME_PM_MRK_DATA_FROM_L3 ] = { .pme_name = "PM_MRK_DATA_FROM_L3", .pme_code = 0x1c708e, .pme_short_desc = "Marked data loaded from L3", .pme_long_desc = "The processor's Data Cache was reloaded from the local L3 due to a marked load.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L3], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L3] }, [ POWER5_PME_PM_GCT_NOSLOT_SRQ_FULL ] = { .pme_name = "PM_GCT_NOSLOT_SRQ_FULL", .pme_code = 0x310084, .pme_short_desc = "No slot in GCT caused by SRQ full", .pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread because the Store Request Queue (SRQ) is full. This happens when the storage subsystem can not process the stores in the SRQ. Groups can not be dispatched until a SRQ entry is available.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_GCT_NOSLOT_SRQ_FULL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GCT_NOSLOT_SRQ_FULL] }, [ POWER5_PME_PM_THRD_SEL_OVER_ISU_HOLD ] = { .pme_name = "PM_THRD_SEL_OVER_ISU_HOLD", .pme_code = 0x410c5, .pme_short_desc = "Thread selection overrides caused by ISU holds", .pme_long_desc = "Thread selection was overridden because of an ISU hold.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_SEL_OVER_ISU_HOLD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_SEL_OVER_ISU_HOLD] }, [ POWER5_PME_PM_CMPLU_STALL_DCACHE_MISS ] = { .pme_name = "PM_CMPLU_STALL_DCACHE_MISS", .pme_code = 0x21109a, .pme_short_desc = "Completion stall caused by D cache miss", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a Data Cache Miss. Data Cache Miss has higher priority than any other Load/Store delay, so if an instruction encounters multiple delays only the Data Cache Miss will be reported and the entire delay period will be charged to Data Cache Miss. This is a subset of PM_CMPLU_STALL_LSU.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_CMPLU_STALL_DCACHE_MISS], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_CMPLU_STALL_DCACHE_MISS] }, [ POWER5_PME_PM_L3SA_MOD_INV ] = { .pme_name = "PM_L3SA_MOD_INV", .pme_code = 0x730e3, .pme_short_desc = "L3 slice A transition from modified to invalid", .pme_long_desc = "L3 snooper detects someone doing a store to a line that is truly M in this L3 (i.e. L3 going M=>I) Mu|Me are not included since they are formed due to a prev read op. Tx is not included since it is considered shared at this point.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SA_MOD_INV], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SA_MOD_INV] }, [ POWER5_PME_PM_LSU_FLUSH_LRQ ] = { .pme_name = "PM_LSU_FLUSH_LRQ", .pme_code = 0x2c0090, .pme_short_desc = "LRQ flushes", .pme_long_desc = "A load was flushed because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. Combined Units 0 and 1.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_FLUSH_LRQ], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_FLUSH_LRQ] }, [ POWER5_PME_PM_THRD_PRIO_2_CYC ] = { .pme_name = "PM_THRD_PRIO_2_CYC", .pme_code = 0x420e1, .pme_short_desc = "Cycles thread running at priority level 2", .pme_long_desc = "Cycles this thread was running at priority level 2.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_PRIO_2_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_PRIO_2_CYC] }, [ POWER5_PME_PM_LSU_FLUSH_SRQ ] = { .pme_name = "PM_LSU_FLUSH_SRQ", .pme_code = 0x1c0090, .pme_short_desc = "SRQ flushes", .pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group. Combined Unit 0 + 1.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_FLUSH_SRQ], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_FLUSH_SRQ] }, [ POWER5_PME_PM_MRK_LSU_SRQ_INST_VALID ] = { .pme_name = "PM_MRK_LSU_SRQ_INST_VALID", .pme_code = 0xc70e6, .pme_short_desc = "Marked instruction valid in SRQ", .pme_long_desc = "This signal is asserted every cycle when a marked request is resident in the Store Request Queue", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LSU_SRQ_INST_VALID], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LSU_SRQ_INST_VALID] }, [ POWER5_PME_PM_L3SA_REF ] = { .pme_name = "PM_L3SA_REF", .pme_code = 0x701c3, .pme_short_desc = "L3 slice A references", .pme_long_desc = "Number of attempts made by this chip cores to find data in the L3. Reported per L3 slice ", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SA_REF], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SA_REF] }, [ POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL ] = { .pme_name = "PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL", .pme_code = 0x713c2, .pme_short_desc = "L2 slice C RC dispatch attempt failed due to all CO busy", .pme_long_desc = "A Read/Claim dispatch was rejected because all Castout machines were busy.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL] }, [ POWER5_PME_PM_FPU0_STALL3 ] = { .pme_name = "PM_FPU0_STALL3", .pme_code = 0x20e1, .pme_short_desc = "FPU0 stalled in pipe3", .pme_long_desc = "FPU0 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always).", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU0_STALL3], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU0_STALL3] }, [ POWER5_PME_PM_GPR_MAP_FULL_CYC ] = { .pme_name = "PM_GPR_MAP_FULL_CYC", .pme_code = 0x130e5, .pme_short_desc = "Cycles GPR mapper full", .pme_long_desc = "The General Purpose Register mapper cannot accept any more groups. This condition will prevent dispatch groups from being dispatched. This event only indicates that the mapper was full, not that dispatch was prevented.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_GPR_MAP_FULL_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GPR_MAP_FULL_CYC] }, [ POWER5_PME_PM_TB_BIT_TRANS ] = { .pme_name = "PM_TB_BIT_TRANS", .pme_code = 0x100018, .pme_short_desc = "Time Base bit transition", .pme_long_desc = "When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 ", .pme_event_ids = power5_event_ids[POWER5_PME_PM_TB_BIT_TRANS], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_TB_BIT_TRANS] }, [ POWER5_PME_PM_MRK_LSU_FLUSH_LRQ ] = { .pme_name = "PM_MRK_LSU_FLUSH_LRQ", .pme_code = 0x381088, .pme_short_desc = "Marked LRQ flushes", .pme_long_desc = "A marked load was flushed because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LSU_FLUSH_LRQ], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LSU_FLUSH_LRQ] }, [ POWER5_PME_PM_FPU0_STF ] = { .pme_name = "PM_FPU0_STF", .pme_code = 0x20e2, .pme_short_desc = "FPU0 executed store instruction", .pme_long_desc = "FPU0 has executed a Floating Point Store instruction.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU0_STF], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU0_STF] }, [ POWER5_PME_PM_MRK_DTLB_MISS ] = { .pme_name = "PM_MRK_DTLB_MISS", .pme_code = 0xc50c6, .pme_short_desc = "Marked Data TLB misses", .pme_long_desc = "Data TLB references by a marked instruction that missed the TLB (all page sizes).", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DTLB_MISS], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DTLB_MISS] }, [ POWER5_PME_PM_FPU1_FMA ] = { .pme_name = "PM_FPU1_FMA", .pme_code = 0xc5, .pme_short_desc = "FPU1 executed multiply-add instruction", .pme_long_desc = "The floating point unit has executed a multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU1_FMA], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU1_FMA] }, [ POWER5_PME_PM_L2SA_MOD_TAG ] = { .pme_name = "PM_L2SA_MOD_TAG", .pme_code = 0x720e0, .pme_short_desc = "L2 slice A transition from modified to tagged", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_MOD_TAG], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_MOD_TAG] }, [ POWER5_PME_PM_LSU1_FLUSH_ULD ] = { .pme_name = "PM_LSU1_FLUSH_ULD", .pme_code = 0xc00c4, .pme_short_desc = "LSU1 unaligned load flushes", .pme_long_desc = "A load was flushed from unit 1 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1).", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU1_FLUSH_ULD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU1_FLUSH_ULD] }, [ POWER5_PME_PM_MRK_LSU0_FLUSH_UST ] = { .pme_name = "PM_MRK_LSU0_FLUSH_UST", .pme_code = 0x810c1, .pme_short_desc = "LSU0 marked unaligned store flushes", .pme_long_desc = "A marked store was flushed from unit 0 because it was unaligned", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LSU0_FLUSH_UST], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LSU0_FLUSH_UST] }, [ POWER5_PME_PM_MRK_INST_FIN ] = { .pme_name = "PM_MRK_INST_FIN", .pme_code = 0x300005, .pme_short_desc = "Marked instruction finished", .pme_long_desc = "One of the execution units finished a marked instruction. Instructions that finish may not necessary complete", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_INST_FIN], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_INST_FIN] }, [ POWER5_PME_PM_FPU0_FULL_CYC ] = { .pme_name = "PM_FPU0_FULL_CYC", .pme_code = 0x100c3, .pme_short_desc = "Cycles FPU0 issue queue full", .pme_long_desc = "The issue queue for FPU0 cannot accept any more instruction. Dispatch to this issue queue is stopped.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU0_FULL_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU0_FULL_CYC] }, [ POWER5_PME_PM_LSU_LRQ_S0_ALLOC ] = { .pme_name = "PM_LSU_LRQ_S0_ALLOC", .pme_code = 0xc20e6, .pme_short_desc = "LRQ slot 0 allocated", .pme_long_desc = "LRQ slot zero was allocated", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_LRQ_S0_ALLOC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_LRQ_S0_ALLOC] }, [ POWER5_PME_PM_MRK_LSU1_FLUSH_ULD ] = { .pme_name = "PM_MRK_LSU1_FLUSH_ULD", .pme_code = 0x810c4, .pme_short_desc = "LSU1 marked unaligned load flushes", .pme_long_desc = "A marked load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LSU1_FLUSH_ULD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LSU1_FLUSH_ULD] }, [ POWER5_PME_PM_MRK_DTLB_REF ] = { .pme_name = "PM_MRK_DTLB_REF", .pme_code = 0x1c4090, .pme_short_desc = "Marked Data TLB reference", .pme_long_desc = "Total number of Data TLB references by a marked instruction for all page sizes. Page size is determined at TLB reload time.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DTLB_REF], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DTLB_REF] }, [ POWER5_PME_PM_BR_UNCOND ] = { .pme_name = "PM_BR_UNCOND", .pme_code = 0x123087, .pme_short_desc = "Unconditional branch", .pme_long_desc = "An unconditional branch was executed.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_BR_UNCOND], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_BR_UNCOND] }, [ POWER5_PME_PM_THRD_SEL_OVER_L2MISS ] = { .pme_name = "PM_THRD_SEL_OVER_L2MISS", .pme_code = 0x410c3, .pme_short_desc = "Thread selection overrides caused by L2 misses", .pme_long_desc = "Thread selection was overridden because one thread was had a L2 miss pending.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_SEL_OVER_L2MISS], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_SEL_OVER_L2MISS] }, [ POWER5_PME_PM_L2SB_SHR_INV ] = { .pme_name = "PM_L2SB_SHR_INV", .pme_code = 0x710c1, .pme_short_desc = "L2 slice B transition from shared to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A, B, and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_SHR_INV], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_SHR_INV] }, [ POWER5_PME_PM_MEM_LO_PRIO_WR_CMPL ] = { .pme_name = "PM_MEM_LO_PRIO_WR_CMPL", .pme_code = 0x736e6, .pme_short_desc = "Low priority write completed", .pme_long_desc = "A memory write, which was not upgraded to high priority, completed. This event is sent from the Memory Controller clock domain and must be scaled accordingly", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_LO_PRIO_WR_CMPL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_LO_PRIO_WR_CMPL] }, [ POWER5_PME_PM_L3SC_MOD_TAG ] = { .pme_name = "PM_L3SC_MOD_TAG", .pme_code = 0x720e5, .pme_short_desc = "L3 slice C transition from modified to TAG", .pme_long_desc = "L3 snooper detects someone doing a read to a line that is truly M in this L3(i.e. L3 going M->T or M->I(go_Mu case); Mu|Me are not included since they are formed due to a prev read op). Tx is not included since it is considered shared at this point.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SC_MOD_TAG], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SC_MOD_TAG] }, [ POWER5_PME_PM_MRK_ST_MISS_L1 ] = { .pme_name = "PM_MRK_ST_MISS_L1", .pme_code = 0x820e3, .pme_short_desc = "Marked L1 D cache store misses", .pme_long_desc = "A marked store missed the dcache", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_ST_MISS_L1], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_ST_MISS_L1] }, [ POWER5_PME_PM_GRP_DISP_SUCCESS ] = { .pme_name = "PM_GRP_DISP_SUCCESS", .pme_code = 0x300002, .pme_short_desc = "Group dispatch success", .pme_long_desc = "Number of groups sucessfully dispatched (not rejected)", .pme_event_ids = power5_event_ids[POWER5_PME_PM_GRP_DISP_SUCCESS], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GRP_DISP_SUCCESS] }, [ POWER5_PME_PM_THRD_PRIO_DIFF_1or2_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_1or2_CYC", .pme_code = 0x430e4, .pme_short_desc = "Cycles thread priority difference is 1 or 2", .pme_long_desc = "Cycles when this thread's priority is higher than the other thread's priority by 1 or 2.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_PRIO_DIFF_1or2_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_PRIO_DIFF_1or2_CYC] }, [ POWER5_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = { .pme_name = "PM_IC_DEMAND_L2_BHT_REDIRECT", .pme_code = 0x230e0, .pme_short_desc = "L2 I cache demand request due to BHT redirect", .pme_long_desc = "A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (CR mispredict).", .pme_event_ids = power5_event_ids[POWER5_PME_PM_IC_DEMAND_L2_BHT_REDIRECT], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_IC_DEMAND_L2_BHT_REDIRECT] }, [ POWER5_PME_PM_MEM_WQ_DISP_Q8to15 ] = { .pme_name = "PM_MEM_WQ_DISP_Q8to15", .pme_code = 0x733e6, .pme_short_desc = "Memory write queue dispatched to queues 8-15", .pme_long_desc = "A memory operation was dispatched to a write queue in the range between 8 and 15. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_WQ_DISP_Q8to15], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_WQ_DISP_Q8to15] }, [ POWER5_PME_PM_FPU0_SINGLE ] = { .pme_name = "PM_FPU0_SINGLE", .pme_code = 0x20e3, .pme_short_desc = "FPU0 executed single precision instruction", .pme_long_desc = "FPU0 has executed a single precision instruction.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU0_SINGLE], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU0_SINGLE] }, [ POWER5_PME_PM_LSU_DERAT_MISS ] = { .pme_name = "PM_LSU_DERAT_MISS", .pme_code = 0x280090, .pme_short_desc = "DERAT misses", .pme_long_desc = "Total D-ERAT Misses. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction. Combined Unit 0 + 1.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_DERAT_MISS], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_DERAT_MISS] }, [ POWER5_PME_PM_THRD_PRIO_1_CYC ] = { .pme_name = "PM_THRD_PRIO_1_CYC", .pme_code = 0x420e0, .pme_short_desc = "Cycles thread running at priority level 1", .pme_long_desc = "Cycles this thread was running at priority level 1. Priority level 1 is the lowest and indicates the thread is sleeping.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_PRIO_1_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_PRIO_1_CYC] }, [ POWER5_PME_PM_L2SC_RCST_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2SC_RCST_DISP_FAIL_OTHER", .pme_code = 0x732e2, .pme_short_desc = "L2 slice C RC store dispatch attempt failed due to other reasons", .pme_long_desc = "A Read/Claim dispatch for a store failed for some reason other than Full or Collision conditions. Rejected dispatches do not count because they have not yet been attempted.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_RCST_DISP_FAIL_OTHER], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_RCST_DISP_FAIL_OTHER] }, [ POWER5_PME_PM_FPU1_FEST ] = { .pme_name = "PM_FPU1_FEST", .pme_code = 0x10c6, .pme_short_desc = "FPU1 executed FEST instruction", .pme_long_desc = "FPU1 has executed an estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU1_FEST], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU1_FEST] }, [ POWER5_PME_PM_FAB_HOLDtoVN_EMPTY ] = { .pme_name = "PM_FAB_HOLDtoVN_EMPTY", .pme_code = 0x721e7, .pme_short_desc = "Hold buffer to VN empty", .pme_long_desc = "Fabric cycles when the Vertical Node out hold-buffers are emtpy. The signal is delivered at FBC speed and the count must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_HOLDtoVN_EMPTY], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_HOLDtoVN_EMPTY] }, [ POWER5_PME_PM_SNOOP_RD_RETRY_RQ ] = { .pme_name = "PM_SNOOP_RD_RETRY_RQ", .pme_code = 0x705c6, .pme_short_desc = "Snoop read retry due to collision with active read queue", .pme_long_desc = "A snoop request for a read from memory was retried because it matched the cache line of an active read. The snoop request is retried because the L2 may be able to source data via intervention for the 2nd read faster than the MC. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_SNOOP_RD_RETRY_RQ], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SNOOP_RD_RETRY_RQ] }, [ POWER5_PME_PM_SNOOP_DCLAIM_RETRY_QFULL ] = { .pme_name = "PM_SNOOP_DCLAIM_RETRY_QFULL", .pme_code = 0x720e6, .pme_short_desc = "Snoop dclaim/flush retry due to write/dclaim queues full", .pme_long_desc = "The memory controller A memory write was dispatched to a write queue. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_SNOOP_DCLAIM_RETRY_QFULL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SNOOP_DCLAIM_RETRY_QFULL] }, [ POWER5_PME_PM_MRK_DATA_FROM_L25_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L25_SHR_CYC", .pme_code = 0x2c70a2, .pme_short_desc = "Marked load latency from L2.5 shared", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L25_SHR_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L25_SHR_CYC] }, [ POWER5_PME_PM_MRK_ST_CMPL_INT ] = { .pme_name = "PM_MRK_ST_CMPL_INT", .pme_code = 0x300003, .pme_short_desc = "Marked store completed with intervention", .pme_long_desc = "A marked store previously sent to the memory subsystem completed (data home) after requiring intervention", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_ST_CMPL_INT], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_ST_CMPL_INT] }, [ POWER5_PME_PM_FLUSH_BR_MPRED ] = { .pme_name = "PM_FLUSH_BR_MPRED", .pme_code = 0x110c6, .pme_short_desc = "Flush caused by branch mispredict", .pme_long_desc = "A flush was caused by a branch mispredict.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FLUSH_BR_MPRED], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FLUSH_BR_MPRED] }, [ POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2SB_RCLD_DISP_FAIL_ADDR", .pme_code = 0x711c1, .pme_short_desc = "L2 slice B RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = "A Read/Claim dispatch for a load failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_ADDR] }, [ POWER5_PME_PM_FPU_STF ] = { .pme_name = "PM_FPU_STF", .pme_code = 0x202090, .pme_short_desc = "FPU executed store instruction", .pme_long_desc = "FPU has executed a store instruction. Combined Unit 0 + Unit 1.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU_STF], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU_STF] }, [ POWER5_PME_PM_CMPLU_STALL_FPU ] = { .pme_name = "PM_CMPLU_STALL_FPU", .pme_code = 0x411098, .pme_short_desc = "Completion stall caused by FPU instruction", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a floating point instruction.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_CMPLU_STALL_FPU], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_CMPLU_STALL_FPU] }, [ POWER5_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_minus1or2_CYC", .pme_code = 0x430e2, .pme_short_desc = "Cycles thread priority difference is -1 or -2", .pme_long_desc = "Cycles when this thread's priority is lower than the other thread's priority by 1 or 2.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_PRIO_DIFF_minus1or2_CYC] }, [ POWER5_PME_PM_GCT_NOSLOT_CYC ] = { .pme_name = "PM_GCT_NOSLOT_CYC", .pme_code = 0x100004, .pme_short_desc = "Cycles no GCT slot allocated", .pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_GCT_NOSLOT_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GCT_NOSLOT_CYC] }, [ POWER5_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { .pme_name = "PM_FXU0_BUSY_FXU1_IDLE", .pme_code = 0x300012, .pme_short_desc = "FXU0 busy FXU1 idle", .pme_long_desc = "FXU0 is busy while FXU1 was idle", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FXU0_BUSY_FXU1_IDLE], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FXU0_BUSY_FXU1_IDLE] }, [ POWER5_PME_PM_PTEG_FROM_L35_SHR ] = { .pme_name = "PM_PTEG_FROM_L35_SHR", .pme_code = 0x18309e, .pme_short_desc = "PTEG loaded from L3.5 shared", .pme_long_desc = "A Page Table Entry was loaded into the TLB with shared (S) data from the L3 of a chip on the same module as this processor is located, due to a demand load.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_PTEG_FROM_L35_SHR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PTEG_FROM_L35_SHR] }, [ POWER5_PME_PM_MRK_LSU_FLUSH_UST ] = { .pme_name = "PM_MRK_LSU_FLUSH_UST", .pme_code = 0x381090, .pme_short_desc = "Marked unaligned store flushes", .pme_long_desc = "A marked store was flushed because it was unaligned", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LSU_FLUSH_UST], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LSU_FLUSH_UST] }, [ POWER5_PME_PM_L3SA_HIT ] = { .pme_name = "PM_L3SA_HIT", .pme_code = 0x711c3, .pme_short_desc = "L3 slice A hits", .pme_long_desc = "Number of attempts made by this chip cores that resulted in an L3 hit. Reported per L3 slice", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SA_HIT], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SA_HIT] }, [ POWER5_PME_PM_MRK_DATA_FROM_L25_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L25_SHR", .pme_code = 0x1c7097, .pme_short_desc = "Marked data loaded from L2.5 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (T or SL) data from the L2 of a chip on the same module as this processor is located due to a marked load.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L25_SHR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L25_SHR] }, [ POWER5_PME_PM_L2SB_RCST_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2SB_RCST_DISP_FAIL_ADDR", .pme_code = 0x712c1, .pme_short_desc = "L2 slice B RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = "A Read/Claim dispatch for a store failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_RCST_DISP_FAIL_ADDR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_RCST_DISP_FAIL_ADDR] }, [ POWER5_PME_PM_MRK_DATA_FROM_L35_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L35_SHR", .pme_code = 0x1c709e, .pme_short_desc = "Marked data loaded from L3.5 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (S) data from the L3 of a chip on the same module as this processor is located due to a marked load.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L35_SHR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L35_SHR] }, [ POWER5_PME_PM_IERAT_XLATE_WR ] = { .pme_name = "PM_IERAT_XLATE_WR", .pme_code = 0x220e7, .pme_short_desc = "Translation written to ierat", .pme_long_desc = "An entry was written into the IERAT as a result of an IERAT miss. This event can be used to count IERAT misses. An ERAT miss that are later ignored will not be counted unless the ERAT is written before the instruction stream is changed.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_IERAT_XLATE_WR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_IERAT_XLATE_WR] }, [ POWER5_PME_PM_L2SA_ST_REQ ] = { .pme_name = "PM_L2SA_ST_REQ", .pme_code = 0x723e0, .pme_short_desc = "L2 slice A store requests", .pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A, B, and C.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_ST_REQ], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_ST_REQ] }, [ POWER5_PME_PM_THRD_SEL_T1 ] = { .pme_name = "PM_THRD_SEL_T1", .pme_code = 0x410c1, .pme_short_desc = "Decode selected thread 1", .pme_long_desc = "Thread selection picked thread 1 for decode.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_SEL_T1], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_SEL_T1] }, [ POWER5_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = { .pme_name = "PM_IC_DEMAND_L2_BR_REDIRECT", .pme_code = 0x230e1, .pme_short_desc = "L2 I cache demand request due to branch redirect", .pme_long_desc = "A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (either ALL mispredicted or Target).", .pme_event_ids = power5_event_ids[POWER5_PME_PM_IC_DEMAND_L2_BR_REDIRECT], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_IC_DEMAND_L2_BR_REDIRECT] }, [ POWER5_PME_PM_INST_FROM_LMEM ] = { .pme_name = "PM_INST_FROM_LMEM", .pme_code = 0x222086, .pme_short_desc = "Instruction fetched from local memory", .pme_long_desc = "An instruction fetch group was fetched from memory attached to the same module this proccessor is located on. Fetch groups can contain up to 8 instructions", .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_LMEM], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_LMEM] }, [ POWER5_PME_PM_FPU0_1FLOP ] = { .pme_name = "PM_FPU0_1FLOP", .pme_code = 0xc3, .pme_short_desc = "FPU0 executed add", .pme_long_desc = " mult", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU0_1FLOP], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU0_1FLOP] }, [ POWER5_PME_PM_MRK_DATA_FROM_L35_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L35_SHR_CYC", .pme_code = 0x2c70a6, .pme_short_desc = "Marked load latency from L3.5 shared", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L35_SHR_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L35_SHR_CYC] }, [ POWER5_PME_PM_PTEG_FROM_L2 ] = { .pme_name = "PM_PTEG_FROM_L2", .pme_code = 0x183087, .pme_short_desc = "PTEG loaded from L2", .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local L2 due to a demand load", .pme_event_ids = power5_event_ids[POWER5_PME_PM_PTEG_FROM_L2], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PTEG_FROM_L2] }, [ POWER5_PME_PM_MEM_PW_CMPL ] = { .pme_name = "PM_MEM_PW_CMPL", .pme_code = 0x724e6, .pme_short_desc = "Memory partial-write completed", .pme_long_desc = "Number of Partial Writes completed. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_PW_CMPL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_PW_CMPL] }, [ POWER5_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_minus5or6_CYC", .pme_code = 0x430e0, .pme_short_desc = "Cycles thread priority difference is -5 or -6", .pme_long_desc = "Cycles when this thread's priority is lower than the other thread's priority by 5 or 6.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_PRIO_DIFF_minus5or6_CYC] }, [ POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2SB_RCLD_DISP_FAIL_OTHER", .pme_code = 0x731e1, .pme_short_desc = "L2 slice B RC load dispatch attempt failed due to other reasons", .pme_long_desc = "A Read/Claim dispatch for a load failed for some reason other than Full or Collision conditions.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_OTHER] }, [ POWER5_PME_PM_FPU0_FIN ] = { .pme_name = "PM_FPU0_FIN", .pme_code = 0x10c3, .pme_short_desc = "FPU0 produced a result", .pme_long_desc = "FPU0 finished, produced a result. This only indicates finish, not completion. Floating Point Stores are included in this count but not Floating Point Loads.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU0_FIN], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU0_FIN] }, [ POWER5_PME_PM_MRK_DTLB_MISS_4K ] = { .pme_name = "PM_MRK_DTLB_MISS_4K", .pme_code = 0xc40c1, .pme_short_desc = "Marked Data TLB misses for 4K page", .pme_long_desc = "Data TLB references to 4KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DTLB_MISS_4K], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DTLB_MISS_4K] }, [ POWER5_PME_PM_L3SC_SHR_INV ] = { .pme_name = "PM_L3SC_SHR_INV", .pme_code = 0x710c5, .pme_short_desc = "L3 slice C transition from shared to invalid", .pme_long_desc = "L3 snooper detects someone doing a store to a line that is Sx in this L3(i.e. invalidate hit SX and dispatched).", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SC_SHR_INV], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SC_SHR_INV] }, [ POWER5_PME_PM_GRP_BR_REDIR ] = { .pme_name = "PM_GRP_BR_REDIR", .pme_code = 0x120e6, .pme_short_desc = "Group experienced branch redirect", .pme_long_desc = "Number of groups, counted at dispatch, that have encountered a branch redirect. Every group constructed from a fetch group that has been redirected will count.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_GRP_BR_REDIR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GRP_BR_REDIR] }, [ POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL ] = { .pme_name = "PM_L2SC_RCLD_DISP_FAIL_RC_FULL", .pme_code = 0x721e2, .pme_short_desc = "L2 slice C RC load dispatch attempt failed due to all RC full", .pme_long_desc = "A Read/Claim dispatch for a load failed because all RC machines are busy.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_RC_FULL] }, [ POWER5_PME_PM_MRK_LSU_FLUSH_SRQ ] = { .pme_name = "PM_MRK_LSU_FLUSH_SRQ", .pme_code = 0x481088, .pme_short_desc = "Marked SRQ lhs flushes", .pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LSU_FLUSH_SRQ], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LSU_FLUSH_SRQ] }, [ POWER5_PME_PM_PTEG_FROM_L275_SHR ] = { .pme_name = "PM_PTEG_FROM_L275_SHR", .pme_code = 0x383097, .pme_short_desc = "PTEG loaded from L2.75 shared", .pme_long_desc = "A Page Table Entry was loaded into the TLB with shared (T) data from the L2 on a different module than this processor is located due to a demand load.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_PTEG_FROM_L275_SHR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PTEG_FROM_L275_SHR] }, [ POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL ] = { .pme_name = "PM_L2SB_RCLD_DISP_FAIL_RC_FULL", .pme_code = 0x721e1, .pme_short_desc = "L2 slice B RC load dispatch attempt failed due to all RC full", .pme_long_desc = "A Read/Claim dispatch for a load failed because all RC machines are busy.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_RCLD_DISP_FAIL_RC_FULL] }, [ POWER5_PME_PM_SNOOP_RD_RETRY_WQ ] = { .pme_name = "PM_SNOOP_RD_RETRY_WQ", .pme_code = 0x715c6, .pme_short_desc = "Snoop read retry due to collision with active write queue", .pme_long_desc = "A snoop request for a read from memory was retried because it matched the cache line of an active write. The snoop request is retried and the active write is changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_SNOOP_RD_RETRY_WQ], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SNOOP_RD_RETRY_WQ] }, [ POWER5_PME_PM_LSU0_NCLD ] = { .pme_name = "PM_LSU0_NCLD", .pme_code = 0xc50c1, .pme_short_desc = "LSU0 non-cacheable loads", .pme_long_desc = "A non-cacheable load was executed by unit 0.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU0_NCLD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU0_NCLD] }, [ POWER5_PME_PM_FAB_DCLAIM_RETRIED ] = { .pme_name = "PM_FAB_DCLAIM_RETRIED", .pme_code = 0x730e7, .pme_short_desc = "dclaim retried", .pme_long_desc = "A DCLAIM command was retried. Each chip reports its own counts. The signal is delivered at FBC speed and the count must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_DCLAIM_RETRIED], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_DCLAIM_RETRIED] }, [ POWER5_PME_PM_LSU1_BUSY_REJECT ] = { .pme_name = "PM_LSU1_BUSY_REJECT", .pme_code = 0xc20e7, .pme_short_desc = "LSU1 busy due to reject", .pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU1_BUSY_REJECT], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU1_BUSY_REJECT] }, [ POWER5_PME_PM_FXLS0_FULL_CYC ] = { .pme_name = "PM_FXLS0_FULL_CYC", .pme_code = 0x110c0, .pme_short_desc = "Cycles FXU0/LS0 queue full", .pme_long_desc = "The issue queue that feeds the Fixed Point unit 0 / Load Store Unit 0 is full. This condition will prevent dispatch groups from being dispatched. This event only indicates that the queue was full, not that dispatch was prevented.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FXLS0_FULL_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FXLS0_FULL_CYC] }, [ POWER5_PME_PM_FPU0_FEST ] = { .pme_name = "PM_FPU0_FEST", .pme_code = 0x10c2, .pme_short_desc = "FPU0 executed FEST instruction", .pme_long_desc = "FPU0 has executed an estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. ", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU0_FEST], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU0_FEST] }, [ POWER5_PME_PM_DTLB_REF_16M ] = { .pme_name = "PM_DTLB_REF_16M", .pme_code = 0xc40c6, .pme_short_desc = "Data TLB reference for 16M page", .pme_long_desc = "Data TLB references for 16MB pages. Includes hits + misses.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_DTLB_REF_16M], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DTLB_REF_16M] }, [ POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2SC_RCLD_DISP_FAIL_ADDR", .pme_code = 0x711c2, .pme_short_desc = "L2 slice C RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = "A Read/Claim dispatch for a load failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_ADDR] }, [ POWER5_PME_PM_LSU0_REJECT_ERAT_MISS ] = { .pme_name = "PM_LSU0_REJECT_ERAT_MISS", .pme_code = 0xc60e3, .pme_short_desc = "LSU0 reject due to ERAT miss", .pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions due to an ERAT miss. Requests that miss the Derat are rejected and retried until the request hits in the Erat.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU0_REJECT_ERAT_MISS], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU0_REJECT_ERAT_MISS] }, [ POWER5_PME_PM_DATA_FROM_L25_MOD ] = { .pme_name = "PM_DATA_FROM_L25_MOD", .pme_code = 0x2c3097, .pme_short_desc = "Data loaded from L2.5 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L2 of a chip on the same module as this processor is located due to a demand load.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_DATA_FROM_L25_MOD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DATA_FROM_L25_MOD] }, [ POWER5_PME_PM_GCT_USAGE_60to79_CYC ] = { .pme_name = "PM_GCT_USAGE_60to79_CYC", .pme_code = 0x20001f, .pme_short_desc = "Cycles GCT 60-79% full", .pme_long_desc = "Cycles when the Global Completion Table has between 60% and 70% of its slots used. The GCT has 20 entries shared between threads.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_GCT_USAGE_60to79_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GCT_USAGE_60to79_CYC] }, [ POWER5_PME_PM_DATA_FROM_L375_MOD ] = { .pme_name = "PM_DATA_FROM_L375_MOD", .pme_code = 0x1c30a7, .pme_short_desc = "Data loaded from L3.75 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L3 of a chip on the same module as this processor is located due to a demand load.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_DATA_FROM_L375_MOD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DATA_FROM_L375_MOD] }, [ POWER5_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_LMQ_SRQ_EMPTY_CYC", .pme_code = 0x200015, .pme_short_desc = "Cycles LMQ and SRQ empty", .pme_long_desc = "Cycles when both the LMQ and SRQ are empty (LSU is idle)", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC] }, [ POWER5_PME_PM_LSU0_REJECT_RELOAD_CDF ] = { .pme_name = "PM_LSU0_REJECT_RELOAD_CDF", .pme_code = 0xc60e2, .pme_short_desc = "LSU0 reject due to reload CDF or tag update collision", .pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions because of Critical Data Forward. When critical data arrives from the storage system it is formatted and immediately forwarded, bypassing the data cache, to the destination register using the result bus. Any instruction the requires the result bus in the same cycle is rejected. Tag update rejects are caused when an instruction requires access to the Dcache directory or ERAT in the same system when they are being updated.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU0_REJECT_RELOAD_CDF], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU0_REJECT_RELOAD_CDF] }, [ POWER5_PME_PM_0INST_FETCH ] = { .pme_name = "PM_0INST_FETCH", .pme_code = 0x42208d, .pme_short_desc = "No instructions fetched", .pme_long_desc = "No instructions were fetched this cycles (due to IFU hold, redirect, or icache miss)", .pme_event_ids = power5_event_ids[POWER5_PME_PM_0INST_FETCH], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_0INST_FETCH] }, [ POWER5_PME_PM_LSU1_REJECT_RELOAD_CDF ] = { .pme_name = "PM_LSU1_REJECT_RELOAD_CDF", .pme_code = 0xc60e6, .pme_short_desc = "LSU1 reject due to reload CDF or tag update collision", .pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions because of Critical Data Forward. When critical data arrives from the storage system it is formatted and immediately forwarded, bypassing the data cache, to the destination register using the result bus. Any instruction the requires the result bus in the same cycle is rejected. Tag update rejects are caused when an instruction requires access to the Dcache directory or ERAT in the same system when they are being updated.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU1_REJECT_RELOAD_CDF], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU1_REJECT_RELOAD_CDF] }, [ POWER5_PME_PM_L1_PREF ] = { .pme_name = "PM_L1_PREF", .pme_code = 0xc70e7, .pme_short_desc = "L1 cache data prefetches", .pme_long_desc = "A request to prefetch data into the L1 was made", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L1_PREF], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L1_PREF] }, [ POWER5_PME_PM_MEM_WQ_DISP_Q0to7 ] = { .pme_name = "PM_MEM_WQ_DISP_Q0to7", .pme_code = 0x723e6, .pme_short_desc = "Memory write queue dispatched to queues 0-7", .pme_long_desc = "A memory operation was dispatched to a write queue in the range between 0 and 7. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_WQ_DISP_Q0to7], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_WQ_DISP_Q0to7] }, [ POWER5_PME_PM_MRK_DATA_FROM_LMEM_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_LMEM_CYC", .pme_code = 0x4c70a0, .pme_short_desc = "Marked load latency from local memory", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_LMEM_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_LMEM_CYC] }, [ POWER5_PME_PM_BRQ_FULL_CYC ] = { .pme_name = "PM_BRQ_FULL_CYC", .pme_code = 0x100c5, .pme_short_desc = "Cycles branch queue full", .pme_long_desc = "Cycles when the issue queue that feeds the branch unit is full. This condition will prevent dispatch groups from being dispatched. This event only indicates that the queue was full, not that dispatch was prevented.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_BRQ_FULL_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_BRQ_FULL_CYC] }, [ POWER5_PME_PM_GRP_IC_MISS_NONSPEC ] = { .pme_name = "PM_GRP_IC_MISS_NONSPEC", .pme_code = 0x112099, .pme_short_desc = "Group experienced non-speculative I cache miss", .pme_long_desc = "Number of groups, counted at completion, that have encountered an instruction cache miss.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_GRP_IC_MISS_NONSPEC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GRP_IC_MISS_NONSPEC] }, [ POWER5_PME_PM_PTEG_FROM_L275_MOD ] = { .pme_name = "PM_PTEG_FROM_L275_MOD", .pme_code = 0x1830a3, .pme_short_desc = "PTEG loaded from L2.75 modified", .pme_long_desc = "A Page Table Entry was loaded into the TLB with modified (M) data from the L2 on a different module than this processor is located due to a demand load. ", .pme_event_ids = power5_event_ids[POWER5_PME_PM_PTEG_FROM_L275_MOD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PTEG_FROM_L275_MOD] }, [ POWER5_PME_PM_MRK_LD_MISS_L1_LSU0 ] = { .pme_name = "PM_MRK_LD_MISS_L1_LSU0", .pme_code = 0x820e0, .pme_short_desc = "LSU0 marked L1 D cache load misses", .pme_long_desc = "Load references that miss the Level 1 Data cache, by LSU0.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LD_MISS_L1_LSU0], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LD_MISS_L1_LSU0] }, [ POWER5_PME_PM_MRK_DATA_FROM_L375_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L375_SHR_CYC", .pme_code = 0x2c70a7, .pme_short_desc = "Marked load latency from L3.75 shared", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L375_SHR_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L375_SHR_CYC] }, [ POWER5_PME_PM_LSU_FLUSH ] = { .pme_name = "PM_LSU_FLUSH", .pme_code = 0x110c5, .pme_short_desc = "Flush initiated by LSU", .pme_long_desc = "A flush was initiated by the Load Store Unit", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_FLUSH], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_FLUSH] }, [ POWER5_PME_PM_DATA_FROM_L3 ] = { .pme_name = "PM_DATA_FROM_L3", .pme_code = 0x1c308e, .pme_short_desc = "Data loaded from L3", .pme_long_desc = "The processor's Data Cache was reloaded from the local L3 due to a demand load.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_DATA_FROM_L3], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DATA_FROM_L3] }, [ POWER5_PME_PM_INST_FROM_L2 ] = { .pme_name = "PM_INST_FROM_L2", .pme_code = 0x122086, .pme_short_desc = "Instruction fetched from L2", .pme_long_desc = "An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions", .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_L2], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_L2] }, [ POWER5_PME_PM_PMC2_OVERFLOW ] = { .pme_name = "PM_PMC2_OVERFLOW", .pme_code = 0x30000a, .pme_short_desc = "PMC2 Overflow", .pme_long_desc = "Overflows from PMC2 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_PMC2_OVERFLOW], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PMC2_OVERFLOW] }, [ POWER5_PME_PM_FPU0_DENORM ] = { .pme_name = "PM_FPU0_DENORM", .pme_code = 0x20e0, .pme_short_desc = "FPU0 received denormalized data", .pme_long_desc = "FPU0 has encountered a denormalized operand. ", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU0_DENORM], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU0_DENORM] }, [ POWER5_PME_PM_FPU1_FMOV_FEST ] = { .pme_name = "PM_FPU1_FMOV_FEST", .pme_code = 0x10c4, .pme_short_desc = "FPU1 executed FMOV or FEST instructions", .pme_long_desc = "FPU1 has executed a move kind of instruction or one of the estimate instructions. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU1_FMOV_FEST], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU1_FMOV_FEST] }, [ POWER5_PME_PM_INST_FETCH_CYC ] = { .pme_name = "PM_INST_FETCH_CYC", .pme_code = 0x220e4, .pme_short_desc = "Cycles at least 1 instruction fetched", .pme_long_desc = "Cycles when at least one instruction was sent from the fetch unit to the decode unit.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FETCH_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FETCH_CYC] }, [ POWER5_PME_PM_LSU_LDF ] = { .pme_name = "PM_LSU_LDF", .pme_code = 0x4c5090, .pme_short_desc = "LSU executed Floating Point load instruction", .pme_long_desc = "LSU executed Floating Point load instruction. Combined Unit 0 + 1.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_LDF], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_LDF] }, [ POWER5_PME_PM_INST_DISP ] = { .pme_name = "PM_INST_DISP", .pme_code = 0x300009, .pme_short_desc = "Instructions dispatched", .pme_long_desc = "Number of PowerPC instructions successfully dispatched.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_DISP], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_DISP] }, [ POWER5_PME_PM_DATA_FROM_L25_SHR ] = { .pme_name = "PM_DATA_FROM_L25_SHR", .pme_code = 0x1c3097, .pme_short_desc = "Data loaded from L2.5 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (T or SL) data from the L2 of a chip on the same module as this processor is located due to a demand load.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_DATA_FROM_L25_SHR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DATA_FROM_L25_SHR] }, [ POWER5_PME_PM_L1_DCACHE_RELOAD_VALID ] = { .pme_name = "PM_L1_DCACHE_RELOAD_VALID", .pme_code = 0xc30e4, .pme_short_desc = "L1 reload data source valid", .pme_long_desc = "The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L1_DCACHE_RELOAD_VALID], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L1_DCACHE_RELOAD_VALID] }, [ POWER5_PME_PM_MEM_WQ_DISP_DCLAIM ] = { .pme_name = "PM_MEM_WQ_DISP_DCLAIM", .pme_code = 0x713c6, .pme_short_desc = "Memory write queue dispatched due to dclaim/flush", .pme_long_desc = "A memory dclaim or flush operation was dispatched to a write queue. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_WQ_DISP_DCLAIM], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_WQ_DISP_DCLAIM] }, [ POWER5_PME_PM_FPU_FULL_CYC ] = { .pme_name = "PM_FPU_FULL_CYC", .pme_code = 0x110090, .pme_short_desc = "Cycles FPU issue queue full", .pme_long_desc = "Cycles when one or both FPU issue queues are full. Combined Unit 0 + 1. Use with caution since this is the sum of cycles when Unit 0 was full plus Unit 1 full. It does not indicate when both units were full.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU_FULL_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU_FULL_CYC] }, [ POWER5_PME_PM_MRK_GRP_ISSUED ] = { .pme_name = "PM_MRK_GRP_ISSUED", .pme_code = 0x100015, .pme_short_desc = "Marked group issued", .pme_long_desc = "A sampled instruction was issued.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_GRP_ISSUED], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_GRP_ISSUED] }, [ POWER5_PME_PM_THRD_PRIO_3_CYC ] = { .pme_name = "PM_THRD_PRIO_3_CYC", .pme_code = 0x420e2, .pme_short_desc = "Cycles thread running at priority level 3", .pme_long_desc = "Cycles this thread was running at priority level 3.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_PRIO_3_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_PRIO_3_CYC] }, [ POWER5_PME_PM_FPU_FMA ] = { .pme_name = "PM_FPU_FMA", .pme_code = 0x200088, .pme_short_desc = "FPU executed multiply-add instruction", .pme_long_desc = "This signal is active for one cycle when FPU is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU_FMA], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU_FMA] }, [ POWER5_PME_PM_INST_FROM_L35_MOD ] = { .pme_name = "PM_INST_FROM_L35_MOD", .pme_code = 0x22209d, .pme_short_desc = "Instruction fetched from L3.5 modified", .pme_long_desc = "An instruction fetch group was fetched with modified (M) data from the L3 of a chip on the same module as this processor is located. Fetch groups can contain up to 8 instructions", .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_L35_MOD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_L35_MOD] }, [ POWER5_PME_PM_MRK_CRU_FIN ] = { .pme_name = "PM_MRK_CRU_FIN", .pme_code = 0x400005, .pme_short_desc = "Marked instruction CRU processing finished", .pme_long_desc = "The Condition Register Unit finished a marked instruction. Instructions that finish may not necessary complete.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_CRU_FIN], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_CRU_FIN] }, [ POWER5_PME_PM_SNOOP_WR_RETRY_WQ ] = { .pme_name = "PM_SNOOP_WR_RETRY_WQ", .pme_code = 0x716c6, .pme_short_desc = "Snoop write/dclaim retry due to collision with active write queue", .pme_long_desc = "A snoop request for a write or dclaim to memory was retried because it matched the cache line of an active write. The snoop request is retried and the active write is changed to high priority. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_SNOOP_WR_RETRY_WQ], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SNOOP_WR_RETRY_WQ] }, [ POWER5_PME_PM_CMPLU_STALL_REJECT ] = { .pme_name = "PM_CMPLU_STALL_REJECT", .pme_code = 0x41109a, .pme_short_desc = "Completion stall caused by reject", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a load/store reject. This is a subset of PM_CMPLU_STALL_LSU.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_CMPLU_STALL_REJECT], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_CMPLU_STALL_REJECT] }, [ POWER5_PME_PM_LSU1_REJECT_ERAT_MISS ] = { .pme_name = "PM_LSU1_REJECT_ERAT_MISS", .pme_code = 0xc60e7, .pme_short_desc = "LSU1 reject due to ERAT miss", .pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions due to an ERAT miss. Requests that miss the Derat are rejected and retried until the request hits in the Erat.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU1_REJECT_ERAT_MISS], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU1_REJECT_ERAT_MISS] }, [ POWER5_PME_PM_MRK_FXU_FIN ] = { .pme_name = "PM_MRK_FXU_FIN", .pme_code = 0x200014, .pme_short_desc = "Marked instruction FXU processing finished", .pme_long_desc = "One of the Fixed Point Units finished a marked instruction. Instructions that finish may not necessary complete.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_FXU_FIN], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_FXU_FIN] }, [ POWER5_PME_PM_L2SB_RCST_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2SB_RCST_DISP_FAIL_OTHER", .pme_code = 0x732e1, .pme_short_desc = "L2 slice B RC store dispatch attempt failed due to other reasons", .pme_long_desc = "A Read/Claim dispatch for a store failed for some reason other than Full or Collision conditions. Rejected dispatches do not count because they have not yet been attempted.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_RCST_DISP_FAIL_OTHER], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_RCST_DISP_FAIL_OTHER] }, [ POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY ] = { .pme_name = "PM_L2SC_RC_DISP_FAIL_CO_BUSY", .pme_code = 0x703c2, .pme_short_desc = "L2 slice C RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy", .pme_long_desc = "A Read/Claim Dispatch was rejected at dispatch because the Castout Machine was busy. In the case of an RC starting up on a miss and the victim is valid, the CO machine must be available for the RC to process the access. If the CO is still busy working on an old castout, then the RC must not-ack the access if it is a miss(re-issued by the CIU). If it is a miss and the CO is available to process the castout, the RC will accept the access. Once the RC has finished, it can restart and process new accesses that result in a hit (or miss that doesn't need a CO) even though the CO is still processing a castout from a previous access.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_RC_DISP_FAIL_CO_BUSY] }, [ POWER5_PME_PM_PMC4_OVERFLOW ] = { .pme_name = "PM_PMC4_OVERFLOW", .pme_code = 0x10000a, .pme_short_desc = "PMC4 Overflow", .pme_long_desc = "Overflows from PMC4 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_PMC4_OVERFLOW], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PMC4_OVERFLOW] }, [ POWER5_PME_PM_L3SA_SNOOP_RETRY ] = { .pme_name = "PM_L3SA_SNOOP_RETRY", .pme_code = 0x731e3, .pme_short_desc = "L3 slice A snoop retries", .pme_long_desc = "Number of times an L3 retried a snoop because it got two in at the same time (one on snp_a, one on snp_b)", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SA_SNOOP_RETRY], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SA_SNOOP_RETRY] }, [ POWER5_PME_PM_PTEG_FROM_L35_MOD ] = { .pme_name = "PM_PTEG_FROM_L35_MOD", .pme_code = 0x28309e, .pme_short_desc = "PTEG loaded from L3.5 modified", .pme_long_desc = "A Page Table Entry was loaded into the TLB with modified (M) data from the L3 of a chip on the same module as this processor is located, due to a demand load.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_PTEG_FROM_L35_MOD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PTEG_FROM_L35_MOD] }, [ POWER5_PME_PM_INST_FROM_L25_MOD ] = { .pme_name = "PM_INST_FROM_L25_MOD", .pme_code = 0x222096, .pme_short_desc = "Instruction fetched from L2.5 modified", .pme_long_desc = "An instruction fetch group was fetched with modified (M) data from the L2 of a chip on the same module as this processor is located. Fetch groups can contain up to 8 instructions.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_L25_MOD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_L25_MOD] }, [ POWER5_PME_PM_THRD_SMT_HANG ] = { .pme_name = "PM_THRD_SMT_HANG", .pme_code = 0x330e7, .pme_short_desc = "SMT hang detected", .pme_long_desc = "A hung thread was detected", .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_SMT_HANG], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_SMT_HANG] }, [ POWER5_PME_PM_CMPLU_STALL_ERAT_MISS ] = { .pme_name = "PM_CMPLU_STALL_ERAT_MISS", .pme_code = 0x41109b, .pme_short_desc = "Completion stall caused by ERAT miss", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered an ERAT miss. This is a subset of PM_CMPLU_STALL_REJECT.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_CMPLU_STALL_ERAT_MISS], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_CMPLU_STALL_ERAT_MISS] }, [ POWER5_PME_PM_L3SA_MOD_TAG ] = { .pme_name = "PM_L3SA_MOD_TAG", .pme_code = 0x720e3, .pme_short_desc = "L3 slice A transition from modified to TAG", .pme_long_desc = "L3 snooper detects someone doing a read to a line that is truly M in this L3(i.e. L3 going M->T or M->I(go_Mu case) Mu|Me are not included since they are formed due to a prev read op). Tx is not included since it is considered shared at this point.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SA_MOD_TAG], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SA_MOD_TAG] }, [ POWER5_PME_PM_FLUSH_SYNC ] = { .pme_name = "PM_FLUSH_SYNC", .pme_code = 0x330e1, .pme_short_desc = "Flush caused by sync", .pme_long_desc = "This thread has been flushed at dispatch due to a sync, lwsync, ptesync, or tlbsync instruction. This allows the other thread to have more machine resources for it to make progress until the sync finishes.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FLUSH_SYNC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FLUSH_SYNC] }, [ POWER5_PME_PM_INST_FROM_L2MISS ] = { .pme_name = "PM_INST_FROM_L2MISS", .pme_code = 0x12209b, .pme_short_desc = "Instruction fetched missed L2", .pme_long_desc = "An instruction fetch group was fetched from beyond the local L2.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_L2MISS], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_L2MISS] }, [ POWER5_PME_PM_L2SC_ST_HIT ] = { .pme_name = "PM_L2SC_ST_HIT", .pme_code = 0x733e2, .pme_short_desc = "L2 slice C store hits", .pme_long_desc = "A store request made from the core hit in the L2 directory. The event is provided on each of the three slices A, B, and C.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_ST_HIT], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_ST_HIT] }, [ POWER5_PME_PM_MEM_RQ_DISP_Q8to11 ] = { .pme_name = "PM_MEM_RQ_DISP_Q8to11", .pme_code = 0x722e6, .pme_short_desc = "Memory read queue dispatched to queues 8-11", .pme_long_desc = "A memory operation was dispatched to read queue 8,9,10 or 11. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_RQ_DISP_Q8to11], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_RQ_DISP_Q8to11] }, [ POWER5_PME_PM_MRK_GRP_DISP ] = { .pme_name = "PM_MRK_GRP_DISP", .pme_code = 0x100002, .pme_short_desc = "Marked group dispatched", .pme_long_desc = "A group containing a sampled instruction was dispatched", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_GRP_DISP], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_GRP_DISP] }, [ POWER5_PME_PM_L2SB_MOD_TAG ] = { .pme_name = "PM_L2SB_MOD_TAG", .pme_code = 0x720e1, .pme_short_desc = "L2 slice B transition from modified to tagged", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_MOD_TAG], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_MOD_TAG] }, [ POWER5_PME_PM_CLB_EMPTY_CYC ] = { .pme_name = "PM_CLB_EMPTY_CYC", .pme_code = 0x410c6, .pme_short_desc = "Cycles CLB empty", .pme_long_desc = "Cycles when both thread's CLB is completely empty.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_CLB_EMPTY_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_CLB_EMPTY_CYC] }, [ POWER5_PME_PM_L2SB_ST_HIT ] = { .pme_name = "PM_L2SB_ST_HIT", .pme_code = 0x733e1, .pme_short_desc = "L2 slice B store hits", .pme_long_desc = "A store request made from the core hit in the L2 directory. This event is provided on each of the three L2 slices A, B and C.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_ST_HIT], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_ST_HIT] }, [ POWER5_PME_PM_MEM_NONSPEC_RD_CANCEL ] = { .pme_name = "PM_MEM_NONSPEC_RD_CANCEL", .pme_code = 0x711c6, .pme_short_desc = "Non speculative memory read cancelled", .pme_long_desc = "A non-speculative read was cancelled because the combined response indicated it was sourced from aother L2 or L3. This event is sent from the Memory Controller clock domain and must be scaled accordingly", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_NONSPEC_RD_CANCEL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_NONSPEC_RD_CANCEL] }, [ POWER5_PME_PM_BR_PRED_CR_TA ] = { .pme_name = "PM_BR_PRED_CR_TA", .pme_code = 0x423087, .pme_short_desc = "A conditional branch was predicted", .pme_long_desc = " CR and target prediction", .pme_event_ids = power5_event_ids[POWER5_PME_PM_BR_PRED_CR_TA], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_BR_PRED_CR_TA] }, [ POWER5_PME_PM_MRK_LSU0_FLUSH_SRQ ] = { .pme_name = "PM_MRK_LSU0_FLUSH_SRQ", .pme_code = 0x810c3, .pme_short_desc = "LSU0 marked SRQ lhs flushes", .pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LSU0_FLUSH_SRQ], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LSU0_FLUSH_SRQ] }, [ POWER5_PME_PM_MRK_LSU_FLUSH_ULD ] = { .pme_name = "PM_MRK_LSU_FLUSH_ULD", .pme_code = 0x481090, .pme_short_desc = "Marked unaligned load flushes", .pme_long_desc = "A marked load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LSU_FLUSH_ULD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LSU_FLUSH_ULD] }, [ POWER5_PME_PM_INST_DISP_ATTEMPT ] = { .pme_name = "PM_INST_DISP_ATTEMPT", .pme_code = 0x120e1, .pme_short_desc = "Instructions dispatch attempted", .pme_long_desc = "Number of PowerPC Instructions dispatched (attempted, not filtered by success.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_DISP_ATTEMPT], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_DISP_ATTEMPT] }, [ POWER5_PME_PM_INST_FROM_RMEM ] = { .pme_name = "PM_INST_FROM_RMEM", .pme_code = 0x422086, .pme_short_desc = "Instruction fetched from remote memory", .pme_long_desc = "An instruction fetch group was fetched from memory attached to a different module than this proccessor is located on. Fetch groups can contain up to 8 instructions", .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_RMEM], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_RMEM] }, [ POWER5_PME_PM_ST_REF_L1_LSU0 ] = { .pme_name = "PM_ST_REF_L1_LSU0", .pme_code = 0xc10c1, .pme_short_desc = "LSU0 L1 D cache store references", .pme_long_desc = "Store references to the Data Cache by LSU0.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_ST_REF_L1_LSU0], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_ST_REF_L1_LSU0] }, [ POWER5_PME_PM_LSU0_DERAT_MISS ] = { .pme_name = "PM_LSU0_DERAT_MISS", .pme_code = 0x800c2, .pme_short_desc = "LSU0 DERAT misses", .pme_long_desc = "Total D-ERAT Misses by LSU0. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU0_DERAT_MISS], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU0_DERAT_MISS] }, [ POWER5_PME_PM_L2SB_RCLD_DISP ] = { .pme_name = "PM_L2SB_RCLD_DISP", .pme_code = 0x701c1, .pme_short_desc = "L2 slice B RC load dispatch attempt", .pme_long_desc = "A Read/Claim dispatch for a Load was attempted", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_RCLD_DISP], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_RCLD_DISP] }, [ POWER5_PME_PM_FPU_STALL3 ] = { .pme_name = "PM_FPU_STALL3", .pme_code = 0x202088, .pme_short_desc = "FPU stalled in pipe3", .pme_long_desc = "FPU has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. Combined Unit 0 + Unit 1.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU_STALL3], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU_STALL3] }, [ POWER5_PME_PM_BR_PRED_CR ] = { .pme_name = "PM_BR_PRED_CR", .pme_code = 0x230e2, .pme_short_desc = "A conditional branch was predicted", .pme_long_desc = " CR prediction", .pme_event_ids = power5_event_ids[POWER5_PME_PM_BR_PRED_CR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_BR_PRED_CR] }, [ POWER5_PME_PM_MRK_DATA_FROM_L2 ] = { .pme_name = "PM_MRK_DATA_FROM_L2", .pme_code = 0x1c7087, .pme_short_desc = "Marked data loaded from L2", .pme_long_desc = "The processor's Data Cache was reloaded from the local L2 due to a marked load.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L2], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L2] }, [ POWER5_PME_PM_LSU0_FLUSH_SRQ ] = { .pme_name = "PM_LSU0_FLUSH_SRQ", .pme_code = 0xc00c3, .pme_short_desc = "LSU0 SRQ lhs flushes", .pme_long_desc = "A store was flushed by unit 0 because younger load hits and older store that is already in the SRQ or in the same group.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU0_FLUSH_SRQ], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU0_FLUSH_SRQ] }, [ POWER5_PME_PM_FAB_PNtoNN_DIRECT ] = { .pme_name = "PM_FAB_PNtoNN_DIRECT", .pme_code = 0x703c7, .pme_short_desc = "PN to NN beat went straight to its destination", .pme_long_desc = "Fabric Data beats that the base chip takes the inbound PN data and passes it through to the outbound NN bus without going into a sidecar. The signal is delivered at FBC speed and the count must be scaled.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_PNtoNN_DIRECT], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_PNtoNN_DIRECT] }, [ POWER5_PME_PM_IOPS_CMPL ] = { .pme_name = "PM_IOPS_CMPL", .pme_code = 0x1, .pme_short_desc = "Internal operations completed", .pme_long_desc = "Number of internal operations that completed.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_IOPS_CMPL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_IOPS_CMPL] }, [ POWER5_PME_PM_L2SC_SHR_INV ] = { .pme_name = "PM_L2SC_SHR_INV", .pme_code = 0x710c2, .pme_short_desc = "L2 slice C transition from shared to invalid", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L, or Tagged) to the Invalid state. This transition was caused by any external snoop request. The event is provided on each of the three slices A, B, and C. NOTE: For this event to be useful the tablewalk duration event should also be counted.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_SHR_INV], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_SHR_INV] }, [ POWER5_PME_PM_L2SA_RCST_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2SA_RCST_DISP_FAIL_OTHER", .pme_code = 0x732e0, .pme_short_desc = "L2 slice A RC store dispatch attempt failed due to other reasons", .pme_long_desc = "A Read/Claim dispatch for a store failed for some reason other than Full or Collision conditions. Rejected dispatches do not count because they have not yet been attempted.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_RCST_DISP_FAIL_OTHER], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_RCST_DISP_FAIL_OTHER] }, [ POWER5_PME_PM_L2SA_RCST_DISP ] = { .pme_name = "PM_L2SA_RCST_DISP", .pme_code = 0x702c0, .pme_short_desc = "L2 slice A RC store dispatch attempt", .pme_long_desc = "A Read/Claim dispatch for a Store was attempted.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_RCST_DISP], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_RCST_DISP] }, [ POWER5_PME_PM_SNOOP_RETRY_AB_COLLISION ] = { .pme_name = "PM_SNOOP_RETRY_AB_COLLISION", .pme_code = 0x735e6, .pme_short_desc = "Snoop retry due to a b collision", .pme_long_desc = "Snoop retry due to a b collision", .pme_event_ids = power5_event_ids[POWER5_PME_PM_SNOOP_RETRY_AB_COLLISION], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SNOOP_RETRY_AB_COLLISION] }, [ POWER5_PME_PM_FAB_PNtoVN_SIDECAR ] = { .pme_name = "PM_FAB_PNtoVN_SIDECAR", .pme_code = 0x733e7, .pme_short_desc = "PN to VN beat went to sidecar first", .pme_long_desc = "Fabric data beats that the base chip takes the inbound PN data and forwards it on to the outbound VN data bus after going into a sidecar first. The signal is delivered at FBC speed and the count must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_PNtoVN_SIDECAR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_PNtoVN_SIDECAR] }, [ POWER5_PME_PM_LSU_LMQ_S0_ALLOC ] = { .pme_name = "PM_LSU_LMQ_S0_ALLOC", .pme_code = 0xc30e6, .pme_short_desc = "LMQ slot 0 allocated", .pme_long_desc = "The first entry in the LMQ was allocated.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_LMQ_S0_ALLOC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_LMQ_S0_ALLOC] }, [ POWER5_PME_PM_LSU0_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU0_REJECT_LMQ_FULL", .pme_code = 0xc60e1, .pme_short_desc = "LSU0 reject due to LMQ full or missed data coming", .pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU0_REJECT_LMQ_FULL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU0_REJECT_LMQ_FULL] }, [ POWER5_PME_PM_SNOOP_PW_RETRY_RQ ] = { .pme_name = "PM_SNOOP_PW_RETRY_RQ", .pme_code = 0x707c6, .pme_short_desc = "Snoop partial-write retry due to collision with active read queue", .pme_long_desc = "A snoop request for a partial write to memory was retried because it matched the cache line of an active read. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_SNOOP_PW_RETRY_RQ], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SNOOP_PW_RETRY_RQ] }, [ POWER5_PME_PM_DTLB_REF ] = { .pme_name = "PM_DTLB_REF", .pme_code = 0x2c4090, .pme_short_desc = "Data TLB references", .pme_long_desc = "Total number of Data TLB references for all page sizes. Page size is determined at TLB reload time.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_DTLB_REF], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DTLB_REF] }, [ POWER5_PME_PM_PTEG_FROM_L3 ] = { .pme_name = "PM_PTEG_FROM_L3", .pme_code = 0x18308e, .pme_short_desc = "PTEG loaded from L3", .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local L3 due to a demand load.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_PTEG_FROM_L3], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PTEG_FROM_L3] }, [ POWER5_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY ] = { .pme_name = "PM_FAB_M1toVNorNN_SIDECAR_EMPTY", .pme_code = 0x712c7, .pme_short_desc = "M1 to VN/NN sidecar empty", .pme_long_desc = "Fabric cycles when the Minus-1 jump sidecar (sidecars for mcm to mcm data transfer) is empty. The signal is delivered at FBC speed and the count must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FAB_M1toVNorNN_SIDECAR_EMPTY] }, [ POWER5_PME_PM_LSU_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_SRQ_EMPTY_CYC", .pme_code = 0x400015, .pme_short_desc = "Cycles SRQ empty", .pme_long_desc = "Cycles the Store Request Queue is empty", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_SRQ_EMPTY_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_SRQ_EMPTY_CYC] }, [ POWER5_PME_PM_FPU1_STF ] = { .pme_name = "PM_FPU1_STF", .pme_code = 0x20e6, .pme_short_desc = "FPU1 executed store instruction", .pme_long_desc = "FPU1 has executed a Floating Point Store instruction.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU1_STF], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU1_STF] }, [ POWER5_PME_PM_LSU_LMQ_S0_VALID ] = { .pme_name = "PM_LSU_LMQ_S0_VALID", .pme_code = 0xc30e5, .pme_short_desc = "LMQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle when the first entry in the LMQ is valid. The LMQ had eight entries that are allocated FIFO", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_LMQ_S0_VALID], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_LMQ_S0_VALID] }, [ POWER5_PME_PM_GCT_USAGE_00to59_CYC ] = { .pme_name = "PM_GCT_USAGE_00to59_CYC", .pme_code = 0x10001f, .pme_short_desc = "Cycles GCT less than 60% full", .pme_long_desc = "Cycles when the Global Completion Table has fewer than 60% of its slots used. The GCT has 20 entries shared between threads.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_GCT_USAGE_00to59_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GCT_USAGE_00to59_CYC] }, [ POWER5_PME_PM_DATA_FROM_L2MISS ] = { .pme_name = "PM_DATA_FROM_L2MISS", .pme_code = 0x3c309b, .pme_short_desc = "Data loaded missed L2", .pme_long_desc = "The processor's Data Cache was reloaded but not from the local L2.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_DATA_FROM_L2MISS], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DATA_FROM_L2MISS] }, [ POWER5_PME_PM_GRP_DISP_BLK_SB_CYC ] = { .pme_name = "PM_GRP_DISP_BLK_SB_CYC", .pme_code = 0x130e1, .pme_short_desc = "Cycles group dispatch blocked by scoreboard", .pme_long_desc = "A scoreboard operation on a non-renamed resource has blocked dispatch.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_GRP_DISP_BLK_SB_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GRP_DISP_BLK_SB_CYC] }, [ POWER5_PME_PM_FPU_FMOV_FEST ] = { .pme_name = "PM_FPU_FMOV_FEST", .pme_code = 0x301088, .pme_short_desc = "FPU executed FMOV or FEST instructions", .pme_long_desc = "The floating point unit has executed a move kind of instruction or one of the estimate instructions. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ.. Combined Unit 0 + Unit 1.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU_FMOV_FEST], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU_FMOV_FEST] }, [ POWER5_PME_PM_XER_MAP_FULL_CYC ] = { .pme_name = "PM_XER_MAP_FULL_CYC", .pme_code = 0x100c2, .pme_short_desc = "Cycles XER mapper full", .pme_long_desc = "The XER mapper cannot accept any more groups. This condition will prevent dispatch groups from being dispatched. This event only indicates that the mapper was full, not that dispatch was prevented.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_XER_MAP_FULL_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_XER_MAP_FULL_CYC] }, [ POWER5_PME_PM_FLUSH_SB ] = { .pme_name = "PM_FLUSH_SB", .pme_code = 0x330e2, .pme_short_desc = "Flush caused by scoreboard operation", .pme_long_desc = "This thread has been flushed at dispatch because its scoreboard bit is set indicating that a non-renamed resource is being updated. This allows the other thread to have more machine resources for it to make progress while this thread is stalled.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FLUSH_SB], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FLUSH_SB] }, [ POWER5_PME_PM_MRK_DATA_FROM_L375_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L375_SHR", .pme_code = 0x3c709e, .pme_short_desc = "Marked data loaded from L3.75 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (S) data from the L3 of a chip on a different module than this processor is located due to a marked load.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L375_SHR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L375_SHR] }, [ POWER5_PME_PM_MRK_GRP_CMPL ] = { .pme_name = "PM_MRK_GRP_CMPL", .pme_code = 0x400013, .pme_short_desc = "Marked group completed", .pme_long_desc = "A group containing a sampled instruction completed. Microcoded instructions that span multiple groups will generate this event once per group.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_GRP_CMPL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_GRP_CMPL] }, [ POWER5_PME_PM_SUSPENDED ] = { .pme_name = "PM_SUSPENDED", .pme_code = 0x0, .pme_short_desc = "Suspended", .pme_long_desc = "The counter is suspended (does not count).", .pme_event_ids = power5_event_ids[POWER5_PME_PM_SUSPENDED], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SUSPENDED] }, [ POWER5_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC ] = { .pme_name = "PM_GRP_IC_MISS_BR_REDIR_NONSPEC", .pme_code = 0x120e5, .pme_short_desc = "Group experienced non-speculative I cache miss or branch redirect", .pme_long_desc = "Group experienced non-speculative I cache miss or branch redirect", .pme_event_ids = power5_event_ids[POWER5_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GRP_IC_MISS_BR_REDIR_NONSPEC] }, [ POWER5_PME_PM_SNOOP_RD_RETRY_QFULL ] = { .pme_name = "PM_SNOOP_RD_RETRY_QFULL", .pme_code = 0x700c6, .pme_short_desc = "Snoop read retry due to read queue full", .pme_long_desc = "A snoop request for a read from memory was retried because the read queues were full. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_SNOOP_RD_RETRY_QFULL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_SNOOP_RD_RETRY_QFULL] }, [ POWER5_PME_PM_L3SB_MOD_INV ] = { .pme_name = "PM_L3SB_MOD_INV", .pme_code = 0x730e4, .pme_short_desc = "L3 slice B transition from modified to invalid", .pme_long_desc = "L3 snooper detects someone doing a store to a line that is truly M in this L3 (i.e. L3 going M=>I). Mu|Me are not included since they are formed due to a prev read op. Tx is not included since it is considered shared at this point.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SB_MOD_INV], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SB_MOD_INV] }, [ POWER5_PME_PM_DATA_FROM_L35_SHR ] = { .pme_name = "PM_DATA_FROM_L35_SHR", .pme_code = 0x1c309e, .pme_short_desc = "Data loaded from L3.5 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (S) data from the L3 of a chip on the same module as this processor is located due to a demand load.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_DATA_FROM_L35_SHR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DATA_FROM_L35_SHR] }, [ POWER5_PME_PM_LD_MISS_L1_LSU1 ] = { .pme_name = "PM_LD_MISS_L1_LSU1", .pme_code = 0xc10c6, .pme_short_desc = "LSU1 L1 D cache load misses", .pme_long_desc = "Load references that miss the Level 1 Data cache, by unit 1.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LD_MISS_L1_LSU1], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LD_MISS_L1_LSU1] }, [ POWER5_PME_PM_STCX_FAIL ] = { .pme_name = "PM_STCX_FAIL", .pme_code = 0x820e1, .pme_short_desc = "STCX failed", .pme_long_desc = "A stcx (stwcx or stdcx) failed", .pme_event_ids = power5_event_ids[POWER5_PME_PM_STCX_FAIL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_STCX_FAIL] }, [ POWER5_PME_PM_DC_PREF_DST ] = { .pme_name = "PM_DC_PREF_DST", .pme_code = 0x830e6, .pme_short_desc = "DST (Data Stream Touch) stream start", .pme_long_desc = "A prefetch stream was started using the DST instruction.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_DC_PREF_DST], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DC_PREF_DST] }, [ POWER5_PME_PM_GRP_DISP ] = { .pme_name = "PM_GRP_DISP", .pme_code = 0x200002, .pme_short_desc = "Group dispatches", .pme_long_desc = "A group was dispatched", .pme_event_ids = power5_event_ids[POWER5_PME_PM_GRP_DISP], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_GRP_DISP] }, [ POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2SA_RCLD_DISP_FAIL_ADDR", .pme_code = 0x711c0, .pme_short_desc = "L2 slice A RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = "A Read/Claim dispatch for a load failed because of an address conflict. Two RC machines will never both work on the same line or line in the same congruence class at the same time.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_RCLD_DISP_FAIL_ADDR] }, [ POWER5_PME_PM_FPU0_FPSCR ] = { .pme_name = "PM_FPU0_FPSCR", .pme_code = 0x30e0, .pme_short_desc = "FPU0 executed FPSCR instruction", .pme_long_desc = "FPU0 has executed FPSCR move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*, mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU0_FPSCR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU0_FPSCR] }, [ POWER5_PME_PM_DATA_FROM_L2 ] = { .pme_name = "PM_DATA_FROM_L2", .pme_code = 0x1c3087, .pme_short_desc = "Data loaded from L2", .pme_long_desc = "The processor's Data Cache was reloaded from the local L2 due to a demand load.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_DATA_FROM_L2], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DATA_FROM_L2] }, [ POWER5_PME_PM_FPU1_DENORM ] = { .pme_name = "PM_FPU1_DENORM", .pme_code = 0x20e4, .pme_short_desc = "FPU1 received denormalized data", .pme_long_desc = "FPU1 has encountered a denormalized operand.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU1_DENORM], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU1_DENORM] }, [ POWER5_PME_PM_FPU_1FLOP ] = { .pme_name = "PM_FPU_1FLOP", .pme_code = 0x100090, .pme_short_desc = "FPU executed one flop instruction", .pme_long_desc = "The floating point unit has executed an add, mult, sub, compare, fsel, fneg, fabs, fnabs, fres, or frsqrte kind of instruction. These are single FLOP operations.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU_1FLOP], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU_1FLOP] }, [ POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2SC_RCLD_DISP_FAIL_OTHER", .pme_code = 0x731e2, .pme_short_desc = "L2 slice C RC load dispatch attempt failed due to other reasons", .pme_long_desc = "A Read/Claim dispatch for a load failed for some reason other than Full or Collision conditions.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_RCLD_DISP_FAIL_OTHER] }, [ POWER5_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL ] = { .pme_name = "PM_L2SC_RCST_DISP_FAIL_RC_FULL", .pme_code = 0x722e2, .pme_short_desc = "L2 slice C RC store dispatch attempt failed due to all RC full", .pme_long_desc = "A Read/Claim dispatch for a store failed because all RC machines are busy.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_RCST_DISP_FAIL_RC_FULL] }, [ POWER5_PME_PM_FPU0_FSQRT ] = { .pme_name = "PM_FPU0_FSQRT", .pme_code = 0xc2, .pme_short_desc = "FPU0 executed FSQRT instruction", .pme_long_desc = "FPU0 has executed a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU0_FSQRT], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU0_FSQRT] }, [ POWER5_PME_PM_LD_REF_L1 ] = { .pme_name = "PM_LD_REF_L1", .pme_code = 0x4c1090, .pme_short_desc = "L1 D cache load references", .pme_long_desc = "Load references to the Level 1 Data Cache. Combined unit 0 + 1.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LD_REF_L1], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LD_REF_L1] }, [ POWER5_PME_PM_INST_FROM_L1 ] = { .pme_name = "PM_INST_FROM_L1", .pme_code = 0x22208d, .pme_short_desc = "Instruction fetched from L1", .pme_long_desc = "An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions", .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_L1], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_L1] }, [ POWER5_PME_PM_TLBIE_HELD ] = { .pme_name = "PM_TLBIE_HELD", .pme_code = 0x130e4, .pme_short_desc = "TLBIE held at dispatch", .pme_long_desc = "Cycles a TLBIE instruction was held at dispatch.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_TLBIE_HELD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_TLBIE_HELD] }, [ POWER5_PME_PM_DC_PREF_OUT_OF_STREAMS ] = { .pme_name = "PM_DC_PREF_OUT_OF_STREAMS", .pme_code = 0xc50c2, .pme_short_desc = "D cache out of prefetch streams", .pme_long_desc = "A new prefetch stream was detected but no more stream entries were available.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_DC_PREF_OUT_OF_STREAMS], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DC_PREF_OUT_OF_STREAMS] }, [ POWER5_PME_PM_MRK_DATA_FROM_L25_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L25_MOD_CYC", .pme_code = 0x4c70a2, .pme_short_desc = "Marked load latency from L2.5 modified", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L25_MOD_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L25_MOD_CYC] }, [ POWER5_PME_PM_MRK_LSU1_FLUSH_SRQ ] = { .pme_name = "PM_MRK_LSU1_FLUSH_SRQ", .pme_code = 0x810c7, .pme_short_desc = "LSU1 marked SRQ lhs flushes", .pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LSU1_FLUSH_SRQ], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LSU1_FLUSH_SRQ] }, [ POWER5_PME_PM_MEM_RQ_DISP_Q0to3 ] = { .pme_name = "PM_MEM_RQ_DISP_Q0to3", .pme_code = 0x702c6, .pme_short_desc = "Memory read queue dispatched to queues 0-3", .pme_long_desc = "A memory operation was dispatched to read queue 0,1,2, or 3. This event is sent from the Memory Controller clock domain and must be scaled accordingly.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MEM_RQ_DISP_Q0to3], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MEM_RQ_DISP_Q0to3] }, [ POWER5_PME_PM_ST_REF_L1_LSU1 ] = { .pme_name = "PM_ST_REF_L1_LSU1", .pme_code = 0xc10c5, .pme_short_desc = "LSU1 L1 D cache store references", .pme_long_desc = "Store references to the Data Cache by LSU1.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_ST_REF_L1_LSU1], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_ST_REF_L1_LSU1] }, [ POWER5_PME_PM_MRK_LD_MISS_L1 ] = { .pme_name = "PM_MRK_LD_MISS_L1", .pme_code = 0x182088, .pme_short_desc = "Marked L1 D cache load misses", .pme_long_desc = "Marked L1 D cache load misses", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LD_MISS_L1], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LD_MISS_L1] }, [ POWER5_PME_PM_L1_WRITE_CYC ] = { .pme_name = "PM_L1_WRITE_CYC", .pme_code = 0x230e7, .pme_short_desc = "Cycles writing to instruction L1", .pme_long_desc = "Cycles that a cache line was written to the instruction cache.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L1_WRITE_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L1_WRITE_CYC] }, [ POWER5_PME_PM_L2SC_ST_REQ ] = { .pme_name = "PM_L2SC_ST_REQ", .pme_code = 0x723e2, .pme_short_desc = "L2 slice C store requests", .pme_long_desc = "A store request as seen at the L2 directory has been made from the core. Stores are counted after gathering in the L2 store queues. The event is provided on each of the three slices A, B, and C.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_ST_REQ], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_ST_REQ] }, [ POWER5_PME_PM_CMPLU_STALL_FDIV ] = { .pme_name = "PM_CMPLU_STALL_FDIV", .pme_code = 0x21109b, .pme_short_desc = "Completion stall caused by FDIV or FQRT instruction", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a floating point divide or square root instruction. This is a subset of PM_CMPLU_STALL_FPU.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_CMPLU_STALL_FDIV], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_CMPLU_STALL_FDIV] }, [ POWER5_PME_PM_THRD_SEL_OVER_CLB_EMPTY ] = { .pme_name = "PM_THRD_SEL_OVER_CLB_EMPTY", .pme_code = 0x410c2, .pme_short_desc = "Thread selection overrides caused by CLB empty", .pme_long_desc = "Thread selection was overridden because one thread's CLB was empty.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_SEL_OVER_CLB_EMPTY], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_SEL_OVER_CLB_EMPTY] }, [ POWER5_PME_PM_BR_MPRED_CR ] = { .pme_name = "PM_BR_MPRED_CR", .pme_code = 0x230e5, .pme_short_desc = "Branch mispredictions due to CR bit setting", .pme_long_desc = "A conditional branch instruction was incorrectly predicted as taken or not taken. The branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_BR_MPRED_CR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_BR_MPRED_CR] }, [ POWER5_PME_PM_L3SB_MOD_TAG ] = { .pme_name = "PM_L3SB_MOD_TAG", .pme_code = 0x720e4, .pme_short_desc = "L3 slice B transition from modified to TAG", .pme_long_desc = "L3 snooper detects someone doing a read to a line that is truly M in this L3(i.e. L3 going M->T or M->I(go_Mu case); Mu|Me are not included since they are formed due to a prev read op). Tx is not included since it is considered shared at this point.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SB_MOD_TAG], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SB_MOD_TAG] }, [ POWER5_PME_PM_MRK_DATA_FROM_L2MISS ] = { .pme_name = "PM_MRK_DATA_FROM_L2MISS", .pme_code = 0x3c709b, .pme_short_desc = "Marked data loaded missed L2", .pme_long_desc = "DL1 was reloaded from beyond L2 due to a marked demand load.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_DATA_FROM_L2MISS], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_DATA_FROM_L2MISS] }, [ POWER5_PME_PM_LSU_REJECT_SRQ ] = { .pme_name = "PM_LSU_REJECT_SRQ", .pme_code = 0x1c6088, .pme_short_desc = "LSU SRQ lhs rejects", .pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions because of Load Hit Store conditions. Loads are rejected when data is needed from a previous store instruction but store forwarding is not possible because the data is not fully contained in the Store Data Queue or is not yet available in the Store Data Queue. Combined Unit 0 + 1.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_REJECT_SRQ], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_REJECT_SRQ] }, [ POWER5_PME_PM_LD_MISS_L1 ] = { .pme_name = "PM_LD_MISS_L1", .pme_code = 0x3c1088, .pme_short_desc = "L1 D cache load misses", .pme_long_desc = "Load references that miss the Level 1 Data cache. Combined unit 0 + 1.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LD_MISS_L1], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LD_MISS_L1] }, [ POWER5_PME_PM_INST_FROM_PREF ] = { .pme_name = "PM_INST_FROM_PREF", .pme_code = 0x32208d, .pme_short_desc = "Instruction fetched from prefetch", .pme_long_desc = "An instruction fetch group was fetched from the prefetch buffer. Fetch groups can contain up to 8 instructions", .pme_event_ids = power5_event_ids[POWER5_PME_PM_INST_FROM_PREF], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_INST_FROM_PREF] }, [ POWER5_PME_PM_DC_INV_L2 ] = { .pme_name = "PM_DC_INV_L2", .pme_code = 0xc10c7, .pme_short_desc = "L1 D cache entries invalidated from L2", .pme_long_desc = "A dcache invalidated was received from the L2 because a line in L2 was castout.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_DC_INV_L2], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DC_INV_L2] }, [ POWER5_PME_PM_STCX_PASS ] = { .pme_name = "PM_STCX_PASS", .pme_code = 0x820e5, .pme_short_desc = "Stcx passes", .pme_long_desc = "A stcx (stwcx or stdcx) instruction was successful", .pme_event_ids = power5_event_ids[POWER5_PME_PM_STCX_PASS], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_STCX_PASS] }, [ POWER5_PME_PM_LSU_SRQ_FULL_CYC ] = { .pme_name = "PM_LSU_SRQ_FULL_CYC", .pme_code = 0x110c3, .pme_short_desc = "Cycles SRQ full", .pme_long_desc = "Cycles the Store Request Queue is full.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_SRQ_FULL_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_SRQ_FULL_CYC] }, [ POWER5_PME_PM_FPU_FIN ] = { .pme_name = "PM_FPU_FIN", .pme_code = 0x401088, .pme_short_desc = "FPU produced a result", .pme_long_desc = "FPU finished, produced a result. This only indicates finish, not completion. Combined Unit 0 + Unit 1. Floating Point Stores are included in this count but not Floating Point Loads., , , XYZs", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU_FIN], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU_FIN] }, [ POWER5_PME_PM_L2SA_SHR_MOD ] = { .pme_name = "PM_L2SA_SHR_MOD", .pme_code = 0x700c0, .pme_short_desc = "L2 slice A transition from shared to modified", .pme_long_desc = "A cache line in the local L2 directory made a state transition from Shared (Shared, Shared L , or Tagged) to the Modified state. This transition was caused by a store from either of the two local CPUs to a cache line in any of the Shared states. The event is provided on each of the three slices A, B, and C. ", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_SHR_MOD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_SHR_MOD] }, [ POWER5_PME_PM_LSU_SRQ_STFWD ] = { .pme_name = "PM_LSU_SRQ_STFWD", .pme_code = 0x1c2088, .pme_short_desc = "SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. Combined Unit 0 + 1.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU_SRQ_STFWD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU_SRQ_STFWD] }, [ POWER5_PME_PM_0INST_CLB_CYC ] = { .pme_name = "PM_0INST_CLB_CYC", .pme_code = 0x400c0, .pme_short_desc = "Cycles no instructions in CLB", .pme_long_desc = "The cache line buffer (CLB) is a 6-deep, 4-wide instruction buffer. Fullness is reported on a cycle basis with each event representing the number of cycles the CLB had the corresponding number of entries occupied. These events give a real time history of the number of instruction buffers used, but not the number of PowerPC instructions within those buffers. Each thread has its own set of CLB; these events are thread specific.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_0INST_CLB_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_0INST_CLB_CYC] }, [ POWER5_PME_PM_FXU0_FIN ] = { .pme_name = "PM_FXU0_FIN", .pme_code = 0x130e2, .pme_short_desc = "FXU0 produced a result", .pme_long_desc = "The Fixed Point unit 0 finished an instruction and produced a result. Instructions that finish may not necessary complete.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FXU0_FIN], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FXU0_FIN] }, [ POWER5_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL ] = { .pme_name = "PM_L2SB_RCST_DISP_FAIL_RC_FULL", .pme_code = 0x722e1, .pme_short_desc = "L2 slice B RC store dispatch attempt failed due to all RC full", .pme_long_desc = "A Read/Claim dispatch for a store failed because all RC machines are busy.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_RCST_DISP_FAIL_RC_FULL] }, [ POWER5_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = { .pme_name = "PM_THRD_GRP_CMPL_BOTH_CYC", .pme_code = 0x200013, .pme_short_desc = "Cycles group completed by both threads", .pme_long_desc = "Cycles that both threads completed.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_GRP_CMPL_BOTH_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_GRP_CMPL_BOTH_CYC] }, [ POWER5_PME_PM_PMC5_OVERFLOW ] = { .pme_name = "PM_PMC5_OVERFLOW", .pme_code = 0x10001a, .pme_short_desc = "PMC5 Overflow", .pme_long_desc = "Overflows from PMC5 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_PMC5_OVERFLOW], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PMC5_OVERFLOW] }, [ POWER5_PME_PM_FPU0_FDIV ] = { .pme_name = "PM_FPU0_FDIV", .pme_code = 0xc0, .pme_short_desc = "FPU0 executed FDIV instruction", .pme_long_desc = "FPU0 has executed a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_FPU0_FDIV], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_FPU0_FDIV] }, [ POWER5_PME_PM_PTEG_FROM_L375_SHR ] = { .pme_name = "PM_PTEG_FROM_L375_SHR", .pme_code = 0x38309e, .pme_short_desc = "PTEG loaded from L3.75 shared", .pme_long_desc = "A Page Table Entry was loaded into the TLB with shared (S) data from the L3 of a chip on a different module than this processor is located, due to a demand load.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_PTEG_FROM_L375_SHR], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_PTEG_FROM_L375_SHR] }, [ POWER5_PME_PM_LD_REF_L1_LSU1 ] = { .pme_name = "PM_LD_REF_L1_LSU1", .pme_code = 0xc10c4, .pme_short_desc = "LSU1 L1 D cache load references", .pme_long_desc = "Load references to Level 1 Data Cache, by unit 1.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LD_REF_L1_LSU1], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LD_REF_L1_LSU1] }, [ POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY ] = { .pme_name = "PM_L2SA_RC_DISP_FAIL_CO_BUSY", .pme_code = 0x703c0, .pme_short_desc = "L2 slice A RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy", .pme_long_desc = "A Read/Claim Dispatch was rejected at dispatch because the Castout Machine was busy. In the case of an RC starting up on a miss and the victim is valid, the CO machine must be available for the RC to process the access. If the CO is still busy working on an old castout, then the RC must not-ack the access if it is a miss(re-issued by the CIU). If it is a miss and the CO is available to process the castout, the RC will accept the access. Once the RC has finished, it can restart and process new accesses that result in a hit (or miss that doesn't need a CO) even though the CO is still processing a castout from a previous access.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SA_RC_DISP_FAIL_CO_BUSY] }, [ POWER5_PME_PM_HV_CYC ] = { .pme_name = "PM_HV_CYC", .pme_code = 0x20000b, .pme_short_desc = "Hypervisor Cycles", .pme_long_desc = "Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0)", .pme_event_ids = power5_event_ids[POWER5_PME_PM_HV_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_HV_CYC] }, [ POWER5_PME_PM_THRD_PRIO_DIFF_0_CYC ] = { .pme_name = "PM_THRD_PRIO_DIFF_0_CYC", .pme_code = 0x430e3, .pme_short_desc = "Cycles no thread priority difference", .pme_long_desc = "Cycles when this thread's priority is equal to the other thread's priority.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_THRD_PRIO_DIFF_0_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_THRD_PRIO_DIFF_0_CYC] }, [ POWER5_PME_PM_LR_CTR_MAP_FULL_CYC ] = { .pme_name = "PM_LR_CTR_MAP_FULL_CYC", .pme_code = 0x100c6, .pme_short_desc = "Cycles LR/CTR mapper full", .pme_long_desc = "The LR/CTR mapper cannot accept any more groups. This condition will prevent dispatch groups from being dispatched. This event only indicates that the mapper was full, not that dispatch was prevented.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LR_CTR_MAP_FULL_CYC], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LR_CTR_MAP_FULL_CYC] }, [ POWER5_PME_PM_L3SB_SHR_INV ] = { .pme_name = "PM_L3SB_SHR_INV", .pme_code = 0x710c4, .pme_short_desc = "L3 slice B transition from shared to invalid", .pme_long_desc = "L3 snooper detects someone doing a store to a line that is Sx in this L3(i.e. invalidate hit SX and dispatched).", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L3SB_SHR_INV], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L3SB_SHR_INV] }, [ POWER5_PME_PM_DATA_FROM_RMEM ] = { .pme_name = "PM_DATA_FROM_RMEM", .pme_code = 0x1c30a1, .pme_short_desc = "Data loaded from remote memory", .pme_long_desc = "The processor's Data Cache was reloaded from memory attached to a different module than this proccessor is located on.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_DATA_FROM_RMEM], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DATA_FROM_RMEM] }, [ POWER5_PME_PM_DATA_FROM_L275_MOD ] = { .pme_name = "PM_DATA_FROM_L275_MOD", .pme_code = 0x1c30a3, .pme_short_desc = "Data loaded from L2.75 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from the L2 on a different module than this processor is located due to a demand load. ", .pme_event_ids = power5_event_ids[POWER5_PME_PM_DATA_FROM_L275_MOD], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DATA_FROM_L275_MOD] }, [ POWER5_PME_PM_LSU0_REJECT_SRQ ] = { .pme_name = "PM_LSU0_REJECT_SRQ", .pme_code = 0xc60e0, .pme_short_desc = "LSU0 SRQ lhs rejects", .pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions because of Load Hit Store conditions. Loads are rejected when data is needed from a previous store instruction but store forwarding is not possible because the data is not fully contained in the Store Data Queue or is not yet available in the Store Data Queue.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU0_REJECT_SRQ], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU0_REJECT_SRQ] }, [ POWER5_PME_PM_LSU1_DERAT_MISS ] = { .pme_name = "PM_LSU1_DERAT_MISS", .pme_code = 0x800c6, .pme_short_desc = "LSU1 DERAT misses", .pme_long_desc = "A data request (load or store) from LSU Unit 1 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU1_DERAT_MISS], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU1_DERAT_MISS] }, [ POWER5_PME_PM_MRK_LSU_FIN ] = { .pme_name = "PM_MRK_LSU_FIN", .pme_code = 0x400014, .pme_short_desc = "Marked instruction LSU processing finished", .pme_long_desc = "One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete", .pme_event_ids = power5_event_ids[POWER5_PME_PM_MRK_LSU_FIN], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_MRK_LSU_FIN] }, [ POWER5_PME_PM_DTLB_MISS_16M ] = { .pme_name = "PM_DTLB_MISS_16M", .pme_code = 0xc40c4, .pme_short_desc = "Data TLB miss for 16M page", .pme_long_desc = "Data TLB references to 16MB pages that missed the TLB. Page size is determined at TLB reload time.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_DTLB_MISS_16M], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_DTLB_MISS_16M] }, [ POWER5_PME_PM_LSU0_FLUSH_UST ] = { .pme_name = "PM_LSU0_FLUSH_UST", .pme_code = 0xc00c1, .pme_short_desc = "LSU0 unaligned store flushes", .pme_long_desc = "A store was flushed from unit 0 because it was unaligned (crossed a 4K boundary).", .pme_event_ids = power5_event_ids[POWER5_PME_PM_LSU0_FLUSH_UST], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_LSU0_FLUSH_UST] }, [ POWER5_PME_PM_L2SC_MOD_TAG ] = { .pme_name = "PM_L2SC_MOD_TAG", .pme_code = 0x720e2, .pme_short_desc = "L2 slice C transition from modified to tagged", .pme_long_desc = "A cache line in the local L2 directory made a state transition from the Modified state to the Tagged state. This transition was caused by a read snoop request that hit against a modified entry in the local L2. The event is provided on each of the three slices A, B, and C.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SC_MOD_TAG], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SC_MOD_TAG] }, [ POWER5_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY ] = { .pme_name = "PM_L2SB_RC_DISP_FAIL_CO_BUSY", .pme_code = 0x703c1, .pme_short_desc = "L2 slice B RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy", .pme_long_desc = "A Read/Claim Dispatch was rejected at dispatch because the Castout Machine was busy. In the case of an RC starting up on a miss and the victim is valid, the CO machine must be available for the RC to process the access. If the CO is still busy working on an old castout, then the RC must not-ack the access if it is a miss(re-issued by the CIU). If it is a miss and the CO is available to process the castout, the RC will accept the access. Once the RC has finished, it can restart and process new accesses that result in a hit (or miss that doesn't need a CO) even though the CO is still processing a castout from a previous access.", .pme_event_ids = power5_event_ids[POWER5_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY], .pme_group_vector = power5_group_vecs[POWER5_PME_PM_L2SB_RC_DISP_FAIL_CO_BUSY] } }; #define POWER5_PME_EVENT_COUNT 474 static const int power5_group_event_ids[][POWER5_NUM_EVENT_COUNTERS] = { [ 0 ] = { 190, 71, 56, 12, 0, 0 }, [ 1 ] = { 2, 195, 49, 12, 0, 0 }, [ 2 ] = { 66, 65, 50, 60, 0, 0 }, [ 3 ] = { 0, 2, 169, 138, 0, 0 }, [ 4 ] = { 6, 6, 149, 59, 0, 0 }, [ 5 ] = { 60, 59, 46, 51, 0, 0 }, [ 6 ] = { 62, 61, 47, 52, 0, 0 }, [ 7 ] = { 143, 143, 113, 119, 0, 0 }, [ 8 ] = { 147, 147, 119, 123, 0, 0 }, [ 9 ] = { 149, 141, 112, 122, 0, 0 }, [ 10 ] = { 212, 73, 117, 18, 0, 0 }, [ 11 ] = { 73, 9, 61, 58, 0, 0 }, [ 12 ] = { 139, 1, 87, 59, 0, 0 }, [ 13 ] = { 126, 135, 13, 91, 0, 0 }, [ 14 ] = { 145, 144, 25, 159, 0, 0 }, [ 15 ] = { 125, 134, 55, 66, 0, 0 }, [ 16 ] = { 123, 132, 120, 191, 0, 0 }, [ 17 ] = { 124, 133, 55, 1, 0, 0 }, [ 18 ] = { 146, 145, 109, 31, 0, 0 }, [ 19 ] = { 73, 140, 25, 16, 0, 0 }, [ 20 ] = { 81, 71, 27, 33, 0, 0 }, [ 21 ] = { 141, 138, 55, 113, 0, 0 }, [ 22 ] = { 119, 128, 109, 59, 0, 0 }, [ 23 ] = { 120, 129, 55, 113, 0, 0 }, [ 24 ] = { 142, 140, 0, 59, 0, 0 }, [ 25 ] = { 121, 130, 109, 59, 0, 0 }, [ 26 ] = { 122, 131, 55, 113, 0, 0 }, [ 27 ] = { 140, 71, 147, 114, 0, 0 }, [ 28 ] = { 70, 13, 55, 10, 0, 0 }, [ 29 ] = { 73, 10, 6, 8, 0, 0 }, [ 30 ] = { 68, 12, 55, 7, 0, 0 }, [ 31 ] = { 57, 11, 55, 9, 0, 0 }, [ 32 ] = { 115, 7, 116, 116, 0, 0 }, [ 33 ] = { 41, 49, 40, 46, 0, 0 }, [ 34 ] = { 11, 114, 48, 11, 0, 0 }, [ 35 ] = { 35, 204, 188, 59, 0, 0 }, [ 36 ] = { 198, 193, 106, 112, 0, 0 }, [ 37 ] = { 117, 126, 52, 57, 0, 0 }, [ 38 ] = { 72, 69, 54, 0, 0, 0 }, [ 39 ] = { 69, 67, 60, 59, 0, 0 }, [ 40 ] = { 210, 184, 1, 3, 0, 0 }, [ 41 ] = { 9, 8, 3, 5, 0, 0 }, [ 42 ] = { 64, 62, 24, 59, 0, 0 }, [ 43 ] = { 20, 21, 100, 106, 0, 0 }, [ 44 ] = { 13, 137, 165, 171, 0, 0 }, [ 45 ] = { 21, 78, 101, 105, 0, 0 }, [ 46 ] = { 26, 23, 103, 108, 0, 0 }, [ 47 ] = { 25, 22, 166, 173, 0, 0 }, [ 48 ] = { 16, 18, 26, 59, 0, 0 }, [ 49 ] = { 16, 18, 187, 15, 0, 0 }, [ 50 ] = { 14, 16, 8, 13, 0, 0 }, [ 51 ] = { 17, 17, 10, 14, 0, 0 }, [ 52 ] = { 78, 74, 59, 63, 0, 0 }, [ 53 ] = { 76, 77, 55, 0, 0, 0 }, [ 54 ] = { 77, 75, 57, 61, 0, 0 }, [ 55 ] = { 79, 76, 58, 62, 0, 0 }, [ 56 ] = { 184, 181, 154, 163, 0, 0 }, [ 57 ] = { 187, 182, 156, 164, 0, 0 }, [ 58 ] = { 183, 183, 189, 165, 0, 0 }, [ 59 ] = { 186, 64, 51, 16, 0, 0 }, [ 60 ] = { 83, 82, 64, 69, 0, 0 }, [ 61 ] = { 85, 84, 66, 71, 0, 0 }, [ 62 ] = { 87, 87, 68, 74, 0, 0 }, [ 63 ] = { 91, 90, 72, 77, 0, 0 }, [ 64 ] = { 93, 92, 74, 79, 0, 0 }, [ 65 ] = { 95, 95, 76, 82, 0, 0 }, [ 66 ] = { 99, 98, 80, 85, 0, 0 }, [ 67 ] = { 101, 100, 82, 87, 0, 0 }, [ 68 ] = { 103, 103, 84, 90, 0, 0 }, [ 69 ] = { 107, 71, 89, 94, 0, 0 }, [ 70 ] = { 73, 108, 93, 98, 0, 0 }, [ 71 ] = { 73, 111, 97, 102, 0, 0 }, [ 72 ] = { 82, 86, 63, 73, 0, 0 }, [ 73 ] = { 90, 94, 71, 81, 0, 0 }, [ 74 ] = { 98, 102, 79, 89, 0, 0 }, [ 75 ] = { 106, 107, 91, 99, 0, 0 }, [ 76 ] = { 108, 109, 88, 96, 0, 0 }, [ 77 ] = { 112, 112, 99, 100, 0, 0 }, [ 78 ] = { 55, 54, 38, 43, 0, 0 }, [ 79 ] = { 56, 53, 39, 44, 0, 0 }, [ 80 ] = { 54, 55, 30, 40, 0, 0 }, [ 81 ] = { 58, 56, 55, 115, 0, 0 }, [ 82 ] = { 40, 48, 29, 39, 0, 0 }, [ 83 ] = { 37, 45, 31, 41, 0, 0 }, [ 84 ] = { 38, 46, 33, 42, 0, 0 }, [ 85 ] = { 43, 51, 55, 37, 0, 0 }, [ 86 ] = { 42, 50, 105, 111, 0, 0 }, [ 87 ] = { 39, 47, 55, 42, 0, 0 }, [ 88 ] = { 36, 44, 30, 59, 0, 0 }, [ 89 ] = { 44, 52, 105, 59, 0, 0 }, [ 90 ] = { 59, 57, 42, 49, 0, 0 }, [ 91 ] = { 171, 172, 45, 47, 0, 0 }, [ 92 ] = { 4, 4, 43, 50, 0, 0 }, [ 93 ] = { 206, 203, 171, 178, 0, 0 }, [ 94 ] = { 205, 202, 173, 180, 0, 0 }, [ 95 ] = { 204, 201, 175, 182, 0, 0 }, [ 96 ] = { 203, 68, 177, 59, 0, 0 }, [ 97 ] = { 202, 196, 55, 176, 0, 0 }, [ 98 ] = { 196, 71, 182, 189, 0, 0 }, [ 99 ] = { 73, 0, 178, 185, 0, 0 }, [ 100 ] = { 73, 15, 180, 187, 0, 0 }, [ 101 ] = { 27, 27, 17, 23, 0, 0 }, [ 102 ] = { 32, 29, 20, 28, 0, 0 }, [ 103 ] = { 33, 33, 21, 27, 0, 0 }, [ 104 ] = { 31, 28, 15, 24, 0, 0 }, [ 105 ] = { 193, 185, 161, 166, 0, 0 }, [ 106 ] = { 194, 189, 160, 59, 0, 0 }, [ 107 ] = { 197, 150, 162, 127, 0, 0 }, [ 108 ] = { 192, 149, 159, 126, 0, 0 }, [ 109 ] = { 156, 155, 125, 20, 0, 0 }, [ 110 ] = { 155, 148, 126, 21, 0, 0 }, [ 111 ] = { 159, 156, 128, 132, 0, 0 }, [ 112 ] = { 153, 152, 124, 128, 0, 0 }, [ 113 ] = { 171, 173, 185, 158, 0, 0 }, [ 114 ] = { 171, 179, 137, 146, 0, 0 }, [ 115 ] = { 172, 158, 138, 147, 0, 0 }, [ 116 ] = { 160, 162, 129, 135, 0, 0 }, [ 117 ] = { 161, 160, 55, 44, 0, 0 }, [ 118 ] = { 163, 166, 131, 138, 0, 0 }, [ 119 ] = { 166, 161, 130, 143, 0, 0 }, [ 120 ] = { 164, 164, 133, 141, 0, 0 }, [ 121 ] = { 162, 161, 55, 137, 0, 0 }, [ 122 ] = { 165, 165, 132, 140, 0, 0 }, [ 123 ] = { 168, 168, 135, 144, 0, 0 }, [ 124 ] = { 170, 170, 55, 144, 0, 0 }, [ 125 ] = { 175, 71, 150, 134, 0, 0 }, [ 126 ] = { 179, 179, 148, 160, 0, 0 }, [ 127 ] = { 178, 178, 136, 148, 0, 0 }, [ 128 ] = { 13, 74, 165, 106, 0, 0 }, [ 129 ] = { 16, 18, 165, 106, 0, 0 }, [ 130 ] = { 81, 21, 165, 106, 0, 0 }, [ 131 ] = { 16, 18, 100, 171, 0, 0 }, [ 132 ] = { 12, 69, 61, 91, 0, 0 }, [ 133 ] = { 9, 8, 3, 1, 0, 0 }, [ 134 ] = { 43, 51, 30, 37, 0, 0 }, [ 135 ] = { 39, 47, 33, 42, 0, 0 }, [ 136 ] = { 36, 44, 30, 40, 0, 0 }, [ 137 ] = { 56, 54, 165, 106, 0, 0 }, [ 138 ] = { 58, 56, 30, 40, 0, 0 }, [ 139 ] = { 55, 53, 39, 44, 0, 0 }, [ 140 ] = { 12, 58, 6, 44, 0, 0 }, [ 141 ] = { 12, 56, 56, 115, 0, 0 }, [ 142 ] = { 12, 72, 100, 171, 0, 0 }, [ 143 ] = { 210, 15, 165, 106, 0, 0 }, [ 144 ] = { 56, 54, 6, 59, 0, 0 } }; static const pmg_power_group_t power5_groups[] = { [ 0 ] = { .pmg_name = "pm_utilization", .pmg_desc = "CPI and utilization data", .pmg_event_ids = power5_group_event_ids[0], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000000a02121eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 1 ] = { .pmg_name = "pm_completion", .pmg_desc = "Completion and cycle counts", .pmg_event_ids = power5_group_event_ids[1], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000002608261eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 2 ] = { .pmg_name = "pm_group_dispatch", .pmg_desc = "Group dispatch events", .pmg_event_ids = power5_group_event_ids[2], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4000000ec6c8c212ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 3 ] = { .pmg_name = "pm_clb1", .pmg_desc = "CLB fullness", .pmg_event_ids = power5_group_event_ids[3], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x015b000180848c4cULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 4 ] = { .pmg_name = "pm_clb2", .pmg_desc = "CLB fullness", .pmg_event_ids = power5_group_event_ids[4], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x014300028a8ccc02ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 5 ] = { .pmg_name = "pm_gct_empty", .pmg_desc = "GCT empty reasons", .pmg_event_ids = power5_group_event_ids[5], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4000000008380838ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 6 ] = { .pmg_name = "pm_gct_usage", .pmg_desc = "GCT Usage", .pmg_event_ids = power5_group_event_ids[6], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000003e3e3e3eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 7 ] = { .pmg_name = "pm_lsu1", .pmg_desc = "LSU LRQ and LMQ events", .pmg_event_ids = power5_group_event_ids[7], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000f000fccc4cccaULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 8 ] = { .pmg_name = "pm_lsu2", .pmg_desc = "LSU SRQ events", .pmg_event_ids = power5_group_event_ids[8], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x400e000ecac2ca86ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 9 ] = { .pmg_name = "pm_lsu3", .pmg_desc = "LSU SRQ and LMQ events", .pmg_event_ids = power5_group_event_ids[9], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x010f000a102aca2aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 10 ] = { .pmg_name = "pm_prefetch1", .pmg_desc = "Prefetch stream allocation", .pmg_event_ids = power5_group_event_ids[10], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x8432000d36c884ceULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 11 ] = { .pmg_name = "pm_prefetch2", .pmg_desc = "Prefetch events", .pmg_event_ids = power5_group_event_ids[11], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x8103000602cace8eULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 12 ] = { .pmg_name = "pm_prefetch3", .pmg_desc = "L2 prefetch and misc events", .pmg_event_ids = power5_group_event_ids[12], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x047c000820828602ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 13 ] = { .pmg_name = "pm_prefetch4", .pmg_desc = "Misc prefetch and reject events", .pmg_event_ids = power5_group_event_ids[13], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x063e000ec0c8cc86ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 14 ] = { .pmg_name = "pm_lsu_reject1", .pmg_desc = "LSU reject events", .pmg_event_ids = power5_group_event_ids[14], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xc22c000e2010c610ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 15 ] = { .pmg_name = "pm_lsu_reject2", .pmg_desc = "LSU rejects due to reload CDF or tag update collision", .pmg_event_ids = power5_group_event_ids[15], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x820c000dc4cc02ceULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 16 ] = { .pmg_name = "LSU rejects due to ERAT", .pmg_desc = " held instuctions", .pmg_event_ids = power5_group_event_ids[16], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x420c000fc6cec0c8ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 17 ] = { .pmg_name = "pm_lsu_reject4", .pmg_desc = "LSU0/1 reject LMQ full", .pmg_event_ids = power5_group_event_ids[17], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x820c000dc2ca02c8ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 18 ] = { .pmg_name = "pm_lsu_reject5", .pmg_desc = "LSU misc reject and flush events", .pmg_event_ids = power5_group_event_ids[18], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x420c000c10208a8eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 19 ] = { .pmg_name = "pm_flush1", .pmg_desc = "Misc flush events", .pmg_event_ids = power5_group_event_ids[19], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xc0f000020210c68eULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 20 ] = { .pmg_name = "pm_flush2", .pmg_desc = "Flushes due to scoreboard and sync", .pmg_event_ids = power5_group_event_ids[20], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xc08000038002c4c2ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 21 ] = { .pmg_name = "pm_lsu_flush_srq_lrq", .pmg_desc = "LSU flush by SRQ and LRQ events", .pmg_event_ids = power5_group_event_ids[21], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x40c000002020028aULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 22 ] = { .pmg_name = "pm_lsu_flush_lrq", .pmg_desc = "LSU0/1 flush due to LRQ", .pmg_event_ids = power5_group_event_ids[22], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x40c00000848c8a02ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 23 ] = { .pmg_name = "pm_lsu_flush_srq", .pmg_desc = "LSU0/1 flush due to SRQ", .pmg_event_ids = power5_group_event_ids[23], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x40c00000868e028aULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 24 ] = { .pmg_name = "pm_lsu_flush_unaligned", .pmg_desc = "LSU flush due to unaligned data", .pmg_event_ids = power5_group_event_ids[24], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x80c000021010c802ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 25 ] = { .pmg_name = "pm_lsu_flush_uld", .pmg_desc = "LSU0/1 flush due to unaligned load", .pmg_event_ids = power5_group_event_ids[25], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x40c0000080888a02ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 26 ] = { .pmg_name = "pm_lsu_flush_ust", .pmg_desc = "LSU0/1 flush due to unaligned store", .pmg_event_ids = power5_group_event_ids[26], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x40c00000828a028aULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 27 ] = { .pmg_name = "pm_lsu_flush_full", .pmg_desc = "LSU flush due to LRQ/SRQ full", .pmg_event_ids = power5_group_event_ids[27], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xc0200009ce0210c0ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 28 ] = { .pmg_name = "pm_lsu_stall1", .pmg_desc = "LSU Stalls", .pmg_event_ids = power5_group_event_ids[28], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4000000028300234ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 29 ] = { .pmg_name = "pm_lsu_stall2", .pmg_desc = "LSU Stalls", .pmg_event_ids = power5_group_event_ids[29], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4000000002341e36ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 30 ] = { .pmg_name = "pm_fxu_stall", .pmg_desc = "FXU Stalls", .pmg_event_ids = power5_group_event_ids[30], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4000000822320232ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 31 ] = { .pmg_name = "pm_fpu_stall", .pmg_desc = "FPU Stalls", .pmg_event_ids = power5_group_event_ids[31], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4000000020360230ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 32 ] = { .pmg_name = "pm_queue_full", .pmg_desc = "BRQ LRQ LMQ queue full", .pmg_event_ids = power5_group_event_ids[32], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x400b0009ce8a84ceULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 33 ] = { .pmg_name = "pm_issueq_full", .pmg_desc = "FPU FX full", .pmg_event_ids = power5_group_event_ids[33], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x40000000868e8088ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 34 ] = { .pmg_name = "pm_mapper_full1", .pmg_desc = "CR CTR GPR mapper full", .pmg_event_ids = power5_group_event_ids[34], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x40000002888cca82ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 35 ] = { .pmg_name = "pm_mapper_full2", .pmg_desc = "FPR XER mapper full", .pmg_event_ids = power5_group_event_ids[35], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4103000282843602ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 36 ] = { .pmg_name = "pm_misc_load", .pmg_desc = "Non-cachable loads and stcx events", .pmg_event_ids = power5_group_event_ids[36], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0438000cc2ca828aULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 37 ] = { .pmg_name = "pm_ic_demand", .pmg_desc = "ICache demand from BR redirect", .pmg_event_ids = power5_group_event_ids[37], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x800c000fc6cec0c2ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 38 ] = { .pmg_name = "pm_ic_pref", .pmg_desc = "ICache prefetch", .pmg_event_ids = power5_group_event_ids[38], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x8000000ccecc8e1aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 39 ] = { .pmg_name = "pm_ic_miss", .pmg_desc = "ICache misses", .pmg_event_ids = power5_group_event_ids[39], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4003000e32cec802ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 40 ] = { .pmg_name = "Branch mispredict", .pmg_desc = " TLB and SLB misses", .pmg_event_ids = power5_group_event_ids[40], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x808000031010caccULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 41 ] = { .pmg_name = "pm_branch1", .pmg_desc = "Branch operations", .pmg_event_ids = power5_group_event_ids[41], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x800000030e0e0e0eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 42 ] = { .pmg_name = "pm_branch2", .pmg_desc = "Branch operations", .pmg_event_ids = power5_group_event_ids[42], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4000000ccacc8c02ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 43 ] = { .pmg_name = "pm_L1_tlbmiss", .pmg_desc = "L1 load and TLB misses", .pmg_event_ids = power5_group_event_ids[43], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00b000008e881020ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 44 ] = { .pmg_name = "pm_L1_DERAT_miss", .pmg_desc = "L1 store and DERAT misses", .pmg_event_ids = power5_group_event_ids[44], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00b300000e202086ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 45 ] = { .pmg_name = "pm_L1_slbmiss", .pmg_desc = "L1 load and SLB misses", .pmg_event_ids = power5_group_event_ids[45], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00b000008a82848cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 46 ] = { .pmg_name = "pm_L1_dtlbmiss_4K", .pmg_desc = "L1 load references and 4K Data TLB references and misses", .pmg_event_ids = power5_group_event_ids[46], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x08f0000084808088ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 47 ] = { .pmg_name = "pm_L1_dtlbmiss_16M", .pmg_desc = "L1 store references and 16M Data TLB references and misses", .pmg_event_ids = power5_group_event_ids[47], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x08f000008c88828aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 48 ] = { .pmg_name = "pm_dsource1", .pmg_desc = "L3 cache and memory data access", .pmg_event_ids = power5_group_event_ids[48], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x400300001c0e8e02ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 49 ] = { .pmg_name = "pm_dsource2", .pmg_desc = "L3 cache and memory data access", .pmg_event_ids = power5_group_event_ids[49], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000300031c0e360eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 50 ] = { .pmg_name = "pm_dsource_L2", .pmg_desc = "L2 cache data access", .pmg_event_ids = power5_group_event_ids[50], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000300032e2e2e2eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 51 ] = { .pmg_name = "pm_dsource_L3", .pmg_desc = "L3 cache data access", .pmg_event_ids = power5_group_event_ids[51], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000300033c3c3c3cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 52 ] = { .pmg_name = "pm_isource1", .pmg_desc = "Instruction source information", .pmg_event_ids = power5_group_event_ids[52], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x8000000c1a1a1a0cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 53 ] = { .pmg_name = "pm_isource2", .pmg_desc = "Instruction source information", .pmg_event_ids = power5_group_event_ids[53], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x8000000c0c0c021aULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 54 ] = { .pmg_name = "pm_isource_L2", .pmg_desc = "L2 instruction source information", .pmg_event_ids = power5_group_event_ids[54], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x8000000c2c2c2c2cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 55 ] = { .pmg_name = "pm_isource_L3", .pmg_desc = "L3 instruction source information", .pmg_event_ids = power5_group_event_ids[55], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x8000000c3a3a3a3aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 56 ] = { .pmg_name = "pm_pteg_source1", .pmg_desc = "PTEG source information", .pmg_event_ids = power5_group_event_ids[56], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000200032e2e2e2eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 57 ] = { .pmg_name = "pm_pteg_source2", .pmg_desc = "PTEG source information", .pmg_event_ids = power5_group_event_ids[57], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000200033c3c3c3cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 58 ] = { .pmg_name = "pm_pteg_source3", .pmg_desc = "PTEG source information", .pmg_event_ids = power5_group_event_ids[58], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000200030e0e360eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 59 ] = { .pmg_name = "pm_pteg_source4", .pmg_desc = "L3 PTEG and group disptach events", .pmg_event_ids = power5_group_event_ids[59], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x003200001c04048eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 60 ] = { .pmg_name = "pm_L2SA_ld", .pmg_desc = "L2 slice A load events", .pmg_event_ids = power5_group_event_ids[60], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3055400580c080c0ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 61 ] = { .pmg_name = "pm_L2SA_st", .pmg_desc = "L2 slice A store events", .pmg_event_ids = power5_group_event_ids[61], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3055800580c080c0ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 62 ] = { .pmg_name = "pm_L2SA_st2", .pmg_desc = "L2 slice A store events", .pmg_event_ids = power5_group_event_ids[62], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3055c00580c080c0ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 63 ] = { .pmg_name = "pm_L2SB_ld", .pmg_desc = "L2 slice B load events", .pmg_event_ids = power5_group_event_ids[63], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3055400582c282c2ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 64 ] = { .pmg_name = "pm_L2SB_st", .pmg_desc = "L2 slice B store events", .pmg_event_ids = power5_group_event_ids[64], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3055800582c282c2ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 65 ] = { .pmg_name = "pm_L2SB_st2", .pmg_desc = "L2 slice B store events", .pmg_event_ids = power5_group_event_ids[65], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3055c00582c282c2ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 66 ] = { .pmg_name = "pm_L2SB_ld", .pmg_desc = "L2 slice C load events", .pmg_event_ids = power5_group_event_ids[66], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3055400584c484c4ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 67 ] = { .pmg_name = "pm_L2SB_st", .pmg_desc = "L2 slice C store events", .pmg_event_ids = power5_group_event_ids[67], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3055800584c484c4ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 68 ] = { .pmg_name = "pm_L2SB_st2", .pmg_desc = "L2 slice C store events", .pmg_event_ids = power5_group_event_ids[68], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3055c00584c484c4ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 69 ] = { .pmg_name = "pm_L3SA_trans", .pmg_desc = "L3 slice A state transistions", .pmg_event_ids = power5_group_event_ids[69], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3015000ac602c686ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 70 ] = { .pmg_name = "pm_L3SB_trans", .pmg_desc = "L3 slice B state transistions", .pmg_event_ids = power5_group_event_ids[70], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3015000602c8c888ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 71 ] = { .pmg_name = "pm_L3SC_trans", .pmg_desc = "L3 slice C state transistions", .pmg_event_ids = power5_group_event_ids[71], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3015000602caca8aULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 72 ] = { .pmg_name = "pm_L2SA_trans", .pmg_desc = "L2 slice A state transistions", .pmg_event_ids = power5_group_event_ids[72], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3055000ac080c080ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 73 ] = { .pmg_name = "pm_L2SB_trans", .pmg_desc = "L2 slice B state transistions", .pmg_event_ids = power5_group_event_ids[73], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3055000ac282c282ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 74 ] = { .pmg_name = "pm_L2SC_trans", .pmg_desc = "L2 slice C state transistions", .pmg_event_ids = power5_group_event_ids[74], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3055000ac484c484ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 75 ] = { .pmg_name = "pm_L3SAB_retry", .pmg_desc = "L3 slice A/B snoop retry and all CI/CO busy", .pmg_event_ids = power5_group_event_ids[75], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3005100fc6c8c6c8ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 76 ] = { .pmg_name = "pm_L3SAB_hit", .pmg_desc = "L3 slice A/B hit and reference", .pmg_event_ids = power5_group_event_ids[76], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3050100086888688ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 77 ] = { .pmg_name = "pm_L3SC_retry_hit", .pmg_desc = "L3 slice C hit & snoop retry", .pmg_event_ids = power5_group_event_ids[77], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x3055100aca8aca8aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 78 ] = { .pmg_name = "pm_fpu1", .pmg_desc = "Floating Point events", .pmg_event_ids = power5_group_event_ids[78], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000010101020ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 79 ] = { .pmg_name = "pm_fpu2", .pmg_desc = "Floating Point events", .pmg_event_ids = power5_group_event_ids[79], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000020202010ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 80 ] = { .pmg_name = "pm_fpu3", .pmg_desc = "Floating point events", .pmg_event_ids = power5_group_event_ids[80], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000c1010868eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 81 ] = { .pmg_name = "pm_fpu4", .pmg_desc = "Floating point events", .pmg_event_ids = power5_group_event_ids[81], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0430000c20200220ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 82 ] = { .pmg_name = "pm_fpu5", .pmg_desc = "Floating point events by unit", .pmg_event_ids = power5_group_event_ids[82], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000848c848cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 83 ] = { .pmg_name = "pm_fpu6", .pmg_desc = "Floating point events by unit", .pmg_event_ids = power5_group_event_ids[83], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000cc0c88088ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 84 ] = { .pmg_name = "pm_fpu7", .pmg_desc = "Floating point events by unit", .pmg_event_ids = power5_group_event_ids[84], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000008088828aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 85 ] = { .pmg_name = "pm_fpu8", .pmg_desc = "Floating point events by unit", .pmg_event_ids = power5_group_event_ids[85], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000dc2ca02c0ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 86 ] = { .pmg_name = "pm_fpu9", .pmg_desc = "Floating point events by unit", .pmg_event_ids = power5_group_event_ids[86], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0430000cc6ce8088ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 87 ] = { .pmg_name = "pm_fpu10", .pmg_desc = "Floating point events by unit", .pmg_event_ids = power5_group_event_ids[87], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000828a028aULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 88 ] = { .pmg_name = "pm_fpu11", .pmg_desc = "Floating point events by unit", .pmg_event_ids = power5_group_event_ids[88], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000868e8602ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 89 ] = { .pmg_name = "pm_fpu12", .pmg_desc = "Floating point events by unit", .pmg_event_ids = power5_group_event_ids[89], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0430000cc4cc8002ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 90 ] = { .pmg_name = "pm_fxu1", .pmg_desc = "Fixed Point events", .pmg_event_ids = power5_group_event_ids[90], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000024242424ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 91 ] = { .pmg_name = "pm_fxu2", .pmg_desc = "Fixed Point events", .pmg_event_ids = power5_group_event_ids[91], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4000000604221020ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 92 ] = { .pmg_name = "pm_fxu3", .pmg_desc = "Fixed Point events", .pmg_event_ids = power5_group_event_ids[92], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x404000038688c4ccULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 93 ] = { .pmg_name = "pm_smt_priorities1", .pmg_desc = "Thread priority events", .pmg_event_ids = power5_group_event_ids[93], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0005000fc6ccc6c8ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 94 ] = { .pmg_name = "pm_smt_priorities2", .pmg_desc = "Thread priority events", .pmg_event_ids = power5_group_event_ids[94], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0005000fc4cacaccULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 95 ] = { .pmg_name = "pm_smt_priorities3", .pmg_desc = "Thread priority events", .pmg_event_ids = power5_group_event_ids[95], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0005000fc2c8c4c2ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 96 ] = { .pmg_name = "pm_smt_priorities4", .pmg_desc = "Thread priority events", .pmg_event_ids = power5_group_event_ids[96], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0005000ac016c002ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 97 ] = { .pmg_name = "pm_smt_both", .pmg_desc = "Thread common events", .pmg_event_ids = power5_group_event_ids[97], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0010000016260208ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 98 ] = { .pmg_name = "pm_smt_selection", .pmg_desc = "Thread selection", .pmg_event_ids = power5_group_event_ids[98], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0090000086028082ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 99 ] = { .pmg_name = "pm_smt_selectover1", .pmg_desc = "Thread selection overide", .pmg_event_ids = power5_group_event_ids[99], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0050000002808488ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 100 ] = { .pmg_name = "pm_smt_selectover2", .pmg_desc = "Thread selection overide", .pmg_event_ids = power5_group_event_ids[100], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00100000021e8a86ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 101 ] = { .pmg_name = "pm_fabric1", .pmg_desc = "Fabric events", .pmg_event_ids = power5_group_event_ids[101], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x305500058ece8eceULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 102 ] = { .pmg_name = "pm_fabric2", .pmg_desc = "Fabric data movement", .pmg_event_ids = power5_group_event_ids[102], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x305500858ece8eceULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 103 ] = { .pmg_name = "pm_fabric3", .pmg_desc = "Fabric data movement", .pmg_event_ids = power5_group_event_ids[103], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x305501858ece8eceULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 104 ] = { .pmg_name = "pm_fabric4", .pmg_desc = "Fabric data movement", .pmg_event_ids = power5_group_event_ids[104], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x705401068ecec68eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 105 ] = { .pmg_name = "pm_snoop1", .pmg_desc = "Snoop retry", .pmg_event_ids = power5_group_event_ids[105], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x305500058ccc8cccULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 106 ] = { .pmg_name = "pm_snoop2", .pmg_desc = "Snoop read retry", .pmg_event_ids = power5_group_event_ids[106], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x30540a048ccc8c02ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 107 ] = { .pmg_name = "pm_snoop3", .pmg_desc = "Snoop write retry", .pmg_event_ids = power5_group_event_ids[107], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x30550c058ccc8cccULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 108 ] = { .pmg_name = "pm_snoop4", .pmg_desc = "Snoop partial write retry", .pmg_event_ids = power5_group_event_ids[108], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x30550e058ccc8cccULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 109 ] = { .pmg_name = "pm_mem_rq", .pmg_desc = "Memory read queue dispatch", .pmg_event_ids = power5_group_event_ids[109], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x705402058ccc8cceULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 110 ] = { .pmg_name = "pm_mem_read", .pmg_desc = "Memory read complete and cancel", .pmg_event_ids = power5_group_event_ids[110], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x305404048ccc8c06ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 111 ] = { .pmg_name = "pm_mem_wq", .pmg_desc = "Memory write queue dispatch", .pmg_event_ids = power5_group_event_ids[111], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x305506058ccc8cccULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 112 ] = { .pmg_name = "pm_mem_pwq", .pmg_desc = "Memory partial write queue", .pmg_event_ids = power5_group_event_ids[112], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x305508058ccc8cccULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 113 ] = { .pmg_name = "pm_threshold", .pmg_desc = "Thresholding", .pmg_event_ids = power5_group_event_ids[113], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0008000404c41628ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 114 ] = { .pmg_name = "pm_mrk_grp1", .pmg_desc = "Marked group events", .pmg_event_ids = power5_group_event_ids[114], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0008000404c60a26ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 115 ] = { .pmg_name = "pm_mrk_grp2", .pmg_desc = "Marked group events", .pmg_event_ids = power5_group_event_ids[115], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x410300022a0ac822ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 116 ] = { .pmg_name = "pm_mrk_dsource1", .pmg_desc = "Marked data from ", .pmg_event_ids = power5_group_event_ids[116], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x010b00030e404444ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 117 ] = { .pmg_name = "pm_mrk_dsource2", .pmg_desc = "Marked data from", .pmg_event_ids = power5_group_event_ids[117], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x010b00002e440210ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 118 ] = { .pmg_name = "pm_mrk_dsource3", .pmg_desc = "Marked data from", .pmg_event_ids = power5_group_event_ids[118], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x010b00031c484c4cULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 119 ] = { .pmg_name = "pm_mrk_dsource4", .pmg_desc = "Marked data from", .pmg_event_ids = power5_group_event_ids[119], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x010b000342462e42ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 120 ] = { .pmg_name = "pm_mrk_dsource5", .pmg_desc = "Marked data from", .pmg_event_ids = power5_group_event_ids[120], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x010b00033c4c4040ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 121 ] = { .pmg_name = "pm_mrk_dsource6", .pmg_desc = "Marked data from", .pmg_event_ids = power5_group_event_ids[121], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x010b000146460246ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 122 ] = { .pmg_name = "pm_mrk_dsource7", .pmg_desc = "Marked data from", .pmg_event_ids = power5_group_event_ids[122], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x010b00034e4e3c4eULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 123 ] = { .pmg_name = "pm_mrk_lbmiss", .pmg_desc = "Marked TLB and SLB misses", .pmg_event_ids = power5_group_event_ids[123], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0cf00000828a8c8eULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 124 ] = { .pmg_name = "pm_mrk_lbref", .pmg_desc = "Marked TLB and SLB references", .pmg_event_ids = power5_group_event_ids[124], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0cf00000868e028eULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 125 ] = { .pmg_name = "pm_mrk_lsmiss", .pmg_desc = "Marked load and store miss", .pmg_event_ids = power5_group_event_ids[125], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000800081002060aULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 126 ] = { .pmg_name = "pm_mrk_ulsflush", .pmg_desc = "Mark unaligned load and store flushes", .pmg_event_ids = power5_group_event_ids[126], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0028000406c62020ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 127 ] = { .pmg_name = "pm_mrk_misc", .pmg_desc = "Misc marked instructions", .pmg_event_ids = power5_group_event_ids[127], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00080008cc062816ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 128 ] = { .pmg_name = "pm_lsref_L1", .pmg_desc = "Load/Store operations and L1 activity", .pmg_event_ids = power5_group_event_ids[128], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x803300040e1a2020ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 129 ] = { .pmg_name = "Load/Store operations and L2", .pmg_desc = "L3 activity", .pmg_event_ids = power5_group_event_ids[129], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x003300001c0e2020ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 130 ] = { .pmg_name = "pm_lsref_tlbmiss", .pmg_desc = "Load/Store operations and TLB misses", .pmg_event_ids = power5_group_event_ids[130], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00b0000080882020ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 131 ] = { .pmg_name = "pm_Dmiss", .pmg_desc = "Data cache misses", .pmg_event_ids = power5_group_event_ids[131], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x003300001c0e1086ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 132 ] = { .pmg_name = "pm_prefetchX", .pmg_desc = "Prefetch events", .pmg_event_ids = power5_group_event_ids[132], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x853300061eccce86ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 133 ] = { .pmg_name = "pm_branchX", .pmg_desc = "Branch operations", .pmg_event_ids = power5_group_event_ids[133], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x800000030e0e0ec8ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 134 ] = { .pmg_name = "pm_fpuX1", .pmg_desc = "Floating point events by unit", .pmg_event_ids = power5_group_event_ids[134], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000dc2ca86c0ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 135 ] = { .pmg_name = "pm_fpuX2", .pmg_desc = "Floating point events by unit", .pmg_event_ids = power5_group_event_ids[135], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000828a828aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 136 ] = { .pmg_name = "pm_fpuX3", .pmg_desc = "Floating point events by unit", .pmg_event_ids = power5_group_event_ids[136], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000868e868eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 137 ] = { .pmg_name = "pm_fpuX4", .pmg_desc = "Floating point and L1 events", .pmg_event_ids = power5_group_event_ids[137], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0030000020102020ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 138 ] = { .pmg_name = "pm_fpuX5", .pmg_desc = "Floating point events", .pmg_event_ids = power5_group_event_ids[138], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000c2020868eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 139 ] = { .pmg_name = "pm_fpuX6", .pmg_desc = "Floating point events", .pmg_event_ids = power5_group_event_ids[139], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000010202010ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 140 ] = { .pmg_name = "pm_hpmcount1", .pmg_desc = "HPM group for set 1 ", .pmg_event_ids = power5_group_event_ids[140], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000001e281e10ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 141 ] = { .pmg_name = "pm_hpmcount2", .pmg_desc = "HPM group for set 2", .pmg_event_ids = power5_group_event_ids[141], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x043000041e201220ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 142 ] = { .pmg_name = "pm_hpmcount3", .pmg_desc = "HPM group for set 3 ", .pmg_event_ids = power5_group_event_ids[142], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x403000041ec21086ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 143 ] = { .pmg_name = "pm_hpmcount4", .pmg_desc = "HPM group for set 7", .pmg_event_ids = power5_group_event_ids[143], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00b00000101e2020ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 144 ] = { .pmg_name = "pm_1flop_with_fma", .pmg_desc = "One flop instructions plus FMA", .pmg_event_ids = power5_group_event_ids[144], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000020101e02ULL, .pmg_mmcra = 0x0000000000000000ULL } }; #endif papi-5.5.1/src/libpfm-3.y/lib/pfmlib_priv_comp_ia64.h0000644000307100002310000000375413013651450022224 0ustar yarkhangraduate/* * Copyright (c) 2003-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #ifndef __PFMLIB_PRIV_COMP_IA64_H__ #define __PFMLIB_PRIV_COMP_IA64_H__ #include #ifdef LIBPFM_USING_INTEL_ECC_COMPILER #define ia64_get_cpuid(regnum) __getIndReg(_IA64_REG_INDR_CPUID, (regnum)) #define ia64_getf(d) __getf_exp(d) #elif defined(__GNUC__) static inline unsigned long ia64_get_cpuid (unsigned long regnum) { unsigned long r; asm ("mov %0=cpuid[%r1]" : "=r"(r) : "rO"(regnum)); return r; } static inline unsigned long ia64_getf(double d) { unsigned long exp; __asm__ ("getf.exp %0=%1" : "=r"(exp) : "f"(d)); return exp; } #else /* !GNUC nor INTEL_ECC */ #error "need to define a set of compiler-specific macros" #endif #endif /* __PFMLIB_PRIV_COMP_IA64_H__ */ papi-5.5.1/src/libpfm-3.y/lib/pentium4_events.h0000644000307100002310000013360713013651450021204 0ustar yarkhangraduate/* * Copyright (c) 2006 IBM Corp. * Contributed by Kevin Corry * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * pentium4_events.h * * This header contains arrays to describe the Event-Selection-Control * Registers (ESCRs), Counter-Configuration-Control Registers (CCCRs), * and countable events on Pentium4/Xeon/EM64T systems. * * For more details, see: * - IA-32 Intel Architecture Software Developer's Manual, * Volume 3B: System Programming Guide, Part 2 * (available at: http://www.intel.com/design/Pentium4/manuals/253669.htm) * - Chapter 18.10: Performance Monitoring Overview * - Chapter 18.13: Performance Monitoring - Pentium4 and Xeon Processors * - Chapter 18.14: Performance Monitoring and Hyper-Threading Technology * - Appendix A.1: Pentium4 and Xeon Processor Performance-Monitoring Events * * This header also contains an array to describe how the Perfmon PMCs map to * the ESCRs and CCCRs. */ #ifndef _PENTIUM4_EVENTS_H_ #define _PENTIUM4_EVENTS_H_ /** * pentium4_escrs * * Array of event-selection-control registers that are available * on Pentium4. **/ pentium4_escr_reg_t pentium4_escrs[] = { {.name = "BPU_ESCR0", .pmc = 0, .allowed_cccrs = { 0, 9, -1, }, }, {.name = "IS_ESCR0", .pmc = 1, .allowed_cccrs = { 0, 9, -1, }, }, {.name = "MOB_ESCR0", .pmc = 2, .allowed_cccrs = { 0, 9, -1, }, }, {.name = "ITLB_ESCR0", .pmc = 3, .allowed_cccrs = { 0, 9, -1, }, }, {.name = "PMH_ESCR0", .pmc = 4, .allowed_cccrs = { 0, 9, -1, }, }, {.name = "IX_ESCR0", .pmc = 5, .allowed_cccrs = { 0, 9, -1, }, }, {.name = "FSB_ESCR0", .pmc = 6, .allowed_cccrs = { 0, 9, -1, }, }, {.name = "BSU_ESCR0", .pmc = 7, .allowed_cccrs = { 0, 9, -1, }, }, {.name = "MS_ESCR0", .pmc = 8, .allowed_cccrs = { 2, 11, -1, }, }, {.name = "TC_ESCR0", .pmc = 9, .allowed_cccrs = { 2, 11, -1, }, }, {.name = "TBPU_ESCR0", .pmc = 10, .allowed_cccrs = { 2, 11, -1, }, }, {.name = "FLAME_ESCR0", .pmc = 11, .allowed_cccrs = { 4, 13, -1, }, }, {.name = "FIRM_ESCR0", .pmc = 12, .allowed_cccrs = { 4, 13, -1, }, }, {.name = "SAAT_ESCR0", .pmc = 13, .allowed_cccrs = { 4, 13, -1, }, }, {.name = "U2L_ESCR0", .pmc = 14, .allowed_cccrs = { 4, 13, -1, }, }, {.name = "DAC_ESCR0", .pmc = 15, .allowed_cccrs = { 4, 13, -1, }, }, {.name = "IQ_ESCR0", .pmc = 16, .allowed_cccrs = { 6, 8, 15, }, }, {.name = "ALF_ESCR0", .pmc = 17, .allowed_cccrs = { 6, 8, 15, }, }, {.name = "RAT_ESCR0", .pmc = 18, .allowed_cccrs = { 6, 8, 15, }, }, {.name = "SSU_ESCR0", .pmc = 19, .allowed_cccrs = { 6, 8, 15, }, }, {.name = "CRU_ESCR0", .pmc = 20, .allowed_cccrs = { 6, 8, 15, }, }, {.name = "CRU_ESCR2", .pmc = 21, .allowed_cccrs = { 6, 8, 15, }, }, {.name = "CRU_ESCR4", .pmc = 22, .allowed_cccrs = { 6, 8, 15, }, }, {.name = "BPU_ESCR1", .pmc = 32, .allowed_cccrs = { 1, 10, -1, }, }, {.name = "IS_ESCR1", .pmc = 33, .allowed_cccrs = { 1, 10, -1, }, }, {.name = "MOB_ESCR1", .pmc = 34, .allowed_cccrs = { 1, 10, -1, }, }, {.name = "ITLB_ESCR1", .pmc = 35, .allowed_cccrs = { 1, 10, -1, }, }, {.name = "PMH_ESCR1", .pmc = 36, .allowed_cccrs = { 1, 10, -1, }, }, {.name = "IX_ESCR1", .pmc = 37, .allowed_cccrs = { 1, 10, -1, }, }, {.name = "FSB_ESCR1", .pmc = 38, .allowed_cccrs = { 1, 10, -1, }, }, {.name = "BSU_ESCR1", .pmc = 39, .allowed_cccrs = { 1, 10, -1, }, }, {.name = "MS_ESCR1", .pmc = 40, .allowed_cccrs = { 3, 12, -1, }, }, {.name = "TC_ESCR1", .pmc = 41, .allowed_cccrs = { 3, 12, -1, }, }, {.name = "TBPU_ESCR1", .pmc = 42, .allowed_cccrs = { 3, 12, -1, }, }, {.name = "FLAME_ESCR1", .pmc = 43, .allowed_cccrs = { 5, 14, -1, }, }, {.name = "FIRM_ESCR1", .pmc = 44, .allowed_cccrs = { 5, 14, -1, }, }, {.name = "SAAT_ESCR1", .pmc = 45, .allowed_cccrs = { 5, 14, -1, }, }, {.name = "U2L_ESCR1", .pmc = 46, .allowed_cccrs = { 5, 14, -1, }, }, {.name = "DAC_ESCR1", .pmc = 47, .allowed_cccrs = { 5, 14, -1, }, }, {.name = "IQ_ESCR1", .pmc = 48, .allowed_cccrs = { 7, 16, 17, }, }, {.name = "ALF_ESCR1", .pmc = 49, .allowed_cccrs = { 7, 16, 17, }, }, {.name = "RAT_ESCR1", .pmc = 50, .allowed_cccrs = { 7, 16, 17, }, }, {.name = "CRU_ESCR1", .pmc = 51, .allowed_cccrs = { 7, 16, 17, }, }, {.name = "CRU_ESCR3", .pmc = 52, .allowed_cccrs = { 7, 16, 17, }, }, {.name = "CRU_ESCR5", .pmc = 53, .allowed_cccrs = { 7, 16, 17, }, }, }; #define PENTIUM4_NUM_ESCRS (sizeof(pentium4_escrs)/sizeof(pentium4_escrs[0])) /** * pentium4_cccrs * * Array of counter-configuration-control registers that are available * on Pentium4. **/ pentium4_cccr_reg_t pentium4_cccrs[] = { {.name = "BPU_CCCR0", .pmc = 23, .pmd = 0, .allowed_escrs = { 0, 1, 2, 3, 4, 5, 6, 7 }, }, {.name = "BPU_CCCR2", .pmc = 24, .pmd = 9, .allowed_escrs = { 23, 24, 25, 26, 27, 28, 29, 30 }, }, {.name = "MS_CCCR0", .pmc = 25, .pmd = 2, .allowed_escrs = { 8, 9, 10, -1, -1, -1, -1, -1, }, }, {.name = "MS_CCCR2", .pmc = 56, .pmd = 11, .allowed_escrs = { 31, 32, 33, -1, -1, -1, -1, -1, }, }, {.name = "FLAME_CCCR0", .pmc = 27, .pmd = 4, .allowed_escrs = { 11, 12, 13, 14, -1, 15, -1, -1 }, }, {.name = "FLAME_CCCR2", .pmc = 58, .pmd = 13, .allowed_escrs = { 34, 35, 36, 37, -1, 38, -1, -1 }, }, {.name = "IQ_CCCR0", .pmc = 29, .pmd = 6, .allowed_escrs = { 16, 17, 18, 19, 20, 21, 22, -1 }, }, {.name = "IQ_CCCR2", .pmc = 60, .pmd = 15, .allowed_escrs = { 39, 40, 41, -1, 42, 43, 44, -1 }, }, {.name = "IQ_CCCR4", .pmc = 31, .pmd = 8, .allowed_escrs = { 16, 17, 18, 19, 20, 21, 22, -1 }, }, {.name = "BPU_CCCR1", .pmc = 24, .pmd = 1, .allowed_escrs = { 0, 1, 2, 3, 4, 5, 6, 7 }, }, {.name = "BPU_CCCR3", .pmc = 55, .pmd = 10, .allowed_escrs = { 23, 24, 25, 26, 27, 28, 29, 30 }, }, {.name = "MS_CCCR1", .pmc = 26, .pmd = 3, .allowed_escrs = { 8, 9, 10, -1, -1, -1, -1, -1, }, }, {.name = "MS_CCCR3", .pmc = 57, .pmd = 12, .allowed_escrs = { 31, 32, 33, -1, -1, -1, -1, -1, }, }, {.name = "FLAME_CCCR1", .pmc = 28, .pmd = 5, .allowed_escrs = { 11, 12, 13, 14, -1, 15, -1, -1 }, }, {.name = "FLAME_CCCR3", .pmc = 59, .pmd = 14, .allowed_escrs = { 34, 35, 36, 37, -1, 38, -1, -1 }, }, {.name = "IQ_CCCR1", .pmc = 30, .pmd = 7, .allowed_escrs = { 16, 17, 18, 19, 20, 21, 22, -1 }, }, {.name = "IQ_CCCR3", .pmc = 61, .pmd = 16, .allowed_escrs = { 39, 40, 41, -1, 42, 43, 44, -1 }, }, {.name = "IQ_CCCR5", .pmc = 62, .pmd = 17, .allowed_escrs = { 39, 40, 41, -1, 42, 43, 44, -1 }, }, }; #define PENTIUM4_NUM_CCCRS (sizeof(pentium4_cccrs)/sizeof(pentium4_cccrs[0])) #define PENTIUM4_NUM_PMCS (PENTIUM4_NUM_CCCRS + PENTIUM4_NUM_ESCRS) #define PENTIUM4_NUM_PMDS PENTIUM4_NUM_CCCRS #define PENTIUM4_COUNTER_WIDTH 40 /** * pentium4_pmcs * * Array of PMCs on the Pentium4, showing how they map to the ESCRs and CCCRs. **/ pentium4_pmc_t pentium4_pmcs[PENTIUM4_NUM_PMCS] = { {.name = "BPU_ESCR0", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 0, }, {.name = "IS_ESCR0", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 1, }, {.name = "MOB_ESCR0", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 2, }, {.name = "ITLB_ESCR0", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 3, }, {.name = "PMH_ESCR0", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 4, }, {.name = "IX_ESCR0", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 5, }, {.name = "FSB_ESCR0", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 6, }, {.name = "BSU_ESCR0", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 7, }, {.name = "MS_ESCR0", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 8, }, {.name = "TC_ESCR0", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 9, }, {.name = "TBPU_ESCR0", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 10, }, {.name = "FLAME_ESCR0", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 11, }, {.name = "FIRM_ESCR0", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 12, }, {.name = "SAAT_ESCR0", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 13, }, {.name = "U2L_ESCR0", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 14, }, {.name = "DAC_ESCR0", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 15, }, {.name = "IQ_ESCR0", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 16, }, {.name = "ALF_ESCR0", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 17, }, {.name = "RAT_ESCR0", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 18, }, {.name = "SSU_ESCR0", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 19, }, {.name = "CRU_ESCR0", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 20, }, {.name = "CRU_ESCR2", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 21, }, {.name = "CRU_ESCR4", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 22, }, {.name = "BPU_CCCR0", .type = PENTIUM4_PMC_TYPE_CCCR, .index = 0, }, {.name = "BPU_CCCR2", .type = PENTIUM4_PMC_TYPE_CCCR, .index = 1, }, {.name = "MS_CCCR0", .type = PENTIUM4_PMC_TYPE_CCCR, .index = 2, }, {.name = "MS_CCCR2", .type = PENTIUM4_PMC_TYPE_CCCR, .index = 3, }, {.name = "FLAME_CCCR0", .type = PENTIUM4_PMC_TYPE_CCCR, .index = 4, }, {.name = "FLAME_CCCR2", .type = PENTIUM4_PMC_TYPE_CCCR, .index = 5, }, {.name = "IQ_CCCR0", .type = PENTIUM4_PMC_TYPE_CCCR, .index = 6, }, {.name = "IQ_CCCR2", .type = PENTIUM4_PMC_TYPE_CCCR, .index = 7, }, {.name = "IQ_CCCR4", .type = PENTIUM4_PMC_TYPE_CCCR, .index = 8, }, {.name = "BPU_ESCR1", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 23, }, {.name = "IS_ESCR1", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 24, }, {.name = "MOB_ESCR1", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 25, }, {.name = "ITLB_ESCR1", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 26, }, {.name = "PMH_ESCR1", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 27, }, {.name = "IX_ESCR1", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 28, }, {.name = "FSB_ESCR1", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 29, }, {.name = "BSU_ESCR1", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 30, }, {.name = "MS_ESCR1", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 31, }, {.name = "TC_ESCR1", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 32, }, {.name = "TBPU_ESCR1", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 33, }, {.name = "FLAME_ESCR1", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 34, }, {.name = "FIRM_ESCR1", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 35, }, {.name = "SAAT_ESCR1", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 36, }, {.name = "U2L_ESCR1", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 37, }, {.name = "DAC_ESCR1", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 38, }, {.name = "IQ_ESCR1", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 39, }, {.name = "ALF_ESCR1", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 40, }, {.name = "RAT_ESCR1", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 41, }, {.name = "CRU_ESCR1", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 42, }, {.name = "CRU_ESCR3", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 43, }, {.name = "CRU_ESCR5", .type = PENTIUM4_PMC_TYPE_ESCR, .index = 44, }, {.name = "BPU_CCCR1", .type = PENTIUM4_PMC_TYPE_CCCR, .index = 9, }, {.name = "BPU_CCCR3", .type = PENTIUM4_PMC_TYPE_CCCR, .index = 10, }, {.name = "MS_CCCR1", .type = PENTIUM4_PMC_TYPE_CCCR, .index = 11, }, {.name = "MS_CCCR3", .type = PENTIUM4_PMC_TYPE_CCCR, .index = 12, }, {.name = "FLAME_CCCR1", .type = PENTIUM4_PMC_TYPE_CCCR, .index = 13, }, {.name = "FLAME_CCCR3", .type = PENTIUM4_PMC_TYPE_CCCR, .index = 14, }, {.name = "IQ_CCCR1", .type = PENTIUM4_PMC_TYPE_CCCR, .index = 15, }, {.name = "IQ_CCCR3", .type = PENTIUM4_PMC_TYPE_CCCR, .index = 16, }, {.name = "IQ_CCCR5", .type = PENTIUM4_PMC_TYPE_CCCR, .index = 17, }, }; /** * pentium4_events * * Array of events that can be counted on Pentium4. **/ pentium4_event_t pentium4_events[] = { /* 0 */ {.name = "TC_deliver_mode", .desc = "The duration (in clock cycles) of the operating modes of " "the trace cache and decode engine in the processor package.", .event_select = 0x1, .escr_select = 0x1, .allowed_escrs = { 9, 32 }, .event_masks = { {.name = "DD", .desc = "Both logical CPUs in deliver mode.", .bit = 0, }, {.name = "DB", .desc = "Logical CPU 0 in deliver mode and " "logical CPU 1 in build mode.", .bit = 1, }, {.name = "DI", .desc = "Logical CPU 0 in deliver mode and logical CPU 1 " "either halted, under machine clear condition, or " "transitioning to a long microcode flow.", .bit = 2, }, {.name = "BD", .desc = "Logical CPU 0 in build mode and " "logical CPU 1 is in deliver mode.", .bit = 3, }, {.name = "BB", .desc = "Both logical CPUs in build mode.", .bit = 4, }, {.name = "BI", .desc = "Logical CPU 0 in build mode and logical CPU 1 " "either halted, under machine clear condition, or " "transitioning to a long microcode flow.", .bit = 5, }, {.name = "ID", .desc = "Logical CPU 0 either halted, under machine clear " "condition, or transitioning to a long microcode " "flow, and logical CPU 1 in deliver mode.", .bit = 6, }, {.name = "IB", .desc = "Logical CPU 0 either halted, under machine clear " "condition, or transitioning to a long microcode " "flow, and logical CPU 1 in build mode.", .bit = 7, }, }, }, /* 1 */ {.name = "BPU_fetch_request", .desc = "Instruction fetch requests by the Branch Prediction Unit.", .event_select = 0x3, .escr_select = 0x0, .allowed_escrs = { 0, 23 }, .event_masks = { {.name = "TCMISS", .desc = "Trace cache lookup miss.", .bit = 0, }, }, }, /* 2 */ {.name = "ITLB_reference", .desc = "Translations using the Instruction " "Translation Look-Aside Buffer.", .event_select = 0x18, .escr_select = 0x3, .allowed_escrs = { 3, 26 }, .event_masks = { {.name = "HIT", .desc = "ITLB hit.", .bit = 0, }, {.name = "MISS", .desc = "ITLB miss.", .bit = 1, }, {.name = "HIT_UC", .desc = "Uncacheable ITLB hit.", .bit = 2, }, }, }, /* 3 */ {.name = "memory_cancel", .desc = "Canceling of various types of requests in the " "Data cache Address Control unit (DAC).", .event_select = 0x2, .escr_select = 0x5, .allowed_escrs = { 15, 38 }, .event_masks = { {.name = "ST_RB_FULL", .desc = "Replayed because no store request " "buffer is available.", .bit = 2, }, {.name = "64K_CONF", .desc = "Conflicts due to 64K aliasing.", .bit = 3, }, }, }, /* 4 */ {.name = "memory_complete", .desc = "Completions of a load split, store split, " "uncacheable (UC) split, or UC load.", .event_select = 0x8, .escr_select = 0x2, .allowed_escrs = { 13, 36 }, .event_masks = { {.name = "LSC", .desc = "Load split completed, excluding UC/WC loads.", .bit = 0, }, {.name = "SSC", .desc = "Any split stores completed.", .bit = 1, }, }, }, /* 5 */ {.name = "load_port_replay", .desc = "Replayed events at the load port.", .event_select = 0x4, .escr_select = 0x2, .allowed_escrs = { 13, 36 }, .event_masks = { {.name = "SPLIT_LD", .desc = "Split load.", .bit = 1, }, }, }, /* 6 */ {.name = "store_port_replay", .desc = "Replayed events at the store port.", .event_select = 0x5, .escr_select = 0x2, .allowed_escrs = { 13, 36 }, .event_masks = { {.name = "SPLIT_ST", .desc = "Split store.", .bit = 1, }, }, }, /* 7 */ {.name = "MOB_load_replay", .desc = "Count of times the memory order buffer (MOB) " "caused a load operation to be replayed.", .event_select = 0x3, .escr_select = 0x2, .allowed_escrs = { 2, 25 }, .event_masks = { {.name = "NO_STA", .desc = "Replayed because of unknown store address.", .bit = 1, }, {.name = "NO_STD", .desc = "Replayed because of unknown store data.", .bit = 3, }, {.name = "PARTIAL_DATA", .desc = "Replayed because of partially overlapped data " "access between the load and store operations.", .bit = 4, }, {.name = "UNALGN_ADDR", .desc = "Replayed because the lower 4 bits of the " "linear address do not match between the " "load and store operations.", .bit = 5, }, }, }, /* 8 */ {.name = "page_walk_type", .desc = "Page walks that the page miss handler (PMH) performs.", .event_select = 0x1, .escr_select = 0x4, .allowed_escrs = { 4, 27 }, .event_masks = { {.name = "DTMISS", .desc = "Page walk for a data TLB miss (load or store)", .bit = 0, }, {.name = "ITMISS", .desc = "Page walk for an instruction TLB miss", .bit = 1, }, }, }, /* 9 */ {.name = "BSQ_cache_reference", .desc = "Cache references (2nd or 3rd level caches) as seen by the " "bus unit. Read types include both load and RFO, and write " "types include writebacks and evictions.", .event_select = 0xC, .escr_select = 0x7, .allowed_escrs = { 7, 30 }, .event_masks = { {.name = "RD_2ndL_HITS", .desc = "Read 2nd level cache hit Shared.", .bit = 0, }, {.name = "RD_2ndL_HITE", .desc = "Read 2nd level cache hit Exclusive.", .bit = 1, }, {.name = "RD_2ndL_HITM", .desc = "Read 2nd level cache hit Modified.", .bit = 2, }, {.name = "RD_3rdL_HITS", .desc = "Read 3rd level cache hit Shared.", .bit = 3, }, {.name = "RD_3rdL_HITE", .desc = "Read 3rd level cache hit Exclusive.", .bit = 4, }, {.name = "RD_3rdL_HITM", .desc = "Read 3rd level cache hit Modified.", .bit = 5, }, {.name = "RD_2ndL_MISS", .desc = "Read 2nd level cache miss.", .bit = 8, }, {.name = "RD_3rdL_MISS", .desc = "Read 3rd level cache miss.", .bit = 9, }, {.name = "WR_2ndL_MISS", .desc = "A writeback lookup from DAC misses the 2nd " "level cache (unlikely to happen)", .bit = 10, }, }, }, /* 10 */ {.name = "IOQ_allocation", .desc = "Count of various types of transactions on the bus. A count " "is generated each time a transaction is allocated into the " "IOQ that matches the specified mask bits. An allocated entry " "can be a sector (64 bytes) or a chunk of 8 bytes. Requests " "are counted once per retry. All 'TYPE_BIT*' event-masks " "together are treated as a single 5-bit value.", .event_select = 0x3, .escr_select = 0x6, .allowed_escrs = { 6, 29 }, .event_masks = { {.name = "TYPE_BIT0", .desc = "Bus request type (bit 0).", .bit = 0, }, {.name = "TYPE_BIT1", .desc = "Bus request type (bit 1).", .bit = 1, }, {.name = "TYPE_BIT2", .desc = "Bus request type (bit 2).", .bit = 2, }, {.name = "TYPE_BIT3", .desc = "Bus request type (bit 3).", .bit = 3, }, {.name = "TYPE_BIT4", .desc = "Bus request type (bit 4).", .bit = 4, }, {.name = "ALL_READ", .desc = "Count read entries.", .bit = 5, }, {.name = "ALL_WRITE", .desc = "Count write entries.", .bit = 6, }, {.name = "MEM_UC", .desc = "Count UC memory access entries.", .bit = 7, }, {.name = "MEM_WC", .desc = "Count WC memory access entries.", .bit = 8, }, {.name = "MEM_WT", .desc = "Count write-through (WT) memory access entries.", .bit = 9, }, {.name = "MEM_WP", .desc = "Count write-protected (WP) memory access entries.", .bit = 10, }, {.name = "MEM_WB", .desc = "Count WB memory access entries.", .bit = 11, }, {.name = "OWN", .desc = "Count all store requests driven by processor, as " "opposed to other processor or DMA.", .bit = 13, }, {.name = "OTHER", .desc = "Count all requests driven by other " "processors or DMA.", .bit = 14, }, {.name = "PREFETCH", .desc = "Include HW and SW prefetch requests in the count.", .bit = 15, }, }, }, /* 11 */ {.name = "IOQ_active_entries", .desc = "Number of entries (clipped at 15) in the IOQ that are " "active. An allocated entry can be a sector (64 bytes) " "or a chunk of 8 bytes. This event must be programmed in " "conjuction with IOQ_allocation. All 'TYPE_BIT*' event-masks " "together are treated as a single 5-bit value.", .event_select = 0x1A, .escr_select = 0x6, .allowed_escrs = { 29, -1 }, .event_masks = { {.name = "TYPE_BIT0", .desc = "Bus request type (bit 0).", .bit = 0, }, {.name = "TYPE_BIT1", .desc = "Bus request type (bit 1).", .bit = 1, }, {.name = "TYPE_BIT2", .desc = "Bus request type (bit 2).", .bit = 2, }, {.name = "TYPE_BIT3", .desc = "Bus request type (bit 3).", .bit = 3, }, {.name = "TYPE_BIT4", .desc = "Bus request type (bit 4).", .bit = 4, }, {.name = "ALL_READ", .desc = "Count read entries.", .bit = 5, }, {.name = "ALL_WRITE", .desc = "Count write entries.", .bit = 6, }, {.name = "MEM_UC", .desc = "Count UC memory access entries.", .bit = 7, }, {.name = "MEM_WC", .desc = "Count WC memory access entries.", .bit = 8, }, {.name = "MEM_WT", .desc = "Count write-through (WT) memory access entries.", .bit = 9, }, {.name = "MEM_WP", .desc = "Count write-protected (WP) memory access entries.", .bit = 10, }, {.name = "MEM_WB", .desc = "Count WB memory access entries.", .bit = 11, }, {.name = "OWN", .desc = "Count all store requests driven by processor, as " "opposed to other processor or DMA.", .bit = 13, }, {.name = "OTHER", .desc = "Count all requests driven by other " "processors or DMA.", .bit = 14, }, {.name = "PREFETCH", .desc = "Include HW and SW prefetch requests in the count.", .bit = 15, }, }, }, /* 12 */ {.name = "FSB_data_activity", .desc = "Count of DRDY or DBSY events that " "occur on the front side bus.", .event_select = 0x17, .escr_select = 0x6, .allowed_escrs = { 6, 29 }, .event_masks = { {.name = "DRDY_DRV", .desc = "Count when this processor drives data onto the bus. " "Includes writes and implicit writebacks.", .bit = 0, }, {.name = "DRDY_OWN", .desc = "Count when this processor reads data from the bus. " "Includes loads and some PIC transactions. Count " "DRDY events that we drive. Count DRDY events sampled " "that we own.", .bit = 1, }, {.name = "DRDY_OTHER", .desc = "Count when data is on the bus but not being sampled " "by the processor. It may or may not be driven by " "this processor.", .bit = 2, }, {.name = "DBSY_DRV", .desc = "Count when this processor reserves the bus for use " "in the next bus cycle in order to drive data.", .bit = 3, }, {.name = "DBSY_OWN", .desc = "Count when some agent reserves the bus for use in " "the next bus cycle to drive data that this processor " "will sample.", .bit = 4, }, {.name = "DBSY_OTHER", .desc = "Count when some agent reserves the bus for use in " "the next bus cycle to drive data that this processor " "will NOT sample. It may or may not be being driven " "by this processor.", .bit = 5, }, }, }, /* 13 */ {.name = "BSQ_allocation", .desc = "Allocations in the Bus Sequence Unit (BSQ). The event mask " "bits consist of four sub-groups: request type, request " "length, memory type, and a sub-group consisting mostly of " "independent bits (5 through 10). Must specify a mask for " "each sub-group.", .event_select = 0x5, .escr_select = 0x7, .allowed_escrs = { 7, -1 }, .event_masks = { {.name = "REQ_TYPE0", .desc = "Along with REQ_TYPE1, request type encodings are: " "0 - Read (excludes read invalidate), 1 - Read " "invalidate, 2 - Write (other than writebacks), 3 - " "Writeback (evicted from cache).", .bit = 0, }, {.name = "REQ_TYPE1", .desc = "Along with REQ_TYPE0, request type encodings are: " "0 - Read (excludes read invalidate), 1 - Read " "invalidate, 2 - Write (other than writebacks), 3 - " "Writeback (evicted from cache).", .bit = 1, }, {.name = "REQ_LEN0", .desc = "Along with REQ_LEN1, request length encodings are: " "0 - zero chunks, 1 - one chunk, 3 - eight chunks.", .bit = 2, }, {.name = "REQ_LEN1", .desc = "Along with REQ_LEN0, request length encodings are: " "0 - zero chunks, 1 - one chunk, 3 - eight chunks.", .bit = 3, }, {.name = "REQ_IO_TYPE", .desc = "Request type is input or output.", .bit = 5, }, {.name = "REQ_LOCK_TYPE", .desc = "Request type is bus lock.", .bit = 6, }, {.name = "REQ_CACHE_TYPE", .desc = "Request type is cacheable.", .bit = 7, }, {.name = "REQ_SPLIT_TYPE", .desc = "Request type is a bus 8-byte chunk split across " "an 8-byte boundary.", .bit = 8, }, {.name = "REQ_DEM_TYPE", .desc = "0: Request type is HW.SW prefetch. " "1: Request type is a demand.", .bit = 9, }, {.name = "REQ_ORD_TYPE", .desc = "Request is an ordered type.", .bit = 10, }, {.name = "MEM_TYPE0", .desc = "Along with MEM_TYPE1 and MEM_TYPE2, " "memory type encodings are: 0 - UC, " "1 - USWC, 4- WT, 5 - WP, 6 - WB", .bit = 11, }, {.name = "MEM_TYPE1", .desc = "Along with MEM_TYPE0 and MEM_TYPE2, " "memory type encodings are: 0 - UC, " "1 - USWC, 4- WT, 5 - WP, 6 - WB", .bit = 12, }, {.name = "MEM_TYPE2", .desc = "Along with MEM_TYPE0 and MEM_TYPE1, " "memory type encodings are: 0 - UC, " "1 - USWC, 4- WT, 5 - WP, 6 - WB", .bit = 13, }, }, }, /* 14 */ {.name = "BSQ_active_entries", .desc = "Number of BSQ entries (clipped at 15) currently active " "(valid) which meet the subevent mask criteria during " "allocation in the BSQ. Active request entries are allocated " "on the BSQ until de-allocated. De-allocation of an entry " "does not necessarily imply the request is filled. This " "event must be programmed in conjunction with BSQ_allocation.", .event_select = 0x6, .escr_select = 0x7, .allowed_escrs = { 30, -1 }, .event_masks = { {.name = "REQ_TYPE0", .desc = "Along with REQ_TYPE1, request type encodings are: " "0 - Read (excludes read invalidate), 1 - Read " "invalidate, 2 - Write (other than writebacks), 3 - " "Writeback (evicted from cache).", .bit = 0, }, {.name = "REQ_TYPE1", .desc = "Along with REQ_TYPE0, request type encodings are: " "0 - Read (excludes read invalidate), 1 - Read " "invalidate, 2 - Write (other than writebacks), 3 - " "Writeback (evicted from cache).", .bit = 1, }, {.name = "REQ_LEN0", .desc = "Along with REQ_LEN1, request length encodings are: " "0 - zero chunks, 1 - one chunk, 3 - eight chunks.", .bit = 2, }, {.name = "REQ_LEN1", .desc = "Along with REQ_LEN0, request length encodings are: " "0 - zero chunks, 1 - one chunk, 3 - eight chunks.", .bit = 3, }, {.name = "REQ_IO_TYPE", .desc = "Request type is input or output.", .bit = 5, }, {.name = "REQ_LOCK_TYPE", .desc = "Request type is bus lock.", .bit = 6, }, {.name = "REQ_CACHE_TYPE", .desc = "Request type is cacheable.", .bit = 7, }, {.name = "REQ_SPLIT_TYPE", .desc = "Request type is a bus 8-byte chunk split across " "an 8-byte boundary.", .bit = 8, }, {.name = "REQ_DEM_TYPE", .desc = "0: Request type is HW.SW prefetch. " "1: Request type is a demand.", .bit = 9, }, {.name = "REQ_ORD_TYPE", .desc = "Request is an ordered type.", .bit = 10, }, {.name = "MEM_TYPE0", .desc = "Along with MEM_TYPE1 and MEM_TYPE2, " "memory type encodings are: 0 - UC, " "1 - USWC, 4- WT, 5 - WP, 6 - WB", .bit = 11, }, {.name = "MEM_TYPE1", .desc = "Along with MEM_TYPE0 and MEM_TYPE2, " "memory type encodings are: 0 - UC, " "1 - USWC, 4- WT, 5 - WP, 6 - WB", .bit = 12, }, {.name = "MEM_TYPE2", .desc = "Along with MEM_TYPE0 and MEM_TYPE1, " "memory type encodings are: 0 - UC, " "1 - USWC, 4- WT, 5 - WP, 6 - WB", .bit = 13, }, }, }, /* 15 */ {.name = "SSE_input_assist", .desc = "Number of times an assist is requested to handle problems " "with input operands for SSE/SSE2/SSE3 operations; most " "notably denormal source operands when the DAZ bit isn't set.", .event_select = 0x34, .escr_select = 0x1, .allowed_escrs = { 12, 35 }, .event_masks = { {.name = "ALL", .desc = "Count assists for SSE/SSE2/SSE3 uops.", .bit = 15, }, }, }, /* 16 */ {.name = "packed_SP_uop", .desc = "Number of packed single-precision uops.", .event_select = 0x8, .escr_select = 0x1, .allowed_escrs = { 12, 35 }, .event_masks = { {.name = "ALL", .desc = "Count all uops operating on packed " "single-precisions operands.", .bit = 15, }, {.name = "TAG0", .desc = "Tag this event with tag bit 0 " "for retirement counting with execution_event.", .bit = 16, }, {.name = "TAG1", .desc = "Tag this event with tag bit 1 " "for retirement counting with execution_event.", .bit = 17, }, {.name = "TAG2", .desc = "Tag this event with tag bit 2 " "for retirement counting with execution_event.", .bit = 18, }, {.name = "TAG3", .desc = "Tag this event with tag bit 3 " "for retirement counting with execution_event.", .bit = 19, }, }, }, /* 17 */ {.name = "packed_DP_uop", .desc = "Number of packed double-precision uops.", .event_select = 0xC, .escr_select = 0x1, .allowed_escrs = { 12, 35 }, .event_masks = { {.name = "ALL", .desc = "Count all uops operating on packed " "double-precisions operands.", .bit = 15, }, {.name = "TAG0", .desc = "Tag this event with tag bit 0 " "for retirement counting with execution_event.", .bit = 16, }, {.name = "TAG1", .desc = "Tag this event with tag bit 1 " "for retirement counting with execution_event.", .bit = 17, }, {.name = "TAG2", .desc = "Tag this event with tag bit 2 " "for retirement counting with execution_event.", .bit = 18, }, {.name = "TAG3", .desc = "Tag this event with tag bit 3 " "for retirement counting with execution_event.", .bit = 19, }, }, }, /* 18 */ {.name = "scalar_SP_uop", .desc = "Number of scalar single-precision uops.", .event_select = 0xA, .escr_select = 0x1, .allowed_escrs = { 12, 35 }, .event_masks = { {.name = "ALL", .desc = "Count all uops operating on scalar " "single-precisions operands.", .bit = 15, }, {.name = "TAG0", .desc = "Tag this event with tag bit 0 " "for retirement counting with execution_event.", .bit = 16, }, {.name = "TAG1", .desc = "Tag this event with tag bit 1 " "for retirement counting with execution_event.", .bit = 17, }, {.name = "TAG2", .desc = "Tag this event with tag bit 2 " "for retirement counting with execution_event.", .bit = 18, }, {.name = "TAG3", .desc = "Tag this event with tag bit 3 " "for retirement counting with execution_event.", .bit = 19, }, }, }, /* 19 */ {.name = "scalar_DP_uop", .desc = "Number of scalar double-precision uops.", .event_select = 0xE, .escr_select = 0x1, .allowed_escrs = { 12, 35 }, .event_masks = { {.name = "ALL", .desc = "Count all uops operating on scalar " "double-precisions operands.", .bit = 15, }, {.name = "TAG0", .desc = "Tag this event with tag bit 0 " "for retirement counting with execution_event.", .bit = 16, }, {.name = "TAG1", .desc = "Tag this event with tag bit 1 " "for retirement counting with execution_event.", .bit = 17, }, {.name = "TAG2", .desc = "Tag this event with tag bit 2 " "for retirement counting with execution_event.", .bit = 18, }, {.name = "TAG3", .desc = "Tag this event with tag bit 3 " "for retirement counting with execution_event.", .bit = 19, }, }, }, /* 20 */ {.name = "64bit_MMX_uop", .desc = "Number of MMX instructions which " "operate on 64-bit SIMD operands.", .event_select = 0x2, .escr_select = 0x1, .allowed_escrs = { 12, 35 }, .event_masks = { {.name = "ALL", .desc = "Count all uops operating on 64-bit SIMD integer " "operands in memory or MMX registers.", .bit = 15, }, {.name = "TAG0", .desc = "Tag this event with tag bit 0 " "for retirement counting with execution_event.", .bit = 16, }, {.name = "TAG1", .desc = "Tag this event with tag bit 1 " "for retirement counting with execution_event.", .bit = 17, }, {.name = "TAG2", .desc = "Tag this event with tag bit 2 " "for retirement counting with execution_event.", .bit = 18, }, {.name = "TAG3", .desc = "Tag this event with tag bit 3 " "for retirement counting with execution_event.", .bit = 19, }, }, }, /* 21 */ {.name = "128bit_MMX_uop", .desc = "Number of MMX instructions which " "operate on 128-bit SIMD operands.", .event_select = 0x1A, .escr_select = 0x1, .allowed_escrs = { 12, 35 }, .event_masks = { {.name = "ALL", .desc = "Count all uops operating on 128-bit SIMD integer " "operands in memory or MMX registers.", .bit = 15, }, {.name = "TAG0", .desc = "Tag this event with tag bit 0 " "for retirement counting with execution_event.", .bit = 16, }, {.name = "TAG1", .desc = "Tag this event with tag bit 1 " "for retirement counting with execution_event.", .bit = 17, }, {.name = "TAG2", .desc = "Tag this event with tag bit 2 " "for retirement counting with execution_event.", .bit = 18, }, {.name = "TAG3", .desc = "Tag this event with tag bit 3 " "for retirement counting with execution_event.", .bit = 19, }, }, }, /* 22 */ {.name = "x87_FP_uop", .desc = "Number of x87 floating-point uops.", .event_select = 0x4, .escr_select = 0x1, .allowed_escrs = { 12, 35 }, .event_masks = { {.name = "ALL", .desc = "Count all x87 FP uops.", .bit = 15, }, {.name = "TAG0", .desc = "Tag this event with tag bit 0 " "for retirement counting with execution_event.", .bit = 16, }, {.name = "TAG1", .desc = "Tag this event with tag bit 1 " "for retirement counting with execution_event.", .bit = 17, }, {.name = "TAG2", .desc = "Tag this event with tag bit 2 " "for retirement counting with execution_event.", .bit = 18, }, {.name = "TAG3", .desc = "Tag this event with tag bit 3 " "for retirement counting with execution_event.", .bit = 19, }, }, }, /* 23 */ {.name = "TC_misc", .desc = "Miscellaneous events detected by the TC. The counter will " "count twice for each occurrence.", .event_select = 0x6, .escr_select = 0x1, .allowed_escrs = { 9, 32 }, .event_masks = { {.name = "FLUSH", .desc = "Number of flushes", .bit = 4, }, }, }, /* 24 */ {.name = "global_power_events", .desc = "Counts the time during which a processor is not stopped.", .event_select = 0x13, .escr_select = 0x6, .allowed_escrs = { 6, 29 }, .event_masks = { {.name = "RUNNING", .desc = "The processor is active (includes the " "handling of HLT STPCLK and throttling.", .bit = 0, }, }, }, /* 25 */ {.name = "tc_ms_xfer", .desc = "Number of times that uop delivery changed from TC to MS ROM.", .event_select = 0x5, .escr_select = 0x0, .allowed_escrs = { 8, 31 }, .event_masks = { {.name = "CISC", .desc = "A TC to MS transfer occurred.", .bit = 0, }, }, }, /* 26 */ {.name = "uop_queue_writes", .desc = "Number of valid uops written to the uop queue.", .event_select = 0x9, .escr_select = 0x0, .allowed_escrs = { 8, 31 }, .event_masks = { {.name = "FROM_TC_BUILD", .desc = "The uops being written are from TC build mode.", .bit = 0, }, {.name = "FROM_TC_DELIVER", .desc = "The uops being written are from TC deliver mode.", .bit = 1, }, {.name = "FROM_ROM", .desc = "The uops being written are from microcode ROM.", .bit = 2, }, }, }, /* 27 */ {.name = "retired_mispred_branch_type", .desc = "Number of retiring mispredicted branches by type.", .event_select = 0x5, .escr_select = 0x2, .allowed_escrs = { 10, 33 }, .event_masks = { {.name = "CONDITIONAL", .desc = "Conditional jumps.", .bit = 1, }, {.name = "CALL", .desc = "Indirect call branches.", .bit = 2, }, {.name = "RETURN", .desc = "Return branches.", .bit = 3, }, {.name = "INDIRECT", .desc = "Returns, indirect calls, or indirect jumps.", .bit = 4, }, }, }, /* 28 */ {.name = "retired_branch_type", .desc = "Number of retiring branches by type.", .event_select = 0x4, .escr_select = 0x2, .allowed_escrs = { 10, 33 }, .event_masks = { {.name = "CONDITIONAL", .desc = "Conditional jumps.", .bit = 1, }, {.name = "CALL", .desc = "Indirect call branches.", .bit = 2, }, {.name = "RETURN", .desc = "Return branches.", .bit = 3, }, {.name = "INDIRECT", .desc = "Returns, indirect calls, or indirect jumps.", .bit = 4, }, }, }, /* 29 */ {.name = "resource_stall", .desc = "Occurrences of latency or stalls in the Allocator.", .event_select = 0x1, .escr_select = 0x1, .allowed_escrs = { 17, 40 }, .event_masks = { {.name = "SBFULL", .desc = "A stall due to lack of store buffers.", .bit = 5, }, }, }, /* 30 */ {.name = "WC_Buffer", .desc = "Number of Write Combining Buffer operations.", .event_select = 0x5, .escr_select = 0x5, .allowed_escrs = { 15, 38 }, .event_masks = { {.name = "WCB_EVICTS", .desc = "WC Buffer evictions of all causes.", .bit = 0, }, {.name = "WCB_FULL_EVICT", .desc = "WC Buffer eviction; no WC buffer is available.", .bit = 1, }, }, }, /* 31 */ {.name = "b2b_cycles", .desc = "Number of back-to-back bus cycles", .event_select = 0x16, .escr_select = 0x3, .allowed_escrs = { 6, 29 }, /* FIXME: Appendix A is missing event-mask info. .event_masks = { {.name = .desc = .bit = }, }, */ }, /* 32 */ {.name = "bnr", .desc = "Number of bus-not-ready conditions.", .event_select = 0x8, .escr_select = 0x3, .allowed_escrs = { 6, 29 }, /* FIXME: Appendix A is missing event-mask info. .event_masks = { {.name = .desc = .bit = }, }, */ }, /* 33 */ {.name = "snoop", .desc = "Number of snoop hit modified bus traffic.", .event_select = 0x6, .escr_select = 0x3, .allowed_escrs = { 6, 29 }, /* FIXME: Appendix A is missing event-mask info. .event_masks = { {.name = .desc = .bit = }, }, */ }, /* 34 */ {.name = "response", .desc = "Count of different types of responses.", .event_select = 0x4, .escr_select = 0x3, .allowed_escrs = { 6, 29 }, /* FIXME: Appendix A is missing event-mask info. .event_masks = { {.name = .desc = .bit = }, }, */ }, /* 35 */ {.name = "front_end_event", .desc = "Number of retirements of tagged uops which are specified " "through the front-end tagging mechanism.", .event_select = 0x8, .escr_select = 0x5, .allowed_escrs = { 21, 43 }, .event_masks = { {.name = "NBOGUS", .desc = "The marked uops are not bogus.", .bit = 0, }, {.name = "BOGUS", .desc = "The marked uops are bogus.", .bit = 1, }, }, }, /* 36 */ {.name = "execution_event", .desc = "Number of retirements of tagged uops which are specified " "through the execution tagging mechanism. The event-mask " "allows from one to four types of uops to be tagged.", .event_select = 0xC, .escr_select = 0x5, .allowed_escrs = { 21, 43 }, .event_masks = { {.name = "NBOGUS0", .desc = "The marked uops are not bogus.", .bit = 0, }, {.name = "NBOGUS1", .desc = "The marked uops are not bogus.", .bit = 1, }, {.name = "NBOGUS2", .desc = "The marked uops are not bogus.", .bit = 2, }, {.name = "NBOGUS3", .desc = "The marked uops are not bogus.", .bit = 3, }, {.name = "BOGUS0", .desc = "The marked uops are bogus.", .bit = 4, }, {.name = "BOGUS1", .desc = "The marked uops are bogus.", .bit = 5, }, {.name = "BOGUS2", .desc = "The marked uops are bogus.", .bit = 6, }, {.name = "BOGUS3", .desc = "The marked uops are bogus.", .bit = 7, }, }, }, /* 37 */ {.name = "replay_event", .desc = "Number of retirements of tagged uops which are specified " "through the replay tagging mechanism.", .event_select = 0x9, .escr_select = 0x5, .allowed_escrs = { 21, 43 }, .event_masks = { {.name = "NBOGUS", .desc = "The marked uops are not bogus.", .bit = 0, }, {.name = "BOGUS", .desc = "The marked uops are bogus.", .bit = 1, }, {.name = "L1_LD_MISS", .desc = "Virtual mask for L1 cache load miss replays.", .bit = 2, }, {.name = "L2_LD_MISS", .desc = "Virtual mask for L2 cache load miss replays.", .bit = 3, }, {.name = "DTLB_LD_MISS", .desc = "Virtual mask for DTLB load miss replays.", .bit = 4, }, {.name = "DTLB_ST_MISS", .desc = "Virtual mask for DTLB store miss replays.", .bit = 5, }, {.name = "DTLB_ALL_MISS", .desc = "Virtual mask for all DTLB miss replays.", .bit = 6, }, {.name = "BR_MSP", .desc = "Virtual mask for tagged mispredicted branch replays.", .bit = 7, }, {.name = "MOB_LD_REPLAY", .desc = "Virtual mask for MOB load replays.", .bit = 8, }, {.name = "SP_LD_RET", .desc = "Virtual mask for split load replays. Use with load_port_replay event.", .bit = 9, }, {.name = "SP_ST_RET", .desc = "Virtual mask for split store replays. Use with store_port_replay event.", .bit = 10, }, }, }, /* 38 */ {.name = "instr_retired", .desc = "Number of instructions retired during a clock cycle.", .event_select = 0x2, .escr_select = 0x4, .allowed_escrs = { 20, 42 }, .event_masks = { {.name = "NBOGUSNTAG", .desc = "Non-bogus instructions that are not tagged.", .bit = 0, }, {.name = "NBOGUSTAG", .desc = "Non-bogus instructions that are tagged.", .bit = 1, }, {.name = "BOGUSNTAG", .desc = "Bogus instructions that are not tagged.", .bit = 2, }, {.name = "BOGUSTAG", .desc = "Bogus instructions that are tagged.", .bit = 3, }, }, }, /* 39 */ {.name = "uops_retired", .desc = "Number of uops retired during a clock cycle.", .event_select = 0x1, .escr_select = 0x4, .allowed_escrs = { 20, 42 }, .event_masks = { {.name = "NBOGUS", .desc = "The marked uops are not bogus.", .bit = 0, }, {.name = "BOGUS", .desc = "The marked uops are bogus.", .bit = 1, }, }, }, /* 40 */ {.name = "uops_type", .desc = "This event is used in conjunction with with the front-end " "mechanism to tag load and store uops.", .event_select = 0x2, .escr_select = 0x2, .allowed_escrs = { 18, 41 }, .event_masks = { {.name = "TAGLOADS", .desc = "The uop is a load operation.", .bit = 1, }, {.name = "TAGSTORES", .desc = "The uop is a store operation.", .bit = 2, }, }, }, /* 41 */ {.name = "branch_retired", .desc = "Number of retirements of a branch.", .event_select = 0x6, .escr_select = 0x5, .allowed_escrs = { 21, 43 }, .event_masks = { {.name = "MMNP", .desc = "Branch not-taken predicted.", .bit = 0, }, {.name = "MMNM", .desc = "Branch not-taken mispredicted.", .bit = 1, }, {.name = "MMTP", .desc = "Branch taken predicted.", .bit = 2, }, {.name = "MMTM", .desc = "Branch taken mispredicted.", .bit = 3, }, }, }, /* 42 */ {.name = "mispred_branch_retired", .desc = "Number of retirements of mispredicted " "IA-32 branch instructions", .event_select = 0x3, .escr_select = 0x4, .allowed_escrs = { 20, 42 }, .event_masks = { {.name = "BOGUS", .desc = "The retired instruction is not bogus.", .bit = 0, }, }, }, /* 43 */ {.name = "x87_assist", .desc = "Number of retirements of x87 instructions that required " "special handling.", .event_select = 0x3, .escr_select = 0x5, .allowed_escrs = { 21, 43 }, .event_masks = { {.name = "FPSU", .desc = "Handle FP stack underflow.", .bit = 0, }, {.name = "FPSO", .desc = "Handle FP stack overflow.", .bit = 1, }, {.name = "POAO", .desc = "Handle x87 output overflow.", .bit = 2, }, {.name = "POAU", .desc = "Handle x87 output underflow.", .bit = 3, }, {.name = "PREA", .desc = "Handle x87 input assist.", .bit = 4, }, }, }, /* 44 */ {.name = "machine_clear", .desc = "Number of occurances when the entire " "pipeline of the machine is cleared.", .event_select = 0x2, .escr_select = 0x5, .allowed_escrs = { 21, 43 }, .event_masks = { {.name = "CLEAR", .desc = "Counts for a portion of the many cycles while the " "machine is cleared for any cause. Use edge-" "triggering for this bit only to get a count of " "occurances versus a duration.", .bit = 0, }, {.name = "MOCLEAR", .desc = "Increments each time the machine is cleared due to " "memory ordering issues.", .bit = 2, }, {.name = "SMCLEAR", .desc = "Increments each time the machine is cleared due to " "self-modifying code issues.", .bit = 6, }, }, }, /* 45 */ {.name = "instr_completed", .desc = "Instructions that have completed and " "retired during a clock cycle. Supported on models 3, 4, 6 only", .event_select = 0x7, .escr_select = 0x5, .allowed_escrs = { 21, 42 }, .event_masks = { {.name = "NBOGUS", .desc = "Non-bogus instructions.", .bit = 0, }, {.name = "BOGUS", .desc = "Bogus instructions.", .bit = 1, }, }, }, }; #define PME_INSTR_COMPLETED 45 #define PME_REPLAY_EVENT 37 #define PENTIUM4_EVENT_COUNT (sizeof(pentium4_events)/sizeof(pentium4_events[0])) /* CPU_CLK_UNHALTED uses the global_power_events event. * INST_RETIRED uses the instr_retired event. */ #define PENTIUM4_CPU_CLK_UNHALTED 24 #define PENTIUM4_INST_RETIRED 38 #endif papi-5.5.1/src/libpfm-3.y/lib/pfmlib_amd64.c0000644000307100002310000005526213013651450020312 0ustar yarkhangraduate/* * pfmlib_amd64.c : support for the AMD64 architected PMU * (for both 64 and 32 bit modes) * * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* public headers */ #include /* private headers */ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_amd64_priv.h" /* architecture private */ #include "amd64_events.h" /* PMU private */ /* let's define some handy shortcuts! */ #define sel_event_mask perfsel.sel_event_mask #define sel_unit_mask perfsel.sel_unit_mask #define sel_usr perfsel.sel_usr #define sel_os perfsel.sel_os #define sel_edge perfsel.sel_edge #define sel_pc perfsel.sel_pc #define sel_int perfsel.sel_int #define sel_en perfsel.sel_en #define sel_inv perfsel.sel_inv #define sel_cnt_mask perfsel.sel_cnt_mask #define sel_event_mask2 perfsel.sel_event_mask2 #define sel_guest perfsel.sel_guest #define sel_host perfsel.sel_host #define CHECK_AMD_ARCH(reg) \ ((reg).sel_event_mask2 || (reg).sel_guest || (reg).sel_host) #define PFMLIB_AMD64_HAS_COMBO(_e) \ ((pfm_amd64_get_event_entry(_e)->pme_flags & PFMLIB_AMD64_UMASK_COMBO) != 0) #define PFMLIB_AMD64_ALL_FLAGS \ (PFM_AMD64_SEL_INV|PFM_AMD64_SEL_EDGE|PFM_AMD64_SEL_GUEST|PFM_AMD64_SEL_HOST) /* * Description of the PMC register mappings use by * this module: * pfp_pmcs[].reg_num: * 0 -> PMC0 -> PERFEVTSEL0 -> MSR @ 0xc0010000 * 1 -> PMC1 -> PERFEVTSEL1 -> MSR @ 0xc0010001 * ... * pfp_pmds[].reg_num: * 0 -> PMD0 -> PERCTR0 -> MSR @ 0xc0010004 * 1 -> PMD1 -> PERCTR1 -> MSR @ 0xc0010005 * ... */ #define AMD64_SEL_BASE 0xc0010000 #define AMD64_CTR_BASE 0xc0010004 #define AMD64_SEL_BASE_F15H 0xc0010200 #define AMD64_CTR_BASE_F15H 0xc0010201 static struct { amd64_rev_t revision; char *name; unsigned int cpu_clks; unsigned int ret_inst; int family; int model; int stepping; pme_amd64_entry_t *events; } amd64_pmu; pme_amd64_entry_t unsupported_event = { .pme_name = "", .pme_desc = "This event is not supported be this cpu revision.", .pme_code = ~0, .pme_flags = PFMLIB_AMD64_NOT_SUPP, }; pfm_pmu_support_t amd64_support; #define amd64_revision amd64_pmu.revision #define amd64_event_count amd64_support.pme_count #define amd64_cpu_clks amd64_pmu.cpu_clks #define amd64_ret_inst amd64_pmu.ret_inst #define amd64_events amd64_pmu.events #define amd64_family amd64_pmu.family #define amd64_model amd64_pmu.model #define amd64_stepping amd64_pmu.stepping /* AMD architectural pmu features starts with family 10h */ #define IS_AMD_ARCH() (amd64_pmu.family >= 0x10) static amd64_rev_t amd64_get_revision(int family, int model, int stepping) { switch (family) { case 6: return AMD64_K7; case 0x0f: switch (model >> 4) { case 0: if (model == 5 && stepping < 2) return AMD64_K8_REV_B; if (model == 4 && stepping == 0) return AMD64_K8_REV_B; return AMD64_K8_REV_C; case 1: return AMD64_K8_REV_D; case 2: case 3: return AMD64_K8_REV_E; case 4: case 5: case 0xc: return AMD64_K8_REV_F; case 6: case 7: case 8: return AMD64_K8_REV_G; } return AMD64_K8_REV_B; case 0x10: switch (model) { case 4: case 5: case 6: return AMD64_FAM10H_REV_C; case 8: case 9: return AMD64_FAM10H_REV_D; case 10: return AMD64_FAM10H_REV_E; } return AMD64_FAM10H_REV_B; case 0x15: return AMD64_FAM15H_REV_B; } return AMD64_CPU_UN; } /* * .byte 0x53 == push ebx. it's universal for 32 and 64 bit * .byte 0x5b == pop ebx. * Some gcc's (4.1.2 on Core2) object to pairing push/pop and ebx in 64 bit mode. * Using the opcode directly avoids this problem. */ static inline void cpuid(unsigned int op, unsigned int *a, unsigned int *b, unsigned int *c, unsigned int *d) { __asm__ __volatile__ (".byte 0x53\n\tcpuid\n\tmovl %%ebx, %%esi\n\t.byte 0x5b" : "=a" (*a), "=S" (*b), "=c" (*c), "=d" (*d) : "a" (op)); } static void pfm_amd64_setup(amd64_rev_t revision) { amd64_pmu.revision = revision; amd64_pmu.name = (char *)amd64_cpu_strs[revision]; amd64_support.pmu_name = amd64_pmu.name; /* K8 (default) */ amd64_pmu.events = amd64_k8_table.events; amd64_support.pme_count = amd64_k8_table.num; amd64_pmu.cpu_clks = amd64_k8_table.cpu_clks; amd64_pmu.ret_inst = amd64_k8_table.ret_inst; amd64_support.pmu_type = PFMLIB_AMD64_PMU; amd64_support.num_cnt = PMU_AMD64_NUM_COUNTERS; amd64_support.pmc_count = PMU_AMD64_NUM_COUNTERS; amd64_support.pmd_count = PMU_AMD64_NUM_COUNTERS; switch (amd64_pmu.family) { case 6: /* K7 */ amd64_pmu.events = amd64_k7_table.events; amd64_support.pme_count = amd64_k7_table.num; amd64_pmu.cpu_clks = amd64_k7_table.cpu_clks; amd64_pmu.ret_inst = amd64_k7_table.ret_inst; return; case 0x10: /* Family 10h */ amd64_pmu.events = amd64_fam10h_table.events; amd64_support.pme_count = amd64_fam10h_table.num; amd64_pmu.cpu_clks = amd64_fam10h_table.cpu_clks; amd64_pmu.ret_inst = amd64_fam10h_table.ret_inst; amd64_support.pmc_count = PMU_AMD64_NUM_PERFSEL; amd64_support.pmd_count = PMU_AMD64_NUM_PERFCTR; return; case 0x15: /* Family 15h */ amd64_pmu.events = amd64_fam15h_table.events; amd64_support.pme_count = amd64_fam15h_table.num; amd64_pmu.cpu_clks = amd64_fam15h_table.cpu_clks; amd64_pmu.ret_inst = amd64_fam15h_table.ret_inst; amd64_support.num_cnt = PMU_AMD64_NUM_COUNTERS_F15H; amd64_support.pmc_count = PMU_AMD64_NUM_PERFSEL; amd64_support.pmd_count = PMU_AMD64_NUM_PERFCTR; return; } } static int pfm_amd64_detect(void) { unsigned int a, b, c, d; char buffer[128]; cpuid(0, &a, &b, &c, &d); strncpy(&buffer[0], (char *)(&b), 4); strncpy(&buffer[4], (char *)(&d), 4); strncpy(&buffer[8], (char *)(&c), 4); buffer[12] = '\0'; if (strcmp(buffer, "AuthenticAMD")) return PFMLIB_ERR_NOTSUPP; cpuid(1, &a, &b, &c, &d); amd64_family = (a >> 8) & 0x0000000f; // bits 11 - 8 amd64_model = (a >> 4) & 0x0000000f; // Bits 7 - 4 if (amd64_family == 0xf) { amd64_family += (a >> 20) & 0x000000ff; // Extended family amd64_model |= (a >> 12) & 0x000000f0; // Extended model } amd64_stepping = a & 0x0000000f; // bits 3 - 0 amd64_revision = amd64_get_revision(amd64_family, amd64_model, amd64_stepping); if (amd64_revision == AMD64_CPU_UN) return PFMLIB_ERR_NOTSUPP; return PFMLIB_SUCCESS; } static void pfm_amd64_force(void) { char *str; int pmu_type; /* parses LIBPFM_FORCE_PMU=16,,, */ str = getenv("LIBPFM_FORCE_PMU"); if (!str) goto failed; pmu_type = strtol(str, &str, 10); if (pmu_type != PFMLIB_AMD64_PMU) goto failed; if (!*str || *str++ != ',') goto failed; amd64_family = strtol(str, &str, 10); if (!*str || *str++ != ',') goto failed; amd64_model = strtol(str, &str, 10); if (!*str || *str++ != ',') goto failed; amd64_stepping = strtol(str, &str, 10); if (!*str) goto done; failed: DPRINT("force failed at: %s\n", str ? str : ""); /* force AMD64 = force to Barcelona */ amd64_family = 16; amd64_model = 2; amd64_stepping = 2; done: amd64_revision = amd64_get_revision(amd64_family, amd64_model, amd64_stepping); } static int pfm_amd64_init(void) { if (forced_pmu != PFMLIB_NO_PMU) pfm_amd64_force(); __pfm_vbprintf("AMD family=%d model=0x%x stepping=0x%x rev=%s, %s\n", amd64_family, amd64_model, amd64_stepping, amd64_rev_strs[amd64_revision], amd64_cpu_strs[amd64_revision]); pfm_amd64_setup(amd64_revision); return PFMLIB_SUCCESS; } static int is_valid_rev(unsigned int flags, int revision) { if (revision < from_revision(flags)) return 0; if (revision > till_revision(flags)) return 0; /* no restrictions or matches restrictions */ return 1; } static inline pme_amd64_entry_t *pfm_amd64_get_event_entry(unsigned int index) { /* * Since there are no NULL pointer checks for the return * value, &unsupported_event is returned instead. Function * is_valid_index() may be used to validate the index. */ pme_amd64_entry_t *event; if (index >= amd64_event_count) return &unsupported_event; event = &amd64_events[index]; if (!is_valid_rev(event->pme_flags, amd64_revision)) return &unsupported_event; return event; } static inline int is_valid_index(unsigned int index) { return (pfm_amd64_get_event_entry(index) != &unsupported_event); } /* * Automatically dispatch events to corresponding counters following constraints. */ static int pfm_amd64_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_amd64_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfmlib_amd64_input_param_t *param = mod_in; pfmlib_amd64_counter_t *cntrs; pfm_amd64_sel_reg_t reg; pfmlib_event_t *e; pfmlib_reg_t *pc, *pd; pfmlib_regmask_t *r_pmcs; unsigned long plm; unsigned int i, j, k, cnt, umask; unsigned int assign[PMU_AMD64_MAX_COUNTERS]; e = inp->pfp_events; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; cnt = inp->pfp_event_count; r_pmcs = &inp->pfp_unavail_pmcs; cntrs = param ? param->pfp_amd64_counters : NULL; /* priviledge level 1 and 2 are not supported */ if (inp->pfp_dfl_plm & (PFM_PLM1|PFM_PLM2)) { DPRINT("invalid plm=%x\n", inp->pfp_dfl_plm); return PFMLIB_ERR_INVAL; } if (PFMLIB_DEBUG()) { for (j=0; j < cnt; j++) { DPRINT("ev[%d]=%s\n", j, pfm_amd64_get_event_entry(e[j].event)->pme_name); } } if (cnt > amd64_support.num_cnt) return PFMLIB_ERR_TOOMANY; for(i=0, j=0; j < cnt; j++, i++) { /* * AMD64 only supports two priv levels for perf counters */ if (e[j].plm & (PFM_PLM1|PFM_PLM2)) { DPRINT("event=%d invalid plm=%d\n", e[j].event, e[j].plm); return PFMLIB_ERR_INVAL; } /* * check illegal unit masks combination */ if (e[j].num_masks > 1 && PFMLIB_AMD64_HAS_COMBO(e[j].event) == 0) { DPRINT("event does not supports unit mask combination\n"); return PFMLIB_ERR_FEATCOMB; } /* * check revision restrictions at the event level * (check at the umask level later) */ if (!is_valid_rev(pfm_amd64_get_event_entry(e[i].event)->pme_flags, amd64_revision)) { DPRINT("CPU does not have correct revision level\n"); return PFMLIB_ERR_BADHOST; } if (cntrs && (cntrs[j].flags & ~PFMLIB_AMD64_ALL_FLAGS)) { DPRINT("invalid AMD64 flags\n"); return PFMLIB_ERR_INVAL; } if (cntrs && (cntrs[j].cnt_mask >= PMU_AMD64_CNT_MASK_MAX)) { DPRINT("event=%d invalid cnt_mask=%d: must be < %u\n", e[j].event, cntrs[j].cnt_mask, PMU_AMD64_CNT_MASK_MAX); return PFMLIB_ERR_INVAL; } /* * exclude unavailable registers from assignment */ while(i < amd64_support.num_cnt && pfm_regmask_isset(r_pmcs, i)) i++; if (i == amd64_support.num_cnt) return PFMLIB_ERR_NOASSIGN; assign[j] = i; } for (j=0; j < cnt ; j++ ) { reg.val = 0; /* assume reserved bits are zerooed */ /* if plm is 0, then assume not specified per-event and use default */ plm = e[j].plm ? e[j].plm : inp->pfp_dfl_plm; if (!is_valid_rev(pfm_amd64_get_event_entry(e[j].event)->pme_flags, amd64_revision)) return PFMLIB_ERR_BADHOST; reg.sel_event_mask = pfm_amd64_get_event_entry(e[j].event)->pme_code; reg.sel_event_mask2 = pfm_amd64_get_event_entry(e[j].event)->pme_code >> 8; umask = 0; for(k=0; k < e[j].num_masks; k++) { /* check unit mask revision restrictions */ if (!is_valid_rev(pfm_amd64_get_event_entry(e[j].event)->pme_umasks[e[j].unit_masks[k]].pme_uflags, amd64_revision)) return PFMLIB_ERR_BADHOST; umask |= pfm_amd64_get_event_entry(e[j].event)->pme_umasks[e[j].unit_masks[k]].pme_ucode; } if (e[j].event == PME_AMD64_IBSOP) { ibsopctl_t ibsopctl; ibsopctl.val = 0; ibsopctl.reg.ibsopen = 1; if (umask == 2 && amd64_revision < from_revision(PFMLIB_AMD64_FAM10H_REV_C)) { DPRINT("IBSOP:UOPS available on Rev C and later processors\n"); return PFMLIB_ERR_BADHOST; } /* * 1: cycles * 2: uops */ ibsopctl.reg.ibsopcntl = umask == 0x1 ? 0 : 1; pc[j].reg_value = ibsopctl.val; pc[j].reg_num = PMU_AMD64_IBSOPCTL_PMC; pc[j].reg_addr = 0xc0011033; __pfm_vbprintf("[IBSOPCTL(pmc%u)=0x%llx en=%d uops=%d maxcnt=0x%x]\n", PMU_AMD64_IBSOPCTL_PMD, ibsopctl.val, ibsopctl.reg.ibsopen, ibsopctl.reg.ibsopcntl, ibsopctl.reg.ibsopmaxcnt); pd[j].reg_num = PMU_AMD64_IBSOPCTL_PMD; pd[j].reg_addr = 0xc0011033; __pfm_vbprintf("[IBSOPCTL(pmd%u)]\n", PMU_AMD64_IBSOPCTL_PMD); } else if (e[j].event == PME_AMD64_IBSFETCH) { ibsfetchctl_t ibsfetchctl; ibsfetchctl.val = 0; ibsfetchctl.reg.ibsfetchen = 1; ibsfetchctl.reg.ibsranden = umask == 0x1 ? 1 : 0; pc[j].reg_value = ibsfetchctl.val; pc[j].reg_num = PMU_AMD64_IBSFETCHCTL_PMC; pc[j].reg_addr = 0xc0011031; pd[j].reg_num = PMU_AMD64_IBSFETCHCTL_PMD; pd[j].reg_addr = 0xc0011031; __pfm_vbprintf("[IBSFETCHCTL(pmc%u)=0x%llx en=%d maxcnt=0x%x rand=%u]\n", PMU_AMD64_IBSFETCHCTL_PMD, ibsfetchctl.val, ibsfetchctl.reg.ibsfetchen, ibsfetchctl.reg.ibsfetchmaxcnt, ibsfetchctl.reg.ibsranden); __pfm_vbprintf("[IBSOPFETCH(pmd%u)]\n", PMU_AMD64_IBSFETCHCTL_PMD); } else { reg.sel_unit_mask = umask; reg.sel_usr = plm & PFM_PLM3 ? 1 : 0; reg.sel_os = plm & PFM_PLM0 ? 1 : 0; reg.sel_en = 1; /* force enable bit to 1 */ reg.sel_int = 1; /* force APIC int to 1 */ if (cntrs) { reg.sel_cnt_mask = cntrs[j].cnt_mask; reg.sel_edge = cntrs[j].flags & PFM_AMD64_SEL_EDGE ? 1 : 0; reg.sel_inv = cntrs[j].flags & PFM_AMD64_SEL_INV ? 1 : 0; reg.sel_guest = cntrs[j].flags & PFM_AMD64_SEL_GUEST ? 1 : 0; reg.sel_host = cntrs[j].flags & PFM_AMD64_SEL_HOST ? 1 : 0; } pc[j].reg_num = assign[j]; if ((CHECK_AMD_ARCH(reg)) && !IS_AMD_ARCH()) return PFMLIB_ERR_BADHOST; if (amd64_support.num_cnt == PMU_AMD64_NUM_COUNTERS_F15H) { pc[j].reg_addr = AMD64_SEL_BASE_F15H + (assign[j] << 1); pd[j].reg_addr = AMD64_CTR_BASE_F15H + (assign[j] << 1); } else { pc[j].reg_addr = AMD64_SEL_BASE + assign[j]; pd[j].reg_addr = AMD64_CTR_BASE + assign[j]; } pc[j].reg_value = reg.val; pc[j].reg_alt_addr = pc[j].reg_addr; pd[j].reg_num = assign[j]; pd[j].reg_alt_addr = assign[j]; /* index to use with RDPMC */ __pfm_vbprintf("[PERFSEL%u(pmc%u)=0x%llx emask=0x%x umask=0x%x os=%d usr=%d inv=%d en=%d int=%d edge=%d cnt_mask=%d] %s\n", assign[j], assign[j], reg.val, reg.sel_event_mask, reg.sel_unit_mask, reg.sel_os, reg.sel_usr, reg.sel_inv, reg.sel_en, reg.sel_int, reg.sel_edge, reg.sel_cnt_mask, pfm_amd64_get_event_entry(e[j].event)->pme_name); __pfm_vbprintf("[PERFCTR%u(pmd%u)]\n", pd[j].reg_num, pd[j].reg_num); } } /* number of evtsel/ctr registers programmed */ outp->pfp_pmc_count = cnt; outp->pfp_pmd_count = cnt; return PFMLIB_SUCCESS; } static int pfm_amd64_dispatch_ibs(pfmlib_input_param_t *inp, pfmlib_amd64_input_param_t *inp_mod, pfmlib_output_param_t *outp, pfmlib_amd64_output_param_t *outp_mod) { unsigned int pmc_base, pmd_base; ibsfetchctl_t ibsfetchctl; ibsopctl_t ibsopctl; if (!inp_mod || !outp || !outp_mod) return PFMLIB_ERR_INVAL; if (!IS_AMD_ARCH()) return PFMLIB_ERR_BADHOST; /* IBS fetch profiling */ if (inp_mod->flags & PFMLIB_AMD64_USE_IBSFETCH) { /* check availability of a PMC and PMD */ if (outp->pfp_pmc_count >= PFMLIB_MAX_PMCS) return PFMLIB_ERR_NOASSIGN; if (outp->pfp_pmd_count >= PFMLIB_MAX_PMDS) return PFMLIB_ERR_NOASSIGN; pmc_base = outp->pfp_pmc_count; pmd_base = outp->pfp_pmd_count; outp->pfp_pmcs[pmc_base].reg_num = PMU_AMD64_IBSFETCHCTL_PMC; ibsfetchctl.val = 0; ibsfetchctl.reg.ibsfetchen = 1; ibsfetchctl.reg.ibsfetchmaxcnt = inp_mod->ibsfetch.maxcnt >> 4; if (inp_mod->ibsfetch.options & IBS_OPTIONS_RANDEN) ibsfetchctl.reg.ibsranden = 1; outp->pfp_pmcs[pmc_base].reg_value = ibsfetchctl.val; outp->pfp_pmds[pmd_base].reg_num = PMU_AMD64_IBSFETCHCTL_PMD; outp_mod->ibsfetch_base = pmd_base; ++outp->pfp_pmc_count; ++outp->pfp_pmd_count; } /* IBS execution profiling */ if (inp_mod->flags & PFMLIB_AMD64_USE_IBSOP) { /* check availability of a PMC and PMD */ if (outp->pfp_pmc_count >= PFMLIB_MAX_PMCS) return PFMLIB_ERR_NOASSIGN; if (outp->pfp_pmd_count >= PFMLIB_MAX_PMDS) return PFMLIB_ERR_NOASSIGN; pmc_base = outp->pfp_pmc_count; pmd_base = outp->pfp_pmd_count; outp->pfp_pmcs[pmc_base].reg_num = PMU_AMD64_IBSOPCTL_PMC; ibsopctl.val = 0; ibsopctl.reg.ibsopen = 1; ibsopctl.reg.ibsopmaxcnt = inp_mod->ibsop.maxcnt >> 4; if (inp_mod->ibsop.options & IBS_OPTIONS_UOPS) { if (amd64_revision < from_revision(PFMLIB_AMD64_FAM10H_REV_C)) { DPRINT("IBSOP:UOPS available on Rev C and later processors\n"); return PFMLIB_ERR_BADHOST; } ibsopctl.reg.ibsopcntl = 1; } outp->pfp_pmcs[pmc_base].reg_value = ibsopctl.val; outp->pfp_pmds[pmd_base].reg_num = PMU_AMD64_IBSOPCTL_PMD; outp_mod->ibsop_base = pmd_base; ++outp->pfp_pmc_count; ++outp->pfp_pmd_count; } return PFMLIB_SUCCESS; } static int pfm_amd64_dispatch_events( pfmlib_input_param_t *inp, void *_inp_mod, pfmlib_output_param_t *outp, void *outp_mod) { pfmlib_amd64_input_param_t *inp_mod = _inp_mod; int ret = PFMLIB_ERR_INVAL; if (!outp) return PFMLIB_ERR_INVAL; /* * At least one of the dispatch function calls must return * PFMLIB_SUCCESS */ if (inp && inp->pfp_event_count) { ret = pfm_amd64_dispatch_counters(inp, inp_mod, outp); if (ret != PFMLIB_SUCCESS) return ret; } if (inp_mod && inp_mod->flags & (PFMLIB_AMD64_USE_IBSOP | PFMLIB_AMD64_USE_IBSFETCH)) ret = pfm_amd64_dispatch_ibs(inp, inp_mod, outp, outp_mod); return ret; } static int pfm_amd64_get_event_code(unsigned int i, unsigned int cnt, int *code) { if (cnt != PFMLIB_CNT_FIRST && cnt >= amd64_support.num_cnt) return PFMLIB_ERR_INVAL; *code = pfm_amd64_get_event_entry(i)->pme_code; return PFMLIB_SUCCESS; } /* * This function is accessible directly to the user */ int pfm_amd64_get_event_umask(unsigned int i, unsigned long *umask) { if (i >= amd64_event_count || umask == NULL) return PFMLIB_ERR_INVAL; *umask = 0; //evt_umask(i); return PFMLIB_SUCCESS; } static void pfm_amd64_get_event_counters(unsigned int j, pfmlib_regmask_t *counters) { unsigned int i; memset(counters, 0, sizeof(*counters)); for(i=0; i < amd64_support.num_cnt; i++) pfm_regmask_set(counters, i); } static void pfm_amd64_get_impl_perfsel(pfmlib_regmask_t *impl_pmcs) { unsigned int i = 0; /* all pmcs are contiguous */ for(i=0; i < amd64_support.pmc_count; i++) pfm_regmask_set(impl_pmcs, i); } static void pfm_amd64_get_impl_perfctr(pfmlib_regmask_t *impl_pmds) { unsigned int i = 0; /* all pmds are contiguous */ for(i=0; i < amd64_support.pmd_count; i++) pfm_regmask_set(impl_pmds, i); } static void pfm_amd64_get_impl_counters(pfmlib_regmask_t *impl_counters) { unsigned int i = 0; /* counting pmds are contiguous */ for(i=0; i < amd64_support.num_cnt; i++) pfm_regmask_set(impl_counters, i); } static void pfm_amd64_get_hw_counter_width(unsigned int *width) { *width = PMU_AMD64_COUNTER_WIDTH; } static char * pfm_amd64_get_event_name(unsigned int i) { if (!is_valid_index(i)) return NULL; return pfm_amd64_get_event_entry(i)->pme_name; } static int pfm_amd64_get_event_desc(unsigned int ev, char **str) { char *s; s = pfm_amd64_get_event_entry(ev)->pme_desc; if (s) { *str = strdup(s); } else { *str = NULL; } return PFMLIB_SUCCESS; } static char * pfm_amd64_get_event_mask_name(unsigned int ev, unsigned int midx) { pme_amd64_umask_t *umask; umask = &pfm_amd64_get_event_entry(ev)->pme_umasks[midx]; if (!is_valid_rev(umask->pme_uflags, amd64_revision)) return NULL; return umask->pme_uname; } static int pfm_amd64_get_event_mask_desc(unsigned int ev, unsigned int midx, char **str) { char *s; s = pfm_amd64_get_event_entry(ev)->pme_umasks[midx].pme_udesc; if (s) { *str = strdup(s); } else { *str = NULL; } return PFMLIB_SUCCESS; } static unsigned int pfm_amd64_get_num_event_masks(unsigned int ev) { return pfm_amd64_get_event_entry(ev)->pme_numasks; } static int pfm_amd64_get_event_mask_code(unsigned int ev, unsigned int midx, unsigned int *code) { *code = pfm_amd64_get_event_entry(ev)->pme_umasks[midx].pme_ucode; return PFMLIB_SUCCESS; } static int pfm_amd64_get_cycle_event(pfmlib_event_t *e) { e->event = amd64_cpu_clks; return PFMLIB_SUCCESS; } static int pfm_amd64_get_inst_retired(pfmlib_event_t *e) { e->event = amd64_ret_inst; return PFMLIB_SUCCESS; } pfm_pmu_support_t amd64_support = { .pmu_name = "AMD64", .pmu_type = PFMLIB_AMD64_PMU, .pme_count = 0, .pmc_count = PMU_AMD64_NUM_COUNTERS, .pmd_count = PMU_AMD64_NUM_COUNTERS, .num_cnt = PMU_AMD64_NUM_COUNTERS, .get_event_code = pfm_amd64_get_event_code, .get_event_name = pfm_amd64_get_event_name, .get_event_counters = pfm_amd64_get_event_counters, .dispatch_events = pfm_amd64_dispatch_events, .pmu_detect = pfm_amd64_detect, .pmu_init = pfm_amd64_init, .get_impl_pmcs = pfm_amd64_get_impl_perfsel, .get_impl_pmds = pfm_amd64_get_impl_perfctr, .get_impl_counters = pfm_amd64_get_impl_counters, .get_hw_counter_width = pfm_amd64_get_hw_counter_width, .get_event_desc = pfm_amd64_get_event_desc, .get_num_event_masks = pfm_amd64_get_num_event_masks, .get_event_mask_name = pfm_amd64_get_event_mask_name, .get_event_mask_code = pfm_amd64_get_event_mask_code, .get_event_mask_desc = pfm_amd64_get_event_mask_desc, .get_cycle_event = pfm_amd64_get_cycle_event, .get_inst_retired_event = pfm_amd64_get_inst_retired }; papi-5.5.1/src/libpfm-3.y/lib/amd64_events_k7.h0000644000307100002310000001513213013651450020743 0ustar yarkhangraduate/* * Copyright (c) 2006, 2007 Advanced Micro Devices, Inc. * Contributed by Ray Bryant * Contributed by Robert Richter * Modified for K7 by Vince Weaver * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ /* * Definitions taken from "AMD Athlon Processor x86 Code Optimization Guide" * Table 11 February 2002 */ static pme_amd64_entry_t amd64_k7_pe[]={ /* 0 */{.pme_name = "DATA_CACHE_ACCESSES", .pme_code = 0x40, .pme_desc = "Data Cache Accesses", }, /* 1 */{.pme_name = "DATA_CACHE_MISSES", .pme_code = 0x41, .pme_desc = "Data Cache Misses", }, /* 2 */{.pme_name = "DATA_CACHE_REFILLS", .pme_code = 0x42, .pme_desc = "Data Cache Refills from L2", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 6, .pme_umasks = { { .pme_uname = "L2_INVALID", .pme_udesc = "Invalid line from L2", .pme_ucode = 0x01, }, { .pme_uname = "L2_SHARED", .pme_udesc = "Shared-state line from L2", .pme_ucode = 0x02, }, { .pme_uname = "L2_EXCLUSIVE", .pme_udesc = "Exclusive-state line from L2", .pme_ucode = 0x04, }, { .pme_uname = "L2_OWNED", .pme_udesc = "Owned-state line from L2", .pme_ucode = 0x08, }, { .pme_uname = "L2_MODIFIED", .pme_udesc = "Modified-state line from L2", .pme_ucode = 0x10, }, { .pme_uname = "ALL", .pme_udesc = "Shared, Exclusive, Owned, Modified State Refills", .pme_ucode = 0x1F, }, }, }, /* 3 */{.pme_name = "DATA_CACHE_REFILLS_FROM_SYSTEM", .pme_code = 0x43, .pme_desc = "Data Cache Refills from System", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 6, .pme_umasks = { { .pme_uname = "INVALID", .pme_udesc = "Invalid", .pme_ucode = 0x01, }, { .pme_uname = "SHARED", .pme_udesc = "Shared", .pme_ucode = 0x02, }, { .pme_uname = "EXCLUSIVE", .pme_udesc = "Exclusive", .pme_ucode = 0x04, }, { .pme_uname = "OWNED", .pme_udesc = "Owned", .pme_ucode = 0x08, }, { .pme_uname = "MODIFIED", .pme_udesc = "Modified", .pme_ucode = 0x10, }, { .pme_uname = "ALL", .pme_udesc = "Invalid, Shared, Exclusive, Owned, Modified", .pme_ucode = 0x1F, }, }, }, /* 4 */{.pme_name = "DATA_CACHE_LINES_EVICTED", .pme_code = 0x44, .pme_desc = "Data Cache Lines Evicted", .pme_flags = PFMLIB_AMD64_UMASK_COMBO, .pme_numasks = 6, .pme_umasks = { { .pme_uname = "INVALID", .pme_udesc = "Invalid", .pme_ucode = 0x01, }, { .pme_uname = "SHARED", .pme_udesc = "Shared", .pme_ucode = 0x02, }, { .pme_uname = "EXCLUSIVE", .pme_udesc = "Exclusive", .pme_ucode = 0x04, }, { .pme_uname = "OWNED", .pme_udesc = "Owned", .pme_ucode = 0x08, }, { .pme_uname = "MODIFIED", .pme_udesc = "Modified", .pme_ucode = 0x10, }, { .pme_uname = "ALL", .pme_udesc = "Invalid, Shared, Exclusive, Owned, Modified", .pme_ucode = 0x1F, }, }, }, /* 5 */{.pme_name = "L1_DTLB_MISS_AND_L2_DTLB_HIT", .pme_code = 0x45, .pme_desc = "L1 DTLB Miss and L2 DTLB Hit", }, /* 6 */{.pme_name = "L1_DTLB_AND_L2_DTLB_MISS", .pme_code = 0x46, .pme_desc = "L1 DTLB and L2 DTLB Miss", }, /* 7 */{.pme_name = "MISALIGNED_ACCESSES", .pme_code = 0x47, .pme_desc = "Misaligned Accesses", }, /* CPU_CLK_UNHALTED is undocumented in the Athlon Guide? */ /* 8 */{.pme_name = "CPU_CLK_UNHALTED", .pme_code = 0x76, .pme_desc = "CPU Clocks not Halted", }, /* 9 */{.pme_name = "INSTRUCTION_CACHE_FETCHES", .pme_code = 0x80, .pme_desc = "Instruction Cache Fetches", }, /* 10 */{.pme_name = "INSTRUCTION_CACHE_MISSES", .pme_code = 0x81, .pme_desc = "Instruction Cache Misses", }, /* 11 */{.pme_name = "L1_ITLB_MISS_AND_L2_ITLB_HIT", .pme_code = 0x84, .pme_desc = "L1 ITLB Miss and L2 ITLB Hit", }, /* 12 */{.pme_name = "L1_ITLB_MISS_AND_L2_ITLB_MISS", .pme_code = 0x85, .pme_desc = "L1 ITLB Miss and L2 ITLB Miss", }, /* 13 */{.pme_name = "RETIRED_INSTRUCTIONS", .pme_code = 0xC0, .pme_desc = "Retired Instructions (includes exceptions, interrupts, resyncs)", }, /* 14 */{.pme_name = "RETIRED_UOPS", .pme_code = 0xC1, .pme_desc = "Retired uops", }, /* 15 */{.pme_name = "RETIRED_BRANCH_INSTRUCTIONS", .pme_code = 0xC2, .pme_desc = "Retired Branch Instructions", }, /* 16 */{.pme_name = "RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS", .pme_code = 0xC3, .pme_desc = "Retired Mispredicted Branch Instructions", }, /* 17 */{.pme_name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS", .pme_code = 0xC4, .pme_desc = "Retired Taken Branch Instructions", }, /* 18 */{.pme_name = "RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED", .pme_code = 0xC5, .pme_desc = "Retired Taken Branch Instructions Mispredicted", }, /* 19 */{.pme_name = "RETIRED_FAR_CONTROL_TRANSFERS", .pme_code = 0xC6, .pme_desc = "Retired Far Control Transfers", }, /* 20 */{.pme_name = "RETIRED_BRANCH_RESYNCS", .pme_code = 0xC7, .pme_desc = "Retired Branch Resyncs (only non-control transfer branches)", }, /* 21 */{.pme_name = "INTERRUPTS_MASKED_CYCLES", .pme_code = 0xCD, .pme_desc = "Interrupts-Masked Cycles", }, /* 22 */{.pme_name = "INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING", .pme_code = 0xCE, .pme_desc = "Interrupts-Masked Cycles with Interrupt Pending", }, /* 23 */{.pme_name = "INTERRUPTS_TAKEN", .pme_code = 0xCF, .pme_desc = "Interrupts Taken", }, }; #define PME_AMD64_K7_EVENT_COUNT (sizeof(amd64_k7_pe)/sizeof(pme_amd64_entry_t)) #define PME_AMD64_K7_CPU_CLK_UNHALTED 8 #define PME_AMD64_K7_RETIRED_INSTRUCTIONS 13 papi-5.5.1/src/libpfm-3.y/lib/intel_atom_events.h0000644000307100002310000006641513013651450021574 0ustar yarkhangraduate/* * Copyright (c) 2008 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ /* table 18.11 */ #define INTEL_ATOM_MESI \ { .pme_uname = "MESI",\ .pme_udesc = "Any cacheline access",\ .pme_ucode = 0xf\ },\ { .pme_uname = "I_STATE",\ .pme_udesc = "Invalid cacheline",\ .pme_ucode = 0x1\ },\ { .pme_uname = "S_STATE",\ .pme_udesc = "Shared cacheline",\ .pme_ucode = 0x2\ },\ { .pme_uname = "E_STATE",\ .pme_udesc = "Exclusive cacheline",\ .pme_ucode = 0x4\ },\ { .pme_uname = "M_STATE",\ .pme_udesc = "Modified cacheline",\ .pme_ucode = 0x8\ } /* table 18.9 */ #define INTEL_ATOM_AGENT \ { .pme_uname = "THIS_AGENT",\ .pme_udesc = "This agent",\ .pme_ucode = 0x00\ },\ { .pme_uname = "ALL_AGENTS",\ .pme_udesc = "Any agent on the bus",\ .pme_ucode = 0x20\ } /* table 18.8 */ #define INTEL_ATOM_CORE \ { .pme_uname = "SELF",\ .pme_udesc = "This core",\ .pme_ucode = 0x40\ },\ { .pme_uname = "BOTH_CORES",\ .pme_udesc = "Both cores",\ .pme_ucode = 0xc0\ } /* table 18.10 */ #define INTEL_ATOM_PREFETCH \ { .pme_uname = "ANY",\ .pme_udesc = "All inclusive",\ .pme_ucode = 0x30\ },\ { .pme_uname = "PREFETCH",\ .pme_udesc = "Hardware prefetch only",\ .pme_ucode = 0x10\ } static pme_intel_atom_entry_t intel_atom_pe[]={ /* * BEGIN architectural perfmon events */ /* 0 */{.pme_name = "UNHALTED_CORE_CYCLES", .pme_code = 0x003c, .pme_flags = PFMLIB_INTEL_ATOM_FIXED1, .pme_desc = "Unhalted core cycles", }, /* 1 */{.pme_name = "UNHALTED_REFERENCE_CYCLES", .pme_code = 0x013c, .pme_flags = PFMLIB_INTEL_ATOM_FIXED2_ONLY, .pme_desc = "Unhalted reference cycles. Measures bus cycles" }, /* 2 */{.pme_name = "INSTRUCTIONS_RETIRED", .pme_code = 0xc0, .pme_flags = PFMLIB_INTEL_ATOM_FIXED0|PFMLIB_INTEL_ATOM_PEBS, .pme_desc = "Instructions retired" }, /* 3 */{.pme_name = "LAST_LEVEL_CACHE_REFERENCES", .pme_code = 0x4f2e, .pme_desc = "Last level of cache references" }, /* 4 */{.pme_name = "LAST_LEVEL_CACHE_MISSES", .pme_code = 0x412e, .pme_desc = "Last level of cache misses", }, /* 5 */{.pme_name = "BRANCH_INSTRUCTIONS_RETIRED", .pme_code = 0xc4, .pme_desc = "Branch instructions retired" }, /* 6 */{.pme_name = "MISPREDICTED_BRANCH_RETIRED", .pme_code = 0xc5, .pme_flags = PFMLIB_INTEL_ATOM_PEBS, .pme_desc = "Mispredicted branch instruction retired" }, /* * BEGIN non architectural events */ { .pme_name = "SIMD_INSTR_RETIRED", .pme_desc = "SIMD Instructions retired", .pme_code = 0xCE, .pme_flags = 0, }, { .pme_name = "L2_REJECT_BUSQ", .pme_desc = "Rejected L2 cache requests", .pme_code = 0x30, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_MESI, INTEL_ATOM_CORE, INTEL_ATOM_PREFETCH }, .pme_numasks = 9, }, { .pme_name = "SIMD_SAT_INSTR_RETIRED", .pme_desc = "Saturated arithmetic instructions retired", .pme_code = 0xCF, .pme_flags = 0, }, { .pme_name = "ICACHE", .pme_desc = "Instruction fetches", .pme_code = 0x80, .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ACCESSES", .pme_udesc = "Instruction fetches, including uncacheacble fetches", .pme_ucode = 0x3, }, { .pme_uname = "MISSES", .pme_udesc = "count all instructions fetches that miss tha icache or produce memory requests. This includes uncacheache fetches. Any instruction fetch miss is counted only once and not once for every cycle it is outstanding", .pme_ucode = 0x2, }, }, .pme_numasks = 2 }, { .pme_name = "L2_LOCK", .pme_desc = "L2 locked accesses", .pme_code = 0x2B, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_MESI, INTEL_ATOM_CORE }, .pme_numasks = 7 }, { .pme_name = "UOPS_RETIRED", .pme_desc = "Micro-ops retired", .pme_code = 0xC2, .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "Micro-ops retired", .pme_ucode = 0x10, }, { .pme_uname = "STALLED_CYCLES", .pme_udesc = "Cycles no micro-ops retired", .pme_ucode = 0x1d010, /* inv=1 cnt_mask=1 */ }, { .pme_uname = "STALLS", .pme_udesc = "Periods no micro-ops retired", .pme_ucode = 0x1d410, /* inv=1 edge=1, cnt_mask=1 */ }, }, .pme_numasks = 3 }, { .pme_name = "L2_M_LINES_OUT", .pme_desc = "Modified lines evicted from the L2 cache", .pme_code = 0x27, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_CORE, INTEL_ATOM_PREFETCH }, .pme_numasks = 4 }, { .pme_name = "SIMD_COMP_INST_RETIRED", .pme_desc = "Retired computational Streaming SIMD Extensions (SSE) instructions", .pme_code = 0xCA, .pme_flags = 0, .pme_umasks = { { .pme_uname = "PACKED_SINGLE", .pme_udesc = "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions", .pme_ucode = 0x1, }, { .pme_uname = "SCALAR_SINGLE", .pme_udesc = "Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions", .pme_ucode = 0x2, }, { .pme_uname = "PACKED_DOUBLE", .pme_udesc = "Retired computational Streaming SIMD Extensions 2 (SSE2) packed-double instructions", .pme_ucode = 0x4, }, { .pme_uname = "SCALAR_DOUBLE", .pme_udesc = "Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions", .pme_ucode = 0x8, }, }, .pme_numasks = 4 }, { .pme_name = "SNOOP_STALL_DRV", .pme_desc = "Bus stalled for snoops", .pme_code = 0x7E, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_CORE, INTEL_ATOM_AGENT, }, .pme_numasks = 4 }, { .pme_name = "BUS_TRANS_BURST", .pme_desc = "Burst (full cache-line) bus transactions", .pme_code = 0x6E, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_CORE, INTEL_ATOM_AGENT, }, .pme_numasks = 4 }, { .pme_name = "SIMD_SAT_UOP_EXEC", .pme_desc = "SIMD saturated arithmetic micro-ops executed", .pme_code = 0xB1, .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "S", .pme_udesc = "SIMD saturated arithmetic micro-ops executed", .pme_ucode = 0x0, }, { .pme_uname = "AR", .pme_udesc = "SIMD saturated arithmetic micro-ops retired", .pme_ucode = 0x80, }, }, .pme_numasks = 2 }, { .pme_name = "BUS_TRANS_IO", .pme_desc = "IO bus transactions", .pme_code = 0x6C, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_CORE, INTEL_ATOM_AGENT }, .pme_numasks = 4 }, { .pme_name = "BUS_TRANS_RFO", .pme_desc = "RFO bus transactions", .pme_code = 0x66, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_CORE, INTEL_ATOM_AGENT }, .pme_numasks = 4 }, { .pme_name = "SIMD_ASSIST", .pme_desc = "SIMD assists invoked", .pme_code = 0xCD, .pme_flags = 0, }, { .pme_name = "INST_RETIRED", .pme_desc = "Instructions retired", .pme_code = 0xC0, .pme_flags = 0, .pme_umasks = { { .pme_uname = "ANY_P", .pme_udesc = "Instructions retired using generic counter (precise event)", .pme_ucode = 0x0, .pme_flags = PFMLIB_INTEL_ATOM_PEBS }, }, .pme_numasks = 1 }, { .pme_name = "L1D_CACHE", .pme_desc = "L1 Cacheable Data Reads", .pme_code = 0x40, .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "LD", .pme_udesc = "L1 Cacheable Data Reads", .pme_ucode = 0x21, }, { .pme_uname = "ST", .pme_udesc = "L1 Cacheable Data Writes", .pme_ucode = 0x22, }, }, .pme_numasks = 2 }, { .pme_name = "MUL", .pme_desc = "Multiply operations executed", .pme_code = 0x12, .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "S", .pme_udesc = "Multiply operations executed", .pme_ucode = 0x1, }, { .pme_uname = "AR", .pme_udesc = "Multiply operations retired", .pme_ucode = 0x81, }, }, .pme_numasks = 2 }, { .pme_name = "DIV", .pme_desc = "Divide operations executed", .pme_code = 0x13, .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "S", .pme_udesc = "Divide operations executed", .pme_ucode = 0x1, }, { .pme_uname = "AR", .pme_udesc = "Divide operations retired", .pme_ucode = 0x81, }, }, .pme_numasks = 2 }, { .pme_name = "BUS_TRANS_P", .pme_desc = "Partial bus transactions", .pme_code = 0x6b, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_AGENT, INTEL_ATOM_CORE, }, .pme_numasks = 4 }, { .pme_name = "BUS_IO_WAIT", .pme_desc = "IO requests waiting in the bus queue", .pme_code = 0x7F, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_CORE }, .pme_numasks = 2 }, { .pme_name = "L2_M_LINES_IN", .pme_desc = "L2 cache line modifications", .pme_code = 0x25, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_CORE }, .pme_numasks = 2 }, { .pme_name = "L2_LINES_IN", .pme_desc = "L2 cache misses", .pme_code = 0x24, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_CORE, INTEL_ATOM_PREFETCH }, .pme_numasks = 4 }, { .pme_name = "BUSQ_EMPTY", .pme_desc = "Bus queue is empty", .pme_code = 0x7D, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_CORE }, .pme_numasks = 2 }, { .pme_name = "L2_IFETCH", .pme_desc = "L2 cacheable instruction fetch requests", .pme_code = 0x28, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_MESI, INTEL_ATOM_CORE }, .pme_numasks = 7 }, { .pme_name = "BUS_HITM_DRV", .pme_desc = "HITM signal asserted", .pme_code = 0x7B, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_AGENT }, .pme_numasks = 2 }, { .pme_name = "ITLB", .pme_desc = "ITLB hits", .pme_code = 0x82, .pme_flags = 0, .pme_umasks = { { .pme_uname = "FLUSH", .pme_udesc = "ITLB flushes", .pme_ucode = 0x4, }, { .pme_uname = "MISSES", .pme_udesc = "ITLB misses", .pme_ucode = 0x2, }, }, .pme_numasks = 2 }, { .pme_name = "BUS_TRANS_MEM", .pme_desc = "Memory bus transactions", .pme_code = 0x6F, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_CORE, INTEL_ATOM_AGENT, }, .pme_numasks = 4 }, { .pme_name = "BUS_TRANS_PWR", .pme_desc = "Partial write bus transaction", .pme_code = 0x6A, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_CORE, INTEL_ATOM_AGENT, }, .pme_numasks = 4 }, { .pme_name = "BR_INST_DECODED", .pme_desc = "Branch instructions decoded", .pme_code = 0x1E0, .pme_flags = 0, }, { .pme_name = "BUS_TRANS_INVAL", .pme_desc = "Invalidate bus transactions", .pme_code = 0x69, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_CORE, INTEL_ATOM_AGENT }, .pme_numasks = 4 }, { .pme_name = "SIMD_UOP_TYPE_EXEC", .pme_desc = "SIMD micro-ops executed", .pme_code = 0xB3, .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "MUL_S", .pme_udesc = "SIMD packed multiply micro-ops executed", .pme_ucode = 0x1, }, { .pme_uname = "MUL_AR", .pme_udesc = "SIMD packed multiply micro-ops retired", .pme_ucode = 0x81, }, { .pme_uname = "SHIFT_S", .pme_udesc = "SIMD packed shift micro-ops executed", .pme_ucode = 0x2, }, { .pme_uname = "SHIFT_AR", .pme_udesc = "SIMD packed shift micro-ops retired", .pme_ucode = 0x82, }, { .pme_uname = "PACK_S", .pme_udesc = "SIMD packed micro-ops executed", .pme_ucode = 0x4, }, { .pme_uname = "PACK_AR", .pme_udesc = "SIMD packed micro-ops retired", .pme_ucode = 0x84, }, { .pme_uname = "UNPACK_S", .pme_udesc = "SIMD unpacked micro-ops executed", .pme_ucode = 0x8, }, { .pme_uname = "UNPACK_AR", .pme_udesc = "SIMD unpacked micro-ops retired", .pme_ucode = 0x88, }, { .pme_uname = "LOGICAL_S", .pme_udesc = "SIMD packed logical micro-ops executed", .pme_ucode = 0x10, }, { .pme_uname = "LOGICAL_AR", .pme_udesc = "SIMD packed logical micro-ops retired", .pme_ucode = 0x90, }, { .pme_uname = "ARITHMETIC_S", .pme_udesc = "SIMD packed arithmetic micro-ops executed", .pme_ucode = 0x20, }, { .pme_uname = "ARITHMETIC_AR", .pme_udesc = "SIMD packed arithmetic micro-ops retired", .pme_ucode = 0xA0, }, }, .pme_numasks = 12 }, { .pme_name = "SIMD_INST_RETIRED", .pme_desc = "Retired Streaming SIMD Extensions (SSE)", .pme_code = 0xC7, .pme_flags = 0, .pme_umasks = { { .pme_uname = "PACKED_SINGLE", .pme_udesc = "Retired Streaming SIMD Extensions (SSE) packed-single instructions", .pme_ucode = 0x1, }, { .pme_uname = "SCALAR_SINGLE", .pme_udesc = "Retired Streaming SIMD Extensions (SSE) scalar-single instructions", .pme_ucode = 0x2, }, { .pme_uname = "PACKED_DOUBLE", .pme_udesc = "Retired Streaming SIMD Extensions 2 (SSE2) packed-double instructions", .pme_ucode = 0x4, }, { .pme_uname = "SCALAR_DOUBLE", .pme_udesc = "Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions", .pme_ucode = 0x8, }, { .pme_uname = "VECTOR", .pme_udesc = "Retired Streaming SIMD Extensions 2 (SSE2) vector instructions", .pme_ucode = 0x10, }, { .pme_uname = "ANY", .pme_udesc = "Retired Streaming SIMD instructions", .pme_ucode = 0x1F, }, }, .pme_numasks = 6 }, { .pme_name = "CYCLES_DIV_BUSY", .pme_desc = "Cycles the divider is busy", .pme_code = 0x14, .pme_flags = 0, }, { .pme_name = "PREFETCH", .pme_desc = "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed", .pme_code = 0x7, .pme_flags = 0, .pme_umasks = { { .pme_uname = "PREFETCHT0", .pme_udesc = "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed", .pme_ucode = 0x01, }, { .pme_uname = "SW_L2", .pme_udesc = "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed", .pme_ucode = 0x06, }, { .pme_uname = "PREFETCHNTA", .pme_udesc = "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed", .pme_ucode = 0x08, }, }, .pme_numasks = 3 }, { .pme_name = "L2_RQSTS", .pme_desc = "L2 cache requests", .pme_code = 0x2E, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_CORE, INTEL_ATOM_PREFETCH, INTEL_ATOM_MESI }, .pme_numasks = 9 }, { .pme_name = "SIMD_UOPS_EXEC", .pme_desc = "SIMD micro-ops executed (excluding stores)", .pme_code = 0xB0, .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "S", .pme_udesc = "number of SMD saturated arithmetic micro-ops executed", .pme_ucode = 0x0, }, { .pme_uname = "AR", .pme_udesc = "number of SIMD saturated arithmetic micro-ops retired", .pme_ucode = 0x80, }, }, .pme_numasks = 2 }, { .pme_name = "HW_INT_RCV", .pme_desc = "Hardware interrupts received", .pme_code = 0xC8, .pme_flags = 0, }, { .pme_name = "BUS_TRANS_BRD", .pme_desc = "Burst read bus transactions", .pme_code = 0x65, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_AGENT, INTEL_ATOM_CORE }, .pme_numasks = 4 }, { .pme_name = "BOGUS_BR", .pme_desc = "Bogus branches", .pme_code = 0xE4, .pme_flags = 0, }, { .pme_name = "BUS_DATA_RCV", .pme_desc = "Bus cycles while processor receives data", .pme_code = 0x64, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_CORE, }, .pme_numasks = 2 }, { .pme_name = "MACHINE_CLEARS", .pme_desc = "Self-Modifying Code detected", .pme_code = 0xC3, .pme_flags = 0, .pme_umasks = { { .pme_uname = "SMC", .pme_udesc = "Self-Modifying Code detected", .pme_ucode = 0x1, }, }, .pme_numasks = 1 }, { .pme_name = "BR_INST_RETIRED", .pme_desc = "Retired branch instructions", .pme_code = 0xC4, .pme_flags = 0, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "Retired branch instructions", .pme_ucode = 0x0, }, { .pme_uname = "PRED_NOT_TAKEN", .pme_udesc = "Retired branch instructions that were predicted not-taken", .pme_ucode = 0x1, }, { .pme_uname = "MISPRED_NOT_TAKEN", .pme_udesc = "Retired branch instructions that were mispredicted not-taken", .pme_ucode = 0x2, }, { .pme_uname = "PRED_TAKEN", .pme_udesc = "Retired branch instructions that were predicted taken", .pme_ucode = 0x4, }, { .pme_uname = "MISPRED_TAKEN", .pme_udesc = "Retired branch instructions that were mispredicted taken", .pme_ucode = 0x8, }, { .pme_uname = "MISPRED", .pme_udesc = "Retired mispredicted branch instructions (precise event)", .pme_flags = PFMLIB_INTEL_ATOM_PEBS, .pme_ucode = 0xA, }, { .pme_uname = "TAKEN", .pme_udesc = "Retired taken branch instructions", .pme_ucode = 0xC, }, { .pme_uname = "ANY1", .pme_udesc = "Retired branch instructions", .pme_ucode = 0xF, }, }, .pme_numasks = 8 }, { .pme_name = "L2_ADS", .pme_desc = "Cycles L2 address bus is in use", .pme_code = 0x21, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_CORE }, .pme_numasks = 2 }, { .pme_name = "EIST_TRANS", .pme_desc = "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions", .pme_code = 0x3A, .pme_flags = 0, }, { .pme_name = "BUS_TRANS_WB", .pme_desc = "Explicit writeback bus transactions", .pme_code = 0x67, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_CORE, INTEL_ATOM_AGENT }, .pme_numasks = 4 }, { .pme_name = "MACRO_INSTS", .pme_desc = "Macro instructions decoded", .pme_code = 0xAA, .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "NON_CISC_DECODED", .pme_udesc = "Non-CISC macro instructions decoded", .pme_ucode = 0x1, }, { .pme_uname = "ALL_DECODED", .pme_udesc = "All Instructions decoded", .pme_ucode = 0x3, }, }, .pme_numasks = 2 }, { .pme_name = "L2_LINES_OUT", .pme_desc = "L2 cache lines evicted", .pme_code = 0x26, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_CORE, INTEL_ATOM_PREFETCH }, .pme_numasks = 4 }, { .pme_name = "L2_LD", .pme_desc = "L2 cache reads", .pme_code = 0x29, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_CORE, INTEL_ATOM_PREFETCH, INTEL_ATOM_MESI }, .pme_numasks = 9 }, { .pme_name = "SEGMENT_REG_LOADS", .pme_desc = "Number of segment register loads", .pme_code = 0x6, .pme_flags = 0, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "Number of segment register loads", .pme_ucode = 0x80, }, }, .pme_numasks = 1 }, { .pme_name = "L2_NO_REQ", .pme_desc = "Cycles no L2 cache requests are pending", .pme_code = 0x32, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_CORE }, .pme_numasks = 2 }, { .pme_name = "THERMAL_TRIP", .pme_desc = "Number of thermal trips", .pme_code = 0xC03B, .pme_flags = 0, }, { .pme_name = "EXT_SNOOP", .pme_desc = "External snoops", .pme_code = 0x77, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_MESI, INTEL_ATOM_CORE }, .pme_numasks = 7 }, { .pme_name = "BACLEARS", .pme_desc = "BACLEARS asserted", .pme_code = 0xE6, .pme_flags = 0, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "BACLEARS asserted", .pme_ucode = 0x1, }, }, .pme_numasks = 1 }, { .pme_name = "CYCLES_INT_MASKED", .pme_desc = "Cycles during which interrupts are disabled", .pme_code = 0xC6, .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "CYCLES_INT_MASKED", .pme_udesc = "Cycles during which interrupts are disabled", .pme_ucode = 0x1, }, { .pme_uname = "CYCLES_INT_PENDING_AND_MASKED", .pme_udesc = "Cycles during which interrupts are pending and disabled", .pme_ucode = 0x2, }, }, .pme_numasks = 2 }, { .pme_name = "FP_ASSIST", .pme_desc = "Floating point assists", .pme_code = 0x11, .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "S", .pme_udesc = "Floating point assists for executed instructions", .pme_ucode = 0x1, }, { .pme_uname = "AR", .pme_udesc = "Floating point assists for retired instructions", .pme_ucode = 0x81, }, }, .pme_numasks = 2 }, { .pme_name = "L2_ST", .pme_desc = "L2 store requests", .pme_code = 0x2A, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_MESI, INTEL_ATOM_CORE }, .pme_numasks = 7 }, { .pme_name = "BUS_TRANS_DEF", .pme_desc = "Deferred bus transactions", .pme_code = 0x6D, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_CORE, INTEL_ATOM_AGENT }, .pme_numasks = 4 }, { .pme_name = "DATA_TLB_MISSES", .pme_desc = "Memory accesses that missed the DTLB", .pme_code = 0x8, .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "DTLB_MISS", .pme_udesc = "Memory accesses that missed the DTLB", .pme_ucode = 0x7, }, { .pme_uname = "DTLB_MISS_LD", .pme_udesc = "DTLB misses due to load operations", .pme_ucode = 0x5, }, { .pme_uname = "L0_DTLB_MISS_LD", .pme_udesc = "L0 (micro-TLB) misses due to load operations", .pme_ucode = 0x9, }, { .pme_uname = "DTLB_MISS_ST", .pme_udesc = "DTLB misses due to store operations", .pme_ucode = 0x6, }, }, .pme_numasks = 4 }, { .pme_name = "BUS_BNR_DRV", .pme_desc = "Number of Bus Not Ready signals asserted", .pme_code = 0x61, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_AGENT }, .pme_numasks = 2 }, { .pme_name = "STORE_FORWARDS", .pme_desc = "All store forwards", .pme_code = 0x2, .pme_flags = 0, .pme_umasks = { { .pme_uname = "GOOD", .pme_udesc = "Good store forwards", .pme_ucode = 0x81, }, }, .pme_numasks = 1 }, { .pme_name = "CPU_CLK_UNHALTED", .pme_code = 0x3c, .pme_desc = "Core cycles when core is not halted", .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "CORE_P", .pme_udesc = "Core cycles when core is not halted", .pme_ucode = 0x0, }, { .pme_uname = "BUS", .pme_udesc = "Bus cycles when core is not halted. This event can give a measurement of the elapsed time. This events has a constant ratio with CPU_CLK_UNHALTED:REF event, which is the maximum bus to processor frequency ratio", .pme_ucode = 0x1, }, { .pme_uname = "NO_OTHER", .pme_udesc = "Bus cycles when core is active and other is halted", .pme_ucode = 0x2, }, }, .pme_numasks = 3 }, { .pme_name = "BUS_TRANS_ANY", .pme_desc = "All bus transactions", .pme_code = 0x70, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_CORE, INTEL_ATOM_AGENT }, .pme_numasks = 4 }, { .pme_name = "MEM_LOAD_RETIRED", .pme_desc = "Retired loads that hit the L2 cache (precise event)", .pme_code = 0xCB, .pme_flags = 0, .pme_umasks = { { .pme_uname = "L2_HIT", .pme_udesc = "Retired loads that hit the L2 cache (precise event)", .pme_ucode = 0x1, .pme_flags = PFMLIB_INTEL_ATOM_PEBS }, { .pme_uname = "L2_MISS", .pme_udesc = "Retired loads that miss the L2 cache (precise event)", .pme_ucode = 0x2, .pme_flags = PFMLIB_INTEL_ATOM_PEBS }, { .pme_uname = "DTLB_MISS", .pme_udesc = "Retired loads that miss the DTLB (precise event)", .pme_ucode = 0x4, .pme_flags = PFMLIB_INTEL_ATOM_PEBS }, }, .pme_numasks = 3 }, { .pme_name = "X87_COMP_OPS_EXE", .pme_desc = "Floating point computational micro-ops executed", .pme_code = 0x10, .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY_S", .pme_udesc = "Floating point computational micro-ops executed", .pme_ucode = 0x1, }, { .pme_uname = "ANY_AR", .pme_udesc = "Floating point computational micro-ops retired", .pme_ucode = 0x81, }, }, .pme_numasks = 2 }, { .pme_name = "PAGE_WALKS", .pme_desc = "Number of page-walks executed", .pme_code = 0xC, .pme_flags = PFMLIB_INTEL_ATOM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "WALKS", .pme_udesc = "Number of page-walks executed", .pme_ucode = 0x3 | 1ul << 10, }, { .pme_uname = "CYCLES", .pme_udesc = "Duration of page-walks in core cycles", .pme_ucode = 0x3, }, }, .pme_numasks = 2 }, { .pme_name = "BUS_LOCK_CLOCKS", .pme_desc = "Bus cycles when a LOCK signal is asserted", .pme_code = 0x63, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_AGENT, INTEL_ATOM_CORE }, .pme_numasks = 4 }, { .pme_name = "BUS_REQUEST_OUTSTANDING", .pme_desc = "Outstanding cacheable data read bus requests duration", .pme_code = 0x60, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_AGENT, INTEL_ATOM_CORE }, .pme_numasks = 4 }, { .pme_name = "BUS_TRANS_IFETCH", .pme_desc = "Instruction-fetch bus transactions", .pme_code = 0x68, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_AGENT, INTEL_ATOM_CORE }, .pme_numasks = 4 }, { .pme_name = "BUS_HIT_DRV", .pme_desc = "HIT signal asserted", .pme_code = 0x7A, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_AGENT }, .pme_numasks = 2 }, { .pme_name = "BUS_DRDY_CLOCKS", .pme_desc = "Bus cycles when data is sent on the bus", .pme_code = 0x62, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_AGENT }, .pme_numasks = 2 }, { .pme_name = "L2_DBUS_BUSY", .pme_desc = "Cycles the L2 cache data bus is busy", .pme_code = 0x22, .pme_flags = 0, .pme_umasks = { INTEL_ATOM_CORE }, .pme_numasks = 2 }, }; #define PME_INTEL_ATOM_UNHALTED_CORE_CYCLES 0 #define PME_INTEL_ATOM_INSTRUCTIONS_RETIRED 2 #define PME_INTEL_ATOM_EVENT_COUNT (sizeof(intel_atom_pe)/sizeof(pme_intel_atom_entry_t)) papi-5.5.1/src/libpfm-3.y/lib/pfmlib_pentium4_priv.h0000644000307100002310000001252713013651450022206 0ustar yarkhangraduate/* * Copyright (c) 2006 IBM Corp. * Contributed by Kevin Corry * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * pfmlib_pentium4_priv.h * * Structures and definitions for use in the Pentium4/Xeon/EM64T libpfm code. */ #ifndef _PFMLIB_PENTIUM4_PRIV_H_ #define _PFMLIB_PENTIUM4_PRIV_H_ /** * pentium4_escr_reg_t * * Describe one ESCR register. * * "pentium4_escrs" is a flat array of these structures * that defines all the ESCRs. * * @name: ESCR's name * @pmc: Perfmon's PMC number for this ESCR. * @allowed_cccrs: Array of CCCR numbers that can be used with this ESCR. A * positive value is an index into the pentium4_ccrs array. * A value of -1 indicates that slot is unused. **/ #define MAX_CCCRS_PER_ESCR 3 typedef struct { char *name; int pmc; int allowed_cccrs[MAX_CCCRS_PER_ESCR]; } pentium4_escr_reg_t; /* CCCR: Counter Configuration Control Register * * These registers are used to configure the data counters. There are 18 * CCCRs, one for each data counter. */ /** * pentium4_cccr_reg_t * * Describe one CCCR register. * * "pentium4_cccrs" is a flat array of these structures * that defines all the CCCRs. * * @name: CCCR's name * @pmc: Perfmon's PMC number for this CCCR * @pmd: Perfmon's PMD number for the associated data counter. Every CCCR has * exactly one counter. * @allowed_escrs: Array of ESCR numbers that can be used with this CCCR. A * positive value is an index into the pentium4_escrs array. * A value of -1 indicates that slot is unused. The index into * this array is the value to use in the escr_select portion * of the CCCR value. **/ #define MAX_ESCRS_PER_CCCR 8 typedef struct { char *name; int pmc; int pmd; int allowed_escrs[MAX_ESCRS_PER_CCCR]; } pentium4_cccr_reg_t; /** * pentium4_replay_regs_t * * Describe one pair of PEBS registers for use with the replay_event event. * * "p4_replay_regs" is a flat array of these structures * that defines all the PEBS pairs per Table A-10 of * the Intel System Programming Guide Vol 3B. * * @enb: value for the PEBS_ENABLE register for a given replay metric. * @mat_vert: value for the PEBS_MATRIX_VERT register for a given metric. * The replay_event event defines a series of virtual mask bits * that serve as indexes into this array. The values at that index * provide information programmed into the PEBS registers to count * specific metrics available to the replay_event event. **/ typedef struct { int enb; int mat_vert; } pentium4_replay_regs_t; /** * pentium4_pmc_t * * Provide a mapping from PMC number to the type of control register and * its index within the appropriate array. * * @name: Name * @type: PENTIUM4_PMC_TYPE_ESCR or PENTIUM4_PMC_TYPE_CCCR * @index: Index into the pentium4_escrs array or the pentium4_cccrs array. **/ typedef struct { char *name; int type; int index; } pentium4_pmc_t; #define PENTIUM4_PMC_TYPE_ESCR 1 #define PENTIUM4_PMC_TYPE_CCCR 2 /** * pentium4_event_mask_t * * Defines one bit of the event-mask for one Pentium4 event. * * @name: Event mask name * @desc: Event mask description * @bit: The bit position within the event_mask field. **/ typedef struct { char *name; char *desc; unsigned int bit; } pentium4_event_mask_t; /** * pentium4_event_t * * Describe one event that can be counted on Pentium4/EM64T. * * "pentium4_events" is a flat array of these structures that defines * all possible events. * * @name: Event name * @desc: Event description * @event_select: Value for the 'event_select' field in the ESCR (bits [31:25]). * @escr_select: Value for the 'escr_select' field in the CCCR (bits [15:13]). * @allowed_escrs: Numbers for ESCRs that can be used to count this event. A * positive value is an index into the pentium4_escrs array. * A value of -1 means that slot is not used. * @event_masks: Array of descriptions of available masks for this event. * Array elements with a NULL 'name' field are unused. **/ #define MAX_ESCRS_PER_EVENT 2 typedef struct { char *name; char *desc; unsigned int event_select; unsigned int escr_select; int allowed_escrs[MAX_ESCRS_PER_EVENT]; pentium4_event_mask_t event_masks[EVENT_MASK_BITS]; } pentium4_event_t; #endif papi-5.5.1/src/libpfm-3.y/lib/pfmlib_common.c0000644000307100002310000006063113013651450020663 0ustar yarkhangraduate/* * pfmlib_common.c: set of functions common to all PMU models * * Copyright (c) 2001-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _GNU_SOURCE #define _GNU_SOURCE /* for getline */ #endif #include #include #include #include #include #include #include #include #include "pfmlib_priv.h" static pfm_pmu_support_t *supported_pmus[]= { #ifdef CONFIG_PFMLIB_ARCH_IA64 &montecito_support, &itanium2_support, &itanium_support, &generic_ia64_support, /* must always be last for IA-64 */ #endif #ifdef CONFIG_PFMLIB_ARCH_X86_64 &amd64_support, &pentium4_support, &core_support, &intel_atom_support, &intel_nhm_support, &intel_wsm_support, &gen_ia32_support, /* must always be last for x86-64 */ #endif #ifdef CONFIG_PFMLIB_ARCH_I386 &i386_pii_support, &i386_ppro_support, &i386_p6_support, &i386_pm_support, &coreduo_support, &amd64_support, &pentium4_support, &core_support, &intel_atom_support, &intel_nhm_support, &intel_wsm_support, &gen_ia32_support, /* must always be last for i386 */ #endif #ifdef CONFIG_PFMLIB_ARCH_MIPS64 &generic_mips64_support, #endif #ifdef CONFIG_PFMLIB_ARCH_SICORTEX &sicortex_support, #endif #ifdef CONFIG_PFMLIB_ARCH_POWERPC &gen_powerpc_support, #endif #ifdef CONFIG_PFMLIB_ARCH_SPARC &sparc_support, #endif #ifdef CONFIG_PFMLIB_ARCH_CRAYX2 &crayx2_support, #endif #ifdef CONFIG_PFMLIB_CELL &cell_support, #endif NULL }; /* * contains runtime configuration options for the library. * mostly for debug purposes. */ pfm_config_t pfm_config = { .current = NULL }; int forced_pmu = PFMLIB_NO_PMU; /* * check environment variables for: * LIBPFM_VERBOSE : enable verbose output (must be 1) * LIBPFM_DEBUG : enable debug output (must be 1) */ static void pfm_check_debug_env(void) { char *str; libpfm_fp = stderr; str = getenv("LIBPFM_VERBOSE"); if (str && *str >= '0' && *str <= '9') { pfm_config.options.pfm_verbose = *str - '0'; pfm_config.options_env_set = 1; } str = getenv("LIBPFM_DEBUG"); if (str && *str >= '0' && *str <= '9') { pfm_config.options.pfm_debug = *str - '0'; pfm_config.options_env_set = 1; } str = getenv("LIBPFM_DEBUG_STDOUT"); if (str) libpfm_fp = stdout; str = getenv("LIBPFM_FORCE_PMU"); if (str) forced_pmu = atoi(str); } int pfm_initialize(void) { pfm_pmu_support_t **p = supported_pmus; int ret; pfm_check_debug_env(); /* * syscall mapping, no failure on error */ pfm_init_syscalls(); while(*p) { DPRINT("trying %s\n", (*p)->pmu_name); /* * check for forced_pmu * pmu_type can never be zero */ if ((*p)->pmu_type == forced_pmu) { __pfm_vbprintf("PMU forced to %s\n", (*p)->pmu_name); goto found; } if (forced_pmu == PFMLIB_NO_PMU && (*p)->pmu_detect() == PFMLIB_SUCCESS) goto found; p++; } return PFMLIB_ERR_NOTSUPP; found: DPRINT("found %s\n", (*p)->pmu_name); /* * run a few sanity checks */ if ((*p)->pmc_count >= PFMLIB_MAX_PMCS) return PFMLIB_ERR_NOTSUPP; if ((*p)->pmd_count >= PFMLIB_MAX_PMDS) return PFMLIB_ERR_NOTSUPP; if ((*p)->pmu_init) { ret = (*p)->pmu_init(); if (ret != PFMLIB_SUCCESS) return ret; } pfm_current = *p; return PFMLIB_SUCCESS; } int pfm_set_options(pfmlib_options_t *opt) { if (opt == NULL) return PFMLIB_ERR_INVAL; /* * environment variables override program presets */ if (pfm_config.options_env_set == 0) pfm_config.options = *opt; return PFMLIB_SUCCESS; } /* * return the name corresponding to the pmu type. Only names * of PMU actually compiled in the library will be returned. */ int pfm_get_pmu_name_bytype(int type, char *name, size_t maxlen) { pfm_pmu_support_t **p = supported_pmus; if (name == NULL || maxlen < 1) return PFMLIB_ERR_INVAL; while (*p) { if ((*p)->pmu_type == type) goto found; p++; } return PFMLIB_ERR_INVAL; found: strncpy(name, (*p)->pmu_name, maxlen-1); /* make sure the string is null terminated */ name[maxlen-1] = '\0'; return PFMLIB_SUCCESS; } int pfm_list_supported_pmus(int (*pf)(const char *fmt,...)) { pfm_pmu_support_t **p; if (pf == NULL) return PFMLIB_ERR_INVAL; (*pf)("supported PMU models: "); for (p = supported_pmus; *p; p++) { (*pf)("[%s] ", (*p)->pmu_name);; } (*pf)("\ndetected host PMU: %s\n", pfm_current ? pfm_current->pmu_name : "not detected yet"); return PFMLIB_SUCCESS; } int pfm_get_pmu_name(char *name, int maxlen) { if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; if (name == NULL || maxlen < 1) return PFMLIB_ERR_INVAL; strncpy(name, pfm_current->pmu_name, maxlen-1); name[maxlen-1] = '\0'; return PFMLIB_SUCCESS; } int pfm_get_pmu_type(int *type) { if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; if (type == NULL) return PFMLIB_ERR_INVAL; *type = pfm_current->pmu_type; return PFMLIB_SUCCESS; } /* * boolean return value */ int pfm_is_pmu_supported(int type) { pfm_pmu_support_t **p = supported_pmus; if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; while (*p) { if ((*p)->pmu_type == type) return PFMLIB_SUCCESS; p++; } return PFMLIB_ERR_NOTSUPP; } int pfm_force_pmu(int type) { pfm_pmu_support_t **p = supported_pmus; while (*p) { if ((*p)->pmu_type == type) goto found; p++; } return PFMLIB_ERR_NOTSUPP; found: pfm_current = *p; return PFMLIB_SUCCESS; } int pfm_find_event_byname(const char *n, unsigned int *idx) { char *p, *e; unsigned int i; size_t len; if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; if (n == NULL || idx == NULL) return PFMLIB_ERR_INVAL; /* * this function ignores any ':' separator */ p = strchr(n, ':'); if (!p) len = strlen(n); else len = p - n; /* * we do case insensitive comparisons * * event names must match completely */ for(i=0; i < pfm_current->pme_count; i++) { e = pfm_current->get_event_name(i); if (!e) continue; if (!strncasecmp(e, n, len) && len == strlen(e)) goto found; } return PFMLIB_ERR_NOTFOUND; found: *idx = i; return PFMLIB_SUCCESS; } int pfm_find_event_bycode(int code, unsigned int *idx) { pfmlib_regmask_t impl_cnt; unsigned int i, j, num_cnt; int code2; if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; if (idx == NULL) return PFMLIB_ERR_INVAL; if (pfm_current->flags & PFMLIB_MULT_CODE_EVENT) { pfm_current->get_impl_counters(&impl_cnt); num_cnt = pfm_current->num_cnt; for(i=0; i < pfm_current->pme_count; i++) { for(j=0; num_cnt; j++) { if (pfm_regmask_isset(&impl_cnt, j)) { pfm_current->get_event_code(i, j, &code2); if (code2 == code) goto found; num_cnt--; } } } } else { for(i=0; i < pfm_current->pme_count; i++) { pfm_current->get_event_code(i, PFMLIB_CNT_FIRST, &code2); if (code2 == code) goto found; } } return PFMLIB_ERR_NOTFOUND; found: *idx = i; return PFMLIB_SUCCESS; } int pfm_find_event(const char *v, unsigned int *ev) { unsigned long number; char *endptr = NULL; int ret = PFMLIB_ERR_INVAL; if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; if (v == NULL || ev == NULL) return PFMLIB_ERR_INVAL; if (isdigit((int)*v)) { number = strtoul(v,&endptr, 0); /* check for errors */ if (*endptr!='\0') return PFMLIB_ERR_INVAL; if (number <= INT_MAX) { int the_int_number = (int)number; ret = pfm_find_event_bycode(the_int_number, ev); } } else ret = pfm_find_event_byname(v, ev); return ret; } int pfm_find_event_bycode_next(int code, unsigned int i, unsigned int *next) { int code2; if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; if (!next) return PFMLIB_ERR_INVAL; for(++i; i < pfm_current->pme_count; i++) { pfm_current->get_event_code(i, PFMLIB_CNT_FIRST, &code2); if (code2 == code) goto found; } return PFMLIB_ERR_NOTFOUND; found: *next = i; return PFMLIB_SUCCESS; } static int pfm_do_find_event_mask(unsigned int ev, const char *str, unsigned int *mask_idx) { unsigned int i, c, num_masks = 0; unsigned long mask_val = -1; char *endptr = NULL; char *mask_name; /* empty mask name */ if (*str == '\0') return PFMLIB_ERR_UMASK; num_masks = pfm_num_masks(ev); for (i = 0; i < num_masks; i++) { mask_name = pfm_current->get_event_mask_name(ev, i); if (!mask_name) continue; if (strcasecmp(mask_name, str)) continue; *mask_idx = i; return PFMLIB_SUCCESS; } /* don't give up yet; check for a exact numerical value */ mask_val = strtoul(str, &endptr, 0); if (mask_val != ULONG_MAX && endptr && *endptr == '\0') { for (i = 0; i < num_masks; i++) { pfm_current->get_event_mask_code(ev, i, &c); if (mask_val == c) { *mask_idx = i; return PFMLIB_SUCCESS; } } } return PFMLIB_ERR_UMASK; } int pfm_find_event_mask(unsigned int ev, const char *str, unsigned int *mask_idx) { if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; if (str == NULL || mask_idx == NULL || ev >= pfm_current->pme_count) return PFMLIB_ERR_INVAL; return pfm_do_find_event_mask(ev, str, mask_idx); } /* * check if unit mask is not already present */ static inline int pfm_check_duplicates(pfmlib_event_t *e, unsigned int u) { unsigned int j; for(j=0; j < e->num_masks; j++) { if (e->unit_masks[j] == u) return PFMLIB_ERR_UMASK; } return PFMLIB_SUCCESS; } static int pfm_add_numeric_masks(pfmlib_event_t *e, const char *str) { unsigned int i, j, c; unsigned int num_masks = 0; unsigned long mask_val = -1, m = 0; char *endptr = NULL; int ret = PFMLIB_ERR_UMASK; /* empty mask name */ if (*str == '\0') return PFMLIB_ERR_UMASK; num_masks = pfm_num_masks(e->event); /* * add to the existing list of unit masks */ j = e->num_masks; /* * use unsigned long to benefit from radix wildcard * and error checking of strtoul() */ mask_val = strtoul(str, &endptr, 0); if (endptr && *endptr != '\0') return PFMLIB_ERR_UMASK; /* * look for a numerical match */ for (i = 0; i < num_masks; i++) { pfm_current->get_event_mask_code(e->event, i, &c); if ((mask_val & c) == (unsigned long)c) { /* ignore duplicates */ if (pfm_check_duplicates(e, i) == PFMLIB_SUCCESS) { if (j == PFMLIB_MAX_MASKS_PER_EVENT) { ret = PFMLIB_ERR_TOOMANY; break; } e->unit_masks[j++] = i; } m |= c; } } /* * all bits accounted for */ if (mask_val == m) { e->num_masks = j; return PFMLIB_SUCCESS; } /* * extra bits left over; * reset and flag error */ for (i = e->num_masks; i < j; i++) e->unit_masks[i] = 0; return ret; } int pfm_get_event_name(unsigned int i, char *name, size_t maxlen) { size_t l, j; char *str; if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; if (i >= pfm_current->pme_count || name == NULL || maxlen < 1) return PFMLIB_ERR_INVAL; str = pfm_current->get_event_name(i); if (!str) return PFMLIB_ERR_BADHOST; l = strlen(str); /* * we fail if buffer is too small, simply because otherwise we * get partial names which are useless for subsequent calls * users mus invoke pfm_get_event_name_max_len() to correctly size * the buffer for this call */ if ((maxlen-1) < l) return PFMLIB_ERR_INVAL; for(j=0; j < l; j++) name[j] = (char)toupper(str[j]); name[l] = '\0'; return PFMLIB_SUCCESS; } int pfm_get_event_code(unsigned int i, int *code) { if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; if (i >= pfm_current->pme_count || code == NULL) return PFMLIB_ERR_INVAL; return pfm_current->get_event_code(i, PFMLIB_CNT_FIRST, code); } int pfm_get_event_code_counter(unsigned int i, unsigned int cnt, int *code) { if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; if (i >= pfm_current->pme_count || code == NULL) return PFMLIB_ERR_INVAL; return pfm_current->get_event_code(i, cnt, code); } int pfm_get_event_counters(unsigned int i, pfmlib_regmask_t *counters) { if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; if (i >= pfm_current->pme_count) return PFMLIB_ERR_INVAL; pfm_current->get_event_counters(i, counters); return PFMLIB_SUCCESS; } int pfm_get_event_mask_name(unsigned int ev, unsigned int mask, char *name, size_t maxlen) { char *str; unsigned int num; size_t l, j; if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; if (ev >= pfm_current->pme_count || name == NULL || maxlen < 1) return PFMLIB_ERR_INVAL; num = pfm_num_masks(ev); if (num == 0) return PFMLIB_ERR_NOTSUPP; if (mask >= num) return PFMLIB_ERR_INVAL; str = pfm_current->get_event_mask_name(ev, mask); if (!str) return PFMLIB_ERR_BADHOST; l = strlen(str); if (l >= (maxlen-1)) return PFMLIB_ERR_FULL; strcpy(name, str); /* * present nice uniform names */ l = strlen(name); for(j=0; j < l; j++) if (islower(name[j])) name[j] = (char)toupper(name[j]); return PFMLIB_SUCCESS; } int pfm_get_num_events(unsigned int *count) { if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; if (count == NULL) return PFMLIB_ERR_INVAL; *count = pfm_current->pme_count; return PFMLIB_SUCCESS; } int pfm_get_num_event_masks(unsigned int ev, unsigned int *count) { if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; if (ev >= pfm_current->pme_count || count == NULL) return PFMLIB_ERR_INVAL; *count = pfm_num_masks(ev); return PFMLIB_SUCCESS; } #if 0 /* * check that the unavailable PMCs registers correspond * to implemented PMC registers */ static int pfm_check_unavail_pmcs(pfmlib_regmask_t *pmcs) { pfmlib_regmask_t impl_pmcs; pfm_current->get_impl_pmcs(&impl_pmcs); unsigned int i; for (i=0; i < PFMLIB_REG_BV; i++) { if ((pmcs->bits[i] & impl_pmcs.bits[i]) != pmcs->bits[i]) return PFMLIB_ERR_INVAL; } return PFMLIB_SUCCESS; } #endif /* * we do not check if pfp_unavail_pmcs contains only implemented PMC * registers. In other words, invalid registers are ignored */ int pfm_dispatch_events( pfmlib_input_param_t *inp, void *model_in, pfmlib_output_param_t *outp, void *model_out) { unsigned count; unsigned int i; int ret; if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; /* at least one input and one output set must exist */ if (!inp && !model_in) return PFMLIB_ERR_INVAL; if (!outp && !model_out) return PFMLIB_ERR_INVAL; if (!inp) count = 0; else if (inp->pfp_dfl_plm == 0) /* the default priv level must be set to something */ return PFMLIB_ERR_INVAL; else if (inp->pfp_event_count >= PFMLIB_MAX_PMCS) return PFMLIB_ERR_INVAL; else if (inp->pfp_event_count > pfm_current->num_cnt) return PFMLIB_ERR_NOASSIGN; else count = inp->pfp_event_count; /* * check that event and unit masks descriptors are correct */ for (i=0; i < count; i++) { ret = __pfm_check_event(inp->pfp_events+i); if (ret != PFMLIB_SUCCESS) return ret; } /* reset output data structure */ if (outp) memset(outp, 0, sizeof(*outp)); return pfm_current->dispatch_events(inp, model_in, outp, model_out); } /* * more or less obosleted by pfm_get_impl_counters() */ int pfm_get_num_counters(unsigned int *num) { if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; if (num == NULL) return PFMLIB_ERR_INVAL; *num = pfm_current->num_cnt; return PFMLIB_SUCCESS; } int pfm_get_num_pmcs(unsigned int *num) { if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; if (num == NULL) return PFMLIB_ERR_INVAL; *num = pfm_current->pmc_count; return PFMLIB_SUCCESS; } int pfm_get_num_pmds(unsigned int *num) { if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; if (num == NULL) return PFMLIB_ERR_INVAL; *num = pfm_current->pmd_count; return PFMLIB_SUCCESS; } int pfm_get_impl_pmcs(pfmlib_regmask_t *impl_pmcs) { if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; if (impl_pmcs == NULL) return PFMLIB_ERR_INVAL; memset(impl_pmcs , 0, sizeof(*impl_pmcs)); pfm_current->get_impl_pmcs(impl_pmcs); return PFMLIB_SUCCESS; } int pfm_get_impl_pmds(pfmlib_regmask_t *impl_pmds) { if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; if (impl_pmds == NULL) return PFMLIB_ERR_INVAL; memset(impl_pmds, 0, sizeof(*impl_pmds)); pfm_current->get_impl_pmds(impl_pmds); return PFMLIB_SUCCESS; } int pfm_get_impl_counters(pfmlib_regmask_t *impl_counters) { if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; if (impl_counters == NULL) return PFMLIB_ERR_INVAL; memset(impl_counters, 0, sizeof(*impl_counters)); pfm_current->get_impl_counters(impl_counters); return PFMLIB_SUCCESS; } int pfm_get_hw_counter_width(unsigned int *width) { if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; if (width == NULL) return PFMLIB_ERR_INVAL; pfm_current->get_hw_counter_width(width); return PFMLIB_SUCCESS; } /* sorry, only English supported at this point! */ static char *pfmlib_err_list[]= { "success", "not supported", "invalid parameters", "pfmlib not initialized", "event not found", "cannot assign events to counters", "buffer is full or too small", "event used more than once", "invalid model specific magic number", "invalid combination of model specific features", "incompatible event sets", "incompatible events combination", "too many events or unit masks", "code range too big", "empty code range", "invalid code range", "too many code ranges", "invalid data range", "too many data ranges", "not supported by host cpu", "code range is not bundle-aligned", "code range requires some flags in rr_flags", "invalid or missing unit mask", "out of memory" }; static size_t pfmlib_err_count = sizeof(pfmlib_err_list)/sizeof(char *); char * pfm_strerror(int code) { code = -code; if (code <0 || code >= pfmlib_err_count) return "unknown error code"; return pfmlib_err_list[code]; } int pfm_get_version(unsigned int *version) { if (version == NULL) return PFMLIB_ERR_INVAL; *version = PFMLIB_VERSION; return 0; } int pfm_get_max_event_name_len(size_t *len) { unsigned int i, j, num_masks; size_t max = 0, l; char *str; if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; if (len == NULL) return PFMLIB_ERR_INVAL; for(i=0; i < pfm_current->pme_count; i++) { str = pfm_current->get_event_name(i); if (!str) continue; l = strlen(str); if (l > max) max = l; num_masks = pfm_num_masks(i); /* * we need to add up all length because unit masks can * be combined typically. We add 1 to account for ':' * which is inserted as the unit mask separator */ for (j = 0; j < num_masks; j++) { str = pfm_current->get_event_mask_name(i, j); if (!str) continue; l += 1 + strlen(str); } if (l > max) max = l; } *len = max; return PFMLIB_SUCCESS; } /* * return the index of the event that counts elapsed cycles */ int pfm_get_cycle_event(pfmlib_event_t *e) { if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; if (e == NULL) return PFMLIB_ERR_INVAL; if (!pfm_current->get_cycle_event) return PFMLIB_ERR_NOTSUPP; memset(e, 0, sizeof(*e)); return pfm_current->get_cycle_event(e); } /* * return the index of the event that retired instructions */ int pfm_get_inst_retired_event(pfmlib_event_t *e) { if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; if (e == NULL) return PFMLIB_ERR_INVAL; if (!pfm_current->get_inst_retired_event) return PFMLIB_ERR_NOTSUPP; memset(e, 0, sizeof(*e)); return pfm_current->get_inst_retired_event(e); } int pfm_get_event_description(unsigned int i, char **str) { if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; if (i >= pfm_current->pme_count || str == NULL) return PFMLIB_ERR_INVAL; if (pfm_current->get_event_desc == NULL) { *str = strdup("no description available"); return PFMLIB_SUCCESS; } return pfm_current->get_event_desc(i, str); } int pfm_get_event_mask_description(unsigned int event_idx, unsigned int mask_idx, char **desc) { if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; if (event_idx >= pfm_current->pme_count || desc == NULL) return PFMLIB_ERR_INVAL; if (pfm_current->get_event_mask_desc == NULL) { *desc = strdup("no description available"); return PFMLIB_SUCCESS; } if (mask_idx >= pfm_current->get_num_event_masks(event_idx)) return PFMLIB_ERR_INVAL; return pfm_current->get_event_mask_desc(event_idx, mask_idx, desc); } int pfm_get_event_mask_code(unsigned int event_idx, unsigned int mask_idx, unsigned int *code) { if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; if (event_idx >= pfm_current->pme_count || code == NULL) return PFMLIB_ERR_INVAL; if (pfm_current->get_event_mask_code == NULL) { *code = 0; return PFMLIB_SUCCESS; } if (mask_idx >= pfm_current->get_num_event_masks(event_idx)) return PFMLIB_ERR_INVAL; return pfm_current->get_event_mask_code(event_idx, mask_idx, code); } int pfm_get_full_event_name(pfmlib_event_t *e, char *name, size_t maxlen) { char *str; size_t l, j; int ret; if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; if (e == NULL || name == NULL || maxlen < 1) return PFMLIB_ERR_INVAL; ret = __pfm_check_event(e); if (ret != PFMLIB_SUCCESS) return ret; /* * make sure the string is at least empty * important for programs that do not check return value * from this function! */ *name = '\0'; str = pfm_current->get_event_name(e->event); if (!str) return PFMLIB_ERR_BADHOST; l = strlen(str); if (l > (maxlen-1)) return PFMLIB_ERR_FULL; strcpy(name, str); maxlen -= l + 1; for(j=0; j < e->num_masks; j++) { str = pfm_current->get_event_mask_name(e->event, e->unit_masks[j]); if (!str) continue; l = strlen(str); if (l > (maxlen-1)) return PFMLIB_ERR_FULL; strcat(name, ":"); strcat(name, str); maxlen -= l + 1; } /* * present nice uniform names */ l = strlen(name); for(j=0; j < l; j++) if (islower(name[j])) name[j] = (char)toupper(name[j]); return PFMLIB_SUCCESS; } int pfm_find_full_event(const char *v, pfmlib_event_t *e) { char *str, *p, *q; unsigned int j, mask; int ret = PFMLIB_SUCCESS; if (PFMLIB_INITIALIZED() == 0) return PFMLIB_ERR_NOINIT; if (v == NULL || e == NULL) return PFMLIB_ERR_INVAL; memset(e, 0, sizeof(*e)); /* * must copy string because we modify it when parsing */ str = strdup(v); if (!str) return PFMLIB_ERR_NOMEM; /* * find event. this function ignores ':' separator */ ret = pfm_find_event_byname(str, &e->event); if (ret) goto error; /* * get number of unit masks for event */ j = pfm_num_masks(e->event); /* * look for colon (unit mask separator) */ p = strchr(str, ':'); /* If no unit masks available and none specified, we're done */ if ((j == 0) && (p == NULL)) { free(str); return PFMLIB_SUCCESS; } ret = PFMLIB_ERR_UMASK; /* * error if: * - event has no unit mask and at least one is passed */ if (p && !j) goto error; /* * error if: * - event has unit masks, no default unit mask, and none is passed */ if (j && !p) { if (pfm_current->has_umask_default && pfm_current->has_umask_default(e->event)) { free(str); return PFMLIB_SUCCESS; } goto error; } /* skip : */ p++; /* * separator is passed but there is nothing behind it */ if (!*p) goto error; /* parse unit masks */ for( q = p; q ; p = q) { q = strchr(p,':'); if (q) *q++ = '\0'; /* * text or exact unit mask value match */ ret = pfm_do_find_event_mask(e->event, p, &mask); if (ret == PFMLIB_ERR_UMASK) { ret = pfm_add_numeric_masks(e, p); if (ret != PFMLIB_SUCCESS) break; } else if (ret == PFMLIB_SUCCESS) { /* * ignore duplicates */ ret = pfm_check_duplicates(e, mask); if (ret != PFMLIB_SUCCESS) { ret = PFMLIB_SUCCESS; continue; } if (e->num_masks == PFMLIB_MAX_MASKS_PER_EVENT) { ret = PFMLIB_ERR_TOOMANY; break; } e->unit_masks[e->num_masks] = mask; e->num_masks++; } } error: free(str); return ret; } papi-5.5.1/src/libpfm-3.y/lib/pfmlib_os_linux_v3.c0000644000307100002310000000706413013651450021644 0ustar yarkhangraduate/* * pfmlib_os_linux_v3.c: Perfmon3 API syscalls * * Copyright (c) 2008 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _GNU_SOURCE #define _GNU_SOURCE /* for getline */ #endif #include #include #include #include #include #include #include #include #include #include "pfmlib_priv.h" /* * v3.x interface */ #define PFM_pfm_create (_pfmlib_get_sys_base()+0) #define PFM_pfm_write (_pfmlib_get_sys_base()+1) #define PFM_pfm_read (_pfmlib_get_sys_base()+2) #define PFM_pfm_attach (_pfmlib_get_sys_base()+3) #define PFM_pfm_set_state (_pfmlib_get_sys_base()+4) #define PFM_pfm_create_sets (_pfmlib_get_sys_base()+5) #define PFM_pfm_getinfo_sets (_pfmlib_get_sys_base()+6) /* * perfmon v3 interface */ int //pfm_create(int flags, pfarg_sinfo_t *sif, char *name, void *smpl_arg, size_t smpl_size) pfm_create(int flags, pfarg_sinfo_t *sif, ...) { va_list ap; char *name = NULL; void *smpl_arg = NULL; size_t smpl_size = 0; int ret; if (_pfmlib_major_version < 3) { errno = ENOSYS; return -1; } if (flags & PFM_FL_SMPL_FMT) va_start(ap, sif); if (flags & PFM_FL_SMPL_FMT) { name = va_arg(ap, char *); smpl_arg = va_arg(ap, void *); smpl_size = va_arg(ap, size_t); } ret = (int)syscall(PFM_pfm_create, flags, sif, name, smpl_arg, smpl_size); if (flags & PFM_FL_SMPL_FMT) va_end(ap); return ret; } int pfm_write(int fd, int flags, int type, void *pms, size_t sz) { if (_pfmlib_major_version < 3) return -ENOSYS; return (int)syscall(PFM_pfm_write, fd, flags, type, pms, sz); } int pfm_read(int fd, int flags, int type, void *pms, size_t sz) { if (_pfmlib_major_version < 3) return -ENOSYS; return (int)syscall(PFM_pfm_read, fd, flags, type, pms, sz); } int pfm_create_sets(int fd, int flags, pfarg_set_desc_t *setd, size_t sz) { if (_pfmlib_major_version < 3) return -ENOSYS; return (int)syscall(PFM_pfm_create_sets, fd, flags, setd, sz); } int pfm_getinfo_sets(int fd, int flags, pfarg_set_info_t *info, size_t sz) { if (_pfmlib_major_version < 3) return -ENOSYS; return (int)syscall(PFM_pfm_getinfo_sets, fd, flags, info, sz); } int pfm_attach(int fd, int flags, int target) { if (_pfmlib_major_version < 3) return -ENOSYS; return (int)syscall(PFM_pfm_attach, fd, flags, target); } int pfm_set_state(int fd, int flags, int state) { if (_pfmlib_major_version < 3) return -ENOSYS; return (int)syscall(PFM_pfm_set_state, fd, flags, state); } papi-5.5.1/src/libpfm-3.y/lib/pfmlib_coreduo_priv.h0000644000307100002310000000444413013651450022100 0ustar yarkhangraduate/* * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Based on: * Copyright (c) 2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef __PFMLIB_COREDUO_PRIV_H__ #define __PFMLIB_COREDUO_PRIV_H__ #define PFMLIB_COREDUO_MAX_UMASK 16 typedef struct { char *pme_uname; /* unit mask name */ char *pme_udesc; /* event/umask description */ unsigned int pme_ucode; /* unit mask code */ unsigned int pme_flags; /* unit mask flags */ } pme_coreduo_umask_t; typedef struct { char *pme_name; /* event name */ char *pme_desc; /* event description */ unsigned int pme_code; /* event code */ unsigned int pme_numasks; /* number of umasks */ unsigned int pme_flags; /* flags */ pme_coreduo_umask_t pme_umasks[PFMLIB_COREDUO_MAX_UMASK]; /* umask desc */ } pme_coreduo_entry_t; /* * pme_flags value (event and unit mask) */ /* event-level constraints */ #define PFMLIB_COREDUO_CSPEC 0x02 /* requires a core specification */ #define PFMLIB_COREDUO_PMC0 0x04 /* works only on IA32_PMC0 */ #define PFMLIB_COREDUO_PMC1 0x08 /* works only on IA32_PMC1 */ #define PFMLIB_COREDUO_MESI 0x10 /* requires MESI */ #endif /* __PFMLIB_COREDUO_PRIV_H__ */ papi-5.5.1/src/libpfm-3.y/lib/ultra3plus_events.h0000644000307100002310000003206313013651450021547 0ustar yarkhangraduatestatic pme_sparc_entry_t ultra3plus_pe[] = { /* These two must always be first. */ { .pme_name = "Cycle_cnt", .pme_desc = "Accumulated cycles", .pme_ctrl = PME_CTRL_S0 | PME_CTRL_S1, .pme_val = 0x0, }, { .pme_name = "Instr_cnt", .pme_desc = "Number of instructions completed", .pme_ctrl = PME_CTRL_S0 | PME_CTRL_S1, .pme_val = 0x1, }, /* PIC0 events common to all UltraSPARC processors */ { .pme_name = "Dispatch0_IC_miss", .pme_desc = "I-buffer is empty from I-Cache miss", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x2, }, { .pme_name = "IC_ref", .pme_desc = "I-cache refrences", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x8, }, { .pme_name = "DC_rd", .pme_desc = "D-cache read references (including accesses that subsequently trap)", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x9, }, { .pme_name = "DC_wr", .pme_desc = "D-cache store accesses (including cacheable stores that subsequently trap)", .pme_ctrl = PME_CTRL_S0, .pme_val = 0xa, }, { .pme_name = "EC_ref", .pme_desc = "E-cache references", .pme_ctrl = PME_CTRL_S0, .pme_val = 0xc, }, { .pme_name = "EC_snoop_inv", .pme_desc = "L2-cache invalidates generated from a snoop by a remote processor", .pme_ctrl = PME_CTRL_S0, .pme_val = 0xe, }, /* PIC1 events common to all UltraSPARC processors */ { .pme_name = "Dispatch0_mispred", .pme_desc = "I-buffer is empty from Branch misprediction", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x2, }, { .pme_name = "EC_wb", .pme_desc = "Dirty sub-blocks that produce writebacks due to L2-cache miss events", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xd, }, { .pme_name = "EC_snoop_cb", .pme_desc = "L2-cache copybacks generated from a snoop by a remote processor", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xe, }, /* PIC0 events common to all UltraSPARC-III/III+/IIIi processors */ { .pme_name = "Dispatch0_br_target", .pme_desc = "I-buffer is empty due to a branch target address calculation", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x3, }, { .pme_name = "Dispatch0_2nd_br", .pme_desc = "Stall cycles due to having two branch instructions line-up in one 4-instruction group causing the second branch in the group to be re-fetched, delaying it's entrance into the I-buffer", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x4, }, { .pme_name = "Rstall_storeQ", .pme_desc = "R-stage stall for a store instruction which is the next instruction to be executed, but it stailled due to the store queue being full", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x5, }, { .pme_name = "Rstall_IU_use", .pme_desc = "R-stage stall for an event that the next instruction to be executed depends on the result of a preceeding integer instruction in the pipeline that is not yet available", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x6, }, { .pme_name = "EC_write_hit_RTO", .pme_desc = "W-cache exclusive requests that hit L2-cache in S, O, or Os state and thus, do a read-to-own bus transaction", .pme_ctrl = PME_CTRL_S0, .pme_val = 0xd, }, { .pme_name = "EC_rd_miss", .pme_desc = "L2-cache miss events (including atomics) from D-cache events", .pme_ctrl = PME_CTRL_S0, .pme_val = 0xf, }, { .pme_name = "PC_port0_rd", .pme_desc = "P-cache cacheable FP loads to the first port (general purpose load path to D-cache and P-cache via MS pipeline)", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x10, }, { .pme_name = "SI_snoop", .pme_desc = "Counts snoops from remote processor(s) including RTS, RTSR, RTO, RTOR, RS, RSR, RTSM, and WS", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x11, }, { .pme_name = "SI_ciq_flow", .pme_desc = "Counts system clock cycles when the flow control (PauseOut) signal is asserted", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x12, }, { .pme_name = "SI_owned", .pme_desc = "Counts events where owned_in is asserted on bus requests from the local processor", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x13, }, { .pme_name = "SW_count0", .pme_desc = "Counts software-generated occurrences of 'sethi %hi(0xfc000), %g0' instruction", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x14, }, { .pme_name = "IU_Stat_Br_miss_taken", .pme_desc = "Retired branches that were predicted to be taken, but in fact were not taken", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x15, }, { .pme_name = "IU_Stat_Br_Count_taken", .pme_desc = "Retired taken branches", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x16, }, { .pme_name = "Dispatch0_rs_mispred", .pme_desc = "I-buffer is empty due to a Return Address Stack misprediction", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x4, }, { .pme_name = "FA_pipe_completion", .pme_desc = "Instructions that complete execution on the FPG ALU pipelines", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x18, }, /* PIC1 events common to all UltraSPARC-III/III+/IIIi processors */ { .pme_name = "IC_miss_cancelled", .pme_desc = "I-cache misses cancelled due to mis-speculation, recycle, or other events", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x3, }, { .pme_name = "Re_FPU_bypass", .pme_desc = "Stall due to recirculation when an FPU bypass condition that does not have a direct bypass path occurs", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x5, }, { .pme_name = "Re_DC_miss", .pme_desc = "Stall due to loads that miss D-cache and get recirculated", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x6, }, { .pme_name = "Re_EC_miss", .pme_desc = "Stall due to loads that miss L2-cache and get recirculated", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x7, }, { .pme_name = "IC_miss", .pme_desc = "I-cache misses, including fetches from mis-speculated execution paths which are later cancelled", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x8, }, { .pme_name = "DC_rd_miss", .pme_desc = "Recirculated loads that miss the D-cache", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x9, }, { .pme_name = "DC_wr_miss", .pme_desc = "D-cache store accesses that miss D-cache", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xa, }, { .pme_name = "Rstall_FP_use", .pme_desc = "R-stage stall for an event that the next instruction to be executed depends on the result of a preceeding floating-point instruction in the pipeline that is not yet available", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xb, }, { .pme_name = "EC_misses", .pme_desc = "E-cache misses", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xc, }, { .pme_name = "EC_ic_miss", .pme_desc = "L2-cache read misses from I-cache requests", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xf, }, { .pme_name = "Re_PC_miss", .pme_desc = "Stall due to recirculation when a prefetch cache miss occurs on a prefetch predicted second load", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x10, }, { .pme_name = "ITLB_miss", .pme_desc = "I-TLB miss traps taken", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x11, }, { .pme_name = "DTLB_miss", .pme_desc = "Memory reference instructions which trap due to D-TLB miss", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x12, }, { .pme_name = "WC_miss", .pme_desc = "W-cache misses", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x13, }, { .pme_name = "WC_snoop_cb", .pme_desc = "W-cache copybacks generated by a snoop from a remote processor", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x14, }, { .pme_name = "WC_scrubbed", .pme_desc = "W-cache hits to clean lines", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x15, }, { .pme_name = "WC_wb_wo_read", .pme_desc = "W-cache writebacks not requiring a read", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x16, }, { .pme_name = "PC_soft_hit", .pme_desc = "FP loads that hit a P-cache line that was prefetched by a software-prefetch instruction", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x18, }, { .pme_name = "PC_snoop_inv", .pme_desc = "P-cache invalidates that were generated by a snoop from a remote processor and stores by a local processor", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x19, }, { .pme_name = "PC_hard_hit", .pme_desc = "FP loads that hit a P-cache line that was prefetched by a hardware prefetch", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x1a, }, { .pme_name = "PC_port1_rd", .pme_desc = "P-cache cacheable FP loads to the second port (memory and out-of-pipeline instruction execution loads via the A0 and A1 pipelines)", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x1b, }, { .pme_name = "SW_count1", .pme_desc = "Counts software-generated occurrences of 'sethi %hi(0xfc000), %g0' instruction", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x1c, }, { .pme_name = "IU_Stat_Br_miss_untaken", .pme_desc = "Retired branches that were predicted to be untaken, but in fact were taken", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x1d, }, { .pme_name = "IU_Stat_Br_Count_untaken", .pme_desc = "Retired untaken branches", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x1e, }, { .pme_name = "PC_MS_miss", .pme_desc = "FP loads through the MS pipeline that miss P-cache", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x1f, }, { .pme_name = "Re_RAW_miss", .pme_desc = "Stall due to recirculation when there is a load in the E-stage which has a non-bypassable read-after-write hazard with an earlier store instruction", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x26, }, { .pme_name = "FM_pipe_completion", .pme_desc = "Instructions that complete execution on the FPG Multiply pipelines", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x27, }, /* PIC0 memory controller events common to UltraSPARC-III/III+ processors */ { .pme_name = "MC_reads_0", .pme_desc = "Read requests completed to memory bank 0", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x20, }, { .pme_name = "MC_reads_1", .pme_desc = "Read requests completed to memory bank 1", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x21, }, { .pme_name = "MC_reads_2", .pme_desc = "Read requests completed to memory bank 2", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x22, }, { .pme_name = "MC_reads_3", .pme_desc = "Read requests completed to memory bank 3", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x23, }, { .pme_name = "MC_stalls_0", .pme_desc = "Clock cycles that requests were stalled in the MCU queues because bank 0 was busy with a previous request", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x24, }, { .pme_name = "MC_stalls_2", .pme_desc = "Clock cycles that requests were stalled in the MCU queues because bank 2 was busy with a previous request", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x25, }, /* PIC1 memory controller events common to all UltraSPARC-III/III+ processors */ { .pme_name = "MC_writes_0", .pme_desc = "Write requests completed to memory bank 0", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x20, }, { .pme_name = "MC_writes_1", .pme_desc = "Write requests completed to memory bank 1", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x21, }, { .pme_name = "MC_writes_2", .pme_desc = "Write requests completed to memory bank 2", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x22, }, { .pme_name = "MC_writes_3", .pme_desc = "Write requests completed to memory bank 3", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x23, }, { .pme_name = "MC_stalls_1", .pme_desc = "Clock cycles that requests were stalled in the MCU queues because bank 1 was busy with a previous request", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x24, }, { .pme_name = "MC_stalls_3", .pme_desc = "Clock cycles that requests were stalled in the MCU queues because bank 3 was busy with a previous request", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x25, }, /* PIC0 events specific to UltraSPARC-III+ processors */ { .pme_name = "EC_wb_remote", .pme_desc = "Counts the retry event when any victimization for which the processor generates an R_WB transaction to non_LPA address region", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x19, }, { .pme_name = "EC_miss_local", .pme_desc = "Counts any transaction to an LPA for which the processor issues an RTS/RTO/RS transaction", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x1a, }, { .pme_name = "EC_miss_mtag_remote", .pme_desc = "Counts any transaction to an LPA in which the processor is required to generate a retry transaction", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x1b, }, /* PIC1 events specific to UltraSPARC-III+/IIIi processors */ { .pme_name = "Re_DC_missovhd", .pme_desc = "Used to measure D-cache stall counts seperatedly for L2-cache hits and misses. This counter is used with the recirculation and cache access events to seperately calculate the D-cache loads that hit and miss the L2-cache", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x4, }, /* PIC1 events specific to UltraSPARC-III+ processors */ { .pme_name = "EC_miss_mtag_remote", .pme_desc = "Counts any transaction to an LPA in which the processor is required to generate a retry transaction", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x28, }, { .pme_name = "EC_miss_remote", .pme_desc = "Counts the events triggered whenever the processor generates a remote (R_*) transaction and the address is to a non-LPA portion (remote) of the physical address space, or an R_WS transaction due to block-store/block-store-commit to any address space (LPA or non-LPA), or an R-RTO due to store/swap request on Os state to LPA space", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x29, }, }; #define PME_ULTRA3PLUS_EVENT_COUNT (sizeof(ultra3plus_pe)/sizeof(pme_sparc_entry_t)) papi-5.5.1/src/libpfm-3.y/lib/pfmlib_ppc970_priv.h0000644000307100002310000000117313013651450021456 0ustar yarkhangraduate/****************************/ /* THIS IS OPEN SOURCE CODE */ /****************************/ #ifndef __PFMLIB_PPC970_PRIV_H__ #define __PFMLIB_PPC970_PRIV_H__ /* * File: pfmlib_ppc970_priv.h * CVS: * Author: Corey Ashford * cjashfor@us.ibm.com * Mods: * * * (C) Copyright IBM Corporation, 2007. All Rights Reserved. * Contributed by Corey Ashford * * Note: This code was automatically generated and should not be modified by * hand. * */ #define PPC970_NUM_EVENT_COUNTERS 8 #define PPC970_NUM_GROUP_VEC 1 #define PPC970_NUM_CONTROL_REGS 3 #endif papi-5.5.1/src/libpfm-3.y/lib/intel_wsm_events.h0000644000307100002310000020137413013651450021435 0ustar yarkhangraduate/* * Copyright (c) 2010 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ static pme_nhm_entry_t wsm_pe[]={ /* * BEGIN architected events */ {.pme_name = "UNHALTED_CORE_CYCLES", .pme_code = 0x003c, .pme_cntmsk = 0x2000f, .pme_flags = PFMLIB_NHM_FIXED1, .pme_desc = "count core clock cycles whenever the clock signal on the specific core is running (not halted). Alias to event CPU_CLK_UNHALTED:THREAD" }, {.pme_name = "INSTRUCTION_RETIRED", .pme_code = 0x00c0, .pme_cntmsk = 0x1000f, .pme_flags = PFMLIB_NHM_FIXED0|PFMLIB_NHM_PEBS, .pme_desc = "count the number of instructions at retirement. Alias to event INST_RETIRED:ANY_P", }, {.pme_name = "INSTRUCTIONS_RETIRED", .pme_code = 0x00c0, .pme_cntmsk = 0x1000f, .pme_flags = PFMLIB_NHM_FIXED0|PFMLIB_NHM_PEBS, .pme_desc = "This is an alias for INSTRUCTION_RETIRED", }, {.pme_name = "UNHALTED_REFERENCE_CYCLES", .pme_code = 0x013c, .pme_cntmsk = 0x40000, .pme_flags = PFMLIB_NHM_FIXED2_ONLY, .pme_desc = "Unhalted reference cycles", }, {.pme_name = "LLC_REFERENCES", .pme_code = 0x4f2e, .pme_cntmsk = 0xf, .pme_desc = "count each request originating from the core to reference a cache line in the last level cache. The count may include speculation, but excludes cache line fills due to hardware prefetch. Alias to L2_RQSTS:SELF_DEMAND_MESI", }, {.pme_name = "LAST_LEVEL_CACHE_REFERENCES", .pme_code = 0x4f2e, .pme_cntmsk = 0xf, .pme_desc = "This is an alias for LLC_REFERENCES", }, {.pme_name = "LLC_MISSES", .pme_code = 0x412e, .pme_cntmsk = 0xf, .pme_desc = "count each cache miss condition for references to the last level cache. The event count may include speculation, but excludes cache line fills due to hardware prefetch. Alias to event L2_RQSTS:SELF_DEMAND_I_STATE", }, {.pme_name = "LAST_LEVEL_CACHE_MISSES", .pme_code = 0x412e, .pme_cntmsk = 0xf, .pme_desc = "This is an alias for LLC_MISSES", }, {.pme_name = "BRANCH_INSTRUCTIONS_RETIRED", .pme_code = 0x00c4, .pme_cntmsk = 0xf, .pme_desc = "count branch instructions at retirement. Specifically, this event counts the retirement of the last micro-op of a branch instruction. Alias to event BR_INST_RETIRED:ANY", }, /* * BEGIN core specific events */ { .pme_name = "UOPS_DECODED", .pme_desc = "micro-ops decoded", .pme_code = 0xD1, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ESP_FOLDING", .pme_udesc = "Stack pointer instructions decoded", .pme_ucode = 0x4, .pme_uflags = 0, }, { .pme_uname = "ESP_SYNC", .pme_udesc = "Stack pointer sync operations", .pme_ucode = 0x8, .pme_uflags = 0, }, { .pme_uname = "MS_CYCLES_ACTIVE", .pme_udesc = "cycles in which at least one uop is decoded by Microcode Sequencer", .pme_ucode = 0x2 | (1<< 16), /* counter-mask = 1 */ .pme_uflags = 0, }, { .pme_uname = "STALL_CYCLES", .pme_udesc = "Cycles no Uops are decoded", .pme_ucode = 0x1 | (1<<16) | (1<<15), /* inv=1, counter-mask=1 */ .pme_uflags = 0, }, }, .pme_numasks = 4 }, { .pme_name = "L1D_CACHE_LOCK_FB_HIT", .pme_desc = "L1D cacheable load lock speculated or retired accepted into the fill buffer", .pme_code = 0x0152, .pme_flags = 0, }, { .pme_name = "BPU_CLEARS", .pme_desc = "Branch Prediciton Unit clears", .pme_code = 0xE8, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "EARLY", .pme_udesc = "Early Branch Prediciton Unit clears", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "LATE", .pme_udesc = "Late Branch Prediction Unit clears", .pme_ucode = 0x2, .pme_uflags = 0, }, }, .pme_numasks = 2 }, { .pme_name = "UOPS_RETIRED", .pme_desc = "Cycles Uops are being retired", .pme_code = 0xC2, .pme_flags = PFMLIB_NHM_PEBS|PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "Uops retired (Precise Event)", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "MACRO_FUSED", .pme_udesc = "Macro-fused Uops retired (Precise Event)", .pme_ucode = 0x4, .pme_uflags = 0, }, { .pme_uname = "RETIRE_SLOTS", .pme_udesc = "Retirement slots used (Precise Event)", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "STALL_CYCLES", .pme_udesc = "Cycles Uops are not retiring (Precise Event)", .pme_ucode = 0x01 | (1<<16) | (1<<15), /* counter-mask=1, inv=1 */ .pme_uflags = 0, }, { .pme_uname = "TOTAL_CYCLES", .pme_udesc = "Total cycles using precise uop retired event (Precise Event)", .pme_ucode = 0x01 | (1<< 16), /* counter mask = 1 */ .pme_uflags = PFMLIB_NHM_PEBS, }, { .pme_uname = "ACTIVE_CYCLES", .pme_udesc = "Alias for TOTAL_CYCLES", .pme_ucode = 0x01 | (1<< 16), /* counter mask = 1 */ .pme_uflags = PFMLIB_NHM_PEBS, }, }, .pme_numasks = 6 }, { .pme_name = "BR_MISP_RETIRED", .pme_desc = "Mispredicted retired branches", .pme_code = 0xC5, .pme_flags = PFMLIB_NHM_PEBS|PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ALL_BRANCHES", .pme_udesc = "Mispredicted retired branch instructions", .pme_ucode = 0x4, .pme_uflags = 0, }, { .pme_uname = "NEAR_CALL", .pme_udesc = "Mispredicted near retired calls", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "CONDITIONAL", .pme_udesc = "Mispredicted conditional branches retired", .pme_ucode = 0x1, .pme_uflags = 0, } }, .pme_numasks = 3 }, { .pme_name = "EPT", .pme_desc = "Extended Page Table", .pme_code = 0x4F, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "WALK_CYCLES", .pme_udesc = "Extended Page Table walk cycles", .pme_ucode = 0x10, .pme_uflags = 0, }, }, .pme_numasks = 1 }, { .pme_name = "UOPS_EXECUTED", .pme_desc = "micro-ops executed", .pme_code = 0xB1, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "PORT0", .pme_udesc = "Uops executed on port 0 (integer arithmetic, SIMD and FP add uops)", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "PORT1", .pme_udesc = "Uops executed on port 1 (integer arithmetic, SIMD, integer shift, FP multiply, FP divide uops)", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "PORT2_CORE", .pme_udesc = "Uops executed on port 2 from any thread (load uops) (core count only)", .pme_ucode = 0x04 | (1<< 13), /* any=1 */ .pme_uflags = 0, }, { .pme_uname = "PORT3_CORE", .pme_udesc = "Uops executed on port 3 from any thread (store uops) (core count only)", .pme_ucode = 0x08 | (1<<13), /* any=1 */ .pme_uflags = 0, }, { .pme_uname = "PORT4_CORE", .pme_udesc = "Uops executed on port 4 from any thread (handle store values for stores on port 3) (core count only)", .pme_ucode = 0x10 | (1<<13), /* any=1 */ .pme_uflags = 0, }, { .pme_uname = "PORT5", .pme_udesc = "Uops executed on port 5", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "PORT015", .pme_udesc = "Uops issued on ports 0, 1 or 5", .pme_ucode = 0x40, .pme_uflags = 0, }, { .pme_uname = "PORT234_CORE", .pme_udesc = "Uops issued on ports 2, 3 or 4 from any thread (core count only)", .pme_ucode = 0x80 | (1<<13), /* any=1 */ .pme_uflags = 0, }, { .pme_uname = "PORT015_STALL_CYCLES", .pme_udesc = "Cycles no Uops issued on ports 0, 1 or 5", .pme_ucode = 0x40 | (1<<16) | (1<<15), /* counter-mask=1, inv=1 */ .pme_uflags = 0, }, { .pme_uname = "CORE_ACTIVE_CYCLES_NO_PORT5", .pme_udesc = "Cycles in which uops are executed only on port0-4 on any thread (core count only)", .pme_ucode = 0x1f | (1<<13) | (1<<16), /* counter-mask = 1, any=1 */ }, { .pme_uname = "CORE_ACTIVE_CYCLES", .pme_udesc = "Cycles in which uops are executed on any port any thread (core count only)", .pme_ucode = 0x3f | (1<<13) | (1<<16), /* counter-mask = 1, any=1 */ }, { .pme_uname = "CORE_STALL_CYCLES", .pme_udesc = "Cycles in which no uops are executed on any port any thread (core count only)", .pme_ucode = 0x3f | (1<<13) | (1<<15) | (1<<16), /* counter-mask = 1, inv = 1,any=1 */ }, { .pme_uname = "CORE_STALL_CYCLES_NO_PORT5", .pme_udesc = "Cycles in which no uops are executed on any port0-4 on any thread (core count only)", .pme_ucode = 0x1f | (1<<13) | (1<<15) | (1<<16), /* counter-mask = 1, inv = 1,any=1 */ }, { .pme_uname = "CORE_STALL_COUNT", .pme_udesc = "number of transitions from stalled to uops to execute on any port any thread(core count only)", .pme_ucode = 0x3f | (1<<13) | (1<<15) | (1<<16) | (1<<10), /* counter-mask = 1, inv = 1, any=1, edge=1 */ }, { .pme_uname = "CORE_STALL_COUNT_NO_PORT5", .pme_udesc = "number of transitions from stalled to uops to execute on port0-4 on any thread (core count only)", .pme_ucode = 0x1f | (1<<13) | (1<<15) | (1<<16) | (1<<10), /* counter-mask = 1, inv = 1, any=1, edge=1 */ }, }, .pme_numasks = 15 }, { .pme_name = "IO_TRANSACTIONS", .pme_desc = "I/O transactions", .pme_code = 0x016C, .pme_flags = 0, }, { .pme_name = "ES_REG_RENAMES", .pme_desc = "ES segment renames", .pme_code = 0x01D5, .pme_flags = 0, }, { .pme_name = "INST_RETIRED", .pme_desc = "Instructions retired", .pme_code = 0xC0, .pme_flags = PFMLIB_NHM_PEBS|PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY_P", .pme_udesc = "Instructions Retired (Precise Event)", .pme_ucode = 0x00, .pme_uflags = 0, }, { .pme_uname = "X87", .pme_udesc = "Retired floating-point operations (Precise Event)", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "MMX", .pme_udesc = "Retired MMX instructions (Precise Event)", .pme_ucode = 0x4, .pme_uflags = 0, }, { .pme_uname = "TOTAL_CYCLES", .pme_udesc = "Total cycles (Precise Event)", .pme_ucode = 0x1 | (16 << 16) | (1 <<15), /* inv=1, cmask = 16 */ .pme_uflags = 0, }, }, .pme_numasks = 4 }, { .pme_name = "ILD_STALL", .pme_desc = "Instruction Length Decoder stalls", .pme_code = 0x87, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "Any Instruction Length Decoder stall cycles", .pme_ucode = 0xF, .pme_uflags = 0, }, { .pme_uname = "IQ_FULL", .pme_udesc = "Instruction Queue full stall cycles", .pme_ucode = 0x4, .pme_uflags = 0, }, { .pme_uname = "LCP", .pme_udesc = "Length Change Prefix stall cycles", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "MRU", .pme_udesc = "Stall cycles due to BPU MRU bypass", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "REGEN", .pme_udesc = "Regen stall cycles", .pme_ucode = 0x8, .pme_uflags = 0, }, }, .pme_numasks = 5 }, { .pme_name = "DTLB_LOAD_MISSES", .pme_desc = "DTLB load misses", .pme_code = 0x8, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "DTLB load misses", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "PDE_MISS", .pme_udesc = "DTLB load miss caused by low part of address", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "STLB_HIT", .pme_udesc = "DTLB second level hit", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "WALK_COMPLETED", .pme_udesc = "DTLB load miss page walks complete", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "WALK_CYCLES", .pme_udesc = "DTLB load miss page walk cycles", .pme_ucode = 0x4, .pme_uflags = 0, }, }, .pme_numasks = 5 }, { .pme_name = "L2_LINES_IN", .pme_desc = "L2 lines alloacated", .pme_code = 0xF1, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "L2 lines alloacated", .pme_ucode = 0x7, .pme_uflags = 0, }, { .pme_uname = "E_STATE", .pme_udesc = "L2 lines allocated in the E state", .pme_ucode = 0x4, .pme_uflags = 0, }, { .pme_uname = "S_STATE", .pme_udesc = "L2 lines allocated in the S state", .pme_ucode = 0x2, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "SSEX_UOPS_RETIRED", .pme_desc = "SIMD micro-ops retired (Precise Event)", .pme_code = 0xC7, .pme_flags = PFMLIB_NHM_PEBS|PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "PACKED_DOUBLE", .pme_udesc = "SIMD Packed-Double Uops retired (Precise Event)", .pme_ucode = 0x4, .pme_uflags = 0, }, { .pme_uname = "PACKED_SINGLE", .pme_udesc = "SIMD Packed-Single Uops retired (Precise Event)", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "SCALAR_DOUBLE", .pme_udesc = "SIMD Scalar-Double Uops retired (Precise Event)", .pme_ucode = 0x8, .pme_uflags = 0, }, { .pme_uname = "SCALAR_SINGLE", .pme_udesc = "SIMD Scalar-Single Uops retired (Precise Event)", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "VECTOR_INTEGER", .pme_udesc = "SIMD Vector Integer Uops retired (Precise Event)", .pme_ucode = 0x10, .pme_uflags = 0, }, }, .pme_numasks = 5 }, { .pme_name = "STORE_BLOCKS", .pme_desc = "Load delayed by block code", .pme_code = 0x6, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "AT_RET", .pme_udesc = "Loads delayed with at-Retirement block code", .pme_ucode = 0x4, .pme_uflags = 0, }, { .pme_uname = "L1D_BLOCK", .pme_udesc = "Cacheable loads delayed with L1D block code", .pme_ucode = 0x8, .pme_uflags = 0, }, }, .pme_numasks = 2 }, { .pme_name = "FP_MMX_TRANS", .pme_desc = "Floating Point to and from MMX transitions", .pme_code = 0xCC, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "All Floating Point to and from MMX transitions", .pme_ucode = 0x3, .pme_uflags = 0, }, { .pme_uname = "TO_FP", .pme_udesc = "Transitions from MMX to Floating Point instructions", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "TO_MMX", .pme_udesc = "Transitions from Floating Point to MMX instructions", .pme_ucode = 0x2, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "CACHE_LOCK_CYCLES", .pme_desc = "Cache locked", .pme_code = 0x63, .pme_flags = PFMLIB_NHM_PMC01, .pme_umasks = { { .pme_uname = "L1D", .pme_udesc = "Cycles L1D locked", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "L1D_L2", .pme_udesc = "Cycles L1D and L2 locked", .pme_ucode = 0x1, .pme_uflags = 0, }, }, .pme_numasks = 2 }, { .pme_name = "OFFCORE_REQUESTS_SQ_FULL", .pme_desc = "Offcore requests blocked due to Super Queue full", .pme_code = 0x01B2, .pme_flags = 0, }, { .pme_name = "L3_LAT_CACHE", .pme_desc = "Last level cache accesses", .pme_code = 0x2E, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "MISS", .pme_udesc = "Last level cache miss", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "REFERENCE", .pme_udesc = "Last level cache reference", .pme_ucode = 0x2, .pme_uflags = 0, }, }, .pme_numasks = 2 }, { .pme_name = "SIMD_INT_64", .pme_desc = "SIMD 64-bit integer operations", .pme_code = 0xFD, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "PACK", .pme_udesc = "SIMD integer 64 bit pack operations", .pme_ucode = 0x4, .pme_uflags = 0, }, { .pme_uname = "PACKED_ARITH", .pme_udesc = "SIMD integer 64 bit arithmetic operations", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "PACKED_LOGICAL", .pme_udesc = "SIMD integer 64 bit logical operations", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "PACKED_MPY", .pme_udesc = "SIMD integer 64 bit packed multiply operations", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "PACKED_SHIFT", .pme_udesc = "SIMD integer 64 bit shift operations", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "SHUFFLE_MOVE", .pme_udesc = "SIMD integer 64 bit shuffle/move operations", .pme_ucode = 0x40, .pme_uflags = 0, }, { .pme_uname = "UNPACK", .pme_udesc = "SIMD integer 64 bit unpack operations", .pme_ucode = 0x8, .pme_uflags = 0, }, }, .pme_numasks = 7 }, { .pme_name = "BR_INST_DECODED", .pme_desc = "Branch instructions decoded", .pme_code = 0x01E0, .pme_flags = 0, }, { .pme_name = "BR_MISP_EXEC", .pme_desc = "Mispredicted branches executed", .pme_code = 0x89, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "Mispredicted branches executed", .pme_ucode = 0x7F, .pme_uflags = 0, }, { .pme_uname = "COND", .pme_udesc = "Mispredicted conditional branches executed", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "DIRECT", .pme_udesc = "Mispredicted unconditional branches executed", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "DIRECT_NEAR_CALL", .pme_udesc = "Mispredicted non call branches executed", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "INDIRECT_NEAR_CALL", .pme_udesc = "Mispredicted indirect call branches executed", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "INDIRECT_NON_CALL", .pme_udesc = "Mispredicted indirect non call branches executed", .pme_ucode = 0x4, .pme_uflags = 0, }, { .pme_uname = "NEAR_CALLS", .pme_udesc = "Mispredicted call branches executed", .pme_ucode = 0x30, .pme_uflags = 0, }, { .pme_uname = "NON_CALLS", .pme_udesc = "Mispredicted non call branches executed", .pme_ucode = 0x7, .pme_uflags = 0, }, { .pme_uname = "RETURN_NEAR", .pme_udesc = "Mispredicted return branches executed", .pme_ucode = 0x8, .pme_uflags = 0, }, { .pme_uname = "TAKEN", .pme_udesc = "Mispredicted taken branches executed", .pme_ucode = 0x40, .pme_uflags = 0, }, }, .pme_numasks = 10 }, { .pme_name = "SQ_FULL_STALL_CYCLES", .pme_desc = "Super Queue full stall cycles", .pme_code = 0x01F6, .pme_flags = 0, }, /* * BEGIN OFFCORE_RESPONSE */ { .pme_name = "OFFCORE_RESPONSE_0", .pme_desc = "Offcore response 0", .pme_code = 0x01B7, .pme_flags = PFMLIB_NHM_OFFCORE_RSP0, .pme_umasks = { { .pme_uname = "DMND_DATA_RD", .pme_udesc = "Request. Counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "DMND_RFO", .pme_udesc = "Request. Counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "DMND_IFETCH", .pme_udesc = "Request. Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "WB", .pme_udesc = "Request. Counts the number of writeback (modified to exclusive) transactions", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "PF_DATA_RD", .pme_udesc = "Request. Counts the number of data cacheline reads generated by L2 prefetchers", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "PF_RFO", .pme_udesc = "Request. Counts the number of RFO requests generated by L2 prefetchers", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "PF_IFETCH", .pme_udesc = "Request. Counts the number of code reads generated by L2 prefetchers", .pme_ucode = 0x40, .pme_uflags = 0, }, { .pme_uname = "OTHER", .pme_udesc = "Request. Counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lock", .pme_ucode = 0x80, .pme_uflags = 0, }, { .pme_uname = "ANY_REQUEST", .pme_udesc = "Request. Counts any request type", .pme_ucode = 0xff, .pme_uflags = 0, }, { .pme_uname = "UNCORE_HIT", .pme_udesc = "Response. Counts L3 Hit: local or remote home requests that hit L3 cache in the uncore with no coherency actions required (snooping)", .pme_ucode = 0x100, .pme_uflags = 0, }, { .pme_uname = "OTHER_CORE_HIT_SNP", .pme_udesc = "Response. Counts L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where no modified copies were found (clean)", .pme_ucode = 0x200, .pme_uflags = 0, }, { .pme_uname = "OTHER_CORE_HITM", .pme_udesc = "Response. Counts L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where modified copies were found (HITM)", .pme_ucode = 0x400, .pme_uflags = 0, }, { .pme_uname = "REMOTE_CACHE_FWD", .pme_udesc = "Response. Counts L3 Miss: local homed requests that missed the L3 cache and was serviced by forwarded data following a cross package snoop where no modified copies found. (Remote home requests are not counted)", .pme_ucode = 0x1000, .pme_uflags = 0, }, { .pme_uname = "REMOTE_DRAM", .pme_udesc = "Response. Counts L3 Miss: remote home requests that missed the L3 cache and were serviced by remote DRAM", .pme_ucode = 0x2000, .pme_uflags = 0, }, { .pme_uname = "LOCAL_DRAM", .pme_udesc = "Response. Counts L3 Miss: local home requests that missed the L3 cache and were serviced by local DRAM", .pme_ucode = 0x4000, .pme_uflags = 0, }, { .pme_uname = "NON_DRAM", .pme_udesc = "Response. Non-DRAM requests that were serviced by IOH", .pme_ucode = 0x8000, .pme_uflags = 0, }, { .pme_uname = "ANY_RESPONSE", .pme_udesc = "Response. Counts any response type", .pme_ucode = 0xf700, .pme_uflags = 0, }, }, .pme_numasks = 17 }, { .pme_name = "OFFCORE_RESPONSE_1", .pme_desc = "Offcore response 1", .pme_code = 0x01BB, .pme_flags = PFMLIB_NHM_OFFCORE_RSP1, .pme_umasks = { { .pme_uname = "DMND_DATA_RD", .pme_udesc = "Request. Counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "DMND_RFO", .pme_udesc = "Request. Counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "DMND_IFETCH", .pme_udesc = "Request. Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches", .pme_ucode = 0x04, .pme_uflags = 0, }, { .pme_uname = "WB", .pme_udesc = "Request. Counts the number of writeback (modified to exclusive) transactions", .pme_ucode = 0x08, .pme_uflags = 0, }, { .pme_uname = "PF_DATA_RD", .pme_udesc = "Request. Counts the number of data cacheline reads generated by L2 prefetchers", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "PF_RFO", .pme_udesc = "Request. Counts the number of RFO requests generated by L2 prefetchers", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "PF_IFETCH", .pme_udesc = "Request. Counts the number of code reads generated by L2 prefetchers", .pme_ucode = 0x40, .pme_uflags = 0, }, { .pme_uname = "OTHER", .pme_udesc = "Request. Counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lock", .pme_ucode = 0x80, .pme_uflags = 0, }, { .pme_uname = "ANY_REQUEST", .pme_udesc = "Request. Counts any request type", .pme_ucode = 0xff, .pme_uflags = 0, }, { .pme_uname = "UNCORE_HIT", .pme_udesc = "Response. Counts L3 Hit: local or remote home requests that hit L3 cache in the uncore with no coherency actions required (snooping)", .pme_ucode = 0x100, .pme_uflags = 0, }, { .pme_uname = "OTHER_CORE_HIT_SNP", .pme_udesc = "Response. Counts L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where no modified copies were found (clean)", .pme_ucode = 0x200, .pme_uflags = 0, }, { .pme_uname = "OTHER_CORE_HITM", .pme_udesc = "Response. Counts L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where modified copies were found (HITM)", .pme_ucode = 0x400, .pme_uflags = 0, }, { .pme_uname = "REMOTE_CACHE_FWD", .pme_udesc = "Response. Counts L3 Miss: local homed requests that missed the L3 cache and was serviced by forwarded data following a cross package snoop where no modified copies found. (Remote home requests are not counted)", .pme_ucode = 0x1000, .pme_uflags = 0, }, { .pme_uname = "REMOTE_DRAM", .pme_udesc = "Response. Counts L3 Miss: remote home requests that missed the L3 cache and were serviced by remote DRAM", .pme_ucode = 0x2000, .pme_uflags = 0, }, { .pme_uname = "LOCAL_DRAM", .pme_udesc = "Response. Counts L3 Miss: local home requests that missed the L3 cache and were serviced by local DRAM", .pme_ucode = 0x4000, .pme_uflags = 0, }, { .pme_uname = "NON_DRAM", .pme_udesc = "Response. Non-DRAM requests that were serviced by IOH", .pme_ucode = 0x8000, .pme_uflags = 0, }, { .pme_uname = "ANY_RESPONSE", .pme_udesc = "Response. Counts any response type", .pme_ucode = 0xf700, .pme_uflags = 0, }, }, .pme_numasks = 17 }, /* * END OFFCORE_RESPONSE */ { .pme_name = "BACLEAR", .pme_desc = "Branch address calculator clears", .pme_code = 0xE6, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "BAD_TARGET", .pme_udesc = "BACLEAR asserted with bad target address", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "CLEAR", .pme_udesc = "BACLEAR asserted, regardless of cause", .pme_ucode = 0x1, .pme_uflags = 0, }, }, .pme_numasks = 2 }, { .pme_name = "DTLB_MISSES", .pme_desc = "Data TLB misses", .pme_code = 0x49, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "DTLB misses", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "LARGE_WALK_COMPLETED", .pme_udesc = "DTLB miss large page walks", .pme_ucode = 0x80, .pme_uflags = 0, }, { .pme_uname = "STLB_HIT", .pme_udesc = "DTLB first level misses but second level hit", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "WALK_COMPLETED", .pme_udesc = "DTLB miss page walks", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "WALK_CYCLES", .pme_udesc = "DTLB miss page walk cycles", .pme_ucode = 0x4, .pme_uflags = 0, }, }, .pme_numasks = 5 }, { .pme_name = "MEM_INST_RETIRED", .pme_desc = "Memory instructions retired", .pme_code = 0x0B, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "LATENCY_ABOVE_THRESHOLD", .pme_udesc = "Memory instructions retired above programmed clocks, minimum value threhold is 4, requires PEBS", .pme_ucode = 0x10, .pme_uflags = PFMLIB_NHM_PEBS, }, { .pme_uname = "LOADS", .pme_udesc = "Instructions retired which contains a load (Precise Event)", .pme_ucode = 0x01, .pme_uflags = PFMLIB_NHM_PEBS, }, { .pme_uname = "STORES", .pme_udesc = "Instructions retired which contains a store (Precise Event)", .pme_ucode = 0x02, .pme_uflags = PFMLIB_NHM_PEBS, }, }, .pme_numasks = 3 }, { .pme_name = "UOPS_ISSUED", .pme_desc = "Uops issued", .pme_code = 0x0E, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "Uops issued", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "STALL_CYCLES", .pme_udesc = "Cycles stalled no issued uops", .pme_ucode = 0x01 | (1<<16) | (1<<15), /* counter-mask=1, inv=1 */ .pme_uflags = 0, }, { .pme_uname = "FUSED", .pme_udesc = "Fused Uops issued", .pme_ucode = 0x02, .pme_uflags = 0, }, { .pme_uname = "CYCLES_ALL_THREADS", .pme_udesc = "Cycles uops issued on either threads (core count)", .pme_ucode = 0x01 | (1<<16) | (1<<13), /* counter-mask=1, any=1 */ .pme_uflags = 0, }, { .pme_uname = "CORE_STALL_CYCLES", .pme_udesc = "Cycles no uops issued on any threads (core count)", .pme_ucode = 0x01 | (1<<16) | (1<<15) | (1<<13), /* counter-mask=1, any=1, inv=1 */ .pme_uflags = 0, }, }, .pme_numasks = 5 }, { .pme_name = "L2_RQSTS", .pme_desc = "L2 requests", .pme_code = 0x24, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "IFETCH_HIT", .pme_udesc = "L2 instruction fetch hits", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "IFETCH_MISS", .pme_udesc = "L2 instruction fetch misses", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "IFETCHES", .pme_udesc = "L2 instruction fetches", .pme_ucode = 0x30, .pme_uflags = 0, }, { .pme_uname = "LD_HIT", .pme_udesc = "L2 load hits", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "LD_MISS", .pme_udesc = "L2 load misses", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "LOADS", .pme_udesc = "L2 requests", .pme_ucode = 0x3, .pme_uflags = 0, }, { .pme_uname = "MISS", .pme_udesc = "All L2 misses", .pme_ucode = 0xAA, .pme_uflags = 0, }, { .pme_uname = "PREFETCH_HIT", .pme_udesc = "L2 prefetch hits", .pme_ucode = 0x40, .pme_uflags = 0, }, { .pme_uname = "PREFETCH_MISS", .pme_udesc = "L2 prefetch misses", .pme_ucode = 0x80, .pme_uflags = 0, }, { .pme_uname = "PREFETCHES", .pme_udesc = "All L2 prefetches", .pme_ucode = 0xC0, .pme_uflags = 0, }, { .pme_uname = "REFERENCES", .pme_udesc = "All L2 requests", .pme_ucode = 0xFF, .pme_uflags = 0, }, { .pme_uname = "RFO_HIT", .pme_udesc = "L2 RFO hits", .pme_ucode = 0x4, .pme_uflags = 0, }, { .pme_uname = "RFO_MISS", .pme_udesc = "L2 RFO misses", .pme_ucode = 0x8, .pme_uflags = 0, }, { .pme_uname = "RFOS", .pme_udesc = "L2 RFO requests", .pme_ucode = 0xC, .pme_uflags = 0, }, }, .pme_numasks = 14 }, { .pme_name = "TWO_UOP_INSTS_DECODED", .pme_desc = "Two Uop instructions decoded", .pme_code = 0x0119, .pme_flags = 0, }, { .pme_name = "LOAD_DISPATCH", .pme_desc = "Loads dispatched", .pme_code = 0x13, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "All loads dispatched", .pme_ucode = 0x7, .pme_uflags = 0, }, { .pme_uname = "RS", .pme_udesc = "Number of loads dispatched from the Reservation Station (RS) that bypass the Memory Order Buffer", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "RS_DELAYED", .pme_udesc = "Number of delayed RS dispatches at the stage latch", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "MOB", .pme_udesc = "Number of loads dispatched from Reservation Station (RS)", .pme_ucode = 0x4, .pme_uflags = 0, }, }, .pme_numasks = 4 }, { .pme_name = "BACLEAR_FORCE_IQ", .pme_desc = "BACLEAR forced by Instruction queue", .pme_code = 0x01A7, .pme_flags = 0, }, { .pme_name = "SNOOPQ_REQUESTS", .pme_desc = "Snoopq requests", .pme_code = 0xB4, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "CODE", .pme_udesc = "Snoop code requests", .pme_ucode = 0x4, .pme_uflags = 0, }, { .pme_uname = "DATA", .pme_udesc = "Snoop data requests", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "INVALIDATE", .pme_udesc = "Snoop invalidate requests", .pme_ucode = 0x2, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "OFFCORE_REQUESTS", .pme_desc = "offcore requests", .pme_code = 0xB0, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "All offcore requests", .pme_ucode = 0x80, .pme_uflags = 0, }, { .pme_uname = "ANY_READ", .pme_udesc = "Offcore read requests", .pme_ucode = 0x8, .pme_uflags = 0, }, { .pme_uname = "ANY_RFO", .pme_udesc = "Offcore RFO requests", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "DEMAND_READ_CODE", .pme_udesc = "Offcore demand code read requests", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "DEMAND_READ_DATA", .pme_udesc = "Offcore demand data read requests", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "DEMAND_RFO", .pme_udesc = "Offcore demand RFO requests", .pme_ucode = 0x4, .pme_uflags = 0, }, { .pme_uname = "L1D_WRITEBACK", .pme_udesc = "Offcore L1 data cache writebacks", .pme_ucode = 0x40, .pme_uflags = 0, }, }, .pme_numasks = 7 }, { .pme_name = "LOAD_BLOCK", .pme_desc = "Loads blocked", .pme_code = 0x3, .pme_flags = 0, .pme_umasks = { { .pme_uname = "OVERLAP_STORE", .pme_udesc = "lods that partially overlap an earlier store", .pme_ucode = 0x2, .pme_uflags = 0, }, }, .pme_numasks = 1 }, { .pme_name = "MISALIGN_MEMORY", .pme_desc = "Misaligned accesses", .pme_code = 0x5, .pme_flags = 0, .pme_umasks = { { .pme_uname = "STORE", .pme_udesc = "store referenced with misaligned address", .pme_ucode = 0x2, .pme_uflags = 0, }, }, .pme_numasks = 1 }, { .pme_name = "INST_QUEUE_WRITE_CYCLES", .pme_desc = "Cycles instructions are written to the instruction queue", .pme_code = 0x011E, .pme_flags = 0, }, { .pme_name = "MACHINE_CLEARS", .pme_desc = "Machine clear asserted", .pme_code = 0xC3, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "MEM_ORDER", .pme_udesc = "Execution pipeline restart due to Memory ordering conflicts ", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "CYCLES", .pme_udesc = "cycles machine clear is asserted", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "SMC", .pme_udesc = "Self-modifying code detected", .pme_ucode = 0x4, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "FP_COMP_OPS_EXE", .pme_desc = "SSE/MMX micro-ops", .pme_code = 0x10, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "MMX", .pme_udesc = "MMX Uops", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "SSE_DOUBLE_PRECISION", .pme_udesc = "SSE FP double precision Uops", .pme_ucode = 0x80, .pme_uflags = 0, }, { .pme_uname = "SSE_FP", .pme_udesc = "SSE and SSE2 FP Uops", .pme_ucode = 0x4, .pme_uflags = 0, }, { .pme_uname = "SSE_FP_PACKED", .pme_udesc = "SSE FP packed Uops", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "SSE_FP_SCALAR", .pme_udesc = "SSE FP scalar Uops", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "SSE_SINGLE_PRECISION", .pme_udesc = "SSE FP single precision Uops", .pme_ucode = 0x40, .pme_uflags = 0, }, { .pme_uname = "SSE2_INTEGER", .pme_udesc = "SSE2 integer Uops", .pme_ucode = 0x8, .pme_uflags = 0, }, { .pme_uname = "X87", .pme_udesc = "Computational floating-point operations executed", .pme_ucode = 0x1, .pme_uflags = 0, }, }, .pme_numasks = 8 }, { .pme_name = "ITLB_FLUSH", .pme_desc = "ITLB flushes", .pme_code = 0x01AE, .pme_flags = 0, }, { .pme_name = "BR_INST_RETIRED", .pme_desc = "Retired branch instructions (Precise Event)", .pme_code = 0xC4, .pme_flags = PFMLIB_NHM_PEBS|PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ALL_BRANCHES", .pme_udesc = "Retired branch instructions (Precise Event)", .pme_ucode = 0x0, .pme_uflags = 0, }, { .pme_uname = "CONDITIONAL", .pme_udesc = "Retired conditional branch instructions (Precise Event)", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "NEAR_CALL", .pme_udesc = "Retired near call instructions (Precise Event)", .pme_ucode = 0x2, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "L1D_CACHE_PREFETCH_LOCK_FB_HIT", .pme_desc = "L1D prefetch load lock accepted in fill buffer", .pme_code = 0x0152, .pme_flags = 0, }, { .pme_name = "LARGE_ITLB", .pme_desc = "Large ITLB accesses", .pme_code = 0x82, .pme_flags = 0, .pme_umasks = { { .pme_uname = "HIT", .pme_udesc = "Large ITLB hit", .pme_ucode = 0x1, .pme_uflags = 0, }, }, .pme_numasks = 1 }, { .pme_name = "LSD", .pme_desc = "Loop stream detector", .pme_code = 0xA8, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "UOPS", .pme_udesc = "counts the number of micro-ops delivered by LSD", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "ACTIVE", .pme_udesc = "Cycles is which at least one micro-op delivered by LSD", .pme_ucode = 0x01 | (1<<16), .pme_uflags = 0, }, }, .pme_numasks = 2 }, { .pme_name = "L2_LINES_OUT", .pme_desc = "L2 lines evicted", .pme_code = 0xF2, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "L2 lines evicted", .pme_ucode = 0xF, .pme_uflags = 0, }, { .pme_uname = "DEMAND_CLEAN", .pme_udesc = "L2 lines evicted by a demand request", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "DEMAND_DIRTY", .pme_udesc = "L2 modified lines evicted by a demand request", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "PREFETCH_CLEAN", .pme_udesc = "L2 lines evicted by a prefetch request", .pme_ucode = 0x4, .pme_uflags = 0, }, { .pme_uname = "PREFETCH_DIRTY", .pme_udesc = "L2 modified lines evicted by a prefetch request", .pme_ucode = 0x8, .pme_uflags = 0, }, }, .pme_numasks = 5 }, { .pme_name = "ITLB_MISSES", .pme_desc = "ITLB miss", .pme_code = 0x85, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "ITLB miss", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "WALK_COMPLETED", .pme_udesc = "ITLB miss page walks", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "WALK_CYCLES", .pme_udesc = "ITLB miss page walk cycles", .pme_ucode = 0x4, .pme_uflags = 0, }, { .pme_uname = "LARGE_WALK_COMPLETED", .pme_udesc = "Number of completed large page walks due to misses in the STLB", .pme_ucode = 0x80, .pme_uflags = 0, }, }, .pme_numasks = 4 }, { .pme_name = "L1D_PREFETCH", .pme_desc = "L1D hardware prefetch", .pme_code = 0x4E, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "MISS", .pme_udesc = "L1D hardware prefetch misses", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "REQUESTS", .pme_udesc = "L1D hardware prefetch requests", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "TRIGGERS", .pme_udesc = "L1D hardware prefetch requests triggered", .pme_ucode = 0x4, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "SQ_MISC", .pme_desc = "Super Queue miscellaneous", .pme_code = 0xF4, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "LRU_HINTS", .pme_udesc = "Super Queue LRU hints sent to LLC", .pme_ucode = 0x4, .pme_uflags = 0, }, { .pme_uname = "SPLIT_LOCK", .pme_udesc = "Super Queue lock splits across a cache line", .pme_ucode = 0x10, .pme_uflags = 0, }, }, .pme_numasks = 2 }, { .pme_name = "SEG_RENAME_STALLS", .pme_desc = "Segment rename stall cycles", .pme_code = 0x01D4, .pme_flags = 0, }, { .pme_name = "FP_ASSIST", .pme_desc = "X87 Floating point assists (Precise Event)", .pme_code = 0xF7, .pme_flags = PFMLIB_NHM_PEBS|PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ALL", .pme_udesc = "All X87 Floating point assists (Precise Event)", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "INPUT", .pme_udesc = "X87 Floating poiint assists for invalid input value (Precise Event)", .pme_ucode = 0x4, .pme_uflags = 0, }, { .pme_uname = "OUTPUT", .pme_udesc = "X87 Floating point assists for invalid output value (Precise Event)", .pme_ucode = 0x2, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "SIMD_INT_128", .pme_desc = "128 bit SIMD operations", .pme_code = 0x12, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "PACK", .pme_udesc = "128 bit SIMD integer pack operations", .pme_ucode = 0x4, .pme_uflags = 0, }, { .pme_uname = "PACKED_ARITH", .pme_udesc = "128 bit SIMD integer arithmetic operations", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "PACKED_LOGICAL", .pme_udesc = "128 bit SIMD integer logical operations", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "PACKED_MPY", .pme_udesc = "128 bit SIMD integer multiply operations", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "PACKED_SHIFT", .pme_udesc = "128 bit SIMD integer shift operations", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "SHUFFLE_MOVE", .pme_udesc = "128 bit SIMD integer shuffle/move operations", .pme_ucode = 0x40, .pme_uflags = 0, }, { .pme_uname = "UNPACK", .pme_udesc = "128 bit SIMD integer unpack operations", .pme_ucode = 0x8, .pme_uflags = 0, }, }, .pme_numasks = 7 }, { .pme_name = "OFFCORE_REQUESTS_OUTSTANDING", .pme_desc = "Outstanding offcore requests", .pme_code = 0x60, .pme_flags = PFMLIB_NHM_PMC0|PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY_READ", .pme_udesc = "Outstanding offcore reads", .pme_ucode = 0x8, .pme_uflags = 0, }, { .pme_uname = "DEMAND_READ_CODE", .pme_udesc = "Outstanding offcore demand code reads", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "DEMAND_READ_DATA", .pme_udesc = "Outstanding offcore demand data reads", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "DEMAND_RFO", .pme_udesc = "Outstanding offcore demand RFOs", .pme_ucode = 0x4, .pme_uflags = 0, }, }, .pme_numasks = 4 }, { .pme_name = "MEM_STORE_RETIRED", .pme_desc = "Retired stores", .pme_code = 0xC, .pme_flags = 0, .pme_umasks = { { .pme_uname = "DTLB_MISS", .pme_udesc = "Retired stores that miss the DTLB (Precise Event)", .pme_ucode = 0x1, .pme_uflags = 0, }, }, .pme_numasks = 1 }, { .pme_name = "INST_DECODED", .pme_desc = "Instructions decoded", .pme_code = 0x18, .pme_flags = 0, .pme_umasks = { { .pme_uname = "DEC0", .pme_udesc = "Instructions that must be decoded by decoder 0", .pme_ucode = 0x1, .pme_uflags = 0, }, }, .pme_numasks = 1 }, { .pme_name = "MACRO_INSTS_FUSIONS_DECODED", .pme_desc = "Count the number of instructions decoded that are macros-fused but not necessarily executed or retired", .pme_code = 0x01A6, .pme_flags = 0, }, { .pme_name = "MACRO_INSTS", .pme_desc = "macro-instructions", .pme_code = 0xD0, .pme_flags = 0, .pme_umasks = { { .pme_uname = "DECODED", .pme_udesc = "Instructions decoded", .pme_ucode = 0x1, .pme_uflags = 0, }, }, .pme_numasks = 1 }, { .pme_name = "PARTIAL_ADDRESS_ALIAS", .pme_desc = "False dependencies due to partial address aliasing", .pme_code = 0x0107, .pme_flags = 0, }, { .pme_name = "ARITH", .pme_desc = "Counts arithmetic multiply and divide operations", .pme_code = 0x14, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "CYCLES_DIV_BUSY", .pme_udesc = "Counts the number of cycles the divider is busy executing divide or square root operations. The divide can be integer, X87 or Streaming SIMD Extensions (SSE). The square root operation can be either X87 or SSE. Count may be incorrect when HT is on", .pme_ucode = 0x01, .pme_uflags = 0, }, { .pme_uname = "DIV", .pme_udesc = "Counts the number of divide or square root operations. The divide can be integer, X87 or Streaming SIMD Extensions (SSE). The square root operation can be either X87 or SSE. Count may be incorrect when HT is on", .pme_ucode = 0x01 | (1<<16) | (1<<15) | (1<<10), /* cmask=1  invert=1  edge=1 */ .pme_uflags = 0, }, { .pme_uname = "MUL", .pme_udesc = "Counts the number of multiply operations executed. This includes integer as well as floating point multiply operations but excludes DPPS mul and MPSAD. Count may be incorrect when HT is on", .pme_ucode = 0x02, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "L2_TRANSACTIONS", .pme_desc = "All L2 transactions", .pme_code = 0xF0, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "All L2 transactions", .pme_ucode = 0x80, .pme_uflags = 0, }, { .pme_uname = "FILL", .pme_udesc = "L2 fill transactions", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "IFETCH", .pme_udesc = "L2 instruction fetch transactions", .pme_ucode = 0x4, .pme_uflags = 0, }, { .pme_uname = "L1D_WB", .pme_udesc = "L1D writeback to L2 transactions", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "LOAD", .pme_udesc = "L2 Load transactions", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "PREFETCH", .pme_udesc = "L2 prefetch transactions", .pme_ucode = 0x8, .pme_uflags = 0, }, { .pme_uname = "RFO", .pme_udesc = "L2 RFO transactions", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "WB", .pme_udesc = "L2 writeback to LLC transactions", .pme_ucode = 0x40, .pme_uflags = 0, }, }, .pme_numasks = 8 }, { .pme_name = "INST_QUEUE_WRITES", .pme_desc = "Instructions written to instruction queue.", .pme_code = 0x0117, .pme_flags = 0, }, { .pme_name = "LSD_OVERFLOW", .pme_desc = "Number of loops that cannot stream from the instruction queue.", .pme_code = 0x0120, .pme_flags = 0, }, { .pme_name = "SB_DRAIN", .pme_desc = "store buffer", .pme_code = 0x4, .pme_flags = 0, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "All Store buffer stall cycles", .pme_ucode = 0x7, .pme_uflags = 0, }, }, .pme_numasks = 1 }, { .pme_name = "LOAD_HIT_PRE", .pme_desc = "Load operations conflicting with software prefetches", .pme_code = 0x014C, .pme_flags = PFMLIB_NHM_PMC01, }, { .pme_name = "MEM_UNCORE_RETIRED", .pme_desc = "Load instructions retired (Precise Event)", .pme_code = 0xF, .pme_flags = PFMLIB_NHM_PEBS|PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "LOCAL_HITM", .pme_udesc = "Load instructions retired that HIT modified data in sibling core (Precise Event) (Model 44 only)", .pme_ucode = 0x2, .pme_umodel = 44, }, { .pme_uname = "LOCAL_DRAM_AND_REMOTE_CACHE_HIT", .pme_udesc = "Load instructions retired local dram and remote cache HIT data sources (Precise Event) (Model 44 only)", .pme_ucode = 0x8, .pme_umodel = 44, }, { .pme_uname = "REMOTE_DRAM", .pme_udesc = "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event) (Model 44 only)", .pme_ucode = 0x10, .pme_umodel = 44, }, { .pme_uname = "UNCACHEABLE", .pme_udesc = "Load instructions retired IO (Precise Event)", .pme_ucode = 0x80, }, { .pme_uname = "REMOTE_HITM", .pme_udesc = "Retired lods that hit remote socket in modified state (Precise Event) (Model 44 only)", .pme_ucode = 0x4, .pme_umodel = 44, }, { .pme_uname = "OTHER_LLC_MISS", .pme_udesc = "Load instructions retired other LLC miss (Precise Event) (Model 44 only)", .pme_ucode = 0x20, .pme_umodel = 44, }, { .pme_uname = "UNKNOWN_SOURCE", .pme_udesc = "Load instructions retired unknown LLC miss(Precise Event) (Model 44 only)", .pme_ucode = 0x1, .pme_umodel = 44, }, { .pme_uname = "LOCAL_DRAM", .pme_udesc = "Retired loads with a data source of local DRAM or locally homed remote cache HITM (Precise Event) (Model 37 only)", .pme_ucode = 0x10, .pme_umodel = 37, }, { .pme_uname = "OTHER_CORE_L2_HITM", .pme_udesc = "Retired loads instruction that hit modified data in sibling core (Precise Event) (Model 37 only)", .pme_ucode = 0x2, .pme_umodel = 37, }, { .pme_uname = "REMOTE_CACHE_LOCAL_HOME_HIT", .pme_udesc = "Retired loads instruction that hit remote cache hit data source (Precise Event) (Model 37 only)", .pme_ucode = 0x8, .pme_umodel = 37, }, { .pme_uname = "REMOTE_DRAM", .pme_udesc = "Retired loads instruction remote DRAM and remote home-remote cache HITM (Precise Event) (Model 37 only)", .pme_ucode = 0x20, .pme_umodel = 37, }, }, .pme_numasks = 11, }, { .pme_name = "L2_DATA_RQSTS", .pme_desc = "All L2 data requests", .pme_code = 0x26, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "All L2 data requests", .pme_ucode = 0xFF, .pme_uflags = 0, }, { .pme_uname = "DEMAND_E_STATE", .pme_udesc = "L2 data demand loads in E state", .pme_ucode = 0x4, .pme_uflags = 0, }, { .pme_uname = "DEMAND_I_STATE", .pme_udesc = "L2 data demand loads in I state (misses)", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "DEMAND_M_STATE", .pme_udesc = "L2 data demand loads in M state", .pme_ucode = 0x8, .pme_uflags = 0, }, { .pme_uname = "DEMAND_MESI", .pme_udesc = "L2 data demand requests", .pme_ucode = 0xF, .pme_uflags = 0, }, { .pme_uname = "DEMAND_S_STATE", .pme_udesc = "L2 data demand loads in S state", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "PREFETCH_E_STATE", .pme_udesc = "L2 data prefetches in E state", .pme_ucode = 0x40, .pme_uflags = 0, }, { .pme_uname = "PREFETCH_I_STATE", .pme_udesc = "L2 data prefetches in the I state (misses)", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "PREFETCH_M_STATE", .pme_udesc = "L2 data prefetches in M state", .pme_ucode = 0x80, .pme_uflags = 0, }, { .pme_uname = "PREFETCH_MESI", .pme_udesc = "All L2 data prefetches", .pme_ucode = 0xF0, .pme_uflags = 0, }, { .pme_uname = "PREFETCH_S_STATE", .pme_udesc = "L2 data prefetches in the S state", .pme_ucode = 0x20, .pme_uflags = 0, }, }, .pme_numasks = 11 }, { .pme_name = "BR_INST_EXEC", .pme_desc = "Branch instructions executed", .pme_code = 0x88, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "Branch instructions executed", .pme_ucode = 0x7F, .pme_uflags = 0, }, { .pme_uname = "COND", .pme_udesc = "Conditional branch instructions executed", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "DIRECT", .pme_udesc = "Unconditional branches executed", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "DIRECT_NEAR_CALL", .pme_udesc = "Unconditional call branches executed", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "INDIRECT_NEAR_CALL", .pme_udesc = "Indirect call branches executed", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "INDIRECT_NON_CALL", .pme_udesc = "Indirect non call branches executed", .pme_ucode = 0x4, .pme_uflags = 0, }, { .pme_uname = "NEAR_CALLS", .pme_udesc = "Call branches executed", .pme_ucode = 0x30, .pme_uflags = 0, }, { .pme_uname = "NON_CALLS", .pme_udesc = "All non call branches executed", .pme_ucode = 0x7, .pme_uflags = 0, }, { .pme_uname = "RETURN_NEAR", .pme_udesc = "Indirect return branches executed", .pme_ucode = 0x8, .pme_uflags = 0, }, { .pme_uname = "TAKEN", .pme_udesc = "Taken branches executed", .pme_ucode = 0x40, .pme_uflags = 0, }, }, .pme_numasks = 10 }, { .pme_name = "ITLB_MISS_RETIRED", .pme_desc = "Retired instructions that missed the ITLB (Precise Event)", .pme_code = 0x20C8, .pme_flags = 0, }, { .pme_name = "BPU_MISSED_CALL_RET", .pme_desc = "Branch prediction unit missed call or return", .pme_code = 0x01E5, .pme_flags = 0, }, { .pme_name = "SNOOPQ_REQUESTS_OUTSTANDING", .pme_desc = "Outstanding snoop requests", .pme_code = 0xB3, .pme_flags = PFMLIB_NHM_PMC0|PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "CODE", .pme_udesc = "Outstanding snoop code requests", .pme_ucode = 0x4, .pme_uflags = 0, }, { .pme_uname = "CODE_NOT_EMPTY", .pme_udesc = "Cycles snoop code requests queue not empty", .pme_ucode = 0x4 | (1 << 16), /* cmask=1 */ .pme_uflags = 0, }, { .pme_uname = "DATA", .pme_udesc = "Outstanding snoop data requests", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "DATA_NOT_EMPTY", .pme_udesc = "Cycles snoop data requests queue not empty", .pme_ucode = 0x1 | (1 << 16), /* cmask=1 */ .pme_uflags = 0, }, { .pme_uname = "INVALIDATE", .pme_udesc = "Outstanding snoop invalidate requests", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "INVALIDATE_NOT_EMPTY", .pme_udesc = "Cycles snoop invalidate requests queue not empty", .pme_ucode = 0x2 | (1 << 16), /* cmask=1 */ .pme_uflags = 0, }, }, .pme_numasks = 6 }, { .pme_name = "MEM_LOAD_RETIRED", .pme_desc = "memory load retired (Precise Event)", .pme_code = 0xCB, .pme_flags = PFMLIB_NHM_PEBS|PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "DTLB_MISS", .pme_udesc = "Retired loads that miss the DTLB (Precise Event)", .pme_ucode = 0x80, .pme_uflags = 0, }, { .pme_uname = "HIT_LFB", .pme_udesc = "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)", .pme_ucode = 0x40, .pme_uflags = 0, }, { .pme_uname = "L1D_HIT", .pme_udesc = "Retired loads that hit the L1 data cache (Precise Event)", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "L2_HIT", .pme_udesc = "Retired loads that hit the L2 cache (Precise Event)", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "L3_MISS", .pme_udesc = "Retired loads that miss the LLC cache (Precise Event)", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "L3_UNSHARED_HIT", .pme_udesc = "Retired loads that hit valid versions in the LLC cache (Precise Event)", .pme_ucode = 0x4, .pme_uflags = 0, }, { .pme_uname = "OTHER_CORE_L2_HIT_HITM", .pme_udesc = "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)", .pme_ucode = 0x8, .pme_uflags = 0, }, }, .pme_numasks = 7 }, { .pme_name = "L1I", .pme_desc = "L1I instruction fetch", .pme_code = 0x80, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "CYCLES_STALLED", .pme_udesc = "L1I instruction fetch stall cycles", .pme_ucode = 0x4, .pme_uflags = 0, }, { .pme_uname = "HITS", .pme_udesc = "L1I instruction fetch hits", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "MISSES", .pme_udesc = "L1I instruction fetch misses", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "READS", .pme_udesc = "L1I Instruction fetches", .pme_ucode = 0x3, .pme_uflags = 0, }, }, .pme_numasks = 4 }, { .pme_name = "L2_WRITE", .pme_desc = "L2 demand lock/store RFO", .pme_code = 0x27, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "LOCK_E_STATE", .pme_udesc = "L2 demand lock RFOs in E state", .pme_ucode = 0x40, .pme_uflags = 0, }, { .pme_uname = "LOCK_HIT", .pme_udesc = "All demand L2 lock RFOs that hit the cache", .pme_ucode = 0xE0, .pme_uflags = 0, }, { .pme_uname = "LOCK_I_STATE", .pme_udesc = "L2 demand lock RFOs in I state (misses)", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "LOCK_M_STATE", .pme_udesc = "L2 demand lock RFOs in M state", .pme_ucode = 0x80, .pme_uflags = 0, }, { .pme_uname = "LOCK_MESI", .pme_udesc = "All demand L2 lock RFOs", .pme_ucode = 0xF0, .pme_uflags = 0, }, { .pme_uname = "LOCK_S_STATE", .pme_udesc = "L2 demand lock RFOs in S state", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "RFO_HIT", .pme_udesc = "All L2 demand store RFOs that hit the cache", .pme_ucode = 0xE, .pme_uflags = 0, }, { .pme_uname = "RFO_I_STATE", .pme_udesc = "L2 demand store RFOs in I state (misses)", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "RFO_M_STATE", .pme_udesc = "L2 demand store RFOs in M state", .pme_ucode = 0x8, .pme_uflags = 0, }, { .pme_uname = "RFO_MESI", .pme_udesc = "All L2 demand store RFOs", .pme_ucode = 0xF, .pme_uflags = 0, }, { .pme_uname = "RFO_S_STATE", .pme_udesc = "L2 demand store RFOs in S state", .pme_ucode = 0x2, .pme_uflags = 0, }, }, .pme_numasks = 11 }, { .pme_name = "SNOOP_RESPONSE", .pme_desc = "Snoop", .pme_code = 0xB8, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "HIT", .pme_udesc = "Thread responded HIT to snoop", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "HITE", .pme_udesc = "Thread responded HITE to snoop", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "HITM", .pme_udesc = "Thread responded HITM to snoop", .pme_ucode = 0x4, .pme_uflags = 0, }, }, .pme_numasks = 3 }, { .pme_name = "L1D", .pme_desc = "L1D cache", .pme_code = 0x51, .pme_flags = PFMLIB_NHM_PMC01|PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "M_EVICT", .pme_udesc = "L1D cache lines replaced in M state ", .pme_ucode = 0x4, .pme_uflags = 0, }, { .pme_uname = "M_REPL", .pme_udesc = "L1D cache lines allocated in the M state", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "M_SNOOP_EVICT", .pme_udesc = "L1D snoop eviction of cache lines in M state", .pme_ucode = 0x8, .pme_uflags = 0, }, { .pme_uname = "REPL", .pme_udesc = "L1 data cache lines allocated", .pme_ucode = 0x1, .pme_uflags = 0, }, }, .pme_numasks = 4 }, { .pme_name = "RESOURCE_STALLS", .pme_desc = "Resource related stall cycles", .pme_code = 0xA2, .pme_flags = 0, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "Resource related stall cycles", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "FPCW", .pme_udesc = "FPU control word write stall cycles", .pme_ucode = 0x20, .pme_uflags = 0, }, { .pme_uname = "LOAD", .pme_udesc = "Load buffer stall cycles", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "MXCSR", .pme_udesc = "MXCSR rename stall cycles", .pme_ucode = 0x40, .pme_uflags = 0, }, { .pme_uname = "OTHER", .pme_udesc = "Other Resource related stall cycles", .pme_ucode = 0x80, .pme_uflags = 0, }, { .pme_uname = "ROB_FULL", .pme_udesc = "ROB full stall cycles", .pme_ucode = 0x10, .pme_uflags = 0, }, { .pme_uname = "RS_FULL", .pme_udesc = "Reservation Station full stall cycles", .pme_ucode = 0x4, .pme_uflags = 0, }, { .pme_uname = "STORE", .pme_udesc = "Store buffer stall cycles", .pme_ucode = 0x8, .pme_uflags = 0, }, }, .pme_numasks = 8 }, { .pme_name = "RAT_STALLS", .pme_desc = "All RAT stall cycles", .pme_code = 0xD2, .pme_flags = 0, .pme_umasks = { { .pme_uname = "ANY", .pme_udesc = "All RAT stall cycles", .pme_ucode = 0xF, .pme_uflags = 0, }, { .pme_uname = "FLAGS", .pme_udesc = "Flag stall cycles", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "REGISTERS", .pme_udesc = "Partial register stall cycles", .pme_ucode = 0x2, .pme_uflags = 0, }, { .pme_uname = "ROB_READ_PORT", .pme_udesc = "ROB read port stalls cycles", .pme_ucode = 0x4, .pme_uflags = 0, }, { .pme_uname = "SCOREBOARD", .pme_udesc = "Scoreboard stall cycles", .pme_ucode = 0x8, .pme_uflags = 0, }, }, .pme_numasks = 5 }, { .pme_name = "CPU_CLK_UNHALTED", .pme_desc = "Cycles when processor is not in halted state", .pme_code = 0x3C, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "THREAD_P", .pme_udesc = "Cycles when thread is not halted (programmable counter)", .pme_ucode = 0x00, .pme_uflags = 0, }, { .pme_uname = "REF_P", .pme_udesc = "Reference base clock (133 Mhz) cycles when thread is not halted", .pme_ucode = 0x01, .pme_uflags = 0, }, }, .pme_numasks = 2 }, { .pme_name = "L1D_WB_L2", .pme_desc = "L1D writebacks to L2", .pme_code = 0x28, .pme_flags = PFMLIB_NHM_UMASK_NCOMBO, .pme_umasks = { { .pme_uname = "E_STATE", .pme_udesc = "L1 writebacks to L2 in E state", .pme_ucode = 0x4, .pme_uflags = 0, }, { .pme_uname = "I_STATE", .pme_udesc = "L1 writebacks to L2 in I state (misses)", .pme_ucode = 0x1, .pme_uflags = 0, }, { .pme_uname = "M_STATE", .pme_udesc = "L1 writebacks to L2 in M state", .pme_ucode = 0x8, .pme_uflags = 0, }, { .pme_uname = "MESI", .pme_udesc = "All L1 writebacks to L2", .pme_ucode = 0xF, .pme_uflags = 0, }, { .pme_uname = "S_STATE", .pme_udesc = "L1 writebacks to L2 in S state", .pme_ucode = 0x2, .pme_uflags = 0, }, }, .pme_numasks = 5 }, {.pme_name = "MISPREDICTED_BRANCH_RETIRED", .pme_code = 0x00c5, .pme_desc = "count mispredicted branch instructions at retirement. Specifically, this event counts at retirement of the last micro-op of a branch instruction in the architectural path of the execution and experienced misprediction in the branch prediction hardware", }, {.pme_name = "THREAD_ACTIVE", .pme_code= 0x01ec, .pme_desc = "Cycles thread is active", }, {.pme_name = "UOP_UNFUSION", .pme_code= 0x01db, .pme_desc = "Counts unfusion events due to floating point exception to a fused uop", } }; #define PME_WSM_UNHALTED_CORE_CYCLES 0 #define PME_WSM_INSTRUCTIONS_RETIRED 1 #define PME_WSM_EVENT_COUNT (sizeof(wsm_pe)/sizeof(pme_nhm_entry_t)) papi-5.5.1/src/libpfm-3.y/lib/ultra3_events.h0000644000307100002310000002647713013651450020657 0ustar yarkhangraduatestatic pme_sparc_entry_t ultra3_pe[] = { /* These two must always be first. */ { .pme_name = "Cycle_cnt", .pme_desc = "Accumulated cycles", .pme_ctrl = PME_CTRL_S0 | PME_CTRL_S1, .pme_val = 0x0, }, { .pme_name = "Instr_cnt", .pme_desc = "Number of instructions completed", .pme_ctrl = PME_CTRL_S0 | PME_CTRL_S1, .pme_val = 0x1, }, /* PIC0 events common to all UltraSPARC processors */ { .pme_name = "Dispatch0_IC_miss", .pme_desc = "I-buffer is empty from I-Cache miss", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x2, }, { .pme_name = "IC_ref", .pme_desc = "I-cache refrences", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x8, }, { .pme_name = "DC_rd", .pme_desc = "D-cache read references (including accesses that subsequently trap)", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x9, }, { .pme_name = "DC_wr", .pme_desc = "D-cache store accesses (including cacheable stores that subsequently trap)", .pme_ctrl = PME_CTRL_S0, .pme_val = 0xa, }, { .pme_name = "EC_ref", .pme_desc = "E-cache references", .pme_ctrl = PME_CTRL_S0, .pme_val = 0xc, }, { .pme_name = "EC_snoop_inv", .pme_desc = "L2-cache invalidates generated from a snoop by a remote processor", .pme_ctrl = PME_CTRL_S0, .pme_val = 0xe, }, /* PIC1 events common to all UltraSPARC processors */ { .pme_name = "Dispatch0_mispred", .pme_desc = "I-buffer is empty from Branch misprediction", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x2, }, { .pme_name = "EC_wb", .pme_desc = "Dirty sub-blocks that produce writebacks due to L2-cache miss events", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xd, }, { .pme_name = "EC_snoop_cb", .pme_desc = "L2-cache copybacks generated from a snoop by a remote processor", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xe, }, /* PIC0 events common to all UltraSPARC-III/III+/IIIi processors */ { .pme_name = "Dispatch0_br_target", .pme_desc = "I-buffer is empty due to a branch target address calculation", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x3, }, { .pme_name = "Dispatch0_2nd_br", .pme_desc = "Stall cycles due to having two branch instructions line-up in one 4-instruction group causing the second branch in the group to be re-fetched, delaying it's entrance into the I-buffer", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x4, }, { .pme_name = "Rstall_storeQ", .pme_desc = "R-stage stall for a store instruction which is the next instruction to be executed, but it stailled due to the store queue being full", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x5, }, { .pme_name = "Rstall_IU_use", .pme_desc = "R-stage stall for an event that the next instruction to be executed depends on the result of a preceeding integer instruction in the pipeline that is not yet available", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x6, }, { .pme_name = "EC_write_hit_RTO", .pme_desc = "W-cache exclusive requests that hit L2-cache in S, O, or Os state and thus, do a read-to-own bus transaction", .pme_ctrl = PME_CTRL_S0, .pme_val = 0xd, }, { .pme_name = "EC_rd_miss", .pme_desc = "L2-cache miss events (including atomics) from D-cache events", .pme_ctrl = PME_CTRL_S0, .pme_val = 0xf, }, { .pme_name = "PC_port0_rd", .pme_desc = "P-cache cacheable FP loads to the first port (general purpose load path to D-cache and P-cache via MS pipeline)", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x10, }, { .pme_name = "SI_snoop", .pme_desc = "Counts snoops from remote processor(s) including RTS, RTSR, RTO, RTOR, RS, RSR, RTSM, and WS", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x11, }, { .pme_name = "SI_ciq_flow", .pme_desc = "Counts system clock cycles when the flow control (PauseOut) signal is asserted", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x12, }, { .pme_name = "SI_owned", .pme_desc = "Counts events where owned_in is asserted on bus requests from the local processor", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x13, }, { .pme_name = "SW_count0", .pme_desc = "Counts software-generated occurrences of 'sethi %hi(0xfc000), %g0' instruction", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x14, }, { .pme_name = "IU_Stat_Br_miss_taken", .pme_desc = "Retired branches that were predicted to be taken, but in fact were not taken", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x15, }, { .pme_name = "IU_Stat_Br_Count_taken", .pme_desc = "Retired taken branches", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x16, }, { .pme_name = "Dispatch0_rs_mispred", .pme_desc = "I-buffer is empty due to a Return Address Stack misprediction", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x4, }, { .pme_name = "FA_pipe_completion", .pme_desc = "Instructions that complete execution on the FPG ALU pipelines", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x18, }, /* PIC1 events common to all UltraSPARC-III/III+/IIIi processors */ { .pme_name = "IC_miss_cancelled", .pme_desc = "I-cache misses cancelled due to mis-speculation, recycle, or other events", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x3, }, { .pme_name = "Re_FPU_bypass", .pme_desc = "Stall due to recirculation when an FPU bypass condition that does not have a direct bypass path occurs", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x5, }, { .pme_name = "Re_DC_miss", .pme_desc = "Stall due to loads that miss D-cache and get recirculated", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x6, }, { .pme_name = "Re_EC_miss", .pme_desc = "Stall due to loads that miss L2-cache and get recirculated", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x7, }, { .pme_name = "IC_miss", .pme_desc = "I-cache misses, including fetches from mis-speculated execution paths which are later cancelled", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x8, }, { .pme_name = "DC_rd_miss", .pme_desc = "Recirculated loads that miss the D-cache", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x9, }, { .pme_name = "DC_wr_miss", .pme_desc = "D-cache store accesses that miss D-cache", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xa, }, { .pme_name = "Rstall_FP_use", .pme_desc = "R-stage stall for an event that the next instruction to be executed depends on the result of a preceeding floating-point instruction in the pipeline that is not yet available", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xb, }, { .pme_name = "EC_misses", .pme_desc = "E-cache misses", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xc, }, { .pme_name = "EC_ic_miss", .pme_desc = "L2-cache read misses from I-cache requests", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xf, }, { .pme_name = "Re_PC_miss", .pme_desc = "Stall due to recirculation when a prefetch cache miss occurs on a prefetch predicted second load", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x10, }, { .pme_name = "ITLB_miss", .pme_desc = "I-TLB miss traps taken", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x11, }, { .pme_name = "DTLB_miss", .pme_desc = "Memory reference instructions which trap due to D-TLB miss", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x12, }, { .pme_name = "WC_miss", .pme_desc = "W-cache misses", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x13, }, { .pme_name = "WC_snoop_cb", .pme_desc = "W-cache copybacks generated by a snoop from a remote processor", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x14, }, { .pme_name = "WC_scrubbed", .pme_desc = "W-cache hits to clean lines", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x15, }, { .pme_name = "WC_wb_wo_read", .pme_desc = "W-cache writebacks not requiring a read", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x16, }, { .pme_name = "PC_soft_hit", .pme_desc = "FP loads that hit a P-cache line that was prefetched by a software-prefetch instruction", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x18, }, { .pme_name = "PC_snoop_inv", .pme_desc = "P-cache invalidates that were generated by a snoop from a remote processor and stores by a local processor", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x19, }, { .pme_name = "PC_hard_hit", .pme_desc = "FP loads that hit a P-cache line that was prefetched by a hardware prefetch", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x1a, }, { .pme_name = "PC_port1_rd", .pme_desc = "P-cache cacheable FP loads to the second port (memory and out-of-pipeline instruction execution loads via the A0 and A1 pipelines)", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x1b, }, { .pme_name = "SW_count1", .pme_desc = "Counts software-generated occurrences of 'sethi %hi(0xfc000), %g0' instruction", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x1c, }, { .pme_name = "IU_Stat_Br_miss_untaken", .pme_desc = "Retired branches that were predicted to be untaken, but in fact were taken", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x1d, }, { .pme_name = "IU_Stat_Br_Count_untaken", .pme_desc = "Retired untaken branches", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x1e, }, { .pme_name = "PC_MS_miss", .pme_desc = "FP loads through the MS pipeline that miss P-cache", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x1f, }, { .pme_name = "Re_RAW_miss", .pme_desc = "Stall due to recirculation when there is a load in the E-stage which has a non-bypassable read-after-write hazard with an earlier store instruction", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x26, }, { .pme_name = "FM_pipe_completion", .pme_desc = "Instructions that complete execution on the FPG Multiply pipelines", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x27, }, /* PIC0 memory controller events common to UltraSPARC-III/III+ processors */ { .pme_name = "MC_reads_0", .pme_desc = "Read requests completed to memory bank 0", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x20, }, { .pme_name = "MC_reads_1", .pme_desc = "Read requests completed to memory bank 1", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x21, }, { .pme_name = "MC_reads_2", .pme_desc = "Read requests completed to memory bank 2", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x22, }, { .pme_name = "MC_reads_3", .pme_desc = "Read requests completed to memory bank 3", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x23, }, { .pme_name = "MC_stalls_0", .pme_desc = "Clock cycles that requests were stalled in the MCU queues because bank 0 was busy with a previous request", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x24, }, { .pme_name = "MC_stalls_2", .pme_desc = "Clock cycles that requests were stalled in the MCU queues because bank 2 was busy with a previous request", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x25, }, /* PIC1 memory controller events common to all UltraSPARC-III/III+ processors */ { .pme_name = "MC_writes_0", .pme_desc = "Write requests completed to memory bank 0", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x20, }, { .pme_name = "MC_writes_1", .pme_desc = "Write requests completed to memory bank 1", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x21, }, { .pme_name = "MC_writes_2", .pme_desc = "Write requests completed to memory bank 2", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x22, }, { .pme_name = "MC_writes_3", .pme_desc = "Write requests completed to memory bank 3", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x23, }, { .pme_name = "MC_stalls_1", .pme_desc = "Clock cycles that requests were stalled in the MCU queues because bank 1 was busy with a previous request", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x24, }, { .pme_name = "MC_stalls_3", .pme_desc = "Clock cycles that requests were stalled in the MCU queues because bank 3 was busy with a previous request", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x25, }, }; #define PME_ULTRA3_EVENT_COUNT (sizeof(ultra3_pe)/sizeof(pme_sparc_entry_t)) papi-5.5.1/src/libpfm-3.y/lib/ppc970mp_events.h0000644000307100002310000044544113013651450021020 0ustar yarkhangraduate/****************************/ /* THIS IS OPEN SOURCE CODE */ /****************************/ #ifndef __PPC970MP_EVENTS_H__ #define __PPC970MP_EVENTS_H__ /* * File: ppc970mp_events.h * CVS: * Author: Corey Ashford * cjashfor@us.ibm.com * Mods: * * * (C) Copyright IBM Corporation, 2007. All Rights Reserved. * Contributed by Corey Ashford * * Note: This code was automatically generated and should not be modified by * hand. * */ #define PPC970MP_PME_PM_LSU_REJECT_RELOAD_CDF 0 #define PPC970MP_PME_PM_MRK_LSU_SRQ_INST_VALID 1 #define PPC970MP_PME_PM_FPU1_SINGLE 2 #define PPC970MP_PME_PM_FPU0_STALL3 3 #define PPC970MP_PME_PM_TB_BIT_TRANS 4 #define PPC970MP_PME_PM_GPR_MAP_FULL_CYC 5 #define PPC970MP_PME_PM_MRK_ST_CMPL 6 #define PPC970MP_PME_PM_FPU0_STF 7 #define PPC970MP_PME_PM_FPU1_FMA 8 #define PPC970MP_PME_PM_LSU1_FLUSH_ULD 9 #define PPC970MP_PME_PM_MRK_INST_FIN 10 #define PPC970MP_PME_PM_MRK_LSU0_FLUSH_UST 11 #define PPC970MP_PME_PM_LSU_LRQ_S0_ALLOC 12 #define PPC970MP_PME_PM_FPU_FDIV 13 #define PPC970MP_PME_PM_FPU0_FULL_CYC 14 #define PPC970MP_PME_PM_FPU_SINGLE 15 #define PPC970MP_PME_PM_FPU0_FMA 16 #define PPC970MP_PME_PM_MRK_LSU1_FLUSH_ULD 17 #define PPC970MP_PME_PM_LSU1_FLUSH_LRQ 18 #define PPC970MP_PME_PM_DTLB_MISS 19 #define PPC970MP_PME_PM_CMPLU_STALL_FXU 20 #define PPC970MP_PME_PM_MRK_ST_MISS_L1 21 #define PPC970MP_PME_PM_EXT_INT 22 #define PPC970MP_PME_PM_MRK_LSU1_FLUSH_LRQ 23 #define PPC970MP_PME_PM_MRK_ST_GPS 24 #define PPC970MP_PME_PM_GRP_DISP_SUCCESS 25 #define PPC970MP_PME_PM_LSU1_LDF 26 #define PPC970MP_PME_PM_LSU0_SRQ_STFWD 27 #define PPC970MP_PME_PM_CR_MAP_FULL_CYC 28 #define PPC970MP_PME_PM_MRK_LSU0_FLUSH_ULD 29 #define PPC970MP_PME_PM_LSU_DERAT_MISS 30 #define PPC970MP_PME_PM_FPU0_SINGLE 31 #define PPC970MP_PME_PM_FPU1_FDIV 32 #define PPC970MP_PME_PM_FPU1_FEST 33 #define PPC970MP_PME_PM_FPU0_FRSP_FCONV 34 #define PPC970MP_PME_PM_GCT_EMPTY_SRQ_FULL 35 #define PPC970MP_PME_PM_MRK_ST_CMPL_INT 36 #define PPC970MP_PME_PM_FLUSH_BR_MPRED 37 #define PPC970MP_PME_PM_FXU_FIN 38 #define PPC970MP_PME_PM_FPU_STF 39 #define PPC970MP_PME_PM_DSLB_MISS 40 #define PPC970MP_PME_PM_FXLS1_FULL_CYC 41 #define PPC970MP_PME_PM_CMPLU_STALL_FPU 42 #define PPC970MP_PME_PM_LSU_LMQ_LHR_MERGE 43 #define PPC970MP_PME_PM_MRK_STCX_FAIL 44 #define PPC970MP_PME_PM_FXU0_BUSY_FXU1_IDLE 45 #define PPC970MP_PME_PM_CMPLU_STALL_LSU 46 #define PPC970MP_PME_PM_MRK_DATA_FROM_L25_SHR 47 #define PPC970MP_PME_PM_LSU_FLUSH_ULD 48 #define PPC970MP_PME_PM_MRK_BRU_FIN 49 #define PPC970MP_PME_PM_IERAT_XLATE_WR 50 #define PPC970MP_PME_PM_GCT_EMPTY_BR_MPRED 51 #define PPC970MP_PME_PM_LSU0_BUSY 52 #define PPC970MP_PME_PM_DATA_FROM_MEM 53 #define PPC970MP_PME_PM_FPR_MAP_FULL_CYC 54 #define PPC970MP_PME_PM_FPU1_FULL_CYC 55 #define PPC970MP_PME_PM_FPU0_FIN 56 #define PPC970MP_PME_PM_GRP_BR_REDIR 57 #define PPC970MP_PME_PM_GCT_EMPTY_IC_MISS 58 #define PPC970MP_PME_PM_THRESH_TIMEO 59 #define PPC970MP_PME_PM_FPU_FSQRT 60 #define PPC970MP_PME_PM_MRK_LSU0_FLUSH_LRQ 61 #define PPC970MP_PME_PM_PMC1_OVERFLOW 62 #define PPC970MP_PME_PM_FXLS0_FULL_CYC 63 #define PPC970MP_PME_PM_FPU0_ALL 64 #define PPC970MP_PME_PM_DATA_TABLEWALK_CYC 65 #define PPC970MP_PME_PM_FPU0_FEST 66 #define PPC970MP_PME_PM_DATA_FROM_L25_MOD 67 #define PPC970MP_PME_PM_LSU0_REJECT_ERAT_MISS 68 #define PPC970MP_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 69 #define PPC970MP_PME_PM_LSU0_REJECT_RELOAD_CDF 70 #define PPC970MP_PME_PM_FPU_FEST 71 #define PPC970MP_PME_PM_0INST_FETCH 72 #define PPC970MP_PME_PM_LD_MISS_L1_LSU0 73 #define PPC970MP_PME_PM_LSU1_REJECT_RELOAD_CDF 74 #define PPC970MP_PME_PM_L1_PREF 75 #define PPC970MP_PME_PM_FPU1_STALL3 76 #define PPC970MP_PME_PM_BRQ_FULL_CYC 77 #define PPC970MP_PME_PM_PMC8_OVERFLOW 78 #define PPC970MP_PME_PM_PMC7_OVERFLOW 79 #define PPC970MP_PME_PM_WORK_HELD 80 #define PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU0 81 #define PPC970MP_PME_PM_FXU_IDLE 82 #define PPC970MP_PME_PM_INST_CMPL 83 #define PPC970MP_PME_PM_LSU1_FLUSH_UST 84 #define PPC970MP_PME_PM_LSU0_FLUSH_ULD 85 #define PPC970MP_PME_PM_LSU_FLUSH 86 #define PPC970MP_PME_PM_INST_FROM_L2 87 #define PPC970MP_PME_PM_LSU1_REJECT_LMQ_FULL 88 #define PPC970MP_PME_PM_PMC2_OVERFLOW 89 #define PPC970MP_PME_PM_FPU0_DENORM 90 #define PPC970MP_PME_PM_FPU1_FMOV_FEST 91 #define PPC970MP_PME_PM_INST_FETCH_CYC 92 #define PPC970MP_PME_PM_GRP_DISP_REJECT 93 #define PPC970MP_PME_PM_LSU_LDF 94 #define PPC970MP_PME_PM_INST_DISP 95 #define PPC970MP_PME_PM_DATA_FROM_L25_SHR 96 #define PPC970MP_PME_PM_L1_DCACHE_RELOAD_VALID 97 #define PPC970MP_PME_PM_MRK_GRP_ISSUED 98 #define PPC970MP_PME_PM_FPU_FMA 99 #define PPC970MP_PME_PM_MRK_CRU_FIN 100 #define PPC970MP_PME_PM_CMPLU_STALL_REJECT 101 #define PPC970MP_PME_PM_MRK_LSU1_FLUSH_UST 102 #define PPC970MP_PME_PM_MRK_FXU_FIN 103 #define PPC970MP_PME_PM_LSU1_REJECT_ERAT_MISS 104 #define PPC970MP_PME_PM_BR_ISSUED 105 #define PPC970MP_PME_PM_PMC4_OVERFLOW 106 #define PPC970MP_PME_PM_EE_OFF 107 #define PPC970MP_PME_PM_INST_FROM_L25_MOD 108 #define PPC970MP_PME_PM_CMPLU_STALL_ERAT_MISS 109 #define PPC970MP_PME_PM_ITLB_MISS 110 #define PPC970MP_PME_PM_FXU1_BUSY_FXU0_IDLE 111 #define PPC970MP_PME_PM_GRP_DISP_VALID 112 #define PPC970MP_PME_PM_MRK_GRP_DISP 113 #define PPC970MP_PME_PM_LSU_FLUSH_UST 114 #define PPC970MP_PME_PM_FXU1_FIN 115 #define PPC970MP_PME_PM_GRP_CMPL 116 #define PPC970MP_PME_PM_FPU_FRSP_FCONV 117 #define PPC970MP_PME_PM_MRK_LSU0_FLUSH_SRQ 118 #define PPC970MP_PME_PM_CMPLU_STALL_OTHER 119 #define PPC970MP_PME_PM_LSU_LMQ_FULL_CYC 120 #define PPC970MP_PME_PM_ST_REF_L1_LSU0 121 #define PPC970MP_PME_PM_LSU0_DERAT_MISS 122 #define PPC970MP_PME_PM_LSU_SRQ_SYNC_CYC 123 #define PPC970MP_PME_PM_FPU_STALL3 124 #define PPC970MP_PME_PM_LSU_REJECT_ERAT_MISS 125 #define PPC970MP_PME_PM_MRK_DATA_FROM_L2 126 #define PPC970MP_PME_PM_LSU0_FLUSH_SRQ 127 #define PPC970MP_PME_PM_FPU0_FMOV_FEST 128 #define PPC970MP_PME_PM_IOPS_CMPL 129 #define PPC970MP_PME_PM_LD_REF_L1_LSU0 130 #define PPC970MP_PME_PM_LSU1_FLUSH_SRQ 131 #define PPC970MP_PME_PM_CMPLU_STALL_DIV 132 #define PPC970MP_PME_PM_GRP_BR_MPRED 133 #define PPC970MP_PME_PM_LSU_LMQ_S0_ALLOC 134 #define PPC970MP_PME_PM_LSU0_REJECT_LMQ_FULL 135 #define PPC970MP_PME_PM_ST_REF_L1 136 #define PPC970MP_PME_PM_MRK_VMX_FIN 137 #define PPC970MP_PME_PM_LSU_SRQ_EMPTY_CYC 138 #define PPC970MP_PME_PM_FPU1_STF 139 #define PPC970MP_PME_PM_RUN_CYC 140 #define PPC970MP_PME_PM_LSU_LMQ_S0_VALID 141 #define PPC970MP_PME_PM_LSU0_LDF 142 #define PPC970MP_PME_PM_LSU_LRQ_S0_VALID 143 #define PPC970MP_PME_PM_PMC3_OVERFLOW 144 #define PPC970MP_PME_PM_MRK_IMR_RELOAD 145 #define PPC970MP_PME_PM_MRK_GRP_TIMEO 146 #define PPC970MP_PME_PM_FPU_FMOV_FEST 147 #define PPC970MP_PME_PM_GRP_DISP_BLK_SB_CYC 148 #define PPC970MP_PME_PM_XER_MAP_FULL_CYC 149 #define PPC970MP_PME_PM_ST_MISS_L1 150 #define PPC970MP_PME_PM_STOP_COMPLETION 151 #define PPC970MP_PME_PM_MRK_GRP_CMPL 152 #define PPC970MP_PME_PM_ISLB_MISS 153 #define PPC970MP_PME_PM_SUSPENDED 154 #define PPC970MP_PME_PM_CYC 155 #define PPC970MP_PME_PM_LD_MISS_L1_LSU1 156 #define PPC970MP_PME_PM_STCX_FAIL 157 #define PPC970MP_PME_PM_LSU1_SRQ_STFWD 158 #define PPC970MP_PME_PM_GRP_DISP 159 #define PPC970MP_PME_PM_L2_PREF 160 #define PPC970MP_PME_PM_FPU1_DENORM 161 #define PPC970MP_PME_PM_DATA_FROM_L2 162 #define PPC970MP_PME_PM_FPU0_FPSCR 163 #define PPC970MP_PME_PM_MRK_DATA_FROM_L25_MOD 164 #define PPC970MP_PME_PM_FPU0_FSQRT 165 #define PPC970MP_PME_PM_LD_REF_L1 166 #define PPC970MP_PME_PM_MRK_L1_RELOAD_VALID 167 #define PPC970MP_PME_PM_1PLUS_PPC_CMPL 168 #define PPC970MP_PME_PM_INST_FROM_L1 169 #define PPC970MP_PME_PM_EE_OFF_EXT_INT 170 #define PPC970MP_PME_PM_PMC6_OVERFLOW 171 #define PPC970MP_PME_PM_LSU_LRQ_FULL_CYC 172 #define PPC970MP_PME_PM_IC_PREF_INSTALL 173 #define PPC970MP_PME_PM_DC_PREF_OUT_OF_STREAMS 174 #define PPC970MP_PME_PM_MRK_LSU1_FLUSH_SRQ 175 #define PPC970MP_PME_PM_GCT_FULL_CYC 176 #define PPC970MP_PME_PM_INST_FROM_MEM 177 #define PPC970MP_PME_PM_FLUSH_LSU_BR_MPRED 178 #define PPC970MP_PME_PM_FXU_BUSY 179 #define PPC970MP_PME_PM_ST_REF_L1_LSU1 180 #define PPC970MP_PME_PM_MRK_LD_MISS_L1 181 #define PPC970MP_PME_PM_L1_WRITE_CYC 182 #define PPC970MP_PME_PM_LSU1_BUSY 183 #define PPC970MP_PME_PM_LSU_REJECT_LMQ_FULL 184 #define PPC970MP_PME_PM_CMPLU_STALL_FDIV 185 #define PPC970MP_PME_PM_FPU_ALL 186 #define PPC970MP_PME_PM_LSU_SRQ_S0_ALLOC 187 #define PPC970MP_PME_PM_INST_FROM_L25_SHR 188 #define PPC970MP_PME_PM_GRP_MRK 189 #define PPC970MP_PME_PM_BR_MPRED_CR 190 #define PPC970MP_PME_PM_DC_PREF_STREAM_ALLOC 191 #define PPC970MP_PME_PM_FPU1_FIN 192 #define PPC970MP_PME_PM_LSU_REJECT_SRQ 193 #define PPC970MP_PME_PM_BR_MPRED_TA 194 #define PPC970MP_PME_PM_CRQ_FULL_CYC 195 #define PPC970MP_PME_PM_LD_MISS_L1 196 #define PPC970MP_PME_PM_INST_FROM_PREF 197 #define PPC970MP_PME_PM_STCX_PASS 198 #define PPC970MP_PME_PM_DC_INV_L2 199 #define PPC970MP_PME_PM_LSU_SRQ_FULL_CYC 200 #define PPC970MP_PME_PM_LSU0_FLUSH_LRQ 201 #define PPC970MP_PME_PM_LSU_SRQ_S0_VALID 202 #define PPC970MP_PME_PM_LARX_LSU0 203 #define PPC970MP_PME_PM_GCT_EMPTY_CYC 204 #define PPC970MP_PME_PM_FPU1_ALL 205 #define PPC970MP_PME_PM_FPU1_FSQRT 206 #define PPC970MP_PME_PM_FPU_FIN 207 #define PPC970MP_PME_PM_LSU_SRQ_STFWD 208 #define PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU1 209 #define PPC970MP_PME_PM_FXU0_FIN 210 #define PPC970MP_PME_PM_MRK_FPU_FIN 211 #define PPC970MP_PME_PM_PMC5_OVERFLOW 212 #define PPC970MP_PME_PM_SNOOP_TLBIE 213 #define PPC970MP_PME_PM_FPU1_FRSP_FCONV 214 #define PPC970MP_PME_PM_FPU0_FDIV 215 #define PPC970MP_PME_PM_LD_REF_L1_LSU1 216 #define PPC970MP_PME_PM_HV_CYC 217 #define PPC970MP_PME_PM_LR_CTR_MAP_FULL_CYC 218 #define PPC970MP_PME_PM_FPU_DENORM 219 #define PPC970MP_PME_PM_LSU0_REJECT_SRQ 220 #define PPC970MP_PME_PM_LSU1_REJECT_SRQ 221 #define PPC970MP_PME_PM_LSU1_DERAT_MISS 222 #define PPC970MP_PME_PM_IC_PREF_REQ 223 #define PPC970MP_PME_PM_MRK_LSU_FIN 224 #define PPC970MP_PME_PM_MRK_DATA_FROM_MEM 225 #define PPC970MP_PME_PM_CMPLU_STALL_DCACHE_MISS 226 #define PPC970MP_PME_PM_LSU0_FLUSH_UST 227 #define PPC970MP_PME_PM_LSU_FLUSH_LRQ 228 #define PPC970MP_PME_PM_LSU_FLUSH_SRQ 229 static const int ppc970mp_event_ids[][PPC970MP_NUM_EVENT_COUNTERS] = { [ PPC970MP_PME_PM_LSU_REJECT_RELOAD_CDF ] = { -1, -1, -1, -1, -1, 66, -1, -1 }, [ PPC970MP_PME_PM_MRK_LSU_SRQ_INST_VALID ] = { -1, -1, 61, 61, -1, -1, 60, 61 }, [ PPC970MP_PME_PM_FPU1_SINGLE ] = { 23, 22, -1, -1, 23, 22, -1, -1 }, [ PPC970MP_PME_PM_FPU0_STALL3 ] = { 15, 14, -1, -1, 15, 14, -1, -1 }, [ PPC970MP_PME_PM_TB_BIT_TRANS ] = { -1, -1, -1, -1, -1, -1, -1, 67 }, [ PPC970MP_PME_PM_GPR_MAP_FULL_CYC ] = { -1, -1, 27, 28, -1, -1, 27, 27 }, [ PPC970MP_PME_PM_MRK_ST_CMPL ] = { 78, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_FPU0_STF ] = { 16, 15, -1, -1, 16, 15, -1, -1 }, [ PPC970MP_PME_PM_FPU1_FMA ] = { 20, 19, -1, -1, 20, 19, -1, -1 }, [ PPC970MP_PME_PM_LSU1_FLUSH_ULD ] = { 57, 56, -1, -1, 58, 55, -1, -1 }, [ PPC970MP_PME_PM_MRK_INST_FIN ] = { -1, -1, -1, -1, -1, -1, 50, -1 }, [ PPC970MP_PME_PM_MRK_LSU0_FLUSH_UST ] = { -1, -1, 56, 56, -1, -1, 55, 55 }, [ PPC970MP_PME_PM_LSU_LRQ_S0_ALLOC ] = { 65, 65, -1, -1, 66, 64, -1, -1 }, [ PPC970MP_PME_PM_FPU_FDIV ] = { 27, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_FPU0_FULL_CYC ] = { 13, 12, -1, -1, 13, 12, -1, -1 }, [ PPC970MP_PME_PM_FPU_SINGLE ] = { -1, -1, -1, -1, 27, -1, -1, -1 }, [ PPC970MP_PME_PM_FPU0_FMA ] = { 11, 10, -1, -1, 11, 10, -1, -1 }, [ PPC970MP_PME_PM_MRK_LSU1_FLUSH_ULD ] = { -1, -1, 59, 59, -1, -1, 58, 58 }, [ PPC970MP_PME_PM_LSU1_FLUSH_LRQ ] = { 55, 54, -1, -1, 56, 53, -1, -1 }, [ PPC970MP_PME_PM_DTLB_MISS ] = { 6, 5, -1, -1, 6, 5, -1, -1 }, [ PPC970MP_PME_PM_CMPLU_STALL_FXU ] = { -1, -1, -1, -1, 85, -1, -1, -1 }, [ PPC970MP_PME_PM_MRK_ST_MISS_L1 ] = { 79, 75, -1, -1, 76, 76, -1, -1 }, [ PPC970MP_PME_PM_EXT_INT ] = { -1, -1, -1, -1, -1, -1, -1, 10 }, [ PPC970MP_PME_PM_MRK_LSU1_FLUSH_LRQ ] = { -1, -1, 57, 57, -1, -1, 56, 56 }, [ PPC970MP_PME_PM_MRK_ST_GPS ] = { -1, -1, -1, -1, -1, 75, -1, -1 }, [ PPC970MP_PME_PM_GRP_DISP_SUCCESS ] = { -1, -1, -1, -1, 33, -1, -1, -1 }, [ PPC970MP_PME_PM_LSU1_LDF ] = { -1, -1, 42, 40, -1, -1, 40, 41 }, [ PPC970MP_PME_PM_LSU0_SRQ_STFWD ] = { 53, 52, -1, -1, 54, 51, -1, -1 }, [ PPC970MP_PME_PM_CR_MAP_FULL_CYC ] = { 1, 1, -1, -1, 2, 1, -1, -1 }, [ PPC970MP_PME_PM_MRK_LSU0_FLUSH_ULD ] = { -1, -1, 55, 55, -1, -1, 54, 54 }, [ PPC970MP_PME_PM_LSU_DERAT_MISS ] = { -1, -1, -1, -1, -1, 62, -1, -1 }, [ PPC970MP_PME_PM_FPU0_SINGLE ] = { 14, 13, -1, -1, 14, 13, -1, -1 }, [ PPC970MP_PME_PM_FPU1_FDIV ] = { 19, 18, -1, -1, 19, 18, -1, -1 }, [ PPC970MP_PME_PM_FPU1_FEST ] = { -1, -1, 17, 18, -1, -1, 17, 18 }, [ PPC970MP_PME_PM_FPU0_FRSP_FCONV ] = { -1, -1, 16, 17, -1, -1, 16, 17 }, [ PPC970MP_PME_PM_GCT_EMPTY_SRQ_FULL ] = { -1, 27, -1, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_MRK_ST_CMPL_INT ] = { -1, -1, 62, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_FLUSH_BR_MPRED ] = { -1, -1, 10, 11, -1, -1, 10, 11 }, [ PPC970MP_PME_PM_FXU_FIN ] = { -1, -1, 26, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_FPU_STF ] = { -1, -1, -1, -1, -1, 26, -1, -1 }, [ PPC970MP_PME_PM_DSLB_MISS ] = { 5, 4, -1, -1, 5, 4, -1, -1 }, [ PPC970MP_PME_PM_FXLS1_FULL_CYC ] = { -1, -1, 23, 24, -1, -1, 23, 24 }, [ PPC970MP_PME_PM_CMPLU_STALL_FPU ] = { -1, -1, -1, -1, -1, -1, 67, -1 }, [ PPC970MP_PME_PM_LSU_LMQ_LHR_MERGE ] = { -1, -1, 45, 43, -1, -1, 43, 45 }, [ PPC970MP_PME_PM_MRK_STCX_FAIL ] = { 77, 74, -1, -1, 75, 74, -1, -1 }, [ PPC970MP_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { -1, -1, -1, -1, -1, -1, 24, -1 }, [ PPC970MP_PME_PM_CMPLU_STALL_LSU ] = { -1, -1, -1, -1, 84, -1, -1, -1 }, [ PPC970MP_PME_PM_MRK_DATA_FROM_L25_SHR ] = { -1, -1, -1, -1, 92, -1, -1, -1 }, [ PPC970MP_PME_PM_LSU_FLUSH_ULD ] = { 64, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_MRK_BRU_FIN ] = { -1, 70, -1, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_IERAT_XLATE_WR ] = { -1, -1, 70, 67, -1, -1, 72, 68 }, [ PPC970MP_PME_PM_GCT_EMPTY_BR_MPRED ] = { -1, -1, -1, -1, -1, -1, 71, -1 }, [ PPC970MP_PME_PM_LSU0_BUSY ] = { 85, 80, -1, -1, 81, 81, -1, -1 }, [ PPC970MP_PME_PM_DATA_FROM_MEM ] = { -1, 87, -1, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_FPR_MAP_FULL_CYC ] = { 7, 6, -1, -1, 7, 6, -1, -1 }, [ PPC970MP_PME_PM_FPU1_FULL_CYC ] = { 22, 21, -1, -1, 22, 21, -1, -1 }, [ PPC970MP_PME_PM_FPU0_FIN ] = { -1, -1, 13, 14, -1, -1, 13, 14 }, [ PPC970MP_PME_PM_GRP_BR_REDIR ] = { 31, 30, -1, -1, 31, 30, -1, -1 }, [ PPC970MP_PME_PM_GCT_EMPTY_IC_MISS ] = { -1, -1, -1, -1, 88, -1, -1, -1 }, [ PPC970MP_PME_PM_THRESH_TIMEO ] = { -1, 82, -1, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_FPU_FSQRT ] = { -1, -1, -1, -1, -1, 25, -1, -1 }, [ PPC970MP_PME_PM_MRK_LSU0_FLUSH_LRQ ] = { -1, -1, 53, 53, -1, -1, 52, 52 }, [ PPC970MP_PME_PM_PMC1_OVERFLOW ] = { -1, 76, -1, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_FXLS0_FULL_CYC ] = { -1, -1, 22, 23, -1, -1, 22, 23 }, [ PPC970MP_PME_PM_FPU0_ALL ] = { 8, 7, -1, -1, 8, 7, -1, -1 }, [ PPC970MP_PME_PM_DATA_TABLEWALK_CYC ] = { 4, 3, -1, -1, 4, 3, -1, -1 }, [ PPC970MP_PME_PM_FPU0_FEST ] = { -1, -1, 12, 13, -1, -1, 12, 13 }, [ PPC970MP_PME_PM_DATA_FROM_L25_MOD ] = { -1, -1, -1, -1, -1, 87, -1, -1 }, [ PPC970MP_PME_PM_LSU0_REJECT_ERAT_MISS ] = { 49, 48, -1, -1, 50, 47, -1, -1 }, [ PPC970MP_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { -1, 64, 48, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_LSU0_REJECT_RELOAD_CDF ] = { 51, 50, -1, -1, 52, 49, -1, -1 }, [ PPC970MP_PME_PM_FPU_FEST ] = { -1, -1, 21, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_0INST_FETCH ] = { -1, -1, -1, 0, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_LD_MISS_L1_LSU0 ] = { -1, -1, 37, 35, -1, -1, 35, 35 }, [ PPC970MP_PME_PM_LSU1_REJECT_RELOAD_CDF ] = { 61, 60, -1, -1, 62, 59, -1, -1 }, [ PPC970MP_PME_PM_L1_PREF ] = { -1, -1, 33, 32, -1, -1, 32, 32 }, [ PPC970MP_PME_PM_FPU1_STALL3 ] = { 24, 23, -1, -1, 24, 23, -1, -1 }, [ PPC970MP_PME_PM_BRQ_FULL_CYC ] = { 0, 0, -1, -1, 1, 0, -1, -1 }, [ PPC970MP_PME_PM_PMC8_OVERFLOW ] = { 80, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_PMC7_OVERFLOW ] = { -1, -1, -1, -1, -1, -1, -1, 62 }, [ PPC970MP_PME_PM_WORK_HELD ] = { -1, 83, -1, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU0 ] = { 75, 72, -1, -1, 73, 72, -1, -1 }, [ PPC970MP_PME_PM_FXU_IDLE ] = { -1, -1, -1, -1, 28, -1, -1, -1 }, [ PPC970MP_PME_PM_INST_CMPL ] = { 36, 36, 30, 30, 38, 35, 30, 30 }, [ PPC970MP_PME_PM_LSU1_FLUSH_UST ] = { 58, 57, -1, -1, 59, 56, -1, -1 }, [ PPC970MP_PME_PM_LSU0_FLUSH_ULD ] = { 47, 46, -1, -1, 48, 45, -1, -1 }, [ PPC970MP_PME_PM_LSU_FLUSH ] = { -1, -1, 43, 41, -1, -1, 41, 42 }, [ PPC970MP_PME_PM_INST_FROM_L2 ] = { 39, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_LSU1_REJECT_LMQ_FULL ] = { 60, 59, -1, -1, 61, 58, -1, -1 }, [ PPC970MP_PME_PM_PMC2_OVERFLOW ] = { -1, -1, 64, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_FPU0_DENORM ] = { 9, 8, -1, -1, 9, 8, -1, -1 }, [ PPC970MP_PME_PM_FPU1_FMOV_FEST ] = { -1, -1, 19, 20, -1, -1, 19, 20 }, [ PPC970MP_PME_PM_INST_FETCH_CYC ] = { 90, 86, -1, -1, 90, 85, -1, -1 }, [ PPC970MP_PME_PM_GRP_DISP_REJECT ] = { 32, 32, -1, -1, 32, 31, -1, 29 }, [ PPC970MP_PME_PM_LSU_LDF ] = { -1, -1, -1, -1, -1, -1, -1, 43 }, [ PPC970MP_PME_PM_INST_DISP ] = { 37, 37, -1, -1, 39, 36, -1, -1 }, [ PPC970MP_PME_PM_DATA_FROM_L25_SHR ] = { -1, -1, -1, -1, 91, -1, -1, -1 }, [ PPC970MP_PME_PM_L1_DCACHE_RELOAD_VALID ] = { -1, -1, 32, 31, -1, -1, 31, 31 }, [ PPC970MP_PME_PM_MRK_GRP_ISSUED ] = { -1, -1, -1, -1, -1, 70, -1, -1 }, [ PPC970MP_PME_PM_FPU_FMA ] = { -1, 25, -1, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_MRK_CRU_FIN ] = { -1, -1, -1, 50, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_CMPLU_STALL_REJECT ] = { -1, -1, -1, -1, -1, -1, 69, -1 }, [ PPC970MP_PME_PM_MRK_LSU1_FLUSH_UST ] = { -1, -1, 60, 60, -1, -1, 59, 59 }, [ PPC970MP_PME_PM_MRK_FXU_FIN ] = { -1, -1, -1, -1, -1, 69, -1, -1 }, [ PPC970MP_PME_PM_LSU1_REJECT_ERAT_MISS ] = { 59, 58, -1, -1, 60, 57, -1, -1 }, [ PPC970MP_PME_PM_BR_ISSUED ] = { -1, -1, 0, 1, -1, -1, 0, 0 }, [ PPC970MP_PME_PM_PMC4_OVERFLOW ] = { -1, -1, -1, -1, 77, -1, -1, -1 }, [ PPC970MP_PME_PM_EE_OFF ] = { -1, -1, 8, 9, -1, -1, 8, 8 }, [ PPC970MP_PME_PM_INST_FROM_L25_MOD ] = { -1, -1, -1, -1, -1, 37, -1, -1 }, [ PPC970MP_PME_PM_CMPLU_STALL_ERAT_MISS ] = { -1, -1, -1, -1, -1, -1, 70, -1 }, [ PPC970MP_PME_PM_ITLB_MISS ] = { 41, 40, -1, -1, 42, 39, -1, -1 }, [ PPC970MP_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { -1, -1, -1, 26, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_GRP_DISP_VALID ] = { 33, 33, -1, -1, 34, 32, -1, -1 }, [ PPC970MP_PME_PM_MRK_GRP_DISP ] = { 72, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_LSU_FLUSH_UST ] = { -1, 63, -1, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_FXU1_FIN ] = { -1, -1, 25, 27, -1, -1, 26, 26 }, [ PPC970MP_PME_PM_GRP_CMPL ] = { -1, -1, -1, -1, -1, -1, 28, -1 }, [ PPC970MP_PME_PM_FPU_FRSP_FCONV ] = { -1, -1, -1, -1, -1, -1, 21, -1 }, [ PPC970MP_PME_PM_MRK_LSU0_FLUSH_SRQ ] = { -1, -1, 54, 54, -1, -1, 53, 53 }, [ PPC970MP_PME_PM_CMPLU_STALL_OTHER ] = { 88, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_LSU_LMQ_FULL_CYC ] = { -1, -1, 44, 42, -1, -1, 42, 44 }, [ PPC970MP_PME_PM_ST_REF_L1_LSU0 ] = { -1, -1, 67, 64, -1, -1, 64, 64 }, [ PPC970MP_PME_PM_LSU0_DERAT_MISS ] = { 44, 43, -1, -1, 45, 42, -1, -1 }, [ PPC970MP_PME_PM_LSU_SRQ_SYNC_CYC ] = { -1, -1, 51, 49, -1, -1, 48, 50 }, [ PPC970MP_PME_PM_FPU_STALL3 ] = { -1, 26, -1, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_LSU_REJECT_ERAT_MISS ] = { -1, -1, -1, -1, 68, -1, -1, -1 }, [ PPC970MP_PME_PM_MRK_DATA_FROM_L2 ] = { 71, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_LSU0_FLUSH_SRQ ] = { 46, 45, -1, -1, 47, 44, -1, -1 }, [ PPC970MP_PME_PM_FPU0_FMOV_FEST ] = { -1, -1, 14, 15, -1, -1, 14, 15 }, [ PPC970MP_PME_PM_IOPS_CMPL ] = { 91, -1, -1, 68, -1, 86, 73, 69 }, [ PPC970MP_PME_PM_LD_REF_L1_LSU0 ] = { -1, -1, 39, 37, -1, -1, 37, 38 }, [ PPC970MP_PME_PM_LSU1_FLUSH_SRQ ] = { 56, 55, -1, -1, 57, 54, -1, -1 }, [ PPC970MP_PME_PM_CMPLU_STALL_DIV ] = { -1, -1, -1, -1, -1, -1, 68, -1 }, [ PPC970MP_PME_PM_GRP_BR_MPRED ] = { 30, 29, -1, -1, 30, 29, -1, -1 }, [ PPC970MP_PME_PM_LSU_LMQ_S0_ALLOC ] = { -1, -1, 46, 44, -1, -1, 44, 46 }, [ PPC970MP_PME_PM_LSU0_REJECT_LMQ_FULL ] = { 50, 49, -1, -1, 51, 48, -1, -1 }, [ PPC970MP_PME_PM_ST_REF_L1 ] = { -1, -1, -1, -1, -1, -1, 63, -1 }, [ PPC970MP_PME_PM_MRK_VMX_FIN ] = { -1, -1, 63, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_LSU_SRQ_EMPTY_CYC ] = { -1, -1, -1, 47, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_FPU1_STF ] = { 25, 24, -1, -1, 25, 24, -1, -1 }, [ PPC970MP_PME_PM_RUN_CYC ] = { 81, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_LSU_LMQ_S0_VALID ] = { -1, -1, 47, 45, -1, -1, 45, 47 }, [ PPC970MP_PME_PM_LSU0_LDF ] = { -1, -1, 41, 39, -1, -1, 39, 40 }, [ PPC970MP_PME_PM_LSU_LRQ_S0_VALID ] = { 66, 66, -1, -1, 67, 65, -1, -1 }, [ PPC970MP_PME_PM_PMC3_OVERFLOW ] = { -1, -1, -1, 62, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_MRK_IMR_RELOAD ] = { 73, 71, -1, -1, 72, 71, -1, -1 }, [ PPC970MP_PME_PM_MRK_GRP_TIMEO ] = { -1, -1, -1, -1, 71, -1, -1, -1 }, [ PPC970MP_PME_PM_FPU_FMOV_FEST ] = { -1, -1, -1, -1, -1, -1, -1, 22 }, [ PPC970MP_PME_PM_GRP_DISP_BLK_SB_CYC ] = { -1, -1, 28, 29, -1, -1, 29, 28 }, [ PPC970MP_PME_PM_XER_MAP_FULL_CYC ] = { 87, 84, -1, -1, 83, 83, -1, -1 }, [ PPC970MP_PME_PM_ST_MISS_L1 ] = { -1, -1, 66, 63, -1, -1, 62, 63 }, [ PPC970MP_PME_PM_STOP_COMPLETION ] = { -1, -1, 65, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_MRK_GRP_CMPL ] = { -1, -1, -1, 51, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_ISLB_MISS ] = { 40, 39, -1, -1, 41, 38, -1, -1 }, [ PPC970MP_PME_PM_SUSPENDED ] = { 86, 81, 69, 66, 82, 82, 66, 66 }, [ PPC970MP_PME_PM_CYC ] = { 2, 2, 4, 5, 3, 2, 4, 4 }, [ PPC970MP_PME_PM_LD_MISS_L1_LSU1 ] = { -1, -1, 38, 36, -1, -1, 36, 36 }, [ PPC970MP_PME_PM_STCX_FAIL ] = { 83, 78, -1, -1, 79, 79, -1, -1 }, [ PPC970MP_PME_PM_LSU1_SRQ_STFWD ] = { 63, 62, -1, -1, 64, 61, -1, -1 }, [ PPC970MP_PME_PM_GRP_DISP ] = { -1, 31, -1, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_L2_PREF ] = { -1, -1, 35, 34, -1, -1, 34, 34 }, [ PPC970MP_PME_PM_FPU1_DENORM ] = { 18, 17, -1, -1, 18, 17, -1, -1 }, [ PPC970MP_PME_PM_DATA_FROM_L2 ] = { 3, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_FPU0_FPSCR ] = { -1, -1, 15, 16, -1, -1, 15, 16 }, [ PPC970MP_PME_PM_MRK_DATA_FROM_L25_MOD ] = { -1, -1, -1, -1, -1, 88, -1, -1 }, [ PPC970MP_PME_PM_FPU0_FSQRT ] = { 12, 11, -1, -1, 12, 11, -1, -1 }, [ PPC970MP_PME_PM_LD_REF_L1 ] = { -1, -1, -1, -1, -1, -1, -1, 37 }, [ PPC970MP_PME_PM_MRK_L1_RELOAD_VALID ] = { -1, -1, 52, 52, -1, -1, 51, 51 }, [ PPC970MP_PME_PM_1PLUS_PPC_CMPL ] = { -1, -1, -1, -1, 0, -1, -1, -1 }, [ PPC970MP_PME_PM_INST_FROM_L1 ] = { 38, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_EE_OFF_EXT_INT ] = { -1, -1, 9, 10, -1, -1, 9, 9 }, [ PPC970MP_PME_PM_PMC6_OVERFLOW ] = { -1, -1, -1, -1, -1, -1, 61, -1 }, [ PPC970MP_PME_PM_LSU_LRQ_FULL_CYC ] = { -1, -1, 49, 46, -1, -1, 46, 48 }, [ PPC970MP_PME_PM_IC_PREF_INSTALL ] = { 34, 34, -1, -1, 36, 33, -1, -1 }, [ PPC970MP_PME_PM_DC_PREF_OUT_OF_STREAMS ] = { -1, -1, 6, 7, -1, -1, 6, 6 }, [ PPC970MP_PME_PM_MRK_LSU1_FLUSH_SRQ ] = { -1, -1, 58, 58, -1, -1, 57, 57 }, [ PPC970MP_PME_PM_GCT_FULL_CYC ] = { 29, 28, -1, -1, 29, 28, -1, -1 }, [ PPC970MP_PME_PM_INST_FROM_MEM ] = { -1, 38, -1, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_FLUSH_LSU_BR_MPRED ] = { -1, -1, 11, 12, -1, -1, 11, 12 }, [ PPC970MP_PME_PM_FXU_BUSY ] = { -1, -1, -1, -1, -1, 27, -1, -1 }, [ PPC970MP_PME_PM_ST_REF_L1_LSU1 ] = { -1, -1, 68, 65, -1, -1, 65, 65 }, [ PPC970MP_PME_PM_MRK_LD_MISS_L1 ] = { 74, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_L1_WRITE_CYC ] = { -1, -1, 34, 33, -1, -1, 33, 33 }, [ PPC970MP_PME_PM_LSU1_BUSY ] = { 89, 85, -1, -1, 89, 84, -1, -1 }, [ PPC970MP_PME_PM_LSU_REJECT_LMQ_FULL ] = { -1, 67, -1, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_CMPLU_STALL_FDIV ] = { -1, -1, -1, -1, 87, -1, -1, -1 }, [ PPC970MP_PME_PM_FPU_ALL ] = { -1, -1, -1, -1, 26, -1, -1, -1 }, [ PPC970MP_PME_PM_LSU_SRQ_S0_ALLOC ] = { 68, 68, -1, -1, 69, 67, -1, -1 }, [ PPC970MP_PME_PM_INST_FROM_L25_SHR ] = { -1, -1, -1, -1, 40, -1, -1, -1 }, [ PPC970MP_PME_PM_GRP_MRK ] = { -1, -1, -1, -1, 35, -1, -1, -1 }, [ PPC970MP_PME_PM_BR_MPRED_CR ] = { -1, -1, 1, 2, -1, -1, 1, 1 }, [ PPC970MP_PME_PM_DC_PREF_STREAM_ALLOC ] = { -1, -1, 7, 8, -1, -1, 7, 7 }, [ PPC970MP_PME_PM_FPU1_FIN ] = { -1, -1, 18, 19, -1, -1, 18, 19 }, [ PPC970MP_PME_PM_LSU_REJECT_SRQ ] = { 67, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_BR_MPRED_TA ] = { -1, -1, 2, 3, -1, -1, 2, 2 }, [ PPC970MP_PME_PM_CRQ_FULL_CYC ] = { -1, -1, 3, 4, -1, -1, 3, 3 }, [ PPC970MP_PME_PM_LD_MISS_L1 ] = { -1, -1, 36, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_INST_FROM_PREF ] = { -1, -1, 31, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_STCX_PASS ] = { 84, 79, -1, -1, 80, 80, -1, -1 }, [ PPC970MP_PME_PM_DC_INV_L2 ] = { -1, -1, 5, 6, -1, -1, 5, 5 }, [ PPC970MP_PME_PM_LSU_SRQ_FULL_CYC ] = { -1, -1, 50, 48, -1, -1, 47, 49 }, [ PPC970MP_PME_PM_LSU0_FLUSH_LRQ ] = { 45, 44, -1, -1, 46, 43, -1, -1 }, [ PPC970MP_PME_PM_LSU_SRQ_S0_VALID ] = { 69, 69, -1, -1, 70, 68, -1, -1 }, [ PPC970MP_PME_PM_LARX_LSU0 ] = { 42, 41, -1, -1, 43, 40, -1, -1 }, [ PPC970MP_PME_PM_GCT_EMPTY_CYC ] = { 28, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_FPU1_ALL ] = { 17, 16, -1, -1, 17, 16, -1, -1 }, [ PPC970MP_PME_PM_FPU1_FSQRT ] = { 21, 20, -1, -1, 21, 20, -1, -1 }, [ PPC970MP_PME_PM_FPU_FIN ] = { -1, -1, -1, 22, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_LSU_SRQ_STFWD ] = { 70, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU1 ] = { 76, 73, -1, -1, 74, 73, -1, -1 }, [ PPC970MP_PME_PM_FXU0_FIN ] = { -1, -1, 24, 25, -1, -1, 25, 25 }, [ PPC970MP_PME_PM_MRK_FPU_FIN ] = { -1, -1, -1, -1, -1, -1, 49, -1 }, [ PPC970MP_PME_PM_PMC5_OVERFLOW ] = { -1, -1, -1, -1, -1, 77, -1, -1 }, [ PPC970MP_PME_PM_SNOOP_TLBIE ] = { 82, 77, -1, -1, 78, 78, -1, -1 }, [ PPC970MP_PME_PM_FPU1_FRSP_FCONV ] = { -1, -1, 20, 21, -1, -1, 20, 21 }, [ PPC970MP_PME_PM_FPU0_FDIV ] = { 10, 9, -1, -1, 10, 9, -1, -1 }, [ PPC970MP_PME_PM_LD_REF_L1_LSU1 ] = { -1, -1, 40, 38, -1, -1, 38, 39 }, [ PPC970MP_PME_PM_HV_CYC ] = { -1, -1, 29, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_LR_CTR_MAP_FULL_CYC ] = { 43, 42, -1, -1, 44, 41, -1, -1 }, [ PPC970MP_PME_PM_FPU_DENORM ] = { 26, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_LSU0_REJECT_SRQ ] = { 52, 51, -1, -1, 53, 50, -1, -1 }, [ PPC970MP_PME_PM_LSU1_REJECT_SRQ ] = { 62, 61, -1, -1, 63, 60, -1, -1 }, [ PPC970MP_PME_PM_LSU1_DERAT_MISS ] = { 54, 53, -1, -1, 55, 52, -1, -1 }, [ PPC970MP_PME_PM_IC_PREF_REQ ] = { 35, 35, -1, -1, 37, 34, -1, -1 }, [ PPC970MP_PME_PM_MRK_LSU_FIN ] = { -1, -1, -1, -1, -1, -1, -1, 60 }, [ PPC970MP_PME_PM_MRK_DATA_FROM_MEM ] = { -1, 88, -1, -1, -1, -1, -1, -1 }, [ PPC970MP_PME_PM_CMPLU_STALL_DCACHE_MISS ] = { -1, -1, -1, -1, 86, -1, -1, -1 }, [ PPC970MP_PME_PM_LSU0_FLUSH_UST ] = { 48, 47, -1, -1, 49, 46, -1, -1 }, [ PPC970MP_PME_PM_LSU_FLUSH_LRQ ] = { -1, -1, -1, -1, -1, 63, -1, -1 }, [ PPC970MP_PME_PM_LSU_FLUSH_SRQ ] = { -1, -1, -1, -1, 65, -1, -1, -1 } }; static const unsigned long long ppc970mp_group_vecs[][PPC970MP_NUM_GROUP_VEC] = { [ PPC970MP_PME_PM_LSU_REJECT_RELOAD_CDF ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_MRK_LSU_SRQ_INST_VALID ] = { 0x0000000800000000ULL }, [ PPC970MP_PME_PM_FPU1_SINGLE ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_FPU0_STALL3 ] = { 0x0000000000002000ULL }, [ PPC970MP_PME_PM_TB_BIT_TRANS ] = { 0x0000000000080000ULL }, [ PPC970MP_PME_PM_GPR_MAP_FULL_CYC ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_MRK_ST_CMPL ] = { 0x0000000800000000ULL }, [ PPC970MP_PME_PM_FPU0_STF ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_FPU1_FMA ] = { 0x0000000000000400ULL }, [ PPC970MP_PME_PM_LSU1_FLUSH_ULD ] = { 0x0000000000008000ULL }, [ PPC970MP_PME_PM_MRK_INST_FIN ] = { 0x0004000200000000ULL }, [ PPC970MP_PME_PM_MRK_LSU0_FLUSH_UST ] = { 0x0000001000000000ULL }, [ PPC970MP_PME_PM_LSU_LRQ_S0_ALLOC ] = { 0x0000000010000000ULL }, [ PPC970MP_PME_PM_FPU_FDIV ] = { 0x0000100000900010ULL }, [ PPC970MP_PME_PM_FPU0_FULL_CYC ] = { 0x0000000000000080ULL }, [ PPC970MP_PME_PM_FPU_SINGLE ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_FPU0_FMA ] = { 0x0000000000000400ULL }, [ PPC970MP_PME_PM_MRK_LSU1_FLUSH_ULD ] = { 0x0000001000000000ULL }, [ PPC970MP_PME_PM_LSU1_FLUSH_LRQ ] = { 0x0000000000004000ULL }, [ PPC970MP_PME_PM_DTLB_MISS ] = { 0x0000000010600000ULL }, [ PPC970MP_PME_PM_CMPLU_STALL_FXU ] = { 0x0000080000000000ULL }, [ PPC970MP_PME_PM_MRK_ST_MISS_L1 ] = { 0x0000001000000000ULL }, [ PPC970MP_PME_PM_EXT_INT ] = { 0x0000000000000200ULL }, [ PPC970MP_PME_PM_MRK_LSU1_FLUSH_LRQ ] = { 0x0000002000000000ULL }, [ PPC970MP_PME_PM_MRK_ST_GPS ] = { 0x0000000800000000ULL }, [ PPC970MP_PME_PM_GRP_DISP_SUCCESS ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_LSU1_LDF ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_LSU0_SRQ_STFWD ] = { 0x0000000000020000ULL }, [ PPC970MP_PME_PM_CR_MAP_FULL_CYC ] = { 0x0000000000000040ULL }, [ PPC970MP_PME_PM_MRK_LSU0_FLUSH_ULD ] = { 0x0000001000000000ULL }, [ PPC970MP_PME_PM_LSU_DERAT_MISS ] = { 0x0000040100000000ULL }, [ PPC970MP_PME_PM_FPU0_SINGLE ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_FPU1_FDIV ] = { 0x0000000000000400ULL }, [ PPC970MP_PME_PM_FPU1_FEST ] = { 0x0000000000001000ULL }, [ PPC970MP_PME_PM_FPU0_FRSP_FCONV ] = { 0x0000000000000400ULL }, [ PPC970MP_PME_PM_GCT_EMPTY_SRQ_FULL ] = { 0x0000080000000000ULL }, [ PPC970MP_PME_PM_MRK_ST_CMPL_INT ] = { 0x0000000800000000ULL }, [ PPC970MP_PME_PM_FLUSH_BR_MPRED ] = { 0x0000200000000000ULL }, [ PPC970MP_PME_PM_FXU_FIN ] = { 0x0000084000100000ULL }, [ PPC970MP_PME_PM_FPU_STF ] = { 0x0000000000800020ULL }, [ PPC970MP_PME_PM_DSLB_MISS ] = { 0x0000000004000000ULL }, [ PPC970MP_PME_PM_FXLS1_FULL_CYC ] = { 0x0000008000000080ULL }, [ PPC970MP_PME_PM_CMPLU_STALL_FPU ] = { 0x0000100000000000ULL }, [ PPC970MP_PME_PM_LSU_LMQ_LHR_MERGE ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_MRK_STCX_FAIL ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { 0x0000004000000000ULL }, [ PPC970MP_PME_PM_CMPLU_STALL_LSU ] = { 0x0000020000000000ULL }, [ PPC970MP_PME_PM_MRK_DATA_FROM_L25_SHR ] = { 0x0004000000000000ULL }, [ PPC970MP_PME_PM_LSU_FLUSH_ULD ] = { 0x0000000000000008ULL }, [ PPC970MP_PME_PM_MRK_BRU_FIN ] = { 0x0000000400000000ULL }, [ PPC970MP_PME_PM_IERAT_XLATE_WR ] = { 0x0000000080000000ULL }, [ PPC970MP_PME_PM_GCT_EMPTY_BR_MPRED ] = { 0x0000200000000000ULL }, [ PPC970MP_PME_PM_LSU0_BUSY ] = { 0x0000020003020000ULL }, [ PPC970MP_PME_PM_DATA_FROM_MEM ] = { 0x0003000008000000ULL }, [ PPC970MP_PME_PM_FPR_MAP_FULL_CYC ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_FPU1_FULL_CYC ] = { 0x0000000000000080ULL }, [ PPC970MP_PME_PM_FPU0_FIN ] = { 0x0000000000802800ULL }, [ PPC970MP_PME_PM_GRP_BR_REDIR ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_GCT_EMPTY_IC_MISS ] = { 0x0000200000000000ULL }, [ PPC970MP_PME_PM_THRESH_TIMEO ] = { 0x0000000200000000ULL }, [ PPC970MP_PME_PM_FPU_FSQRT ] = { 0x0000100000100010ULL }, [ PPC970MP_PME_PM_MRK_LSU0_FLUSH_LRQ ] = { 0x0000002000000000ULL }, [ PPC970MP_PME_PM_PMC1_OVERFLOW ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_FXLS0_FULL_CYC ] = { 0x0000008000000080ULL }, [ PPC970MP_PME_PM_FPU0_ALL ] = { 0x0000000000000800ULL }, [ PPC970MP_PME_PM_DATA_TABLEWALK_CYC ] = { 0x0000000020000000ULL }, [ PPC970MP_PME_PM_FPU0_FEST ] = { 0x0000000000001000ULL }, [ PPC970MP_PME_PM_DATA_FROM_L25_MOD ] = { 0x0002400000000000ULL }, [ PPC970MP_PME_PM_LSU0_REJECT_ERAT_MISS ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { 0x0000000000480000ULL }, [ PPC970MP_PME_PM_LSU0_REJECT_RELOAD_CDF ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_FPU_FEST ] = { 0x0000000000000010ULL }, [ PPC970MP_PME_PM_0INST_FETCH ] = { 0x0000010000000000ULL }, [ PPC970MP_PME_PM_LD_MISS_L1_LSU0 ] = { 0x0001000000008000ULL }, [ PPC970MP_PME_PM_LSU1_REJECT_RELOAD_CDF ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_L1_PREF ] = { 0x0000000010000000ULL }, [ PPC970MP_PME_PM_FPU1_STALL3 ] = { 0x0000000000002000ULL }, [ PPC970MP_PME_PM_BRQ_FULL_CYC ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_PMC8_OVERFLOW ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_PMC7_OVERFLOW ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_WORK_HELD ] = { 0x0000000000000200ULL }, [ PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU0 ] = { 0x0000002000000000ULL }, [ PPC970MP_PME_PM_FXU_IDLE ] = { 0x000000c000000000ULL }, [ PPC970MP_PME_PM_INST_CMPL ] = { 0x0007fffbffffffffULL }, [ PPC970MP_PME_PM_LSU1_FLUSH_UST ] = { 0x0000000000010000ULL }, [ PPC970MP_PME_PM_LSU0_FLUSH_ULD ] = { 0x0000000000008000ULL }, [ PPC970MP_PME_PM_LSU_FLUSH ] = { 0x0000020000000000ULL }, [ PPC970MP_PME_PM_INST_FROM_L2 ] = { 0x0000800020000000ULL }, [ PPC970MP_PME_PM_LSU1_REJECT_LMQ_FULL ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_PMC2_OVERFLOW ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_FPU0_DENORM ] = { 0x0000000000001000ULL }, [ PPC970MP_PME_PM_FPU1_FMOV_FEST ] = { 0x0000000000001000ULL }, [ PPC970MP_PME_PM_INST_FETCH_CYC ] = { 0x0000010000000000ULL }, [ PPC970MP_PME_PM_GRP_DISP_REJECT ] = { 0x0000000000000101ULL }, [ PPC970MP_PME_PM_LSU_LDF ] = { 0x0000000000800020ULL }, [ PPC970MP_PME_PM_INST_DISP ] = { 0x0000000100000146ULL }, [ PPC970MP_PME_PM_DATA_FROM_L25_SHR ] = { 0x0002400000000000ULL }, [ PPC970MP_PME_PM_L1_DCACHE_RELOAD_VALID ] = { 0x0000000100040000ULL }, [ PPC970MP_PME_PM_MRK_GRP_ISSUED ] = { 0x0000000200000000ULL }, [ PPC970MP_PME_PM_FPU_FMA ] = { 0x0000100000900010ULL }, [ PPC970MP_PME_PM_MRK_CRU_FIN ] = { 0x0000000400000000ULL }, [ PPC970MP_PME_PM_CMPLU_STALL_REJECT ] = { 0x0000040000000000ULL }, [ PPC970MP_PME_PM_MRK_LSU1_FLUSH_UST ] = { 0x0000001000000000ULL }, [ PPC970MP_PME_PM_MRK_FXU_FIN ] = { 0x0000000400000000ULL }, [ PPC970MP_PME_PM_LSU1_REJECT_ERAT_MISS ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_BR_ISSUED ] = { 0x0000800007000000ULL }, [ PPC970MP_PME_PM_PMC4_OVERFLOW ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_EE_OFF ] = { 0x0000000000000200ULL }, [ PPC970MP_PME_PM_INST_FROM_L25_MOD ] = { 0x0000010000000000ULL }, [ PPC970MP_PME_PM_CMPLU_STALL_ERAT_MISS ] = { 0x0000020000000000ULL }, [ PPC970MP_PME_PM_ITLB_MISS ] = { 0x0000000010200000ULL }, [ PPC970MP_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { 0x0000004000000000ULL }, [ PPC970MP_PME_PM_GRP_DISP_VALID ] = { 0x0000000100000100ULL }, [ PPC970MP_PME_PM_MRK_GRP_DISP ] = { 0x0000000400000000ULL }, [ PPC970MP_PME_PM_LSU_FLUSH_UST ] = { 0x0000000000000008ULL }, [ PPC970MP_PME_PM_FXU1_FIN ] = { 0x0000008000000100ULL }, [ PPC970MP_PME_PM_GRP_CMPL ] = { 0x0000000020080001ULL }, [ PPC970MP_PME_PM_FPU_FRSP_FCONV ] = { 0x0000000000000020ULL }, [ PPC970MP_PME_PM_MRK_LSU0_FLUSH_SRQ ] = { 0x0000002000000000ULL }, [ PPC970MP_PME_PM_CMPLU_STALL_OTHER ] = { 0x0000040000000000ULL }, [ PPC970MP_PME_PM_LSU_LMQ_FULL_CYC ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_ST_REF_L1_LSU0 ] = { 0x0000000000030000ULL }, [ PPC970MP_PME_PM_LSU0_DERAT_MISS ] = { 0x0000000000040000ULL }, [ PPC970MP_PME_PM_LSU_SRQ_SYNC_CYC ] = { 0x0000000040000000ULL }, [ PPC970MP_PME_PM_FPU_STALL3 ] = { 0x0000000000000020ULL }, [ PPC970MP_PME_PM_LSU_REJECT_ERAT_MISS ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_MRK_DATA_FROM_L2 ] = { 0x0004000000000000ULL }, [ PPC970MP_PME_PM_LSU0_FLUSH_SRQ ] = { 0x0000000000004000ULL }, [ PPC970MP_PME_PM_FPU0_FMOV_FEST ] = { 0x0000000000001000ULL }, [ PPC970MP_PME_PM_IOPS_CMPL ] = { 0x0000100000000000ULL }, [ PPC970MP_PME_PM_LD_REF_L1_LSU0 ] = { 0x0000000000008000ULL }, [ PPC970MP_PME_PM_LSU1_FLUSH_SRQ ] = { 0x0000000000004000ULL }, [ PPC970MP_PME_PM_CMPLU_STALL_DIV ] = { 0x0000080000000000ULL }, [ PPC970MP_PME_PM_GRP_BR_MPRED ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_LSU_LMQ_S0_ALLOC ] = { 0x0000400008000000ULL }, [ PPC970MP_PME_PM_LSU0_REJECT_LMQ_FULL ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_ST_REF_L1 ] = { 0x000000010260000eULL }, [ PPC970MP_PME_PM_MRK_VMX_FIN ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_LSU_SRQ_EMPTY_CYC ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_FPU1_STF ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_RUN_CYC ] = { 0x0000000004000001ULL }, [ PPC970MP_PME_PM_LSU_LMQ_S0_VALID ] = { 0x0000400008000000ULL }, [ PPC970MP_PME_PM_LSU0_LDF ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_LSU_LRQ_S0_VALID ] = { 0x0000000010000000ULL }, [ PPC970MP_PME_PM_PMC3_OVERFLOW ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_MRK_IMR_RELOAD ] = { 0x0000001000000000ULL }, [ PPC970MP_PME_PM_MRK_GRP_TIMEO ] = { 0x0000000800000000ULL }, [ PPC970MP_PME_PM_FPU_FMOV_FEST ] = { 0x0000000000100010ULL }, [ PPC970MP_PME_PM_GRP_DISP_BLK_SB_CYC ] = { 0x0000000000000040ULL }, [ PPC970MP_PME_PM_XER_MAP_FULL_CYC ] = { 0x0000000000000040ULL }, [ PPC970MP_PME_PM_ST_MISS_L1 ] = { 0x0000000000610000ULL }, [ PPC970MP_PME_PM_STOP_COMPLETION ] = { 0x0000000000000201ULL }, [ PPC970MP_PME_PM_MRK_GRP_CMPL ] = { 0x0000000a00000000ULL }, [ PPC970MP_PME_PM_ISLB_MISS ] = { 0x0000000004000000ULL }, [ PPC970MP_PME_PM_SUSPENDED ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_CYC ] = { 0x0007ffffffffffffULL }, [ PPC970MP_PME_PM_LD_MISS_L1_LSU1 ] = { 0x0003000000008000ULL }, [ PPC970MP_PME_PM_STCX_FAIL ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_LSU1_SRQ_STFWD ] = { 0x0000000000020000ULL }, [ PPC970MP_PME_PM_GRP_DISP ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_L2_PREF ] = { 0x0000000010000000ULL }, [ PPC970MP_PME_PM_FPU1_DENORM ] = { 0x0000000000001000ULL }, [ PPC970MP_PME_PM_DATA_FROM_L2 ] = { 0x0003000008000000ULL }, [ PPC970MP_PME_PM_FPU0_FPSCR ] = { 0x0000000000002000ULL }, [ PPC970MP_PME_PM_MRK_DATA_FROM_L25_MOD ] = { 0x0004000000000000ULL }, [ PPC970MP_PME_PM_FPU0_FSQRT ] = { 0x0000000000000800ULL }, [ PPC970MP_PME_PM_LD_REF_L1 ] = { 0x000304004260000eULL }, [ PPC970MP_PME_PM_MRK_L1_RELOAD_VALID ] = { 0x0004000000000000ULL }, [ PPC970MP_PME_PM_1PLUS_PPC_CMPL ] = { 0x0001000000080001ULL }, [ PPC970MP_PME_PM_INST_FROM_L1 ] = { 0x0000010080000000ULL }, [ PPC970MP_PME_PM_EE_OFF_EXT_INT ] = { 0x0000000000000200ULL }, [ PPC970MP_PME_PM_PMC6_OVERFLOW ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_LSU_LRQ_FULL_CYC ] = { 0x0000000000000080ULL }, [ PPC970MP_PME_PM_IC_PREF_INSTALL ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_DC_PREF_OUT_OF_STREAMS ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_MRK_LSU1_FLUSH_SRQ ] = { 0x0000002000000000ULL }, [ PPC970MP_PME_PM_GCT_FULL_CYC ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_INST_FROM_MEM ] = { 0x0000810020000000ULL }, [ PPC970MP_PME_PM_FLUSH_LSU_BR_MPRED ] = { 0x0000020000000000ULL }, [ PPC970MP_PME_PM_FXU_BUSY ] = { 0x000008c000000000ULL }, [ PPC970MP_PME_PM_ST_REF_L1_LSU1 ] = { 0x0000000000030000ULL }, [ PPC970MP_PME_PM_MRK_LD_MISS_L1 ] = { 0x0000000200000000ULL }, [ PPC970MP_PME_PM_L1_WRITE_CYC ] = { 0x0000200000000000ULL }, [ PPC970MP_PME_PM_LSU1_BUSY ] = { 0x0000020000000000ULL }, [ PPC970MP_PME_PM_LSU_REJECT_LMQ_FULL ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_CMPLU_STALL_FDIV ] = { 0x0000100000000000ULL }, [ PPC970MP_PME_PM_FPU_ALL ] = { 0x0000000000000020ULL }, [ PPC970MP_PME_PM_LSU_SRQ_S0_ALLOC ] = { 0x0000000040000000ULL }, [ PPC970MP_PME_PM_INST_FROM_L25_SHR ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_GRP_MRK ] = { 0x0000000600000000ULL }, [ PPC970MP_PME_PM_BR_MPRED_CR ] = { 0x0000800005000000ULL }, [ PPC970MP_PME_PM_DC_PREF_STREAM_ALLOC ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_FPU1_FIN ] = { 0x0000000000802800ULL }, [ PPC970MP_PME_PM_LSU_REJECT_SRQ ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_BR_MPRED_TA ] = { 0x0000a00005000000ULL }, [ PPC970MP_PME_PM_CRQ_FULL_CYC ] = { 0x0000000000000040ULL }, [ PPC970MP_PME_PM_LD_MISS_L1 ] = { 0x0000040043600006ULL }, [ PPC970MP_PME_PM_INST_FROM_PREF ] = { 0x0000810000000000ULL }, [ PPC970MP_PME_PM_STCX_PASS ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_DC_INV_L2 ] = { 0x0000000020010006ULL }, [ PPC970MP_PME_PM_LSU_SRQ_FULL_CYC ] = { 0x0000000000000080ULL }, [ PPC970MP_PME_PM_LSU0_FLUSH_LRQ ] = { 0x0000000000004000ULL }, [ PPC970MP_PME_PM_LSU_SRQ_S0_VALID ] = { 0x0000000040000000ULL }, [ PPC970MP_PME_PM_LARX_LSU0 ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_GCT_EMPTY_CYC ] = { 0x0000200100080200ULL }, [ PPC970MP_PME_PM_FPU1_ALL ] = { 0x0000000000000800ULL }, [ PPC970MP_PME_PM_FPU1_FSQRT ] = { 0x0000000000000800ULL }, [ PPC970MP_PME_PM_FPU_FIN ] = { 0x0000080000100010ULL }, [ PPC970MP_PME_PM_LSU_SRQ_STFWD ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU1 ] = { 0x0000002000000000ULL }, [ PPC970MP_PME_PM_FXU0_FIN ] = { 0x0000008000000100ULL }, [ PPC970MP_PME_PM_MRK_FPU_FIN ] = { 0x0000000400000000ULL }, [ PPC970MP_PME_PM_PMC5_OVERFLOW ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_SNOOP_TLBIE ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_FPU1_FRSP_FCONV ] = { 0x0000000000000400ULL }, [ PPC970MP_PME_PM_FPU0_FDIV ] = { 0x0000000000000400ULL }, [ PPC970MP_PME_PM_LD_REF_L1_LSU1 ] = { 0x0000000000008000ULL }, [ PPC970MP_PME_PM_HV_CYC ] = { 0x0000000020080000ULL }, [ PPC970MP_PME_PM_LR_CTR_MAP_FULL_CYC ] = { 0x0000000000000040ULL }, [ PPC970MP_PME_PM_FPU_DENORM ] = { 0x0000000000000020ULL }, [ PPC970MP_PME_PM_LSU0_REJECT_SRQ ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_LSU1_REJECT_SRQ ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_LSU1_DERAT_MISS ] = { 0x0000000000040000ULL }, [ PPC970MP_PME_PM_IC_PREF_REQ ] = { 0x0000000000000000ULL }, [ PPC970MP_PME_PM_MRK_LSU_FIN ] = { 0x0000000400000000ULL }, [ PPC970MP_PME_PM_MRK_DATA_FROM_MEM ] = { 0x0004000000000000ULL }, [ PPC970MP_PME_PM_CMPLU_STALL_DCACHE_MISS ] = { 0x0000040000000000ULL }, [ PPC970MP_PME_PM_LSU0_FLUSH_UST ] = { 0x0000000000010000ULL }, [ PPC970MP_PME_PM_LSU_FLUSH_LRQ ] = { 0x0000000000000008ULL }, [ PPC970MP_PME_PM_LSU_FLUSH_SRQ ] = { 0x0000000000000008ULL } }; static const pme_power_entry_t ppc970mp_pe[] = { [ PPC970MP_PME_PM_LSU_REJECT_RELOAD_CDF ] = { .pme_name = "PM_LSU_REJECT_RELOAD_CDF", .pme_code = 0x6920, .pme_short_desc = "LSU reject due to reload CDF or tag update collision", .pme_long_desc = "LSU reject due to reload CDF or tag update collision", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_REJECT_RELOAD_CDF], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_REJECT_RELOAD_CDF] }, [ PPC970MP_PME_PM_MRK_LSU_SRQ_INST_VALID ] = { .pme_name = "PM_MRK_LSU_SRQ_INST_VALID", .pme_code = 0x936, .pme_short_desc = "Marked instruction valid in SRQ", .pme_long_desc = "This signal is asserted every cycle when a marked request is resident in the Store Request Queue", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_LSU_SRQ_INST_VALID], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_LSU_SRQ_INST_VALID] }, [ PPC970MP_PME_PM_FPU1_SINGLE ] = { .pme_name = "PM_FPU1_SINGLE", .pme_code = 0x127, .pme_short_desc = "FPU1 executed single precision instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing single precision instruction.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU1_SINGLE], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU1_SINGLE] }, [ PPC970MP_PME_PM_FPU0_STALL3 ] = { .pme_name = "PM_FPU0_STALL3", .pme_code = 0x121, .pme_short_desc = "FPU0 stalled in pipe3", .pme_long_desc = "This signal indicates that fp0 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. ", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU0_STALL3], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU0_STALL3] }, [ PPC970MP_PME_PM_TB_BIT_TRANS ] = { .pme_name = "PM_TB_BIT_TRANS", .pme_code = 0x8005, .pme_short_desc = "Time Base bit transition", .pme_long_desc = "When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 ", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_TB_BIT_TRANS], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_TB_BIT_TRANS] }, [ PPC970MP_PME_PM_GPR_MAP_FULL_CYC ] = { .pme_name = "PM_GPR_MAP_FULL_CYC", .pme_code = 0x335, .pme_short_desc = "Cycles GPR mapper full", .pme_long_desc = "The ISU sends a signal indicating that the gpr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GPR_MAP_FULL_CYC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GPR_MAP_FULL_CYC] }, [ PPC970MP_PME_PM_MRK_ST_CMPL ] = { .pme_name = "PM_MRK_ST_CMPL", .pme_code = 0x1003, .pme_short_desc = "Marked store instruction completed", .pme_long_desc = "A sampled store has completed (data home)", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_ST_CMPL], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_ST_CMPL] }, [ PPC970MP_PME_PM_FPU0_STF ] = { .pme_name = "PM_FPU0_STF", .pme_code = 0x122, .pme_short_desc = "FPU0 executed store instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing a store instruction.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU0_STF], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU0_STF] }, [ PPC970MP_PME_PM_FPU1_FMA ] = { .pme_name = "PM_FPU1_FMA", .pme_code = 0x105, .pme_short_desc = "FPU1 executed multiply-add instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU1_FMA], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU1_FMA] }, [ PPC970MP_PME_PM_LSU1_FLUSH_ULD ] = { .pme_name = "PM_LSU1_FLUSH_ULD", .pme_code = 0x804, .pme_short_desc = "LSU1 unaligned load flushes", .pme_long_desc = "A load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU1_FLUSH_ULD], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU1_FLUSH_ULD] }, [ PPC970MP_PME_PM_MRK_INST_FIN ] = { .pme_name = "PM_MRK_INST_FIN", .pme_code = 0x7005, .pme_short_desc = "Marked instruction finished", .pme_long_desc = "One of the execution units finished a marked instruction. Instructions that finish may not necessary complete", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_INST_FIN], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_INST_FIN] }, [ PPC970MP_PME_PM_MRK_LSU0_FLUSH_UST ] = { .pme_name = "PM_MRK_LSU0_FLUSH_UST", .pme_code = 0x711, .pme_short_desc = "LSU0 marked unaligned store flushes", .pme_long_desc = "A marked store was flushed from unit 0 because it was unaligned", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_LSU0_FLUSH_UST], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_LSU0_FLUSH_UST] }, [ PPC970MP_PME_PM_LSU_LRQ_S0_ALLOC ] = { .pme_name = "PM_LSU_LRQ_S0_ALLOC", .pme_code = 0x826, .pme_short_desc = "LRQ slot 0 allocated", .pme_long_desc = "LRQ slot zero was allocated", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_LRQ_S0_ALLOC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_LRQ_S0_ALLOC] }, [ PPC970MP_PME_PM_FPU_FDIV ] = { .pme_name = "PM_FPU_FDIV", .pme_code = 0x1100, .pme_short_desc = "FPU executed FDIV instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when FPU is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs. Combined Unit 0 + Unit 1", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU_FDIV], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU_FDIV] }, [ PPC970MP_PME_PM_FPU0_FULL_CYC ] = { .pme_name = "PM_FPU0_FULL_CYC", .pme_code = 0x303, .pme_short_desc = "Cycles FPU0 issue queue full", .pme_long_desc = "The issue queue for FPU unit 0 cannot accept any more instructions. Issue is stopped", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU0_FULL_CYC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU0_FULL_CYC] }, [ PPC970MP_PME_PM_FPU_SINGLE ] = { .pme_name = "PM_FPU_SINGLE", .pme_code = 0x5120, .pme_short_desc = "FPU executed single precision instruction", .pme_long_desc = "FPU is executing single precision instruction. Combined Unit 0 + Unit 1", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU_SINGLE], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU_SINGLE] }, [ PPC970MP_PME_PM_FPU0_FMA ] = { .pme_name = "PM_FPU0_FMA", .pme_code = 0x101, .pme_short_desc = "FPU0 executed multiply-add instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU0_FMA], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU0_FMA] }, [ PPC970MP_PME_PM_MRK_LSU1_FLUSH_ULD ] = { .pme_name = "PM_MRK_LSU1_FLUSH_ULD", .pme_code = 0x714, .pme_short_desc = "LSU1 marked unaligned load flushes", .pme_long_desc = "A marked load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_LSU1_FLUSH_ULD], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_LSU1_FLUSH_ULD] }, [ PPC970MP_PME_PM_LSU1_FLUSH_LRQ ] = { .pme_name = "PM_LSU1_FLUSH_LRQ", .pme_code = 0x806, .pme_short_desc = "LSU1 LRQ flushes", .pme_long_desc = "A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU1_FLUSH_LRQ], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU1_FLUSH_LRQ] }, [ PPC970MP_PME_PM_DTLB_MISS ] = { .pme_name = "PM_DTLB_MISS", .pme_code = 0x704, .pme_short_desc = "Data TLB misses", .pme_long_desc = "A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_DTLB_MISS], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_DTLB_MISS] }, [ PPC970MP_PME_PM_CMPLU_STALL_FXU ] = { .pme_name = "PM_CMPLU_STALL_FXU", .pme_code = 0x508b, .pme_short_desc = "Completion stall caused by FXU instruction", .pme_long_desc = "Completion stall caused by FXU instruction", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_CMPLU_STALL_FXU], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_CMPLU_STALL_FXU] }, [ PPC970MP_PME_PM_MRK_ST_MISS_L1 ] = { .pme_name = "PM_MRK_ST_MISS_L1", .pme_code = 0x723, .pme_short_desc = "Marked L1 D cache store misses", .pme_long_desc = "A marked store missed the dcache", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_ST_MISS_L1], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_ST_MISS_L1] }, [ PPC970MP_PME_PM_EXT_INT ] = { .pme_name = "PM_EXT_INT", .pme_code = 0x8002, .pme_short_desc = "External interrupts", .pme_long_desc = "An external interrupt occurred", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_EXT_INT], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_EXT_INT] }, [ PPC970MP_PME_PM_MRK_LSU1_FLUSH_LRQ ] = { .pme_name = "PM_MRK_LSU1_FLUSH_LRQ", .pme_code = 0x716, .pme_short_desc = "LSU1 marked LRQ flushes", .pme_long_desc = "A marked load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_LSU1_FLUSH_LRQ], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_LSU1_FLUSH_LRQ] }, [ PPC970MP_PME_PM_MRK_ST_GPS ] = { .pme_name = "PM_MRK_ST_GPS", .pme_code = 0x6003, .pme_short_desc = "Marked store sent to GPS", .pme_long_desc = "A sampled store has been sent to the memory subsystem", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_ST_GPS], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_ST_GPS] }, [ PPC970MP_PME_PM_GRP_DISP_SUCCESS ] = { .pme_name = "PM_GRP_DISP_SUCCESS", .pme_code = 0x5001, .pme_short_desc = "Group dispatch success", .pme_long_desc = "Number of groups sucessfully dispatched (not rejected)", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GRP_DISP_SUCCESS], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GRP_DISP_SUCCESS] }, [ PPC970MP_PME_PM_LSU1_LDF ] = { .pme_name = "PM_LSU1_LDF", .pme_code = 0x734, .pme_short_desc = "LSU1 executed Floating Point load instruction", .pme_long_desc = "A floating point load was executed from LSU unit 1", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU1_LDF], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU1_LDF] }, [ PPC970MP_PME_PM_LSU0_SRQ_STFWD ] = { .pme_name = "PM_LSU0_SRQ_STFWD", .pme_code = 0x820, .pme_short_desc = "LSU0 SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load on unit 0", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU0_SRQ_STFWD], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU0_SRQ_STFWD] }, [ PPC970MP_PME_PM_CR_MAP_FULL_CYC ] = { .pme_name = "PM_CR_MAP_FULL_CYC", .pme_code = 0x304, .pme_short_desc = "Cycles CR logical operation mapper full", .pme_long_desc = "The ISU sends a signal indicating that the cr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_CR_MAP_FULL_CYC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_CR_MAP_FULL_CYC] }, [ PPC970MP_PME_PM_MRK_LSU0_FLUSH_ULD ] = { .pme_name = "PM_MRK_LSU0_FLUSH_ULD", .pme_code = 0x710, .pme_short_desc = "LSU0 marked unaligned load flushes", .pme_long_desc = "A marked load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_LSU0_FLUSH_ULD], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_LSU0_FLUSH_ULD] }, [ PPC970MP_PME_PM_LSU_DERAT_MISS ] = { .pme_name = "PM_LSU_DERAT_MISS", .pme_code = 0x6700, .pme_short_desc = "DERAT misses", .pme_long_desc = "Total D-ERAT Misses (Unit 0 + Unit 1). Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_DERAT_MISS], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_DERAT_MISS] }, [ PPC970MP_PME_PM_FPU0_SINGLE ] = { .pme_name = "PM_FPU0_SINGLE", .pme_code = 0x123, .pme_short_desc = "FPU0 executed single precision instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing single precision instruction.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU0_SINGLE], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU0_SINGLE] }, [ PPC970MP_PME_PM_FPU1_FDIV ] = { .pme_name = "PM_FPU1_FDIV", .pme_code = 0x104, .pme_short_desc = "FPU1 executed FDIV instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp1 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU1_FDIV], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU1_FDIV] }, [ PPC970MP_PME_PM_FPU1_FEST ] = { .pme_name = "PM_FPU1_FEST", .pme_code = 0x116, .pme_short_desc = "FPU1 executed FEST instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. ", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU1_FEST], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU1_FEST] }, [ PPC970MP_PME_PM_FPU0_FRSP_FCONV ] = { .pme_name = "PM_FPU0_FRSP_FCONV", .pme_code = 0x111, .pme_short_desc = "FPU0 executed FRSP or FCONV instructions", .pme_long_desc = "This signal is active for one cycle when fp0 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU0_FRSP_FCONV], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU0_FRSP_FCONV] }, [ PPC970MP_PME_PM_GCT_EMPTY_SRQ_FULL ] = { .pme_name = "PM_GCT_EMPTY_SRQ_FULL", .pme_code = 0x200b, .pme_short_desc = "GCT empty caused by SRQ full", .pme_long_desc = "GCT empty caused by SRQ full", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GCT_EMPTY_SRQ_FULL], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GCT_EMPTY_SRQ_FULL] }, [ PPC970MP_PME_PM_MRK_ST_CMPL_INT ] = { .pme_name = "PM_MRK_ST_CMPL_INT", .pme_code = 0x3003, .pme_short_desc = "Marked store completed with intervention", .pme_long_desc = "A marked store previously sent to the memory subsystem completed (data home) after requiring intervention", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_ST_CMPL_INT], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_ST_CMPL_INT] }, [ PPC970MP_PME_PM_FLUSH_BR_MPRED ] = { .pme_name = "PM_FLUSH_BR_MPRED", .pme_code = 0x316, .pme_short_desc = "Flush caused by branch mispredict", .pme_long_desc = "Flush caused by branch mispredict", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FLUSH_BR_MPRED], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FLUSH_BR_MPRED] }, [ PPC970MP_PME_PM_FXU_FIN ] = { .pme_name = "PM_FXU_FIN", .pme_code = 0x3330, .pme_short_desc = "FXU produced a result", .pme_long_desc = "The fixed point unit (Unit 0 + Unit 1) finished an instruction. Instructions that finish may not necessary complete.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FXU_FIN], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FXU_FIN] }, [ PPC970MP_PME_PM_FPU_STF ] = { .pme_name = "PM_FPU_STF", .pme_code = 0x6120, .pme_short_desc = "FPU executed store instruction", .pme_long_desc = "FPU is executing a store instruction. Combined Unit 0 + Unit 1", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU_STF], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU_STF] }, [ PPC970MP_PME_PM_DSLB_MISS ] = { .pme_name = "PM_DSLB_MISS", .pme_code = 0x705, .pme_short_desc = "Data SLB misses", .pme_long_desc = "A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_DSLB_MISS], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_DSLB_MISS] }, [ PPC970MP_PME_PM_FXLS1_FULL_CYC ] = { .pme_name = "PM_FXLS1_FULL_CYC", .pme_code = 0x314, .pme_short_desc = "Cycles FXU1/LS1 queue full", .pme_long_desc = "The issue queue for FXU/LSU unit 0 cannot accept any more instructions. Issue is stopped", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FXLS1_FULL_CYC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FXLS1_FULL_CYC] }, [ PPC970MP_PME_PM_CMPLU_STALL_FPU ] = { .pme_name = "PM_CMPLU_STALL_FPU", .pme_code = 0x704b, .pme_short_desc = "Completion stall caused by FPU instruction", .pme_long_desc = "Completion stall caused by FPU instruction", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_CMPLU_STALL_FPU], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_CMPLU_STALL_FPU] }, [ PPC970MP_PME_PM_LSU_LMQ_LHR_MERGE ] = { .pme_name = "PM_LSU_LMQ_LHR_MERGE", .pme_code = 0x935, .pme_short_desc = "LMQ LHR merges", .pme_long_desc = "A dcache miss occured for the same real cache line address as an earlier request already in the Load Miss Queue and was merged into the LMQ entry.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_LMQ_LHR_MERGE], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_LMQ_LHR_MERGE] }, [ PPC970MP_PME_PM_MRK_STCX_FAIL ] = { .pme_name = "PM_MRK_STCX_FAIL", .pme_code = 0x726, .pme_short_desc = "Marked STCX failed", .pme_long_desc = "A marked stcx (stwcx or stdcx) failed", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_STCX_FAIL], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_STCX_FAIL] }, [ PPC970MP_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { .pme_name = "PM_FXU0_BUSY_FXU1_IDLE", .pme_code = 0x7002, .pme_short_desc = "FXU0 busy FXU1 idle", .pme_long_desc = "FXU0 is busy while FXU1 was idle", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FXU0_BUSY_FXU1_IDLE], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FXU0_BUSY_FXU1_IDLE] }, [ PPC970MP_PME_PM_CMPLU_STALL_LSU ] = { .pme_name = "PM_CMPLU_STALL_LSU", .pme_code = 0x504b, .pme_short_desc = "Completion stall caused by LSU instruction", .pme_long_desc = "Completion stall caused by LSU instruction", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_CMPLU_STALL_LSU], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_CMPLU_STALL_LSU] }, [ PPC970MP_PME_PM_MRK_DATA_FROM_L25_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L25_SHR", .pme_code = 0x5937, .pme_short_desc = "Marked data loaded from L2.5 shared", .pme_long_desc = "DL1 was reloaded with shared (T or SL) data from the L2 of a chip on this MCM due to a marked demand load", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_DATA_FROM_L25_SHR], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_DATA_FROM_L25_SHR] }, [ PPC970MP_PME_PM_LSU_FLUSH_ULD ] = { .pme_name = "PM_LSU_FLUSH_ULD", .pme_code = 0x1800, .pme_short_desc = "LRQ unaligned load flushes", .pme_long_desc = "A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_FLUSH_ULD], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_FLUSH_ULD] }, [ PPC970MP_PME_PM_MRK_BRU_FIN ] = { .pme_name = "PM_MRK_BRU_FIN", .pme_code = 0x2005, .pme_short_desc = "Marked instruction BRU processing finished", .pme_long_desc = "The branch unit finished a marked instruction. Instructions that finish may not necessary complete", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_BRU_FIN], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_BRU_FIN] }, [ PPC970MP_PME_PM_IERAT_XLATE_WR ] = { .pme_name = "PM_IERAT_XLATE_WR", .pme_code = 0x430, .pme_short_desc = "Translation written to ierat", .pme_long_desc = "This signal will be asserted each time the I-ERAT is written. This indicates that an ERAT miss has been serviced. ERAT misses will initiate a sequence resulting in the ERAT being written. ERAT misses that are later ignored will not be counted unless the ERAT is written before the instruction stream is changed, This should be a fairly accurate count of ERAT missed (best available).", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_IERAT_XLATE_WR], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_IERAT_XLATE_WR] }, [ PPC970MP_PME_PM_GCT_EMPTY_BR_MPRED ] = { .pme_name = "PM_GCT_EMPTY_BR_MPRED", .pme_code = 0x708c, .pme_short_desc = "GCT empty due to branch mispredict", .pme_long_desc = "GCT empty due to branch mispredict", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GCT_EMPTY_BR_MPRED], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GCT_EMPTY_BR_MPRED] }, [ PPC970MP_PME_PM_LSU0_BUSY ] = { .pme_name = "PM_LSU0_BUSY", .pme_code = 0x823, .pme_short_desc = "LSU0 busy", .pme_long_desc = "LSU unit 0 is busy rejecting instructions", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU0_BUSY], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU0_BUSY] }, [ PPC970MP_PME_PM_DATA_FROM_MEM ] = { .pme_name = "PM_DATA_FROM_MEM", .pme_code = 0x2837, .pme_short_desc = "Data loaded from memory", .pme_long_desc = "Data loaded from memory", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_DATA_FROM_MEM], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_DATA_FROM_MEM] }, [ PPC970MP_PME_PM_FPR_MAP_FULL_CYC ] = { .pme_name = "PM_FPR_MAP_FULL_CYC", .pme_code = 0x301, .pme_short_desc = "Cycles FPR mapper full", .pme_long_desc = "The ISU sends a signal indicating that the FPR mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPR_MAP_FULL_CYC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPR_MAP_FULL_CYC] }, [ PPC970MP_PME_PM_FPU1_FULL_CYC ] = { .pme_name = "PM_FPU1_FULL_CYC", .pme_code = 0x307, .pme_short_desc = "Cycles FPU1 issue queue full", .pme_long_desc = "The issue queue for FPU unit 1 cannot accept any more instructions. Issue is stopped", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU1_FULL_CYC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU1_FULL_CYC] }, [ PPC970MP_PME_PM_FPU0_FIN ] = { .pme_name = "PM_FPU0_FIN", .pme_code = 0x113, .pme_short_desc = "FPU0 produced a result", .pme_long_desc = "fp0 finished, produced a result This only indicates finish, not completion. ", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU0_FIN], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU0_FIN] }, [ PPC970MP_PME_PM_GRP_BR_REDIR ] = { .pme_name = "PM_GRP_BR_REDIR", .pme_code = 0x326, .pme_short_desc = "Group experienced branch redirect", .pme_long_desc = "Group experienced branch redirect", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GRP_BR_REDIR], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GRP_BR_REDIR] }, [ PPC970MP_PME_PM_GCT_EMPTY_IC_MISS ] = { .pme_name = "PM_GCT_EMPTY_IC_MISS", .pme_code = 0x508c, .pme_short_desc = "GCT empty due to I cache miss", .pme_long_desc = "GCT empty due to I cache miss", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GCT_EMPTY_IC_MISS], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GCT_EMPTY_IC_MISS] }, [ PPC970MP_PME_PM_THRESH_TIMEO ] = { .pme_name = "PM_THRESH_TIMEO", .pme_code = 0x2003, .pme_short_desc = "Threshold timeout", .pme_long_desc = "The threshold timer expired", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_THRESH_TIMEO], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_THRESH_TIMEO] }, [ PPC970MP_PME_PM_FPU_FSQRT ] = { .pme_name = "PM_FPU_FSQRT", .pme_code = 0x6100, .pme_short_desc = "FPU executed FSQRT instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when FPU is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU_FSQRT], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU_FSQRT] }, [ PPC970MP_PME_PM_MRK_LSU0_FLUSH_LRQ ] = { .pme_name = "PM_MRK_LSU0_FLUSH_LRQ", .pme_code = 0x712, .pme_short_desc = "LSU0 marked LRQ flushes", .pme_long_desc = "A marked load was flushed by unit 0 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_LSU0_FLUSH_LRQ], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_LSU0_FLUSH_LRQ] }, [ PPC970MP_PME_PM_PMC1_OVERFLOW ] = { .pme_name = "PM_PMC1_OVERFLOW", .pme_code = 0x200a, .pme_short_desc = "PMC1 Overflow", .pme_long_desc = "PMC1 Overflow", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_PMC1_OVERFLOW], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_PMC1_OVERFLOW] }, [ PPC970MP_PME_PM_FXLS0_FULL_CYC ] = { .pme_name = "PM_FXLS0_FULL_CYC", .pme_code = 0x310, .pme_short_desc = "Cycles FXU0/LS0 queue full", .pme_long_desc = "The issue queue for FXU/LSU unit 0 cannot accept any more instructions. Issue is stopped", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FXLS0_FULL_CYC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FXLS0_FULL_CYC] }, [ PPC970MP_PME_PM_FPU0_ALL ] = { .pme_name = "PM_FPU0_ALL", .pme_code = 0x103, .pme_short_desc = "FPU0 executed add", .pme_long_desc = " mult", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU0_ALL], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU0_ALL] }, [ PPC970MP_PME_PM_DATA_TABLEWALK_CYC ] = { .pme_name = "PM_DATA_TABLEWALK_CYC", .pme_code = 0x707, .pme_short_desc = "Cycles doing data tablewalks", .pme_long_desc = "This signal is asserted every cycle when a tablewalk is active. While a tablewalk is active any request attempting to access the TLB will be rejected and retried.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_DATA_TABLEWALK_CYC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_DATA_TABLEWALK_CYC] }, [ PPC970MP_PME_PM_FPU0_FEST ] = { .pme_name = "PM_FPU0_FEST", .pme_code = 0x112, .pme_short_desc = "FPU0 executed FEST instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. ", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU0_FEST], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU0_FEST] }, [ PPC970MP_PME_PM_DATA_FROM_L25_MOD ] = { .pme_name = "PM_DATA_FROM_L25_MOD", .pme_code = 0x6837, .pme_short_desc = "Data loaded from L2.5 modified", .pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a demand load", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_DATA_FROM_L25_MOD], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_DATA_FROM_L25_MOD] }, [ PPC970MP_PME_PM_LSU0_REJECT_ERAT_MISS ] = { .pme_name = "PM_LSU0_REJECT_ERAT_MISS", .pme_code = 0x923, .pme_short_desc = "LSU0 reject due to ERAT miss", .pme_long_desc = "LSU0 reject due to ERAT miss", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU0_REJECT_ERAT_MISS], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU0_REJECT_ERAT_MISS] }, [ PPC970MP_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_LMQ_SRQ_EMPTY_CYC", .pme_code = 0x2002, .pme_short_desc = "Cycles LMQ and SRQ empty", .pme_long_desc = "Cycles when both the LMQ and SRQ are empty (LSU is idle)", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC] }, [ PPC970MP_PME_PM_LSU0_REJECT_RELOAD_CDF ] = { .pme_name = "PM_LSU0_REJECT_RELOAD_CDF", .pme_code = 0x922, .pme_short_desc = "LSU0 reject due to reload CDF or tag update collision", .pme_long_desc = "LSU0 reject due to reload CDF or tag update collision", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU0_REJECT_RELOAD_CDF], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU0_REJECT_RELOAD_CDF] }, [ PPC970MP_PME_PM_FPU_FEST ] = { .pme_name = "PM_FPU_FEST", .pme_code = 0x3110, .pme_short_desc = "FPU executed FEST instruction", .pme_long_desc = "This signal is active for one cycle when executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. Combined Unit 0 + Unit 1.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU_FEST], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU_FEST] }, [ PPC970MP_PME_PM_0INST_FETCH ] = { .pme_name = "PM_0INST_FETCH", .pme_code = 0x442d, .pme_short_desc = "No instructions fetched", .pme_long_desc = "No instructions were fetched this cycles (due to IFU hold, redirect, or icache miss)", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_0INST_FETCH], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_0INST_FETCH] }, [ PPC970MP_PME_PM_LD_MISS_L1_LSU0 ] = { .pme_name = "PM_LD_MISS_L1_LSU0", .pme_code = 0x812, .pme_short_desc = "LSU0 L1 D cache load misses", .pme_long_desc = "A load, executing on unit 0, missed the dcache", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LD_MISS_L1_LSU0], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LD_MISS_L1_LSU0] }, [ PPC970MP_PME_PM_LSU1_REJECT_RELOAD_CDF ] = { .pme_name = "PM_LSU1_REJECT_RELOAD_CDF", .pme_code = 0x926, .pme_short_desc = "LSU1 reject due to reload CDF or tag update collision", .pme_long_desc = "LSU1 reject due to reload CDF or tag update collision", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU1_REJECT_RELOAD_CDF], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU1_REJECT_RELOAD_CDF] }, [ PPC970MP_PME_PM_L1_PREF ] = { .pme_name = "PM_L1_PREF", .pme_code = 0x731, .pme_short_desc = "L1 cache data prefetches", .pme_long_desc = "A request to prefetch data into the L1 was made", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_L1_PREF], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_L1_PREF] }, [ PPC970MP_PME_PM_FPU1_STALL3 ] = { .pme_name = "PM_FPU1_STALL3", .pme_code = 0x125, .pme_short_desc = "FPU1 stalled in pipe3", .pme_long_desc = "This signal indicates that fp1 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. ", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU1_STALL3], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU1_STALL3] }, [ PPC970MP_PME_PM_BRQ_FULL_CYC ] = { .pme_name = "PM_BRQ_FULL_CYC", .pme_code = 0x305, .pme_short_desc = "Cycles branch queue full", .pme_long_desc = "The ISU sends a signal indicating that the issue queue that feeds the ifu br unit cannot accept any more group (queue is full of groups).", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_BRQ_FULL_CYC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_BRQ_FULL_CYC] }, [ PPC970MP_PME_PM_PMC8_OVERFLOW ] = { .pme_name = "PM_PMC8_OVERFLOW", .pme_code = 0x100a, .pme_short_desc = "PMC8 Overflow", .pme_long_desc = "PMC8 Overflow", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_PMC8_OVERFLOW], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_PMC8_OVERFLOW] }, [ PPC970MP_PME_PM_PMC7_OVERFLOW ] = { .pme_name = "PM_PMC7_OVERFLOW", .pme_code = 0x800a, .pme_short_desc = "PMC7 Overflow", .pme_long_desc = "PMC7 Overflow", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_PMC7_OVERFLOW], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_PMC7_OVERFLOW] }, [ PPC970MP_PME_PM_WORK_HELD ] = { .pme_name = "PM_WORK_HELD", .pme_code = 0x2001, .pme_short_desc = "Work held", .pme_long_desc = "RAS Unit has signaled completion to stop and there are groups waiting to complete", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_WORK_HELD], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_WORK_HELD] }, [ PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU0 ] = { .pme_name = "PM_MRK_LD_MISS_L1_LSU0", .pme_code = 0x720, .pme_short_desc = "LSU0 L1 D cache load misses", .pme_long_desc = "A marked load, executing on unit 0, missed the dcache", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU0], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU0] }, [ PPC970MP_PME_PM_FXU_IDLE ] = { .pme_name = "PM_FXU_IDLE", .pme_code = 0x5002, .pme_short_desc = "FXU idle", .pme_long_desc = "FXU0 and FXU1 are both idle", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FXU_IDLE], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FXU_IDLE] }, [ PPC970MP_PME_PM_INST_CMPL ] = { .pme_name = "PM_INST_CMPL", .pme_code = 0x1, .pme_short_desc = "Instructions completed", .pme_long_desc = "Number of Eligible Instructions that completed. ", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_INST_CMPL], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_INST_CMPL] }, [ PPC970MP_PME_PM_LSU1_FLUSH_UST ] = { .pme_name = "PM_LSU1_FLUSH_UST", .pme_code = 0x805, .pme_short_desc = "LSU1 unaligned store flushes", .pme_long_desc = "A store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU1_FLUSH_UST], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU1_FLUSH_UST] }, [ PPC970MP_PME_PM_LSU0_FLUSH_ULD ] = { .pme_name = "PM_LSU0_FLUSH_ULD", .pme_code = 0x800, .pme_short_desc = "LSU0 unaligned load flushes", .pme_long_desc = "A load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU0_FLUSH_ULD], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU0_FLUSH_ULD] }, [ PPC970MP_PME_PM_LSU_FLUSH ] = { .pme_name = "PM_LSU_FLUSH", .pme_code = 0x315, .pme_short_desc = "Flush initiated by LSU", .pme_long_desc = "Flush initiated by LSU", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_FLUSH], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_FLUSH] }, [ PPC970MP_PME_PM_INST_FROM_L2 ] = { .pme_name = "PM_INST_FROM_L2", .pme_code = 0x1426, .pme_short_desc = "Instructions fetched from L2", .pme_long_desc = "An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_INST_FROM_L2], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_INST_FROM_L2] }, [ PPC970MP_PME_PM_LSU1_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU1_REJECT_LMQ_FULL", .pme_code = 0x925, .pme_short_desc = "LSU1 reject due to LMQ full or missed data coming", .pme_long_desc = "LSU1 reject due to LMQ full or missed data coming", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU1_REJECT_LMQ_FULL], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU1_REJECT_LMQ_FULL] }, [ PPC970MP_PME_PM_PMC2_OVERFLOW ] = { .pme_name = "PM_PMC2_OVERFLOW", .pme_code = 0x300a, .pme_short_desc = "PMC2 Overflow", .pme_long_desc = "PMC2 Overflow", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_PMC2_OVERFLOW], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_PMC2_OVERFLOW] }, [ PPC970MP_PME_PM_FPU0_DENORM ] = { .pme_name = "PM_FPU0_DENORM", .pme_code = 0x120, .pme_short_desc = "FPU0 received denormalized data", .pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU0_DENORM], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU0_DENORM] }, [ PPC970MP_PME_PM_FPU1_FMOV_FEST ] = { .pme_name = "PM_FPU1_FMOV_FEST", .pme_code = 0x114, .pme_short_desc = "FPU1 executing FMOV or FEST instructions", .pme_long_desc = "This signal is active for one cycle when fp1 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU1_FMOV_FEST], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU1_FMOV_FEST] }, [ PPC970MP_PME_PM_INST_FETCH_CYC ] = { .pme_name = "PM_INST_FETCH_CYC", .pme_code = 0x424, .pme_short_desc = "Cycles at least 1 instruction fetched", .pme_long_desc = "Asserted each cycle when the IFU sends at least one instruction to the IDU. ", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_INST_FETCH_CYC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_INST_FETCH_CYC] }, [ PPC970MP_PME_PM_GRP_DISP_REJECT ] = { .pme_name = "PM_GRP_DISP_REJECT", .pme_code = 0x324, .pme_short_desc = "Group dispatch rejected", .pme_long_desc = "A group that previously attempted dispatch was rejected.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GRP_DISP_REJECT], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GRP_DISP_REJECT] }, [ PPC970MP_PME_PM_LSU_LDF ] = { .pme_name = "PM_LSU_LDF", .pme_code = 0x8730, .pme_short_desc = "LSU executed Floating Point load instruction", .pme_long_desc = "LSU executed Floating Point load instruction", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_LDF], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_LDF] }, [ PPC970MP_PME_PM_INST_DISP ] = { .pme_name = "PM_INST_DISP", .pme_code = 0x320, .pme_short_desc = "Instructions dispatched", .pme_long_desc = "The ISU sends the number of instructions dispatched.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_INST_DISP], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_INST_DISP] }, [ PPC970MP_PME_PM_DATA_FROM_L25_SHR ] = { .pme_name = "PM_DATA_FROM_L25_SHR", .pme_code = 0x5837, .pme_short_desc = "Data loaded from L2.5 shared", .pme_long_desc = "DL1 was reloaded with shared (T or SL) data from the L2 of a chip on this MCM due to a demand load", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_DATA_FROM_L25_SHR], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_DATA_FROM_L25_SHR] }, [ PPC970MP_PME_PM_L1_DCACHE_RELOAD_VALID ] = { .pme_name = "PM_L1_DCACHE_RELOAD_VALID", .pme_code = 0x834, .pme_short_desc = "L1 reload data source valid", .pme_long_desc = "The data source information is valid", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_L1_DCACHE_RELOAD_VALID], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_L1_DCACHE_RELOAD_VALID] }, [ PPC970MP_PME_PM_MRK_GRP_ISSUED ] = { .pme_name = "PM_MRK_GRP_ISSUED", .pme_code = 0x6005, .pme_short_desc = "Marked group issued", .pme_long_desc = "A sampled instruction was issued", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_GRP_ISSUED], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_GRP_ISSUED] }, [ PPC970MP_PME_PM_FPU_FMA ] = { .pme_name = "PM_FPU_FMA", .pme_code = 0x2100, .pme_short_desc = "FPU executed multiply-add instruction", .pme_long_desc = "This signal is active for one cycle when FPU is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU_FMA], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU_FMA] }, [ PPC970MP_PME_PM_MRK_CRU_FIN ] = { .pme_name = "PM_MRK_CRU_FIN", .pme_code = 0x4005, .pme_short_desc = "Marked instruction CRU processing finished", .pme_long_desc = "The Condition Register Unit finished a marked instruction. Instructions that finish may not necessary complete", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_CRU_FIN], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_CRU_FIN] }, [ PPC970MP_PME_PM_CMPLU_STALL_REJECT ] = { .pme_name = "PM_CMPLU_STALL_REJECT", .pme_code = 0x70cb, .pme_short_desc = "Completion stall caused by reject", .pme_long_desc = "Completion stall caused by reject", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_CMPLU_STALL_REJECT], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_CMPLU_STALL_REJECT] }, [ PPC970MP_PME_PM_MRK_LSU1_FLUSH_UST ] = { .pme_name = "PM_MRK_LSU1_FLUSH_UST", .pme_code = 0x715, .pme_short_desc = "LSU1 marked unaligned store flushes", .pme_long_desc = "A marked store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_LSU1_FLUSH_UST], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_LSU1_FLUSH_UST] }, [ PPC970MP_PME_PM_MRK_FXU_FIN ] = { .pme_name = "PM_MRK_FXU_FIN", .pme_code = 0x6004, .pme_short_desc = "Marked instruction FXU processing finished", .pme_long_desc = "Marked instruction FXU processing finished", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_FXU_FIN], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_FXU_FIN] }, [ PPC970MP_PME_PM_LSU1_REJECT_ERAT_MISS ] = { .pme_name = "PM_LSU1_REJECT_ERAT_MISS", .pme_code = 0x927, .pme_short_desc = "LSU1 reject due to ERAT miss", .pme_long_desc = "LSU1 reject due to ERAT miss", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU1_REJECT_ERAT_MISS], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU1_REJECT_ERAT_MISS] }, [ PPC970MP_PME_PM_BR_ISSUED ] = { .pme_name = "PM_BR_ISSUED", .pme_code = 0x431, .pme_short_desc = "Branches issued", .pme_long_desc = "This signal will be asserted each time the ISU issues a branch instruction. This signal will be asserted each time the ISU selects a branch instruction to issue.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_BR_ISSUED], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_BR_ISSUED] }, [ PPC970MP_PME_PM_PMC4_OVERFLOW ] = { .pme_name = "PM_PMC4_OVERFLOW", .pme_code = 0x500a, .pme_short_desc = "PMC4 Overflow", .pme_long_desc = "PMC4 Overflow", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_PMC4_OVERFLOW], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_PMC4_OVERFLOW] }, [ PPC970MP_PME_PM_EE_OFF ] = { .pme_name = "PM_EE_OFF", .pme_code = 0x333, .pme_short_desc = "Cycles MSR(EE) bit off", .pme_long_desc = "The number of Cycles MSR(EE) bit was off.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_EE_OFF], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_EE_OFF] }, [ PPC970MP_PME_PM_INST_FROM_L25_MOD ] = { .pme_name = "PM_INST_FROM_L25_MOD", .pme_code = 0x6426, .pme_short_desc = "Instruction fetched from L2.5 modified", .pme_long_desc = "Instruction fetched from L2.5 modified", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_INST_FROM_L25_MOD], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_INST_FROM_L25_MOD] }, [ PPC970MP_PME_PM_CMPLU_STALL_ERAT_MISS ] = { .pme_name = "PM_CMPLU_STALL_ERAT_MISS", .pme_code = 0x704c, .pme_short_desc = "Completion stall caused by ERAT miss", .pme_long_desc = "Completion stall caused by ERAT miss", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_CMPLU_STALL_ERAT_MISS], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_CMPLU_STALL_ERAT_MISS] }, [ PPC970MP_PME_PM_ITLB_MISS ] = { .pme_name = "PM_ITLB_MISS", .pme_code = 0x700, .pme_short_desc = "Instruction TLB misses", .pme_long_desc = "A TLB miss for an Instruction Fetch has occurred", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_ITLB_MISS], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_ITLB_MISS] }, [ PPC970MP_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { .pme_name = "PM_FXU1_BUSY_FXU0_IDLE", .pme_code = 0x4002, .pme_short_desc = "FXU1 busy FXU0 idle", .pme_long_desc = "FXU0 was idle while FXU1 was busy", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FXU1_BUSY_FXU0_IDLE], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FXU1_BUSY_FXU0_IDLE] }, [ PPC970MP_PME_PM_GRP_DISP_VALID ] = { .pme_name = "PM_GRP_DISP_VALID", .pme_code = 0x323, .pme_short_desc = "Group dispatch valid", .pme_long_desc = "Dispatch has been attempted for a valid group. Some groups may be rejected. The total number of successful dispatches is the number of dispatch valid minus dispatch reject.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GRP_DISP_VALID], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GRP_DISP_VALID] }, [ PPC970MP_PME_PM_MRK_GRP_DISP ] = { .pme_name = "PM_MRK_GRP_DISP", .pme_code = 0x1002, .pme_short_desc = "Marked group dispatched", .pme_long_desc = "A group containing a sampled instruction was dispatched", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_GRP_DISP], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_GRP_DISP] }, [ PPC970MP_PME_PM_LSU_FLUSH_UST ] = { .pme_name = "PM_LSU_FLUSH_UST", .pme_code = 0x2800, .pme_short_desc = "SRQ unaligned store flushes", .pme_long_desc = "A store was flushed because it was unaligned", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_FLUSH_UST], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_FLUSH_UST] }, [ PPC970MP_PME_PM_FXU1_FIN ] = { .pme_name = "PM_FXU1_FIN", .pme_code = 0x336, .pme_short_desc = "FXU1 produced a result", .pme_long_desc = "The Fixed Point unit 1 finished an instruction and produced a result", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FXU1_FIN], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FXU1_FIN] }, [ PPC970MP_PME_PM_GRP_CMPL ] = { .pme_name = "PM_GRP_CMPL", .pme_code = 0x7003, .pme_short_desc = "Group completed", .pme_long_desc = "A group completed. Microcoded instructions that span multiple groups will generate this event once per group.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GRP_CMPL], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GRP_CMPL] }, [ PPC970MP_PME_PM_FPU_FRSP_FCONV ] = { .pme_name = "PM_FPU_FRSP_FCONV", .pme_code = 0x7110, .pme_short_desc = "FPU executed FRSP or FCONV instructions", .pme_long_desc = "This signal is active for one cycle when executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU_FRSP_FCONV], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU_FRSP_FCONV] }, [ PPC970MP_PME_PM_MRK_LSU0_FLUSH_SRQ ] = { .pme_name = "PM_MRK_LSU0_FLUSH_SRQ", .pme_code = 0x713, .pme_short_desc = "LSU0 marked SRQ flushes", .pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_LSU0_FLUSH_SRQ], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_LSU0_FLUSH_SRQ] }, [ PPC970MP_PME_PM_CMPLU_STALL_OTHER ] = { .pme_name = "PM_CMPLU_STALL_OTHER", .pme_code = 0x100b, .pme_short_desc = "Completion stall caused by other reason", .pme_long_desc = "Completion stall caused by other reason", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_CMPLU_STALL_OTHER], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_CMPLU_STALL_OTHER] }, [ PPC970MP_PME_PM_LSU_LMQ_FULL_CYC ] = { .pme_name = "PM_LSU_LMQ_FULL_CYC", .pme_code = 0x837, .pme_short_desc = "Cycles LMQ full", .pme_long_desc = "The LMQ was full", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_LMQ_FULL_CYC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_LMQ_FULL_CYC] }, [ PPC970MP_PME_PM_ST_REF_L1_LSU0 ] = { .pme_name = "PM_ST_REF_L1_LSU0", .pme_code = 0x811, .pme_short_desc = "LSU0 L1 D cache store references", .pme_long_desc = "A store executed on unit 0", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_ST_REF_L1_LSU0], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_ST_REF_L1_LSU0] }, [ PPC970MP_PME_PM_LSU0_DERAT_MISS ] = { .pme_name = "PM_LSU0_DERAT_MISS", .pme_code = 0x702, .pme_short_desc = "LSU0 DERAT misses", .pme_long_desc = "A data request (load or store) from LSU Unit 0 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU0_DERAT_MISS], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU0_DERAT_MISS] }, [ PPC970MP_PME_PM_LSU_SRQ_SYNC_CYC ] = { .pme_name = "PM_LSU_SRQ_SYNC_CYC", .pme_code = 0x735, .pme_short_desc = "SRQ sync duration", .pme_long_desc = "This signal is asserted every cycle when a sync is in the SRQ.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_SRQ_SYNC_CYC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_SRQ_SYNC_CYC] }, [ PPC970MP_PME_PM_FPU_STALL3 ] = { .pme_name = "PM_FPU_STALL3", .pme_code = 0x2120, .pme_short_desc = "FPU stalled in pipe3", .pme_long_desc = "FPU has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. Combined Unit 0 + Unit 1", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU_STALL3], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU_STALL3] }, [ PPC970MP_PME_PM_LSU_REJECT_ERAT_MISS ] = { .pme_name = "PM_LSU_REJECT_ERAT_MISS", .pme_code = 0x5920, .pme_short_desc = "LSU reject due to ERAT miss", .pme_long_desc = "LSU reject due to ERAT miss", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_REJECT_ERAT_MISS], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_REJECT_ERAT_MISS] }, [ PPC970MP_PME_PM_MRK_DATA_FROM_L2 ] = { .pme_name = "PM_MRK_DATA_FROM_L2", .pme_code = 0x1937, .pme_short_desc = "Marked data loaded from L2", .pme_long_desc = "DL1 was reloaded from the local L2 due to a marked demand load", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_DATA_FROM_L2], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_DATA_FROM_L2] }, [ PPC970MP_PME_PM_LSU0_FLUSH_SRQ ] = { .pme_name = "PM_LSU0_FLUSH_SRQ", .pme_code = 0x803, .pme_short_desc = "LSU0 SRQ flushes", .pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU0_FLUSH_SRQ], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU0_FLUSH_SRQ] }, [ PPC970MP_PME_PM_FPU0_FMOV_FEST ] = { .pme_name = "PM_FPU0_FMOV_FEST", .pme_code = 0x110, .pme_short_desc = "FPU0 executed FMOV or FEST instructions", .pme_long_desc = "This signal is active for one cycle when fp0 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU0_FMOV_FEST], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU0_FMOV_FEST] }, [ PPC970MP_PME_PM_IOPS_CMPL ] = { .pme_name = "PM_IOPS_CMPL", .pme_code = 0x1001, .pme_short_desc = "IOPS instructions completed", .pme_long_desc = "Number of IOPS Instructions that completed.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_IOPS_CMPL], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_IOPS_CMPL] }, [ PPC970MP_PME_PM_LD_REF_L1_LSU0 ] = { .pme_name = "PM_LD_REF_L1_LSU0", .pme_code = 0x810, .pme_short_desc = "LSU0 L1 D cache load references", .pme_long_desc = "A load executed on unit 0", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LD_REF_L1_LSU0], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LD_REF_L1_LSU0] }, [ PPC970MP_PME_PM_LSU1_FLUSH_SRQ ] = { .pme_name = "PM_LSU1_FLUSH_SRQ", .pme_code = 0x807, .pme_short_desc = "LSU1 SRQ flushes", .pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group. ", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU1_FLUSH_SRQ], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU1_FLUSH_SRQ] }, [ PPC970MP_PME_PM_CMPLU_STALL_DIV ] = { .pme_name = "PM_CMPLU_STALL_DIV", .pme_code = 0x708b, .pme_short_desc = "Completion stall caused by DIV instruction", .pme_long_desc = "Completion stall caused by DIV instruction", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_CMPLU_STALL_DIV], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_CMPLU_STALL_DIV] }, [ PPC970MP_PME_PM_GRP_BR_MPRED ] = { .pme_name = "PM_GRP_BR_MPRED", .pme_code = 0x327, .pme_short_desc = "Group experienced a branch mispredict", .pme_long_desc = "Group experienced a branch mispredict", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GRP_BR_MPRED], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GRP_BR_MPRED] }, [ PPC970MP_PME_PM_LSU_LMQ_S0_ALLOC ] = { .pme_name = "PM_LSU_LMQ_S0_ALLOC", .pme_code = 0x836, .pme_short_desc = "LMQ slot 0 allocated", .pme_long_desc = "The first entry in the LMQ was allocated.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_LMQ_S0_ALLOC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_LMQ_S0_ALLOC] }, [ PPC970MP_PME_PM_LSU0_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU0_REJECT_LMQ_FULL", .pme_code = 0x921, .pme_short_desc = "LSU0 reject due to LMQ full or missed data coming", .pme_long_desc = "LSU0 reject due to LMQ full or missed data coming", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU0_REJECT_LMQ_FULL], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU0_REJECT_LMQ_FULL] }, [ PPC970MP_PME_PM_ST_REF_L1 ] = { .pme_name = "PM_ST_REF_L1", .pme_code = 0x7810, .pme_short_desc = "L1 D cache store references", .pme_long_desc = "Total DL1 Store references", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_ST_REF_L1], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_ST_REF_L1] }, [ PPC970MP_PME_PM_MRK_VMX_FIN ] = { .pme_name = "PM_MRK_VMX_FIN", .pme_code = 0x3005, .pme_short_desc = "Marked instruction VMX processing finished", .pme_long_desc = "Marked instruction VMX processing finished", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_VMX_FIN], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_VMX_FIN] }, [ PPC970MP_PME_PM_LSU_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_SRQ_EMPTY_CYC", .pme_code = 0x4003, .pme_short_desc = "Cycles SRQ empty", .pme_long_desc = "The Store Request Queue is empty", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_SRQ_EMPTY_CYC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_SRQ_EMPTY_CYC] }, [ PPC970MP_PME_PM_FPU1_STF ] = { .pme_name = "PM_FPU1_STF", .pme_code = 0x126, .pme_short_desc = "FPU1 executed store instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing a store instruction.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU1_STF], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU1_STF] }, [ PPC970MP_PME_PM_RUN_CYC ] = { .pme_name = "PM_RUN_CYC", .pme_code = 0x1005, .pme_short_desc = "Run cycles", .pme_long_desc = "Processor Cycles gated by the run latch", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_RUN_CYC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_RUN_CYC] }, [ PPC970MP_PME_PM_LSU_LMQ_S0_VALID ] = { .pme_name = "PM_LSU_LMQ_S0_VALID", .pme_code = 0x835, .pme_short_desc = "LMQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle when the first entry in the LMQ is valid. The LMQ had eight entries that are allocated FIFO", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_LMQ_S0_VALID], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_LMQ_S0_VALID] }, [ PPC970MP_PME_PM_LSU0_LDF ] = { .pme_name = "PM_LSU0_LDF", .pme_code = 0x730, .pme_short_desc = "LSU0 executed Floating Point load instruction", .pme_long_desc = "A floating point load was executed from LSU unit 0", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU0_LDF], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU0_LDF] }, [ PPC970MP_PME_PM_LSU_LRQ_S0_VALID ] = { .pme_name = "PM_LSU_LRQ_S0_VALID", .pme_code = 0x822, .pme_short_desc = "LRQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_LRQ_S0_VALID], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_LRQ_S0_VALID] }, [ PPC970MP_PME_PM_PMC3_OVERFLOW ] = { .pme_name = "PM_PMC3_OVERFLOW", .pme_code = 0x400a, .pme_short_desc = "PMC3 Overflow", .pme_long_desc = "PMC3 Overflow", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_PMC3_OVERFLOW], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_PMC3_OVERFLOW] }, [ PPC970MP_PME_PM_MRK_IMR_RELOAD ] = { .pme_name = "PM_MRK_IMR_RELOAD", .pme_code = 0x722, .pme_short_desc = "Marked IMR reloaded", .pme_long_desc = "A DL1 reload occured due to marked load", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_IMR_RELOAD], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_IMR_RELOAD] }, [ PPC970MP_PME_PM_MRK_GRP_TIMEO ] = { .pme_name = "PM_MRK_GRP_TIMEO", .pme_code = 0x5005, .pme_short_desc = "Marked group completion timeout", .pme_long_desc = "The sampling timeout expired indicating that the previously sampled instruction is no longer in the processor", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_GRP_TIMEO], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_GRP_TIMEO] }, [ PPC970MP_PME_PM_FPU_FMOV_FEST ] = { .pme_name = "PM_FPU_FMOV_FEST", .pme_code = 0x8110, .pme_short_desc = "FPU executing FMOV or FEST instructions", .pme_long_desc = "This signal is active for one cycle when executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ . Combined Unit 0 + Unit 1", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU_FMOV_FEST], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU_FMOV_FEST] }, [ PPC970MP_PME_PM_GRP_DISP_BLK_SB_CYC ] = { .pme_name = "PM_GRP_DISP_BLK_SB_CYC", .pme_code = 0x331, .pme_short_desc = "Cycles group dispatch blocked by scoreboard", .pme_long_desc = "The ISU sends a signal indicating that dispatch is blocked by scoreboard.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GRP_DISP_BLK_SB_CYC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GRP_DISP_BLK_SB_CYC] }, [ PPC970MP_PME_PM_XER_MAP_FULL_CYC ] = { .pme_name = "PM_XER_MAP_FULL_CYC", .pme_code = 0x302, .pme_short_desc = "Cycles XER mapper full", .pme_long_desc = "The ISU sends a signal indicating that the xer mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_XER_MAP_FULL_CYC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_XER_MAP_FULL_CYC] }, [ PPC970MP_PME_PM_ST_MISS_L1 ] = { .pme_name = "PM_ST_MISS_L1", .pme_code = 0x813, .pme_short_desc = "L1 D cache store misses", .pme_long_desc = "A store missed the dcache", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_ST_MISS_L1], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_ST_MISS_L1] }, [ PPC970MP_PME_PM_STOP_COMPLETION ] = { .pme_name = "PM_STOP_COMPLETION", .pme_code = 0x3001, .pme_short_desc = "Completion stopped", .pme_long_desc = "RAS Unit has signaled completion to stop", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_STOP_COMPLETION], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_STOP_COMPLETION] }, [ PPC970MP_PME_PM_MRK_GRP_CMPL ] = { .pme_name = "PM_MRK_GRP_CMPL", .pme_code = 0x4004, .pme_short_desc = "Marked group completed", .pme_long_desc = "A group containing a sampled instruction completed. Microcoded instructions that span multiple groups will generate this event once per group.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_GRP_CMPL], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_GRP_CMPL] }, [ PPC970MP_PME_PM_ISLB_MISS ] = { .pme_name = "PM_ISLB_MISS", .pme_code = 0x701, .pme_short_desc = "Instruction SLB misses", .pme_long_desc = "A SLB miss for an instruction fetch as occurred", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_ISLB_MISS], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_ISLB_MISS] }, [ PPC970MP_PME_PM_SUSPENDED ] = { .pme_name = "PM_SUSPENDED", .pme_code = 0x0, .pme_short_desc = "Suspended", .pme_long_desc = "Suspended", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_SUSPENDED], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_SUSPENDED] }, [ PPC970MP_PME_PM_CYC ] = { .pme_name = "PM_CYC", .pme_code = 0x7, .pme_short_desc = "Processor cycles", .pme_long_desc = "Processor cycles", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_CYC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_CYC] }, [ PPC970MP_PME_PM_LD_MISS_L1_LSU1 ] = { .pme_name = "PM_LD_MISS_L1_LSU1", .pme_code = 0x816, .pme_short_desc = "LSU1 L1 D cache load misses", .pme_long_desc = "A load, executing on unit 1, missed the dcache", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LD_MISS_L1_LSU1], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LD_MISS_L1_LSU1] }, [ PPC970MP_PME_PM_STCX_FAIL ] = { .pme_name = "PM_STCX_FAIL", .pme_code = 0x721, .pme_short_desc = "STCX failed", .pme_long_desc = "A stcx (stwcx or stdcx) failed", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_STCX_FAIL], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_STCX_FAIL] }, [ PPC970MP_PME_PM_LSU1_SRQ_STFWD ] = { .pme_name = "PM_LSU1_SRQ_STFWD", .pme_code = 0x824, .pme_short_desc = "LSU1 SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load on unit 1", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU1_SRQ_STFWD], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU1_SRQ_STFWD] }, [ PPC970MP_PME_PM_GRP_DISP ] = { .pme_name = "PM_GRP_DISP", .pme_code = 0x2004, .pme_short_desc = "Group dispatches", .pme_long_desc = "A group was dispatched", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GRP_DISP], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GRP_DISP] }, [ PPC970MP_PME_PM_L2_PREF ] = { .pme_name = "PM_L2_PREF", .pme_code = 0x733, .pme_short_desc = "L2 cache prefetches", .pme_long_desc = "A request to prefetch data into L2 was made", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_L2_PREF], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_L2_PREF] }, [ PPC970MP_PME_PM_FPU1_DENORM ] = { .pme_name = "PM_FPU1_DENORM", .pme_code = 0x124, .pme_short_desc = "FPU1 received denormalized data", .pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU1_DENORM], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU1_DENORM] }, [ PPC970MP_PME_PM_DATA_FROM_L2 ] = { .pme_name = "PM_DATA_FROM_L2", .pme_code = 0x1837, .pme_short_desc = "Data loaded from L2", .pme_long_desc = "DL1 was reloaded from the local L2 due to a demand load", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_DATA_FROM_L2], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_DATA_FROM_L2] }, [ PPC970MP_PME_PM_FPU0_FPSCR ] = { .pme_name = "PM_FPU0_FPSCR", .pme_code = 0x130, .pme_short_desc = "FPU0 executed FPSCR instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing fpscr move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*. mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU0_FPSCR], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU0_FPSCR] }, [ PPC970MP_PME_PM_MRK_DATA_FROM_L25_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L25_MOD", .pme_code = 0x6937, .pme_short_desc = "Marked data loaded from L2.5 modified", .pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a marked demand load", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_DATA_FROM_L25_MOD], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_DATA_FROM_L25_MOD] }, [ PPC970MP_PME_PM_FPU0_FSQRT ] = { .pme_name = "PM_FPU0_FSQRT", .pme_code = 0x102, .pme_short_desc = "FPU0 executed FSQRT instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp0 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU0_FSQRT], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU0_FSQRT] }, [ PPC970MP_PME_PM_LD_REF_L1 ] = { .pme_name = "PM_LD_REF_L1", .pme_code = 0x8810, .pme_short_desc = "L1 D cache load references", .pme_long_desc = "Total DL1 Load references", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LD_REF_L1], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LD_REF_L1] }, [ PPC970MP_PME_PM_MRK_L1_RELOAD_VALID ] = { .pme_name = "PM_MRK_L1_RELOAD_VALID", .pme_code = 0x934, .pme_short_desc = "Marked L1 reload data source valid", .pme_long_desc = "The source information is valid and is for a marked load", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_L1_RELOAD_VALID], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_L1_RELOAD_VALID] }, [ PPC970MP_PME_PM_1PLUS_PPC_CMPL ] = { .pme_name = "PM_1PLUS_PPC_CMPL", .pme_code = 0x5003, .pme_short_desc = "One or more PPC instruction completed", .pme_long_desc = "A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_1PLUS_PPC_CMPL], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_1PLUS_PPC_CMPL] }, [ PPC970MP_PME_PM_INST_FROM_L1 ] = { .pme_name = "PM_INST_FROM_L1", .pme_code = 0x142d, .pme_short_desc = "Instruction fetched from L1", .pme_long_desc = "An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_INST_FROM_L1], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_INST_FROM_L1] }, [ PPC970MP_PME_PM_EE_OFF_EXT_INT ] = { .pme_name = "PM_EE_OFF_EXT_INT", .pme_code = 0x337, .pme_short_desc = "Cycles MSR(EE) bit off and external interrupt pending", .pme_long_desc = "Cycles MSR(EE) bit off and external interrupt pending", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_EE_OFF_EXT_INT], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_EE_OFF_EXT_INT] }, [ PPC970MP_PME_PM_PMC6_OVERFLOW ] = { .pme_name = "PM_PMC6_OVERFLOW", .pme_code = 0x700a, .pme_short_desc = "PMC6 Overflow", .pme_long_desc = "PMC6 Overflow", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_PMC6_OVERFLOW], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_PMC6_OVERFLOW] }, [ PPC970MP_PME_PM_LSU_LRQ_FULL_CYC ] = { .pme_name = "PM_LSU_LRQ_FULL_CYC", .pme_code = 0x312, .pme_short_desc = "Cycles LRQ full", .pme_long_desc = "The ISU sends this signal when the LRQ is full.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_LRQ_FULL_CYC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_LRQ_FULL_CYC] }, [ PPC970MP_PME_PM_IC_PREF_INSTALL ] = { .pme_name = "PM_IC_PREF_INSTALL", .pme_code = 0x427, .pme_short_desc = "Instruction prefetched installed in prefetch", .pme_long_desc = "New line coming into the prefetch buffer", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_IC_PREF_INSTALL], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_IC_PREF_INSTALL] }, [ PPC970MP_PME_PM_DC_PREF_OUT_OF_STREAMS ] = { .pme_name = "PM_DC_PREF_OUT_OF_STREAMS", .pme_code = 0x732, .pme_short_desc = "D cache out of streams", .pme_long_desc = "out of streams", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_DC_PREF_OUT_OF_STREAMS], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_DC_PREF_OUT_OF_STREAMS] }, [ PPC970MP_PME_PM_MRK_LSU1_FLUSH_SRQ ] = { .pme_name = "PM_MRK_LSU1_FLUSH_SRQ", .pme_code = 0x717, .pme_short_desc = "LSU1 marked SRQ flushes", .pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_LSU1_FLUSH_SRQ], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_LSU1_FLUSH_SRQ] }, [ PPC970MP_PME_PM_GCT_FULL_CYC ] = { .pme_name = "PM_GCT_FULL_CYC", .pme_code = 0x300, .pme_short_desc = "Cycles GCT full", .pme_long_desc = "The ISU sends a signal indicating the gct is full. ", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GCT_FULL_CYC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GCT_FULL_CYC] }, [ PPC970MP_PME_PM_INST_FROM_MEM ] = { .pme_name = "PM_INST_FROM_MEM", .pme_code = 0x2426, .pme_short_desc = "Instruction fetched from memory", .pme_long_desc = "Instruction fetched from memory", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_INST_FROM_MEM], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_INST_FROM_MEM] }, [ PPC970MP_PME_PM_FLUSH_LSU_BR_MPRED ] = { .pme_name = "PM_FLUSH_LSU_BR_MPRED", .pme_code = 0x317, .pme_short_desc = "Flush caused by LSU or branch mispredict", .pme_long_desc = "Flush caused by LSU or branch mispredict", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FLUSH_LSU_BR_MPRED], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FLUSH_LSU_BR_MPRED] }, [ PPC970MP_PME_PM_FXU_BUSY ] = { .pme_name = "PM_FXU_BUSY", .pme_code = 0x6002, .pme_short_desc = "FXU busy", .pme_long_desc = "FXU0 and FXU1 are both busy", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FXU_BUSY], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FXU_BUSY] }, [ PPC970MP_PME_PM_ST_REF_L1_LSU1 ] = { .pme_name = "PM_ST_REF_L1_LSU1", .pme_code = 0x815, .pme_short_desc = "LSU1 L1 D cache store references", .pme_long_desc = "A store executed on unit 1", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_ST_REF_L1_LSU1], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_ST_REF_L1_LSU1] }, [ PPC970MP_PME_PM_MRK_LD_MISS_L1 ] = { .pme_name = "PM_MRK_LD_MISS_L1", .pme_code = 0x1720, .pme_short_desc = "Marked L1 D cache load misses", .pme_long_desc = "Marked L1 D cache load misses", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_LD_MISS_L1], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_LD_MISS_L1] }, [ PPC970MP_PME_PM_L1_WRITE_CYC ] = { .pme_name = "PM_L1_WRITE_CYC", .pme_code = 0x434, .pme_short_desc = "Cycles writing to instruction L1", .pme_long_desc = "This signal is asserted each cycle a cache write is active.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_L1_WRITE_CYC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_L1_WRITE_CYC] }, [ PPC970MP_PME_PM_LSU1_BUSY ] = { .pme_name = "PM_LSU1_BUSY", .pme_code = 0x827, .pme_short_desc = "LSU1 busy", .pme_long_desc = "LSU unit 0 is busy rejecting instructions ", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU1_BUSY], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU1_BUSY] }, [ PPC970MP_PME_PM_LSU_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU_REJECT_LMQ_FULL", .pme_code = 0x2920, .pme_short_desc = "LSU reject due to LMQ full or missed data coming", .pme_long_desc = "LSU reject due to LMQ full or missed data coming", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_REJECT_LMQ_FULL], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_REJECT_LMQ_FULL] }, [ PPC970MP_PME_PM_CMPLU_STALL_FDIV ] = { .pme_name = "PM_CMPLU_STALL_FDIV", .pme_code = 0x504c, .pme_short_desc = "Completion stall caused by FDIV or FQRT instruction", .pme_long_desc = "Completion stall caused by FDIV or FQRT instruction", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_CMPLU_STALL_FDIV], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_CMPLU_STALL_FDIV] }, [ PPC970MP_PME_PM_FPU_ALL ] = { .pme_name = "PM_FPU_ALL", .pme_code = 0x5100, .pme_short_desc = "FPU executed add", .pme_long_desc = " mult", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU_ALL], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU_ALL] }, [ PPC970MP_PME_PM_LSU_SRQ_S0_ALLOC ] = { .pme_name = "PM_LSU_SRQ_S0_ALLOC", .pme_code = 0x825, .pme_short_desc = "SRQ slot 0 allocated", .pme_long_desc = "SRQ Slot zero was allocated", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_SRQ_S0_ALLOC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_SRQ_S0_ALLOC] }, [ PPC970MP_PME_PM_INST_FROM_L25_SHR ] = { .pme_name = "PM_INST_FROM_L25_SHR", .pme_code = 0x5426, .pme_short_desc = "Instruction fetched from L2.5 shared", .pme_long_desc = "Instruction fetched from L2.5 shared", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_INST_FROM_L25_SHR], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_INST_FROM_L25_SHR] }, [ PPC970MP_PME_PM_GRP_MRK ] = { .pme_name = "PM_GRP_MRK", .pme_code = 0x5004, .pme_short_desc = "Group marked in IDU", .pme_long_desc = "A group was sampled (marked)", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GRP_MRK], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GRP_MRK] }, [ PPC970MP_PME_PM_BR_MPRED_CR ] = { .pme_name = "PM_BR_MPRED_CR", .pme_code = 0x432, .pme_short_desc = "Branch mispredictions due to CR bit setting", .pme_long_desc = "This signal is asserted when the branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This signal is asserted after a branch issue event and will result in a branch redirect flush if not overridden by a flush of an older instruction.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_BR_MPRED_CR], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_BR_MPRED_CR] }, [ PPC970MP_PME_PM_DC_PREF_STREAM_ALLOC ] = { .pme_name = "PM_DC_PREF_STREAM_ALLOC", .pme_code = 0x737, .pme_short_desc = "D cache new prefetch stream allocated", .pme_long_desc = "A new Prefetch Stream was allocated", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_DC_PREF_STREAM_ALLOC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_DC_PREF_STREAM_ALLOC] }, [ PPC970MP_PME_PM_FPU1_FIN ] = { .pme_name = "PM_FPU1_FIN", .pme_code = 0x117, .pme_short_desc = "FPU1 produced a result", .pme_long_desc = "fp1 finished, produced a result. This only indicates finish, not completion. ", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU1_FIN], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU1_FIN] }, [ PPC970MP_PME_PM_LSU_REJECT_SRQ ] = { .pme_name = "PM_LSU_REJECT_SRQ", .pme_code = 0x1920, .pme_short_desc = "LSU SRQ rejects", .pme_long_desc = "LSU SRQ rejects", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_REJECT_SRQ], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_REJECT_SRQ] }, [ PPC970MP_PME_PM_BR_MPRED_TA ] = { .pme_name = "PM_BR_MPRED_TA", .pme_code = 0x433, .pme_short_desc = "Branch mispredictions due to target address", .pme_long_desc = "branch miss predict due to a target address prediction. This signal will be asserted each time the branch execution unit detects an incorrect target address prediction. This signal will be asserted after a valid branch execution unit issue and will cause a branch mispredict flush unless a flush is detected from an older instruction.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_BR_MPRED_TA], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_BR_MPRED_TA] }, [ PPC970MP_PME_PM_CRQ_FULL_CYC ] = { .pme_name = "PM_CRQ_FULL_CYC", .pme_code = 0x311, .pme_short_desc = "Cycles CR issue queue full", .pme_long_desc = "The ISU sends a signal indicating that the issue queue that feeds the ifu cr unit cannot accept any more group (queue is full of groups).", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_CRQ_FULL_CYC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_CRQ_FULL_CYC] }, [ PPC970MP_PME_PM_LD_MISS_L1 ] = { .pme_name = "PM_LD_MISS_L1", .pme_code = 0x3810, .pme_short_desc = "L1 D cache load misses", .pme_long_desc = "Total DL1 Load references that miss the DL1", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LD_MISS_L1], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LD_MISS_L1] }, [ PPC970MP_PME_PM_INST_FROM_PREF ] = { .pme_name = "PM_INST_FROM_PREF", .pme_code = 0x342d, .pme_short_desc = "Instructions fetched from prefetch", .pme_long_desc = "An instruction fetch group was fetched from the prefetch buffer. Fetch Groups can contain up to 8 instructions", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_INST_FROM_PREF], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_INST_FROM_PREF] }, [ PPC970MP_PME_PM_STCX_PASS ] = { .pme_name = "PM_STCX_PASS", .pme_code = 0x725, .pme_short_desc = "Stcx passes", .pme_long_desc = "A stcx (stwcx or stdcx) instruction was successful", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_STCX_PASS], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_STCX_PASS] }, [ PPC970MP_PME_PM_DC_INV_L2 ] = { .pme_name = "PM_DC_INV_L2", .pme_code = 0x817, .pme_short_desc = "L1 D cache entries invalidated from L2", .pme_long_desc = "A dcache invalidated was received from the L2 because a line in L2 was castout.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_DC_INV_L2], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_DC_INV_L2] }, [ PPC970MP_PME_PM_LSU_SRQ_FULL_CYC ] = { .pme_name = "PM_LSU_SRQ_FULL_CYC", .pme_code = 0x313, .pme_short_desc = "Cycles SRQ full", .pme_long_desc = "The ISU sends this signal when the srq is full.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_SRQ_FULL_CYC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_SRQ_FULL_CYC] }, [ PPC970MP_PME_PM_LSU0_FLUSH_LRQ ] = { .pme_name = "PM_LSU0_FLUSH_LRQ", .pme_code = 0x802, .pme_short_desc = "LSU0 LRQ flushes", .pme_long_desc = "A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU0_FLUSH_LRQ], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU0_FLUSH_LRQ] }, [ PPC970MP_PME_PM_LSU_SRQ_S0_VALID ] = { .pme_name = "PM_LSU_SRQ_S0_VALID", .pme_code = 0x821, .pme_short_desc = "SRQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_SRQ_S0_VALID], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_SRQ_S0_VALID] }, [ PPC970MP_PME_PM_LARX_LSU0 ] = { .pme_name = "PM_LARX_LSU0", .pme_code = 0x727, .pme_short_desc = "Larx executed on LSU0", .pme_long_desc = "A larx (lwarx or ldarx) was executed on side 0 (there is no coresponding unit 1 event since larx instructions can only execute on unit 0)", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LARX_LSU0], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LARX_LSU0] }, [ PPC970MP_PME_PM_GCT_EMPTY_CYC ] = { .pme_name = "PM_GCT_EMPTY_CYC", .pme_code = 0x1004, .pme_short_desc = "Cycles GCT empty", .pme_long_desc = "The Global Completion Table is completely empty", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_GCT_EMPTY_CYC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_GCT_EMPTY_CYC] }, [ PPC970MP_PME_PM_FPU1_ALL ] = { .pme_name = "PM_FPU1_ALL", .pme_code = 0x107, .pme_short_desc = "FPU1 executed add", .pme_long_desc = " mult", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU1_ALL], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU1_ALL] }, [ PPC970MP_PME_PM_FPU1_FSQRT ] = { .pme_name = "PM_FPU1_FSQRT", .pme_code = 0x106, .pme_short_desc = "FPU1 executed FSQRT instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp1 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU1_FSQRT], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU1_FSQRT] }, [ PPC970MP_PME_PM_FPU_FIN ] = { .pme_name = "PM_FPU_FIN", .pme_code = 0x4110, .pme_short_desc = "FPU produced a result", .pme_long_desc = "FPU finished, produced a result This only indicates finish, not completion. Combined Unit 0 + Unit 1", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU_FIN], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU_FIN] }, [ PPC970MP_PME_PM_LSU_SRQ_STFWD ] = { .pme_name = "PM_LSU_SRQ_STFWD", .pme_code = 0x1820, .pme_short_desc = "SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_SRQ_STFWD], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_SRQ_STFWD] }, [ PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU1 ] = { .pme_name = "PM_MRK_LD_MISS_L1_LSU1", .pme_code = 0x724, .pme_short_desc = "LSU1 L1 D cache load misses", .pme_long_desc = "A marked load, executing on unit 1, missed the dcache", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU1], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_LD_MISS_L1_LSU1] }, [ PPC970MP_PME_PM_FXU0_FIN ] = { .pme_name = "PM_FXU0_FIN", .pme_code = 0x332, .pme_short_desc = "FXU0 produced a result", .pme_long_desc = "The Fixed Point unit 0 finished an instruction and produced a result", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FXU0_FIN], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FXU0_FIN] }, [ PPC970MP_PME_PM_MRK_FPU_FIN ] = { .pme_name = "PM_MRK_FPU_FIN", .pme_code = 0x7004, .pme_short_desc = "Marked instruction FPU processing finished", .pme_long_desc = "One of the Floating Point Units finished a marked instruction. Instructions that finish may not necessary complete", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_FPU_FIN], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_FPU_FIN] }, [ PPC970MP_PME_PM_PMC5_OVERFLOW ] = { .pme_name = "PM_PMC5_OVERFLOW", .pme_code = 0x600a, .pme_short_desc = "PMC5 Overflow", .pme_long_desc = "PMC5 Overflow", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_PMC5_OVERFLOW], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_PMC5_OVERFLOW] }, [ PPC970MP_PME_PM_SNOOP_TLBIE ] = { .pme_name = "PM_SNOOP_TLBIE", .pme_code = 0x703, .pme_short_desc = "Snoop TLBIE", .pme_long_desc = "A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_SNOOP_TLBIE], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_SNOOP_TLBIE] }, [ PPC970MP_PME_PM_FPU1_FRSP_FCONV ] = { .pme_name = "PM_FPU1_FRSP_FCONV", .pme_code = 0x115, .pme_short_desc = "FPU1 executed FRSP or FCONV instructions", .pme_long_desc = "This signal is active for one cycle when fp1 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU1_FRSP_FCONV], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU1_FRSP_FCONV] }, [ PPC970MP_PME_PM_FPU0_FDIV ] = { .pme_name = "PM_FPU0_FDIV", .pme_code = 0x100, .pme_short_desc = "FPU0 executed FDIV instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp0 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU0_FDIV], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU0_FDIV] }, [ PPC970MP_PME_PM_LD_REF_L1_LSU1 ] = { .pme_name = "PM_LD_REF_L1_LSU1", .pme_code = 0x814, .pme_short_desc = "LSU1 L1 D cache load references", .pme_long_desc = "A load executed on unit 1", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LD_REF_L1_LSU1], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LD_REF_L1_LSU1] }, [ PPC970MP_PME_PM_HV_CYC ] = { .pme_name = "PM_HV_CYC", .pme_code = 0x3004, .pme_short_desc = "Hypervisor Cycles", .pme_long_desc = "Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0)", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_HV_CYC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_HV_CYC] }, [ PPC970MP_PME_PM_LR_CTR_MAP_FULL_CYC ] = { .pme_name = "PM_LR_CTR_MAP_FULL_CYC", .pme_code = 0x306, .pme_short_desc = "Cycles LR/CTR mapper full", .pme_long_desc = "The ISU sends a signal indicating that the lr/ctr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LR_CTR_MAP_FULL_CYC], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LR_CTR_MAP_FULL_CYC] }, [ PPC970MP_PME_PM_FPU_DENORM ] = { .pme_name = "PM_FPU_DENORM", .pme_code = 0x1120, .pme_short_desc = "FPU received denormalized data", .pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized. Combined Unit 0 + Unit 1", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_FPU_DENORM], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_FPU_DENORM] }, [ PPC970MP_PME_PM_LSU0_REJECT_SRQ ] = { .pme_name = "PM_LSU0_REJECT_SRQ", .pme_code = 0x920, .pme_short_desc = "LSU0 SRQ rejects", .pme_long_desc = "LSU0 SRQ rejects", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU0_REJECT_SRQ], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU0_REJECT_SRQ] }, [ PPC970MP_PME_PM_LSU1_REJECT_SRQ ] = { .pme_name = "PM_LSU1_REJECT_SRQ", .pme_code = 0x924, .pme_short_desc = "LSU1 SRQ rejects", .pme_long_desc = "LSU1 SRQ rejects", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU1_REJECT_SRQ], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU1_REJECT_SRQ] }, [ PPC970MP_PME_PM_LSU1_DERAT_MISS ] = { .pme_name = "PM_LSU1_DERAT_MISS", .pme_code = 0x706, .pme_short_desc = "LSU1 DERAT misses", .pme_long_desc = "A data request (load or store) from LSU Unit 1 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU1_DERAT_MISS], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU1_DERAT_MISS] }, [ PPC970MP_PME_PM_IC_PREF_REQ ] = { .pme_name = "PM_IC_PREF_REQ", .pme_code = 0x426, .pme_short_desc = "Instruction prefetch requests", .pme_long_desc = "Asserted when a non-canceled prefetch is made to the cache interface unit (CIU).", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_IC_PREF_REQ], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_IC_PREF_REQ] }, [ PPC970MP_PME_PM_MRK_LSU_FIN ] = { .pme_name = "PM_MRK_LSU_FIN", .pme_code = 0x8004, .pme_short_desc = "Marked instruction LSU processing finished", .pme_long_desc = "One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_LSU_FIN], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_LSU_FIN] }, [ PPC970MP_PME_PM_MRK_DATA_FROM_MEM ] = { .pme_name = "PM_MRK_DATA_FROM_MEM", .pme_code = 0x2937, .pme_short_desc = "Marked data loaded from memory", .pme_long_desc = "Marked data loaded from memory", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_MRK_DATA_FROM_MEM], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_MRK_DATA_FROM_MEM] }, [ PPC970MP_PME_PM_CMPLU_STALL_DCACHE_MISS ] = { .pme_name = "PM_CMPLU_STALL_DCACHE_MISS", .pme_code = 0x50cb, .pme_short_desc = "Completion stall caused by D cache miss", .pme_long_desc = "Completion stall caused by D cache miss", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_CMPLU_STALL_DCACHE_MISS], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_CMPLU_STALL_DCACHE_MISS] }, [ PPC970MP_PME_PM_LSU0_FLUSH_UST ] = { .pme_name = "PM_LSU0_FLUSH_UST", .pme_code = 0x801, .pme_short_desc = "LSU0 unaligned store flushes", .pme_long_desc = "A store was flushed from unit 0 because it was unaligned (crossed a 4k boundary)", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU0_FLUSH_UST], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU0_FLUSH_UST] }, [ PPC970MP_PME_PM_LSU_FLUSH_LRQ ] = { .pme_name = "PM_LSU_FLUSH_LRQ", .pme_code = 0x6800, .pme_short_desc = "LRQ flushes", .pme_long_desc = "A load was flushed because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_FLUSH_LRQ], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_FLUSH_LRQ] }, [ PPC970MP_PME_PM_LSU_FLUSH_SRQ ] = { .pme_name = "PM_LSU_FLUSH_SRQ", .pme_code = 0x5800, .pme_short_desc = "SRQ flushes", .pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", .pme_event_ids = ppc970mp_event_ids[PPC970MP_PME_PM_LSU_FLUSH_SRQ], .pme_group_vector = ppc970mp_group_vecs[PPC970MP_PME_PM_LSU_FLUSH_SRQ] } }; #define PPC970MP_PME_EVENT_COUNT 230 static const int ppc970mp_group_event_ids[][PPC970MP_NUM_EVENT_COUNTERS] = { [ 0 ] = { 81, 2, 65, 30, 0, 2, 28, 29 }, [ 1 ] = { 2, 2, 36, 6, 39, 35, 63, 37 }, [ 2 ] = { 36, 2, 36, 6, 39, 35, 63, 37 }, [ 3 ] = { 64, 63, 4, 30, 65, 63, 63, 37 }, [ 4 ] = { 27, 25, 21, 22, 3, 25, 30, 22 }, [ 5 ] = { 26, 26, 4, 30, 26, 26, 21, 43 }, [ 6 ] = { 87, 1, 3, 29, 44, 36, 30, 4 }, [ 7 ] = { 13, 21, 22, 24, 3, 35, 46, 49 }, [ 8 ] = { 37, 2, 24, 27, 34, 31, 30, 4 }, [ 9 ] = { 28, 83, 65, 10, 3, 35, 8, 10 }, [ 10 ] = { 10, 18, 16, 21, 11, 19, 30, 4 }, [ 11 ] = { 12, 20, 13, 19, 8, 16, 30, 4 }, [ 12 ] = { 9, 17, 14, 20, 3, 35, 12, 18 }, [ 13 ] = { 15, 23, 13, 19, 3, 35, 4, 16 }, [ 14 ] = { 45, 54, 4, 5, 47, 54, 30, 4 }, [ 15 ] = { 47, 56, 39, 38, 3, 35, 35, 36 }, [ 16 ] = { 48, 57, 67, 65, 3, 35, 62, 5 }, [ 17 ] = { 53, 62, 67, 65, 81, 2, 30, 4 }, [ 18 ] = { 44, 53, 4, 5, 38, 2, 31, 4 }, [ 19 ] = { 28, 64, 29, 5, 0, 35, 28, 67 }, [ 20 ] = { 27, 25, 26, 22, 3, 25, 30, 22 }, [ 21 ] = { 6, 40, 36, 63, 3, 35, 63, 37 }, [ 22 ] = { 6, 64, 36, 63, 3, 35, 63, 37 }, [ 23 ] = { 27, 25, 13, 19, 3, 26, 30, 43 }, [ 24 ] = { 36, 2, 36, 1, 81, 2, 1, 2 }, [ 25 ] = { 36, 2, 36, 1, 3, 81, 63, 37 }, [ 26 ] = { 81, 4, 0, 2, 41, 2, 30, 2 }, [ 27 ] = { 3, 87, 30, 5, 38, 2, 44, 47 }, [ 28 ] = { 6, 40, 30, 5, 66, 65, 32, 34 }, [ 29 ] = { 39, 38, 29, 30, 4, 2, 28, 5 }, [ 30 ] = { 68, 69, 36, 49, 38, 35, 4, 37 }, [ 31 ] = { 38, 36, 70, 5, 38, 2, 30, 4 }, [ 32 ] = { 28, 33, 32, 30, 39, 62, 63, 4 }, [ 33 ] = { 74, 82, 4, 51, 35, 70, 50, 30 }, [ 34 ] = { 72, 70, 4, 50, 35, 69, 49, 60 }, [ 35 ] = { 78, 2, 62, 51, 71, 75, 60, 30 }, [ 36 ] = { 79, 71, 56, 60, 3, 35, 54, 58 }, [ 37 ] = { 75, 73, 53, 57, 3, 35, 53, 57 }, [ 38 ] = { 36, 36, 26, 26, 28, 27, 24, 4 }, [ 39 ] = { 36, 2, 23, 23, 28, 27, 25, 26 }, [ 40 ] = { 38, 38, 31, 0, 90, 37, 4, 30 }, [ 41 ] = { 85, 85, 43, 12, 84, 35, 70, 4 }, [ 42 ] = { 88, 36, 36, 5, 86, 62, 69, 37 }, [ 43 ] = { 36, 27, 26, 22, 85, 27, 68, 4 }, [ 44 ] = { 27, 25, 30, 68, 87, 25, 67, 4 }, [ 45 ] = { 28, 36, 10, 3, 88, 2, 71, 33 }, [ 46 ] = { 36, 36, 4, 5, 91, 87, 44, 47 }, [ 47 ] = { 39, 38, 31, 1, 3, 35, 1, 2 }, [ 48 ] = { 3, 87, 30, 35, 0, 2, 36, 37 }, [ 49 ] = { 3, 87, 30, 5, 91, 87, 36, 37 }, [ 50 ] = { 71, 88, 30, 5, 92, 88, 50, 51 } }; static const pmg_power_group_t ppc970mp_groups[] = { [ 0 ] = { .pmg_name = "pm_slice0", .pmg_desc = "Time Slice 0", .pmg_event_ids = ppc970mp_group_event_ids[0], .pmg_mmcr0 = 0x000000000000051eULL, .pmg_mmcr1 = 0x000000000a46f18cULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 1 ] = { .pmg_name = "pm_eprof", .pmg_desc = "Group for use with eprof", .pmg_event_ids = ppc970mp_group_event_ids[1], .pmg_mmcr0 = 0x0000000000000f1eULL, .pmg_mmcr1 = 0x4003001005f09000ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 2 ] = { .pmg_name = "pm_basic", .pmg_desc = "Basic performance indicators", .pmg_event_ids = ppc970mp_group_event_ids[2], .pmg_mmcr0 = 0x000000000000091eULL, .pmg_mmcr1 = 0x4003001005f09000ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 3 ] = { .pmg_name = "pm_lsu", .pmg_desc = "Information on the Load Store Unit", .pmg_event_ids = ppc970mp_group_event_ids[3], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000f00007a400000ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 4 ] = { .pmg_name = "pm_fpu1", .pmg_desc = "Floating Point events", .pmg_event_ids = ppc970mp_group_event_ids[4], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000001e0480ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 5 ] = { .pmg_name = "pm_fpu2", .pmg_desc = "Floating Point events", .pmg_event_ids = ppc970mp_group_event_ids[5], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000020e87a400000ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 6 ] = { .pmg_name = "pm_isu_rename", .pmg_desc = "ISU Rename Pool Events", .pmg_event_ids = ppc970mp_group_event_ids[6], .pmg_mmcr0 = 0x0000000000001228ULL, .pmg_mmcr1 = 0x400000218e6d84bcULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 7 ] = { .pmg_name = "pm_isu_queues1", .pmg_desc = "ISU Rename Pool Events", .pmg_event_ids = ppc970mp_group_event_ids[7], .pmg_mmcr0 = 0x000000000000132eULL, .pmg_mmcr1 = 0x40000000851e994cULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 8 ] = { .pmg_name = "pm_isu_flow", .pmg_desc = "ISU Instruction Flow Events", .pmg_event_ids = ppc970mp_group_event_ids[8], .pmg_mmcr0 = 0x000000000000181eULL, .pmg_mmcr1 = 0x400000b3d7b7c4bcULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 9 ] = { .pmg_name = "pm_isu_work", .pmg_desc = "ISU Indicators of Work Blockage", .pmg_event_ids = ppc970mp_group_event_ids[9], .pmg_mmcr0 = 0x0000000000000402ULL, .pmg_mmcr1 = 0x400000050fde9d88ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 10 ] = { .pmg_name = "pm_fpu3", .pmg_desc = "Floating Point events by unit", .pmg_event_ids = ppc970mp_group_event_ids[10], .pmg_mmcr0 = 0x0000000000001028ULL, .pmg_mmcr1 = 0x000000008d6354bcULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 11 ] = { .pmg_name = "pm_fpu4", .pmg_desc = "Floating Point events by unit", .pmg_event_ids = ppc970mp_group_event_ids[11], .pmg_mmcr0 = 0x000000000000122cULL, .pmg_mmcr1 = 0x000000009de774bcULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 12 ] = { .pmg_name = "pm_fpu5", .pmg_desc = "Floating Point events by unit", .pmg_event_ids = ppc970mp_group_event_ids[12], .pmg_mmcr0 = 0x0000000000001838ULL, .pmg_mmcr1 = 0x000000c0851e9958ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 13 ] = { .pmg_name = "pm_fpu7", .pmg_desc = "Floating Point events by unit", .pmg_event_ids = ppc970mp_group_event_ids[13], .pmg_mmcr0 = 0x000000000000193aULL, .pmg_mmcr1 = 0x000000c89dde97e0ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 14 ] = { .pmg_name = "pm_lsu_flush", .pmg_desc = "LSU Flush Events", .pmg_event_ids = ppc970mp_group_event_ids[14], .pmg_mmcr0 = 0x000000000000122cULL, .pmg_mmcr1 = 0x000c00007be774bcULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 15 ] = { .pmg_name = "pm_lsu_load1", .pmg_desc = "LSU Load Events", .pmg_event_ids = ppc970mp_group_event_ids[15], .pmg_mmcr0 = 0x0000000000001028ULL, .pmg_mmcr1 = 0x000f0000851e9958ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 16 ] = { .pmg_name = "pm_lsu_store1", .pmg_desc = "LSU Store Events", .pmg_event_ids = ppc970mp_group_event_ids[16], .pmg_mmcr0 = 0x000000000000112aULL, .pmg_mmcr1 = 0x000f00008d5e99dcULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 17 ] = { .pmg_name = "pm_lsu_store2", .pmg_desc = "LSU Store Events", .pmg_event_ids = ppc970mp_group_event_ids[17], .pmg_mmcr0 = 0x0000000000001838ULL, .pmg_mmcr1 = 0x0003c0d08d76f4bcULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 18 ] = { .pmg_name = "pm_lsu7", .pmg_desc = "Information on the Load Store Unit", .pmg_event_ids = ppc970mp_group_event_ids[18], .pmg_mmcr0 = 0x000000000000122cULL, .pmg_mmcr1 = 0x000830047bd2fe3cULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 19 ] = { .pmg_name = "pm_misc", .pmg_desc = "Misc Events for testing", .pmg_event_ids = ppc970mp_group_event_ids[19], .pmg_mmcr0 = 0x0000000000000404ULL, .pmg_mmcr1 = 0x0000000023c69194ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 20 ] = { .pmg_name = "pm_pe_bench1", .pmg_desc = "PE Benchmarker group for FP analysis", .pmg_event_ids = ppc970mp_group_event_ids[20], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x10001002001e0480ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 21 ] = { .pmg_name = "pm_pe_bench4", .pmg_desc = "PE Benchmarker group for L1 and TLB", .pmg_event_ids = ppc970mp_group_event_ids[21], .pmg_mmcr0 = 0x0000000000001420ULL, .pmg_mmcr1 = 0x000b000004de9000ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 22 ] = { .pmg_name = "pm_hpmcount1", .pmg_desc = "Hpmcount group for L1 and TLB behavior", .pmg_event_ids = ppc970mp_group_event_ids[22], .pmg_mmcr0 = 0x0000000000001404ULL, .pmg_mmcr1 = 0x000b000004de9000ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 23 ] = { .pmg_name = "pm_hpmcount2", .pmg_desc = "Hpmcount group for computation", .pmg_event_ids = ppc970mp_group_event_ids[23], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000020289dde0480ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 24 ] = { .pmg_name = "pm_l1andbr", .pmg_desc = "L1 misses and branch misspredict analysis", .pmg_event_ids = ppc970mp_group_event_ids[24], .pmg_mmcr0 = 0x000000000000091eULL, .pmg_mmcr1 = 0x8003c01d0676fd6cULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 25 ] = { .pmg_name = "Instruction mix: loads", .pmg_desc = " stores and branches", .pmg_event_ids = ppc970mp_group_event_ids[25], .pmg_mmcr0 = 0x000000000000091eULL, .pmg_mmcr1 = 0x8003c021065fb000ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 26 ] = { .pmg_name = "pm_branch", .pmg_desc = "SLB and branch misspredict analysis", .pmg_event_ids = ppc970mp_group_event_ids[26], .pmg_mmcr0 = 0x000000000000052aULL, .pmg_mmcr1 = 0x8008000bcea2f4ecULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 27 ] = { .pmg_name = "pm_data", .pmg_desc = "data source and LMQ", .pmg_event_ids = ppc970mp_group_event_ids[27], .pmg_mmcr0 = 0x000000000000070eULL, .pmg_mmcr1 = 0x0000300c4bd2ff74ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 28 ] = { .pmg_name = "pm_tlb", .pmg_desc = "TLB and LRQ plus data prefetch", .pmg_event_ids = ppc970mp_group_event_ids[28], .pmg_mmcr0 = 0x0000000000001420ULL, .pmg_mmcr1 = 0x0008e03c4bfdacecULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 29 ] = { .pmg_name = "pm_isource", .pmg_desc = "inst source and tablewalk", .pmg_event_ids = ppc970mp_group_event_ids[29], .pmg_mmcr0 = 0x000000000000060cULL, .pmg_mmcr1 = 0x800b00c0226ef1dcULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 30 ] = { .pmg_name = "pm_sync", .pmg_desc = "Sync and SRQ", .pmg_event_ids = ppc970mp_group_event_ids[30], .pmg_mmcr0 = 0x0000000000001d32ULL, .pmg_mmcr1 = 0x0003e0c107529780ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 31 ] = { .pmg_name = "pm_ierat", .pmg_desc = "IERAT", .pmg_event_ids = ppc970mp_group_event_ids[31], .pmg_mmcr0 = 0x0000000000000d12ULL, .pmg_mmcr1 = 0x80000082c3d2f4bcULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 32 ] = { .pmg_name = "pm_derat", .pmg_desc = "DERAT", .pmg_event_ids = ppc970mp_group_event_ids[32], .pmg_mmcr0 = 0x0000000000000436ULL, .pmg_mmcr1 = 0x100b7052e274003cULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 33 ] = { .pmg_name = "pm_mark1", .pmg_desc = "Information on marked instructions", .pmg_event_ids = ppc970mp_group_event_ids[33], .pmg_mmcr0 = 0x0000000000000006ULL, .pmg_mmcr1 = 0x00008080790852a4ULL, .pmg_mmcra = 0x0000000000002001ULL }, [ 34 ] = { .pmg_name = "pm_mark2", .pmg_desc = "Marked Instructions Processing Flow", .pmg_event_ids = ppc970mp_group_event_ids[34], .pmg_mmcr0 = 0x000000000000020aULL, .pmg_mmcr1 = 0x0000000079484210ULL, .pmg_mmcra = 0x0000000000002001ULL }, [ 35 ] = { .pmg_name = "pm_mark3", .pmg_desc = "Marked Stores Processing Flow", .pmg_event_ids = ppc970mp_group_event_ids[35], .pmg_mmcr0 = 0x000000000000031eULL, .pmg_mmcr1 = 0x00203004190a3f24ULL, .pmg_mmcra = 0x0000000000002001ULL }, [ 36 ] = { .pmg_name = "pm_lsu_mark1", .pmg_desc = "Load Store Unit Marked Events", .pmg_event_ids = ppc970mp_group_event_ids[36], .pmg_mmcr0 = 0x0000000000001b34ULL, .pmg_mmcr1 = 0x000280c08d5e9850ULL, .pmg_mmcra = 0x0000000000002001ULL }, [ 37 ] = { .pmg_name = "pm_lsu_mark2", .pmg_desc = "Load Store Unit Marked Events", .pmg_event_ids = ppc970mp_group_event_ids[37], .pmg_mmcr0 = 0x0000000000001838ULL, .pmg_mmcr1 = 0x000280c0959e99dcULL, .pmg_mmcra = 0x0000000000002001ULL }, [ 38 ] = { .pmg_name = "pm_fxu1", .pmg_desc = "Fixed Point events by unit", .pmg_event_ids = ppc970mp_group_event_ids[38], .pmg_mmcr0 = 0x0000000000000912ULL, .pmg_mmcr1 = 0x100010020084213cULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 39 ] = { .pmg_name = "pm_fxu2", .pmg_desc = "Fixed Point events by unit", .pmg_event_ids = ppc970mp_group_event_ids[39], .pmg_mmcr0 = 0x000000000000091eULL, .pmg_mmcr1 = 0x4000000ca4042d78ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 40 ] = { .pmg_name = "pm_ifu", .pmg_desc = "pm_ifu", .pmg_event_ids = ppc970mp_group_event_ids[40], .pmg_mmcr0 = 0x0000000000000d0cULL, .pmg_mmcr1 = 0x800000f06b7867a4ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 41 ] = { .pmg_name = "pm_cpi_stack1", .pmg_desc = "CPI stack analysis", .pmg_event_ids = ppc970mp_group_event_ids[41], .pmg_mmcr0 = 0x0000000000001b3eULL, .pmg_mmcr1 = 0x4000c0c0add6963dULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 42 ] = { .pmg_name = "pm_cpi_stack2", .pmg_desc = "CPI stack analysis", .pmg_event_ids = ppc970mp_group_event_ids[42], .pmg_mmcr0 = 0x0000000000000b12ULL, .pmg_mmcr1 = 0x000b000003d60583ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 43 ] = { .pmg_name = "pm_cpi_stack3", .pmg_desc = "CPI stack analysis", .pmg_event_ids = ppc970mp_group_event_ids[43], .pmg_mmcr0 = 0x0000000000000916ULL, .pmg_mmcr1 = 0x10001002001625beULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 44 ] = { .pmg_name = "pm_cpi_stack4", .pmg_desc = "CPI stack analysis", .pmg_event_ids = ppc970mp_group_event_ids[44], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000485805bdULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 45 ] = { .pmg_name = "pm_cpi_stack5", .pmg_desc = "CPI stack analysis", .pmg_event_ids = ppc970mp_group_event_ids[45], .pmg_mmcr0 = 0x0000000000000412ULL, .pmg_mmcr1 = 0x90014009b6d8f672ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 46 ] = { .pmg_name = "pm_data2", .pmg_desc = "data source and LMQ", .pmg_event_ids = ppc970mp_group_event_ids[46], .pmg_mmcr0 = 0x0000000000000912ULL, .pmg_mmcr1 = 0x0000300c7bce7f74ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 47 ] = { .pmg_name = "pm_fetch_branch", .pmg_desc = "Instruction fetch and branch events", .pmg_event_ids = ppc970mp_group_event_ids[47], .pmg_mmcr0 = 0x000000000000060cULL, .pmg_mmcr1 = 0x800000cd6e5e9d6cULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 48 ] = { .pmg_name = "pm_l1l2_miss", .pmg_desc = "L1 and L2 miss events", .pmg_event_ids = ppc970mp_group_event_ids[48], .pmg_mmcr0 = 0x000000000000070eULL, .pmg_mmcr1 = 0x000330004c86fb00ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 49 ] = { .pmg_name = "pm_data_from", .pmg_desc = "Data From L2 instructions", .pmg_event_ids = ppc970mp_group_event_ids[49], .pmg_mmcr0 = 0x000000000000070eULL, .pmg_mmcr1 = 0x000330004bce7b00ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 50 ] = { .pmg_name = "pm_mark_data_from", .pmg_desc = "Marked Data From L2 instructions", .pmg_event_ids = ppc970mp_group_event_ids[50], .pmg_mmcr0 = 0x000000000000070eULL, .pmg_mmcr1 = 0x002030084bce72f0ULL, .pmg_mmcra = 0x0000000000002001ULL } }; #endif papi-5.5.1/src/libpfm-3.y/lib/pfmlib_sicortex.c0000644000307100002310000005051713013651450021235 0ustar yarkhangraduate/* * pfmlib_sicortex.c : support for the generic MIPS64 PMU family * * Contributed by Philip Mucci based on code from * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include /* public headers */ #include #include /* private headers */ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_sicortex_priv.h" /* architecture private */ #include "sicortex/ice9a/ice9a_all_spec_pme.h" #include "sicortex/ice9b/ice9b_all_spec_pme.h" #include "sicortex/ice9/ice9_scb_spec_sw.h" /* let's define some handy shortcuts! */ #define sel_event_mask perfsel.sel_event_mask #define sel_exl perfsel.sel_exl #define sel_os perfsel.sel_os #define sel_usr perfsel.sel_usr #define sel_sup perfsel.sel_sup #define sel_int perfsel.sel_int static pme_sicortex_entry_t *sicortex_pe = NULL; // CHANGE FOR ICET #define core_counters 2 #define MAX_ICE9_PMCS 2+4+256 #define MAX_ICE9_PMDS 2+4+256 static int compute_ice9_counters(int type) { int i; int bound = 0; pme_gen_mips64_entry_t *gen_mips64_pe = NULL; sicortex_support.pmd_count = 0; sicortex_support.pmc_count = 0; for (i=0;i 2) { /* Account for 4 sampling PMD registers */ sicortex_support.num_cnt = sicortex_support.pmd_count - 4; sicortex_support.pme_count = bound; } else { sicortex_support.pme_count = 0; /* Count up CPU only events */ for (i=0;i> (cntr*8)) & 0xff; pc[j].reg_addr = cntr*2; pc[j].reg_value = reg.val; pc[j].reg_num = cntr; __pfm_vbprintf("[CP0_25_%u(pmc%u)=0x%"PRIx64" event_mask=0x%x usr=%d os=%d sup=%d exl=%d int=1] %s\n", pc[j].reg_addr, pc[j].reg_num, pc[j].reg_value, reg.sel_event_mask, reg.sel_usr, reg.sel_os, reg.sel_sup, reg.sel_exl, sicortex_pe[e[j].event].pme_name); pd[j].reg_num = cntr; pd[j].reg_addr = cntr*2 + 1; __pfm_vbprintf("[CP0_25_%u(pmd%u)]\n", pc[j].reg_addr, pc[j].reg_num); } /* SCB event */ else { pmc_sicortex_scb_reg_t scbreg; int k; scbreg.val = 0; scbreg.sicortex_ScbPerfBucket_reg.event = sicortex_pe[e[j].event].pme_code >> 16; for (k=0;kflags & PFMLIB_SICORTEX_INPUT_SCB_INTERVAL)) { two.sicortex_ScbPerfCtl_reg.Interval = mod_in->pfp_sicortex_scb_global.Interval; } else { two.sicortex_ScbPerfCtl_reg.Interval = 6; /* 2048 cycles */ } if (mod_in && (mod_in->flags & PFMLIB_SICORTEX_INPUT_SCB_NOINC)) { two.sicortex_ScbPerfCtl_reg.NoInc = mod_in->pfp_sicortex_scb_global.NoInc; } else { two.sicortex_ScbPerfCtl_reg.NoInc = 0; } two.sicortex_ScbPerfCtl_reg.IntBit = 31; /* Interrupt on last bit */ two.sicortex_ScbPerfCtl_reg.MagicEvent = 0; two.sicortex_ScbPerfCtl_reg.AddrAssert = 1; __pfm_vbprintf("[Scb%s(pmc%u)=0x%"PRIx64" Interval=0x%x IntBit=0x%x NoInc=%d AddrAssert=%d MagicEvent=0x%x]\n","PerfCtl", pc[num].reg_num, two.val, two.sicortex_ScbPerfCtl_reg.Interval, two.sicortex_ScbPerfCtl_reg.IntBit, two.sicortex_ScbPerfCtl_reg.NoInc, two.sicortex_ScbPerfCtl_reg.AddrAssert, two.sicortex_ScbPerfCtl_reg.MagicEvent); pc[num].reg_value = two.val; /*ScbPerfHist */ pc[++num].reg_num = 3; pc[num].reg_addr = 3; three.val = 0; if (mod_in && (mod_in->flags & PFMLIB_SICORTEX_INPUT_SCB_HISTGTE)) three.sicortex_ScbPerfHist_reg.HistGte = mod_in->pfp_sicortex_scb_global.HistGte; else three.sicortex_ScbPerfHist_reg.HistGte = 1; __pfm_vbprintf("[Scb%s(pmc%u)=0x%"PRIx64" HistGte=0x%x]\n","PerfHist", pc[num].reg_num, three.val, three.sicortex_ScbPerfHist_reg.HistGte); pc[num].reg_value = three.val; /*ScbPerfBuckNum */ pc[++num].reg_num = 4; pc[num].reg_addr = 4; four.val = 0; if (mod_in && (mod_in->flags & PFMLIB_SICORTEX_INPUT_SCB_BUCKET)) four.sicortex_ScbPerfBuckNum_reg.Bucket = mod_in->pfp_sicortex_scb_global.Bucket; else four.sicortex_ScbPerfBuckNum_reg.Bucket = 0; __pfm_vbprintf("[Scb%s(pmc%u)=0x%"PRIx64" Bucket=0x%x]\n","PerfBuckNum", pc[num].reg_num, four.val, four.sicortex_ScbPerfBuckNum_reg.Bucket); pc[num].reg_value = four.val; /*ScbPerfEna */ pc[++num].reg_num = 5; pc[num].reg_addr = 5; five.val = 0; five.sicortex_ScbPerfEna_reg.ena = 1; __pfm_vbprintf("[Scb%s(pmc%u)=0x%"PRIx64" ena=%d]\n","PerfEna", pc[num].reg_num, five.val, five.sicortex_ScbPerfEna_reg.ena); pc[num].reg_value = five.val; ++num; return(num); } /* * Automatically dispatch events to corresponding counters following constraints. * Upon return the pfarg_regt structure is ready to be submitted to kernel */ static int pfm_sicortex_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_sicortex_input_param_t *mod_in, pfmlib_output_param_t *outp) { /* pfmlib_sicortex_input_param_t *param = mod_in; */ pfmlib_event_t *e = inp->pfp_events; pfmlib_reg_t *pc, *pd; unsigned int i, j, cnt = inp->pfp_event_count; unsigned int used = 0; extern pfm_pmu_support_t sicortex_support; unsigned int cntr, avail; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; /* Degree N rank based allocation */ if (cnt > sicortex_support.pmc_count) return PFMLIB_ERR_TOOMANY; if (PFMLIB_DEBUG()) { for (j=0; j < cnt; j++) { DPRINT("ev[%d]=%s, counters=0x%x\n", j, sicortex_pe[e[j].event].pme_name,sicortex_pe[e[j].event].pme_counters); } } /* Do rank based allocation, counters that live on 1 reg before counters that live on 2 regs etc. */ /* CPU counters first */ for (i=1;i<=core_counters;i++) { for (j=0; j < cnt;j++) { /* CPU counters first */ if ((sicortex_pe[e[j].event].pme_counters & ((1<pfp_dfl_plm,pc,pd,cntr,j,mod_in); used |= (1 << cntr); DPRINT("Rank %d: Used counters 0x%x\n",i, used); } } } /* SCB counters can live anywhere */ used = 0; for (j=0; j < cnt;j++) { unsigned int cntr; /* CPU counters first */ if (sicortex_pe[e[j].event].pme_counters & (1<pfp_dfl_plm,pc,pd,cntr,j,mod_in); used++; DPRINT("SCB(%d): Used counters %d\n",j,used); } } if (used) { outp->pfp_pmc_count = stuff_sicortex_scb_control_regs(pc,pd,cnt,mod_in); outp->pfp_pmd_count = cnt; return PFMLIB_SUCCESS; } /* number of evtsel registers programmed */ outp->pfp_pmc_count = cnt; outp->pfp_pmd_count = cnt; return PFMLIB_SUCCESS; } static int pfm_sicortex_dispatch_events(pfmlib_input_param_t *inp, void *model_in, pfmlib_output_param_t *outp, void *model_out) { pfmlib_sicortex_input_param_t *mod_sicortex_in = (pfmlib_sicortex_input_param_t *)model_in; return pfm_sicortex_dispatch_counters(inp, mod_sicortex_in, outp); } static int pfm_sicortex_get_event_code(unsigned int i, unsigned int cnt, int *code) { extern pfm_pmu_support_t sicortex_support; /* check validity of counter index */ if (cnt != PFMLIB_CNT_FIRST) { if (cnt < 0 || cnt >= sicortex_support.pmc_count) return PFMLIB_ERR_INVAL; } else { cnt = ffs(sicortex_pe[i].pme_counters)-1; if (cnt == -1) return(PFMLIB_ERR_INVAL); } /* if cnt == 1, shift right by 0, if cnt == 2, shift right by 8 */ /* Works on both 5k anf 20K */ unsigned int tmp = sicortex_pe[i].pme_counters; /* CPU event */ if (tmp & ((1<> (cnt*8)); else return PFMLIB_ERR_INVAL; } /* SCB event */ else { if ((cnt < 6) || (cnt >= sicortex_support.pmc_count)) return PFMLIB_ERR_INVAL; *code = 0xffff & (sicortex_pe[i].pme_code >> 16); } return PFMLIB_SUCCESS; } /* * This function is accessible directly to the user */ int pfm_sicortex_get_event_umask(unsigned int i, unsigned long *umask) { extern pfm_pmu_support_t sicortex_support; if (i >= sicortex_support.pme_count || umask == NULL) return PFMLIB_ERR_INVAL; *umask = 0; //evt_umask(i); return PFMLIB_SUCCESS; } static void pfm_sicortex_get_event_counters(unsigned int j, pfmlib_regmask_t *counters) { extern pfm_pmu_support_t sicortex_support; unsigned int tmp; memset(counters, 0, sizeof(*counters)); tmp = sicortex_pe[j].pme_counters; /* CPU counter */ if (tmp & ((1< core_counters) { /* counting pmds are not contiguous on ICE9*/ for(i=6; i < sicortex_support.pmd_count; i++) pfm_regmask_set(impl_counters, i); } } static void pfm_sicortex_get_hw_counter_width(unsigned int *width) { *width = PMU_GEN_MIPS64_COUNTER_WIDTH; } static char * pfm_sicortex_get_event_name(unsigned int i) { return sicortex_pe[i].pme_name; } static int pfm_sicortex_get_event_description(unsigned int ev, char **str) { char *s; s = sicortex_pe[ev].pme_desc; if (s) { *str = strdup(s); } else { *str = NULL; } return PFMLIB_SUCCESS; } static int pfm_sicortex_get_cycle_event(pfmlib_event_t *e) { return pfm_find_full_event("CPU_CYCLES",e); } static int pfm_sicortex_get_inst_retired(pfmlib_event_t *e) { return pfm_find_full_event("CPU_INSEXEC",e); } /* SiCortex specific functions */ /* CPU counter */ int pfm_sicortex_is_cpu(unsigned int i) { if (i < sicortex_support.pme_count) { unsigned int tmp = sicortex_pe[i].pme_counters; return !(tmp & (1< #include #include #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_sparc_priv.h" #include "ultra12_events.h" #include "ultra3_events.h" #include "ultra3i_events.h" #include "ultra3plus_events.h" #include "ultra4plus_events.h" #include "niagara1_events.h" #include "niagara2_events.h" static char *get_event_name(int event) { switch (sparc_support.pmu_type) { case PFMLIB_SPARC_ULTRA12_PMU: return ultra12_pe[event].pme_name; case PFMLIB_SPARC_ULTRA3_PMU: return ultra3_pe[event].pme_name; case PFMLIB_SPARC_ULTRA3I_PMU: return ultra3i_pe[event].pme_name; case PFMLIB_SPARC_ULTRA3PLUS_PMU: return ultra3plus_pe[event].pme_name; case PFMLIB_SPARC_ULTRA4PLUS_PMU: return ultra4plus_pe[event].pme_name; case PFMLIB_SPARC_NIAGARA1_PMU: return niagara1_pe[event].pme_name; case PFMLIB_SPARC_NIAGARA2_PMU: return niagara2_pe[event].pme_name; } return (char *)-1; } static char *get_event_desc(int event) { switch (sparc_support.pmu_type) { case PFMLIB_SPARC_ULTRA12_PMU: return ultra12_pe[event].pme_desc; case PFMLIB_SPARC_ULTRA3_PMU: return ultra3_pe[event].pme_desc; case PFMLIB_SPARC_ULTRA3I_PMU: return ultra3i_pe[event].pme_desc; case PFMLIB_SPARC_ULTRA3PLUS_PMU: return ultra3plus_pe[event].pme_desc; case PFMLIB_SPARC_ULTRA4PLUS_PMU: return ultra4plus_pe[event].pme_desc; case PFMLIB_SPARC_NIAGARA1_PMU: return niagara1_pe[event].pme_desc; case PFMLIB_SPARC_NIAGARA2_PMU: return niagara2_pe[event].pme_desc; } return (char *)-1; } static char get_ctrl(int event) { switch (sparc_support.pmu_type) { case PFMLIB_SPARC_ULTRA12_PMU: return ultra12_pe[event].pme_ctrl; case PFMLIB_SPARC_ULTRA3_PMU: return ultra3_pe[event].pme_ctrl; case PFMLIB_SPARC_ULTRA3I_PMU: return ultra3i_pe[event].pme_ctrl; case PFMLIB_SPARC_ULTRA3PLUS_PMU: return ultra3plus_pe[event].pme_ctrl; case PFMLIB_SPARC_ULTRA4PLUS_PMU: return ultra4plus_pe[event].pme_ctrl; case PFMLIB_SPARC_NIAGARA1_PMU: return niagara1_pe[event].pme_ctrl; case PFMLIB_SPARC_NIAGARA2_PMU: return niagara2_pe[event].pme_ctrl; } return 0xff; } static int get_val(int event) { switch (sparc_support.pmu_type) { case PFMLIB_SPARC_ULTRA12_PMU: return ultra12_pe[event].pme_val; case PFMLIB_SPARC_ULTRA3_PMU: return ultra3_pe[event].pme_val; case PFMLIB_SPARC_ULTRA3I_PMU: return ultra3i_pe[event].pme_val; case PFMLIB_SPARC_ULTRA3PLUS_PMU: return ultra3plus_pe[event].pme_val; case PFMLIB_SPARC_ULTRA4PLUS_PMU: return ultra4plus_pe[event].pme_val; case PFMLIB_SPARC_NIAGARA1_PMU: return niagara1_pe[event].pme_val; case PFMLIB_SPARC_NIAGARA2_PMU: return niagara2_pe[event].pme_val; } return -1; } static int pfm_sparc_get_event_code(unsigned int event, unsigned int pmd, int *code) { *code = get_val(event); return 0; } static char *pfm_sparc_get_event_name(unsigned int event) { return get_event_name(event); } static char *pfm_sparc_get_event_mask_name(unsigned int event, unsigned int mask) { pme_sparc_mask_entry_t *e; if (sparc_support.pmu_type != PFMLIB_SPARC_NIAGARA2_PMU) return ""; e = &niagara2_pe[event]; return e->pme_masks[mask].mask_name; } static void pfm_sparc_get_event_counters(unsigned int event, pfmlib_regmask_t *counters) { if (sparc_support.pmu_type == PFMLIB_SPARC_NIAGARA2_PMU) { counters->bits[0] = (1 << 0) | (1 << 1); } else { char ctrl = get_ctrl(event); counters->bits[0] = 0; if (ctrl & PME_CTRL_S0) counters->bits[0] |= (1 << 0); if (ctrl & PME_CTRL_S1) counters->bits[0] |= (1 << 1); } } static unsigned int pfm_sparc_get_num_event_masks(unsigned int event) { if (sparc_support.pmu_type != PFMLIB_SPARC_NIAGARA2_PMU) return 0; return (event == 0 ? 0 : EVENT_MASK_BITS); } /* Bits common to all PCR implementations */ #define PCR_PRIV (0x1UL << 0) #define PCR_SYS_TRACE (0x1UL << 1) #define PCR_USER_TRACE (0x1UL << 2) /* The S0 and S1 fields determine which events are monitored in * the assosciated PIC (PIC0 vs. PIC1 respectively). For ultra12 * these fields are 4 bits, on ultra3/3i/3+/4+ they are 6 bits. * For Niagara-1 there is only S0 and it is 3 bits in size. * Niagara-1's PIC1 is hard-coded to record retired instructions. */ #define PCR_S0_SHIFT 4 #define PCR_S0 (0x1fUL << PCR_S0_SHIFT) #define PCR_S1_SHIFT 11 #define PCR_S1 (0x1fUL << PCR_S1_SHIFT) /* Niagara-2 specific PCR bits. It supports event masking. */ #define PCR_N2_HYP_TRACE (0x1UL << 3) #define PCR_N2_TOE0 (0x1UL << 4) #define PCR_N2_TOE1 (0x1UL << 5) #define PCR_N2_SL0_SHIFT 14 #define PCR_N2_SL0 (0xf << PCR_N2_SL0_SHIFT) #define PCR_N2_MASK0_SHIFT 6 #define PCR_N2_MASK0 (0xff << PCR_N2_MASK0_SHIFT) #define PCR_N2_SL1_SHIFT 27 #define PCR_N2_SL1 (0xf << PCR_N2_SL1_SHIFT) #define PCR_N2_MASK1_SHIFT 19 #define PCR_N2_MASK1 (0xff << PCR_N2_MASK1_SHIFT) static int pfm_sparc_dispatch_events(pfmlib_input_param_t *input, void *model_input, pfmlib_output_param_t *output, void *model_output) { unsigned long long pcr, vals[2]; unsigned int plm, i; int niagara2; char ctrls[2]; if (input->pfp_event_count > 2) return PFMLIB_ERR_TOOMANY; plm = ((input->pfp_events[0].plm != 0) ? input->pfp_events[0].plm : input->pfp_dfl_plm); for (i = 1; i < input->pfp_event_count; i++) { if (input->pfp_events[i].plm == 0) { /* it's ok if the default is the same as plm */ if (plm != input->pfp_dfl_plm) return PFMLIB_ERR_NOASSIGN; } else { if (plm != input->pfp_events[i].plm) return PFMLIB_ERR_NOASSIGN; } } niagara2 = 0; if (sparc_support.pmu_type == PFMLIB_SPARC_NIAGARA2_PMU) niagara2 = 1; pcr = 0; if (plm & PFM_PLM3) pcr |= PCR_USER_TRACE; if (plm & PFM_PLM0) pcr |= PCR_SYS_TRACE; if (niagara2 && (plm & PFM_PLM1)) pcr |= PCR_N2_HYP_TRACE; for (i = 0; i < input->pfp_event_count; i++) { pfmlib_event_t *e = &input->pfp_events[i]; ctrls[i] = get_ctrl(e->event); vals[i] = get_val(e->event); if (i == 1) { if ((ctrls[0] & ctrls[1]) == 0) continue; if (ctrls[0] == (PME_CTRL_S0|PME_CTRL_S1)) { if (ctrls[1] == (PME_CTRL_S0|PME_CTRL_S1)) { ctrls[0] = PME_CTRL_S0; ctrls[1] = PME_CTRL_S1; } else { ctrls[0] &= ~ctrls[1]; } } else if (ctrls[1] == (PME_CTRL_S0|PME_CTRL_S1)) { ctrls[1] &= ~ctrls[0]; } else return PFMLIB_ERR_INVAL; } } if (input->pfp_event_count == 1) { if (ctrls[0] == (PME_CTRL_S0|PME_CTRL_S1)) ctrls[0] = PME_CTRL_S0; } for (i = 0; i < input->pfp_event_count; i++) { unsigned long long val = vals[i]; char ctrl = ctrls[i]; switch (ctrl) { case PME_CTRL_S0: output->pfp_pmds[i].reg_num = 0; pcr |= (val << (niagara2 ? PCR_N2_SL0_SHIFT : PCR_S0_SHIFT)); break; case PME_CTRL_S1: output->pfp_pmds[i].reg_num = 1; pcr |= (val << (niagara2 ? PCR_N2_SL1_SHIFT : PCR_S1_SHIFT)); break; default: return PFMLIB_ERR_INVAL; } if (niagara2) { pfmlib_event_t *e = &input->pfp_events[i]; unsigned int j, shift; if (ctrl == PME_CTRL_S0) { pcr |= PCR_N2_TOE0; shift = PCR_N2_MASK0_SHIFT; } else { pcr |= PCR_N2_TOE1; shift = PCR_N2_MASK1_SHIFT; } for (j = 0; j < e->num_masks; j++) { unsigned int mask; mask = e->unit_masks[j]; if (mask >= EVENT_MASK_BITS) return PFMLIB_ERR_INVAL; pcr |= (1ULL << (shift + mask)); } } output->pfp_pmds[i].reg_value = 0; output->pfp_pmds[i].reg_addr = 0; output->pfp_pmds[i].reg_alt_addr = 0; output->pfp_pmds[i].reg_reserved1 = 0; output->pfp_pmd_count = i + 1; } output->pfp_pmcs[0].reg_value = pcr; output->pfp_pmcs[0].reg_addr = 0; output->pfp_pmcs[0].reg_num = 0; output->pfp_pmcs[0].reg_reserved1 = 0; output->pfp_pmc_count = 1; return PFMLIB_SUCCESS; } static int pmu_name_to_pmu_type(char *name) { if (!strcmp(name, "ultra12")) return PFMLIB_SPARC_ULTRA12_PMU; if (!strcmp(name, "ultra3")) return PFMLIB_SPARC_ULTRA3_PMU; if (!strcmp(name, "ultra3i")) return PFMLIB_SPARC_ULTRA3I_PMU; if (!strcmp(name, "ultra3+")) return PFMLIB_SPARC_ULTRA3PLUS_PMU; if (!strcmp(name, "ultra4+")) return PFMLIB_SPARC_ULTRA4PLUS_PMU; if (!strcmp(name, "niagara2")) return PFMLIB_SPARC_NIAGARA2_PMU; if (!strcmp(name, "niagara")) return PFMLIB_SPARC_NIAGARA1_PMU; return -1; } static int pfm_sparc_pmu_detect(void) { int ret, pmu_type, pme_count; char buffer[32]; ret = __pfm_getcpuinfo_attr("pmu", buffer, sizeof(buffer)); if (ret == -1) return PFMLIB_ERR_NOTSUPP; pmu_type = pmu_name_to_pmu_type(buffer); if (pmu_type == -1) return PFMLIB_ERR_NOTSUPP; switch (pmu_type) { default: return PFMLIB_ERR_NOTSUPP; case PFMLIB_SPARC_ULTRA12_PMU: pme_count = PME_ULTRA12_EVENT_COUNT; break; case PFMLIB_SPARC_ULTRA3_PMU: pme_count = PME_ULTRA3_EVENT_COUNT; break; case PFMLIB_SPARC_ULTRA3I_PMU: pme_count = PME_ULTRA3I_EVENT_COUNT; break; case PFMLIB_SPARC_ULTRA3PLUS_PMU: pme_count = PME_ULTRA3PLUS_EVENT_COUNT; break; case PFMLIB_SPARC_ULTRA4PLUS_PMU: pme_count = PME_ULTRA4PLUS_EVENT_COUNT; break; case PFMLIB_SPARC_NIAGARA1_PMU: pme_count = PME_NIAGARA1_EVENT_COUNT; break; case PFMLIB_SPARC_NIAGARA2_PMU: pme_count = PME_NIAGARA2_EVENT_COUNT; break; } sparc_support.pmu_type = pmu_type; sparc_support.pmu_name = strdup(buffer); sparc_support.pme_count = pme_count; return PFMLIB_SUCCESS; } static void pfm_sparc_get_impl_pmcs(pfmlib_regmask_t *impl_pmcs) { impl_pmcs->bits[0] = 0x1; } static void pfm_sparc_get_impl_pmds(pfmlib_regmask_t *impl_pmds) { impl_pmds->bits[0] = 0x3; } static void pfm_sparc_get_impl_counters(pfmlib_regmask_t *impl_counters) { pfm_sparc_get_impl_pmds(impl_counters); } static void pfm_sparc_get_hw_counter_width(unsigned int *width) { *width = 32; } static int pfm_sparc_get_event_desc(unsigned int event, char **desc) { *desc = strdup(get_event_desc(event)); return 0; } static int pfm_sparc_get_event_mask_desc(unsigned int event, unsigned int mask, char **desc) { if (sparc_support.pmu_type != PFMLIB_SPARC_NIAGARA2_PMU) { *desc = strdup(""); } else { pme_sparc_mask_entry_t *e; e = &niagara2_pe[event]; *desc = strdup(e->pme_masks[mask].mask_desc); } return 0; } static int pfm_sparc_get_event_mask_code(unsigned int event, unsigned int mask, unsigned int *code) { if (sparc_support.pmu_type != PFMLIB_SPARC_NIAGARA2_PMU) *code = 0; else *code = mask; return 0; } static int pfm_sparc_get_cycle_event(pfmlib_event_t *e) { switch (sparc_support.pmu_type) { case PFMLIB_SPARC_ULTRA12_PMU: case PFMLIB_SPARC_ULTRA3_PMU: case PFMLIB_SPARC_ULTRA3I_PMU: case PFMLIB_SPARC_ULTRA3PLUS_PMU: case PFMLIB_SPARC_ULTRA4PLUS_PMU: e->event = 0; break; case PFMLIB_SPARC_NIAGARA1_PMU: case PFMLIB_SPARC_NIAGARA2_PMU: default: return PFMLIB_ERR_NOTSUPP; } return PFMLIB_SUCCESS; } static int pfm_sparc_get_inst_retired(pfmlib_event_t *e) { unsigned int i; switch (sparc_support.pmu_type) { case PFMLIB_SPARC_ULTRA12_PMU: case PFMLIB_SPARC_ULTRA3_PMU: case PFMLIB_SPARC_ULTRA3I_PMU: case PFMLIB_SPARC_ULTRA3PLUS_PMU: case PFMLIB_SPARC_ULTRA4PLUS_PMU: e->event = 1; break; case PFMLIB_SPARC_NIAGARA1_PMU: e->event = 0; break; case PFMLIB_SPARC_NIAGARA2_PMU: e->event = 1; e->num_masks = EVENT_MASK_BITS; for (i = 0; i < e->num_masks; i++) e->unit_masks[i] = i; break; default: return PFMLIB_ERR_NOTSUPP; } return PFMLIB_SUCCESS; } /** * sparc_support **/ pfm_pmu_support_t sparc_support = { /* the next 3 fields are initialized in pfm_sparc_pmu_detect */ .pmu_name = NULL, .pmu_type = PFMLIB_UNKNOWN_PMU, .pme_count = 0, .pmd_count = 2, .pmc_count = 1, .num_cnt = 2, .get_event_code = pfm_sparc_get_event_code, .get_event_name = pfm_sparc_get_event_name, .get_event_mask_name = pfm_sparc_get_event_mask_name, .get_event_counters = pfm_sparc_get_event_counters, .get_num_event_masks = pfm_sparc_get_num_event_masks, .dispatch_events = pfm_sparc_dispatch_events, .pmu_detect = pfm_sparc_pmu_detect, .get_impl_pmcs = pfm_sparc_get_impl_pmcs, .get_impl_pmds = pfm_sparc_get_impl_pmds, .get_impl_counters = pfm_sparc_get_impl_counters, .get_hw_counter_width = pfm_sparc_get_hw_counter_width, .get_event_desc = pfm_sparc_get_event_desc, .get_event_mask_desc = pfm_sparc_get_event_mask_desc, .get_event_mask_code = pfm_sparc_get_event_mask_code, .get_cycle_event = pfm_sparc_get_cycle_event, .get_inst_retired_event = pfm_sparc_get_inst_retired }; papi-5.5.1/src/libpfm-3.y/lib/ppc970_events.h0000644000307100002310000041101613013651450020452 0ustar yarkhangraduate/****************************/ /* THIS IS OPEN SOURCE CODE */ /****************************/ #ifndef __PPC970_EVENTS_H__ #define __PPC970_EVENTS_H__ /* * File: ppc970_events.h * CVS: * Author: Corey Ashford * cjashfor@us.ibm.com * Mods: * * * (C) Copyright IBM Corporation, 2007. All Rights Reserved. * Contributed by Corey Ashford * * Note: This code was automatically generated and should not be modified by * hand. * */ #define PPC970_PME_PM_LSU_REJECT_RELOAD_CDF 0 #define PPC970_PME_PM_MRK_LSU_SRQ_INST_VALID 1 #define PPC970_PME_PM_FPU1_SINGLE 2 #define PPC970_PME_PM_FPU0_STALL3 3 #define PPC970_PME_PM_TB_BIT_TRANS 4 #define PPC970_PME_PM_GPR_MAP_FULL_CYC 5 #define PPC970_PME_PM_MRK_ST_CMPL 6 #define PPC970_PME_PM_FPU0_STF 7 #define PPC970_PME_PM_FPU1_FMA 8 #define PPC970_PME_PM_LSU1_FLUSH_ULD 9 #define PPC970_PME_PM_MRK_INST_FIN 10 #define PPC970_PME_PM_MRK_LSU0_FLUSH_UST 11 #define PPC970_PME_PM_LSU_LRQ_S0_ALLOC 12 #define PPC970_PME_PM_FPU_FDIV 13 #define PPC970_PME_PM_FPU0_FULL_CYC 14 #define PPC970_PME_PM_FPU_SINGLE 15 #define PPC970_PME_PM_FPU0_FMA 16 #define PPC970_PME_PM_MRK_LSU1_FLUSH_ULD 17 #define PPC970_PME_PM_LSU1_FLUSH_LRQ 18 #define PPC970_PME_PM_DTLB_MISS 19 #define PPC970_PME_PM_MRK_ST_MISS_L1 20 #define PPC970_PME_PM_EXT_INT 21 #define PPC970_PME_PM_MRK_LSU1_FLUSH_LRQ 22 #define PPC970_PME_PM_MRK_ST_GPS 23 #define PPC970_PME_PM_GRP_DISP_SUCCESS 24 #define PPC970_PME_PM_LSU1_LDF 25 #define PPC970_PME_PM_LSU0_SRQ_STFWD 26 #define PPC970_PME_PM_CR_MAP_FULL_CYC 27 #define PPC970_PME_PM_MRK_LSU0_FLUSH_ULD 28 #define PPC970_PME_PM_LSU_DERAT_MISS 29 #define PPC970_PME_PM_FPU0_SINGLE 30 #define PPC970_PME_PM_FPU1_FDIV 31 #define PPC970_PME_PM_FPU1_FEST 32 #define PPC970_PME_PM_FPU0_FRSP_FCONV 33 #define PPC970_PME_PM_GCT_EMPTY_SRQ_FULL 34 #define PPC970_PME_PM_MRK_ST_CMPL_INT 35 #define PPC970_PME_PM_FLUSH_BR_MPRED 36 #define PPC970_PME_PM_FXU_FIN 37 #define PPC970_PME_PM_FPU_STF 38 #define PPC970_PME_PM_DSLB_MISS 39 #define PPC970_PME_PM_FXLS1_FULL_CYC 40 #define PPC970_PME_PM_LSU_LMQ_LHR_MERGE 41 #define PPC970_PME_PM_MRK_STCX_FAIL 42 #define PPC970_PME_PM_FXU0_BUSY_FXU1_IDLE 43 #define PPC970_PME_PM_MRK_DATA_FROM_L25_SHR 44 #define PPC970_PME_PM_LSU_FLUSH_ULD 45 #define PPC970_PME_PM_MRK_BRU_FIN 46 #define PPC970_PME_PM_IERAT_XLATE_WR 47 #define PPC970_PME_PM_DATA_FROM_MEM 48 #define PPC970_PME_PM_FPR_MAP_FULL_CYC 49 #define PPC970_PME_PM_FPU1_FULL_CYC 50 #define PPC970_PME_PM_FPU0_FIN 51 #define PPC970_PME_PM_GRP_BR_REDIR 52 #define PPC970_PME_PM_THRESH_TIMEO 53 #define PPC970_PME_PM_FPU_FSQRT 54 #define PPC970_PME_PM_MRK_LSU0_FLUSH_LRQ 55 #define PPC970_PME_PM_PMC1_OVERFLOW 56 #define PPC970_PME_PM_FXLS0_FULL_CYC 57 #define PPC970_PME_PM_FPU0_ALL 58 #define PPC970_PME_PM_DATA_TABLEWALK_CYC 59 #define PPC970_PME_PM_FPU0_FEST 60 #define PPC970_PME_PM_DATA_FROM_L25_MOD 61 #define PPC970_PME_PM_LSU0_REJECT_ERAT_MISS 62 #define PPC970_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 63 #define PPC970_PME_PM_LSU0_REJECT_RELOAD_CDF 64 #define PPC970_PME_PM_FPU_FEST 65 #define PPC970_PME_PM_0INST_FETCH 66 #define PPC970_PME_PM_LD_MISS_L1_LSU0 67 #define PPC970_PME_PM_LSU1_REJECT_RELOAD_CDF 68 #define PPC970_PME_PM_L1_PREF 69 #define PPC970_PME_PM_FPU1_STALL3 70 #define PPC970_PME_PM_BRQ_FULL_CYC 71 #define PPC970_PME_PM_PMC8_OVERFLOW 72 #define PPC970_PME_PM_PMC7_OVERFLOW 73 #define PPC970_PME_PM_WORK_HELD 74 #define PPC970_PME_PM_MRK_LD_MISS_L1_LSU0 75 #define PPC970_PME_PM_FXU_IDLE 76 #define PPC970_PME_PM_INST_CMPL 77 #define PPC970_PME_PM_LSU1_FLUSH_UST 78 #define PPC970_PME_PM_LSU0_FLUSH_ULD 79 #define PPC970_PME_PM_LSU_FLUSH 80 #define PPC970_PME_PM_INST_FROM_L2 81 #define PPC970_PME_PM_LSU1_REJECT_LMQ_FULL 82 #define PPC970_PME_PM_PMC2_OVERFLOW 83 #define PPC970_PME_PM_FPU0_DENORM 84 #define PPC970_PME_PM_FPU1_FMOV_FEST 85 #define PPC970_PME_PM_GRP_DISP_REJECT 86 #define PPC970_PME_PM_LSU_LDF 87 #define PPC970_PME_PM_INST_DISP 88 #define PPC970_PME_PM_DATA_FROM_L25_SHR 89 #define PPC970_PME_PM_L1_DCACHE_RELOAD_VALID 90 #define PPC970_PME_PM_MRK_GRP_ISSUED 91 #define PPC970_PME_PM_FPU_FMA 92 #define PPC970_PME_PM_MRK_CRU_FIN 93 #define PPC970_PME_PM_MRK_LSU1_FLUSH_UST 94 #define PPC970_PME_PM_MRK_FXU_FIN 95 #define PPC970_PME_PM_LSU1_REJECT_ERAT_MISS 96 #define PPC970_PME_PM_BR_ISSUED 97 #define PPC970_PME_PM_PMC4_OVERFLOW 98 #define PPC970_PME_PM_EE_OFF 99 #define PPC970_PME_PM_INST_FROM_L25_MOD 100 #define PPC970_PME_PM_ITLB_MISS 101 #define PPC970_PME_PM_FXU1_BUSY_FXU0_IDLE 102 #define PPC970_PME_PM_GRP_DISP_VALID 103 #define PPC970_PME_PM_MRK_GRP_DISP 104 #define PPC970_PME_PM_LSU_FLUSH_UST 105 #define PPC970_PME_PM_FXU1_FIN 106 #define PPC970_PME_PM_GRP_CMPL 107 #define PPC970_PME_PM_FPU_FRSP_FCONV 108 #define PPC970_PME_PM_MRK_LSU0_FLUSH_SRQ 109 #define PPC970_PME_PM_LSU_LMQ_FULL_CYC 110 #define PPC970_PME_PM_ST_REF_L1_LSU0 111 #define PPC970_PME_PM_LSU0_DERAT_MISS 112 #define PPC970_PME_PM_LSU_SRQ_SYNC_CYC 113 #define PPC970_PME_PM_FPU_STALL3 114 #define PPC970_PME_PM_LSU_REJECT_ERAT_MISS 115 #define PPC970_PME_PM_MRK_DATA_FROM_L2 116 #define PPC970_PME_PM_LSU0_FLUSH_SRQ 117 #define PPC970_PME_PM_FPU0_FMOV_FEST 118 #define PPC970_PME_PM_LD_REF_L1_LSU0 119 #define PPC970_PME_PM_LSU1_FLUSH_SRQ 120 #define PPC970_PME_PM_GRP_BR_MPRED 121 #define PPC970_PME_PM_LSU_LMQ_S0_ALLOC 122 #define PPC970_PME_PM_LSU0_REJECT_LMQ_FULL 123 #define PPC970_PME_PM_ST_REF_L1 124 #define PPC970_PME_PM_MRK_VMX_FIN 125 #define PPC970_PME_PM_LSU_SRQ_EMPTY_CYC 126 #define PPC970_PME_PM_FPU1_STF 127 #define PPC970_PME_PM_RUN_CYC 128 #define PPC970_PME_PM_LSU_LMQ_S0_VALID 129 #define PPC970_PME_PM_LSU0_LDF 130 #define PPC970_PME_PM_LSU_LRQ_S0_VALID 131 #define PPC970_PME_PM_PMC3_OVERFLOW 132 #define PPC970_PME_PM_MRK_IMR_RELOAD 133 #define PPC970_PME_PM_MRK_GRP_TIMEO 134 #define PPC970_PME_PM_FPU_FMOV_FEST 135 #define PPC970_PME_PM_GRP_DISP_BLK_SB_CYC 136 #define PPC970_PME_PM_XER_MAP_FULL_CYC 137 #define PPC970_PME_PM_ST_MISS_L1 138 #define PPC970_PME_PM_STOP_COMPLETION 139 #define PPC970_PME_PM_MRK_GRP_CMPL 140 #define PPC970_PME_PM_ISLB_MISS 141 #define PPC970_PME_PM_SUSPENDED 142 #define PPC970_PME_PM_CYC 143 #define PPC970_PME_PM_LD_MISS_L1_LSU1 144 #define PPC970_PME_PM_STCX_FAIL 145 #define PPC970_PME_PM_LSU1_SRQ_STFWD 146 #define PPC970_PME_PM_GRP_DISP 147 #define PPC970_PME_PM_L2_PREF 148 #define PPC970_PME_PM_FPU1_DENORM 149 #define PPC970_PME_PM_DATA_FROM_L2 150 #define PPC970_PME_PM_FPU0_FPSCR 151 #define PPC970_PME_PM_MRK_DATA_FROM_L25_MOD 152 #define PPC970_PME_PM_FPU0_FSQRT 153 #define PPC970_PME_PM_LD_REF_L1 154 #define PPC970_PME_PM_MRK_L1_RELOAD_VALID 155 #define PPC970_PME_PM_1PLUS_PPC_CMPL 156 #define PPC970_PME_PM_INST_FROM_L1 157 #define PPC970_PME_PM_EE_OFF_EXT_INT 158 #define PPC970_PME_PM_PMC6_OVERFLOW 159 #define PPC970_PME_PM_LSU_LRQ_FULL_CYC 160 #define PPC970_PME_PM_IC_PREF_INSTALL 161 #define PPC970_PME_PM_DC_PREF_OUT_OF_STREAMS 162 #define PPC970_PME_PM_MRK_LSU1_FLUSH_SRQ 163 #define PPC970_PME_PM_GCT_FULL_CYC 164 #define PPC970_PME_PM_INST_FROM_MEM 165 #define PPC970_PME_PM_FLUSH_LSU_BR_MPRED 166 #define PPC970_PME_PM_FXU_BUSY 167 #define PPC970_PME_PM_ST_REF_L1_LSU1 168 #define PPC970_PME_PM_MRK_LD_MISS_L1 169 #define PPC970_PME_PM_L1_WRITE_CYC 170 #define PPC970_PME_PM_LSU_REJECT_LMQ_FULL 171 #define PPC970_PME_PM_FPU_ALL 172 #define PPC970_PME_PM_LSU_SRQ_S0_ALLOC 173 #define PPC970_PME_PM_INST_FROM_L25_SHR 174 #define PPC970_PME_PM_GRP_MRK 175 #define PPC970_PME_PM_BR_MPRED_CR 176 #define PPC970_PME_PM_DC_PREF_STREAM_ALLOC 177 #define PPC970_PME_PM_FPU1_FIN 178 #define PPC970_PME_PM_LSU_REJECT_SRQ 179 #define PPC970_PME_PM_BR_MPRED_TA 180 #define PPC970_PME_PM_CRQ_FULL_CYC 181 #define PPC970_PME_PM_LD_MISS_L1 182 #define PPC970_PME_PM_INST_FROM_PREF 183 #define PPC970_PME_PM_STCX_PASS 184 #define PPC970_PME_PM_DC_INV_L2 185 #define PPC970_PME_PM_LSU_SRQ_FULL_CYC 186 #define PPC970_PME_PM_LSU0_FLUSH_LRQ 187 #define PPC970_PME_PM_LSU_SRQ_S0_VALID 188 #define PPC970_PME_PM_LARX_LSU0 189 #define PPC970_PME_PM_GCT_EMPTY_CYC 190 #define PPC970_PME_PM_FPU1_ALL 191 #define PPC970_PME_PM_FPU1_FSQRT 192 #define PPC970_PME_PM_FPU_FIN 193 #define PPC970_PME_PM_LSU_SRQ_STFWD 194 #define PPC970_PME_PM_MRK_LD_MISS_L1_LSU1 195 #define PPC970_PME_PM_FXU0_FIN 196 #define PPC970_PME_PM_MRK_FPU_FIN 197 #define PPC970_PME_PM_PMC5_OVERFLOW 198 #define PPC970_PME_PM_SNOOP_TLBIE 199 #define PPC970_PME_PM_FPU1_FRSP_FCONV 200 #define PPC970_PME_PM_FPU0_FDIV 201 #define PPC970_PME_PM_LD_REF_L1_LSU1 202 #define PPC970_PME_PM_HV_CYC 203 #define PPC970_PME_PM_LR_CTR_MAP_FULL_CYC 204 #define PPC970_PME_PM_FPU_DENORM 205 #define PPC970_PME_PM_LSU0_REJECT_SRQ 206 #define PPC970_PME_PM_LSU1_REJECT_SRQ 207 #define PPC970_PME_PM_LSU1_DERAT_MISS 208 #define PPC970_PME_PM_IC_PREF_REQ 209 #define PPC970_PME_PM_MRK_LSU_FIN 210 #define PPC970_PME_PM_MRK_DATA_FROM_MEM 211 #define PPC970_PME_PM_LSU0_FLUSH_UST 212 #define PPC970_PME_PM_LSU_FLUSH_LRQ 213 #define PPC970_PME_PM_LSU_FLUSH_SRQ 214 static const int ppc970_event_ids[][PPC970_NUM_EVENT_COUNTERS] = { [ PPC970_PME_PM_LSU_REJECT_RELOAD_CDF ] = { -1, -1, -1, -1, -1, 68, -1, -1 }, [ PPC970_PME_PM_MRK_LSU_SRQ_INST_VALID ] = { -1, -1, 63, 61, -1, -1, 60, 61 }, [ PPC970_PME_PM_FPU1_SINGLE ] = { 23, 22, -1, -1, 24, 23, -1, -1 }, [ PPC970_PME_PM_FPU0_STALL3 ] = { 15, 14, -1, -1, 16, 15, -1, -1 }, [ PPC970_PME_PM_TB_BIT_TRANS ] = { -1, -1, -1, -1, -1, -1, -1, 67 }, [ PPC970_PME_PM_GPR_MAP_FULL_CYC ] = { -1, -1, 28, 28, -1, -1, 27, 27 }, [ PPC970_PME_PM_MRK_ST_CMPL ] = { 79, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_FPU0_STF ] = { 16, 15, -1, -1, 17, 16, -1, -1 }, [ PPC970_PME_PM_FPU1_FMA ] = { 20, 19, -1, -1, 21, 20, -1, -1 }, [ PPC970_PME_PM_LSU1_FLUSH_ULD ] = { 58, 57, -1, -1, 60, 57, -1, -1 }, [ PPC970_PME_PM_MRK_INST_FIN ] = { -1, -1, -1, -1, -1, -1, 50, -1 }, [ PPC970_PME_PM_MRK_LSU0_FLUSH_UST ] = { -1, -1, 58, 56, -1, -1, 55, 55 }, [ PPC970_PME_PM_LSU_LRQ_S0_ALLOC ] = { 66, 66, -1, -1, 68, 66, -1, -1 }, [ PPC970_PME_PM_FPU_FDIV ] = { 27, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_FPU0_FULL_CYC ] = { 13, 12, -1, -1, 14, 13, -1, -1 }, [ PPC970_PME_PM_FPU_SINGLE ] = { -1, -1, -1, -1, 28, -1, -1, -1 }, [ PPC970_PME_PM_FPU0_FMA ] = { 11, 10, -1, -1, 12, 11, -1, -1 }, [ PPC970_PME_PM_MRK_LSU1_FLUSH_ULD ] = { -1, -1, 61, 59, -1, -1, 58, 58 }, [ PPC970_PME_PM_LSU1_FLUSH_LRQ ] = { 56, 55, -1, -1, 58, 55, -1, -1 }, [ PPC970_PME_PM_DTLB_MISS ] = { 6, 5, -1, -1, 7, 6, -1, -1 }, [ PPC970_PME_PM_MRK_ST_MISS_L1 ] = { 80, 76, -1, -1, 79, 79, -1, -1 }, [ PPC970_PME_PM_EXT_INT ] = { -1, -1, -1, -1, -1, -1, -1, 10 }, [ PPC970_PME_PM_MRK_LSU1_FLUSH_LRQ ] = { -1, -1, 59, 57, -1, -1, 56, 56 }, [ PPC970_PME_PM_MRK_ST_GPS ] = { -1, -1, -1, -1, -1, 78, -1, -1 }, [ PPC970_PME_PM_GRP_DISP_SUCCESS ] = { -1, -1, -1, -1, 34, -1, -1, -1 }, [ PPC970_PME_PM_LSU1_LDF ] = { -1, -1, 43, 40, -1, -1, 40, 41 }, [ PPC970_PME_PM_LSU0_SRQ_STFWD ] = { 54, 53, -1, -1, 56, 53, -1, -1 }, [ PPC970_PME_PM_CR_MAP_FULL_CYC ] = { 1, 1, -1, -1, 2, 1, -1, -1 }, [ PPC970_PME_PM_MRK_LSU0_FLUSH_ULD ] = { -1, -1, 57, 55, -1, -1, 54, 54 }, [ PPC970_PME_PM_LSU_DERAT_MISS ] = { -1, -1, -1, -1, -1, 64, -1, -1 }, [ PPC970_PME_PM_FPU0_SINGLE ] = { 14, 13, -1, -1, 15, 14, -1, -1 }, [ PPC970_PME_PM_FPU1_FDIV ] = { 19, 18, -1, -1, 20, 19, -1, -1 }, [ PPC970_PME_PM_FPU1_FEST ] = { -1, -1, 18, 18, -1, -1, 17, 18 }, [ PPC970_PME_PM_FPU0_FRSP_FCONV ] = { -1, -1, 17, 17, -1, -1, 16, 17 }, [ PPC970_PME_PM_GCT_EMPTY_SRQ_FULL ] = { -1, 27, -1, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_MRK_ST_CMPL_INT ] = { -1, -1, 64, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_FLUSH_BR_MPRED ] = { -1, -1, 11, 11, -1, -1, 10, 11 }, [ PPC970_PME_PM_FXU_FIN ] = { -1, -1, 27, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_FPU_STF ] = { -1, -1, -1, -1, -1, 27, -1, -1 }, [ PPC970_PME_PM_DSLB_MISS ] = { 5, 4, -1, -1, 6, 5, -1, -1 }, [ PPC970_PME_PM_FXLS1_FULL_CYC ] = { -1, -1, 24, 24, -1, -1, 23, 24 }, [ PPC970_PME_PM_LSU_LMQ_LHR_MERGE ] = { -1, -1, 46, 43, -1, -1, 43, 45 }, [ PPC970_PME_PM_MRK_STCX_FAIL ] = { 78, 75, -1, -1, 78, 77, -1, -1 }, [ PPC970_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { -1, -1, -1, -1, -1, -1, 24, -1 }, [ PPC970_PME_PM_MRK_DATA_FROM_L25_SHR ] = { -1, -1, -1, -1, 73, -1, -1, -1 }, [ PPC970_PME_PM_LSU_FLUSH_ULD ] = { 65, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_MRK_BRU_FIN ] = { -1, 71, -1, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_IERAT_XLATE_WR ] = { 36, 36, -1, -1, 39, 36, -1, -1 }, [ PPC970_PME_PM_DATA_FROM_MEM ] = { -1, -1, 5, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_FPR_MAP_FULL_CYC ] = { 7, 6, -1, -1, 8, 7, -1, -1 }, [ PPC970_PME_PM_FPU1_FULL_CYC ] = { 22, 21, -1, -1, 23, 22, -1, -1 }, [ PPC970_PME_PM_FPU0_FIN ] = { -1, -1, 14, 14, -1, -1, 13, 14 }, [ PPC970_PME_PM_GRP_BR_REDIR ] = { 31, 30, -1, -1, 32, 31, -1, -1 }, [ PPC970_PME_PM_THRESH_TIMEO ] = { -1, 83, -1, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_FPU_FSQRT ] = { -1, -1, -1, -1, -1, 26, -1, -1 }, [ PPC970_PME_PM_MRK_LSU0_FLUSH_LRQ ] = { -1, -1, 55, 53, -1, -1, 52, 52 }, [ PPC970_PME_PM_PMC1_OVERFLOW ] = { -1, 77, -1, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_FXLS0_FULL_CYC ] = { -1, -1, 23, 23, -1, -1, 22, 23 }, [ PPC970_PME_PM_FPU0_ALL ] = { 8, 7, -1, -1, 9, 8, -1, -1 }, [ PPC970_PME_PM_DATA_TABLEWALK_CYC ] = { 4, 3, -1, -1, 5, 4, -1, -1 }, [ PPC970_PME_PM_FPU0_FEST ] = { -1, -1, 13, 13, -1, -1, 12, 13 }, [ PPC970_PME_PM_DATA_FROM_L25_MOD ] = { -1, -1, -1, -1, -1, 3, -1, -1 }, [ PPC970_PME_PM_LSU0_REJECT_ERAT_MISS ] = { 50, 49, -1, -1, 52, 49, -1, -1 }, [ PPC970_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { -1, 65, 49, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_LSU0_REJECT_RELOAD_CDF ] = { 52, 51, -1, -1, 54, 51, -1, -1 }, [ PPC970_PME_PM_FPU_FEST ] = { -1, -1, 22, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_0INST_FETCH ] = { -1, -1, -1, 0, -1, -1, -1, -1 }, [ PPC970_PME_PM_LD_MISS_L1_LSU0 ] = { -1, -1, 38, 35, -1, -1, 35, 35 }, [ PPC970_PME_PM_LSU1_REJECT_RELOAD_CDF ] = { 62, 61, -1, -1, 64, 61, -1, -1 }, [ PPC970_PME_PM_L1_PREF ] = { -1, -1, 34, 32, -1, -1, 32, 32 }, [ PPC970_PME_PM_FPU1_STALL3 ] = { 24, 23, -1, -1, 25, 24, -1, -1 }, [ PPC970_PME_PM_BRQ_FULL_CYC ] = { 0, 0, -1, -1, 1, 0, -1, -1 }, [ PPC970_PME_PM_PMC8_OVERFLOW ] = { 81, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_PMC7_OVERFLOW ] = { -1, -1, -1, -1, -1, -1, -1, 62 }, [ PPC970_PME_PM_WORK_HELD ] = { -1, 84, -1, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_MRK_LD_MISS_L1_LSU0 ] = { 76, 73, -1, -1, 76, 75, -1, -1 }, [ PPC970_PME_PM_FXU_IDLE ] = { -1, -1, -1, -1, 29, -1, -1, -1 }, [ PPC970_PME_PM_INST_CMPL ] = { 37, 37, 31, 30, 40, 37, 30, 30 }, [ PPC970_PME_PM_LSU1_FLUSH_UST ] = { 59, 58, -1, -1, 61, 58, -1, -1 }, [ PPC970_PME_PM_LSU0_FLUSH_ULD ] = { 48, 47, -1, -1, 50, 47, -1, -1 }, [ PPC970_PME_PM_LSU_FLUSH ] = { -1, -1, 44, 41, -1, -1, 41, 42 }, [ PPC970_PME_PM_INST_FROM_L2 ] = { 40, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_LSU1_REJECT_LMQ_FULL ] = { 61, 60, -1, -1, 63, 60, -1, -1 }, [ PPC970_PME_PM_PMC2_OVERFLOW ] = { -1, -1, 66, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_FPU0_DENORM ] = { 9, 8, -1, -1, 10, 9, -1, -1 }, [ PPC970_PME_PM_FPU1_FMOV_FEST ] = { -1, -1, 20, 20, -1, -1, 19, 20 }, [ PPC970_PME_PM_GRP_DISP_REJECT ] = { 32, 32, -1, -1, 33, 32, -1, 29 }, [ PPC970_PME_PM_LSU_LDF ] = { -1, -1, -1, -1, -1, -1, -1, 43 }, [ PPC970_PME_PM_INST_DISP ] = { 38, 38, -1, -1, 41, 38, -1, -1 }, [ PPC970_PME_PM_DATA_FROM_L25_SHR ] = { -1, -1, -1, -1, 4, -1, -1, -1 }, [ PPC970_PME_PM_L1_DCACHE_RELOAD_VALID ] = { -1, -1, 33, 31, -1, -1, 31, 31 }, [ PPC970_PME_PM_MRK_GRP_ISSUED ] = { -1, -1, -1, -1, -1, 73, -1, -1 }, [ PPC970_PME_PM_FPU_FMA ] = { -1, 25, -1, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_MRK_CRU_FIN ] = { -1, -1, -1, 50, -1, -1, -1, -1 }, [ PPC970_PME_PM_MRK_LSU1_FLUSH_UST ] = { -1, -1, 62, 60, -1, -1, 59, 59 }, [ PPC970_PME_PM_MRK_FXU_FIN ] = { -1, -1, -1, -1, -1, 72, -1, -1 }, [ PPC970_PME_PM_LSU1_REJECT_ERAT_MISS ] = { 60, 59, -1, -1, 62, 59, -1, -1 }, [ PPC970_PME_PM_BR_ISSUED ] = { -1, -1, 0, 1, -1, -1, 0, 0 }, [ PPC970_PME_PM_PMC4_OVERFLOW ] = { -1, -1, -1, -1, 80, -1, -1, -1 }, [ PPC970_PME_PM_EE_OFF ] = { -1, -1, 9, 9, -1, -1, 8, 8 }, [ PPC970_PME_PM_INST_FROM_L25_MOD ] = { -1, -1, -1, -1, -1, 39, -1, -1 }, [ PPC970_PME_PM_ITLB_MISS ] = { 42, 41, -1, -1, 44, 41, -1, -1 }, [ PPC970_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { -1, -1, -1, 26, -1, -1, -1, -1 }, [ PPC970_PME_PM_GRP_DISP_VALID ] = { 33, 33, -1, -1, 35, 33, -1, -1 }, [ PPC970_PME_PM_MRK_GRP_DISP ] = { 73, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_LSU_FLUSH_UST ] = { -1, 64, -1, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_FXU1_FIN ] = { -1, -1, 26, 27, -1, -1, 26, 26 }, [ PPC970_PME_PM_GRP_CMPL ] = { -1, -1, -1, -1, -1, -1, 28, -1 }, [ PPC970_PME_PM_FPU_FRSP_FCONV ] = { -1, -1, -1, -1, -1, -1, 21, -1 }, [ PPC970_PME_PM_MRK_LSU0_FLUSH_SRQ ] = { -1, -1, 56, 54, -1, -1, 53, 53 }, [ PPC970_PME_PM_LSU_LMQ_FULL_CYC ] = { -1, -1, 45, 42, -1, -1, 42, 44 }, [ PPC970_PME_PM_ST_REF_L1_LSU0 ] = { -1, -1, 69, 64, -1, -1, 64, 64 }, [ PPC970_PME_PM_LSU0_DERAT_MISS ] = { 45, 44, -1, -1, 47, 44, -1, -1 }, [ PPC970_PME_PM_LSU_SRQ_SYNC_CYC ] = { -1, -1, 52, 49, -1, -1, 48, 50 }, [ PPC970_PME_PM_FPU_STALL3 ] = { -1, 26, -1, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_LSU_REJECT_ERAT_MISS ] = { -1, -1, -1, -1, 70, -1, -1, -1 }, [ PPC970_PME_PM_MRK_DATA_FROM_L2 ] = { 72, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_LSU0_FLUSH_SRQ ] = { 47, 46, -1, -1, 49, 46, -1, -1 }, [ PPC970_PME_PM_FPU0_FMOV_FEST ] = { -1, -1, 15, 15, -1, -1, 14, 15 }, [ PPC970_PME_PM_LD_REF_L1_LSU0 ] = { -1, -1, 40, 37, -1, -1, 37, 38 }, [ PPC970_PME_PM_LSU1_FLUSH_SRQ ] = { 57, 56, -1, -1, 59, 56, -1, -1 }, [ PPC970_PME_PM_GRP_BR_MPRED ] = { 30, 29, -1, -1, 31, 30, -1, -1 }, [ PPC970_PME_PM_LSU_LMQ_S0_ALLOC ] = { -1, -1, 47, 44, -1, -1, 44, 46 }, [ PPC970_PME_PM_LSU0_REJECT_LMQ_FULL ] = { 51, 50, -1, -1, 53, 50, -1, -1 }, [ PPC970_PME_PM_ST_REF_L1 ] = { -1, -1, -1, -1, -1, -1, 63, -1 }, [ PPC970_PME_PM_MRK_VMX_FIN ] = { -1, -1, 65, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_LSU_SRQ_EMPTY_CYC ] = { -1, -1, -1, 47, -1, -1, -1, -1 }, [ PPC970_PME_PM_FPU1_STF ] = { 25, 24, -1, -1, 26, 25, -1, -1 }, [ PPC970_PME_PM_RUN_CYC ] = { 82, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_LSU_LMQ_S0_VALID ] = { -1, -1, 48, 45, -1, -1, 45, 47 }, [ PPC970_PME_PM_LSU0_LDF ] = { -1, -1, 42, 39, -1, -1, 39, 40 }, [ PPC970_PME_PM_LSU_LRQ_S0_VALID ] = { 67, 67, -1, -1, 69, 67, -1, -1 }, [ PPC970_PME_PM_PMC3_OVERFLOW ] = { -1, -1, -1, 62, -1, -1, -1, -1 }, [ PPC970_PME_PM_MRK_IMR_RELOAD ] = { 74, 72, -1, -1, 75, 74, -1, -1 }, [ PPC970_PME_PM_MRK_GRP_TIMEO ] = { -1, -1, -1, -1, 74, -1, -1, -1 }, [ PPC970_PME_PM_FPU_FMOV_FEST ] = { -1, -1, -1, -1, -1, -1, -1, 22 }, [ PPC970_PME_PM_GRP_DISP_BLK_SB_CYC ] = { -1, -1, 29, 29, -1, -1, 29, 28 }, [ PPC970_PME_PM_XER_MAP_FULL_CYC ] = { 88, 85, -1, -1, 86, 86, -1, -1 }, [ PPC970_PME_PM_ST_MISS_L1 ] = { 86, 81, 68, 63, 84, 84, 62, 63 }, [ PPC970_PME_PM_STOP_COMPLETION ] = { -1, -1, 67, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_MRK_GRP_CMPL ] = { -1, -1, -1, 51, -1, -1, -1, -1 }, [ PPC970_PME_PM_ISLB_MISS ] = { 41, 40, -1, -1, 43, 40, -1, -1 }, [ PPC970_PME_PM_SUSPENDED ] = { 87, 82, 71, 66, 85, 85, 66, 66 }, [ PPC970_PME_PM_CYC ] = { 2, 2, 4, 5, 3, 2, 4, 4 }, [ PPC970_PME_PM_LD_MISS_L1_LSU1 ] = { -1, -1, 39, 36, -1, -1, 36, 36 }, [ PPC970_PME_PM_STCX_FAIL ] = { 84, 79, -1, -1, 82, 82, -1, -1 }, [ PPC970_PME_PM_LSU1_SRQ_STFWD ] = { 64, 63, -1, -1, 66, 63, -1, -1 }, [ PPC970_PME_PM_GRP_DISP ] = { -1, 31, -1, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_L2_PREF ] = { -1, -1, 36, 34, -1, -1, 34, 34 }, [ PPC970_PME_PM_FPU1_DENORM ] = { 18, 17, -1, -1, 19, 18, -1, -1 }, [ PPC970_PME_PM_DATA_FROM_L2 ] = { 3, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_FPU0_FPSCR ] = { -1, -1, 16, 16, -1, -1, 15, 16 }, [ PPC970_PME_PM_MRK_DATA_FROM_L25_MOD ] = { -1, -1, -1, -1, -1, 71, -1, -1 }, [ PPC970_PME_PM_FPU0_FSQRT ] = { 12, 11, -1, -1, 13, 12, -1, -1 }, [ PPC970_PME_PM_LD_REF_L1 ] = { -1, -1, -1, -1, -1, -1, -1, 37 }, [ PPC970_PME_PM_MRK_L1_RELOAD_VALID ] = { -1, -1, 54, 52, -1, -1, 51, 51 }, [ PPC970_PME_PM_1PLUS_PPC_CMPL ] = { -1, -1, -1, -1, 0, -1, -1, -1 }, [ PPC970_PME_PM_INST_FROM_L1 ] = { 39, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_EE_OFF_EXT_INT ] = { -1, -1, 10, 10, -1, -1, 9, 9 }, [ PPC970_PME_PM_PMC6_OVERFLOW ] = { -1, -1, -1, -1, -1, -1, 61, -1 }, [ PPC970_PME_PM_LSU_LRQ_FULL_CYC ] = { -1, -1, 50, 46, -1, -1, 46, 48 }, [ PPC970_PME_PM_IC_PREF_INSTALL ] = { 34, 34, -1, -1, 37, 34, -1, -1 }, [ PPC970_PME_PM_DC_PREF_OUT_OF_STREAMS ] = { -1, -1, 7, 7, -1, -1, 6, 6 }, [ PPC970_PME_PM_MRK_LSU1_FLUSH_SRQ ] = { -1, -1, 60, 58, -1, -1, 57, 57 }, [ PPC970_PME_PM_GCT_FULL_CYC ] = { 29, 28, -1, -1, 30, 29, -1, -1 }, [ PPC970_PME_PM_INST_FROM_MEM ] = { -1, 39, -1, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_FLUSH_LSU_BR_MPRED ] = { -1, -1, 12, 12, -1, -1, 11, 12 }, [ PPC970_PME_PM_FXU_BUSY ] = { -1, -1, -1, -1, -1, 28, -1, -1 }, [ PPC970_PME_PM_ST_REF_L1_LSU1 ] = { -1, -1, 70, 65, -1, -1, 65, 65 }, [ PPC970_PME_PM_MRK_LD_MISS_L1 ] = { 75, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_L1_WRITE_CYC ] = { -1, -1, 35, 33, -1, -1, 33, 33 }, [ PPC970_PME_PM_LSU_REJECT_LMQ_FULL ] = { -1, 68, -1, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_FPU_ALL ] = { -1, -1, -1, -1, 27, -1, -1, -1 }, [ PPC970_PME_PM_LSU_SRQ_S0_ALLOC ] = { 69, 69, -1, -1, 71, 69, -1, -1 }, [ PPC970_PME_PM_INST_FROM_L25_SHR ] = { -1, -1, -1, -1, 42, -1, -1, -1 }, [ PPC970_PME_PM_GRP_MRK ] = { -1, -1, -1, -1, 36, -1, -1, -1 }, [ PPC970_PME_PM_BR_MPRED_CR ] = { -1, -1, 1, 2, -1, -1, 1, 1 }, [ PPC970_PME_PM_DC_PREF_STREAM_ALLOC ] = { -1, -1, 8, 8, -1, -1, 7, 7 }, [ PPC970_PME_PM_FPU1_FIN ] = { -1, -1, 19, 19, -1, -1, 18, 19 }, [ PPC970_PME_PM_LSU_REJECT_SRQ ] = { 68, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_BR_MPRED_TA ] = { -1, -1, 2, 3, -1, -1, 2, 2 }, [ PPC970_PME_PM_CRQ_FULL_CYC ] = { -1, -1, 3, 4, -1, -1, 3, 3 }, [ PPC970_PME_PM_LD_MISS_L1 ] = { -1, -1, 37, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_INST_FROM_PREF ] = { -1, -1, 32, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_STCX_PASS ] = { 85, 80, -1, -1, 83, 83, -1, -1 }, [ PPC970_PME_PM_DC_INV_L2 ] = { -1, -1, 6, 6, -1, -1, 5, 5 }, [ PPC970_PME_PM_LSU_SRQ_FULL_CYC ] = { -1, -1, 51, 48, -1, -1, 47, 49 }, [ PPC970_PME_PM_LSU0_FLUSH_LRQ ] = { 46, 45, -1, -1, 48, 45, -1, -1 }, [ PPC970_PME_PM_LSU_SRQ_S0_VALID ] = { 70, 70, -1, -1, 72, 70, -1, -1 }, [ PPC970_PME_PM_LARX_LSU0 ] = { 43, 42, -1, -1, 45, 42, -1, -1 }, [ PPC970_PME_PM_GCT_EMPTY_CYC ] = { 28, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_FPU1_ALL ] = { 17, 16, -1, -1, 18, 17, -1, -1 }, [ PPC970_PME_PM_FPU1_FSQRT ] = { 21, 20, -1, -1, 22, 21, -1, -1 }, [ PPC970_PME_PM_FPU_FIN ] = { -1, -1, -1, 22, -1, -1, -1, -1 }, [ PPC970_PME_PM_LSU_SRQ_STFWD ] = { 71, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_MRK_LD_MISS_L1_LSU1 ] = { 77, 74, -1, -1, 77, 76, -1, -1 }, [ PPC970_PME_PM_FXU0_FIN ] = { -1, -1, 25, 25, -1, -1, 25, 25 }, [ PPC970_PME_PM_MRK_FPU_FIN ] = { -1, -1, -1, -1, -1, -1, 49, -1 }, [ PPC970_PME_PM_PMC5_OVERFLOW ] = { -1, -1, -1, -1, -1, 80, -1, -1 }, [ PPC970_PME_PM_SNOOP_TLBIE ] = { 83, 78, -1, -1, 81, 81, -1, -1 }, [ PPC970_PME_PM_FPU1_FRSP_FCONV ] = { -1, -1, 21, 21, -1, -1, 20, 21 }, [ PPC970_PME_PM_FPU0_FDIV ] = { 10, 9, -1, -1, 11, 10, -1, -1 }, [ PPC970_PME_PM_LD_REF_L1_LSU1 ] = { -1, -1, 41, 38, -1, -1, 38, 39 }, [ PPC970_PME_PM_HV_CYC ] = { -1, -1, 30, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_LR_CTR_MAP_FULL_CYC ] = { 44, 43, -1, -1, 46, 43, -1, -1 }, [ PPC970_PME_PM_FPU_DENORM ] = { 26, -1, -1, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_LSU0_REJECT_SRQ ] = { 53, 52, -1, -1, 55, 52, -1, -1 }, [ PPC970_PME_PM_LSU1_REJECT_SRQ ] = { 63, 62, -1, -1, 65, 62, -1, -1 }, [ PPC970_PME_PM_LSU1_DERAT_MISS ] = { 55, 54, -1, -1, 57, 54, -1, -1 }, [ PPC970_PME_PM_IC_PREF_REQ ] = { 35, 35, -1, -1, 38, 35, -1, -1 }, [ PPC970_PME_PM_MRK_LSU_FIN ] = { -1, -1, -1, -1, -1, -1, -1, 60 }, [ PPC970_PME_PM_MRK_DATA_FROM_MEM ] = { -1, -1, 53, -1, -1, -1, -1, -1 }, [ PPC970_PME_PM_LSU0_FLUSH_UST ] = { 49, 48, -1, -1, 51, 48, -1, -1 }, [ PPC970_PME_PM_LSU_FLUSH_LRQ ] = { -1, -1, -1, -1, -1, 65, -1, -1 }, [ PPC970_PME_PM_LSU_FLUSH_SRQ ] = { -1, -1, -1, -1, 67, -1, -1, -1 } }; static const unsigned long long ppc970_group_vecs[][PPC970_NUM_GROUP_VEC] = { [ PPC970_PME_PM_LSU_REJECT_RELOAD_CDF ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_MRK_LSU_SRQ_INST_VALID ] = { 0x0000000800000000ULL }, [ PPC970_PME_PM_FPU1_SINGLE ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_FPU0_STALL3 ] = { 0x0000000000002000ULL }, [ PPC970_PME_PM_TB_BIT_TRANS ] = { 0x0000000000080000ULL }, [ PPC970_PME_PM_GPR_MAP_FULL_CYC ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_MRK_ST_CMPL ] = { 0x0000000800000000ULL }, [ PPC970_PME_PM_FPU0_STF ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_FPU1_FMA ] = { 0x0000000000000400ULL }, [ PPC970_PME_PM_LSU1_FLUSH_ULD ] = { 0x0000000000008000ULL }, [ PPC970_PME_PM_MRK_INST_FIN ] = { 0x0000000200000000ULL }, [ PPC970_PME_PM_MRK_LSU0_FLUSH_UST ] = { 0x0000001000000000ULL }, [ PPC970_PME_PM_LSU_LRQ_S0_ALLOC ] = { 0x0000000010000000ULL }, [ PPC970_PME_PM_FPU_FDIV ] = { 0x0000000000900010ULL }, [ PPC970_PME_PM_FPU0_FULL_CYC ] = { 0x0000000000000080ULL }, [ PPC970_PME_PM_FPU_SINGLE ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_FPU0_FMA ] = { 0x0000000000000400ULL }, [ PPC970_PME_PM_MRK_LSU1_FLUSH_ULD ] = { 0x0000001000000000ULL }, [ PPC970_PME_PM_LSU1_FLUSH_LRQ ] = { 0x0000000000004000ULL }, [ PPC970_PME_PM_DTLB_MISS ] = { 0x0000000010600000ULL }, [ PPC970_PME_PM_MRK_ST_MISS_L1 ] = { 0x0000001000000000ULL }, [ PPC970_PME_PM_EXT_INT ] = { 0x0000000000000200ULL }, [ PPC970_PME_PM_MRK_LSU1_FLUSH_LRQ ] = { 0x0000002000000000ULL }, [ PPC970_PME_PM_MRK_ST_GPS ] = { 0x0000000800000000ULL }, [ PPC970_PME_PM_GRP_DISP_SUCCESS ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_LSU1_LDF ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_LSU0_SRQ_STFWD ] = { 0x0000000000020000ULL }, [ PPC970_PME_PM_CR_MAP_FULL_CYC ] = { 0x0000000000000040ULL }, [ PPC970_PME_PM_MRK_LSU0_FLUSH_ULD ] = { 0x0000001000000000ULL }, [ PPC970_PME_PM_LSU_DERAT_MISS ] = { 0x0000000100000000ULL }, [ PPC970_PME_PM_FPU0_SINGLE ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_FPU1_FDIV ] = { 0x0000000000000400ULL }, [ PPC970_PME_PM_FPU1_FEST ] = { 0x0000000000001000ULL }, [ PPC970_PME_PM_FPU0_FRSP_FCONV ] = { 0x0000000000000400ULL }, [ PPC970_PME_PM_GCT_EMPTY_SRQ_FULL ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_MRK_ST_CMPL_INT ] = { 0x0000000800000000ULL }, [ PPC970_PME_PM_FLUSH_BR_MPRED ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_FXU_FIN ] = { 0x0000004000100000ULL }, [ PPC970_PME_PM_FPU_STF ] = { 0x0000000000800020ULL }, [ PPC970_PME_PM_DSLB_MISS ] = { 0x0000000004000000ULL }, [ PPC970_PME_PM_FXLS1_FULL_CYC ] = { 0x0000008000000080ULL }, [ PPC970_PME_PM_LSU_LMQ_LHR_MERGE ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_MRK_STCX_FAIL ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { 0x0000004000000000ULL }, [ PPC970_PME_PM_MRK_DATA_FROM_L25_SHR ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_LSU_FLUSH_ULD ] = { 0x0000000000000008ULL }, [ PPC970_PME_PM_MRK_BRU_FIN ] = { 0x0000000400000000ULL }, [ PPC970_PME_PM_IERAT_XLATE_WR ] = { 0x0000000080000000ULL }, [ PPC970_PME_PM_DATA_FROM_MEM ] = { 0x0000000008000000ULL }, [ PPC970_PME_PM_FPR_MAP_FULL_CYC ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_FPU1_FULL_CYC ] = { 0x0000000000000080ULL }, [ PPC970_PME_PM_FPU0_FIN ] = { 0x0000000000802800ULL }, [ PPC970_PME_PM_GRP_BR_REDIR ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_THRESH_TIMEO ] = { 0x0000000200000000ULL }, [ PPC970_PME_PM_FPU_FSQRT ] = { 0x0000000000100010ULL }, [ PPC970_PME_PM_MRK_LSU0_FLUSH_LRQ ] = { 0x0000002000000000ULL }, [ PPC970_PME_PM_PMC1_OVERFLOW ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_FXLS0_FULL_CYC ] = { 0x0000008000000080ULL }, [ PPC970_PME_PM_FPU0_ALL ] = { 0x0000000000000800ULL }, [ PPC970_PME_PM_DATA_TABLEWALK_CYC ] = { 0x0000000020000000ULL }, [ PPC970_PME_PM_FPU0_FEST ] = { 0x0000000000001000ULL }, [ PPC970_PME_PM_DATA_FROM_L25_MOD ] = { 0x0000000008000000ULL }, [ PPC970_PME_PM_LSU0_REJECT_ERAT_MISS ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { 0x0000000000480000ULL }, [ PPC970_PME_PM_LSU0_REJECT_RELOAD_CDF ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_FPU_FEST ] = { 0x0000000000000010ULL }, [ PPC970_PME_PM_0INST_FETCH ] = { 0x0000030000000000ULL }, [ PPC970_PME_PM_LD_MISS_L1_LSU0 ] = { 0x0000000000008000ULL }, [ PPC970_PME_PM_LSU1_REJECT_RELOAD_CDF ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_L1_PREF ] = { 0x0000000010000000ULL }, [ PPC970_PME_PM_FPU1_STALL3 ] = { 0x0000000000002000ULL }, [ PPC970_PME_PM_BRQ_FULL_CYC ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_PMC8_OVERFLOW ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_PMC7_OVERFLOW ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_WORK_HELD ] = { 0x0000000000000200ULL }, [ PPC970_PME_PM_MRK_LD_MISS_L1_LSU0 ] = { 0x0000002000000000ULL }, [ PPC970_PME_PM_FXU_IDLE ] = { 0x000000c000000000ULL }, [ PPC970_PME_PM_INST_CMPL ] = { 0x000003fbffffffffULL }, [ PPC970_PME_PM_LSU1_FLUSH_UST ] = { 0x0000000000010000ULL }, [ PPC970_PME_PM_LSU0_FLUSH_ULD ] = { 0x0000000000008000ULL }, [ PPC970_PME_PM_LSU_FLUSH ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_INST_FROM_L2 ] = { 0x0000020020000000ULL }, [ PPC970_PME_PM_LSU1_REJECT_LMQ_FULL ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_PMC2_OVERFLOW ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_FPU0_DENORM ] = { 0x0000000000001000ULL }, [ PPC970_PME_PM_FPU1_FMOV_FEST ] = { 0x0000000000001000ULL }, [ PPC970_PME_PM_GRP_DISP_REJECT ] = { 0x0000000000000101ULL }, [ PPC970_PME_PM_LSU_LDF ] = { 0x0000000000800020ULL }, [ PPC970_PME_PM_INST_DISP ] = { 0x0000000100000146ULL }, [ PPC970_PME_PM_DATA_FROM_L25_SHR ] = { 0x0000000008000000ULL }, [ PPC970_PME_PM_L1_DCACHE_RELOAD_VALID ] = { 0x0000000100040000ULL }, [ PPC970_PME_PM_MRK_GRP_ISSUED ] = { 0x0000000200000000ULL }, [ PPC970_PME_PM_FPU_FMA ] = { 0x0000000000900010ULL }, [ PPC970_PME_PM_MRK_CRU_FIN ] = { 0x0000000400000000ULL }, [ PPC970_PME_PM_MRK_LSU1_FLUSH_UST ] = { 0x0000001000000000ULL }, [ PPC970_PME_PM_MRK_FXU_FIN ] = { 0x0000000400000000ULL }, [ PPC970_PME_PM_LSU1_REJECT_ERAT_MISS ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_BR_ISSUED ] = { 0x0000000007000000ULL }, [ PPC970_PME_PM_PMC4_OVERFLOW ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_EE_OFF ] = { 0x0000000000000200ULL }, [ PPC970_PME_PM_INST_FROM_L25_MOD ] = { 0x0000020000000000ULL }, [ PPC970_PME_PM_ITLB_MISS ] = { 0x0000000010200000ULL }, [ PPC970_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { 0x0000004000000000ULL }, [ PPC970_PME_PM_GRP_DISP_VALID ] = { 0x0000000100000100ULL }, [ PPC970_PME_PM_MRK_GRP_DISP ] = { 0x0000000400000000ULL }, [ PPC970_PME_PM_LSU_FLUSH_UST ] = { 0x0000000000000008ULL }, [ PPC970_PME_PM_FXU1_FIN ] = { 0x0000008000000100ULL }, [ PPC970_PME_PM_GRP_CMPL ] = { 0x0000000020080001ULL }, [ PPC970_PME_PM_FPU_FRSP_FCONV ] = { 0x0000000000000020ULL }, [ PPC970_PME_PM_MRK_LSU0_FLUSH_SRQ ] = { 0x0000002000000000ULL }, [ PPC970_PME_PM_LSU_LMQ_FULL_CYC ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_ST_REF_L1_LSU0 ] = { 0x0000000000030000ULL }, [ PPC970_PME_PM_LSU0_DERAT_MISS ] = { 0x0000000000040000ULL }, [ PPC970_PME_PM_LSU_SRQ_SYNC_CYC ] = { 0x0000000040000000ULL }, [ PPC970_PME_PM_FPU_STALL3 ] = { 0x0000000000000020ULL }, [ PPC970_PME_PM_LSU_REJECT_ERAT_MISS ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_MRK_DATA_FROM_L2 ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_LSU0_FLUSH_SRQ ] = { 0x0000000000004000ULL }, [ PPC970_PME_PM_FPU0_FMOV_FEST ] = { 0x0000000000001000ULL }, [ PPC970_PME_PM_LD_REF_L1_LSU0 ] = { 0x0000000000008000ULL }, [ PPC970_PME_PM_LSU1_FLUSH_SRQ ] = { 0x0000000000004000ULL }, [ PPC970_PME_PM_GRP_BR_MPRED ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_LSU_LMQ_S0_ALLOC ] = { 0x0000000008000000ULL }, [ PPC970_PME_PM_LSU0_REJECT_LMQ_FULL ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_ST_REF_L1 ] = { 0x000000010260000eULL }, [ PPC970_PME_PM_MRK_VMX_FIN ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_LSU_SRQ_EMPTY_CYC ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_FPU1_STF ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_RUN_CYC ] = { 0x0000000004000001ULL }, [ PPC970_PME_PM_LSU_LMQ_S0_VALID ] = { 0x0000000008000000ULL }, [ PPC970_PME_PM_LSU0_LDF ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_LSU_LRQ_S0_VALID ] = { 0x0000000010000000ULL }, [ PPC970_PME_PM_PMC3_OVERFLOW ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_MRK_IMR_RELOAD ] = { 0x0000001000000000ULL }, [ PPC970_PME_PM_MRK_GRP_TIMEO ] = { 0x0000000800000000ULL }, [ PPC970_PME_PM_FPU_FMOV_FEST ] = { 0x0000000000100010ULL }, [ PPC970_PME_PM_GRP_DISP_BLK_SB_CYC ] = { 0x0000000000000040ULL }, [ PPC970_PME_PM_XER_MAP_FULL_CYC ] = { 0x0000000000000040ULL }, [ PPC970_PME_PM_ST_MISS_L1 ] = { 0x0000000003630000ULL }, [ PPC970_PME_PM_STOP_COMPLETION ] = { 0x0000000000000201ULL }, [ PPC970_PME_PM_MRK_GRP_CMPL ] = { 0x0000000a00000000ULL }, [ PPC970_PME_PM_ISLB_MISS ] = { 0x0000000004000000ULL }, [ PPC970_PME_PM_SUSPENDED ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_CYC ] = { 0x000003ffffffffffULL }, [ PPC970_PME_PM_LD_MISS_L1_LSU1 ] = { 0x0000000000008000ULL }, [ PPC970_PME_PM_STCX_FAIL ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_LSU1_SRQ_STFWD ] = { 0x0000000000020000ULL }, [ PPC970_PME_PM_GRP_DISP ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_L2_PREF ] = { 0x0000000010000000ULL }, [ PPC970_PME_PM_FPU1_DENORM ] = { 0x0000000000001000ULL }, [ PPC970_PME_PM_DATA_FROM_L2 ] = { 0x0000000008000000ULL }, [ PPC970_PME_PM_FPU0_FPSCR ] = { 0x0000000000002000ULL }, [ PPC970_PME_PM_MRK_DATA_FROM_L25_MOD ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_FPU0_FSQRT ] = { 0x0000000000000800ULL }, [ PPC970_PME_PM_LD_REF_L1 ] = { 0x000000004260000eULL }, [ PPC970_PME_PM_MRK_L1_RELOAD_VALID ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_1PLUS_PPC_CMPL ] = { 0x0000000000080001ULL }, [ PPC970_PME_PM_INST_FROM_L1 ] = { 0x0000010080000000ULL }, [ PPC970_PME_PM_EE_OFF_EXT_INT ] = { 0x0000000000000200ULL }, [ PPC970_PME_PM_PMC6_OVERFLOW ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_LSU_LRQ_FULL_CYC ] = { 0x0000000000000080ULL }, [ PPC970_PME_PM_IC_PREF_INSTALL ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_DC_PREF_OUT_OF_STREAMS ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_MRK_LSU1_FLUSH_SRQ ] = { 0x0000002000000000ULL }, [ PPC970_PME_PM_GCT_FULL_CYC ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_INST_FROM_MEM ] = { 0x0000030020000000ULL }, [ PPC970_PME_PM_FLUSH_LSU_BR_MPRED ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_FXU_BUSY ] = { 0x000000c000000000ULL }, [ PPC970_PME_PM_ST_REF_L1_LSU1 ] = { 0x0000000000030000ULL }, [ PPC970_PME_PM_MRK_LD_MISS_L1 ] = { 0x0000000200000000ULL }, [ PPC970_PME_PM_L1_WRITE_CYC ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_LSU_REJECT_LMQ_FULL ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_FPU_ALL ] = { 0x0000000000000020ULL }, [ PPC970_PME_PM_LSU_SRQ_S0_ALLOC ] = { 0x0000000040000000ULL }, [ PPC970_PME_PM_INST_FROM_L25_SHR ] = { 0x0000020000000000ULL }, [ PPC970_PME_PM_GRP_MRK ] = { 0x0000000600000000ULL }, [ PPC970_PME_PM_BR_MPRED_CR ] = { 0x0000000005000000ULL }, [ PPC970_PME_PM_DC_PREF_STREAM_ALLOC ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_FPU1_FIN ] = { 0x0000000000802800ULL }, [ PPC970_PME_PM_LSU_REJECT_SRQ ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_BR_MPRED_TA ] = { 0x0000000005000000ULL }, [ PPC970_PME_PM_CRQ_FULL_CYC ] = { 0x0000000000000040ULL }, [ PPC970_PME_PM_LD_MISS_L1 ] = { 0x0000000043600006ULL }, [ PPC970_PME_PM_INST_FROM_PREF ] = { 0x0000030000000000ULL }, [ PPC970_PME_PM_STCX_PASS ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_DC_INV_L2 ] = { 0x0000000020010006ULL }, [ PPC970_PME_PM_LSU_SRQ_FULL_CYC ] = { 0x0000000000000080ULL }, [ PPC970_PME_PM_LSU0_FLUSH_LRQ ] = { 0x0000000000004000ULL }, [ PPC970_PME_PM_LSU_SRQ_S0_VALID ] = { 0x0000000040000000ULL }, [ PPC970_PME_PM_LARX_LSU0 ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_GCT_EMPTY_CYC ] = { 0x0000000100080200ULL }, [ PPC970_PME_PM_FPU1_ALL ] = { 0x0000000000000800ULL }, [ PPC970_PME_PM_FPU1_FSQRT ] = { 0x0000000000000800ULL }, [ PPC970_PME_PM_FPU_FIN ] = { 0x0000000000100010ULL }, [ PPC970_PME_PM_LSU_SRQ_STFWD ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_MRK_LD_MISS_L1_LSU1 ] = { 0x0000002000000000ULL }, [ PPC970_PME_PM_FXU0_FIN ] = { 0x0000008000000100ULL }, [ PPC970_PME_PM_MRK_FPU_FIN ] = { 0x0000000400000000ULL }, [ PPC970_PME_PM_PMC5_OVERFLOW ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_SNOOP_TLBIE ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_FPU1_FRSP_FCONV ] = { 0x0000000000000400ULL }, [ PPC970_PME_PM_FPU0_FDIV ] = { 0x0000000000000400ULL }, [ PPC970_PME_PM_LD_REF_L1_LSU1 ] = { 0x0000000000008000ULL }, [ PPC970_PME_PM_HV_CYC ] = { 0x0000000020080000ULL }, [ PPC970_PME_PM_LR_CTR_MAP_FULL_CYC ] = { 0x0000000000000040ULL }, [ PPC970_PME_PM_FPU_DENORM ] = { 0x0000000000000020ULL }, [ PPC970_PME_PM_LSU0_REJECT_SRQ ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_LSU1_REJECT_SRQ ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_LSU1_DERAT_MISS ] = { 0x0000000000040000ULL }, [ PPC970_PME_PM_IC_PREF_REQ ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_MRK_LSU_FIN ] = { 0x0000000400000000ULL }, [ PPC970_PME_PM_MRK_DATA_FROM_MEM ] = { 0x0000000000000000ULL }, [ PPC970_PME_PM_LSU0_FLUSH_UST ] = { 0x0000000000010000ULL }, [ PPC970_PME_PM_LSU_FLUSH_LRQ ] = { 0x0000000000000008ULL }, [ PPC970_PME_PM_LSU_FLUSH_SRQ ] = { 0x0000000000000008ULL } }; static const pme_power_entry_t ppc970_pe[] = { [ PPC970_PME_PM_LSU_REJECT_RELOAD_CDF ] = { .pme_name = "PM_LSU_REJECT_RELOAD_CDF", .pme_code = 0x6920, .pme_short_desc = "LSU reject due to reload CDF or tag update collision", .pme_long_desc = "LSU reject due to reload CDF or tag update collision", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_REJECT_RELOAD_CDF], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_REJECT_RELOAD_CDF] }, [ PPC970_PME_PM_MRK_LSU_SRQ_INST_VALID ] = { .pme_name = "PM_MRK_LSU_SRQ_INST_VALID", .pme_code = 0x936, .pme_short_desc = "Marked instruction valid in SRQ", .pme_long_desc = "This signal is asserted every cycle when a marked request is resident in the Store Request Queue", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_LSU_SRQ_INST_VALID], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_LSU_SRQ_INST_VALID] }, [ PPC970_PME_PM_FPU1_SINGLE ] = { .pme_name = "PM_FPU1_SINGLE", .pme_code = 0x127, .pme_short_desc = "FPU1 executed single precision instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing single precision instruction.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU1_SINGLE], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU1_SINGLE] }, [ PPC970_PME_PM_FPU0_STALL3 ] = { .pme_name = "PM_FPU0_STALL3", .pme_code = 0x121, .pme_short_desc = "FPU0 stalled in pipe3", .pme_long_desc = "This signal indicates that fp0 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. ", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU0_STALL3], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU0_STALL3] }, [ PPC970_PME_PM_TB_BIT_TRANS ] = { .pme_name = "PM_TB_BIT_TRANS", .pme_code = 0x8005, .pme_short_desc = "Time Base bit transition", .pme_long_desc = "When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 ", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_TB_BIT_TRANS], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_TB_BIT_TRANS] }, [ PPC970_PME_PM_GPR_MAP_FULL_CYC ] = { .pme_name = "PM_GPR_MAP_FULL_CYC", .pme_code = 0x335, .pme_short_desc = "Cycles GPR mapper full", .pme_long_desc = "The ISU sends a signal indicating that the gpr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_GPR_MAP_FULL_CYC], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_GPR_MAP_FULL_CYC] }, [ PPC970_PME_PM_MRK_ST_CMPL ] = { .pme_name = "PM_MRK_ST_CMPL", .pme_code = 0x1003, .pme_short_desc = "Marked store instruction completed", .pme_long_desc = "A sampled store has completed (data home)", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_ST_CMPL], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_ST_CMPL] }, [ PPC970_PME_PM_FPU0_STF ] = { .pme_name = "PM_FPU0_STF", .pme_code = 0x122, .pme_short_desc = "FPU0 executed store instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing a store instruction.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU0_STF], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU0_STF] }, [ PPC970_PME_PM_FPU1_FMA ] = { .pme_name = "PM_FPU1_FMA", .pme_code = 0x105, .pme_short_desc = "FPU1 executed multiply-add instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU1_FMA], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU1_FMA] }, [ PPC970_PME_PM_LSU1_FLUSH_ULD ] = { .pme_name = "PM_LSU1_FLUSH_ULD", .pme_code = 0x804, .pme_short_desc = "LSU1 unaligned load flushes", .pme_long_desc = "A load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU1_FLUSH_ULD], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU1_FLUSH_ULD] }, [ PPC970_PME_PM_MRK_INST_FIN ] = { .pme_name = "PM_MRK_INST_FIN", .pme_code = 0x7005, .pme_short_desc = "Marked instruction finished", .pme_long_desc = "One of the execution units finished a marked instruction. Instructions that finish may not necessary complete", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_INST_FIN], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_INST_FIN] }, [ PPC970_PME_PM_MRK_LSU0_FLUSH_UST ] = { .pme_name = "PM_MRK_LSU0_FLUSH_UST", .pme_code = 0x711, .pme_short_desc = "LSU0 marked unaligned store flushes", .pme_long_desc = "A marked store was flushed from unit 0 because it was unaligned", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_LSU0_FLUSH_UST], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_LSU0_FLUSH_UST] }, [ PPC970_PME_PM_LSU_LRQ_S0_ALLOC ] = { .pme_name = "PM_LSU_LRQ_S0_ALLOC", .pme_code = 0x826, .pme_short_desc = "LRQ slot 0 allocated", .pme_long_desc = "LRQ slot zero was allocated", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_LRQ_S0_ALLOC], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_LRQ_S0_ALLOC] }, [ PPC970_PME_PM_FPU_FDIV ] = { .pme_name = "PM_FPU_FDIV", .pme_code = 0x1100, .pme_short_desc = "FPU executed FDIV instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when FPU is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs. Combined Unit 0 + Unit 1", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU_FDIV], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU_FDIV] }, [ PPC970_PME_PM_FPU0_FULL_CYC ] = { .pme_name = "PM_FPU0_FULL_CYC", .pme_code = 0x303, .pme_short_desc = "Cycles FPU0 issue queue full", .pme_long_desc = "The issue queue for FPU unit 0 cannot accept any more instructions. Issue is stopped", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU0_FULL_CYC], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU0_FULL_CYC] }, [ PPC970_PME_PM_FPU_SINGLE ] = { .pme_name = "PM_FPU_SINGLE", .pme_code = 0x5120, .pme_short_desc = "FPU executed single precision instruction", .pme_long_desc = "FPU is executing single precision instruction. Combined Unit 0 + Unit 1", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU_SINGLE], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU_SINGLE] }, [ PPC970_PME_PM_FPU0_FMA ] = { .pme_name = "PM_FPU0_FMA", .pme_code = 0x101, .pme_short_desc = "FPU0 executed multiply-add instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU0_FMA], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU0_FMA] }, [ PPC970_PME_PM_MRK_LSU1_FLUSH_ULD ] = { .pme_name = "PM_MRK_LSU1_FLUSH_ULD", .pme_code = 0x714, .pme_short_desc = "LSU1 marked unaligned load flushes", .pme_long_desc = "A marked load was flushed from unit 1 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_LSU1_FLUSH_ULD], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_LSU1_FLUSH_ULD] }, [ PPC970_PME_PM_LSU1_FLUSH_LRQ ] = { .pme_name = "PM_LSU1_FLUSH_LRQ", .pme_code = 0x806, .pme_short_desc = "LSU1 LRQ flushes", .pme_long_desc = "A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU1_FLUSH_LRQ], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU1_FLUSH_LRQ] }, [ PPC970_PME_PM_DTLB_MISS ] = { .pme_name = "PM_DTLB_MISS", .pme_code = 0x704, .pme_short_desc = "Data TLB misses", .pme_long_desc = "A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_DTLB_MISS], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_DTLB_MISS] }, [ PPC970_PME_PM_MRK_ST_MISS_L1 ] = { .pme_name = "PM_MRK_ST_MISS_L1", .pme_code = 0x723, .pme_short_desc = "Marked L1 D cache store misses", .pme_long_desc = "A marked store missed the dcache", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_ST_MISS_L1], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_ST_MISS_L1] }, [ PPC970_PME_PM_EXT_INT ] = { .pme_name = "PM_EXT_INT", .pme_code = 0x8002, .pme_short_desc = "External interrupts", .pme_long_desc = "An external interrupt occurred", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_EXT_INT], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_EXT_INT] }, [ PPC970_PME_PM_MRK_LSU1_FLUSH_LRQ ] = { .pme_name = "PM_MRK_LSU1_FLUSH_LRQ", .pme_code = 0x716, .pme_short_desc = "LSU1 marked LRQ flushes", .pme_long_desc = "A marked load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_LSU1_FLUSH_LRQ], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_LSU1_FLUSH_LRQ] }, [ PPC970_PME_PM_MRK_ST_GPS ] = { .pme_name = "PM_MRK_ST_GPS", .pme_code = 0x6003, .pme_short_desc = "Marked store sent to GPS", .pme_long_desc = "A sampled store has been sent to the memory subsystem", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_ST_GPS], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_ST_GPS] }, [ PPC970_PME_PM_GRP_DISP_SUCCESS ] = { .pme_name = "PM_GRP_DISP_SUCCESS", .pme_code = 0x5001, .pme_short_desc = "Group dispatch success", .pme_long_desc = "Number of groups sucessfully dispatched (not rejected)", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_GRP_DISP_SUCCESS], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_GRP_DISP_SUCCESS] }, [ PPC970_PME_PM_LSU1_LDF ] = { .pme_name = "PM_LSU1_LDF", .pme_code = 0x734, .pme_short_desc = "LSU1 executed Floating Point load instruction", .pme_long_desc = "A floating point load was executed from LSU unit 1", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU1_LDF], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU1_LDF] }, [ PPC970_PME_PM_LSU0_SRQ_STFWD ] = { .pme_name = "PM_LSU0_SRQ_STFWD", .pme_code = 0x820, .pme_short_desc = "LSU0 SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load on unit 0", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU0_SRQ_STFWD], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU0_SRQ_STFWD] }, [ PPC970_PME_PM_CR_MAP_FULL_CYC ] = { .pme_name = "PM_CR_MAP_FULL_CYC", .pme_code = 0x304, .pme_short_desc = "Cycles CR logical operation mapper full", .pme_long_desc = "The ISU sends a signal indicating that the cr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_CR_MAP_FULL_CYC], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_CR_MAP_FULL_CYC] }, [ PPC970_PME_PM_MRK_LSU0_FLUSH_ULD ] = { .pme_name = "PM_MRK_LSU0_FLUSH_ULD", .pme_code = 0x710, .pme_short_desc = "LSU0 marked unaligned load flushes", .pme_long_desc = "A marked load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_LSU0_FLUSH_ULD], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_LSU0_FLUSH_ULD] }, [ PPC970_PME_PM_LSU_DERAT_MISS ] = { .pme_name = "PM_LSU_DERAT_MISS", .pme_code = 0x6700, .pme_short_desc = "DERAT misses", .pme_long_desc = "Total D-ERAT Misses (Unit 0 + Unit 1). Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_DERAT_MISS], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_DERAT_MISS] }, [ PPC970_PME_PM_FPU0_SINGLE ] = { .pme_name = "PM_FPU0_SINGLE", .pme_code = 0x123, .pme_short_desc = "FPU0 executed single precision instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing single precision instruction.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU0_SINGLE], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU0_SINGLE] }, [ PPC970_PME_PM_FPU1_FDIV ] = { .pme_name = "PM_FPU1_FDIV", .pme_code = 0x104, .pme_short_desc = "FPU1 executed FDIV instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp1 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU1_FDIV], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU1_FDIV] }, [ PPC970_PME_PM_FPU1_FEST ] = { .pme_name = "PM_FPU1_FEST", .pme_code = 0x116, .pme_short_desc = "FPU1 executed FEST instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. ", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU1_FEST], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU1_FEST] }, [ PPC970_PME_PM_FPU0_FRSP_FCONV ] = { .pme_name = "PM_FPU0_FRSP_FCONV", .pme_code = 0x111, .pme_short_desc = "FPU0 executed FRSP or FCONV instructions", .pme_long_desc = "This signal is active for one cycle when fp0 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU0_FRSP_FCONV], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU0_FRSP_FCONV] }, [ PPC970_PME_PM_GCT_EMPTY_SRQ_FULL ] = { .pme_name = "PM_GCT_EMPTY_SRQ_FULL", .pme_code = 0x200b, .pme_short_desc = "GCT empty caused by SRQ full", .pme_long_desc = "GCT empty caused by SRQ full", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_GCT_EMPTY_SRQ_FULL], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_GCT_EMPTY_SRQ_FULL] }, [ PPC970_PME_PM_MRK_ST_CMPL_INT ] = { .pme_name = "PM_MRK_ST_CMPL_INT", .pme_code = 0x3003, .pme_short_desc = "Marked store completed with intervention", .pme_long_desc = "A marked store previously sent to the memory subsystem completed (data home) after requiring intervention", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_ST_CMPL_INT], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_ST_CMPL_INT] }, [ PPC970_PME_PM_FLUSH_BR_MPRED ] = { .pme_name = "PM_FLUSH_BR_MPRED", .pme_code = 0x316, .pme_short_desc = "Flush caused by branch mispredict", .pme_long_desc = "Flush caused by branch mispredict", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FLUSH_BR_MPRED], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FLUSH_BR_MPRED] }, [ PPC970_PME_PM_FXU_FIN ] = { .pme_name = "PM_FXU_FIN", .pme_code = 0x3330, .pme_short_desc = "FXU produced a result", .pme_long_desc = "The fixed point unit (Unit 0 + Unit 1) finished a marked instruction. Instructions that finish may not necessary complete.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FXU_FIN], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FXU_FIN] }, [ PPC970_PME_PM_FPU_STF ] = { .pme_name = "PM_FPU_STF", .pme_code = 0x6120, .pme_short_desc = "FPU executed store instruction", .pme_long_desc = "FPU is executing a store instruction. Combined Unit 0 + Unit 1", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU_STF], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU_STF] }, [ PPC970_PME_PM_DSLB_MISS ] = { .pme_name = "PM_DSLB_MISS", .pme_code = 0x705, .pme_short_desc = "Data SLB misses", .pme_long_desc = "A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_DSLB_MISS], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_DSLB_MISS] }, [ PPC970_PME_PM_FXLS1_FULL_CYC ] = { .pme_name = "PM_FXLS1_FULL_CYC", .pme_code = 0x314, .pme_short_desc = "Cycles FXU1/LS1 queue full", .pme_long_desc = "The issue queue for FXU/LSU unit 0 cannot accept any more instructions. Issue is stopped", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FXLS1_FULL_CYC], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FXLS1_FULL_CYC] }, [ PPC970_PME_PM_LSU_LMQ_LHR_MERGE ] = { .pme_name = "PM_LSU_LMQ_LHR_MERGE", .pme_code = 0x935, .pme_short_desc = "LMQ LHR merges", .pme_long_desc = "A dcache miss occured for the same real cache line address as an earlier request already in the Load Miss Queue and was merged into the LMQ entry.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_LMQ_LHR_MERGE], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_LMQ_LHR_MERGE] }, [ PPC970_PME_PM_MRK_STCX_FAIL ] = { .pme_name = "PM_MRK_STCX_FAIL", .pme_code = 0x726, .pme_short_desc = "Marked STCX failed", .pme_long_desc = "A marked stcx (stwcx or stdcx) failed", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_STCX_FAIL], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_STCX_FAIL] }, [ PPC970_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { .pme_name = "PM_FXU0_BUSY_FXU1_IDLE", .pme_code = 0x7002, .pme_short_desc = "FXU0 busy FXU1 idle", .pme_long_desc = "FXU0 is busy while FXU1 was idle", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FXU0_BUSY_FXU1_IDLE], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FXU0_BUSY_FXU1_IDLE] }, [ PPC970_PME_PM_MRK_DATA_FROM_L25_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L25_SHR", .pme_code = 0x193d, .pme_short_desc = "Marked data loaded from L2.5 shared", .pme_long_desc = "DL1 was reloaded with shared (T or SL) data from the L2 of a chip on this MCM due to a marked demand load", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_DATA_FROM_L25_SHR], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_DATA_FROM_L25_SHR] }, [ PPC970_PME_PM_LSU_FLUSH_ULD ] = { .pme_name = "PM_LSU_FLUSH_ULD", .pme_code = 0x1800, .pme_short_desc = "LRQ unaligned load flushes", .pme_long_desc = "A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_FLUSH_ULD], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_FLUSH_ULD] }, [ PPC970_PME_PM_MRK_BRU_FIN ] = { .pme_name = "PM_MRK_BRU_FIN", .pme_code = 0x2005, .pme_short_desc = "Marked instruction BRU processing finished", .pme_long_desc = "The branch unit finished a marked instruction. Instructions that finish may not necessary complete", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_BRU_FIN], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_BRU_FIN] }, [ PPC970_PME_PM_IERAT_XLATE_WR ] = { .pme_name = "PM_IERAT_XLATE_WR", .pme_code = 0x430, .pme_short_desc = "Translation written to ierat", .pme_long_desc = "This signal will be asserted each time the I-ERAT is written. This indicates that an ERAT miss has been serviced. ERAT misses will initiate a sequence resulting in the ERAT being written. ERAT misses that are later ignored will not be counted unless the ERAT is written before the instruction stream is changed, This should be a fairly accurate count of ERAT missed (best available).", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_IERAT_XLATE_WR], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_IERAT_XLATE_WR] }, [ PPC970_PME_PM_DATA_FROM_MEM ] = { .pme_name = "PM_DATA_FROM_MEM", .pme_code = 0x3837, .pme_short_desc = "Data loaded from memory", .pme_long_desc = "Data loaded from memory", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_DATA_FROM_MEM], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_DATA_FROM_MEM] }, [ PPC970_PME_PM_FPR_MAP_FULL_CYC ] = { .pme_name = "PM_FPR_MAP_FULL_CYC", .pme_code = 0x301, .pme_short_desc = "Cycles FPR mapper full", .pme_long_desc = "The ISU sends a signal indicating that the FPR mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPR_MAP_FULL_CYC], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPR_MAP_FULL_CYC] }, [ PPC970_PME_PM_FPU1_FULL_CYC ] = { .pme_name = "PM_FPU1_FULL_CYC", .pme_code = 0x307, .pme_short_desc = "Cycles FPU1 issue queue full", .pme_long_desc = "The issue queue for FPU unit 1 cannot accept any more instructions. Issue is stopped", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU1_FULL_CYC], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU1_FULL_CYC] }, [ PPC970_PME_PM_FPU0_FIN ] = { .pme_name = "PM_FPU0_FIN", .pme_code = 0x113, .pme_short_desc = "FPU0 produced a result", .pme_long_desc = "fp0 finished, produced a result This only indicates finish, not completion. ", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU0_FIN], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU0_FIN] }, [ PPC970_PME_PM_GRP_BR_REDIR ] = { .pme_name = "PM_GRP_BR_REDIR", .pme_code = 0x326, .pme_short_desc = "Group experienced branch redirect", .pme_long_desc = "Group experienced branch redirect", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_GRP_BR_REDIR], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_GRP_BR_REDIR] }, [ PPC970_PME_PM_THRESH_TIMEO ] = { .pme_name = "PM_THRESH_TIMEO", .pme_code = 0x2003, .pme_short_desc = "Threshold timeout", .pme_long_desc = "The threshold timer expired", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_THRESH_TIMEO], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_THRESH_TIMEO] }, [ PPC970_PME_PM_FPU_FSQRT ] = { .pme_name = "PM_FPU_FSQRT", .pme_code = 0x6100, .pme_short_desc = "FPU executed FSQRT instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when FPU is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU_FSQRT], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU_FSQRT] }, [ PPC970_PME_PM_MRK_LSU0_FLUSH_LRQ ] = { .pme_name = "PM_MRK_LSU0_FLUSH_LRQ", .pme_code = 0x712, .pme_short_desc = "LSU0 marked LRQ flushes", .pme_long_desc = "A marked load was flushed by unit 0 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_LSU0_FLUSH_LRQ], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_LSU0_FLUSH_LRQ] }, [ PPC970_PME_PM_PMC1_OVERFLOW ] = { .pme_name = "PM_PMC1_OVERFLOW", .pme_code = 0x200a, .pme_short_desc = "PMC1 Overflow", .pme_long_desc = "PMC1 Overflow", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_PMC1_OVERFLOW], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_PMC1_OVERFLOW] }, [ PPC970_PME_PM_FXLS0_FULL_CYC ] = { .pme_name = "PM_FXLS0_FULL_CYC", .pme_code = 0x310, .pme_short_desc = "Cycles FXU0/LS0 queue full", .pme_long_desc = "The issue queue for FXU/LSU unit 0 cannot accept any more instructions. Issue is stopped", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FXLS0_FULL_CYC], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FXLS0_FULL_CYC] }, [ PPC970_PME_PM_FPU0_ALL ] = { .pme_name = "PM_FPU0_ALL", .pme_code = 0x103, .pme_short_desc = "FPU0 executed add", .pme_long_desc = " mult", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU0_ALL], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU0_ALL] }, [ PPC970_PME_PM_DATA_TABLEWALK_CYC ] = { .pme_name = "PM_DATA_TABLEWALK_CYC", .pme_code = 0x707, .pme_short_desc = "Cycles doing data tablewalks", .pme_long_desc = "This signal is asserted every cycle when a tablewalk is active. While a tablewalk is active any request attempting to access the TLB will be rejected and retried.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_DATA_TABLEWALK_CYC], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_DATA_TABLEWALK_CYC] }, [ PPC970_PME_PM_FPU0_FEST ] = { .pme_name = "PM_FPU0_FEST", .pme_code = 0x112, .pme_short_desc = "FPU0 executed FEST instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. ", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU0_FEST], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU0_FEST] }, [ PPC970_PME_PM_DATA_FROM_L25_MOD ] = { .pme_name = "PM_DATA_FROM_L25_MOD", .pme_code = 0x383d, .pme_short_desc = "Data loaded from L2.5 modified", .pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a demand load", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_DATA_FROM_L25_MOD], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_DATA_FROM_L25_MOD] }, [ PPC970_PME_PM_LSU0_REJECT_ERAT_MISS ] = { .pme_name = "PM_LSU0_REJECT_ERAT_MISS", .pme_code = 0x923, .pme_short_desc = "LSU0 reject due to ERAT miss", .pme_long_desc = "LSU0 reject due to ERAT miss", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU0_REJECT_ERAT_MISS], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU0_REJECT_ERAT_MISS] }, [ PPC970_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_LMQ_SRQ_EMPTY_CYC", .pme_code = 0x2002, .pme_short_desc = "Cycles LMQ and SRQ empty", .pme_long_desc = "Cycles when both the LMQ and SRQ are empty (LSU is idle)", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC] }, [ PPC970_PME_PM_LSU0_REJECT_RELOAD_CDF ] = { .pme_name = "PM_LSU0_REJECT_RELOAD_CDF", .pme_code = 0x922, .pme_short_desc = "LSU0 reject due to reload CDF or tag update collision", .pme_long_desc = "LSU0 reject due to reload CDF or tag update collision", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU0_REJECT_RELOAD_CDF], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU0_REJECT_RELOAD_CDF] }, [ PPC970_PME_PM_FPU_FEST ] = { .pme_name = "PM_FPU_FEST", .pme_code = 0x3110, .pme_short_desc = "FPU executed FEST instruction", .pme_long_desc = "This signal is active for one cycle when executing one of the estimate instructions. This could be fres* or frsqrte* where XYZ* means XYZ or XYZ. Combined Unit 0 + Unit 1.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU_FEST], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU_FEST] }, [ PPC970_PME_PM_0INST_FETCH ] = { .pme_name = "PM_0INST_FETCH", .pme_code = 0x442d, .pme_short_desc = "No instructions fetched", .pme_long_desc = "No instructions were fetched this cycles (due to IFU hold, redirect, or icache miss)", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_0INST_FETCH], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_0INST_FETCH] }, [ PPC970_PME_PM_LD_MISS_L1_LSU0 ] = { .pme_name = "PM_LD_MISS_L1_LSU0", .pme_code = 0x812, .pme_short_desc = "LSU0 L1 D cache load misses", .pme_long_desc = "A load, executing on unit 0, missed the dcache", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LD_MISS_L1_LSU0], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LD_MISS_L1_LSU0] }, [ PPC970_PME_PM_LSU1_REJECT_RELOAD_CDF ] = { .pme_name = "PM_LSU1_REJECT_RELOAD_CDF", .pme_code = 0x926, .pme_short_desc = "LSU1 reject due to reload CDF or tag update collision", .pme_long_desc = "LSU1 reject due to reload CDF or tag update collision", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU1_REJECT_RELOAD_CDF], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU1_REJECT_RELOAD_CDF] }, [ PPC970_PME_PM_L1_PREF ] = { .pme_name = "PM_L1_PREF", .pme_code = 0x731, .pme_short_desc = "L1 cache data prefetches", .pme_long_desc = "A request to prefetch data into the L1 was made", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_L1_PREF], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_L1_PREF] }, [ PPC970_PME_PM_FPU1_STALL3 ] = { .pme_name = "PM_FPU1_STALL3", .pme_code = 0x125, .pme_short_desc = "FPU1 stalled in pipe3", .pme_long_desc = "This signal indicates that fp1 has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. ", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU1_STALL3], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU1_STALL3] }, [ PPC970_PME_PM_BRQ_FULL_CYC ] = { .pme_name = "PM_BRQ_FULL_CYC", .pme_code = 0x305, .pme_short_desc = "Cycles branch queue full", .pme_long_desc = "The ISU sends a signal indicating that the issue queue that feeds the ifu br unit cannot accept any more group (queue is full of groups).", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_BRQ_FULL_CYC], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_BRQ_FULL_CYC] }, [ PPC970_PME_PM_PMC8_OVERFLOW ] = { .pme_name = "PM_PMC8_OVERFLOW", .pme_code = 0x100a, .pme_short_desc = "PMC8 Overflow", .pme_long_desc = "PMC8 Overflow", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_PMC8_OVERFLOW], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_PMC8_OVERFLOW] }, [ PPC970_PME_PM_PMC7_OVERFLOW ] = { .pme_name = "PM_PMC7_OVERFLOW", .pme_code = 0x800a, .pme_short_desc = "PMC7 Overflow", .pme_long_desc = "PMC7 Overflow", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_PMC7_OVERFLOW], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_PMC7_OVERFLOW] }, [ PPC970_PME_PM_WORK_HELD ] = { .pme_name = "PM_WORK_HELD", .pme_code = 0x2001, .pme_short_desc = "Work held", .pme_long_desc = "RAS Unit has signaled completion to stop and there are groups waiting to complete", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_WORK_HELD], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_WORK_HELD] }, [ PPC970_PME_PM_MRK_LD_MISS_L1_LSU0 ] = { .pme_name = "PM_MRK_LD_MISS_L1_LSU0", .pme_code = 0x720, .pme_short_desc = "LSU0 L1 D cache load misses", .pme_long_desc = "A marked load, executing on unit 0, missed the dcache", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_LD_MISS_L1_LSU0], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_LD_MISS_L1_LSU0] }, [ PPC970_PME_PM_FXU_IDLE ] = { .pme_name = "PM_FXU_IDLE", .pme_code = 0x5002, .pme_short_desc = "FXU idle", .pme_long_desc = "FXU0 and FXU1 are both idle", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FXU_IDLE], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FXU_IDLE] }, [ PPC970_PME_PM_INST_CMPL ] = { .pme_name = "PM_INST_CMPL", .pme_code = 0x1, .pme_short_desc = "Instructions completed", .pme_long_desc = "Number of Eligible Instructions that completed. ", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_INST_CMPL], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_INST_CMPL] }, [ PPC970_PME_PM_LSU1_FLUSH_UST ] = { .pme_name = "PM_LSU1_FLUSH_UST", .pme_code = 0x805, .pme_short_desc = "LSU1 unaligned store flushes", .pme_long_desc = "A store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU1_FLUSH_UST], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU1_FLUSH_UST] }, [ PPC970_PME_PM_LSU0_FLUSH_ULD ] = { .pme_name = "PM_LSU0_FLUSH_ULD", .pme_code = 0x800, .pme_short_desc = "LSU0 unaligned load flushes", .pme_long_desc = "A load was flushed from unit 0 because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU0_FLUSH_ULD], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU0_FLUSH_ULD] }, [ PPC970_PME_PM_LSU_FLUSH ] = { .pme_name = "PM_LSU_FLUSH", .pme_code = 0x315, .pme_short_desc = "Flush initiated by LSU", .pme_long_desc = "Flush initiated by LSU", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_FLUSH], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_FLUSH] }, [ PPC970_PME_PM_INST_FROM_L2 ] = { .pme_name = "PM_INST_FROM_L2", .pme_code = 0x1426, .pme_short_desc = "Instructions fetched from L2", .pme_long_desc = "An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_INST_FROM_L2], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_INST_FROM_L2] }, [ PPC970_PME_PM_LSU1_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU1_REJECT_LMQ_FULL", .pme_code = 0x925, .pme_short_desc = "LSU1 reject due to LMQ full or missed data coming", .pme_long_desc = "LSU1 reject due to LMQ full or missed data coming", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU1_REJECT_LMQ_FULL], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU1_REJECT_LMQ_FULL] }, [ PPC970_PME_PM_PMC2_OVERFLOW ] = { .pme_name = "PM_PMC2_OVERFLOW", .pme_code = 0x300a, .pme_short_desc = "PMC2 Overflow", .pme_long_desc = "PMC2 Overflow", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_PMC2_OVERFLOW], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_PMC2_OVERFLOW] }, [ PPC970_PME_PM_FPU0_DENORM ] = { .pme_name = "PM_FPU0_DENORM", .pme_code = 0x120, .pme_short_desc = "FPU0 received denormalized data", .pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU0_DENORM], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU0_DENORM] }, [ PPC970_PME_PM_FPU1_FMOV_FEST ] = { .pme_name = "PM_FPU1_FMOV_FEST", .pme_code = 0x114, .pme_short_desc = "FPU1 executing FMOV or FEST instructions", .pme_long_desc = "This signal is active for one cycle when fp1 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU1_FMOV_FEST], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU1_FMOV_FEST] }, [ PPC970_PME_PM_GRP_DISP_REJECT ] = { .pme_name = "PM_GRP_DISP_REJECT", .pme_code = 0x324, .pme_short_desc = "Group dispatch rejected", .pme_long_desc = "A group that previously attempted dispatch was rejected.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_GRP_DISP_REJECT], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_GRP_DISP_REJECT] }, [ PPC970_PME_PM_LSU_LDF ] = { .pme_name = "PM_LSU_LDF", .pme_code = 0x8730, .pme_short_desc = "LSU executed Floating Point load instruction", .pme_long_desc = "LSU executed Floating Point load instruction", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_LDF], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_LDF] }, [ PPC970_PME_PM_INST_DISP ] = { .pme_name = "PM_INST_DISP", .pme_code = 0x320, .pme_short_desc = "Instructions dispatched", .pme_long_desc = "The ISU sends the number of instructions dispatched.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_INST_DISP], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_INST_DISP] }, [ PPC970_PME_PM_DATA_FROM_L25_SHR ] = { .pme_name = "PM_DATA_FROM_L25_SHR", .pme_code = 0x183d, .pme_short_desc = "Data loaded from L2.5 shared", .pme_long_desc = "DL1 was reloaded with shared (T or SL) data from the L2 of a chip on this MCM due to a demand load", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_DATA_FROM_L25_SHR], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_DATA_FROM_L25_SHR] }, [ PPC970_PME_PM_L1_DCACHE_RELOAD_VALID ] = { .pme_name = "PM_L1_DCACHE_RELOAD_VALID", .pme_code = 0x834, .pme_short_desc = "L1 reload data source valid", .pme_long_desc = "The data source information is valid", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_L1_DCACHE_RELOAD_VALID], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_L1_DCACHE_RELOAD_VALID] }, [ PPC970_PME_PM_MRK_GRP_ISSUED ] = { .pme_name = "PM_MRK_GRP_ISSUED", .pme_code = 0x6005, .pme_short_desc = "Marked group issued", .pme_long_desc = "A sampled instruction was issued", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_GRP_ISSUED], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_GRP_ISSUED] }, [ PPC970_PME_PM_FPU_FMA ] = { .pme_name = "PM_FPU_FMA", .pme_code = 0x2100, .pme_short_desc = "FPU executed multiply-add instruction", .pme_long_desc = "This signal is active for one cycle when FPU is executing multiply-add kind of instruction. This could be fmadd*, fnmadd*, fmsub*, fnmsub* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU_FMA], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU_FMA] }, [ PPC970_PME_PM_MRK_CRU_FIN ] = { .pme_name = "PM_MRK_CRU_FIN", .pme_code = 0x4005, .pme_short_desc = "Marked instruction CRU processing finished", .pme_long_desc = "The Condition Register Unit finished a marked instruction. Instructions that finish may not necessary complete", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_CRU_FIN], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_CRU_FIN] }, [ PPC970_PME_PM_MRK_LSU1_FLUSH_UST ] = { .pme_name = "PM_MRK_LSU1_FLUSH_UST", .pme_code = 0x715, .pme_short_desc = "LSU1 marked unaligned store flushes", .pme_long_desc = "A marked store was flushed from unit 1 because it was unaligned (crossed a 4k boundary)", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_LSU1_FLUSH_UST], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_LSU1_FLUSH_UST] }, [ PPC970_PME_PM_MRK_FXU_FIN ] = { .pme_name = "PM_MRK_FXU_FIN", .pme_code = 0x6004, .pme_short_desc = "Marked instruction FXU processing finished", .pme_long_desc = "Marked instruction FXU processing finished", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_FXU_FIN], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_FXU_FIN] }, [ PPC970_PME_PM_LSU1_REJECT_ERAT_MISS ] = { .pme_name = "PM_LSU1_REJECT_ERAT_MISS", .pme_code = 0x927, .pme_short_desc = "LSU1 reject due to ERAT miss", .pme_long_desc = "LSU1 reject due to ERAT miss", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU1_REJECT_ERAT_MISS], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU1_REJECT_ERAT_MISS] }, [ PPC970_PME_PM_BR_ISSUED ] = { .pme_name = "PM_BR_ISSUED", .pme_code = 0x431, .pme_short_desc = "Branches issued", .pme_long_desc = "This signal will be asserted each time the ISU issues a branch instruction. This signal will be asserted each time the ISU selects a branch instruction to issue.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_BR_ISSUED], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_BR_ISSUED] }, [ PPC970_PME_PM_PMC4_OVERFLOW ] = { .pme_name = "PM_PMC4_OVERFLOW", .pme_code = 0x500a, .pme_short_desc = "PMC4 Overflow", .pme_long_desc = "PMC4 Overflow", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_PMC4_OVERFLOW], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_PMC4_OVERFLOW] }, [ PPC970_PME_PM_EE_OFF ] = { .pme_name = "PM_EE_OFF", .pme_code = 0x333, .pme_short_desc = "Cycles MSR(EE) bit off", .pme_long_desc = "The number of Cycles MSR(EE) bit was off.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_EE_OFF], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_EE_OFF] }, [ PPC970_PME_PM_INST_FROM_L25_MOD ] = { .pme_name = "PM_INST_FROM_L25_MOD", .pme_code = 0x6426, .pme_short_desc = "Instruction fetched from L2.5 modified", .pme_long_desc = "Instruction fetched from L2.5 modified", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_INST_FROM_L25_MOD], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_INST_FROM_L25_MOD] }, [ PPC970_PME_PM_ITLB_MISS ] = { .pme_name = "PM_ITLB_MISS", .pme_code = 0x700, .pme_short_desc = "Instruction TLB misses", .pme_long_desc = "A TLB miss for an Instruction Fetch has occurred", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_ITLB_MISS], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_ITLB_MISS] }, [ PPC970_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { .pme_name = "PM_FXU1_BUSY_FXU0_IDLE", .pme_code = 0x4002, .pme_short_desc = "FXU1 busy FXU0 idle", .pme_long_desc = "FXU0 was idle while FXU1 was busy", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FXU1_BUSY_FXU0_IDLE], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FXU1_BUSY_FXU0_IDLE] }, [ PPC970_PME_PM_GRP_DISP_VALID ] = { .pme_name = "PM_GRP_DISP_VALID", .pme_code = 0x323, .pme_short_desc = "Group dispatch valid", .pme_long_desc = "Dispatch has been attempted for a valid group. Some groups may be rejected. The total number of successful dispatches is the number of dispatch valid minus dispatch reject.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_GRP_DISP_VALID], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_GRP_DISP_VALID] }, [ PPC970_PME_PM_MRK_GRP_DISP ] = { .pme_name = "PM_MRK_GRP_DISP", .pme_code = 0x1002, .pme_short_desc = "Marked group dispatched", .pme_long_desc = "A group containing a sampled instruction was dispatched", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_GRP_DISP], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_GRP_DISP] }, [ PPC970_PME_PM_LSU_FLUSH_UST ] = { .pme_name = "PM_LSU_FLUSH_UST", .pme_code = 0x2800, .pme_short_desc = "SRQ unaligned store flushes", .pme_long_desc = "A store was flushed because it was unaligned", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_FLUSH_UST], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_FLUSH_UST] }, [ PPC970_PME_PM_FXU1_FIN ] = { .pme_name = "PM_FXU1_FIN", .pme_code = 0x336, .pme_short_desc = "FXU1 produced a result", .pme_long_desc = "The Fixed Point unit 1 finished an instruction and produced a result", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FXU1_FIN], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FXU1_FIN] }, [ PPC970_PME_PM_GRP_CMPL ] = { .pme_name = "PM_GRP_CMPL", .pme_code = 0x7003, .pme_short_desc = "Group completed", .pme_long_desc = "A group completed. Microcoded instructions that span multiple groups will generate this event once per group.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_GRP_CMPL], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_GRP_CMPL] }, [ PPC970_PME_PM_FPU_FRSP_FCONV ] = { .pme_name = "PM_FPU_FRSP_FCONV", .pme_code = 0x7110, .pme_short_desc = "FPU executed FRSP or FCONV instructions", .pme_long_desc = "This signal is active for one cycle when executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs. Combined Unit 0 + Unit 1", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU_FRSP_FCONV], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU_FRSP_FCONV] }, [ PPC970_PME_PM_MRK_LSU0_FLUSH_SRQ ] = { .pme_name = "PM_MRK_LSU0_FLUSH_SRQ", .pme_code = 0x713, .pme_short_desc = "LSU0 marked SRQ flushes", .pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_LSU0_FLUSH_SRQ], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_LSU0_FLUSH_SRQ] }, [ PPC970_PME_PM_LSU_LMQ_FULL_CYC ] = { .pme_name = "PM_LSU_LMQ_FULL_CYC", .pme_code = 0x837, .pme_short_desc = "Cycles LMQ full", .pme_long_desc = "The LMQ was full", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_LMQ_FULL_CYC], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_LMQ_FULL_CYC] }, [ PPC970_PME_PM_ST_REF_L1_LSU0 ] = { .pme_name = "PM_ST_REF_L1_LSU0", .pme_code = 0x811, .pme_short_desc = "LSU0 L1 D cache store references", .pme_long_desc = "A store executed on unit 0", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_ST_REF_L1_LSU0], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_ST_REF_L1_LSU0] }, [ PPC970_PME_PM_LSU0_DERAT_MISS ] = { .pme_name = "PM_LSU0_DERAT_MISS", .pme_code = 0x702, .pme_short_desc = "LSU0 DERAT misses", .pme_long_desc = "A data request (load or store) from LSU Unit 0 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU0_DERAT_MISS], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU0_DERAT_MISS] }, [ PPC970_PME_PM_LSU_SRQ_SYNC_CYC ] = { .pme_name = "PM_LSU_SRQ_SYNC_CYC", .pme_code = 0x735, .pme_short_desc = "SRQ sync duration", .pme_long_desc = "This signal is asserted every cycle when a sync is in the SRQ.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_SRQ_SYNC_CYC], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_SRQ_SYNC_CYC] }, [ PPC970_PME_PM_FPU_STALL3 ] = { .pme_name = "PM_FPU_STALL3", .pme_code = 0x2120, .pme_short_desc = "FPU stalled in pipe3", .pme_long_desc = "FPU has generated a stall in pipe3 due to overflow, underflow, massive cancel, convert to integer (sometimes), or convert from integer (always). This signal is active during the entire duration of the stall. Combined Unit 0 + Unit 1", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU_STALL3], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU_STALL3] }, [ PPC970_PME_PM_LSU_REJECT_ERAT_MISS ] = { .pme_name = "PM_LSU_REJECT_ERAT_MISS", .pme_code = 0x5920, .pme_short_desc = "LSU reject due to ERAT miss", .pme_long_desc = "LSU reject due to ERAT miss", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_REJECT_ERAT_MISS], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_REJECT_ERAT_MISS] }, [ PPC970_PME_PM_MRK_DATA_FROM_L2 ] = { .pme_name = "PM_MRK_DATA_FROM_L2", .pme_code = 0x1937, .pme_short_desc = "Marked data loaded from L2", .pme_long_desc = "DL1 was reloaded from the local L2 due to a marked demand load", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_DATA_FROM_L2], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_DATA_FROM_L2] }, [ PPC970_PME_PM_LSU0_FLUSH_SRQ ] = { .pme_name = "PM_LSU0_FLUSH_SRQ", .pme_code = 0x803, .pme_short_desc = "LSU0 SRQ flushes", .pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU0_FLUSH_SRQ], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU0_FLUSH_SRQ] }, [ PPC970_PME_PM_FPU0_FMOV_FEST ] = { .pme_name = "PM_FPU0_FMOV_FEST", .pme_code = 0x110, .pme_short_desc = "FPU0 executed FMOV or FEST instructions", .pme_long_desc = "This signal is active for one cycle when fp0 is executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU0_FMOV_FEST], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU0_FMOV_FEST] }, [ PPC970_PME_PM_LD_REF_L1_LSU0 ] = { .pme_name = "PM_LD_REF_L1_LSU0", .pme_code = 0x810, .pme_short_desc = "LSU0 L1 D cache load references", .pme_long_desc = "A load executed on unit 0", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LD_REF_L1_LSU0], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LD_REF_L1_LSU0] }, [ PPC970_PME_PM_LSU1_FLUSH_SRQ ] = { .pme_name = "PM_LSU1_FLUSH_SRQ", .pme_code = 0x807, .pme_short_desc = "LSU1 SRQ flushes", .pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group. ", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU1_FLUSH_SRQ], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU1_FLUSH_SRQ] }, [ PPC970_PME_PM_GRP_BR_MPRED ] = { .pme_name = "PM_GRP_BR_MPRED", .pme_code = 0x327, .pme_short_desc = "Group experienced a branch mispredict", .pme_long_desc = "Group experienced a branch mispredict", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_GRP_BR_MPRED], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_GRP_BR_MPRED] }, [ PPC970_PME_PM_LSU_LMQ_S0_ALLOC ] = { .pme_name = "PM_LSU_LMQ_S0_ALLOC", .pme_code = 0x836, .pme_short_desc = "LMQ slot 0 allocated", .pme_long_desc = "The first entry in the LMQ was allocated.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_LMQ_S0_ALLOC], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_LMQ_S0_ALLOC] }, [ PPC970_PME_PM_LSU0_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU0_REJECT_LMQ_FULL", .pme_code = 0x921, .pme_short_desc = "LSU0 reject due to LMQ full or missed data coming", .pme_long_desc = "LSU0 reject due to LMQ full or missed data coming", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU0_REJECT_LMQ_FULL], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU0_REJECT_LMQ_FULL] }, [ PPC970_PME_PM_ST_REF_L1 ] = { .pme_name = "PM_ST_REF_L1", .pme_code = 0x7810, .pme_short_desc = "L1 D cache store references", .pme_long_desc = "Total DL1 Store references", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_ST_REF_L1], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_ST_REF_L1] }, [ PPC970_PME_PM_MRK_VMX_FIN ] = { .pme_name = "PM_MRK_VMX_FIN", .pme_code = 0x3005, .pme_short_desc = "Marked instruction VMX processing finished", .pme_long_desc = "Marked instruction VMX processing finished", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_VMX_FIN], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_VMX_FIN] }, [ PPC970_PME_PM_LSU_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_SRQ_EMPTY_CYC", .pme_code = 0x4003, .pme_short_desc = "Cycles SRQ empty", .pme_long_desc = "The Store Request Queue is empty", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_SRQ_EMPTY_CYC], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_SRQ_EMPTY_CYC] }, [ PPC970_PME_PM_FPU1_STF ] = { .pme_name = "PM_FPU1_STF", .pme_code = 0x126, .pme_short_desc = "FPU1 executed store instruction", .pme_long_desc = "This signal is active for one cycle when fp1 is executing a store instruction.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU1_STF], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU1_STF] }, [ PPC970_PME_PM_RUN_CYC ] = { .pme_name = "PM_RUN_CYC", .pme_code = 0x1005, .pme_short_desc = "Run cycles", .pme_long_desc = "Processor Cycles gated by the run latch", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_RUN_CYC], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_RUN_CYC] }, [ PPC970_PME_PM_LSU_LMQ_S0_VALID ] = { .pme_name = "PM_LSU_LMQ_S0_VALID", .pme_code = 0x835, .pme_short_desc = "LMQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle when the first entry in the LMQ is valid. The LMQ had eight entries that are allocated FIFO", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_LMQ_S0_VALID], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_LMQ_S0_VALID] }, [ PPC970_PME_PM_LSU0_LDF ] = { .pme_name = "PM_LSU0_LDF", .pme_code = 0x730, .pme_short_desc = "LSU0 executed Floating Point load instruction", .pme_long_desc = "A floating point load was executed from LSU unit 0", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU0_LDF], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU0_LDF] }, [ PPC970_PME_PM_LSU_LRQ_S0_VALID ] = { .pme_name = "PM_LSU_LRQ_S0_VALID", .pme_code = 0x822, .pme_short_desc = "LRQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_LRQ_S0_VALID], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_LRQ_S0_VALID] }, [ PPC970_PME_PM_PMC3_OVERFLOW ] = { .pme_name = "PM_PMC3_OVERFLOW", .pme_code = 0x400a, .pme_short_desc = "PMC3 Overflow", .pme_long_desc = "PMC3 Overflow", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_PMC3_OVERFLOW], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_PMC3_OVERFLOW] }, [ PPC970_PME_PM_MRK_IMR_RELOAD ] = { .pme_name = "PM_MRK_IMR_RELOAD", .pme_code = 0x722, .pme_short_desc = "Marked IMR reloaded", .pme_long_desc = "A DL1 reload occured due to marked load", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_IMR_RELOAD], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_IMR_RELOAD] }, [ PPC970_PME_PM_MRK_GRP_TIMEO ] = { .pme_name = "PM_MRK_GRP_TIMEO", .pme_code = 0x5005, .pme_short_desc = "Marked group completion timeout", .pme_long_desc = "The sampling timeout expired indicating that the previously sampled instruction is no longer in the processor", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_GRP_TIMEO], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_GRP_TIMEO] }, [ PPC970_PME_PM_FPU_FMOV_FEST ] = { .pme_name = "PM_FPU_FMOV_FEST", .pme_code = 0x8110, .pme_short_desc = "FPU executing FMOV or FEST instructions", .pme_long_desc = "This signal is active for one cycle when executing a move kind of instruction or one of the estimate instructions.. This could be fmr*, fneg*, fabs*, fnabs* , fres* or frsqrte* where XYZ* means XYZ or XYZ . Combined Unit 0 + Unit 1", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU_FMOV_FEST], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU_FMOV_FEST] }, [ PPC970_PME_PM_GRP_DISP_BLK_SB_CYC ] = { .pme_name = "PM_GRP_DISP_BLK_SB_CYC", .pme_code = 0x331, .pme_short_desc = "Cycles group dispatch blocked by scoreboard", .pme_long_desc = "The ISU sends a signal indicating that dispatch is blocked by scoreboard.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_GRP_DISP_BLK_SB_CYC], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_GRP_DISP_BLK_SB_CYC] }, [ PPC970_PME_PM_XER_MAP_FULL_CYC ] = { .pme_name = "PM_XER_MAP_FULL_CYC", .pme_code = 0x302, .pme_short_desc = "Cycles XER mapper full", .pme_long_desc = "The ISU sends a signal indicating that the xer mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_XER_MAP_FULL_CYC], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_XER_MAP_FULL_CYC] }, [ PPC970_PME_PM_ST_MISS_L1 ] = { .pme_name = "PM_ST_MISS_L1", .pme_code = 0x813, .pme_short_desc = "L1 D cache store misses", .pme_long_desc = "A store missed the dcache", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_ST_MISS_L1], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_ST_MISS_L1] }, [ PPC970_PME_PM_STOP_COMPLETION ] = { .pme_name = "PM_STOP_COMPLETION", .pme_code = 0x3001, .pme_short_desc = "Completion stopped", .pme_long_desc = "RAS Unit has signaled completion to stop", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_STOP_COMPLETION], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_STOP_COMPLETION] }, [ PPC970_PME_PM_MRK_GRP_CMPL ] = { .pme_name = "PM_MRK_GRP_CMPL", .pme_code = 0x4004, .pme_short_desc = "Marked group completed", .pme_long_desc = "A group containing a sampled instruction completed. Microcoded instructions that span multiple groups will generate this event once per group.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_GRP_CMPL], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_GRP_CMPL] }, [ PPC970_PME_PM_ISLB_MISS ] = { .pme_name = "PM_ISLB_MISS", .pme_code = 0x701, .pme_short_desc = "Instruction SLB misses", .pme_long_desc = "A SLB miss for an instruction fetch as occurred", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_ISLB_MISS], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_ISLB_MISS] }, [ PPC970_PME_PM_SUSPENDED ] = { .pme_name = "PM_SUSPENDED", .pme_code = 0x0, .pme_short_desc = "Suspended", .pme_long_desc = "Suspended", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_SUSPENDED], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_SUSPENDED] }, [ PPC970_PME_PM_CYC ] = { .pme_name = "PM_CYC", .pme_code = 0x7, .pme_short_desc = "Processor cycles", .pme_long_desc = "Processor cycles", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_CYC], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_CYC] }, [ PPC970_PME_PM_LD_MISS_L1_LSU1 ] = { .pme_name = "PM_LD_MISS_L1_LSU1", .pme_code = 0x816, .pme_short_desc = "LSU1 L1 D cache load misses", .pme_long_desc = "A load, executing on unit 1, missed the dcache", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LD_MISS_L1_LSU1], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LD_MISS_L1_LSU1] }, [ PPC970_PME_PM_STCX_FAIL ] = { .pme_name = "PM_STCX_FAIL", .pme_code = 0x721, .pme_short_desc = "STCX failed", .pme_long_desc = "A stcx (stwcx or stdcx) failed", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_STCX_FAIL], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_STCX_FAIL] }, [ PPC970_PME_PM_LSU1_SRQ_STFWD ] = { .pme_name = "PM_LSU1_SRQ_STFWD", .pme_code = 0x824, .pme_short_desc = "LSU1 SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load on unit 1", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU1_SRQ_STFWD], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU1_SRQ_STFWD] }, [ PPC970_PME_PM_GRP_DISP ] = { .pme_name = "PM_GRP_DISP", .pme_code = 0x2004, .pme_short_desc = "Group dispatches", .pme_long_desc = "A group was dispatched", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_GRP_DISP], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_GRP_DISP] }, [ PPC970_PME_PM_L2_PREF ] = { .pme_name = "PM_L2_PREF", .pme_code = 0x733, .pme_short_desc = "L2 cache prefetches", .pme_long_desc = "A request to prefetch data into L2 was made", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_L2_PREF], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_L2_PREF] }, [ PPC970_PME_PM_FPU1_DENORM ] = { .pme_name = "PM_FPU1_DENORM", .pme_code = 0x124, .pme_short_desc = "FPU1 received denormalized data", .pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU1_DENORM], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU1_DENORM] }, [ PPC970_PME_PM_DATA_FROM_L2 ] = { .pme_name = "PM_DATA_FROM_L2", .pme_code = 0x1837, .pme_short_desc = "Data loaded from L2", .pme_long_desc = "DL1 was reloaded from the local L2 due to a demand load", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_DATA_FROM_L2], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_DATA_FROM_L2] }, [ PPC970_PME_PM_FPU0_FPSCR ] = { .pme_name = "PM_FPU0_FPSCR", .pme_code = 0x130, .pme_short_desc = "FPU0 executed FPSCR instruction", .pme_long_desc = "This signal is active for one cycle when fp0 is executing fpscr move related instruction. This could be mtfsfi*, mtfsb0*, mtfsb1*. mffs*, mtfsf*, mcrsf* where XYZ* means XYZ, XYZs, XYZ., XYZs", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU0_FPSCR], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU0_FPSCR] }, [ PPC970_PME_PM_MRK_DATA_FROM_L25_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L25_MOD", .pme_code = 0x393d, .pme_short_desc = "Marked data loaded from L2.5 modified", .pme_long_desc = "DL1 was reloaded with modified (M) data from the L2 of a chip on this MCM due to a marked demand load", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_DATA_FROM_L25_MOD], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_DATA_FROM_L25_MOD] }, [ PPC970_PME_PM_FPU0_FSQRT ] = { .pme_name = "PM_FPU0_FSQRT", .pme_code = 0x102, .pme_short_desc = "FPU0 executed FSQRT instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp0 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU0_FSQRT], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU0_FSQRT] }, [ PPC970_PME_PM_LD_REF_L1 ] = { .pme_name = "PM_LD_REF_L1", .pme_code = 0x8810, .pme_short_desc = "L1 D cache load references", .pme_long_desc = "Total DL1 Load references", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LD_REF_L1], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LD_REF_L1] }, [ PPC970_PME_PM_MRK_L1_RELOAD_VALID ] = { .pme_name = "PM_MRK_L1_RELOAD_VALID", .pme_code = 0x934, .pme_short_desc = "Marked L1 reload data source valid", .pme_long_desc = "The source information is valid and is for a marked load", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_L1_RELOAD_VALID], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_L1_RELOAD_VALID] }, [ PPC970_PME_PM_1PLUS_PPC_CMPL ] = { .pme_name = "PM_1PLUS_PPC_CMPL", .pme_code = 0x5003, .pme_short_desc = "One or more PPC instruction completed", .pme_long_desc = "A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_1PLUS_PPC_CMPL], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_1PLUS_PPC_CMPL] }, [ PPC970_PME_PM_INST_FROM_L1 ] = { .pme_name = "PM_INST_FROM_L1", .pme_code = 0x142d, .pme_short_desc = "Instruction fetched from L1", .pme_long_desc = "An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_INST_FROM_L1], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_INST_FROM_L1] }, [ PPC970_PME_PM_EE_OFF_EXT_INT ] = { .pme_name = "PM_EE_OFF_EXT_INT", .pme_code = 0x337, .pme_short_desc = "Cycles MSR(EE) bit off and external interrupt pending", .pme_long_desc = "Cycles MSR(EE) bit off and external interrupt pending", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_EE_OFF_EXT_INT], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_EE_OFF_EXT_INT] }, [ PPC970_PME_PM_PMC6_OVERFLOW ] = { .pme_name = "PM_PMC6_OVERFLOW", .pme_code = 0x700a, .pme_short_desc = "PMC6 Overflow", .pme_long_desc = "PMC6 Overflow", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_PMC6_OVERFLOW], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_PMC6_OVERFLOW] }, [ PPC970_PME_PM_LSU_LRQ_FULL_CYC ] = { .pme_name = "PM_LSU_LRQ_FULL_CYC", .pme_code = 0x312, .pme_short_desc = "Cycles LRQ full", .pme_long_desc = "The ISU sends this signal when the LRQ is full.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_LRQ_FULL_CYC], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_LRQ_FULL_CYC] }, [ PPC970_PME_PM_IC_PREF_INSTALL ] = { .pme_name = "PM_IC_PREF_INSTALL", .pme_code = 0x427, .pme_short_desc = "Instruction prefetched installed in prefetch", .pme_long_desc = "New line coming into the prefetch buffer", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_IC_PREF_INSTALL], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_IC_PREF_INSTALL] }, [ PPC970_PME_PM_DC_PREF_OUT_OF_STREAMS ] = { .pme_name = "PM_DC_PREF_OUT_OF_STREAMS", .pme_code = 0x732, .pme_short_desc = "D cache out of streams", .pme_long_desc = "out of streams", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_DC_PREF_OUT_OF_STREAMS], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_DC_PREF_OUT_OF_STREAMS] }, [ PPC970_PME_PM_MRK_LSU1_FLUSH_SRQ ] = { .pme_name = "PM_MRK_LSU1_FLUSH_SRQ", .pme_code = 0x717, .pme_short_desc = "LSU1 marked SRQ flushes", .pme_long_desc = "A marked store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_LSU1_FLUSH_SRQ], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_LSU1_FLUSH_SRQ] }, [ PPC970_PME_PM_GCT_FULL_CYC ] = { .pme_name = "PM_GCT_FULL_CYC", .pme_code = 0x300, .pme_short_desc = "Cycles GCT full", .pme_long_desc = "The ISU sends a signal indicating the gct is full. ", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_GCT_FULL_CYC], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_GCT_FULL_CYC] }, [ PPC970_PME_PM_INST_FROM_MEM ] = { .pme_name = "PM_INST_FROM_MEM", .pme_code = 0x2426, .pme_short_desc = "Instruction fetched from memory", .pme_long_desc = "Instruction fetched from memory", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_INST_FROM_MEM], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_INST_FROM_MEM] }, [ PPC970_PME_PM_FLUSH_LSU_BR_MPRED ] = { .pme_name = "PM_FLUSH_LSU_BR_MPRED", .pme_code = 0x317, .pme_short_desc = "Flush caused by LSU or branch mispredict", .pme_long_desc = "Flush caused by LSU or branch mispredict", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FLUSH_LSU_BR_MPRED], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FLUSH_LSU_BR_MPRED] }, [ PPC970_PME_PM_FXU_BUSY ] = { .pme_name = "PM_FXU_BUSY", .pme_code = 0x6002, .pme_short_desc = "FXU busy", .pme_long_desc = "FXU0 and FXU1 are both busy", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FXU_BUSY], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FXU_BUSY] }, [ PPC970_PME_PM_ST_REF_L1_LSU1 ] = { .pme_name = "PM_ST_REF_L1_LSU1", .pme_code = 0x815, .pme_short_desc = "LSU1 L1 D cache store references", .pme_long_desc = "A store executed on unit 1", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_ST_REF_L1_LSU1], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_ST_REF_L1_LSU1] }, [ PPC970_PME_PM_MRK_LD_MISS_L1 ] = { .pme_name = "PM_MRK_LD_MISS_L1", .pme_code = 0x1720, .pme_short_desc = "Marked L1 D cache load misses", .pme_long_desc = "Marked L1 D cache load misses", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_LD_MISS_L1], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_LD_MISS_L1] }, [ PPC970_PME_PM_L1_WRITE_CYC ] = { .pme_name = "PM_L1_WRITE_CYC", .pme_code = 0x434, .pme_short_desc = "Cycles writing to instruction L1", .pme_long_desc = "This signal is asserted each cycle a cache write is active.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_L1_WRITE_CYC], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_L1_WRITE_CYC] }, [ PPC970_PME_PM_LSU_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU_REJECT_LMQ_FULL", .pme_code = 0x2920, .pme_short_desc = "LSU reject due to LMQ full or missed data coming", .pme_long_desc = "LSU reject due to LMQ full or missed data coming", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_REJECT_LMQ_FULL], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_REJECT_LMQ_FULL] }, [ PPC970_PME_PM_FPU_ALL ] = { .pme_name = "PM_FPU_ALL", .pme_code = 0x5100, .pme_short_desc = "FPU executed add", .pme_long_desc = " mult", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU_ALL], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU_ALL] }, [ PPC970_PME_PM_LSU_SRQ_S0_ALLOC ] = { .pme_name = "PM_LSU_SRQ_S0_ALLOC", .pme_code = 0x825, .pme_short_desc = "SRQ slot 0 allocated", .pme_long_desc = "SRQ Slot zero was allocated", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_SRQ_S0_ALLOC], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_SRQ_S0_ALLOC] }, [ PPC970_PME_PM_INST_FROM_L25_SHR ] = { .pme_name = "PM_INST_FROM_L25_SHR", .pme_code = 0x5426, .pme_short_desc = "Instruction fetched from L2.5 shared", .pme_long_desc = "Instruction fetched from L2.5 shared", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_INST_FROM_L25_SHR], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_INST_FROM_L25_SHR] }, [ PPC970_PME_PM_GRP_MRK ] = { .pme_name = "PM_GRP_MRK", .pme_code = 0x5004, .pme_short_desc = "Group marked in IDU", .pme_long_desc = "A group was sampled (marked)", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_GRP_MRK], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_GRP_MRK] }, [ PPC970_PME_PM_BR_MPRED_CR ] = { .pme_name = "PM_BR_MPRED_CR", .pme_code = 0x432, .pme_short_desc = "Branch mispredictions due to CR bit setting", .pme_long_desc = "This signal is asserted when the branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This signal is asserted after a branch issue event and will result in a branch redirect flush if not overridden by a flush of an older instruction.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_BR_MPRED_CR], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_BR_MPRED_CR] }, [ PPC970_PME_PM_DC_PREF_STREAM_ALLOC ] = { .pme_name = "PM_DC_PREF_STREAM_ALLOC", .pme_code = 0x737, .pme_short_desc = "D cache new prefetch stream allocated", .pme_long_desc = "A new Prefetch Stream was allocated", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_DC_PREF_STREAM_ALLOC], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_DC_PREF_STREAM_ALLOC] }, [ PPC970_PME_PM_FPU1_FIN ] = { .pme_name = "PM_FPU1_FIN", .pme_code = 0x117, .pme_short_desc = "FPU1 produced a result", .pme_long_desc = "fp1 finished, produced a result. This only indicates finish, not completion. ", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU1_FIN], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU1_FIN] }, [ PPC970_PME_PM_LSU_REJECT_SRQ ] = { .pme_name = "PM_LSU_REJECT_SRQ", .pme_code = 0x1920, .pme_short_desc = "LSU SRQ rejects", .pme_long_desc = "LSU SRQ rejects", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_REJECT_SRQ], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_REJECT_SRQ] }, [ PPC970_PME_PM_BR_MPRED_TA ] = { .pme_name = "PM_BR_MPRED_TA", .pme_code = 0x433, .pme_short_desc = "Branch mispredictions due to target address", .pme_long_desc = "branch miss predict due to a target address prediction. This signal will be asserted each time the branch execution unit detects an incorrect target address prediction. This signal will be asserted after a valid branch execution unit issue and will cause a branch mispredict flush unless a flush is detected from an older instruction.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_BR_MPRED_TA], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_BR_MPRED_TA] }, [ PPC970_PME_PM_CRQ_FULL_CYC ] = { .pme_name = "PM_CRQ_FULL_CYC", .pme_code = 0x311, .pme_short_desc = "Cycles CR issue queue full", .pme_long_desc = "The ISU sends a signal indicating that the issue queue that feeds the ifu cr unit cannot accept any more group (queue is full of groups).", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_CRQ_FULL_CYC], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_CRQ_FULL_CYC] }, [ PPC970_PME_PM_LD_MISS_L1 ] = { .pme_name = "PM_LD_MISS_L1", .pme_code = 0x3810, .pme_short_desc = "L1 D cache load misses", .pme_long_desc = "Total DL1 Load references that miss the DL1", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LD_MISS_L1], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LD_MISS_L1] }, [ PPC970_PME_PM_INST_FROM_PREF ] = { .pme_name = "PM_INST_FROM_PREF", .pme_code = 0x342d, .pme_short_desc = "Instructions fetched from prefetch", .pme_long_desc = "An instruction fetch group was fetched from the prefetch buffer. Fetch Groups can contain up to 8 instructions", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_INST_FROM_PREF], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_INST_FROM_PREF] }, [ PPC970_PME_PM_STCX_PASS ] = { .pme_name = "PM_STCX_PASS", .pme_code = 0x725, .pme_short_desc = "Stcx passes", .pme_long_desc = "A stcx (stwcx or stdcx) instruction was successful", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_STCX_PASS], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_STCX_PASS] }, [ PPC970_PME_PM_DC_INV_L2 ] = { .pme_name = "PM_DC_INV_L2", .pme_code = 0x817, .pme_short_desc = "L1 D cache entries invalidated from L2", .pme_long_desc = "A dcache invalidated was received from the L2 because a line in L2 was castout.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_DC_INV_L2], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_DC_INV_L2] }, [ PPC970_PME_PM_LSU_SRQ_FULL_CYC ] = { .pme_name = "PM_LSU_SRQ_FULL_CYC", .pme_code = 0x313, .pme_short_desc = "Cycles SRQ full", .pme_long_desc = "The ISU sends this signal when the srq is full.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_SRQ_FULL_CYC], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_SRQ_FULL_CYC] }, [ PPC970_PME_PM_LSU0_FLUSH_LRQ ] = { .pme_name = "PM_LSU0_FLUSH_LRQ", .pme_code = 0x802, .pme_short_desc = "LSU0 LRQ flushes", .pme_long_desc = "A load was flushed by unit 1 because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU0_FLUSH_LRQ], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU0_FLUSH_LRQ] }, [ PPC970_PME_PM_LSU_SRQ_S0_VALID ] = { .pme_name = "PM_LSU_SRQ_S0_VALID", .pme_code = 0x821, .pme_short_desc = "SRQ slot 0 valid", .pme_long_desc = "This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_SRQ_S0_VALID], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_SRQ_S0_VALID] }, [ PPC970_PME_PM_LARX_LSU0 ] = { .pme_name = "PM_LARX_LSU0", .pme_code = 0x727, .pme_short_desc = "Larx executed on LSU0", .pme_long_desc = "A larx (lwarx or ldarx) was executed on side 0 (there is no coresponding unit 1 event since larx instructions can only execute on unit 0)", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LARX_LSU0], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LARX_LSU0] }, [ PPC970_PME_PM_GCT_EMPTY_CYC ] = { .pme_name = "PM_GCT_EMPTY_CYC", .pme_code = 0x1004, .pme_short_desc = "Cycles GCT empty", .pme_long_desc = "The Global Completion Table is completely empty", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_GCT_EMPTY_CYC], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_GCT_EMPTY_CYC] }, [ PPC970_PME_PM_FPU1_ALL ] = { .pme_name = "PM_FPU1_ALL", .pme_code = 0x107, .pme_short_desc = "FPU1 executed add", .pme_long_desc = " mult", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU1_ALL], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU1_ALL] }, [ PPC970_PME_PM_FPU1_FSQRT ] = { .pme_name = "PM_FPU1_FSQRT", .pme_code = 0x106, .pme_short_desc = "FPU1 executed FSQRT instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp1 is executing a square root instruction. This could be fsqrt* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU1_FSQRT], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU1_FSQRT] }, [ PPC970_PME_PM_FPU_FIN ] = { .pme_name = "PM_FPU_FIN", .pme_code = 0x4110, .pme_short_desc = "FPU produced a result", .pme_long_desc = "FPU finished, produced a result This only indicates finish, not completion. Combined Unit 0 + Unit 1", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU_FIN], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU_FIN] }, [ PPC970_PME_PM_LSU_SRQ_STFWD ] = { .pme_name = "PM_LSU_SRQ_STFWD", .pme_code = 0x1820, .pme_short_desc = "SRQ store forwarded", .pme_long_desc = "Data from a store instruction was forwarded to a load", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_SRQ_STFWD], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_SRQ_STFWD] }, [ PPC970_PME_PM_MRK_LD_MISS_L1_LSU1 ] = { .pme_name = "PM_MRK_LD_MISS_L1_LSU1", .pme_code = 0x724, .pme_short_desc = "LSU1 L1 D cache load misses", .pme_long_desc = "A marked load, executing on unit 1, missed the dcache", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_LD_MISS_L1_LSU1], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_LD_MISS_L1_LSU1] }, [ PPC970_PME_PM_FXU0_FIN ] = { .pme_name = "PM_FXU0_FIN", .pme_code = 0x332, .pme_short_desc = "FXU0 produced a result", .pme_long_desc = "The Fixed Point unit 0 finished an instruction and produced a result", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FXU0_FIN], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FXU0_FIN] }, [ PPC970_PME_PM_MRK_FPU_FIN ] = { .pme_name = "PM_MRK_FPU_FIN", .pme_code = 0x7004, .pme_short_desc = "Marked instruction FPU processing finished", .pme_long_desc = "One of the Floating Point Units finished a marked instruction. Instructions that finish may not necessary complete", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_FPU_FIN], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_FPU_FIN] }, [ PPC970_PME_PM_PMC5_OVERFLOW ] = { .pme_name = "PM_PMC5_OVERFLOW", .pme_code = 0x600a, .pme_short_desc = "PMC5 Overflow", .pme_long_desc = "PMC5 Overflow", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_PMC5_OVERFLOW], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_PMC5_OVERFLOW] }, [ PPC970_PME_PM_SNOOP_TLBIE ] = { .pme_name = "PM_SNOOP_TLBIE", .pme_code = 0x703, .pme_short_desc = "Snoop TLBIE", .pme_long_desc = "A TLB miss for a data request occurred. Requests that miss the TLB may be retried until the instruction is in the next to complete group (unless HID4 is set to allow speculative tablewalks). This may result in multiple TLB misses for the same instruction.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_SNOOP_TLBIE], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_SNOOP_TLBIE] }, [ PPC970_PME_PM_FPU1_FRSP_FCONV ] = { .pme_name = "PM_FPU1_FRSP_FCONV", .pme_code = 0x115, .pme_short_desc = "FPU1 executed FRSP or FCONV instructions", .pme_long_desc = "This signal is active for one cycle when fp1 is executing frsp or convert kind of instruction. This could be frsp*, fcfid*, fcti* where XYZ* means XYZ, XYZs, XYZ., XYZs.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU1_FRSP_FCONV], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU1_FRSP_FCONV] }, [ PPC970_PME_PM_FPU0_FDIV ] = { .pme_name = "PM_FPU0_FDIV", .pme_code = 0x100, .pme_short_desc = "FPU0 executed FDIV instruction", .pme_long_desc = "This signal is active for one cycle at the end of the microcode executed when fp0 is executing a divide instruction. This could be fdiv, fdivs, fdiv. fdivs.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU0_FDIV], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU0_FDIV] }, [ PPC970_PME_PM_LD_REF_L1_LSU1 ] = { .pme_name = "PM_LD_REF_L1_LSU1", .pme_code = 0x814, .pme_short_desc = "LSU1 L1 D cache load references", .pme_long_desc = "A load executed on unit 1", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LD_REF_L1_LSU1], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LD_REF_L1_LSU1] }, [ PPC970_PME_PM_HV_CYC ] = { .pme_name = "PM_HV_CYC", .pme_code = 0x3004, .pme_short_desc = "Hypervisor Cycles", .pme_long_desc = "Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0)", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_HV_CYC], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_HV_CYC] }, [ PPC970_PME_PM_LR_CTR_MAP_FULL_CYC ] = { .pme_name = "PM_LR_CTR_MAP_FULL_CYC", .pme_code = 0x306, .pme_short_desc = "Cycles LR/CTR mapper full", .pme_long_desc = "The ISU sends a signal indicating that the lr/ctr mapper cannot accept any more groups. Dispatch is stopped. Note: this condition indicates that a pool of mapper is full but the entire mapper may not be.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LR_CTR_MAP_FULL_CYC], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LR_CTR_MAP_FULL_CYC] }, [ PPC970_PME_PM_FPU_DENORM ] = { .pme_name = "PM_FPU_DENORM", .pme_code = 0x1120, .pme_short_desc = "FPU received denormalized data", .pme_long_desc = "This signal is active for one cycle when one of the operands is denormalized. Combined Unit 0 + Unit 1", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_FPU_DENORM], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_FPU_DENORM] }, [ PPC970_PME_PM_LSU0_REJECT_SRQ ] = { .pme_name = "PM_LSU0_REJECT_SRQ", .pme_code = 0x920, .pme_short_desc = "LSU0 SRQ rejects", .pme_long_desc = "LSU0 SRQ rejects", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU0_REJECT_SRQ], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU0_REJECT_SRQ] }, [ PPC970_PME_PM_LSU1_REJECT_SRQ ] = { .pme_name = "PM_LSU1_REJECT_SRQ", .pme_code = 0x924, .pme_short_desc = "LSU1 SRQ rejects", .pme_long_desc = "LSU1 SRQ rejects", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU1_REJECT_SRQ], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU1_REJECT_SRQ] }, [ PPC970_PME_PM_LSU1_DERAT_MISS ] = { .pme_name = "PM_LSU1_DERAT_MISS", .pme_code = 0x706, .pme_short_desc = "LSU1 DERAT misses", .pme_long_desc = "A data request (load or store) from LSU Unit 1 missed the ERAT and resulted in an ERAT reload. Multiple instructions may miss the ERAT entry for the same 4K page, but only one reload will occur.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU1_DERAT_MISS], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU1_DERAT_MISS] }, [ PPC970_PME_PM_IC_PREF_REQ ] = { .pme_name = "PM_IC_PREF_REQ", .pme_code = 0x426, .pme_short_desc = "Instruction prefetch requests", .pme_long_desc = "Asserted when a non-canceled prefetch is made to the cache interface unit (CIU).", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_IC_PREF_REQ], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_IC_PREF_REQ] }, [ PPC970_PME_PM_MRK_LSU_FIN ] = { .pme_name = "PM_MRK_LSU_FIN", .pme_code = 0x8004, .pme_short_desc = "Marked instruction LSU processing finished", .pme_long_desc = "One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_LSU_FIN], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_LSU_FIN] }, [ PPC970_PME_PM_MRK_DATA_FROM_MEM ] = { .pme_name = "PM_MRK_DATA_FROM_MEM", .pme_code = 0x3937, .pme_short_desc = "Marked data loaded from memory", .pme_long_desc = "Marked data loaded from memory", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_MRK_DATA_FROM_MEM], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_MRK_DATA_FROM_MEM] }, [ PPC970_PME_PM_LSU0_FLUSH_UST ] = { .pme_name = "PM_LSU0_FLUSH_UST", .pme_code = 0x801, .pme_short_desc = "LSU0 unaligned store flushes", .pme_long_desc = "A store was flushed from unit 0 because it was unaligned (crossed a 4k boundary)", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU0_FLUSH_UST], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU0_FLUSH_UST] }, [ PPC970_PME_PM_LSU_FLUSH_LRQ ] = { .pme_name = "PM_LSU_FLUSH_LRQ", .pme_code = 0x6800, .pme_short_desc = "LRQ flushes", .pme_long_desc = "A load was flushed because a younger load executed before an older store executed and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_FLUSH_LRQ], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_FLUSH_LRQ] }, [ PPC970_PME_PM_LSU_FLUSH_SRQ ] = { .pme_name = "PM_LSU_FLUSH_SRQ", .pme_code = 0x5800, .pme_short_desc = "SRQ flushes", .pme_long_desc = "A store was flushed because younger load hits and older store that is already in the SRQ or in the same group.", .pme_event_ids = ppc970_event_ids[PPC970_PME_PM_LSU_FLUSH_SRQ], .pme_group_vector = ppc970_group_vecs[PPC970_PME_PM_LSU_FLUSH_SRQ] } }; #define PPC970_PME_EVENT_COUNT 215 static const int ppc970_group_event_ids[][PPC970_NUM_EVENT_COUNTERS] = { [ 0 ] = { 82, 2, 67, 30, 0, 2, 28, 29 }, [ 1 ] = { 2, 2, 37, 6, 41, 37, 63, 37 }, [ 2 ] = { 37, 2, 37, 6, 41, 37, 63, 37 }, [ 3 ] = { 65, 64, 4, 30, 67, 65, 63, 37 }, [ 4 ] = { 27, 25, 22, 22, 3, 26, 30, 22 }, [ 5 ] = { 26, 26, 4, 30, 27, 27, 21, 43 }, [ 6 ] = { 88, 1, 3, 29, 46, 38, 30, 4 }, [ 7 ] = { 13, 21, 23, 24, 3, 37, 46, 49 }, [ 8 ] = { 38, 2, 25, 27, 35, 32, 30, 4 }, [ 9 ] = { 28, 84, 67, 10, 3, 37, 8, 10 }, [ 10 ] = { 10, 18, 17, 21, 12, 20, 30, 4 }, [ 11 ] = { 12, 20, 14, 19, 9, 17, 30, 4 }, [ 12 ] = { 9, 17, 15, 20, 3, 37, 12, 18 }, [ 13 ] = { 15, 23, 14, 19, 3, 37, 4, 16 }, [ 14 ] = { 46, 55, 4, 5, 49, 56, 30, 4 }, [ 15 ] = { 48, 57, 40, 38, 3, 37, 35, 36 }, [ 16 ] = { 49, 58, 69, 65, 3, 37, 62, 5 }, [ 17 ] = { 54, 63, 69, 65, 84, 2, 30, 4 }, [ 18 ] = { 45, 54, 4, 5, 40, 2, 31, 4 }, [ 19 ] = { 28, 65, 30, 5, 0, 37, 28, 67 }, [ 20 ] = { 27, 25, 27, 22, 3, 26, 30, 22 }, [ 21 ] = { 6, 41, 37, 63, 3, 37, 63, 37 }, [ 22 ] = { 6, 65, 37, 63, 3, 37, 63, 37 }, [ 23 ] = { 27, 25, 14, 19, 3, 27, 30, 43 }, [ 24 ] = { 37, 2, 37, 1, 84, 2, 1, 2 }, [ 25 ] = { 37, 2, 37, 1, 3, 84, 63, 37 }, [ 26 ] = { 82, 4, 0, 2, 43, 2, 30, 2 }, [ 27 ] = { 3, 37, 5, 5, 4, 3, 44, 47 }, [ 28 ] = { 6, 41, 31, 5, 68, 67, 32, 34 }, [ 29 ] = { 40, 39, 30, 30, 5, 2, 28, 5 }, [ 30 ] = { 69, 70, 37, 49, 40, 37, 4, 37 }, [ 31 ] = { 39, 36, 31, 5, 40, 2, 30, 4 }, [ 32 ] = { 28, 33, 33, 30, 41, 64, 63, 4 }, [ 33 ] = { 75, 83, 4, 51, 36, 73, 50, 30 }, [ 34 ] = { 73, 71, 4, 50, 36, 72, 49, 60 }, [ 35 ] = { 79, 2, 64, 51, 74, 78, 60, 30 }, [ 36 ] = { 80, 72, 58, 60, 3, 37, 54, 58 }, [ 37 ] = { 76, 74, 55, 57, 3, 37, 53, 57 }, [ 38 ] = { 37, 37, 27, 26, 29, 28, 24, 4 }, [ 39 ] = { 37, 2, 24, 23, 29, 28, 25, 26 }, [ 40 ] = { 39, 39, 32, 0, 40, 2, 4, 30 }, [ 41 ] = { 40, 39, 32, 0, 42, 39, 4, 30 } }; static const pmg_power_group_t ppc970_groups[] = { [ 0 ] = { .pmg_name = "pm_slice0", .pmg_desc = "Time Slice 0", .pmg_event_ids = ppc970_group_event_ids[0], .pmg_mmcr0 = 0x000000000000051eULL, .pmg_mmcr1 = 0x000000000a46f18cULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 1 ] = { .pmg_name = "pm_eprof", .pmg_desc = "Group for use with eprof", .pmg_event_ids = ppc970_group_event_ids[1], .pmg_mmcr0 = 0x0000000000000f1eULL, .pmg_mmcr1 = 0x4003001005f09000ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 2 ] = { .pmg_name = "pm_basic", .pmg_desc = "Basic performance indicators", .pmg_event_ids = ppc970_group_event_ids[2], .pmg_mmcr0 = 0x000000000000091eULL, .pmg_mmcr1 = 0x4003001005f09000ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 3 ] = { .pmg_name = "pm_lsu", .pmg_desc = "Information on the Load Store Unit", .pmg_event_ids = ppc970_group_event_ids[3], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000f00007a400000ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 4 ] = { .pmg_name = "pm_fpu1", .pmg_desc = "Floating Point events", .pmg_event_ids = ppc970_group_event_ids[4], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000001e0480ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 5 ] = { .pmg_name = "pm_fpu2", .pmg_desc = "Floating Point events", .pmg_event_ids = ppc970_group_event_ids[5], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000020e87a400000ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 6 ] = { .pmg_name = "pm_isu_rename", .pmg_desc = "ISU Rename Pool Events", .pmg_event_ids = ppc970_group_event_ids[6], .pmg_mmcr0 = 0x0000000000001228ULL, .pmg_mmcr1 = 0x400000218e6d84bcULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 7 ] = { .pmg_name = "pm_isu_queues1", .pmg_desc = "ISU Rename Pool Events", .pmg_event_ids = ppc970_group_event_ids[7], .pmg_mmcr0 = 0x000000000000132eULL, .pmg_mmcr1 = 0x40000000851e994cULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 8 ] = { .pmg_name = "pm_isu_flow", .pmg_desc = "ISU Instruction Flow Events", .pmg_event_ids = ppc970_group_event_ids[8], .pmg_mmcr0 = 0x000000000000181eULL, .pmg_mmcr1 = 0x400000b3d7b7c4bcULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 9 ] = { .pmg_name = "pm_isu_work", .pmg_desc = "ISU Indicators of Work Blockage", .pmg_event_ids = ppc970_group_event_ids[9], .pmg_mmcr0 = 0x0000000000000402ULL, .pmg_mmcr1 = 0x400000050fde9d88ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 10 ] = { .pmg_name = "pm_fpu3", .pmg_desc = "Floating Point events by unit", .pmg_event_ids = ppc970_group_event_ids[10], .pmg_mmcr0 = 0x0000000000001028ULL, .pmg_mmcr1 = 0x000000008d6354bcULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 11 ] = { .pmg_name = "pm_fpu4", .pmg_desc = "Floating Point events by unit", .pmg_event_ids = ppc970_group_event_ids[11], .pmg_mmcr0 = 0x000000000000122cULL, .pmg_mmcr1 = 0x000000009de774bcULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 12 ] = { .pmg_name = "pm_fpu5", .pmg_desc = "Floating Point events by unit", .pmg_event_ids = ppc970_group_event_ids[12], .pmg_mmcr0 = 0x0000000000001838ULL, .pmg_mmcr1 = 0x000000c0851e9958ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 13 ] = { .pmg_name = "pm_fpu7", .pmg_desc = "Floating Point events by unit", .pmg_event_ids = ppc970_group_event_ids[13], .pmg_mmcr0 = 0x000000000000193aULL, .pmg_mmcr1 = 0x000000c89dde97e0ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 14 ] = { .pmg_name = "pm_lsu_flush", .pmg_desc = "LSU Flush Events", .pmg_event_ids = ppc970_group_event_ids[14], .pmg_mmcr0 = 0x000000000000122cULL, .pmg_mmcr1 = 0x000c00007be774bcULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 15 ] = { .pmg_name = "pm_lsu_load1", .pmg_desc = "LSU Load Events", .pmg_event_ids = ppc970_group_event_ids[15], .pmg_mmcr0 = 0x0000000000001028ULL, .pmg_mmcr1 = 0x000f0000851e9958ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 16 ] = { .pmg_name = "pm_lsu_store1", .pmg_desc = "LSU Store Events", .pmg_event_ids = ppc970_group_event_ids[16], .pmg_mmcr0 = 0x000000000000112aULL, .pmg_mmcr1 = 0x000f00008d5e99dcULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 17 ] = { .pmg_name = "pm_lsu_store2", .pmg_desc = "LSU Store Events", .pmg_event_ids = ppc970_group_event_ids[17], .pmg_mmcr0 = 0x0000000000001838ULL, .pmg_mmcr1 = 0x0003c0d08d76f4bcULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 18 ] = { .pmg_name = "pm_lsu7", .pmg_desc = "Information on the Load Store Unit", .pmg_event_ids = ppc970_group_event_ids[18], .pmg_mmcr0 = 0x000000000000122cULL, .pmg_mmcr1 = 0x000830047bd2fe3cULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 19 ] = { .pmg_name = "pm_misc", .pmg_desc = "Misc Events for testing", .pmg_event_ids = ppc970_group_event_ids[19], .pmg_mmcr0 = 0x0000000000000404ULL, .pmg_mmcr1 = 0x0000000023c69194ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 20 ] = { .pmg_name = "pm_pe_bench1", .pmg_desc = "PE Benchmarker group for FP analysis", .pmg_event_ids = ppc970_group_event_ids[20], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x10001002001e0480ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 21 ] = { .pmg_name = "pm_pe_bench4", .pmg_desc = "PE Benchmarker group for L1 and TLB", .pmg_event_ids = ppc970_group_event_ids[21], .pmg_mmcr0 = 0x0000000000001420ULL, .pmg_mmcr1 = 0x000b000004de9000ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 22 ] = { .pmg_name = "pm_hpmcount1", .pmg_desc = "Hpmcount group for L1 and TLB behavior", .pmg_event_ids = ppc970_group_event_ids[22], .pmg_mmcr0 = 0x0000000000001404ULL, .pmg_mmcr1 = 0x000b000004de9000ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 23 ] = { .pmg_name = "pm_hpmcount2", .pmg_desc = "Hpmcount group for computation", .pmg_event_ids = ppc970_group_event_ids[23], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000020289dde0480ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 24 ] = { .pmg_name = "pm_l1andbr", .pmg_desc = "L1 misses and branch misspredict analysis", .pmg_event_ids = ppc970_group_event_ids[24], .pmg_mmcr0 = 0x000000000000091eULL, .pmg_mmcr1 = 0x8003c01d0636fce8ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 25 ] = { .pmg_name = "Instruction mix: loads", .pmg_desc = " stores and branches", .pmg_event_ids = ppc970_group_event_ids[25], .pmg_mmcr0 = 0x000000000000091eULL, .pmg_mmcr1 = 0x8003c021061fb000ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 26 ] = { .pmg_name = "pm_branch", .pmg_desc = "SLB and branch misspredict analysis", .pmg_event_ids = ppc970_group_event_ids[26], .pmg_mmcr0 = 0x000000000000052aULL, .pmg_mmcr1 = 0x8008000bc662f4e8ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 27 ] = { .pmg_name = "pm_data", .pmg_desc = "data source and LMQ", .pmg_event_ids = ppc970_group_event_ids[27], .pmg_mmcr0 = 0x0000000000000712ULL, .pmg_mmcr1 = 0x0000300e3bce7f74ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 28 ] = { .pmg_name = "pm_tlb", .pmg_desc = "TLB and LRQ plus data prefetch", .pmg_event_ids = ppc970_group_event_ids[28], .pmg_mmcr0 = 0x0000000000001420ULL, .pmg_mmcr1 = 0x0008e03c4bfdacecULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 29 ] = { .pmg_name = "pm_isource", .pmg_desc = "inst source and tablewalk", .pmg_event_ids = ppc970_group_event_ids[29], .pmg_mmcr0 = 0x000000000000060cULL, .pmg_mmcr1 = 0x800b00c0226ef1dcULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 30 ] = { .pmg_name = "pm_sync", .pmg_desc = "Sync and SRQ", .pmg_event_ids = ppc970_group_event_ids[30], .pmg_mmcr0 = 0x0000000000001d32ULL, .pmg_mmcr1 = 0x0003e0c107529780ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 31 ] = { .pmg_name = "pm_ierat", .pmg_desc = "IERAT", .pmg_event_ids = ppc970_group_event_ids[31], .pmg_mmcr0 = 0x0000000000000d3eULL, .pmg_mmcr1 = 0x800000c04bd2f4bcULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 32 ] = { .pmg_name = "pm_derat", .pmg_desc = "DERAT", .pmg_event_ids = ppc970_group_event_ids[32], .pmg_mmcr0 = 0x0000000000000436ULL, .pmg_mmcr1 = 0x100b7052e274003cULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 33 ] = { .pmg_name = "pm_mark1", .pmg_desc = "Information on marked instructions", .pmg_event_ids = ppc970_group_event_ids[33], .pmg_mmcr0 = 0x0000000000000006ULL, .pmg_mmcr1 = 0x00008080790852a4ULL, .pmg_mmcra = 0x0000000000002001ULL }, [ 34 ] = { .pmg_name = "pm_mark2", .pmg_desc = "Marked Instructions Processing Flow", .pmg_event_ids = ppc970_group_event_ids[34], .pmg_mmcr0 = 0x000000000000020aULL, .pmg_mmcr1 = 0x0000000079484210ULL, .pmg_mmcra = 0x0000000000002001ULL }, [ 35 ] = { .pmg_name = "pm_mark3", .pmg_desc = "Marked Stores Processing Flow", .pmg_event_ids = ppc970_group_event_ids[35], .pmg_mmcr0 = 0x000000000000031eULL, .pmg_mmcr1 = 0x00203004190a3f24ULL, .pmg_mmcra = 0x0000000000002001ULL }, [ 36 ] = { .pmg_name = "pm_lsu_mark1", .pmg_desc = "Load Store Unit Marked Events", .pmg_event_ids = ppc970_group_event_ids[36], .pmg_mmcr0 = 0x0000000000001b34ULL, .pmg_mmcr1 = 0x000280c08d5e9850ULL, .pmg_mmcra = 0x0000000000002001ULL }, [ 37 ] = { .pmg_name = "pm_lsu_mark2", .pmg_desc = "Load Store Unit Marked Events", .pmg_event_ids = ppc970_group_event_ids[37], .pmg_mmcr0 = 0x0000000000001838ULL, .pmg_mmcr1 = 0x000280c0959e99dcULL, .pmg_mmcra = 0x0000000000002001ULL }, [ 38 ] = { .pmg_name = "pm_fxu1", .pmg_desc = "Fixed Point events by unit", .pmg_event_ids = ppc970_group_event_ids[38], .pmg_mmcr0 = 0x0000000000000912ULL, .pmg_mmcr1 = 0x100010020084213cULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 39 ] = { .pmg_name = "pm_fxu2", .pmg_desc = "Fixed Point events by unit", .pmg_event_ids = ppc970_group_event_ids[39], .pmg_mmcr0 = 0x000000000000091eULL, .pmg_mmcr1 = 0x4000000ca4042d78ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 40 ] = { .pmg_name = "pm_ifu", .pmg_desc = "Instruction Fetch Unit events", .pmg_event_ids = ppc970_group_event_ids[40], .pmg_mmcr0 = 0x0000000000000d0cULL, .pmg_mmcr1 = 0x800000c06b52f7a4ULL, .pmg_mmcra = 0x0000000000002000ULL }, [ 41 ] = { .pmg_name = "pm_L1_icm", .pmg_desc = " Level 1 instruction cache misses", .pmg_event_ids = ppc970_group_event_ids[41], .pmg_mmcr0 = 0x000000000000060cULL, .pmg_mmcr1 = 0x800000f06b4c67a4ULL, .pmg_mmcra = 0x0000000000002000ULL } }; #endif papi-5.5.1/src/libpfm-3.y/lib/pfmlib_power6_priv.h0000644000307100002310000000117313013651450021656 0ustar yarkhangraduate/****************************/ /* THIS IS OPEN SOURCE CODE */ /****************************/ #ifndef __PFMLIB_POWER6_PRIV_H__ #define __PFMLIB_POWER6_PRIV_H__ /* * File: pfmlib_power6_priv.h * CVS: * Author: Corey Ashford * cjashfor@us.ibm.com * Mods: * * * (C) Copyright IBM Corporation, 2007. All Rights Reserved. * Contributed by Corey Ashford * * Note: This code was automatically generated and should not be modified by * hand. * */ #define POWER6_NUM_EVENT_COUNTERS 6 #define POWER6_NUM_GROUP_VEC 4 #define POWER6_NUM_CONTROL_REGS 3 #endif papi-5.5.1/src/libpfm-3.y/lib/pfmlib_intel_nhm.c0000644000307100002310000012734013013651450021351 0ustar yarkhangraduate/* * pfmlib_intel_nhm.c : Intel Nehalem PMU * * Copyright (c) 2008 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * Nehalem PMU = architectural perfmon v3 + OFFCORE + PEBS v2 + uncore PMU + LBR */ #include #include #include #include #include /* public headers */ #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_intel_nhm_priv.h" /* Intel Westmere event tables */ #include "intel_wsm_events.h" #include "intel_wsm_unc_events.h" /* Intel Core i7 event tables */ #include "intel_corei7_events.h" #include "intel_corei7_unc_events.h" /* let's define some handy shortcuts! */ #define usel_event unc_perfevtsel.usel_event #define usel_umask unc_perfevtsel.usel_umask #define usel_occ unc_perfevtsel.usel_occ #define usel_edge unc_perfevtsel.usel_edge #define usel_int unc_perfevtsel.usel_int #define usel_en unc_perfevtsel.usel_en #define usel_inv unc_perfevtsel.usel_inv #define usel_cnt_mask unc_perfevtsel.usel_cnt_mask #define sel_event perfevtsel.sel_event #define sel_umask perfevtsel.sel_umask #define sel_usr perfevtsel.sel_usr #define sel_os perfevtsel.sel_os #define sel_edge perfevtsel.sel_edge #define sel_pc perfevtsel.sel_pc #define sel_int perfevtsel.sel_int #define sel_en perfevtsel.sel_en #define sel_inv perfevtsel.sel_inv #define sel_anythr perfevtsel.sel_anythr #define sel_cnt_mask perfevtsel.sel_cnt_mask /* * Description of the PMC registers mappings: * * 0 -> PMC0 -> PERFEVTSEL0 * 1 -> PMC1 -> PERFEVTSEL1 * 2 -> PMC2 -> PERFEVTSEL2 * 3 -> PMC3 -> PERFEVTSEL3 * 16 -> PMC16 -> FIXED_CTR_CTRL * 17 -> PMC17 -> PEBS_ENABLED * 18 -> PMC18 -> PEBS_LD_LATENCY_THRESHOLD * 19 -> PMC19 -> OFFCORE_RSP0 * 20 -> PMC20 -> UNCORE_FIXED_CTRL * 21 -> PMC21 -> UNCORE_EVNTSEL0 * 22 -> PMC22 -> UNCORE_EVNTSEL1 * 23 -> PMC23 -> UNCORE_EVNTSEL2 * 24 -> PMC24 -> UNCORE_EVNTSEL3 * 25 -> PMC25 -> UNCORE_EVNTSEL4 * 26 -> PMC26 -> UNCORE_EVNTSEL5 * 27 -> PMC27 -> UNCORE_EVNTSEL6 * 28 -> PMC28 -> UNCORE_EVNTSEL7 * 29 -> PMC31 -> UNCORE_ADDROP_MATCH * 30 -> PMC32 -> LBR_SELECT * * Description of the PMD registers mapping: * * 0 -> PMD0 -> PMC0 * 1 -> PMD1 -> PMC1 * 2 -> PMD2 -> PMC2 * 3 -> PMD3 -> PMC3 * 16 -> PMD16 -> FIXED_CTR0 * 17 -> PMD17 -> FIXED_CTR1 * 18 -> PMD18 -> FIXED_CTR2 * 19 not used * 20 -> PMD20 -> UNCORE_FIXED_CTR0 * 21 -> PMD21 -> UNCORE_PMC0 * 22 -> PMD22 -> UNCORE_PMC1 * 23 -> PMD23 -> UNCORE_PMC2 * 24 -> PMD24 -> UNCORE_PMC3 * 25 -> PMD25 -> UNCORE_PMC4 * 26 -> PMD26 -> UNCORE_PMC5 * 27 -> PMD27 -> UNCORE_PMC6 * 28 -> PMD28 -> UNCORE_PMC7 * * 31 -> PMD31 -> LBR_TOS * 32-63 -> PMD32-PMD63 -> LBR_FROM_0/LBR_TO_0 - LBR_FROM15/LBR_TO_15 */ #define NHM_SEL_BASE 0x186 #define NHM_CTR_BASE 0xc1 #define NHM_FIXED_CTR_BASE 0x309 #define UNC_NHM_SEL_BASE 0x3c0 #define UNC_NHM_CTR_BASE 0x3b0 #define UNC_NHM_FIXED_CTR_BASE 0x394 #define MAX_COUNTERS 28 /* highest implemented counter */ #define PFMLIB_NHM_ALL_FLAGS \ (PFM_NHM_SEL_INV|PFM_NHM_SEL_EDGE|PFM_NHM_SEL_ANYTHR) #define NHM_NUM_GEN_COUNTERS 4 #define NHM_NUM_FIXED_COUNTERS 3 pfm_pmu_support_t intel_nhm_support; pfm_pmu_support_t intel_wsm_support; static pfmlib_regmask_t nhm_impl_pmcs, nhm_impl_pmds; static pfmlib_regmask_t nhm_impl_unc_pmcs, nhm_impl_unc_pmds; static pme_nhm_entry_t *pe, *unc_pe; static unsigned int num_pe, num_unc_pe; static int cpu_model, aaj80; static int pme_cycles, pme_instr; #ifdef __i386__ static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx) { /* * because ebx is used in Pic mode, we need to save/restore because * cpuid clobbers it. I could not figure out a way to get ebx out in * one cpuid instruction. To extract ebx, we need to move it to another * register (here eax) */ __asm__("pushl %%ebx;cpuid; popl %%ebx" :"=a" (*eax) : "a" (op) : "ecx", "edx"); __asm__("pushl %%ebx;cpuid; movl %%ebx, %%eax;popl %%ebx" :"=a" (*ebx) : "a" (op) : "ecx", "edx"); } #else static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx) { __asm__("cpuid" : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx) : "0" (op), "c"(0)); } #endif static inline pme_nhm_entry_t * get_nhm_entry(unsigned int i) { return i < num_pe ? pe+i : unc_pe+(i-num_pe); } static int pfm_nhm_midx2uidx(unsigned int ev, unsigned int midx) { int i, num = 0; pme_nhm_entry_t *ne; int model; ne = get_nhm_entry(ev); for (i=0; i < ne->pme_numasks; i++) { model = ne->pme_umasks[i].pme_umodel; if (!model || model == cpu_model) { if (midx == num) return i; num++; } } DPRINT("cannot find umask %d for event %s\n", midx, ne->pme_name); return -1; } static int pfm_nhm_detect_common(void) { int ret; int family; char buffer[128]; ret = __pfm_getcpuinfo_attr("vendor_id", buffer, sizeof(buffer)); if (ret == -1) return PFMLIB_ERR_NOTSUPP; if (strcmp(buffer, "GenuineIntel")) return PFMLIB_ERR_NOTSUPP; ret = __pfm_getcpuinfo_attr("cpu family", buffer, sizeof(buffer)); if (ret == -1) return PFMLIB_ERR_NOTSUPP; family = atoi(buffer); ret = __pfm_getcpuinfo_attr("model", buffer, sizeof(buffer)); if (ret == -1) return PFMLIB_ERR_NOTSUPP; cpu_model = atoi(buffer); if (family != 6) return PFMLIB_ERR_NOTSUPP; return PFMLIB_SUCCESS; } static int pfm_nhm_detect(void) { #define INTEL_ARCH_MISP_BR_RETIRED (1 << 6) unsigned int eax, ebx, ecx, edx; int ret; ret = pfm_nhm_detect_common(); if (ret != PFMLIB_SUCCESS) return ret; switch(cpu_model) { case 26: /* Nehalem */ case 30: case 31: case 46: /* * check for erratum AAJ80 * * MISPREDICTED_BRANCH_RETIRED may be broken * in which case it appears in the list of * unavailable architected events */ cpuid(0xa, &eax, &ebx, &ecx, &edx); if (ebx & INTEL_ARCH_MISP_BR_RETIRED) aaj80 = 1; break; default: return PFMLIB_ERR_NOTSUPP; } return PFMLIB_SUCCESS; } static int pfm_wsm_detect(void) { switch(cpu_model) { case 37: /* Westmere */ case 44: break; default: return PFMLIB_ERR_NOTSUPP; } return PFMLIB_SUCCESS; } static inline void setup_nhm_impl_unc_regs(void) { pfm_regmask_set(&nhm_impl_unc_pmds, 20); pfm_regmask_set(&nhm_impl_unc_pmds, 21); pfm_regmask_set(&nhm_impl_unc_pmds, 22); pfm_regmask_set(&nhm_impl_unc_pmds, 23); pfm_regmask_set(&nhm_impl_unc_pmds, 24); pfm_regmask_set(&nhm_impl_unc_pmds, 25); pfm_regmask_set(&nhm_impl_unc_pmds, 26); pfm_regmask_set(&nhm_impl_unc_pmds, 27); pfm_regmask_set(&nhm_impl_unc_pmds, 28); /* uncore */ pfm_regmask_set(&nhm_impl_unc_pmcs, 20); pfm_regmask_set(&nhm_impl_unc_pmcs, 21); pfm_regmask_set(&nhm_impl_unc_pmcs, 22); pfm_regmask_set(&nhm_impl_unc_pmcs, 23); pfm_regmask_set(&nhm_impl_unc_pmcs, 24); pfm_regmask_set(&nhm_impl_unc_pmcs, 25); pfm_regmask_set(&nhm_impl_unc_pmcs, 26); pfm_regmask_set(&nhm_impl_unc_pmcs, 27); pfm_regmask_set(&nhm_impl_unc_pmcs, 28); /* unnhm_addrop_match */ pfm_regmask_set(&nhm_impl_unc_pmcs, 29); } static void fixup_mem_uncore_retired(void) { size_t i; for(i=0; i < PME_COREI7_EVENT_COUNT; i++) { if (corei7_pe[i].pme_code != 0xf) continue; /* * assume model46 umasks are at the end */ corei7_pe[i].pme_numasks = 6; break; } } static int pfm_nhm_init(void) { pfm_pmu_support_t *supp; int i; int num_unc_cnt = 0; if (forced_pmu != PFMLIB_NO_PMU) { if (forced_pmu == PFMLIB_INTEL_NHM_PMU) cpu_model = 26; else cpu_model = 37; } /* core */ pfm_regmask_set(&nhm_impl_pmcs, 0); pfm_regmask_set(&nhm_impl_pmcs, 1); pfm_regmask_set(&nhm_impl_pmcs, 2); pfm_regmask_set(&nhm_impl_pmcs, 3); pfm_regmask_set(&nhm_impl_pmcs, 16); pfm_regmask_set(&nhm_impl_pmcs, 17); pfm_regmask_set(&nhm_impl_pmcs, 18); pfm_regmask_set(&nhm_impl_pmcs, 19); pfm_regmask_set(&nhm_impl_pmds, 0); pfm_regmask_set(&nhm_impl_pmds, 1); pfm_regmask_set(&nhm_impl_pmds, 2); pfm_regmask_set(&nhm_impl_pmds, 3); pfm_regmask_set(&nhm_impl_pmds, 16); pfm_regmask_set(&nhm_impl_pmds, 17); pfm_regmask_set(&nhm_impl_pmds, 18); /* lbr */ pfm_regmask_set(&nhm_impl_pmcs, 30); for(i=31; i < 64; i++) pfm_regmask_set(&nhm_impl_pmds, i); switch(cpu_model) { case 46: num_pe = PME_COREI7_EVENT_COUNT; num_unc_pe = 0; pe = corei7_pe; unc_pe = NULL; pme_cycles = PME_COREI7_UNHALTED_CORE_CYCLES; pme_instr = PME_COREI7_INSTRUCTIONS_RETIRED; num_unc_cnt = 0; fixup_mem_uncore_retired(); supp = &intel_nhm_support; break; case 26: /* Nehalem */ case 30: /* Lynnfield */ num_pe = PME_COREI7_EVENT_COUNT; num_unc_pe = PME_COREI7_UNC_EVENT_COUNT; pe = corei7_pe; unc_pe = corei7_unc_pe; pme_cycles = PME_COREI7_UNHALTED_CORE_CYCLES; pme_instr = PME_COREI7_INSTRUCTIONS_RETIRED; setup_nhm_impl_unc_regs(); num_unc_cnt = 9; /* one fixed + 8 generic */ supp = &intel_nhm_support; break; case 37: /* Westmere */ case 44: num_pe = PME_WSM_EVENT_COUNT; num_unc_pe = PME_WSM_UNC_EVENT_COUNT; pe = wsm_pe; unc_pe = intel_wsm_unc_pe; pme_cycles = PME_WSM_UNHALTED_CORE_CYCLES; pme_instr = PME_WSM_INSTRUCTIONS_RETIRED; setup_nhm_impl_unc_regs(); num_unc_cnt = 9; /* one fixed + 8 generic */ /* OFFCORE_RESPONSE_1 */ pfm_regmask_set(&nhm_impl_pmcs, 31); supp = &intel_wsm_support; break; default: return PFMLIB_ERR_NOTSUPP; } supp->pme_count = num_pe + num_unc_pe; supp->num_cnt = NHM_NUM_GEN_COUNTERS + NHM_NUM_FIXED_COUNTERS + num_unc_cnt; /* * propagate uncore registers to impl bitmaps */ pfm_regmask_or(&nhm_impl_pmds, &nhm_impl_pmds, &nhm_impl_unc_pmds); pfm_regmask_or(&nhm_impl_pmcs, &nhm_impl_pmcs, &nhm_impl_unc_pmcs); /* * compute number of registers available * not all CPUs may have uncore */ pfm_regmask_weight(&nhm_impl_pmds, &supp->pmd_count); pfm_regmask_weight(&nhm_impl_pmcs, &supp->pmc_count); return PFMLIB_SUCCESS; } static int pfm_nhm_is_fixed(pfmlib_event_t *e, unsigned int f) { pme_nhm_entry_t *ne; unsigned int fl, flc, i; unsigned int mask = 0; ne = get_nhm_entry(e->event); fl = ne->pme_flags; /* * first pass: check if event as a whole supports fixed counters */ switch(f) { case 0: mask = PFMLIB_NHM_FIXED0; break; case 1: mask = PFMLIB_NHM_FIXED1; break; case 2: mask = PFMLIB_NHM_FIXED2_ONLY; break; default: return 0; } if (fl & mask) return 1; /* * second pass: check if unit mask supports fixed counter * * reject if mask not found OR if not all unit masks have * same fixed counter mask */ flc = 0; for(i=0; i < e->num_masks; i++) { int midx = pfm_nhm_midx2uidx(e->event, e->unit_masks[i]); fl = ne->pme_umasks[midx].pme_uflags; if (fl & mask) flc++; } return flc > 0 && flc == e->num_masks ? 1 : 0; } /* * Allow combination of events when cnt_mask > 0 AND unit mask codes do * not overlap (otherwise, we do not know what is actually measured) */ static int pfm_nhm_check_cmask(pfmlib_event_t *e, pme_nhm_entry_t *ne, pfmlib_nhm_counter_t *cntr) { unsigned int ref, ucode; int i, j; if (!cntr) return -1; if (cntr->cnt_mask == 0) return -1; for(i=0; i < e->num_masks; i++) { int midx = pfm_nhm_midx2uidx(e->event, e->unit_masks[i]); ref = ne->pme_umasks[midx].pme_ucode; for(j=i+1; j < e->num_masks; j++) { midx = pfm_nhm_midx2uidx(e->event, e->unit_masks[j]); ucode = ne->pme_umasks[midx].pme_ucode; if (ref & ucode) return -1; } } return 0; } /* * IMPORTANT: the interface guarantees that pfp_pmds[] elements are returned in the order the events * were submitted. */ static int pfm_nhm_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_nhm_input_param_t *param, pfmlib_output_param_t *outp) { #define HAS_OPTIONS(x) (cntrs && (cntrs[x].flags || cntrs[x].cnt_mask)) #define is_fixed_pmc(a) (a == 16 || a == 17 || a == 18) #define is_uncore(a) (a > 19) pme_nhm_entry_t *ne; pfmlib_nhm_counter_t *cntrs; pfm_nhm_sel_reg_t reg; pfmlib_event_t *e; pfmlib_reg_t *pc, *pd; pfmlib_regmask_t *r_pmcs; uint64_t val, unc_global_ctrl; uint64_t pebs_mask, ld_mask; unsigned long long fixed_ctr; unsigned int plm; unsigned int npc, npmc0, npmc01, nf2, nuf; unsigned int i, n, k, j, umask, use_pebs = 0; unsigned int assign_pc[PMU_NHM_NUM_COUNTERS]; unsigned int next_gen, last_gen, u_flags; unsigned int next_unc_gen, last_unc_gen, lat; unsigned int offcore_rsp0_value = 0; unsigned int offcore_rsp1_value = 0; npc = npmc01 = npmc0 = nf2 = nuf = 0; unc_global_ctrl = 0; e = inp->pfp_events; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; n = inp->pfp_event_count; r_pmcs = &inp->pfp_unavail_pmcs; cntrs = param ? param->pfp_nhm_counters : NULL; pebs_mask = ld_mask = 0; use_pebs = param ? param->pfp_nhm_pebs.pebs_used : 0; lat = param ? param->pfp_nhm_pebs.ld_lat_thres : 0; if (n > PMU_NHM_NUM_COUNTERS) return PFMLIB_ERR_TOOMANY; /* * error checking */ for(i=0; i < n; i++) { /* * only supports two priv levels for perf counters */ if (e[i].plm & (PFM_PLM1|PFM_PLM2)) return PFMLIB_ERR_INVAL; ne = get_nhm_entry(e[i].event); /* check for erratum AAJ80 */ if (aaj80 && (ne->pme_code & 0xff) == 0xc5) { DPRINT("MISPREDICTED_BRANCH_RETIRED broken on this Nehalem processor, see eeratum AAJ80\n"); return PFMLIB_ERR_NOTSUPP; } /* * check for valid flags */ if (e[i].flags & ~PFMLIB_NHM_ALL_FLAGS) return PFMLIB_ERR_INVAL; if (ne->pme_flags & PFMLIB_NHM_UMASK_NCOMBO && e[i].num_masks > 1 && pfm_nhm_check_cmask(e, ne, cntrs ? cntrs+i : NULL)) { DPRINT("events does not support unit mask combination\n"); return PFMLIB_ERR_NOASSIGN; } /* * check event-level single register constraint for uncore fixed */ if (ne->pme_flags & PFMLIB_NHM_UNC_FIXED) { if (++nuf > 1) { DPRINT("two events compete for a UNCORE_FIXED_CTR0\n"); return PFMLIB_ERR_NOASSIGN; } if (HAS_OPTIONS(i)) { DPRINT("uncore fixed counter does not support options\n"); return PFMLIB_ERR_NOASSIGN; } } if (ne->pme_flags & PFMLIB_NHM_PMC0) { if (++npmc0 > 1) { DPRINT("two events compete for a PMC0\n"); return PFMLIB_ERR_NOASSIGN; } } /* * check event-level single register constraint (PMC0/1 only) * fail if more than two events requested for the same counter pair */ if (ne->pme_flags & PFMLIB_NHM_PMC01) { if (++npmc01 > 2) { DPRINT("two events compete for a PMC0\n"); return PFMLIB_ERR_NOASSIGN; } } /* * UNHALTED_REFERENCE_CYCLES (CPU_CLK_UNHALTED:BUS) * can only be measured on FIXED_CTR2 */ if (ne->pme_flags & PFMLIB_NHM_FIXED2_ONLY) { if (++nf2 > 1) { DPRINT("two events compete for FIXED_CTR2\n"); return PFMLIB_ERR_NOASSIGN; } if (cntrs && ((cntrs[i].flags & (PFM_NHM_SEL_INV|PFM_NHM_SEL_EDGE)) || cntrs[i].cnt_mask)) { DPRINT("UNHALTED_REFERENCE_CYCLES only accepts anythr filter\n"); return PFMLIB_ERR_NOASSIGN; } } /* * OFFCORE_RSP0 is shared, unit masks for all offcore_response events * must be identical */ umask = 0; for(j=0; j < e[i].num_masks; j++) { int midx = pfm_nhm_midx2uidx(e[i].event, e[i].unit_masks[j]); umask |= ne->pme_umasks[midx].pme_ucode; } if (ne->pme_flags & PFMLIB_NHM_OFFCORE_RSP0) { if (offcore_rsp0_value && offcore_rsp0_value != umask) { DPRINT("all OFFCORE_RSP0 events must have the same unit mask\n"); return PFMLIB_ERR_NOASSIGN; } if (pfm_regmask_isset(r_pmcs, 19)) { DPRINT("OFFCORE_RSP0 register not available\n"); return PFMLIB_ERR_NOASSIGN; } if (!((umask & 0xff) && (umask & 0xff00))) { DPRINT("OFFCORE_RSP0 must have at least one request and response unit mask set\n"); return PFMLIB_ERR_INVAL; } /* lock-in offcore_value */ offcore_rsp0_value = umask; } if (ne->pme_flags & PFMLIB_NHM_OFFCORE_RSP1) { if (offcore_rsp1_value && offcore_rsp1_value != umask) { DPRINT("all OFFCORE_RSP1 events must have the same unit mask\n"); return PFMLIB_ERR_NOASSIGN; } if (pfm_regmask_isset(r_pmcs, 31)) { DPRINT("OFFCORE_RSP1 register not available\n"); return PFMLIB_ERR_NOASSIGN; } if (!((umask & 0xff) && (umask & 0xff00))) { DPRINT("OFFCORE_RSP1 must have at least one request and response unit mask set\n"); return PFMLIB_ERR_INVAL; } /* lock-in offcore_value */ offcore_rsp1_value = umask; } /* * enforce PLM0|PLM3 for uncore events given they have no * priv level filter. This is to ensure users understand what * they are doing */ if (ne->pme_flags & (PFMLIB_NHM_UNC|PFMLIB_NHM_UNC_FIXED)) { if (inp->pfp_dfl_plm != (PFM_PLM0|PFM_PLM3) && e[i].plm != (PFM_PLM0|PFM_PLM3)) { DPRINT("uncore events must have PLM0|PLM3\n"); return PFMLIB_ERR_NOASSIGN; } } } /* * initilize to empty */ for(i=0; i < PMU_NHM_NUM_COUNTERS; i++) assign_pc[i] = -1; next_gen = 0; /* first generic counter */ last_gen = 3; /* last generic counter */ /* * strongest constraint: only uncore_fixed_ctr0 or PMC0 only */ if (nuf || npmc0) { for(i=0; i < n; i++) { ne = get_nhm_entry(e[i].event); if (ne->pme_flags & PFMLIB_NHM_PMC0) { if (pfm_regmask_isset(r_pmcs, 0)) return PFMLIB_ERR_NOASSIGN; assign_pc[i] = 0; next_gen = 1; } if (ne->pme_flags & PFMLIB_NHM_UNC_FIXED) { if (pfm_regmask_isset(r_pmcs, 20)) return PFMLIB_ERR_NOASSIGN; assign_pc[i] = 20; } } } /* * 2nd strongest constraint first: works only on PMC0 or PMC1 * On Nehalem, this constraint applies at the event-level * (not unit mask level, fortunately) * * PEBS works on all 4 generic counters * * Because of sanity check above, we know we can find * only up to 2 events with this constraint */ if (npmc01) { for(i=0; i < n; i++) { ne = get_nhm_entry(e[i].event); if (ne->pme_flags & PFMLIB_NHM_PMC01) { while (next_gen < 2 && pfm_regmask_isset(r_pmcs, next_gen)) next_gen++; if (next_gen == 2) return PFMLIB_ERR_NOASSIGN; assign_pc[i] = next_gen++; } } } /* * next constraint: fixed counters * * We abuse the mapping here for assign_pc to make it easier * to provide the correct values for pd[]. * We use: * - 16 : fixed counter 0 (pmc16, pmd16) * - 17 : fixed counter 1 (pmc16, pmd17) * - 18 : fixed counter 2 (pmc16, pmd18) */ fixed_ctr = pfm_regmask_isset(r_pmcs, 16) ? 0 : 0x7; if (fixed_ctr) { for(i=0; i < n; i++) { /* * Nehalem fixed counters (as for architected perfmon v3) * does support anythr filter */ if (HAS_OPTIONS(i)) { if (use_pebs && pfm_nhm_is_pebs(e+i)) continue; if (cntrs[i].flags != PFM_NHM_SEL_ANYTHR) continue; } if ((fixed_ctr & 0x1) && pfm_nhm_is_fixed(e+i, 0)) { assign_pc[i] = 16; fixed_ctr &= ~1; } if ((fixed_ctr & 0x2) && pfm_nhm_is_fixed(e+i, 1)) { assign_pc[i] = 17; fixed_ctr &= ~2; } if ((fixed_ctr & 0x4) && pfm_nhm_is_fixed(e+i, 2)) { assign_pc[i] = 18; fixed_ctr &= ~4; } } } /* * uncore events on any of the 8 counters */ next_unc_gen = 21; /* first generic uncore counter config */ last_unc_gen = 28; /* last generic uncore counter config */ for(i=0; i < n; i++) { ne = get_nhm_entry(e[i].event); if (ne->pme_flags & PFMLIB_NHM_UNC) { for(; next_unc_gen <= last_unc_gen; next_unc_gen++) { if (!pfm_regmask_isset(r_pmcs, next_unc_gen)) break; } if (next_unc_gen <= last_unc_gen) assign_pc[i] = next_unc_gen++; else { DPRINT("cannot assign generic uncore event\n"); return PFMLIB_ERR_NOASSIGN; } } } /* * assign what is left of the generic events */ for(i=0; i < n; i++) { if (assign_pc[i] == -1) { for(; next_gen <= last_gen; next_gen++) { DPRINT("i=%d next_gen=%d last=%d isset=%d\n", i, next_gen, last_gen, pfm_regmask_isset(r_pmcs, next_gen)); if (!pfm_regmask_isset(r_pmcs, next_gen)) break; } if (next_gen <= last_gen) { assign_pc[i] = next_gen++; } else { DPRINT("cannot assign generic event\n"); return PFMLIB_ERR_NOASSIGN; } } } /* * setup core fixed counters */ reg.val = 0; for (i=0; i < n ; i++ ) { if (!is_fixed_pmc(assign_pc[i])) continue; val = 0; /* if plm is 0, then assume not specified per-event and use default */ plm = e[i].plm ? e[i].plm : inp->pfp_dfl_plm; if (plm & PFM_PLM0) val |= 1ULL; if (plm & PFM_PLM3) val |= 2ULL; if (cntrs && cntrs[i].flags & PFM_NHM_SEL_ANYTHR) val |= 4ULL; val |= 1ULL << 3; /* force APIC int (kernel may force it anyway) */ reg.val |= val << ((assign_pc[i]-16)<<2); } if (reg.val) { pc[npc].reg_num = 16; pc[npc].reg_value = reg.val; pc[npc].reg_addr = 0x38D; pc[npc].reg_alt_addr = 0x38D; __pfm_vbprintf("[FIXED_CTRL(pmc%u)=0x%"PRIx64" pmi0=1 en0=0x%"PRIx64" any0=%d pmi1=1 en1=0x%"PRIx64" any1=%d pmi2=1 en2=0x%"PRIx64" any2=%d] ", pc[npc].reg_num, reg.val, reg.val & 0x3ULL, !!(reg.val & 0x4ULL), (reg.val>>4) & 0x3ULL, !!((reg.val>>4) & 0x4ULL), (reg.val>>8) & 0x3ULL, !!((reg.val>>8) & 0x4ULL)); if ((fixed_ctr & 0x1) == 0) __pfm_vbprintf("INSTRUCTIONS_RETIRED "); if ((fixed_ctr & 0x2) == 0) __pfm_vbprintf("UNHALTED_CORE_CYCLES "); if ((fixed_ctr & 0x4) == 0) __pfm_vbprintf("UNHALTED_REFERENCE_CYCLES "); __pfm_vbprintf("\n"); npc++; if ((fixed_ctr & 0x1) == 0) __pfm_vbprintf("[FIXED_CTR0(pmd16)]\n"); if ((fixed_ctr & 0x2) == 0) __pfm_vbprintf("[FIXED_CTR1(pmd17)]\n"); if ((fixed_ctr & 0x4) == 0) __pfm_vbprintf("[FIXED_CTR2(pmd18)]\n"); } /* * setup core counter config */ for (i=0; i < n ; i++ ) { /* skip fixed counters */ if (is_fixed_pmc(assign_pc[i]) || is_uncore(assign_pc[i])) continue; reg.val = 0; /* assume reserved bits are zeroed */ /* if plm is 0, then assume not specified per-event and use default */ plm = e[i].plm ? e[i].plm : inp->pfp_dfl_plm; ne = get_nhm_entry(e[i].event); val = ne->pme_code; reg.sel_event = val & 0xff; umask = (val >> 8) & 0xff; u_flags = 0; /* * for OFFCORE_RSP, the unit masks are all in the * dedicated OFFCORE_RSP MSRs and event unit mask must be * 0x1 (extracted from pme_code) */ if (!(ne->pme_flags & (PFMLIB_NHM_OFFCORE_RSP0|PFMLIB_NHM_OFFCORE_RSP1))) for(k=0; k < e[i].num_masks; k++) { int midx = pfm_nhm_midx2uidx(e[i].event, e[i].unit_masks[k]); umask |= ne->pme_umasks[midx].pme_ucode; u_flags |= ne->pme_umasks[midx].pme_uflags; } val |= umask << 8; reg.sel_umask = umask; reg.sel_usr = plm & PFM_PLM3 ? 1 : 0; reg.sel_os = plm & PFM_PLM0 ? 1 : 0; reg.sel_en = 1; /* force enable bit to 1 */ reg.sel_int = 1; /* force APIC int to 1 */ reg.sel_cnt_mask = val >>24; reg.sel_inv = val >> 23; reg.sel_anythr = val >> 21; reg.sel_edge = val >> 18; if (cntrs) { /* * occupancy reset flag is for uncore counters only */ if (cntrs[i].flags & PFM_NHM_SEL_OCC_RST) return PFMLIB_ERR_INVAL; if (!reg.sel_cnt_mask) { /* * counter mask is 8-bit wide, do not silently * wrap-around */ if (cntrs[i].cnt_mask > 255) return PFMLIB_ERR_INVAL; reg.sel_cnt_mask = cntrs[i].cnt_mask; } if (!reg.sel_edge) reg.sel_edge = cntrs[i].flags & PFM_NHM_SEL_EDGE ? 1 : 0; if (!reg.sel_inv) reg.sel_inv = cntrs[i].flags & PFM_NHM_SEL_INV ? 1 : 0; if (!reg.sel_anythr) reg.sel_anythr = cntrs[i].flags & PFM_NHM_SEL_ANYTHR ? 1 : 0; } if (u_flags || (ne->pme_flags & PFMLIB_NHM_PEBS)) pebs_mask |= 1ULL << assign_pc[i]; /* * check for MEM_INST_RETIRED:LATENCY_ABOVE_THRESHOLD_0 to enable load latency filtering * when PEBS is used. There is only one threshold possible, yet mutliple counters may be * programmed with this event/umask. That means they all share the same threshold. */ if (reg.sel_event == 0xb && (umask & 0x10)) ld_mask |= 1ULL << assign_pc[i]; pc[npc].reg_num = assign_pc[i]; pc[npc].reg_value = reg.val; pc[npc].reg_addr = NHM_SEL_BASE+assign_pc[i]; pc[npc].reg_alt_addr= NHM_SEL_BASE+assign_pc[i]; __pfm_vbprintf("[PERFEVTSEL%u(pmc%u)=0x%"PRIx64" event_sel=0x%x umask=0x%x os=%d usr=%d anythr=%d en=%d int=%d inv=%d edge=%d cnt_mask=%d] %s\n", pc[npc].reg_num, pc[npc].reg_num, reg.val, reg.sel_event, reg.sel_umask, reg.sel_os, reg.sel_usr, reg.sel_anythr, reg.sel_en, reg.sel_int, reg.sel_inv, reg.sel_edge, reg.sel_cnt_mask, ne->pme_name); __pfm_vbprintf("[PMC%u(pmd%u)]\n", pc[npc].reg_num, pc[npc].reg_num); npc++; } /* * setup uncore fixed counter config */ if (nuf) { pc[npc].reg_num = 20; pc[npc].reg_value = 0x5ULL; /* ena=1, PMI=dtermined by kernel */ pc[npc].reg_addr = 0x395; pc[npc].reg_alt_addr = 0x395; __pfm_vbprintf("[UNC_FIXED_CTRL(pmc20)=0x%"PRIx64" pmi=1 ena=1] UNC_CLK_UNHALTED\n", pc[npc].reg_value); __pfm_vbprintf("[UNC_FIXED_CTR0(pmd20)]\n"); unc_global_ctrl |= 1ULL<< 32; npc++; } /* * setup uncore counter config */ for (i=0; i < n ; i++ ) { /* skip core counters, uncore fixed */ if (!is_uncore(assign_pc[i]) || assign_pc[i] == 20) continue; reg.val = 0; /* assume reserved bits are zerooed */ ne = get_nhm_entry(e[i].event); val = ne->pme_code; reg.usel_event = val & 0xff; umask = (val >> 8) & 0xff; for(k=0; k < e[i].num_masks; k++) { int midx = pfm_nhm_midx2uidx(e[i].event, e[i].unit_masks[k]); umask |= ne->pme_umasks[midx].pme_ucode; } val |= umask << 8; reg.usel_umask = umask; reg.usel_en = 1; /* force enable bit to 1 */ reg.usel_int = 1; /* force APIC int to 1 */ /* * allow hardcoded filters in event table */ reg.usel_cnt_mask = val >>24; reg.usel_inv = val >> 23; reg.usel_edge = val >> 18; reg.usel_occ = val >> 17; if (cntrs) { /* * anythread if for core counters only */ if (cntrs[i].flags & PFM_NHM_SEL_ANYTHR) return PFMLIB_ERR_INVAL; if (!reg.usel_cnt_mask) { /* * counter mask is 8-bit wide, do not silently * wrap-around */ if (cntrs[i].cnt_mask > 255) return PFMLIB_ERR_INVAL; reg.usel_cnt_mask = cntrs[i].cnt_mask; } if (!reg.usel_edge) reg.usel_edge = cntrs[i].flags & PFM_NHM_SEL_EDGE ? 1 : 0; if (!reg.usel_inv) reg.usel_inv = cntrs[i].flags & PFM_NHM_SEL_INV ? 1 : 0; if (!reg.usel_occ) reg.usel_occ = cntrs[i].flags & PFM_NHM_SEL_OCC_RST ? 1 : 0; } unc_global_ctrl |= 1ULL<< (assign_pc[i] - 21); pc[npc].reg_num = assign_pc[i]; pc[npc].reg_value = reg.val; pc[npc].reg_addr = UNC_NHM_SEL_BASE+assign_pc[i] - 21; pc[npc].reg_alt_addr= UNC_NHM_SEL_BASE+assign_pc[i] - 21; __pfm_vbprintf("[UNC_PERFEVTSEL%u(pmc%u)=0x%"PRIx64" event=0x%x umask=0x%x en=%d int=%d inv=%d edge=%d occ=%d cnt_msk=%d] %s\n", pc[npc].reg_num - 21, pc[npc].reg_num, reg.val, reg.usel_event, reg.usel_umask, reg.usel_en, reg.usel_int, reg.usel_inv, reg.usel_edge, reg.usel_occ, reg.usel_cnt_mask, ne->pme_name); __pfm_vbprintf("[UNC_PMC%u(pmd%u)]\n", pc[npc].reg_num - 21, pc[npc].reg_num); npc++; } /* * setup pmds: must be in the same order as the events */ for (i=0; i < n ; i++) { switch (assign_pc[i]) { case 0 ... 4: pd[i].reg_num = assign_pc[i]; pd[i].reg_addr = NHM_CTR_BASE+assign_pc[i]; /* index to use with RDPMC */ pd[i].reg_alt_addr = assign_pc[i]; break; case 16 ... 18: /* setup pd array */ pd[i].reg_num = assign_pc[i]; pd[i].reg_addr = NHM_FIXED_CTR_BASE+assign_pc[i]-16; pd[i].reg_alt_addr = 0x40000000+assign_pc[i]-16; break; case 20: pd[i].reg_num = 20; pd[i].reg_addr = UNC_NHM_FIXED_CTR_BASE; pd[i].reg_alt_addr = UNC_NHM_FIXED_CTR_BASE; break; case 21 ... 28: pd[i].reg_num = assign_pc[i]; pd[i].reg_addr = UNC_NHM_CTR_BASE + assign_pc[i] - 21; pd[i].reg_alt_addr = UNC_NHM_CTR_BASE + assign_pc[i] - 21; break; } } outp->pfp_pmd_count = i; /* * setup PEBS_ENABLE */ if (use_pebs && pebs_mask) { if (!lat) ld_mask = 0; /* * check that PEBS_ENABLE is available */ if (pfm_regmask_isset(r_pmcs, 17)) return PFMLIB_ERR_NOASSIGN; pc[npc].reg_num = 17; pc[npc].reg_value = pebs_mask | (ld_mask <<32); pc[npc].reg_addr = 0x3f1; /* IA32_PEBS_ENABLE */ pc[npc].reg_alt_addr = 0x3f1; /* IA32_PEBS_ENABLE */ __pfm_vbprintf("[PEBS_ENABLE(pmc%u)=0x%"PRIx64" ena0=%d ena1=%d ena2=%d ena3=%d ll0=%d ll1=%d ll2=%d ll3=%d]\n", pc[npc].reg_num, pc[npc].reg_value, pc[npc].reg_value & 0x1, (pc[npc].reg_value >> 1) & 0x1, (pc[npc].reg_value >> 2) & 0x1, (pc[npc].reg_value >> 3) & 0x1, (pc[npc].reg_value >> 32) & 0x1, (pc[npc].reg_value >> 33) & 0x1, (pc[npc].reg_value >> 34) & 0x1, (pc[npc].reg_value >> 35) & 0x1); npc++; if (ld_mask) { if (lat < 3 || lat > 0xffff) { DPRINT("invalid load latency threshold %u (must be in [3:0xffff])\n", lat); return PFMLIB_ERR_INVAL; } if (pfm_regmask_isset(r_pmcs, 18)) return PFMLIB_ERR_NOASSIGN; pc[npc].reg_num = 18; pc[npc].reg_value = lat; pc[npc].reg_addr = 0x3f1; /* IA32_PEBS_ENABLE */ pc[npc].reg_alt_addr = 0x3f1; /* IA32_PEBS_ENABLE */ __pfm_vbprintf("[LOAD_LATENCY_THRESHOLD(pmc%u)=0x%"PRIx64"]\n", pc[npc].reg_num, pc[npc].reg_value); npc++; } } /* * setup OFFCORE_RSP0 */ if (offcore_rsp0_value) { pc[npc].reg_num = 19; pc[npc].reg_value = offcore_rsp0_value; pc[npc].reg_addr = 0x1a6; pc[npc].reg_alt_addr = 0x1a6; __pfm_vbprintf("[OFFCORE_RSP0(pmc%u)=0x%"PRIx64"]\n", pc[npc].reg_num, pc[npc].reg_value); npc++; } /* * setup OFFCORE_RSP1 */ if (offcore_rsp1_value) { pc[npc].reg_num = 31; pc[npc].reg_value = offcore_rsp1_value; pc[npc].reg_addr = 0x1a7; pc[npc].reg_alt_addr = 0x1a7; __pfm_vbprintf("[OFFCORE_RSP1(pmc%u)=0x%"PRIx64"]\n", pc[npc].reg_num, pc[npc].reg_value); npc++; } outp->pfp_pmc_count = npc; return PFMLIB_SUCCESS; } static int pfm_nhm_dispatch_lbr(pfmlib_input_param_t *inp, pfmlib_nhm_input_param_t *param, pfmlib_output_param_t *outp) { static int lbr_plm_map[4]={ 0x3, /* PLM0=0 PLM3=0 neq0=1 eq0=1 */ 0x1, /* PLM0=0 PLM3=1 neq0=0 eq0=1 */ 0x2, /* PLM0=1 PLM3=0 neq0=1 eq0=0 */ 0x0 /* PLM0=1 PLM3=1 neq0=0 eq0=0 */ }; pfm_nhm_sel_reg_t reg; unsigned int filter, i, c; unsigned int plm; /* * check LBR_SELECT is available */ if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 30)) return PFMLIB_ERR_NOASSIGN; reg.val = 0; /* capture everything */ plm = param->pfp_nhm_lbr.lbr_plm; if (!plm) plm = inp->pfp_dfl_plm; /* * LBR does not distinguish PLM1, PLM2 from PLM3 */ i = plm & PFM_PLM0 ? 0x2 : 0; i |= plm & PFM_PLM3 ? 0x1 : 0; if (lbr_plm_map[i] & 0x1) reg.lbr_select.cpl_eq0 = 1; if (lbr_plm_map[i] & 0x2) reg.lbr_select.cpl_neq0 = 1; filter = param->pfp_nhm_lbr.lbr_filter; if (filter & PFM_NHM_LBR_JCC) reg.lbr_select.jcc = 1; if (filter & PFM_NHM_LBR_NEAR_REL_CALL) reg.lbr_select.near_rel_call = 1; if (filter & PFM_NHM_LBR_NEAR_IND_CALL) reg.lbr_select.near_ind_call = 1; if (filter & PFM_NHM_LBR_NEAR_RET) reg.lbr_select.near_ret = 1; if (filter & PFM_NHM_LBR_NEAR_IND_JMP) reg.lbr_select.near_ind_jmp = 1; if (filter & PFM_NHM_LBR_NEAR_REL_JMP) reg.lbr_select.near_rel_jmp = 1; if (filter & PFM_NHM_LBR_FAR_BRANCH) reg.lbr_select.far_branch = 1; __pfm_vbprintf("[LBR_SELECT(PMC30)=0x%"PRIx64" eq0=%d neq0=%d jcc=%d rel=%d ind=%d ret=%d ind_jmp=%d rel_jmp=%d far=%d ]\n", reg.val, reg.lbr_select.cpl_eq0, reg.lbr_select.cpl_neq0, reg.lbr_select.jcc, reg.lbr_select.near_rel_call, reg.lbr_select.near_ind_call, reg.lbr_select.near_ret, reg.lbr_select.near_ind_jmp, reg.lbr_select.near_rel_jmp, reg.lbr_select.far_branch); __pfm_vbprintf("[LBR_TOS(PMD31)]\n"); __pfm_vbprintf("[LBR_FROM-LBR_TO(PMD32..PMD63)]\n"); c = outp->pfp_pmc_count; outp->pfp_pmcs[c].reg_num = 30; outp->pfp_pmcs[c].reg_value = reg.val; outp->pfp_pmcs[c].reg_addr = 0x1c8; outp->pfp_pmcs[c].reg_alt_addr = 0x1c8; c++; outp->pfp_pmc_count = c; c = outp->pfp_pmd_count; outp->pfp_pmds[c].reg_num = 31; outp->pfp_pmds[c].reg_value = 0; outp->pfp_pmds[c].reg_addr = 0x1c9; outp->pfp_pmds[c].reg_alt_addr = 0x1c9; c++; for(i=0; i < 32; i++, c++) { outp->pfp_pmds[c].reg_num = 32 + i; outp->pfp_pmds[c].reg_value = 0; outp->pfp_pmds[c].reg_addr = (i>>1) + ((i & 0x1) ? 0x6c0 : 0x680); outp->pfp_pmds[c].reg_alt_addr = (i>>1) + ((i & 0x1) ? 0x6c0 : 0x680); } outp->pfp_pmd_count = c; return PFMLIB_SUCCESS; } static int pfm_nhm_dispatch_events(pfmlib_input_param_t *inp, void *model_in, pfmlib_output_param_t *outp, void *model_out) { pfmlib_nhm_input_param_t *mod_in = (pfmlib_nhm_input_param_t *)model_in; int ret; if (inp->pfp_dfl_plm & (PFM_PLM1|PFM_PLM2)) { DPRINT("invalid plm=%x\n", inp->pfp_dfl_plm); return PFMLIB_ERR_INVAL; } ret = pfm_nhm_dispatch_counters(inp, mod_in, outp); if (ret != PFMLIB_SUCCESS) return ret; if (mod_in && mod_in->pfp_nhm_lbr.lbr_used) ret = pfm_nhm_dispatch_lbr(inp, mod_in, outp); return ret; } static int pfm_nhm_get_event_code(unsigned int i, unsigned int cnt, int *code) { pfmlib_regmask_t cnts; pfm_get_impl_counters(&cnts); if (cnt != PFMLIB_CNT_FIRST && (cnt > MAX_COUNTERS || !pfm_regmask_isset(&cnts, cnt))) return PFMLIB_ERR_INVAL; *code = get_nhm_entry(i)->pme_code; return PFMLIB_SUCCESS; } static void pfm_nhm_get_event_counters(unsigned int j, pfmlib_regmask_t *counters) { pme_nhm_entry_t *ne; unsigned int i; memset(counters, 0, sizeof(*counters)); ne = get_nhm_entry(j); if (ne->pme_flags & PFMLIB_NHM_UNC_FIXED) { pfm_regmask_set(counters, 20); return; } if (ne->pme_flags & PFMLIB_NHM_UNC) { pfm_regmask_set(counters, 20); pfm_regmask_set(counters, 21); pfm_regmask_set(counters, 22); pfm_regmask_set(counters, 23); pfm_regmask_set(counters, 24); pfm_regmask_set(counters, 25); pfm_regmask_set(counters, 26); pfm_regmask_set(counters, 27); return; } /* * fixed counter events have no unit mask */ if (ne->pme_flags & PFMLIB_NHM_FIXED0) pfm_regmask_set(counters, 16); if (ne->pme_flags & PFMLIB_NHM_FIXED1) pfm_regmask_set(counters, 17); if (ne->pme_flags & PFMLIB_NHM_FIXED2_ONLY) pfm_regmask_set(counters, 18); /* * extract from unit mask level */ for (i=0; i < ne->pme_numasks; i++) { if (ne->pme_umasks[i].pme_uflags & PFMLIB_NHM_FIXED0) pfm_regmask_set(counters, 16); if (ne->pme_umasks[i].pme_uflags & PFMLIB_NHM_FIXED1) pfm_regmask_set(counters, 17); if (ne->pme_umasks[i].pme_uflags & PFMLIB_NHM_FIXED2_ONLY) pfm_regmask_set(counters, 18); } /* * event on FIXED_CTR2 is exclusive CPU_CLK_UNHALTED:REF * PMC0|PMC1 only on 0,1, constraint at event-level */ if (!pfm_regmask_isset(counters, 18)) { pfm_regmask_set(counters, 0); if (!(ne->pme_flags & PFMLIB_NHM_PMC0)) pfm_regmask_set(counters, 1); if (!(ne->pme_flags & (PFMLIB_NHM_PMC01|PFMLIB_NHM_PMC0))) { pfm_regmask_set(counters, 2); pfm_regmask_set(counters, 3); } } } static void pfm_nhm_get_impl_pmcs(pfmlib_regmask_t *impl_pmcs) { *impl_pmcs = nhm_impl_pmcs; } static void pfm_nhm_get_impl_pmds(pfmlib_regmask_t *impl_pmds) { *impl_pmds = nhm_impl_pmds; } static void pfm_nhm_get_impl_counters(pfmlib_regmask_t *impl_counters) { /* core generic */ pfm_regmask_set(impl_counters, 0); pfm_regmask_set(impl_counters, 1); pfm_regmask_set(impl_counters, 2); pfm_regmask_set(impl_counters, 3); /* core fixed */ pfm_regmask_set(impl_counters, 16); pfm_regmask_set(impl_counters, 17); pfm_regmask_set(impl_counters, 18); /* uncore pmd registers all counters */ pfm_regmask_or(impl_counters, impl_counters, &nhm_impl_unc_pmds); } /* * Even though, CPUID 0xa returns in eax the actual counter * width, the architecture specifies that writes are limited * to lower 32-bits. As such, only the lower 32-bit have full * degree of freedom. That is the "useable" counter width. */ #define PMU_NHM_COUNTER_WIDTH 32 static void pfm_nhm_get_hw_counter_width(unsigned int *width) { /* * Even though, CPUID 0xa returns in eax the actual counter * width, the architecture specifies that writes are limited * to lower 32-bits. As such, only the lower 31 bits have full * degree of freedom. That is the "useable" counter width. */ *width = PMU_NHM_COUNTER_WIDTH; } static char * pfm_nhm_get_event_name(unsigned int i) { return get_nhm_entry(i)->pme_name; } static int pfm_nhm_get_event_description(unsigned int ev, char **str) { char *s; s = get_nhm_entry(ev)->pme_desc; if (s) { *str = strdup(s); } else { *str = NULL; } return PFMLIB_SUCCESS; } static char * pfm_nhm_get_event_mask_name(unsigned int ev, unsigned int midx) { midx = pfm_nhm_midx2uidx(ev, midx); return get_nhm_entry(ev)->pme_umasks[midx].pme_uname; } static int pfm_nhm_get_event_mask_desc(unsigned int ev, unsigned int midx, char **str) { char *s; midx = pfm_nhm_midx2uidx(ev, midx); s = get_nhm_entry(ev)->pme_umasks[midx].pme_udesc; if (s) { *str = strdup(s); } else { *str = NULL; } return PFMLIB_SUCCESS; } static unsigned int pfm_nhm_get_num_event_masks(unsigned int ev) { int i, num = 0; pme_nhm_entry_t *ne; int model; ne = get_nhm_entry(ev); for (i=0; i < ne->pme_numasks; i++) { model = ne->pme_umasks[i].pme_umodel; if (!model || model == cpu_model) num++; } DPRINT("event %s numasks=%d\n", ne->pme_name, num); return num; } static int pfm_nhm_get_event_mask_code(unsigned int ev, unsigned int midx, unsigned int *code) { midx = pfm_nhm_midx2uidx(ev, midx); *code =get_nhm_entry(ev)->pme_umasks[midx].pme_ucode; return PFMLIB_SUCCESS; } static int pfm_nhm_get_cycle_event(pfmlib_event_t *e) { e->event = pme_cycles; return PFMLIB_SUCCESS; } static int pfm_nhm_get_inst_retired(pfmlib_event_t *e) { e->event = pme_instr;; return PFMLIB_SUCCESS; } /* * the following function implement the model * specific API directly available to user */ /* * Check if event and all provided unit masks support PEBS * * return: * PFMLIB_ERR_INVAL: invalid event e * 1 event supports PEBS * 0 event does not support PEBS * */ int pfm_nhm_is_pebs(pfmlib_event_t *e) { pme_nhm_entry_t *ne; unsigned int i, n=0; if (e == NULL || e->event >= intel_nhm_support.pme_count) return PFMLIB_ERR_INVAL; ne = get_nhm_entry(e->event); if (ne->pme_flags & PFMLIB_NHM_PEBS) return 1; /* * ALL unit mask must support PEBS for this test to return true */ for(i=0; i < e->num_masks; i++) { int midx; /* check for valid unit mask */ if (e->unit_masks[i] >= ne->pme_numasks) return PFMLIB_ERR_INVAL; midx = pfm_nhm_midx2uidx(e->event, e->unit_masks[i]); if (ne->pme_umasks[midx].pme_uflags & PFMLIB_NHM_PEBS) n++; } return n > 0 && n == e->num_masks; } /* * Check if event is uncore * return: * PFMLIB_ERR_INVAL: invalid event e * 1 event is uncore * 0 event is not uncore */ int pfm_nhm_is_uncore(pfmlib_event_t *e) { if (PFMLIB_INITIALIZED() == 0) return 0; if (e == NULL || e->event >= num_pe) return PFMLIB_ERR_INVAL; return !!(get_nhm_entry(e->event)->pme_flags & (PFMLIB_NHM_UNC|PFMLIB_NHM_UNC_FIXED)); } static const char *data_src_encodings[]={ /* 0 */ "unknown L3 cache miss", /* 1 */ "minimal latency core cache hit. Request was satisfied by L1 data cache", /* 2 */ "pending core cache HIT. Outstanding core cache miss to same cacheline address already underway", /* 3 */ "data request satisfied by the L2", /* 4 */ "L3 HIT. Local or remote home request that hit L3 in the uncore with no coherency actions required (snooping)", /* 5 */ "L3 HIT. Local or remote home request that hit L3 and was serviced by another core with a cross core snoop where no modified copy was found (clean)", /* 6 */ "L3 HIT. Local or remote home request that hit L3 and was serviced by another core with a cross core snoop where modified copies were found (HITM)", /* 7 */ "reserved", /* 8 */ "L3 MISS. Local homed request that missed L3 and was serviced by forwarded data following a cross package snoop where no modified copy was found (remote home requests are not counted)", /* 9 */ "reserved", /* 10 */ "L3 MISS. Local homed request that missed L3 and was serviced by local DRAM (go to shared state)", /* 11 */ "L3 MISS. Remote homed request that missed L3 and was serviced by remote DRAM (go to shared state)", /* 12 */ "L3 MISS. Local homed request that missed L3 and was serviced by local DRAM (go to exclusive state)", /* 13 */ "L3 MISS. Remote homed request that missed L3 and was serviced by remote DRAM (go to exclusive state)", /* 14 */ "reserved", /* 15 */ "request to uncacheable memory" }; /* * return data source encoding based on index in val * To be used with PEBS load latency filtering to decode * source of the load miss */ int pfm_nhm_data_src_desc(unsigned int val, char **desc) { if (val > 15 || !desc) return PFMLIB_ERR_INVAL; *desc = strdup(data_src_encodings[val]); if (!*desc) return PFMLIB_ERR_NOMEM; return PFMLIB_SUCCESS; } pfm_pmu_support_t intel_nhm_support={ .pmu_name = "Intel Nehalem", .pmu_type = PFMLIB_INTEL_NHM_PMU, .pme_count = 0,/* patched at runtime */ .pmc_count = 0,/* patched at runtime */ .pmd_count = 0,/* patched at runtime */ .num_cnt = 0,/* patched at runtime */ .get_event_code = pfm_nhm_get_event_code, .get_event_name = pfm_nhm_get_event_name, .get_event_counters = pfm_nhm_get_event_counters, .dispatch_events = pfm_nhm_dispatch_events, .pmu_detect = pfm_nhm_detect, .pmu_init = pfm_nhm_init, .get_impl_pmcs = pfm_nhm_get_impl_pmcs, .get_impl_pmds = pfm_nhm_get_impl_pmds, .get_impl_counters = pfm_nhm_get_impl_counters, .get_hw_counter_width = pfm_nhm_get_hw_counter_width, .get_event_desc = pfm_nhm_get_event_description, .get_num_event_masks = pfm_nhm_get_num_event_masks, .get_event_mask_name = pfm_nhm_get_event_mask_name, .get_event_mask_code = pfm_nhm_get_event_mask_code, .get_event_mask_desc = pfm_nhm_get_event_mask_desc, .get_cycle_event = pfm_nhm_get_cycle_event, .get_inst_retired_event = pfm_nhm_get_inst_retired }; pfm_pmu_support_t intel_wsm_support={ .pmu_name = "Intel Westmere", .pmu_type = PFMLIB_INTEL_WSM_PMU, .pme_count = 0,/* patched at runtime */ .pmc_count = 0,/* patched at runtime */ .pmd_count = 0,/* patched at runtime */ .num_cnt = 0,/* patched at runtime */ .get_event_code = pfm_nhm_get_event_code, .get_event_name = pfm_nhm_get_event_name, .get_event_counters = pfm_nhm_get_event_counters, .dispatch_events = pfm_nhm_dispatch_events, .pmu_detect = pfm_wsm_detect, .pmu_init = pfm_nhm_init, .get_impl_pmcs = pfm_nhm_get_impl_pmcs, .get_impl_pmds = pfm_nhm_get_impl_pmds, .get_impl_counters = pfm_nhm_get_impl_counters, .get_hw_counter_width = pfm_nhm_get_hw_counter_width, .get_event_desc = pfm_nhm_get_event_description, .get_num_event_masks = pfm_nhm_get_num_event_masks, .get_event_mask_name = pfm_nhm_get_event_mask_name, .get_event_mask_code = pfm_nhm_get_event_mask_code, .get_event_mask_desc = pfm_nhm_get_event_mask_desc, .get_cycle_event = pfm_nhm_get_cycle_event, .get_inst_retired_event = pfm_nhm_get_inst_retired }; papi-5.5.1/src/libpfm-3.y/lib/pfmlib_coreduo.c0000644000307100002310000003273713013651450021041 0ustar yarkhangraduate/* * pfmlib_coreduo.c : Intel Core Duo/Solo * * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * * This file implements support for Intel Core Duo/Solor PMU as specified in the * following document: * "IA-32 Intel Architecture Software Developer's Manual - Volume 3B: System * Programming Guide" * * Core Dup/Solo PMU = architectural perfmon v1 + model specific events */ #include #include #include #include #include /* public headers */ #include /* private headers */ #include "pfmlib_priv.h" #include "pfmlib_coreduo_priv.h" #include "coreduo_events.h" /* let's define some handy shortcuts! */ #define sel_event_select perfevtsel.sel_event_select #define sel_unit_mask perfevtsel.sel_unit_mask #define sel_usr perfevtsel.sel_usr #define sel_os perfevtsel.sel_os #define sel_edge perfevtsel.sel_edge #define sel_pc perfevtsel.sel_pc #define sel_int perfevtsel.sel_int #define sel_en perfevtsel.sel_en #define sel_inv perfevtsel.sel_inv #define sel_cnt_mask perfevtsel.sel_cnt_mask /* * Description of the PMC register mappings: * * 0 -> PMC0 -> PERFEVTSEL0 * 1 -> PMC1 -> PERFEVTSEL1 * 16 -> PMC16 -> FIXED_CTR_CTRL * 17 -> PMC17 -> PEBS_ENABLED * * Description of the PMD register mapping: * * 0 -> PMD0 -> PMC0 * 1 -> PMD1 -> PMC1 * 16 -> PMD2 -> FIXED_CTR0 * 17 -> PMD3 -> FIXED_CTR1 * 18 -> PMD4 -> FIXED_CTR2 */ #define COREDUO_SEL_BASE 0x186 #define COREDUO_CTR_BASE 0xc1 #define PFMLIB_COREDUO_ALL_FLAGS \ (PFM_COREDUO_SEL_INV|PFM_COREDUO_SEL_EDGE) static pfmlib_regmask_t coreduo_impl_pmcs, coreduo_impl_pmds; static int highest_counter; static int pfm_coreduo_detect(void) { char buffer[128]; int family, model; int ret; ret = __pfm_getcpuinfo_attr("vendor_id", buffer, sizeof(buffer)); if (ret == -1) return PFMLIB_ERR_NOTSUPP; if (strcmp(buffer, "GenuineIntel")) return PFMLIB_ERR_NOTSUPP; ret = __pfm_getcpuinfo_attr("cpu family", buffer, sizeof(buffer)); if (ret == -1) return PFMLIB_ERR_NOTSUPP; family = atoi(buffer); ret = __pfm_getcpuinfo_attr("model", buffer, sizeof(buffer)); if (ret == -1) return PFMLIB_ERR_NOTSUPP; model = atoi(buffer); return family == 6 && model == 14 ? PFMLIB_SUCCESS : PFMLIB_ERR_NOTSUPP; } static int pfm_coreduo_init(void) { pfm_regmask_set(&coreduo_impl_pmcs, 0); pfm_regmask_set(&coreduo_impl_pmcs, 1); pfm_regmask_set(&coreduo_impl_pmds, 0); pfm_regmask_set(&coreduo_impl_pmds, 1); highest_counter = 1; return PFMLIB_SUCCESS; } /* * IMPORTANT: the interface guarantees that pfp_pmds[] elements are returned in the order the events * were submitted. */ static int pfm_coreduo_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_coreduo_input_param_t *param, pfmlib_output_param_t *outp) { #define HAS_OPTIONS(x) (cntrs && (cntrs[x].flags || cntrs[x].cnt_mask)) pfm_coreduo_counter_t *cntrs; pfm_coreduo_sel_reg_t reg; pfmlib_event_t *e; pfmlib_reg_t *pc, *pd; pfmlib_regmask_t *r_pmcs; uint64_t val; unsigned long plm; unsigned int npc, npmc0, npmc1, nf2; unsigned int i, n, k, ucode; unsigned int assign_pc[PMU_COREDUO_NUM_COUNTERS]; unsigned int next_gen, last_gen; npc = npmc0 = npmc1 = nf2 = 0; e = inp->pfp_events; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; n = inp->pfp_event_count; r_pmcs = &inp->pfp_unavail_pmcs; cntrs = param ? param->pfp_coreduo_counters : NULL; if (n > PMU_COREDUO_NUM_COUNTERS) return PFMLIB_ERR_TOOMANY; /* * initilize to empty */ for(i=0; i < PMU_COREDUO_NUM_COUNTERS; i++) assign_pc[i] = -1; /* * error checking */ for(i=0; i < n; i++) { /* * only supports two priv levels for perf counters */ if (e[i].plm & (PFM_PLM1|PFM_PLM2)) return PFMLIB_ERR_INVAL; /* * check for valid flags */ if (cntrs && cntrs[i].flags & ~PFMLIB_COREDUO_ALL_FLAGS) return PFMLIB_ERR_INVAL; /* * check event-level single register constraint (PMC0, PMC1, FIXED_CTR2) * fail if more than two events requested for the same counter */ if (coreduo_pe[e[i].event].pme_flags & PFMLIB_COREDUO_PMC0) { if (++npmc0 > 1) { DPRINT("two events compete for a PMC0\n"); return PFMLIB_ERR_NOASSIGN; } } /* * check if PMC1 is available and if only one event is dependent on it */ if (coreduo_pe[e[i].event].pme_flags & PFMLIB_COREDUO_PMC1) { if (++npmc1 > 1) { DPRINT("two events compete for a PMC1\n"); return PFMLIB_ERR_NOASSIGN; } } } next_gen = 0; /* first generic counter */ last_gen = 1; /* last generic counter */ /* * strongest constraint first: works only in IA32_PMC0, IA32_PMC1 */ for(i=0; i < n; i++) { if ((coreduo_pe[e[i].event].pme_flags & PFMLIB_COREDUO_PMC0)) { if (pfm_regmask_isset(r_pmcs, 0)) return PFMLIB_ERR_NOASSIGN; assign_pc[i] = 0; next_gen++; } if (coreduo_pe[e[i].event].pme_flags & PFMLIB_COREDUO_PMC1) { if (pfm_regmask_isset(r_pmcs, 1)) return PFMLIB_ERR_NOASSIGN; assign_pc[i] = 1; next_gen = (next_gen+1) % PMU_COREDUO_NUM_COUNTERS; } } /* * assign what is left */ for(i=0; i < n; i++) { if (assign_pc[i] == -1) { for(; next_gen <= last_gen; next_gen++) { DPRINT("i=%d next_gen=%d last=%d isset=%d\n", i, next_gen, last_gen, pfm_regmask_isset(r_pmcs, next_gen)); if (!pfm_regmask_isset(r_pmcs, next_gen)) break; } if (next_gen <= last_gen) assign_pc[i] = next_gen++; else { DPRINT("cannot assign generic counters\n"); return PFMLIB_ERR_NOASSIGN; } } } for (i=0; i < n ; i++ ) { reg.val = 0; /* assume reserved bits are zerooed */ /* if plm is 0, then assume not specified per-event and use default */ plm = e[i].plm ? e[i].plm : inp->pfp_dfl_plm; val = coreduo_pe[e[i].event].pme_code; reg.sel_event_select = val & 0xff; ucode = (val >> 8) & 0xff; for(k=0; k < e[i].num_masks; k++) { ucode |= coreduo_pe[e[i].event].pme_umasks[e[i].unit_masks[k]].pme_ucode; } /* * for events supporting Core specificity (self, both), a value * of 0 for bits 15:14 (7:6 in our umask) is reserved, therefore we * force to SELF if user did not specify anything */ if ((coreduo_pe[e[i].event].pme_flags & PFMLIB_COREDUO_CSPEC) && ((ucode & (0x3 << 6)) == 0)) { ucode |= 1 << 6; } /* * for events supporting MESI, a value * of 0 for bits 11:8 (0-3 in our umask) means nothing will be * counted. Therefore, we force a default of 0xf (M,E,S,I). */ if ((coreduo_pe[e[i].event].pme_flags & PFMLIB_COREDUO_MESI) && ((ucode & 0xf) == 0)) { ucode |= 0xf; } val |= ucode << 8; reg.sel_unit_mask = ucode; reg.sel_usr = plm & PFM_PLM3 ? 1 : 0; reg.sel_os = plm & PFM_PLM0 ? 1 : 0; reg.sel_en = 1; /* force enable bit to 1 */ reg.sel_int = 1; /* force APIC int to 1 */ reg.sel_cnt_mask = val >>24; reg.sel_inv = val >> 23; reg.sel_edge = val >> 18; if (cntrs) { if (!reg.sel_cnt_mask) { /* * counter mask is 8-bit wide, do not silently * wrap-around */ if (cntrs[i].cnt_mask > 255) return PFMLIB_ERR_INVAL; reg.sel_cnt_mask = cntrs[i].cnt_mask; } if (!reg.sel_edge) reg.sel_edge = cntrs[i].flags & PFM_COREDUO_SEL_EDGE ? 1 : 0; if (!reg.sel_inv) reg.sel_inv = cntrs[i].flags & PFM_COREDUO_SEL_INV ? 1 : 0; } pc[npc].reg_num = assign_pc[i]; pc[npc].reg_value = reg.val; pc[npc].reg_addr = COREDUO_SEL_BASE+assign_pc[i]; pc[npc].reg_alt_addr= COREDUO_SEL_BASE+assign_pc[i]; __pfm_vbprintf("[PERFEVTSEL%u(pmc%u)=0x%"PRIx64" event_sel=0x%x umask=0x%x os=%d usr=%d en=%d int=%d inv=%d edge=%d cnt_mask=%d] %s\n", pc[npc].reg_num, pc[npc].reg_num, reg.val, reg.sel_event_select, reg.sel_unit_mask, reg.sel_os, reg.sel_usr, reg.sel_en, reg.sel_int, reg.sel_inv, reg.sel_edge, reg.sel_cnt_mask, coreduo_pe[e[i].event].pme_name); __pfm_vbprintf("[PMC%u(pmd%u)]\n", pc[npc].reg_num, pc[npc].reg_num); npc++; } /* * setup pmds: must be in the same order as the events */ for (i=0; i < n ; i++) { pd[i].reg_num = assign_pc[i]; pd[i].reg_addr = COREDUO_CTR_BASE+assign_pc[i]; /* index to use with RDPMC */ pd[i].reg_alt_addr = assign_pc[i]; } outp->pfp_pmd_count = i; outp->pfp_pmc_count = npc; return PFMLIB_SUCCESS; } static int pfm_coreduo_dispatch_events(pfmlib_input_param_t *inp, void *model_in, pfmlib_output_param_t *outp, void *model_out) { pfmlib_coreduo_input_param_t *mod_in = (pfmlib_coreduo_input_param_t *)model_in; if (inp->pfp_dfl_plm & (PFM_PLM1|PFM_PLM2)) { DPRINT("invalid plm=%x\n", inp->pfp_dfl_plm); return PFMLIB_ERR_INVAL; } return pfm_coreduo_dispatch_counters(inp, mod_in, outp); } static int pfm_coreduo_get_event_code(unsigned int i, unsigned int cnt, int *code) { if (cnt != PFMLIB_CNT_FIRST && (cnt > highest_counter || !pfm_regmask_isset(&coreduo_impl_pmds, cnt))) return PFMLIB_ERR_INVAL; *code = coreduo_pe[i].pme_code; return PFMLIB_SUCCESS; } static void pfm_coreduo_get_event_counters(unsigned int j, pfmlib_regmask_t *counters) { memset(counters, 0, sizeof(*counters)); pfm_regmask_set(counters, 0); pfm_regmask_set(counters, 1); if (coreduo_pe[j].pme_flags & PFMLIB_COREDUO_PMC0) pfm_regmask_clr(counters, 1); if (coreduo_pe[j].pme_flags & PFMLIB_COREDUO_PMC1) pfm_regmask_clr(counters, 0); } static void pfm_coreduo_get_impl_pmcs(pfmlib_regmask_t *impl_pmcs) { *impl_pmcs = coreduo_impl_pmcs; } static void pfm_coreduo_get_impl_pmds(pfmlib_regmask_t *impl_pmds) { *impl_pmds = coreduo_impl_pmds; } static void pfm_coreduo_get_impl_counters(pfmlib_regmask_t *impl_counters) { /* all pmds are counters */ *impl_counters = coreduo_impl_pmds; } /* * Even though, CPUID 0xa returns in eax the actual counter * width, the architecture specifies that writes are limited * to lower 32-bits. As such, only the lower 32-bit have full * degree of freedom. That is the "useable" counter width. */ static void pfm_coreduo_get_hw_counter_width(unsigned int *width) { /* * Even though, CPUID 0xa returns in eax the actual counter * width, the architecture specifies that writes are limited * to lower 32-bits. As such, only the lower 31 bits have full * degree of freedom. That is the "useable" counter width. */ *width = 32; } static char * pfm_coreduo_get_event_name(unsigned int i) { return coreduo_pe[i].pme_name; } static int pfm_coreduo_get_event_description(unsigned int ev, char **str) { char *s; s = coreduo_pe[ev].pme_desc; if (s) { *str = strdup(s); } else { *str = NULL; } return PFMLIB_SUCCESS; } static char * pfm_coreduo_get_event_mask_name(unsigned int ev, unsigned int midx) { return coreduo_pe[ev].pme_umasks[midx].pme_uname; } static int pfm_coreduo_get_event_mask_desc(unsigned int ev, unsigned int midx, char **str) { char *s; s = coreduo_pe[ev].pme_umasks[midx].pme_udesc; if (s) { *str = strdup(s); } else { *str = NULL; } return PFMLIB_SUCCESS; } static unsigned int pfm_coreduo_get_num_event_masks(unsigned int ev) { return coreduo_pe[ev].pme_numasks; } static int pfm_coreduo_get_event_mask_code(unsigned int ev, unsigned int midx, unsigned int *code) { *code = coreduo_pe[ev].pme_umasks[midx].pme_ucode; return PFMLIB_SUCCESS; } static int pfm_coreduo_get_cycle_event(pfmlib_event_t *e) { e->event = PME_COREDUO_UNHALTED_CORE_CYCLES; return PFMLIB_SUCCESS; } static int pfm_coreduo_get_inst_retired(pfmlib_event_t *e) { e->event = PME_COREDUO_INSTRUCTIONS_RETIRED; return PFMLIB_SUCCESS; } pfm_pmu_support_t coreduo_support={ .pmu_name = "Intel Core Duo/Solo", .pmu_type = PFMLIB_COREDUO_PMU, .pme_count = PME_COREDUO_EVENT_COUNT, .pmc_count = 2, .pmd_count = 2, .num_cnt = 2, .get_event_code = pfm_coreduo_get_event_code, .get_event_name = pfm_coreduo_get_event_name, .get_event_counters = pfm_coreduo_get_event_counters, .dispatch_events = pfm_coreduo_dispatch_events, .pmu_detect = pfm_coreduo_detect, .pmu_init = pfm_coreduo_init, .get_impl_pmcs = pfm_coreduo_get_impl_pmcs, .get_impl_pmds = pfm_coreduo_get_impl_pmds, .get_impl_counters = pfm_coreduo_get_impl_counters, .get_hw_counter_width = pfm_coreduo_get_hw_counter_width, .get_event_desc = pfm_coreduo_get_event_description, .get_num_event_masks = pfm_coreduo_get_num_event_masks, .get_event_mask_name = pfm_coreduo_get_event_mask_name, .get_event_mask_code = pfm_coreduo_get_event_mask_code, .get_event_mask_desc = pfm_coreduo_get_event_mask_desc, .get_cycle_event = pfm_coreduo_get_cycle_event, .get_inst_retired_event = pfm_coreduo_get_inst_retired }; papi-5.5.1/src/libpfm-3.y/lib/itanium_events.h0000644000307100002310000006674113013651450021111 0ustar yarkhangraduate/* * Copyright (c) 2001-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ /* * This file is generated automatically * !! DO NOT CHANGE !! */ /* * Events table for the Itanium PMU family */ static pme_ita_entry_t itanium_pe []={ #define PME_ITA_ALAT_INST_CHKA_LDC_ALL 0 { "ALAT_INST_CHKA_LDC_ALL", {0x30036} , 0xf0, 2, {0xffff0003}, NULL}, #define PME_ITA_ALAT_INST_CHKA_LDC_FP 1 { "ALAT_INST_CHKA_LDC_FP", {0x10036} , 0xf0, 2, {0xffff0003}, NULL}, #define PME_ITA_ALAT_INST_CHKA_LDC_INT 2 { "ALAT_INST_CHKA_LDC_INT", {0x20036} , 0xf0, 2, {0xffff0003}, NULL}, #define PME_ITA_ALAT_INST_FAILED_CHKA_LDC_ALL 3 { "ALAT_INST_FAILED_CHKA_LDC_ALL", {0x30037} , 0xf0, 2, {0xffff0003}, NULL}, #define PME_ITA_ALAT_INST_FAILED_CHKA_LDC_FP 4 { "ALAT_INST_FAILED_CHKA_LDC_FP", {0x10037} , 0xf0, 2, {0xffff0003}, NULL}, #define PME_ITA_ALAT_INST_FAILED_CHKA_LDC_INT 5 { "ALAT_INST_FAILED_CHKA_LDC_INT", {0x20037} , 0xf0, 2, {0xffff0003}, NULL}, #define PME_ITA_ALAT_REPLACEMENT_ALL 6 { "ALAT_REPLACEMENT_ALL", {0x30038} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_ALAT_REPLACEMENT_FP 7 { "ALAT_REPLACEMENT_FP", {0x10038} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_ALAT_REPLACEMENT_INT 8 { "ALAT_REPLACEMENT_INT", {0x20038} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_ALL_STOPS_DISPERSED 9 { "ALL_STOPS_DISPERSED", {0x2f} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_BRANCH_EVENT 10 { "BRANCH_EVENT", {0x811} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_MULTIWAY_ALL_PATHS_ALL_PREDICTIONS 11 { "BRANCH_MULTIWAY_ALL_PATHS_ALL_PREDICTIONS", {0xe} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_MULTIWAY_ALL_PATHS_CORRECT_PREDICTIONS 12 { "BRANCH_MULTIWAY_ALL_PATHS_CORRECT_PREDICTIONS", {0x1000e} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_MULTIWAY_ALL_PATHS_WRONG_PATH 13 { "BRANCH_MULTIWAY_ALL_PATHS_WRONG_PATH", {0x2000e} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_MULTIWAY_ALL_PATHS_WRONG_TARGET 14 { "BRANCH_MULTIWAY_ALL_PATHS_WRONG_TARGET", {0x3000e} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_MULTIWAY_NOT_TAKEN_ALL_PREDICTIONS 15 { "BRANCH_MULTIWAY_NOT_TAKEN_ALL_PREDICTIONS", {0x8000e} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_MULTIWAY_NOT_TAKEN_CORRECT_PREDICTIONS 16 { "BRANCH_MULTIWAY_NOT_TAKEN_CORRECT_PREDICTIONS", {0x9000e} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_MULTIWAY_NOT_TAKEN_WRONG_PATH 17 { "BRANCH_MULTIWAY_NOT_TAKEN_WRONG_PATH", {0xa000e} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_MULTIWAY_NOT_TAKEN_WRONG_TARGET 18 { "BRANCH_MULTIWAY_NOT_TAKEN_WRONG_TARGET", {0xb000e} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_MULTIWAY_TAKEN_ALL_PREDICTIONS 19 { "BRANCH_MULTIWAY_TAKEN_ALL_PREDICTIONS", {0xc000e} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_MULTIWAY_TAKEN_CORRECT_PREDICTIONS 20 { "BRANCH_MULTIWAY_TAKEN_CORRECT_PREDICTIONS", {0xd000e} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_MULTIWAY_TAKEN_WRONG_PATH 21 { "BRANCH_MULTIWAY_TAKEN_WRONG_PATH", {0xe000e} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_MULTIWAY_TAKEN_WRONG_TARGET 22 { "BRANCH_MULTIWAY_TAKEN_WRONG_TARGET", {0xf000e} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_NOT_TAKEN 23 { "BRANCH_NOT_TAKEN", {0x8000d} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_1ST_STAGE_NT_OUTCOMES_CORRECTLY_PREDICTED 24 { "BRANCH_PATH_1ST_STAGE_NT_OUTCOMES_CORRECTLY_PREDICTED", {0x6000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_1ST_STAGE_NT_OUTCOMES_INCORRECTLY_PREDICTED 25 { "BRANCH_PATH_1ST_STAGE_NT_OUTCOMES_INCORRECTLY_PREDICTED", {0x4000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_1ST_STAGE_TK_OUTCOMES_CORRECTLY_PREDICTED 26 { "BRANCH_PATH_1ST_STAGE_TK_OUTCOMES_CORRECTLY_PREDICTED", {0x7000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_1ST_STAGE_TK_OUTCOMES_INCORRECTLY_PREDICTED 27 { "BRANCH_PATH_1ST_STAGE_TK_OUTCOMES_INCORRECTLY_PREDICTED", {0x5000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_2ND_STAGE_NT_OUTCOMES_CORRECTLY_PREDICTED 28 { "BRANCH_PATH_2ND_STAGE_NT_OUTCOMES_CORRECTLY_PREDICTED", {0xa000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_2ND_STAGE_NT_OUTCOMES_INCORRECTLY_PREDICTED 29 { "BRANCH_PATH_2ND_STAGE_NT_OUTCOMES_INCORRECTLY_PREDICTED", {0x8000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_2ND_STAGE_TK_OUTCOMES_CORRECTLY_PREDICTED 30 { "BRANCH_PATH_2ND_STAGE_TK_OUTCOMES_CORRECTLY_PREDICTED", {0xb000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_2ND_STAGE_TK_OUTCOMES_INCORRECTLY_PREDICTED 31 { "BRANCH_PATH_2ND_STAGE_TK_OUTCOMES_INCORRECTLY_PREDICTED", {0x9000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_3RD_STAGE_NT_OUTCOMES_CORRECTLY_PREDICTED 32 { "BRANCH_PATH_3RD_STAGE_NT_OUTCOMES_CORRECTLY_PREDICTED", {0xe000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_3RD_STAGE_NT_OUTCOMES_INCORRECTLY_PREDICTED 33 { "BRANCH_PATH_3RD_STAGE_NT_OUTCOMES_INCORRECTLY_PREDICTED", {0xc000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_3RD_STAGE_TK_OUTCOMES_CORRECTLY_PREDICTED 34 { "BRANCH_PATH_3RD_STAGE_TK_OUTCOMES_CORRECTLY_PREDICTED", {0xf000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_3RD_STAGE_TK_OUTCOMES_INCORRECTLY_PREDICTED 35 { "BRANCH_PATH_3RD_STAGE_TK_OUTCOMES_INCORRECTLY_PREDICTED", {0xd000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_ALL_NT_OUTCOMES_CORRECTLY_PREDICTED 36 { "BRANCH_PATH_ALL_NT_OUTCOMES_CORRECTLY_PREDICTED", {0x2000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_ALL_NT_OUTCOMES_INCORRECTLY_PREDICTED 37 { "BRANCH_PATH_ALL_NT_OUTCOMES_INCORRECTLY_PREDICTED", {0xf} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_ALL_TK_OUTCOMES_CORRECTLY_PREDICTED 38 { "BRANCH_PATH_ALL_TK_OUTCOMES_CORRECTLY_PREDICTED", {0x3000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PATH_ALL_TK_OUTCOMES_INCORRECTLY_PREDICTED 39 { "BRANCH_PATH_ALL_TK_OUTCOMES_INCORRECTLY_PREDICTED", {0x1000f} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_1ST_STAGE_ALL_PREDICTIONS 40 { "BRANCH_PREDICTOR_1ST_STAGE_ALL_PREDICTIONS", {0x40010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_1ST_STAGE_CORRECT_PREDICTIONS 41 { "BRANCH_PREDICTOR_1ST_STAGE_CORRECT_PREDICTIONS", {0x50010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_1ST_STAGE_WRONG_PATH 42 { "BRANCH_PREDICTOR_1ST_STAGE_WRONG_PATH", {0x60010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_1ST_STAGE_WRONG_TARGET 43 { "BRANCH_PREDICTOR_1ST_STAGE_WRONG_TARGET", {0x70010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_2ND_STAGE_ALL_PREDICTIONS 44 { "BRANCH_PREDICTOR_2ND_STAGE_ALL_PREDICTIONS", {0x80010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_2ND_STAGE_CORRECT_PREDICTIONS 45 { "BRANCH_PREDICTOR_2ND_STAGE_CORRECT_PREDICTIONS", {0x90010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_2ND_STAGE_WRONG_PATH 46 { "BRANCH_PREDICTOR_2ND_STAGE_WRONG_PATH", {0xa0010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_2ND_STAGE_WRONG_TARGET 47 { "BRANCH_PREDICTOR_2ND_STAGE_WRONG_TARGET", {0xb0010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_3RD_STAGE_ALL_PREDICTIONS 48 { "BRANCH_PREDICTOR_3RD_STAGE_ALL_PREDICTIONS", {0xc0010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_3RD_STAGE_CORRECT_PREDICTIONS 49 { "BRANCH_PREDICTOR_3RD_STAGE_CORRECT_PREDICTIONS", {0xd0010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_3RD_STAGE_WRONG_PATH 50 { "BRANCH_PREDICTOR_3RD_STAGE_WRONG_PATH", {0xe0010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_3RD_STAGE_WRONG_TARGET 51 { "BRANCH_PREDICTOR_3RD_STAGE_WRONG_TARGET", {0xf0010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_ALL_ALL_PREDICTIONS 52 { "BRANCH_PREDICTOR_ALL_ALL_PREDICTIONS", {0x10} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_ALL_CORRECT_PREDICTIONS 53 { "BRANCH_PREDICTOR_ALL_CORRECT_PREDICTIONS", {0x10010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_ALL_WRONG_PATH 54 { "BRANCH_PREDICTOR_ALL_WRONG_PATH", {0x20010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_PREDICTOR_ALL_WRONG_TARGET 55 { "BRANCH_PREDICTOR_ALL_WRONG_TARGET", {0x30010} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_TAKEN_SLOT_0 56 { "BRANCH_TAKEN_SLOT_0", {0x1000d} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_TAKEN_SLOT_1 57 { "BRANCH_TAKEN_SLOT_1", {0x2000d} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BRANCH_TAKEN_SLOT_2 58 { "BRANCH_TAKEN_SLOT_2", {0x4000d} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_BUS_ALL_ANY 59 { "BUS_ALL_ANY", {0x10047} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_ALL_IO 60 { "BUS_ALL_IO", {0x40047} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_ALL_SELF 61 { "BUS_ALL_SELF", {0x20047} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_BRQ_LIVE_REQ_HI 62 { "BUS_BRQ_LIVE_REQ_HI", {0x5c} , 0xf0, 2, {0xffff0000}, NULL}, #define PME_ITA_BUS_BRQ_LIVE_REQ_LO 63 { "BUS_BRQ_LIVE_REQ_LO", {0x5b} , 0xf0, 2, {0xffff0000}, NULL}, #define PME_ITA_BUS_BRQ_REQ_INSERTED 64 { "BUS_BRQ_REQ_INSERTED", {0x5d} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_BURST_ANY 65 { "BUS_BURST_ANY", {0x10049} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_BURST_IO 66 { "BUS_BURST_IO", {0x40049} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_BURST_SELF 67 { "BUS_BURST_SELF", {0x20049} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_HITM 68 { "BUS_HITM", {0x44} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_IO_ANY 69 { "BUS_IO_ANY", {0x10050} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_IOQ_LIVE_REQ_HI 70 { "BUS_IOQ_LIVE_REQ_HI", {0x58} , 0xf0, 3, {0xffff0000}, NULL}, #define PME_ITA_BUS_IOQ_LIVE_REQ_LO 71 { "BUS_IOQ_LIVE_REQ_LO", {0x57} , 0xf0, 3, {0xffff0000}, NULL}, #define PME_ITA_BUS_IO_SELF 72 { "BUS_IO_SELF", {0x20050} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_LOCK_ANY 73 { "BUS_LOCK_ANY", {0x10053} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_LOCK_CYCLES_ANY 74 { "BUS_LOCK_CYCLES_ANY", {0x10054} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_LOCK_CYCLES_SELF 75 { "BUS_LOCK_CYCLES_SELF", {0x20054} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_LOCK_SELF 76 { "BUS_LOCK_SELF", {0x20053} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_MEMORY_ANY 77 { "BUS_MEMORY_ANY", {0x1004a} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_MEMORY_IO 78 { "BUS_MEMORY_IO", {0x4004a} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_MEMORY_SELF 79 { "BUS_MEMORY_SELF", {0x2004a} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_PARTIAL_ANY 80 { "BUS_PARTIAL_ANY", {0x10048} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_PARTIAL_IO 81 { "BUS_PARTIAL_IO", {0x40048} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_PARTIAL_SELF 82 { "BUS_PARTIAL_SELF", {0x20048} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_ALL_ANY 83 { "BUS_RD_ALL_ANY", {0x1004b} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_ALL_IO 84 { "BUS_RD_ALL_IO", {0x4004b} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_ALL_SELF 85 { "BUS_RD_ALL_SELF", {0x2004b} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_DATA_ANY 86 { "BUS_RD_DATA_ANY", {0x1004c} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_DATA_IO 87 { "BUS_RD_DATA_IO", {0x4004c} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_DATA_SELF 88 { "BUS_RD_DATA_SELF", {0x2004c} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_HIT 89 { "BUS_RD_HIT", {0x40} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_HITM 90 { "BUS_RD_HITM", {0x41} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_INVAL_ANY 91 { "BUS_RD_INVAL_ANY", {0x1004e} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_INVAL_BST_ANY 92 { "BUS_RD_INVAL_BST_ANY", {0x1004f} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_INVAL_BST_HITM 93 { "BUS_RD_INVAL_BST_HITM", {0x43} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_INVAL_BST_IO 94 { "BUS_RD_INVAL_BST_IO", {0x4004f} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_INVAL_BST_SELF 95 { "BUS_RD_INVAL_BST_SELF", {0x2004f} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_INVAL_HITM 96 { "BUS_RD_INVAL_HITM", {0x42} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_INVAL_IO 97 { "BUS_RD_INVAL_IO", {0x4004e} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_INVAL_SELF 98 { "BUS_RD_INVAL_SELF", {0x2004e} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_IO_ANY 99 { "BUS_RD_IO_ANY", {0x10051} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_IO_SELF 100 { "BUS_RD_IO_SELF", {0x20051} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_PRTL_ANY 101 { "BUS_RD_PRTL_ANY", {0x1004d} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_PRTL_IO 102 { "BUS_RD_PRTL_IO", {0x4004d} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_RD_PRTL_SELF 103 { "BUS_RD_PRTL_SELF", {0x2004d} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_SNOOPQ_REQ 104 { "BUS_SNOOPQ_REQ", {0x56} , 0x30, 3, {0xffff0000}, NULL}, #define PME_ITA_BUS_SNOOPS_ANY 105 { "BUS_SNOOPS_ANY", {0x10046} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_SNOOPS_HITM_ANY 106 { "BUS_SNOOPS_HITM_ANY", {0x10045} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_SNOOP_STALL_CYCLES_ANY 107 { "BUS_SNOOP_STALL_CYCLES_ANY", {0x10055} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_SNOOP_STALL_CYCLES_SELF 108 { "BUS_SNOOP_STALL_CYCLES_SELF", {0x20055} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_WR_WB_ANY 109 { "BUS_WR_WB_ANY", {0x10052} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_WR_WB_IO 110 { "BUS_WR_WB_IO", {0x40052} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_BUS_WR_WB_SELF 111 { "BUS_WR_WB_SELF", {0x20052} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_CPU_CPL_CHANGES 112 { "CPU_CPL_CHANGES", {0x34} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_CPU_CYCLES 113 { "CPU_CYCLES", {0x12} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_DATA_ACCESS_CYCLE 114 { "DATA_ACCESS_CYCLE", {0x3} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_DATA_EAR_CACHE_LAT1024 115 { "DATA_EAR_CACHE_LAT1024", {0x90367} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_DATA_EAR_CACHE_LAT128 116 { "DATA_EAR_CACHE_LAT128", {0x50367} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_DATA_EAR_CACHE_LAT16 117 { "DATA_EAR_CACHE_LAT16", {0x20367} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_DATA_EAR_CACHE_LAT2048 118 { "DATA_EAR_CACHE_LAT2048", {0xa0367} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_DATA_EAR_CACHE_LAT256 119 { "DATA_EAR_CACHE_LAT256", {0x60367} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_DATA_EAR_CACHE_LAT32 120 { "DATA_EAR_CACHE_LAT32", {0x30367} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_DATA_EAR_CACHE_LAT4 121 { "DATA_EAR_CACHE_LAT4", {0x367} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_DATA_EAR_CACHE_LAT512 122 { "DATA_EAR_CACHE_LAT512", {0x80367} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_DATA_EAR_CACHE_LAT64 123 { "DATA_EAR_CACHE_LAT64", {0x40367} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_DATA_EAR_CACHE_LAT8 124 { "DATA_EAR_CACHE_LAT8", {0x10367} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_DATA_EAR_CACHE_LAT_NONE 125 { "DATA_EAR_CACHE_LAT_NONE", {0xf0367} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_DATA_EAR_EVENTS 126 { "DATA_EAR_EVENTS", {0x67} , 0xf0, 1, {0xffff0007}, NULL}, #define PME_ITA_DATA_EAR_TLB_L2 127 { "DATA_EAR_TLB_L2", {0x20767} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_DATA_EAR_TLB_SW 128 { "DATA_EAR_TLB_SW", {0x80767} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_DATA_EAR_TLB_VHPT 129 { "DATA_EAR_TLB_VHPT", {0x40767} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_DATA_REFERENCES_RETIRED 130 { "DATA_REFERENCES_RETIRED", {0x63} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_DEPENDENCY_ALL_CYCLE 131 { "DEPENDENCY_ALL_CYCLE", {0x6} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_DEPENDENCY_SCOREBOARD_CYCLE 132 { "DEPENDENCY_SCOREBOARD_CYCLE", {0x2} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_DTC_MISSES 133 { "DTC_MISSES", {0x60} , 0xf0, 1, {0xffff0007}, NULL}, #define PME_ITA_DTLB_INSERTS_HPW 134 { "DTLB_INSERTS_HPW", {0x62} , 0xf0, 1, {0xffff0007}, NULL}, #define PME_ITA_DTLB_MISSES 135 { "DTLB_MISSES", {0x61} , 0xf0, 1, {0xffff0007}, NULL}, #define PME_ITA_EXPL_STOPBITS 136 { "EXPL_STOPBITS", {0x2e} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_FP_FLUSH_TO_ZERO 137 { "FP_FLUSH_TO_ZERO", {0xb} , 0xf0, 2, {0xffff0003}, NULL}, #define PME_ITA_FP_OPS_RETIRED_HI 138 { "FP_OPS_RETIRED_HI", {0xa} , 0xf0, 3, {0xffff0003}, NULL}, #define PME_ITA_FP_OPS_RETIRED_LO 139 { "FP_OPS_RETIRED_LO", {0x9} , 0xf0, 3, {0xffff0003}, NULL}, #define PME_ITA_FP_SIR_FLUSH 140 { "FP_SIR_FLUSH", {0xc} , 0xf0, 2, {0xffff0003}, NULL}, #define PME_ITA_IA32_INST_RETIRED 141 { "IA32_INST_RETIRED", {0x15} , 0xf0, 2, {0xffff0000}, NULL}, #define PME_ITA_IA64_INST_RETIRED 142 { "IA64_INST_RETIRED", {0x8} , 0x30, 6, {0xffff0003}, NULL}, #define PME_ITA_IA64_TAGGED_INST_RETIRED_PMC8 143 { "IA64_TAGGED_INST_RETIRED_PMC8", {0x30008} , 0x30, 6, {0xffff0003}, NULL}, #define PME_ITA_IA64_TAGGED_INST_RETIRED_PMC9 144 { "IA64_TAGGED_INST_RETIRED_PMC9", {0x20008} , 0x30, 6, {0xffff0003}, NULL}, #define PME_ITA_INST_ACCESS_CYCLE 145 { "INST_ACCESS_CYCLE", {0x1} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_INST_DISPERSED 146 { "INST_DISPERSED", {0x2d} , 0x30, 6, {0xffff0001}, NULL}, #define PME_ITA_INST_FAILED_CHKS_RETIRED_ALL 147 { "INST_FAILED_CHKS_RETIRED_ALL", {0x30035} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_INST_FAILED_CHKS_RETIRED_FP 148 { "INST_FAILED_CHKS_RETIRED_FP", {0x20035} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_INST_FAILED_CHKS_RETIRED_INT 149 { "INST_FAILED_CHKS_RETIRED_INT", {0x10035} , 0xf0, 1, {0xffff0003}, NULL}, #define PME_ITA_INSTRUCTION_EAR_CACHE_LAT1024 150 { "INSTRUCTION_EAR_CACHE_LAT1024", {0x80123} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_INSTRUCTION_EAR_CACHE_LAT128 151 { "INSTRUCTION_EAR_CACHE_LAT128", {0x50123} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_INSTRUCTION_EAR_CACHE_LAT16 152 { "INSTRUCTION_EAR_CACHE_LAT16", {0x20123} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_INSTRUCTION_EAR_CACHE_LAT2048 153 { "INSTRUCTION_EAR_CACHE_LAT2048", {0x90123} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_INSTRUCTION_EAR_CACHE_LAT256 154 { "INSTRUCTION_EAR_CACHE_LAT256", {0x60123} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_INSTRUCTION_EAR_CACHE_LAT32 155 { "INSTRUCTION_EAR_CACHE_LAT32", {0x30123} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_INSTRUCTION_EAR_CACHE_LAT4096 156 { "INSTRUCTION_EAR_CACHE_LAT4096", {0xa0123} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_INSTRUCTION_EAR_CACHE_LAT4 157 { "INSTRUCTION_EAR_CACHE_LAT4", {0x123} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_INSTRUCTION_EAR_CACHE_LAT512 158 { "INSTRUCTION_EAR_CACHE_LAT512", {0x70123} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_INSTRUCTION_EAR_CACHE_LAT64 159 { "INSTRUCTION_EAR_CACHE_LAT64", {0x40123} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_INSTRUCTION_EAR_CACHE_LAT8 160 { "INSTRUCTION_EAR_CACHE_LAT8", {0x10123} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_INSTRUCTION_EAR_CACHE_LAT_NONE 161 { "INSTRUCTION_EAR_CACHE_LAT_NONE", {0xf0123} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_INSTRUCTION_EAR_EVENTS 162 { "INSTRUCTION_EAR_EVENTS", {0x23} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_INSTRUCTION_EAR_TLB_SW 163 { "INSTRUCTION_EAR_TLB_SW", {0x80523} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_INSTRUCTION_EAR_TLB_VHPT 164 { "INSTRUCTION_EAR_TLB_VHPT", {0x40523} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_ISA_TRANSITIONS 165 { "ISA_TRANSITIONS", {0x14} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_ISB_LINES_IN 166 { "ISB_LINES_IN", {0x26} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_ITLB_INSERTS_HPW 167 { "ITLB_INSERTS_HPW", {0x28} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_ITLB_MISSES_FETCH 168 { "ITLB_MISSES_FETCH", {0x27} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_L1D_READ_FORCED_MISSES_RETIRED 169 { "L1D_READ_FORCED_MISSES_RETIRED", {0x6b} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_L1D_READ_MISSES_RETIRED 170 { "L1D_READ_MISSES_RETIRED", {0x66} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_L1D_READS_RETIRED 171 { "L1D_READS_RETIRED", {0x64} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_L1I_DEMAND_READS 172 { "L1I_DEMAND_READS", {0x20} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_L1I_FILLS 173 { "L1I_FILLS", {0x21} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L1I_PREFETCH_READS 174 { "L1I_PREFETCH_READS", {0x24} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_L1_OUTSTANDING_REQ_HI 175 { "L1_OUTSTANDING_REQ_HI", {0x79} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L1_OUTSTANDING_REQ_LO 176 { "L1_OUTSTANDING_REQ_LO", {0x78} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L2_DATA_REFERENCES_ALL 177 { "L2_DATA_REFERENCES_ALL", {0x30069} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_L2_DATA_REFERENCES_READS 178 { "L2_DATA_REFERENCES_READS", {0x10069} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_L2_DATA_REFERENCES_WRITES 179 { "L2_DATA_REFERENCES_WRITES", {0x20069} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_L2_FLUSH_DETAILS_ADDR_CONFLICT 180 { "L2_FLUSH_DETAILS_ADDR_CONFLICT", {0x20077} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L2_FLUSH_DETAILS_ALL 181 { "L2_FLUSH_DETAILS_ALL", {0xf0077} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L2_FLUSH_DETAILS_BUS_REJECT 182 { "L2_FLUSH_DETAILS_BUS_REJECT", {0x40077} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L2_FLUSH_DETAILS_FULL_FLUSH 183 { "L2_FLUSH_DETAILS_FULL_FLUSH", {0x80077} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L2_FLUSH_DETAILS_ST_BUFFER 184 { "L2_FLUSH_DETAILS_ST_BUFFER", {0x10077} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L2_FLUSHES 185 { "L2_FLUSHES", {0x76} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L2_INST_DEMAND_READS 186 { "L2_INST_DEMAND_READS", {0x22} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_L2_INST_PREFETCH_READS 187 { "L2_INST_PREFETCH_READS", {0x25} , 0xf0, 1, {0xffff0001}, NULL}, #define PME_ITA_L2_MISSES 188 { "L2_MISSES", {0x6a} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_L2_REFERENCES 189 { "L2_REFERENCES", {0x68} , 0xf0, 3, {0xffff0007}, NULL}, #define PME_ITA_L3_LINES_REPLACED 190 { "L3_LINES_REPLACED", {0x7f} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_MISSES 191 { "L3_MISSES", {0x7c} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_READS_ALL_READS_ALL 192 { "L3_READS_ALL_READS_ALL", {0xf007d} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_READS_ALL_READS_HIT 193 { "L3_READS_ALL_READS_HIT", {0xd007d} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_READS_ALL_READS_MISS 194 { "L3_READS_ALL_READS_MISS", {0xe007d} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_READS_DATA_READS_ALL 195 { "L3_READS_DATA_READS_ALL", {0xb007d} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_READS_DATA_READS_HIT 196 { "L3_READS_DATA_READS_HIT", {0x9007d} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_READS_DATA_READS_MISS 197 { "L3_READS_DATA_READS_MISS", {0xa007d} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_READS_INST_READS_ALL 198 { "L3_READS_INST_READS_ALL", {0x7007d} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_READS_INST_READS_HIT 199 { "L3_READS_INST_READS_HIT", {0x5007d} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_READS_INST_READS_MISS 200 { "L3_READS_INST_READS_MISS", {0x6007d} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_REFERENCES 201 { "L3_REFERENCES", {0x7b} , 0xf0, 1, {0xffff0007}, NULL}, #define PME_ITA_L3_WRITES_ALL_WRITES_ALL 202 { "L3_WRITES_ALL_WRITES_ALL", {0xf007e} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_WRITES_ALL_WRITES_HIT 203 { "L3_WRITES_ALL_WRITES_HIT", {0xd007e} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_WRITES_ALL_WRITES_MISS 204 { "L3_WRITES_ALL_WRITES_MISS", {0xe007e} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_WRITES_DATA_WRITES_ALL 205 { "L3_WRITES_DATA_WRITES_ALL", {0x7007e} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_WRITES_DATA_WRITES_HIT 206 { "L3_WRITES_DATA_WRITES_HIT", {0x5007e} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_WRITES_DATA_WRITES_MISS 207 { "L3_WRITES_DATA_WRITES_MISS", {0x6007e} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_WRITES_L2_WRITEBACK_ALL 208 { "L3_WRITES_L2_WRITEBACK_ALL", {0xb007e} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_WRITES_L2_WRITEBACK_HIT 209 { "L3_WRITES_L2_WRITEBACK_HIT", {0x9007e} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_L3_WRITES_L2_WRITEBACK_MISS 210 { "L3_WRITES_L2_WRITEBACK_MISS", {0xa007e} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_LOADS_RETIRED 211 { "LOADS_RETIRED", {0x6c} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_MEMORY_CYCLE 212 { "MEMORY_CYCLE", {0x7} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_MISALIGNED_LOADS_RETIRED 213 { "MISALIGNED_LOADS_RETIRED", {0x70} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_MISALIGNED_STORES_RETIRED 214 { "MISALIGNED_STORES_RETIRED", {0x71} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_NOPS_RETIRED 215 { "NOPS_RETIRED", {0x30} , 0x30, 6, {0xffff0003}, NULL}, #define PME_ITA_PIPELINE_ALL_FLUSH_CYCLE 216 { "PIPELINE_ALL_FLUSH_CYCLE", {0x4} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_PIPELINE_BACKEND_FLUSH_CYCLE 217 { "PIPELINE_BACKEND_FLUSH_CYCLE", {0x0} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_PIPELINE_FLUSH_ALL 218 { "PIPELINE_FLUSH_ALL", {0xf0033} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_PIPELINE_FLUSH_DTC_FLUSH 219 { "PIPELINE_FLUSH_DTC_FLUSH", {0x40033} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_PIPELINE_FLUSH_IEU_FLUSH 220 { "PIPELINE_FLUSH_IEU_FLUSH", {0x80033} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_PIPELINE_FLUSH_L1D_WAYMP_FLUSH 221 { "PIPELINE_FLUSH_L1D_WAYMP_FLUSH", {0x20033} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_PIPELINE_FLUSH_OTHER_FLUSH 222 { "PIPELINE_FLUSH_OTHER_FLUSH", {0x10033} , 0xf0, 1, {0xffff0000}, NULL}, #define PME_ITA_PREDICATE_SQUASHED_RETIRED 223 { "PREDICATE_SQUASHED_RETIRED", {0x31} , 0x30, 6, {0xffff0003}, NULL}, #define PME_ITA_RSE_LOADS_RETIRED 224 { "RSE_LOADS_RETIRED", {0x72} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_RSE_REFERENCES_RETIRED 225 { "RSE_REFERENCES_RETIRED", {0x65} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_STORES_RETIRED 226 { "STORES_RETIRED", {0x6d} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_UC_LOADS_RETIRED 227 { "UC_LOADS_RETIRED", {0x6e} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_UC_STORES_RETIRED 228 { "UC_STORES_RETIRED", {0x6f} , 0xf0, 2, {0xffff0007}, NULL}, #define PME_ITA_UNSTALLED_BACKEND_CYCLE 229 { "UNSTALLED_BACKEND_CYCLE", {0x5} , 0xf0, 1, {0xffff0000}, NULL}}; #define PME_ITA_EVENT_COUNT 230 papi-5.5.1/src/libpfm-3.y/lib/pfmlib_power7_priv.h0000644000307100002310000000117313013651450021657 0ustar yarkhangraduate/****************************/ /* THIS IS OPEN SOURCE CODE */ /****************************/ #ifndef __PFMLIB_POWER7_PRIV_H__ #define __PFMLIB_POWER7_PRIV_H__ /* * File: pfmlib_power7_priv.h * CVS: * Author: Corey Ashford * cjashfor@us.ibm.com * Mods: * * * (C) Copyright IBM Corporation, 2007. All Rights Reserved. * Contributed by Corey Ashford * * Note: This code was automatically generated and should not be modified by * hand. * */ #define POWER7_NUM_EVENT_COUNTERS 6 #define POWER7_NUM_GROUP_VEC 4 #define POWER7_NUM_CONTROL_REGS 3 #endif papi-5.5.1/src/libpfm-3.y/lib/pfmlib_i386_p6.c0000644000307100002310000004477613013651450020505 0ustar yarkhangraduate/* * pfmlib_i386_pm.c : support for the P6 processor family (family=6) * incl. Pentium II, Pentium III, Pentium Pro, Pentium M * * Copyright (c) 2005-2007 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* public headers */ #include /* private headers */ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_i386_p6_priv.h" /* architecture private */ #include "i386_p6_events.h" /* event tables */ /* let's define some handy shortcuts! */ #define sel_event_mask perfsel.sel_event_mask #define sel_unit_mask perfsel.sel_unit_mask #define sel_usr perfsel.sel_usr #define sel_os perfsel.sel_os #define sel_edge perfsel.sel_edge #define sel_pc perfsel.sel_pc #define sel_int perfsel.sel_int #define sel_en perfsel.sel_en #define sel_inv perfsel.sel_inv #define sel_cnt_mask perfsel.sel_cnt_mask static char * pfm_i386_p6_get_event_name(unsigned int i); static pme_i386_p6_entry_t *i386_pe; static int i386_p6_cycle_event, i386_p6_inst_retired_event; #define PFMLIB_I386_P6_HAS_COMBO(_e) ((i386_pe[_e].pme_flags & PFMLIB_I386_P6_UMASK_COMBO) != 0) #define PFMLIB_I386_P6_ALL_FLAGS \ (PFM_I386_P6_SEL_INV|PFM_I386_P6_SEL_EDGE) /* * Description of the PMC register mappings use by * this module. * pfp_pmcs[].reg_num: * 0 -> PMC0 -> PERFEVTSEL0 -> MSR @ 0x186 * 1 -> PMC1 -> PERFEVTSEL1 -> MSR @ 0x187 * pfp_pmds[].reg_num: * 0 -> PMD0 -> PERFCTR0 -> MSR @ 0xc1 * 1 -> PMD1 -> PERFCTR1 -> MSR @ 0xc2 */ #define I386_P6_SEL_BASE 0x186 #define I386_P6_CTR_BASE 0xc1 static void pfm_i386_p6_get_impl_counters(pfmlib_regmask_t *impl_counters); static int pfm_i386_detect_common(void) { int ret, family; char buffer[128]; ret = __pfm_getcpuinfo_attr("vendor_id", buffer, sizeof(buffer)); if (ret == -1) return PFMLIB_ERR_NOTSUPP; if (strcmp(buffer, "GenuineIntel")) return PFMLIB_ERR_NOTSUPP; ret = __pfm_getcpuinfo_attr("cpu family", buffer, sizeof(buffer)); if (ret == -1) return PFMLIB_ERR_NOTSUPP; family = atoi(buffer); return family != 6 ? PFMLIB_ERR_NOTSUPP : PFMLIB_SUCCESS; } /* * detect Pentium Pro */ static int pfm_i386_p6_detect_ppro(void) { int ret, model; char buffer[128]; ret = pfm_i386_detect_common(); if (ret != PFMLIB_SUCCESS) return ret; ret = __pfm_getcpuinfo_attr("model", buffer, sizeof(buffer)); if (ret == -1) return PFMLIB_ERR_NOTSUPP; model = atoi(buffer); if (model != 1) return PFMLIB_ERR_NOTSUPP; return PFMLIB_SUCCESS; } static int pfm_i386_p6_init_ppro(void) { i386_pe = i386_ppro_pe; i386_p6_cycle_event = PME_I386_PPRO_CPU_CLK_UNHALTED; i386_p6_inst_retired_event = PME_I386_PPRO_INST_RETIRED; return PFMLIB_SUCCESS; } /* * detect Pentium II */ static int pfm_i386_p6_detect_pii(void) { int ret, model; char buffer[128]; ret = pfm_i386_detect_common(); if (ret != PFMLIB_SUCCESS) return ret; ret = __pfm_getcpuinfo_attr("model", buffer, sizeof(buffer)); if (ret == -1) return PFMLIB_ERR_NOTSUPP; model = atoi(buffer); switch(model) { case 3: /* Pentium II */ case 5: /* Pentium II Deschutes */ case 6: /* Pentium II Mendocino */ break; default: return PFMLIB_ERR_NOTSUPP; } return PFMLIB_SUCCESS; } static int pfm_i386_p6_init_pii(void) { i386_pe = i386_pII_pe; i386_p6_cycle_event = PME_I386_PII_CPU_CLK_UNHALTED; i386_p6_inst_retired_event = PME_I386_PII_INST_RETIRED; return PFMLIB_SUCCESS; } /* * detect Pentium III */ static int pfm_i386_p6_detect_piii(void) { int ret, model; char buffer[128]; ret = pfm_i386_detect_common(); if (ret != PFMLIB_SUCCESS) return ret; ret = __pfm_getcpuinfo_attr("model", buffer, sizeof(buffer)); if (ret == -1) return PFMLIB_ERR_NOTSUPP; model = atoi(buffer); switch(model) { case 7: /* Pentium III Katmai */ case 8: /* Pentium III Coppermine */ case 10:/* Pentium III Cascades */ case 11:/* Pentium III Tualatin */ break; default: return PFMLIB_ERR_NOTSUPP; } return PFMLIB_SUCCESS; } static int pfm_i386_p6_init_piii(void) { i386_pe = i386_pIII_pe; i386_p6_cycle_event = PME_I386_PIII_CPU_CLK_UNHALTED; i386_p6_inst_retired_event = PME_I386_PIII_INST_RETIRED; return PFMLIB_SUCCESS; } /* * detect Pentium M */ static int pfm_i386_p6_detect_pm(void) { int ret, model; char buffer[128]; ret = pfm_i386_detect_common(); if (ret != PFMLIB_SUCCESS) return ret; ret = __pfm_getcpuinfo_attr("model", buffer, sizeof(buffer)); if (ret == -1) return PFMLIB_ERR_NOTSUPP; model = atoi(buffer); switch (model) { case 9: case 13: break; default: return PFMLIB_ERR_NOTSUPP; } return PFMLIB_SUCCESS; } static int pfm_i386_p6_init_pm(void) { i386_pe = i386_pm_pe; i386_p6_cycle_event = PME_I386_PM_CPU_CLK_UNHALTED; i386_p6_inst_retired_event = PME_I386_PM_INST_RETIRED; return PFMLIB_SUCCESS; } /* * Automatically dispatch events to corresponding counters following constraints. * Upon return the pfarg_regt structure is ready to be submitted to kernel */ static int pfm_i386_p6_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_i386_p6_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfmlib_i386_p6_input_param_t *param = mod_in; pfmlib_i386_p6_counter_t *cntrs; pfm_i386_p6_sel_reg_t reg; pfmlib_event_t *e; pfmlib_reg_t *pc, *pd; pfmlib_regmask_t impl_cntrs, avail_cntrs; unsigned long plm; unsigned int i, j, cnt, k, umask; unsigned int assign[PMU_I386_P6_NUM_COUNTERS]; e = inp->pfp_events; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; cnt = inp->pfp_event_count; cntrs = param ? param->pfp_i386_p6_counters : NULL; if (PFMLIB_DEBUG()) { for (j=0; j < cnt; j++) { DPRINT("ev[%d]=%s\n", j, i386_pe[e[j].event].pme_name); } } if (cnt > PMU_I386_P6_NUM_COUNTERS) return PFMLIB_ERR_TOOMANY; pfm_i386_p6_get_impl_counters(&impl_cntrs); pfm_regmask_andnot(&avail_cntrs, &impl_cntrs, &inp->pfp_unavail_pmcs); DPRINT("impl=0x%lx avail=0x%lx unavail=0x%lx\n", impl_cntrs.bits[0], avail_cntrs.bits[0], inp->pfp_unavail_pmcs.bits[0]); for(j=0; j < cnt; j++) { /* * P6 only supports two priv levels for perf counters */ if (e[j].plm & (PFM_PLM1|PFM_PLM2)) { DPRINT("event=%d invalid plm=%d\n", e[j].event, e[j].plm); return PFMLIB_ERR_INVAL; } if (cntrs && cntrs[j].flags & ~PFMLIB_I386_P6_ALL_FLAGS) { DPRINT("event=%d invalid flags=0x%lx\n", e[j].event, e[j].flags); return PFMLIB_ERR_INVAL; } /* * check illegal unit masks combination */ if (e[j].num_masks > 1 && PFMLIB_I386_P6_HAS_COMBO(e[j].event) == 0) { DPRINT("event does not support unit mask combination\n"); return PFMLIB_ERR_FEATCOMB; } } /* * first pass: events for fixed counters */ for(j=0; j < cnt; j++) { if (i386_pe[e[j].event].pme_flags & PFMLIB_I386_P6_CTR0_ONLY) { if (!pfm_regmask_isset(&avail_cntrs, 0)) return PFMLIB_ERR_NOASSIGN; assign[j] = 0; pfm_regmask_clr(&avail_cntrs, 0); } else if (i386_pe[e[j].event].pme_flags & PFMLIB_I386_P6_CTR1_ONLY) { if (!pfm_regmask_isset(&avail_cntrs, 1)) return PFMLIB_ERR_NOASSIGN; assign[j] = 1; pfm_regmask_clr(&avail_cntrs, 1); } } /* * second pass: events with no constraints */ for (j=0, i=0; j < cnt ; j++ ) { if (i386_pe[e[j].event].pme_flags & (PFMLIB_I386_P6_CTR0_ONLY|PFMLIB_I386_P6_CTR1_ONLY)) continue; while (i < PMU_I386_P6_NUM_COUNTERS && !pfm_regmask_isset(&avail_cntrs, i)) i++; if (i == PMU_I386_P6_NUM_COUNTERS) return PFMLIB_ERR_NOASSIGN; pfm_regmask_clr(&avail_cntrs, i); assign[j] = i++; } /* * final pass: assign value to registers */ for (j=0; j < cnt ; j++) { reg.val = 0; /* assume reserved bits are zeroed */ /* if plm is 0, then assume not specified per-event and use default */ plm = e[j].plm ? e[j].plm : inp->pfp_dfl_plm; reg.sel_event_mask = i386_pe[e[j].event].pme_code; /* * some events have only a single umask. We do not create * specific umask entry in this case. The umask code is taken * out of the (extended) event code (2nd byte) */ umask = (i386_pe[e[j].event].pme_code >> 8) & 0xff; for(k=0; k < e[j].num_masks; k++) { umask |= i386_pe[e[j].event].pme_umasks[e[j].unit_masks[k]].pme_ucode; } reg.sel_unit_mask = umask; reg.sel_usr = plm & PFM_PLM3 ? 1 : 0; reg.sel_os = plm & PFM_PLM0 ? 1 : 0; reg.sel_int = 1; /* force APIC int to 1 */ /* * only perfevtsel0 has an enable bit (allows atomic start/stop) */ if (assign[j] == 0) reg.sel_en = 1; /* force enable bit to 1 */ if (cntrs) { reg.sel_cnt_mask = cntrs[j].cnt_mask; reg.sel_edge = cntrs[j].flags & PFM_I386_P6_SEL_EDGE ? 1 : 0; reg.sel_inv = cntrs[j].flags & PFM_I386_P6_SEL_INV ? 1 : 0; } pc[j].reg_num = assign[j]; pc[j].reg_value = reg.val; pc[j].reg_addr = I386_P6_SEL_BASE+assign[j]; pc[j].reg_alt_addr= I386_P6_SEL_BASE+assign[j]; pd[j].reg_num = assign[j]; pd[j].reg_addr = I386_P6_CTR_BASE+assign[j]; /* index to use with RDPMC */ pd[j].reg_alt_addr = assign[j]; __pfm_vbprintf("[PERFEVTSEL%u(pmc%u)=0x%lx emask=0x%x umask=0x%x os=%d usr=%d en=%d int=%d inv=%d edge=%d cnt_mask=%d] %s\n", assign[j], assign[j], reg.val, reg.sel_event_mask, reg.sel_unit_mask, reg.sel_os, reg.sel_usr, reg.sel_en, reg.sel_int, reg.sel_inv, reg.sel_edge, reg.sel_cnt_mask, i386_pe[e[j].event].pme_name); __pfm_vbprintf("[PMC%u(pmd%u)]\n", pd[j].reg_num, pd[j].reg_num); } /* * add perfsel0 if not used. This is required as it holds * the enable bit for all counters */ if (pfm_regmask_isset(&avail_cntrs, 0)) { reg.val = 0; reg.sel_en = 1; /* force enable bit to 1 */ pc[j].reg_num = 0; pc[j].reg_value = reg.val; pc[j].reg_addr = I386_P6_SEL_BASE; pc[j].reg_alt_addr = I386_P6_SEL_BASE; j++; __pfm_vbprintf("[PERFEVTSEL0(pmc0)=0x%lx] required for enabling counters\n", reg.val); } /* number of evtsel registers programmed */ outp->pfp_pmc_count = j; outp->pfp_pmd_count = cnt; return PFMLIB_SUCCESS; } static int pfm_i386_p6_dispatch_events(pfmlib_input_param_t *inp, void *model_in, pfmlib_output_param_t *outp, void *model_out) { pfmlib_i386_p6_input_param_t *mod_in = (pfmlib_i386_p6_input_param_t *)model_in; if (inp->pfp_dfl_plm & (PFM_PLM1|PFM_PLM2)) { DPRINT("invalid plm=%x\n", inp->pfp_dfl_plm); return PFMLIB_ERR_INVAL; } return pfm_i386_p6_dispatch_counters(inp, mod_in, outp); } static int pfm_i386_p6_get_event_code(unsigned int i, unsigned int cnt, int *code) { if (cnt != PFMLIB_CNT_FIRST && cnt > 2) return PFMLIB_ERR_INVAL; *code = i386_pe[i].pme_code; return PFMLIB_SUCCESS; } static void pfm_i386_p6_get_event_counters(unsigned int j, pfmlib_regmask_t *counters) { unsigned int i; memset(counters, 0, sizeof(*counters)); if (i386_pe[j].pme_flags & PFMLIB_I386_P6_CTR0_ONLY) { pfm_regmask_set(counters, 0); } else if (i386_pe[j].pme_flags & PFMLIB_I386_P6_CTR1_ONLY) { pfm_regmask_set(counters, 1); } else { for(i=0; i < PMU_I386_P6_NUM_COUNTERS; i++) pfm_regmask_set(counters, i); } } static void pfm_i386_p6_get_impl_perfsel(pfmlib_regmask_t *impl_pmcs) { unsigned int i = 0; /* all pmcs are contiguous */ for(i=0; i < PMU_I386_P6_NUM_PERFSEL; i++) pfm_regmask_set(impl_pmcs, i); } static void pfm_i386_p6_get_impl_perfctr(pfmlib_regmask_t *impl_pmds) { unsigned int i = 0; /* all pmds are contiguous */ for(i=0; i < PMU_I386_P6_NUM_PERFCTR; i++) pfm_regmask_set(impl_pmds, i); } static void pfm_i386_p6_get_impl_counters(pfmlib_regmask_t *impl_counters) { unsigned int i = 0; /* counting pmds are contiguous */ for(i=0; i < PMU_I386_P6_NUM_COUNTERS; i++) pfm_regmask_set(impl_counters, i); } static void pfm_i386_p6_get_hw_counter_width(unsigned int *width) { *width = PMU_I386_P6_COUNTER_WIDTH; } static char * pfm_i386_p6_get_event_name(unsigned int i) { return i386_pe[i].pme_name; } static int pfm_i386_p6_get_event_description(unsigned int ev, char **str) { char *s; s = i386_pe[ev].pme_desc; if (s) { *str = strdup(s); } else { *str = NULL; } return PFMLIB_SUCCESS; } static char * pfm_i386_p6_get_event_mask_name(unsigned int ev, unsigned int midx) { return i386_pe[ev].pme_umasks[midx].pme_uname; } static int pfm_i386_p6_get_event_mask_desc(unsigned int ev, unsigned int midx, char **str) { char *s; s = i386_pe[ev].pme_umasks[midx].pme_udesc; if (s) { *str = strdup(s); } else { *str = NULL; } return PFMLIB_SUCCESS; } static unsigned int pfm_i386_p6_get_num_event_masks(unsigned int ev) { return i386_pe[ev].pme_numasks; } static int pfm_i386_p6_get_event_mask_code(unsigned int ev, unsigned int midx, unsigned int *code) { *code = i386_pe[ev].pme_umasks[midx].pme_ucode; return PFMLIB_SUCCESS; } static int pfm_i386_p6_get_cycle_event(pfmlib_event_t *e) { e->event = i386_p6_cycle_event; return PFMLIB_SUCCESS; } static int pfm_i386_p6_get_inst_retired(pfmlib_event_t *e) { e->event = i386_p6_inst_retired_event; return PFMLIB_SUCCESS; } /* Pentium II support */ pfm_pmu_support_t i386_pii_support={ .pmu_name = "Intel Pentium II", .pmu_type = PFMLIB_INTEL_PII_PMU, .pme_count = PME_I386_PII_EVENT_COUNT, .pmc_count = PMU_I386_P6_NUM_PERFSEL, .pmd_count = PMU_I386_P6_NUM_PERFCTR, .num_cnt = PMU_I386_P6_NUM_COUNTERS, .get_event_code = pfm_i386_p6_get_event_code, .get_event_name = pfm_i386_p6_get_event_name, .get_event_counters = pfm_i386_p6_get_event_counters, .dispatch_events = pfm_i386_p6_dispatch_events, .pmu_detect = pfm_i386_p6_detect_pii, .pmu_init = pfm_i386_p6_init_pii, .get_impl_pmcs = pfm_i386_p6_get_impl_perfsel, .get_impl_pmds = pfm_i386_p6_get_impl_perfctr, .get_impl_counters = pfm_i386_p6_get_impl_counters, .get_hw_counter_width = pfm_i386_p6_get_hw_counter_width, .get_event_desc = pfm_i386_p6_get_event_description, .get_num_event_masks = pfm_i386_p6_get_num_event_masks, .get_event_mask_name = pfm_i386_p6_get_event_mask_name, .get_event_mask_code = pfm_i386_p6_get_event_mask_code, .get_event_mask_desc = pfm_i386_p6_get_event_mask_desc, .get_cycle_event = pfm_i386_p6_get_cycle_event, .get_inst_retired_event = pfm_i386_p6_get_inst_retired }; /* Generic P6 processor support (not incl. Pentium M) */ pfm_pmu_support_t i386_p6_support={ .pmu_name = "Intel P6 Processor Family", .pmu_type = PFMLIB_I386_P6_PMU, .pme_count = PME_I386_PIII_EVENT_COUNT, .pmc_count = PMU_I386_P6_NUM_PERFSEL, .pmd_count = PMU_I386_P6_NUM_PERFCTR, .num_cnt = PMU_I386_P6_NUM_COUNTERS, .get_event_code = pfm_i386_p6_get_event_code, .get_event_name = pfm_i386_p6_get_event_name, .get_event_counters = pfm_i386_p6_get_event_counters, .dispatch_events = pfm_i386_p6_dispatch_events, .pmu_detect = pfm_i386_p6_detect_piii, .pmu_init = pfm_i386_p6_init_piii, .get_impl_pmcs = pfm_i386_p6_get_impl_perfsel, .get_impl_pmds = pfm_i386_p6_get_impl_perfctr, .get_impl_counters = pfm_i386_p6_get_impl_counters, .get_hw_counter_width = pfm_i386_p6_get_hw_counter_width, .get_event_desc = pfm_i386_p6_get_event_description, .get_num_event_masks = pfm_i386_p6_get_num_event_masks, .get_event_mask_name = pfm_i386_p6_get_event_mask_name, .get_event_mask_code = pfm_i386_p6_get_event_mask_code, .get_event_mask_desc = pfm_i386_p6_get_event_mask_desc, .get_cycle_event = pfm_i386_p6_get_cycle_event, .get_inst_retired_event = pfm_i386_p6_get_inst_retired }; pfm_pmu_support_t i386_ppro_support={ .pmu_name = "Intel Pentium Pro", .pmu_type = PFMLIB_INTEL_PPRO_PMU, .pme_count = PME_I386_PPRO_EVENT_COUNT, .pmc_count = PMU_I386_P6_NUM_PERFSEL, .pmd_count = PMU_I386_P6_NUM_PERFCTR, .num_cnt = PMU_I386_P6_NUM_COUNTERS, .get_event_code = pfm_i386_p6_get_event_code, .get_event_name = pfm_i386_p6_get_event_name, .get_event_counters = pfm_i386_p6_get_event_counters, .dispatch_events = pfm_i386_p6_dispatch_events, .pmu_detect = pfm_i386_p6_detect_ppro, .pmu_init = pfm_i386_p6_init_ppro, .get_impl_pmcs = pfm_i386_p6_get_impl_perfsel, .get_impl_pmds = pfm_i386_p6_get_impl_perfctr, .get_impl_counters = pfm_i386_p6_get_impl_counters, .get_hw_counter_width = pfm_i386_p6_get_hw_counter_width, .get_event_desc = pfm_i386_p6_get_event_description, .get_num_event_masks = pfm_i386_p6_get_num_event_masks, .get_event_mask_name = pfm_i386_p6_get_event_mask_name, .get_event_mask_code = pfm_i386_p6_get_event_mask_code, .get_event_mask_desc = pfm_i386_p6_get_event_mask_desc, .get_cycle_event = pfm_i386_p6_get_cycle_event, .get_inst_retired_event = pfm_i386_p6_get_inst_retired }; /* Pentium M support */ pfm_pmu_support_t i386_pm_support={ .pmu_name = "Intel Pentium M", .pmu_type = PFMLIB_I386_PM_PMU, .pme_count = PME_I386_PM_EVENT_COUNT, .pmc_count = PMU_I386_P6_NUM_PERFSEL, .pmd_count = PMU_I386_P6_NUM_PERFCTR, .num_cnt = PMU_I386_P6_NUM_COUNTERS, .get_event_code = pfm_i386_p6_get_event_code, .get_event_name = pfm_i386_p6_get_event_name, .get_event_counters = pfm_i386_p6_get_event_counters, .dispatch_events = pfm_i386_p6_dispatch_events, .pmu_detect = pfm_i386_p6_detect_pm, .pmu_init = pfm_i386_p6_init_pm, .get_impl_pmcs = pfm_i386_p6_get_impl_perfsel, .get_impl_pmds = pfm_i386_p6_get_impl_perfctr, .get_impl_counters = pfm_i386_p6_get_impl_counters, .get_hw_counter_width = pfm_i386_p6_get_hw_counter_width, .get_event_desc = pfm_i386_p6_get_event_description, .get_num_event_masks = pfm_i386_p6_get_num_event_masks, .get_event_mask_name = pfm_i386_p6_get_event_mask_name, .get_event_mask_code = pfm_i386_p6_get_event_mask_code, .get_event_mask_desc = pfm_i386_p6_get_event_mask_desc, .get_cycle_event = pfm_i386_p6_get_cycle_event, .get_inst_retired_event = pfm_i386_p6_get_inst_retired }; papi-5.5.1/src/libpfm-3.y/lib/pfmlib_montecito_priv.h0000644000307100002310000001274013013651450022437 0ustar yarkhangraduate/* * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #ifndef __PFMLIB_MONTECITO_PRIV_H__ #define __PFMLIB_MONTECITO_PRIV_H__ /* * Event type definitions * * The virtual events are not really defined in the specs but are an artifact used * to quickly and easily setup EAR and/or BTB. The event type encodes the exact feature * which must be configured in combination with a counting monitor. * For instance, DATA_EAR_CACHE_LAT4 is a virtual D-EAR cache event. If the user * requests this event, this will configure a counting monitor to count DATA_EAR_EVENTS * and PMC11 will be configured for cache mode. The latency is encoded in the umask, here * it would correspond to 4 cycles. * */ #define PFMLIB_MONT_EVENT_NORMAL 0x0 /* standard counter */ #define PFMLIB_MONT_EVENT_ETB 0x1 /* virtual event used with ETB configuration */ #define PFMLIB_MONT_EVENT_IEAR_TLB 0x2 /* virtual event used for I-EAR TLB configuration */ #define PFMLIB_MONT_EVENT_IEAR_CACHE 0x3 /* virtual event used for I-EAR cache configuration */ #define PFMLIB_MONT_EVENT_DEAR_TLB 0x4 /* virtual event used for D-EAR TLB configuration */ #define PFMLIB_MONT_EVENT_DEAR_CACHE 0x5 /* virtual event used for D-EAR cache configuration */ #define PFMLIB_MONT_EVENT_DEAR_ALAT 0x6 /* virtual event used for D-EAR ALAT configuration */ #define event_is_ear(e) ((e)->pme_type >= PFMLIB_MONT_EVENT_IEAR_TLB &&(e)->pme_type <= PFMLIB_MONT_EVENT_DEAR_ALAT) #define event_is_iear(e) ((e)->pme_type == PFMLIB_MONT_EVENT_IEAR_TLB || (e)->pme_type == PFMLIB_MONT_EVENT_IEAR_CACHE) #define event_is_dear(e) ((e)->pme_type >= PFMLIB_MONT_EVENT_DEAR_TLB && (e)->pme_type <= PFMLIB_MONT_EVENT_DEAR_ALAT) #define event_is_ear_cache(e) ((e)->pme_type == PFMLIB_MONT_EVENT_DEAR_CACHE || (e)->pme_type == PFMLIB_MONT_EVENT_IEAR_CACHE) #define event_is_ear_tlb(e) ((e)->pme_type == PFMLIB_MONT_EVENT_IEAR_TLB || (e)->pme_type == PFMLIB_MONT_EVENT_DEAR_TLB) #define event_is_ear_alat(e) ((e)->pme_type == PFMLIB_MONT_EVENT_DEAR_ALAT) #define event_is_etb(e) ((e)->pme_type == PFMLIB_MONT_EVENT_ETB) /* * Itanium encoding structure * (code must be first 8 bits) */ typedef struct { unsigned long pme_code:8; /* major event code */ unsigned long pme_type:3; /* see definitions above */ unsigned long pme_caf:2; /* Active, Floating, Causal, Self-Floating */ unsigned long pme_ig1:3; /* ignored */ unsigned long pme_umask:16; /* unit mask*/ unsigned long pme_ig:32; /* ignored */ } pme_mont_entry_code_t; typedef union { unsigned long pme_vcode; pme_mont_entry_code_t pme_mont_code; /* must not be larger than vcode */ } pme_mont_code_t; typedef union { unsigned long qual; /* generic qualifier */ struct { unsigned long pme_iar:1; /* instruction address range supported */ unsigned long pme_opm:1; /* opcode match supported */ unsigned long pme_dar:1; /* data address range supported */ unsigned long pme_all:1; /* supports all_thrd=1 */ unsigned long pme_mesi:1; /* event supports MESI */ unsigned long pme_res1:11; /* reserved */ unsigned long pme_group:3; /* event group */ unsigned long pme_set:4; /* event set*/ unsigned long pme_res2:41; /* reserved */ } pme_qual; } pme_mont_qualifiers_t; typedef struct { char *pme_name; pme_mont_code_t pme_entry_code; unsigned long pme_counters; /* supported counters */ unsigned int pme_maxincr; pme_mont_qualifiers_t pme_qualifiers; char *pme_desc; /* text description of the event */ } pme_mont_entry_t; /* * We embed the umask value into the event code. Because it really is * like a subevent. * pme_code: * - lower 16 bits: major event code * - upper 16 bits: unit mask */ #define pme_code pme_entry_code.pme_mont_code.pme_code #define pme_umask pme_entry_code.pme_mont_code.pme_umask #define pme_used pme_qualifiers.pme_qual_struct.pme_used #define pme_type pme_entry_code.pme_mont_code.pme_type #define pme_caf pme_entry_code.pme_mont_code.pme_caf #define event_opcm_ok(e) ((e)->pme_qualifiers.pme_qual.pme_opm==1) #define event_iarr_ok(e) ((e)->pme_qualifiers.pme_qual.pme_iar==1) #define event_darr_ok(e) ((e)->pme_qualifiers.pme_qual.pme_dar==1) #define event_all_ok(e) ((e)->pme_qualifiers.pme_qual.pme_all==1) #define event_mesi_ok(e) ((e)->pme_qualifiers.pme_qual.pme_mesi==1) #endif /* __PFMLIB_MONTECITO_PRIV_H__ */ papi-5.5.1/src/libpfm-3.y/lib/power7_events.h0000644000307100002310000142666013013651450020667 0ustar yarkhangraduate/****************************/ /* THIS IS OPEN SOURCE CODE */ /****************************/ #ifndef __POWER7_EVENTS_H__ #define __POWER7_EVENTS_H__ /* * File: power7_events.h * CVS: * Author: Corey Ashford * cjashfor@us.ibm.com * Mods: * * * (C) Copyright IBM Corporation, 2009. All Rights Reserved. * Contributed by Corey Ashford * * Note: This code was automatically generated and should not be modified by * hand. * */ #define POWER7_PME_PM_NEST_4 0 #define POWER7_PME_PM_IC_DEMAND_L2_BR_ALL 1 #define POWER7_PME_PM_PMC2_SAVED 2 #define POWER7_PME_PM_CMPLU_STALL_DFU 3 #define POWER7_PME_PM_VSU0_16FLOP 4 #define POWER7_PME_PM_NEST_3 5 #define POWER7_PME_PM_MRK_LSU_DERAT_MISS 6 #define POWER7_PME_PM_MRK_ST_CMPL 7 #define POWER7_PME_PM_L2_ST_DISP 8 #define POWER7_PME_PM_L2_CASTOUT_MOD 9 #define POWER7_PME_PM_ISEG 10 #define POWER7_PME_PM_MRK_INST_TIMEO 11 #define POWER7_PME_PM_L2_RCST_DISP_FAIL_ADDR 12 #define POWER7_PME_PM_LSU1_DC_PREF_STREAM_CONFIRM 13 #define POWER7_PME_PM_IERAT_WR_64K 14 #define POWER7_PME_PM_MRK_DTLB_MISS_16M 15 #define POWER7_PME_PM_IERAT_MISS 16 #define POWER7_PME_PM_MRK_PTEG_FROM_LMEM 17 #define POWER7_PME_PM_FLOP 18 #define POWER7_PME_PM_THRD_PRIO_4_5_CYC 19 #define POWER7_PME_PM_BR_PRED_TA 20 #define POWER7_PME_PM_CMPLU_STALL_FXU 21 #define POWER7_PME_PM_EXT_INT 22 #define POWER7_PME_PM_VSU_FSQRT_FDIV 23 #define POWER7_PME_PM_MRK_LD_MISS_EXPOSED_CYC 24 #define POWER7_PME_PM_LSU1_LDF 25 #define POWER7_PME_PM_IC_WRITE_ALL 26 #define POWER7_PME_PM_LSU0_SRQ_STFWD 27 #define POWER7_PME_PM_PTEG_FROM_RL2L3_MOD 28 #define POWER7_PME_PM_MRK_DATA_FROM_L31_SHR 29 #define POWER7_PME_PM_DATA_FROM_L21_MOD 30 #define POWER7_PME_PM_VSU1_SCAL_DOUBLE_ISSUED 31 #define POWER7_PME_PM_VSU0_8FLOP 32 #define POWER7_PME_PM_POWER_EVENT1 33 #define POWER7_PME_PM_DISP_CLB_HELD_BAL 34 #define POWER7_PME_PM_VSU1_2FLOP 35 #define POWER7_PME_PM_LWSYNC_HELD 36 #define POWER7_PME_PM_INST_FROM_L21_MOD 37 #define POWER7_PME_PM_IC_REQ_ALL 38 #define POWER7_PME_PM_DSLB_MISS 39 #define POWER7_PME_PM_L3_MISS 40 #define POWER7_PME_PM_LSU0_L1_PREF 41 #define POWER7_PME_PM_VSU_SCALAR_SINGLE_ISSUED 42 #define POWER7_PME_PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE 43 #define POWER7_PME_PM_L2_INST 44 #define POWER7_PME_PM_VSU0_FRSP 45 #define POWER7_PME_PM_FLUSH_DISP 46 #define POWER7_PME_PM_PTEG_FROM_L2MISS 47 #define POWER7_PME_PM_VSU1_DQ_ISSUED 48 #define POWER7_PME_PM_CMPLU_STALL_LSU 49 #define POWER7_PME_PM_MRK_DATA_FROM_DMEM 50 #define POWER7_PME_PM_LSU_FLUSH_ULD 51 #define POWER7_PME_PM_PTEG_FROM_LMEM 52 #define POWER7_PME_PM_MRK_DERAT_MISS_16M 53 #define POWER7_PME_PM_THRD_ALL_RUN_CYC 54 #define POWER7_PME_PM_MRK_STALL_CMPLU_CYC_COUNT 55 #define POWER7_PME_PM_DATA_FROM_DL2L3_MOD 56 #define POWER7_PME_PM_VSU_FRSP 57 #define POWER7_PME_PM_MRK_DATA_FROM_L21_MOD 58 #define POWER7_PME_PM_PMC1_OVERFLOW 59 #define POWER7_PME_PM_VSU0_SINGLE 60 #define POWER7_PME_PM_MRK_PTEG_FROM_L3MISS 61 #define POWER7_PME_PM_MRK_PTEG_FROM_L31_SHR 62 #define POWER7_PME_PM_VSU0_VECTOR_SP_ISSUED 63 #define POWER7_PME_PM_VSU1_FEST 64 #define POWER7_PME_PM_MRK_INST_DISP 65 #define POWER7_PME_PM_VSU0_COMPLEX_ISSUED 66 #define POWER7_PME_PM_LSU1_FLUSH_UST 67 #define POWER7_PME_PM_INST_CMPL 68 #define POWER7_PME_PM_FXU_IDLE 69 #define POWER7_PME_PM_LSU0_FLUSH_ULD 70 #define POWER7_PME_PM_MRK_DATA_FROM_DL2L3_MOD 71 #define POWER7_PME_PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC 72 #define POWER7_PME_PM_LSU1_REJECT_LMQ_FULL 73 #define POWER7_PME_PM_INST_PTEG_FROM_L21_MOD 74 #define POWER7_PME_PM_GCT_UTIL_3TO6_SLOT 75 #define POWER7_PME_PM_INST_FROM_RL2L3_MOD 76 #define POWER7_PME_PM_SHL_CREATED 77 #define POWER7_PME_PM_L2_ST_HIT 78 #define POWER7_PME_PM_DATA_FROM_DMEM 79 #define POWER7_PME_PM_L3_LD_MISS 80 #define POWER7_PME_PM_FXU1_BUSY_FXU0_IDLE 81 #define POWER7_PME_PM_DISP_CLB_HELD_RES 82 #define POWER7_PME_PM_L2_SN_SX_I_DONE 83 #define POWER7_PME_PM_GRP_CMPL 84 #define POWER7_PME_PM_BCPLUS8_CONV 85 #define POWER7_PME_PM_STCX_CMPL 86 #define POWER7_PME_PM_VSU0_2FLOP 87 #define POWER7_PME_PM_L3_PREF_MISS 88 #define POWER7_PME_PM_LSU_SRQ_SYNC_CYC 89 #define POWER7_PME_PM_LSU_REJECT_ERAT_MISS 90 #define POWER7_PME_PM_L1_ICACHE_MISS 91 #define POWER7_PME_PM_LSU1_FLUSH_SRQ 92 #define POWER7_PME_PM_LD_REF_L1_LSU0 93 #define POWER7_PME_PM_VSU0_FEST 94 #define POWER7_PME_PM_VSU_VECTOR_SINGLE_ISSUED 95 #define POWER7_PME_PM_FREQ_UP 96 #define POWER7_PME_PM_DATA_FROM_LMEM 97 #define POWER7_PME_PM_LSU1_LDX 98 #define POWER7_PME_PM_PMC3_OVERFLOW 99 #define POWER7_PME_PM_MRK_BR_MPRED 100 #define POWER7_PME_PM_SHL_MATCH 101 #define POWER7_PME_PM_MRK_BR_TAKEN 102 #define POWER7_PME_PM_ISLB_MISS 103 #define POWER7_PME_PM_CYC 104 #define POWER7_PME_PM_MRK_DATA_FROM_DRL2L3_MOD_CYC 105 #define POWER7_PME_PM_DISP_HELD_THERMAL 106 #define POWER7_PME_PM_INST_PTEG_FROM_RL2L3_SHR 107 #define POWER7_PME_PM_LSU1_SRQ_STFWD 108 #define POWER7_PME_PM_GCT_NOSLOT_BR_MPRED 109 #define POWER7_PME_PM_1PLUS_PPC_CMPL 110 #define POWER7_PME_PM_PTEG_FROM_DMEM 111 #define POWER7_PME_PM_VSU_2FLOP 112 #define POWER7_PME_PM_GCT_FULL_CYC 113 #define POWER7_PME_PM_MRK_DATA_FROM_L3_CYC 114 #define POWER7_PME_PM_LSU_SRQ_S0_ALLOC 115 #define POWER7_PME_PM_MRK_DERAT_MISS_4K 116 #define POWER7_PME_PM_BR_MPRED_TA 117 #define POWER7_PME_PM_INST_PTEG_FROM_L2MISS 118 #define POWER7_PME_PM_DPU_HELD_POWER 119 #define POWER7_PME_PM_RUN_INST_CMPL 120 #define POWER7_PME_PM_MRK_VSU_FIN 121 #define POWER7_PME_PM_LSU_SRQ_S0_VALID 122 #define POWER7_PME_PM_GCT_EMPTY_CYC 123 #define POWER7_PME_PM_IOPS_DISP 124 #define POWER7_PME_PM_RUN_SPURR 125 #define POWER7_PME_PM_PTEG_FROM_L21_MOD 126 #define POWER7_PME_PM_VSU0_1FLOP 127 #define POWER7_PME_PM_SNOOP_TLBIE 128 #define POWER7_PME_PM_DATA_FROM_L3MISS 129 #define POWER7_PME_PM_VSU_SINGLE 130 #define POWER7_PME_PM_DTLB_MISS_16G 131 #define POWER7_PME_PM_CMPLU_STALL_VECTOR 132 #define POWER7_PME_PM_FLUSH 133 #define POWER7_PME_PM_L2_LD_HIT 134 #define POWER7_PME_PM_NEST_2 135 #define POWER7_PME_PM_VSU1_1FLOP 136 #define POWER7_PME_PM_IC_PREF_REQ 137 #define POWER7_PME_PM_L3_LD_HIT 138 #define POWER7_PME_PM_GCT_NOSLOT_IC_MISS 139 #define POWER7_PME_PM_DISP_HELD 140 #define POWER7_PME_PM_L2_LD 141 #define POWER7_PME_PM_LSU_FLUSH_SRQ 142 #define POWER7_PME_PM_MRK_DATA_FROM_L31_MOD_CYC 143 #define POWER7_PME_PM_L2_RCST_BUSY_RC_FULL 144 #define POWER7_PME_PM_TB_BIT_TRANS 145 #define POWER7_PME_PM_THERMAL_MAX 146 #define POWER7_PME_PM_LSU1_FLUSH_ULD 147 #define POWER7_PME_PM_LSU1_REJECT_LHS 148 #define POWER7_PME_PM_LSU_LRQ_S0_ALLOC 149 #define POWER7_PME_PM_POWER_EVENT4 150 #define POWER7_PME_PM_DATA_FROM_L31_SHR 151 #define POWER7_PME_PM_BR_UNCOND 152 #define POWER7_PME_PM_LSU1_DC_PREF_STREAM_ALLOC 153 #define POWER7_PME_PM_PMC4_REWIND 154 #define POWER7_PME_PM_L2_RCLD_DISP 155 #define POWER7_PME_PM_THRD_PRIO_2_3_CYC 156 #define POWER7_PME_PM_MRK_PTEG_FROM_L2MISS 157 #define POWER7_PME_PM_IC_DEMAND_L2_BHT_REDIRECT 158 #define POWER7_PME_PM_LSU_DERAT_MISS 159 #define POWER7_PME_PM_IC_PREF_CANCEL_L2 160 #define POWER7_PME_PM_GCT_UTIL_7TO10_SLOT 161 #define POWER7_PME_PM_MRK_FIN_STALL_CYC_COUNT 162 #define POWER7_PME_PM_BR_PRED_CCACHE 163 #define POWER7_PME_PM_MRK_ST_CMPL_INT 164 #define POWER7_PME_PM_LSU_TWO_TABLEWALK_CYC 165 #define POWER7_PME_PM_MRK_DATA_FROM_L3MISS 166 #define POWER7_PME_PM_GCT_NOSLOT_CYC 167 #define POWER7_PME_PM_LSU_SET_MPRED 168 #define POWER7_PME_PM_FLUSH_DISP_TLBIE 169 #define POWER7_PME_PM_VSU1_FCONV 170 #define POWER7_PME_PM_NEST_1 171 #define POWER7_PME_PM_DERAT_MISS_16G 172 #define POWER7_PME_PM_INST_FROM_LMEM 173 #define POWER7_PME_PM_IC_DEMAND_L2_BR_REDIRECT 174 #define POWER7_PME_PM_CMPLU_STALL_SCALAR_LONG 175 #define POWER7_PME_PM_INST_PTEG_FROM_L2 176 #define POWER7_PME_PM_PTEG_FROM_L2 177 #define POWER7_PME_PM_MRK_DATA_FROM_L21_SHR_CYC 178 #define POWER7_PME_PM_MRK_DTLB_MISS_4K 179 #define POWER7_PME_PM_VSU0_FPSCR 180 #define POWER7_PME_PM_VSU1_VECT_DOUBLE_ISSUED 181 #define POWER7_PME_PM_MRK_PTEG_FROM_RL2L3_MOD 182 #define POWER7_PME_PM_L2_LD_MISS 183 #define POWER7_PME_PM_VMX_RESULT_SAT_1 184 #define POWER7_PME_PM_L1_PREF 185 #define POWER7_PME_PM_MRK_DATA_FROM_LMEM_CYC 186 #define POWER7_PME_PM_GRP_IC_MISS_NONSPEC 187 #define POWER7_PME_PM_SHL_MERGED 188 #define POWER7_PME_PM_DATA_FROM_L3 189 #define POWER7_PME_PM_LSU_FLUSH 190 #define POWER7_PME_PM_LSU_SRQ_SYNC_COUNT 191 #define POWER7_PME_PM_PMC2_OVERFLOW 192 #define POWER7_PME_PM_LSU_LDF 193 #define POWER7_PME_PM_POWER_EVENT3 194 #define POWER7_PME_PM_DISP_WT 195 #define POWER7_PME_PM_CMPLU_STALL_REJECT 196 #define POWER7_PME_PM_IC_BANK_CONFLICT 197 #define POWER7_PME_PM_BR_MPRED_CR_TA 198 #define POWER7_PME_PM_L2_INST_MISS 199 #define POWER7_PME_PM_CMPLU_STALL_ERAT_MISS 200 #define POWER7_PME_PM_MRK_LSU_FLUSH 201 #define POWER7_PME_PM_L2_LDST 202 #define POWER7_PME_PM_INST_FROM_L31_SHR 203 #define POWER7_PME_PM_VSU0_FIN 204 #define POWER7_PME_PM_LARX_LSU 205 #define POWER7_PME_PM_INST_FROM_RMEM 206 #define POWER7_PME_PM_DISP_CLB_HELD_TLBIE 207 #define POWER7_PME_PM_MRK_DATA_FROM_DMEM_CYC 208 #define POWER7_PME_PM_BR_PRED_CR 209 #define POWER7_PME_PM_LSU_REJECT 210 #define POWER7_PME_PM_CMPLU_STALL_END_GCT_NOSLOT 211 #define POWER7_PME_PM_LSU0_REJECT_LMQ_FULL 212 #define POWER7_PME_PM_VSU_FEST 213 #define POWER7_PME_PM_PTEG_FROM_L3 214 #define POWER7_PME_PM_POWER_EVENT2 215 #define POWER7_PME_PM_IC_PREF_CANCEL_PAGE 216 #define POWER7_PME_PM_VSU0_FSQRT_FDIV 217 #define POWER7_PME_PM_MRK_GRP_CMPL 218 #define POWER7_PME_PM_VSU0_SCAL_DOUBLE_ISSUED 219 #define POWER7_PME_PM_GRP_DISP 220 #define POWER7_PME_PM_LSU0_LDX 221 #define POWER7_PME_PM_DATA_FROM_L2 222 #define POWER7_PME_PM_MRK_DATA_FROM_RL2L3_MOD 223 #define POWER7_PME_PM_LD_REF_L1 224 #define POWER7_PME_PM_VSU0_VECT_DOUBLE_ISSUED 225 #define POWER7_PME_PM_VSU1_2FLOP_DOUBLE 226 #define POWER7_PME_PM_THRD_PRIO_6_7_CYC 227 #define POWER7_PME_PM_BR_MPRED_CR 228 #define POWER7_PME_PM_LD_MISS_L1 229 #define POWER7_PME_PM_DATA_FROM_RL2L3_MOD 230 #define POWER7_PME_PM_LSU_SRQ_FULL_CYC 231 #define POWER7_PME_PM_TABLEWALK_CYC 232 #define POWER7_PME_PM_MRK_PTEG_FROM_RMEM 233 #define POWER7_PME_PM_LSU_SRQ_STFWD 234 #define POWER7_PME_PM_INST_PTEG_FROM_RMEM 235 #define POWER7_PME_PM_FXU0_FIN 236 #define POWER7_PME_PM_PTEG_FROM_L31_MOD 237 #define POWER7_PME_PM_PMC5_OVERFLOW 238 #define POWER7_PME_PM_LD_REF_L1_LSU1 239 #define POWER7_PME_PM_INST_PTEG_FROM_L21_SHR 240 #define POWER7_PME_PM_CMPLU_STALL_THRD 241 #define POWER7_PME_PM_DATA_FROM_RMEM 242 #define POWER7_PME_PM_VSU0_SCAL_SINGLE_ISSUED 243 #define POWER7_PME_PM_BR_MPRED_LSTACK 244 #define POWER7_PME_PM_NEST_8 245 #define POWER7_PME_PM_MRK_DATA_FROM_RL2L3_MOD_CYC 246 #define POWER7_PME_PM_LSU0_FLUSH_UST 247 #define POWER7_PME_PM_LSU_NCST 248 #define POWER7_PME_PM_BR_TAKEN 249 #define POWER7_PME_PM_INST_PTEG_FROM_LMEM 250 #define POWER7_PME_PM_GCT_NOSLOT_BR_MPRED_IC_MISS 251 #define POWER7_PME_PM_DTLB_MISS_4K 252 #define POWER7_PME_PM_PMC4_SAVED 253 #define POWER7_PME_PM_VSU1_PERMUTE_ISSUED 254 #define POWER7_PME_PM_SLB_MISS 255 #define POWER7_PME_PM_LSU1_FLUSH_LRQ 256 #define POWER7_PME_PM_DTLB_MISS 257 #define POWER7_PME_PM_VSU1_FRSP 258 #define POWER7_PME_PM_VSU_VECTOR_DOUBLE_ISSUED 259 #define POWER7_PME_PM_L2_CASTOUT_SHR 260 #define POWER7_PME_PM_NEST_7 261 #define POWER7_PME_PM_DATA_FROM_DL2L3_SHR 262 #define POWER7_PME_PM_VSU1_STF 263 #define POWER7_PME_PM_ST_FIN 264 #define POWER7_PME_PM_PTEG_FROM_L21_SHR 265 #define POWER7_PME_PM_L2_LOC_GUESS_WRONG 266 #define POWER7_PME_PM_MRK_STCX_FAIL 267 #define POWER7_PME_PM_LSU0_REJECT_LHS 268 #define POWER7_PME_PM_IC_PREF_CANCEL_HIT 269 #define POWER7_PME_PM_L3_PREF_BUSY 270 #define POWER7_PME_PM_MRK_BRU_FIN 271 #define POWER7_PME_PM_LSU1_NCLD 272 #define POWER7_PME_PM_INST_PTEG_FROM_L31_MOD 273 #define POWER7_PME_PM_LSU_NCLD 274 #define POWER7_PME_PM_LSU_LDX 275 #define POWER7_PME_PM_L2_LOC_GUESS_CORRECT 276 #define POWER7_PME_PM_THRESH_TIMEO 277 #define POWER7_PME_PM_L3_PREF_ST 278 #define POWER7_PME_PM_DISP_CLB_HELD_SYNC 279 #define POWER7_PME_PM_VSU_SIMPLE_ISSUED 280 #define POWER7_PME_PM_VSU1_SINGLE 281 #define POWER7_PME_PM_DATA_TABLEWALK_CYC 282 #define POWER7_PME_PM_L2_RC_ST_DONE 283 #define POWER7_PME_PM_MRK_PTEG_FROM_L21_MOD 284 #define POWER7_PME_PM_LARX_LSU1 285 #define POWER7_PME_PM_MRK_DATA_FROM_RMEM 286 #define POWER7_PME_PM_DISP_CLB_HELD 287 #define POWER7_PME_PM_DERAT_MISS_4K 288 #define POWER7_PME_PM_L2_RCLD_DISP_FAIL_ADDR 289 #define POWER7_PME_PM_SEG_EXCEPTION 290 #define POWER7_PME_PM_FLUSH_DISP_SB 291 #define POWER7_PME_PM_L2_DC_INV 292 #define POWER7_PME_PM_PTEG_FROM_DL2L3_MOD 293 #define POWER7_PME_PM_DSEG 294 #define POWER7_PME_PM_BR_PRED_LSTACK 295 #define POWER7_PME_PM_VSU0_STF 296 #define POWER7_PME_PM_LSU_FX_FIN 297 #define POWER7_PME_PM_DERAT_MISS_16M 298 #define POWER7_PME_PM_MRK_PTEG_FROM_DL2L3_MOD 299 #define POWER7_PME_PM_INST_FROM_L3 300 #define POWER7_PME_PM_MRK_IFU_FIN 301 #define POWER7_PME_PM_ITLB_MISS 302 #define POWER7_PME_PM_VSU_STF 303 #define POWER7_PME_PM_LSU_FLUSH_UST 304 #define POWER7_PME_PM_L2_LDST_MISS 305 #define POWER7_PME_PM_FXU1_FIN 306 #define POWER7_PME_PM_SHL_DEALLOCATED 307 #define POWER7_PME_PM_L2_SN_M_WR_DONE 308 #define POWER7_PME_PM_LSU_REJECT_SET_MPRED 309 #define POWER7_PME_PM_L3_PREF_LD 310 #define POWER7_PME_PM_L2_SN_M_RD_DONE 311 #define POWER7_PME_PM_MRK_DERAT_MISS_16G 312 #define POWER7_PME_PM_VSU_FCONV 313 #define POWER7_PME_PM_ANY_THRD_RUN_CYC 314 #define POWER7_PME_PM_LSU_LMQ_FULL_CYC 315 #define POWER7_PME_PM_MRK_LSU_REJECT_LHS 316 #define POWER7_PME_PM_MRK_LD_MISS_L1_CYC 317 #define POWER7_PME_PM_MRK_DATA_FROM_L2_CYC 318 #define POWER7_PME_PM_INST_IMC_MATCH_DISP 319 #define POWER7_PME_PM_MRK_DATA_FROM_RMEM_CYC 320 #define POWER7_PME_PM_VSU0_SIMPLE_ISSUED 321 #define POWER7_PME_PM_CMPLU_STALL_DIV 322 #define POWER7_PME_PM_MRK_PTEG_FROM_RL2L3_SHR 323 #define POWER7_PME_PM_VSU_FMA_DOUBLE 324 #define POWER7_PME_PM_VSU_4FLOP 325 #define POWER7_PME_PM_VSU1_FIN 326 #define POWER7_PME_PM_INST_PTEG_FROM_RL2L3_MOD 327 #define POWER7_PME_PM_RUN_CYC 328 #define POWER7_PME_PM_PTEG_FROM_RMEM 329 #define POWER7_PME_PM_LSU_LRQ_S0_VALID 330 #define POWER7_PME_PM_LSU0_LDF 331 #define POWER7_PME_PM_FLUSH_COMPLETION 332 #define POWER7_PME_PM_ST_MISS_L1 333 #define POWER7_PME_PM_L2_NODE_PUMP 334 #define POWER7_PME_PM_INST_FROM_DL2L3_SHR 335 #define POWER7_PME_PM_MRK_STALL_CMPLU_CYC 336 #define POWER7_PME_PM_VSU1_DENORM 337 #define POWER7_PME_PM_MRK_DATA_FROM_L31_SHR_CYC 338 #define POWER7_PME_PM_GCT_USAGE_1TO2_SLOT 339 #define POWER7_PME_PM_NEST_6 340 #define POWER7_PME_PM_INST_FROM_L3MISS 341 #define POWER7_PME_PM_EE_OFF_EXT_INT 342 #define POWER7_PME_PM_INST_PTEG_FROM_DMEM 343 #define POWER7_PME_PM_INST_FROM_DL2L3_MOD 344 #define POWER7_PME_PM_PMC6_OVERFLOW 345 #define POWER7_PME_PM_VSU_2FLOP_DOUBLE 346 #define POWER7_PME_PM_TLB_MISS 347 #define POWER7_PME_PM_FXU_BUSY 348 #define POWER7_PME_PM_L2_RCLD_DISP_FAIL_OTHER 349 #define POWER7_PME_PM_LSU_REJECT_LMQ_FULL 350 #define POWER7_PME_PM_IC_RELOAD_SHR 351 #define POWER7_PME_PM_GRP_MRK 352 #define POWER7_PME_PM_MRK_ST_NEST 353 #define POWER7_PME_PM_VSU1_FSQRT_FDIV 354 #define POWER7_PME_PM_LSU0_FLUSH_LRQ 355 #define POWER7_PME_PM_LARX_LSU0 356 #define POWER7_PME_PM_IBUF_FULL_CYC 357 #define POWER7_PME_PM_MRK_DATA_FROM_DL2L3_SHR_CYC 358 #define POWER7_PME_PM_LSU_DC_PREF_STREAM_ALLOC 359 #define POWER7_PME_PM_GRP_MRK_CYC 360 #define POWER7_PME_PM_MRK_DATA_FROM_RL2L3_SHR_CYC 361 #define POWER7_PME_PM_L2_GLOB_GUESS_CORRECT 362 #define POWER7_PME_PM_LSU_REJECT_LHS 363 #define POWER7_PME_PM_MRK_DATA_FROM_LMEM 364 #define POWER7_PME_PM_INST_PTEG_FROM_L3 365 #define POWER7_PME_PM_FREQ_DOWN 366 #define POWER7_PME_PM_INST_FROM_RL2L3_SHR 367 #define POWER7_PME_PM_MRK_INST_ISSUED 368 #define POWER7_PME_PM_PTEG_FROM_L3MISS 369 #define POWER7_PME_PM_RUN_PURR 370 #define POWER7_PME_PM_MRK_DATA_FROM_L3 371 #define POWER7_PME_PM_MRK_GRP_IC_MISS 372 #define POWER7_PME_PM_CMPLU_STALL_DCACHE_MISS 373 #define POWER7_PME_PM_PTEG_FROM_RL2L3_SHR 374 #define POWER7_PME_PM_LSU_FLUSH_LRQ 375 #define POWER7_PME_PM_MRK_DERAT_MISS_64K 376 #define POWER7_PME_PM_INST_PTEG_FROM_DL2L3_MOD 377 #define POWER7_PME_PM_L2_ST_MISS 378 #define POWER7_PME_PM_LWSYNC 379 #define POWER7_PME_PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE 380 #define POWER7_PME_PM_MRK_PTEG_FROM_L21_SHR 381 #define POWER7_PME_PM_MRK_LSU_FLUSH_LRQ 382 #define POWER7_PME_PM_INST_IMC_MATCH_CMPL 383 #define POWER7_PME_PM_MRK_INST_FIN 384 #define POWER7_PME_PM_INST_FROM_L31_MOD 385 #define POWER7_PME_PM_MRK_DTLB_MISS_64K 386 #define POWER7_PME_PM_LSU_FIN 387 #define POWER7_PME_PM_MRK_LSU_REJECT 388 #define POWER7_PME_PM_L2_CO_FAIL_BUSY 389 #define POWER7_PME_PM_DATA_FROM_L31_MOD 390 #define POWER7_PME_PM_THERMAL_WARN 391 #define POWER7_PME_PM_VSU0_4FLOP 392 #define POWER7_PME_PM_BR_MPRED_CCACHE 393 #define POWER7_PME_PM_L1_DEMAND_WRITE 394 #define POWER7_PME_PM_FLUSH_BR_MPRED 395 #define POWER7_PME_PM_MRK_DTLB_MISS_16G 396 #define POWER7_PME_PM_MRK_PTEG_FROM_DMEM 397 #define POWER7_PME_PM_L2_RCST_DISP 398 #define POWER7_PME_PM_CMPLU_STALL 399 #define POWER7_PME_PM_LSU_PARTIAL_CDF 400 #define POWER7_PME_PM_DISP_CLB_HELD_SB 401 #define POWER7_PME_PM_VSU0_FMA_DOUBLE 402 #define POWER7_PME_PM_FXU0_BUSY_FXU1_IDLE 403 #define POWER7_PME_PM_IC_DEMAND_CYC 404 #define POWER7_PME_PM_MRK_DATA_FROM_L21_SHR 405 #define POWER7_PME_PM_MRK_LSU_FLUSH_UST 406 #define POWER7_PME_PM_INST_PTEG_FROM_L3MISS 407 #define POWER7_PME_PM_VSU_DENORM 408 #define POWER7_PME_PM_MRK_LSU_PARTIAL_CDF 409 #define POWER7_PME_PM_INST_FROM_L21_SHR 410 #define POWER7_PME_PM_IC_PREF_WRITE 411 #define POWER7_PME_PM_BR_PRED 412 #define POWER7_PME_PM_INST_FROM_DMEM 413 #define POWER7_PME_PM_IC_PREF_CANCEL_ALL 414 #define POWER7_PME_PM_LSU_DC_PREF_STREAM_CONFIRM 415 #define POWER7_PME_PM_MRK_LSU_FLUSH_SRQ 416 #define POWER7_PME_PM_MRK_FIN_STALL_CYC 417 #define POWER7_PME_PM_GCT_UTIL_11PLUS_SLOT 418 #define POWER7_PME_PM_L2_RCST_DISP_FAIL_OTHER 419 #define POWER7_PME_PM_VSU1_DD_ISSUED 420 #define POWER7_PME_PM_PTEG_FROM_L31_SHR 421 #define POWER7_PME_PM_DATA_FROM_L21_SHR 422 #define POWER7_PME_PM_LSU0_NCLD 423 #define POWER7_PME_PM_VSU1_4FLOP 424 #define POWER7_PME_PM_VSU1_8FLOP 425 #define POWER7_PME_PM_VSU_8FLOP 426 #define POWER7_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 427 #define POWER7_PME_PM_DTLB_MISS_64K 428 #define POWER7_PME_PM_THRD_CONC_RUN_INST 429 #define POWER7_PME_PM_MRK_PTEG_FROM_L2 430 #define POWER7_PME_PM_VSU_FIN 431 #define POWER7_PME_PM_MRK_DATA_FROM_L31_MOD 432 #define POWER7_PME_PM_THRD_PRIO_0_1_CYC 433 #define POWER7_PME_PM_DERAT_MISS_64K 434 #define POWER7_PME_PM_PMC2_REWIND 435 #define POWER7_PME_PM_INST_FROM_L2 436 #define POWER7_PME_PM_GRP_BR_MPRED_NONSPEC 437 #define POWER7_PME_PM_INST_DISP 438 #define POWER7_PME_PM_LSU0_DC_PREF_STREAM_CONFIRM 439 #define POWER7_PME_PM_L1_DCACHE_RELOAD_VALID 440 #define POWER7_PME_PM_VSU_SCALAR_DOUBLE_ISSUED 441 #define POWER7_PME_PM_L3_PREF_HIT 442 #define POWER7_PME_PM_MRK_PTEG_FROM_L31_MOD 443 #define POWER7_PME_PM_MRK_FXU_FIN 444 #define POWER7_PME_PM_PMC4_OVERFLOW 445 #define POWER7_PME_PM_MRK_PTEG_FROM_L3 446 #define POWER7_PME_PM_LSU0_LMQ_LHR_MERGE 447 #define POWER7_PME_PM_BTAC_HIT 448 #define POWER7_PME_PM_IERAT_XLATE_WR_16MPLUS 449 #define POWER7_PME_PM_L3_RD_BUSY 450 #define POWER7_PME_PM_INST_FROM_L2MISS 451 #define POWER7_PME_PM_LSU0_DC_PREF_STREAM_ALLOC 452 #define POWER7_PME_PM_L2_ST 453 #define POWER7_PME_PM_VSU0_DENORM 454 #define POWER7_PME_PM_MRK_DATA_FROM_DL2L3_SHR 455 #define POWER7_PME_PM_BR_PRED_CR_TA 456 #define POWER7_PME_PM_VSU0_FCONV 457 #define POWER7_PME_PM_MRK_LSU_FLUSH_ULD 458 #define POWER7_PME_PM_BTAC_MISS 459 #define POWER7_PME_PM_MRK_LD_MISS_EXPOSED_CYC_COUNT 460 #define POWER7_PME_PM_MRK_DATA_FROM_L2 461 #define POWER7_PME_PM_VSU_FMA 462 #define POWER7_PME_PM_LSU0_FLUSH_SRQ 463 #define POWER7_PME_PM_LSU1_L1_PREF 464 #define POWER7_PME_PM_IOPS_CMPL 465 #define POWER7_PME_PM_L2_SYS_PUMP 466 #define POWER7_PME_PM_L2_RCLD_BUSY_RC_FULL 467 #define POWER7_PME_PM_BCPLUS8_RSLV_TAKEN 468 #define POWER7_PME_PM_NEST_5 469 #define POWER7_PME_PM_LSU_LMQ_S0_ALLOC 470 #define POWER7_PME_PM_FLUSH_DISP_SYNC 471 #define POWER7_PME_PM_L2_IC_INV 472 #define POWER7_PME_PM_MRK_DATA_FROM_L21_MOD_CYC 473 #define POWER7_PME_PM_L3_PREF_LDST 474 #define POWER7_PME_PM_LSU_SRQ_EMPTY_CYC 475 #define POWER7_PME_PM_LSU_LMQ_S0_VALID 476 #define POWER7_PME_PM_FLUSH_PARTIAL 477 #define POWER7_PME_PM_VSU1_FMA_DOUBLE 478 #define POWER7_PME_PM_1PLUS_PPC_DISP 479 #define POWER7_PME_PM_DATA_FROM_L2MISS 480 #define POWER7_PME_PM_SUSPENDED 481 #define POWER7_PME_PM_VSU0_FMA 482 #define POWER7_PME_PM_CMPLU_STALL_SCALAR 483 #define POWER7_PME_PM_STCX_FAIL 484 #define POWER7_PME_PM_VSU0_FSQRT_FDIV_DOUBLE 485 #define POWER7_PME_PM_DC_PREF_DST 486 #define POWER7_PME_PM_VSU1_SCAL_SINGLE_ISSUED 487 #define POWER7_PME_PM_L3_HIT 488 #define POWER7_PME_PM_L2_GLOB_GUESS_WRONG 489 #define POWER7_PME_PM_MRK_DFU_FIN 490 #define POWER7_PME_PM_INST_FROM_L1 491 #define POWER7_PME_PM_BRU_FIN 492 #define POWER7_PME_PM_IC_DEMAND_REQ 493 #define POWER7_PME_PM_VSU1_FSQRT_FDIV_DOUBLE 494 #define POWER7_PME_PM_VSU1_FMA 495 #define POWER7_PME_PM_MRK_LD_MISS_L1 496 #define POWER7_PME_PM_VSU0_2FLOP_DOUBLE 497 #define POWER7_PME_PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM 498 #define POWER7_PME_PM_INST_PTEG_FROM_L31_SHR 499 #define POWER7_PME_PM_MRK_LSU_REJECT_ERAT_MISS 500 #define POWER7_PME_PM_MRK_DATA_FROM_L2MISS 501 #define POWER7_PME_PM_DATA_FROM_RL2L3_SHR 502 #define POWER7_PME_PM_INST_FROM_PREF 503 #define POWER7_PME_PM_VSU1_SQ 504 #define POWER7_PME_PM_L2_LD_DISP 505 #define POWER7_PME_PM_L2_DISP_ALL 506 #define POWER7_PME_PM_THRD_GRP_CMPL_BOTH_CYC 507 #define POWER7_PME_PM_VSU_FSQRT_FDIV_DOUBLE 508 #define POWER7_PME_PM_BR_MPRED 509 #define POWER7_PME_PM_VSU_1FLOP 510 #define POWER7_PME_PM_HV_CYC 511 #define POWER7_PME_PM_MRK_DATA_FROM_RL2L3_SHR 512 #define POWER7_PME_PM_DTLB_MISS_16M 513 #define POWER7_PME_PM_MRK_LSU_FIN 514 #define POWER7_PME_PM_LSU1_LMQ_LHR_MERGE 515 #define POWER7_PME_PM_IFU_FIN 516 static const int power7_event_ids[][POWER7_NUM_EVENT_COUNTERS] = { [ POWER7_PME_PM_NEST_4 ] = { 213, 213, 208, 203, -1, -1 }, [ POWER7_PME_PM_IC_DEMAND_L2_BR_ALL ] = { 65, 62, 60, 60, -1, -1 }, [ POWER7_PME_PM_PMC2_SAVED ] = { 218, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_CMPLU_STALL_DFU ] = { -1, 18, -1, -1, -1, -1 }, [ POWER7_PME_PM_VSU0_16FLOP ] = { 269, 267, 261, 255, -1, -1 }, [ POWER7_PME_PM_NEST_3 ] = { 212, 212, 207, 202, -1, -1 }, [ POWER7_PME_PM_MRK_LSU_DERAT_MISS ] = { -1, -1, 188, -1, -1, -1 }, [ POWER7_PME_PM_MRK_ST_CMPL ] = { 208, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_L2_ST_DISP ] = { -1, -1, -1, 95, -1, -1 }, [ POWER7_PME_PM_L2_CASTOUT_MOD ] = { 99, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_ISEG ] = { 95, 89, 88, 85, -1, -1 }, [ POWER7_PME_PM_MRK_INST_TIMEO ] = { -1, -1, -1, 184, -1, -1 }, [ POWER7_PME_PM_L2_RCST_DISP_FAIL_ADDR ] = { -1, -1, 100, -1, -1, -1 }, [ POWER7_PME_PM_LSU1_DC_PREF_STREAM_CONFIRM ] = { 167, 161, 161, 154, -1, -1 }, [ POWER7_PME_PM_IERAT_WR_64K ] = { 78, 74, 72, 72, -1, -1 }, [ POWER7_PME_PM_MRK_DTLB_MISS_16M ] = { -1, -1, -1, 181, -1, -1 }, [ POWER7_PME_PM_IERAT_MISS ] = { 77, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_MRK_PTEG_FROM_LMEM ] = { -1, -1, -1, 198, -1, -1 }, [ POWER7_PME_PM_FLOP ] = { 42, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_THRD_PRIO_4_5_CYC ] = { 244, 242, 237, 231, -1, -1 }, [ POWER7_PME_PM_BR_PRED_TA ] = { 14, 12, 13, 14, -1, -1 }, [ POWER7_PME_PM_CMPLU_STALL_FXU ] = { -1, 19, -1, -1, -1, -1 }, [ POWER7_PME_PM_EXT_INT ] = { -1, 43, -1, -1, -1, -1 }, [ POWER7_PME_PM_VSU_FSQRT_FDIV ] = { 260, 258, 252, 246, -1, -1 }, [ POWER7_PME_PM_MRK_LD_MISS_EXPOSED_CYC ] = { 196, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_LSU1_LDF ] = { 174, 168, 168, 161, -1, -1 }, [ POWER7_PME_PM_IC_WRITE_ALL ] = { 76, 73, 71, 71, -1, -1 }, [ POWER7_PME_PM_LSU0_SRQ_STFWD ] = { 165, 159, 159, 152, -1, -1 }, [ POWER7_PME_PM_PTEG_FROM_RL2L3_MOD ] = { 225, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_MRK_DATA_FROM_L31_SHR ] = { 188, 184, -1, -1, -1, -1 }, [ POWER7_PME_PM_DATA_FROM_L21_MOD ] = { -1, -1, 20, -1, -1, -1 }, [ POWER7_PME_PM_VSU1_SCAL_DOUBLE_ISSUED ] = { 310, 308, 302, 296, -1, -1 }, [ POWER7_PME_PM_VSU0_8FLOP ] = { 274, 272, 266, 260, -1, -1 }, [ POWER7_PME_PM_POWER_EVENT1 ] = { 222, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_DISP_CLB_HELD_BAL ] = { 32, 33, 29, 31, -1, -1 }, [ POWER7_PME_PM_VSU1_2FLOP ] = { 294, 292, 286, 280, -1, -1 }, [ POWER7_PME_PM_LWSYNC_HELD ] = { 182, 176, 176, 169, -1, -1 }, [ POWER7_PME_PM_INST_FROM_L21_MOD ] = { -1, -1, 79, -1, -1, -1 }, [ POWER7_PME_PM_IC_REQ_ALL ] = { 75, 72, 70, 70, -1, -1 }, [ POWER7_PME_PM_DSLB_MISS ] = { 39, 40, 37, 37, -1, -1 }, [ POWER7_PME_PM_L3_MISS ] = { 110, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_LSU0_L1_PREF ] = { 158, 152, 152, 145, -1, -1 }, [ POWER7_PME_PM_VSU_SCALAR_SINGLE_ISSUED ] = { 263, 261, 255, 249, -1, -1 }, [ POWER7_PME_PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE ] = { 168, 162, 162, 155, -1, -1 }, [ POWER7_PME_PM_L2_INST ] = { -1, -1, 93, -1, -1, -1 }, [ POWER7_PME_PM_VSU0_FRSP ] = { 283, 281, 275, 269, -1, -1 }, [ POWER7_PME_PM_FLUSH_DISP ] = { 44, 45, 43, 42, -1, -1 }, [ POWER7_PME_PM_PTEG_FROM_L2MISS ] = { -1, -1, -1, 212, -1, -1 }, [ POWER7_PME_PM_VSU1_DQ_ISSUED ] = { 300, 298, 292, 286, -1, -1 }, [ POWER7_PME_PM_CMPLU_STALL_LSU ] = { -1, 20, -1, -1, -1, -1 }, [ POWER7_PME_PM_MRK_DATA_FROM_DMEM ] = { 184, 179, -1, -1, -1, -1 }, [ POWER7_PME_PM_LSU_FLUSH_ULD ] = { 126, 121, 122, 115, -1, -1 }, [ POWER7_PME_PM_PTEG_FROM_LMEM ] = { -1, -1, -1, 213, -1, -1 }, [ POWER7_PME_PM_MRK_DERAT_MISS_16M ] = { -1, -1, 184, -1, -1, -1 }, [ POWER7_PME_PM_THRD_ALL_RUN_CYC ] = { -1, 239, -1, -1, -1, -1 }, [ POWER7_PME_PM_MRK_STALL_CMPLU_CYC_COUNT ] = { -1, -1, 202, -1, -1, -1 }, [ POWER7_PME_PM_DATA_FROM_DL2L3_MOD ] = { -1, -1, 18, 24, -1, -1 }, [ POWER7_PME_PM_VSU_FRSP ] = { 259, 257, 251, 245, -1, -1 }, [ POWER7_PME_PM_MRK_DATA_FROM_L21_MOD ] = { -1, -1, 180, -1, -1, -1 }, [ POWER7_PME_PM_PMC1_OVERFLOW ] = { -1, 218, -1, -1, -1, -1 }, [ POWER7_PME_PM_VSU0_SINGLE ] = { 289, 287, 281, 275, -1, -1 }, [ POWER7_PME_PM_MRK_PTEG_FROM_L3MISS ] = { -1, 206, -1, -1, -1, -1 }, [ POWER7_PME_PM_MRK_PTEG_FROM_L31_SHR ] = { -1, 205, -1, -1, -1, -1 }, [ POWER7_PME_PM_VSU0_VECTOR_SP_ISSUED ] = { 292, 290, 284, 278, -1, -1 }, [ POWER7_PME_PM_VSU1_FEST ] = { 302, 300, 294, 288, -1, -1 }, [ POWER7_PME_PM_MRK_INST_DISP ] = { -1, 194, -1, -1, -1, -1 }, [ POWER7_PME_PM_VSU0_COMPLEX_ISSUED ] = { 275, 273, 267, 261, -1, -1 }, [ POWER7_PME_PM_LSU1_FLUSH_UST ] = { 172, 166, 166, 159, -1, -1 }, [ POWER7_PME_PM_INST_CMPL ] = { 80, 76, 74, 75, -1, -1 }, [ POWER7_PME_PM_FXU_IDLE ] = { 49, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_LSU0_FLUSH_ULD ] = { 156, 150, 150, 143, -1, -1 }, [ POWER7_PME_PM_MRK_DATA_FROM_DL2L3_MOD ] = { -1, -1, 178, 170, -1, -1 }, [ POWER7_PME_PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC ] = { -1, -1, 129, -1, -1, -1 }, [ POWER7_PME_PM_LSU1_REJECT_LMQ_FULL ] = { 179, 173, 173, 166, -1, -1 }, [ POWER7_PME_PM_INST_PTEG_FROM_L21_MOD ] = { -1, -1, 84, -1, -1, -1 }, [ POWER7_PME_PM_GCT_UTIL_3TO6_SLOT ] = { 55, 56, 53, 55, -1, -1 }, [ POWER7_PME_PM_INST_FROM_RL2L3_MOD ] = { 88, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_SHL_CREATED ] = { 228, 227, 222, 217, -1, -1 }, [ POWER7_PME_PM_L2_ST_HIT ] = { -1, -1, -1, 96, -1, -1 }, [ POWER7_PME_PM_DATA_FROM_DMEM ] = { 22, 24, -1, -1, -1, -1 }, [ POWER7_PME_PM_L3_LD_MISS ] = { -1, 104, -1, -1, -1, -1 }, [ POWER7_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { -1, -1, -1, 48, -1, -1 }, [ POWER7_PME_PM_DISP_CLB_HELD_RES ] = { 33, 34, 30, 32, -1, -1 }, [ POWER7_PME_PM_L2_SN_SX_I_DONE ] = { -1, -1, 101, -1, -1, -1 }, [ POWER7_PME_PM_GRP_CMPL ] = { -1, -1, 55, -1, -1, -1 }, [ POWER7_PME_PM_BCPLUS8_CONV ] = { 2, 0, 1, 1, -1, -1 }, [ POWER7_PME_PM_STCX_CMPL ] = { 234, 234, 229, 223, -1, -1 }, [ POWER7_PME_PM_VSU0_2FLOP ] = { 271, 269, 263, 257, -1, -1 }, [ POWER7_PME_PM_L3_PREF_MISS ] = { -1, -1, 106, -1, -1, -1 }, [ POWER7_PME_PM_LSU_SRQ_SYNC_CYC ] = { 149, 143, 143, 136, -1, -1 }, [ POWER7_PME_PM_LSU_REJECT_ERAT_MISS ] = { -1, 134, -1, -1, -1, -1 }, [ POWER7_PME_PM_L1_ICACHE_MISS ] = { -1, 92, -1, -1, -1, -1 }, [ POWER7_PME_PM_LSU1_FLUSH_SRQ ] = { 170, 164, 164, 157, -1, -1 }, [ POWER7_PME_PM_LD_REF_L1_LSU0 ] = { 118, 112, 112, 107, -1, -1 }, [ POWER7_PME_PM_VSU0_FEST ] = { 278, 276, 270, 264, -1, -1 }, [ POWER7_PME_PM_VSU_VECTOR_SINGLE_ISSUED ] = { 268, 266, 260, 254, -1, -1 }, [ POWER7_PME_PM_FREQ_UP ] = { -1, -1, -1, 47, -1, -1 }, [ POWER7_PME_PM_DATA_FROM_LMEM ] = { -1, -1, 23, 27, -1, -1 }, [ POWER7_PME_PM_LSU1_LDX ] = { 175, 169, 169, 162, -1, -1 }, [ POWER7_PME_PM_PMC3_OVERFLOW ] = { -1, -1, -1, 208, -1, -1 }, [ POWER7_PME_PM_MRK_BR_MPRED ] = { -1, -1, 177, -1, -1, -1 }, [ POWER7_PME_PM_SHL_MATCH ] = { 230, 229, 224, 219, -1, -1 }, [ POWER7_PME_PM_MRK_BR_TAKEN ] = { 183, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_ISLB_MISS ] = { 96, 90, 89, 86, -1, -1 }, [ POWER7_PME_PM_CYC ] = { 21, 23, 17, 23, -1, -1 }, [ POWER7_PME_PM_MRK_DATA_FROM_DRL2L3_MOD_CYC ] = { -1, -1, -1, 171, -1, -1 }, [ POWER7_PME_PM_DISP_HELD_THERMAL ] = { -1, -1, 34, -1, -1, -1 }, [ POWER7_PME_PM_INST_PTEG_FROM_RL2L3_SHR ] = { -1, 88, 85, -1, -1, -1 }, [ POWER7_PME_PM_LSU1_SRQ_STFWD ] = { 180, 174, 174, 167, -1, -1 }, [ POWER7_PME_PM_GCT_NOSLOT_BR_MPRED ] = { -1, -1, -1, 51, -1, -1 }, [ POWER7_PME_PM_1PLUS_PPC_CMPL ] = { 0, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_PTEG_FROM_DMEM ] = { -1, 220, -1, -1, -1, -1 }, [ POWER7_PME_PM_VSU_2FLOP ] = { 249, 247, 241, 235, -1, -1 }, [ POWER7_PME_PM_GCT_FULL_CYC ] = { 51, 52, 50, 50, -1, -1 }, [ POWER7_PME_PM_MRK_DATA_FROM_L3_CYC ] = { -1, -1, -1, 175, -1, -1 }, [ POWER7_PME_PM_LSU_SRQ_S0_ALLOC ] = { 145, 139, 139, 132, -1, -1 }, [ POWER7_PME_PM_MRK_DERAT_MISS_4K ] = { 191, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_BR_MPRED_TA ] = { 8, 6, 7, 8, -1, -1 }, [ POWER7_PME_PM_INST_PTEG_FROM_L2MISS ] = { -1, -1, -1, 83, -1, -1 }, [ POWER7_PME_PM_DPU_HELD_POWER ] = { -1, 38, -1, -1, -1, -1 }, [ POWER7_PME_PM_RUN_INST_CMPL ] = { -1, -1, -1, 214, 0, -1 }, [ POWER7_PME_PM_MRK_VSU_FIN ] = { -1, -1, 204, -1, -1, -1 }, [ POWER7_PME_PM_LSU_SRQ_S0_VALID ] = { 146, 140, 140, 133, -1, -1 }, [ POWER7_PME_PM_GCT_EMPTY_CYC ] = { -1, 51, -1, -1, -1, -1 }, [ POWER7_PME_PM_IOPS_DISP ] = { -1, -1, 87, -1, -1, -1 }, [ POWER7_PME_PM_RUN_SPURR ] = { 226, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_PTEG_FROM_L21_MOD ] = { -1, -1, 218, -1, -1, -1 }, [ POWER7_PME_PM_VSU0_1FLOP ] = { 270, 268, 262, 256, -1, -1 }, [ POWER7_PME_PM_SNOOP_TLBIE ] = { 233, 232, 227, 222, -1, -1 }, [ POWER7_PME_PM_DATA_FROM_L3MISS ] = { -1, 28, 22, -1, -1, -1 }, [ POWER7_PME_PM_VSU_SINGLE ] = { 265, 263, 257, 251, -1, -1 }, [ POWER7_PME_PM_DTLB_MISS_16G ] = { 40, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_CMPLU_STALL_VECTOR ] = { -1, 22, -1, -1, -1, -1 }, [ POWER7_PME_PM_FLUSH ] = { -1, -1, -1, 40, -1, -1 }, [ POWER7_PME_PM_L2_LD_HIT ] = { -1, -1, 96, -1, -1, -1 }, [ POWER7_PME_PM_NEST_2 ] = { 211, 211, 206, 201, -1, -1 }, [ POWER7_PME_PM_VSU1_1FLOP ] = { 293, 291, 285, 279, -1, -1 }, [ POWER7_PME_PM_IC_PREF_REQ ] = { 72, 69, 67, 67, -1, -1 }, [ POWER7_PME_PM_L3_LD_HIT ] = { -1, 103, -1, -1, -1, -1 }, [ POWER7_PME_PM_GCT_NOSLOT_IC_MISS ] = { -1, 53, -1, -1, -1, -1 }, [ POWER7_PME_PM_DISP_HELD ] = { 37, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_L2_LD ] = { 103, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_LSU_FLUSH_SRQ ] = { 125, 120, 121, 114, -1, -1 }, [ POWER7_PME_PM_MRK_DATA_FROM_L31_MOD_CYC ] = { -1, -1, -1, 176, -1, -1 }, [ POWER7_PME_PM_L2_RCST_BUSY_RC_FULL ] = { -1, 101, -1, -1, -1, -1 }, [ POWER7_PME_PM_TB_BIT_TRANS ] = { -1, -1, 232, -1, -1, -1 }, [ POWER7_PME_PM_THERMAL_MAX ] = { -1, -1, -1, 226, -1, -1 }, [ POWER7_PME_PM_LSU1_FLUSH_ULD ] = { 171, 165, 165, 158, -1, -1 }, [ POWER7_PME_PM_LSU1_REJECT_LHS ] = { 178, 172, 172, 165, -1, -1 }, [ POWER7_PME_PM_LSU_LRQ_S0_ALLOC ] = { 134, 129, 130, 122, -1, -1 }, [ POWER7_PME_PM_POWER_EVENT4 ] = { -1, -1, -1, 209, -1, -1 }, [ POWER7_PME_PM_DATA_FROM_L31_SHR ] = { 26, 27, -1, -1, -1, -1 }, [ POWER7_PME_PM_BR_UNCOND ] = { 15, 14, 14, 15, -1, -1 }, [ POWER7_PME_PM_LSU1_DC_PREF_STREAM_ALLOC ] = { 166, 160, 160, 153, -1, -1 }, [ POWER7_PME_PM_PMC4_REWIND ] = { 220, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_L2_RCLD_DISP ] = { 106, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_THRD_PRIO_2_3_CYC ] = { 243, 241, 236, 230, -1, -1 }, [ POWER7_PME_PM_MRK_PTEG_FROM_L2MISS ] = { -1, -1, -1, 197, -1, -1 }, [ POWER7_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = { 64, 61, 59, 59, -1, -1 }, [ POWER7_PME_PM_LSU_DERAT_MISS ] = { -1, 117, 117, -1, -1, -1 }, [ POWER7_PME_PM_IC_PREF_CANCEL_L2 ] = { 70, 67, 65, 65, -1, -1 }, [ POWER7_PME_PM_GCT_UTIL_7TO10_SLOT ] = { 56, 57, 54, 56, -1, -1 }, [ POWER7_PME_PM_MRK_FIN_STALL_CYC_COUNT ] = { 194, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_BR_PRED_CCACHE ] = { 10, 8, 9, 10, -1, -1 }, [ POWER7_PME_PM_MRK_ST_CMPL_INT ] = { -1, -1, 200, -1, -1, -1 }, [ POWER7_PME_PM_LSU_TWO_TABLEWALK_CYC ] = { 150, 144, 144, 137, -1, -1 }, [ POWER7_PME_PM_MRK_DATA_FROM_L3MISS ] = { -1, 186, -1, -1, -1, -1 }, [ POWER7_PME_PM_GCT_NOSLOT_CYC ] = { 52, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_LSU_SET_MPRED ] = { 143, 138, 138, 130, -1, -1 }, [ POWER7_PME_PM_FLUSH_DISP_TLBIE ] = { 47, 48, 46, 45, -1, -1 }, [ POWER7_PME_PM_VSU1_FCONV ] = { 301, 299, 293, 287, -1, -1 }, [ POWER7_PME_PM_NEST_1 ] = { 210, 210, 205, 200, -1, -1 }, [ POWER7_PME_PM_DERAT_MISS_16G ] = { -1, -1, -1, 29, -1, -1 }, [ POWER7_PME_PM_INST_FROM_LMEM ] = { -1, -1, 81, 80, -1, -1 }, [ POWER7_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = { 66, 63, 61, 61, -1, -1 }, [ POWER7_PME_PM_CMPLU_STALL_SCALAR_LONG ] = { -1, 21, -1, -1, -1, -1 }, [ POWER7_PME_PM_INST_PTEG_FROM_L2 ] = { 91, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_PTEG_FROM_L2 ] = { 223, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_MRK_DATA_FROM_L21_SHR_CYC ] = { -1, 182, -1, -1, -1, -1 }, [ POWER7_PME_PM_MRK_DTLB_MISS_4K ] = { -1, 192, -1, -1, -1, -1 }, [ POWER7_PME_PM_VSU0_FPSCR ] = { 282, 280, 274, 268, -1, -1 }, [ POWER7_PME_PM_VSU1_VECT_DOUBLE_ISSUED ] = { 315, 313, 307, 301, -1, -1 }, [ POWER7_PME_PM_MRK_PTEG_FROM_RL2L3_MOD ] = { 207, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_L2_LD_MISS ] = { -1, 97, -1, -1, -1, -1 }, [ POWER7_PME_PM_VMX_RESULT_SAT_1 ] = { 247, 245, 239, 233, -1, -1 }, [ POWER7_PME_PM_L1_PREF ] = { 98, 93, 92, 89, -1, -1 }, [ POWER7_PME_PM_MRK_DATA_FROM_LMEM_CYC ] = { -1, 187, -1, -1, -1, -1 }, [ POWER7_PME_PM_GRP_IC_MISS_NONSPEC ] = { 58, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_SHL_MERGED ] = { 231, 230, 225, 220, -1, -1 }, [ POWER7_PME_PM_DATA_FROM_L3 ] = { 24, 26, -1, -1, -1, -1 }, [ POWER7_PME_PM_LSU_FLUSH ] = { 123, 118, 119, 112, -1, -1 }, [ POWER7_PME_PM_LSU_SRQ_SYNC_COUNT ] = { 148, 142, 142, 135, -1, -1 }, [ POWER7_PME_PM_PMC2_OVERFLOW ] = { -1, -1, 213, -1, -1, -1 }, [ POWER7_PME_PM_LSU_LDF ] = { 129, 123, 124, 117, -1, -1 }, [ POWER7_PME_PM_POWER_EVENT3 ] = { -1, -1, 217, -1, -1, -1 }, [ POWER7_PME_PM_DISP_WT ] = { -1, -1, 35, -1, -1, -1 }, [ POWER7_PME_PM_CMPLU_STALL_REJECT ] = { -1, -1, -1, 21, -1, -1 }, [ POWER7_PME_PM_IC_BANK_CONFLICT ] = { 62, 60, 58, 58, -1, -1 }, [ POWER7_PME_PM_BR_MPRED_CR_TA ] = { 6, 4, 5, 6, -1, -1 }, [ POWER7_PME_PM_L2_INST_MISS ] = { -1, -1, 94, -1, -1, -1 }, [ POWER7_PME_PM_CMPLU_STALL_ERAT_MISS ] = { -1, -1, -1, 20, -1, -1 }, [ POWER7_PME_PM_MRK_LSU_FLUSH ] = { 198, 196, 189, 187, -1, -1 }, [ POWER7_PME_PM_L2_LDST ] = { 104, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_INST_FROM_L31_SHR ] = { 86, 81, -1, -1, -1, -1 }, [ POWER7_PME_PM_VSU0_FIN ] = { 279, 277, 271, 265, -1, -1 }, [ POWER7_PME_PM_LARX_LSU ] = { 114, 108, 108, 102, -1, -1 }, [ POWER7_PME_PM_INST_FROM_RMEM ] = { -1, -1, 82, -1, -1, -1 }, [ POWER7_PME_PM_DISP_CLB_HELD_TLBIE ] = { 36, 37, 33, 35, -1, -1 }, [ POWER7_PME_PM_MRK_DATA_FROM_DMEM_CYC ] = { -1, 180, -1, -1, -1, -1 }, [ POWER7_PME_PM_BR_PRED_CR ] = { 11, 9, 10, 11, -1, -1 }, [ POWER7_PME_PM_LSU_REJECT ] = { 139, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_CMPLU_STALL_END_GCT_NOSLOT ] = { 19, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_LSU0_REJECT_LMQ_FULL ] = { 164, 158, 158, 151, -1, -1 }, [ POWER7_PME_PM_VSU_FEST ] = { 255, 253, 247, 241, -1, -1 }, [ POWER7_PME_PM_PTEG_FROM_L3 ] = { -1, 221, -1, -1, -1, -1 }, [ POWER7_PME_PM_POWER_EVENT2 ] = { -1, 219, -1, -1, -1, -1 }, [ POWER7_PME_PM_IC_PREF_CANCEL_PAGE ] = { 71, 68, 66, 66, -1, -1 }, [ POWER7_PME_PM_VSU0_FSQRT_FDIV ] = { 284, 282, 276, 270, -1, -1 }, [ POWER7_PME_PM_MRK_GRP_CMPL ] = { -1, -1, -1, 182, -1, -1 }, [ POWER7_PME_PM_VSU0_SCAL_DOUBLE_ISSUED ] = { 286, 284, 278, 272, -1, -1 }, [ POWER7_PME_PM_GRP_DISP ] = { -1, -1, 56, -1, -1, -1 }, [ POWER7_PME_PM_LSU0_LDX ] = { 160, 154, 154, 147, -1, -1 }, [ POWER7_PME_PM_DATA_FROM_L2 ] = { 23, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_MRK_DATA_FROM_RL2L3_MOD ] = { 189, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_LD_REF_L1 ] = { 117, 111, 111, 106, -1, -1 }, [ POWER7_PME_PM_VSU0_VECT_DOUBLE_ISSUED ] = { 291, 289, 283, 277, -1, -1 }, [ POWER7_PME_PM_VSU1_2FLOP_DOUBLE ] = { 295, 293, 287, 281, -1, -1 }, [ POWER7_PME_PM_THRD_PRIO_6_7_CYC ] = { 245, 243, 238, 232, -1, -1 }, [ POWER7_PME_PM_BR_MPRED_CR ] = { 5, 3, 4, 5, -1, -1 }, [ POWER7_PME_PM_LD_MISS_L1 ] = { -1, -1, -1, 105, -1, -1 }, [ POWER7_PME_PM_DATA_FROM_RL2L3_MOD ] = { 27, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_LSU_SRQ_FULL_CYC ] = { 144, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_TABLEWALK_CYC ] = { 237, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_MRK_PTEG_FROM_RMEM ] = { -1, -1, 199, -1, -1, -1 }, [ POWER7_PME_PM_LSU_SRQ_STFWD ] = { 147, 141, 141, 134, -1, -1 }, [ POWER7_PME_PM_INST_PTEG_FROM_RMEM ] = { -1, -1, 86, -1, -1, -1 }, [ POWER7_PME_PM_FXU0_FIN ] = { 50, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_PTEG_FROM_L31_MOD ] = { 224, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_PMC5_OVERFLOW ] = { 221, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_LD_REF_L1_LSU1 ] = { 119, 113, 113, 108, -1, -1 }, [ POWER7_PME_PM_INST_PTEG_FROM_L21_SHR ] = { -1, -1, -1, 82, -1, -1 }, [ POWER7_PME_PM_CMPLU_STALL_THRD ] = { 20, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_DATA_FROM_RMEM ] = { -1, -1, 24, -1, -1, -1 }, [ POWER7_PME_PM_VSU0_SCAL_SINGLE_ISSUED ] = { 287, 285, 279, 273, -1, -1 }, [ POWER7_PME_PM_BR_MPRED_LSTACK ] = { 7, 5, 6, 7, -1, -1 }, [ POWER7_PME_PM_NEST_8 ] = { 217, 217, 212, 207, -1, -1 }, [ POWER7_PME_PM_MRK_DATA_FROM_RL2L3_MOD_CYC ] = { -1, -1, -1, 178, -1, -1 }, [ POWER7_PME_PM_LSU0_FLUSH_UST ] = { 157, 151, 151, 144, -1, -1 }, [ POWER7_PME_PM_LSU_NCST ] = { 137, 132, 133, 125, -1, -1 }, [ POWER7_PME_PM_BR_TAKEN ] = { -1, 13, -1, -1, -1, -1 }, [ POWER7_PME_PM_INST_PTEG_FROM_LMEM ] = { -1, -1, -1, 84, -1, -1 }, [ POWER7_PME_PM_GCT_NOSLOT_BR_MPRED_IC_MISS ] = { -1, -1, -1, 52, -1, -1 }, [ POWER7_PME_PM_DTLB_MISS_4K ] = { -1, 41, -1, -1, -1, -1 }, [ POWER7_PME_PM_PMC4_SAVED ] = { -1, -1, 215, -1, -1, -1 }, [ POWER7_PME_PM_VSU1_PERMUTE_ISSUED ] = { 309, 307, 301, 295, -1, -1 }, [ POWER7_PME_PM_SLB_MISS ] = { 232, 231, 226, 221, -1, -1 }, [ POWER7_PME_PM_LSU1_FLUSH_LRQ ] = { 169, 163, 163, 156, -1, -1 }, [ POWER7_PME_PM_DTLB_MISS ] = { -1, -1, 38, -1, -1, -1 }, [ POWER7_PME_PM_VSU1_FRSP ] = { 306, 304, 298, 292, -1, -1 }, [ POWER7_PME_PM_VSU_VECTOR_DOUBLE_ISSUED ] = { 267, 265, 259, 253, -1, -1 }, [ POWER7_PME_PM_L2_CASTOUT_SHR ] = { 100, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_NEST_7 ] = { 216, 216, 211, 206, -1, -1 }, [ POWER7_PME_PM_DATA_FROM_DL2L3_SHR ] = { -1, -1, 19, -1, -1, -1 }, [ POWER7_PME_PM_VSU1_STF ] = { 314, 312, 306, 300, -1, -1 }, [ POWER7_PME_PM_ST_FIN ] = { -1, 233, -1, -1, -1, -1 }, [ POWER7_PME_PM_PTEG_FROM_L21_SHR ] = { -1, -1, -1, 211, -1, -1 }, [ POWER7_PME_PM_L2_LOC_GUESS_WRONG ] = { -1, 99, -1, -1, -1, -1 }, [ POWER7_PME_PM_MRK_STCX_FAIL ] = { 209, 209, 203, 199, -1, -1 }, [ POWER7_PME_PM_LSU0_REJECT_LHS ] = { 163, 157, 157, 150, -1, -1 }, [ POWER7_PME_PM_IC_PREF_CANCEL_HIT ] = { 69, 66, 64, 64, -1, -1 }, [ POWER7_PME_PM_L3_PREF_BUSY ] = { -1, -1, -1, 97, -1, -1 }, [ POWER7_PME_PM_MRK_BRU_FIN ] = { -1, 177, -1, -1, -1, -1 }, [ POWER7_PME_PM_LSU1_NCLD ] = { 177, 171, 171, 164, -1, -1 }, [ POWER7_PME_PM_INST_PTEG_FROM_L31_MOD ] = { 92, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_LSU_NCLD ] = { 136, 131, 132, 124, -1, -1 }, [ POWER7_PME_PM_LSU_LDX ] = { 130, 124, 125, 118, -1, -1 }, [ POWER7_PME_PM_L2_LOC_GUESS_CORRECT ] = { 105, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_THRESH_TIMEO ] = { 246, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_L3_PREF_ST ] = { 113, 107, 107, 100, -1, -1 }, [ POWER7_PME_PM_DISP_CLB_HELD_SYNC ] = { 35, 36, 32, 34, -1, -1 }, [ POWER7_PME_PM_VSU_SIMPLE_ISSUED ] = { 264, 262, 256, 250, -1, -1 }, [ POWER7_PME_PM_VSU1_SINGLE ] = { 312, 310, 304, 298, -1, -1 }, [ POWER7_PME_PM_DATA_TABLEWALK_CYC ] = { -1, -1, 25, -1, -1, -1 }, [ POWER7_PME_PM_L2_RC_ST_DONE ] = { -1, -1, 98, -1, -1, -1 }, [ POWER7_PME_PM_MRK_PTEG_FROM_L21_MOD ] = { -1, -1, 197, -1, -1, -1 }, [ POWER7_PME_PM_LARX_LSU1 ] = { 116, 110, 110, 104, -1, -1 }, [ POWER7_PME_PM_MRK_DATA_FROM_RMEM ] = { -1, -1, 183, -1, -1, -1 }, [ POWER7_PME_PM_DISP_CLB_HELD ] = { 31, 32, 28, 30, -1, -1 }, [ POWER7_PME_PM_DERAT_MISS_4K ] = { 30, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_L2_RCLD_DISP_FAIL_ADDR ] = { 107, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_SEG_EXCEPTION ] = { 227, 226, 221, 216, -1, -1 }, [ POWER7_PME_PM_FLUSH_DISP_SB ] = { 45, 46, 44, 43, -1, -1 }, [ POWER7_PME_PM_L2_DC_INV ] = { -1, 94, -1, -1, -1, -1 }, [ POWER7_PME_PM_PTEG_FROM_DL2L3_MOD ] = { -1, -1, -1, 210, -1, -1 }, [ POWER7_PME_PM_DSEG ] = { 38, 39, 36, 36, -1, -1 }, [ POWER7_PME_PM_BR_PRED_LSTACK ] = { 13, 11, 12, 13, -1, -1 }, [ POWER7_PME_PM_VSU0_STF ] = { 290, 288, 282, 276, -1, -1 }, [ POWER7_PME_PM_LSU_FX_FIN ] = { 128, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_DERAT_MISS_16M ] = { -1, -1, 27, -1, -1, -1 }, [ POWER7_PME_PM_MRK_PTEG_FROM_DL2L3_MOD ] = { -1, -1, -1, 195, -1, -1 }, [ POWER7_PME_PM_INST_FROM_L3 ] = { 84, 80, -1, -1, -1, -1 }, [ POWER7_PME_PM_MRK_IFU_FIN ] = { -1, -1, 186, -1, -1, -1 }, [ POWER7_PME_PM_ITLB_MISS ] = { -1, -1, -1, 87, -1, -1 }, [ POWER7_PME_PM_VSU_STF ] = { 266, 264, 258, 252, -1, -1 }, [ POWER7_PME_PM_LSU_FLUSH_UST ] = { 127, 122, 123, 116, -1, -1 }, [ POWER7_PME_PM_L2_LDST_MISS ] = { -1, 98, -1, -1, -1, -1 }, [ POWER7_PME_PM_FXU1_FIN ] = { -1, -1, -1, 49, -1, -1 }, [ POWER7_PME_PM_SHL_DEALLOCATED ] = { 229, 228, 223, 218, -1, -1 }, [ POWER7_PME_PM_L2_SN_M_WR_DONE ] = { -1, -1, -1, 94, -1, -1 }, [ POWER7_PME_PM_LSU_REJECT_SET_MPRED ] = { 142, 137, 137, 129, -1, -1 }, [ POWER7_PME_PM_L3_PREF_LD ] = { 111, 105, 104, 98, -1, -1 }, [ POWER7_PME_PM_L2_SN_M_RD_DONE ] = { -1, -1, -1, 93, -1, -1 }, [ POWER7_PME_PM_MRK_DERAT_MISS_16G ] = { -1, -1, -1, 180, -1, -1 }, [ POWER7_PME_PM_VSU_FCONV ] = { 254, 252, 246, 240, -1, -1 }, [ POWER7_PME_PM_ANY_THRD_RUN_CYC ] = { 1, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_LSU_LMQ_FULL_CYC ] = { 131, 125, 126, 119, -1, -1 }, [ POWER7_PME_PM_MRK_LSU_REJECT_LHS ] = { 204, 202, 196, 194, -1, -1 }, [ POWER7_PME_PM_MRK_LD_MISS_L1_CYC ] = { -1, -1, -1, 185, -1, -1 }, [ POWER7_PME_PM_MRK_DATA_FROM_L2_CYC ] = { -1, 181, -1, -1, -1, -1 }, [ POWER7_PME_PM_INST_IMC_MATCH_DISP ] = { -1, -1, 83, -1, -1, -1 }, [ POWER7_PME_PM_MRK_DATA_FROM_RMEM_CYC ] = { -1, -1, -1, 179, -1, -1 }, [ POWER7_PME_PM_VSU0_SIMPLE_ISSUED ] = { 288, 286, 280, 274, -1, -1 }, [ POWER7_PME_PM_CMPLU_STALL_DIV ] = { -1, -1, -1, 19, -1, -1 }, [ POWER7_PME_PM_MRK_PTEG_FROM_RL2L3_SHR ] = { -1, 207, 198, -1, -1, -1 }, [ POWER7_PME_PM_VSU_FMA_DOUBLE ] = { 258, 256, 250, 244, -1, -1 }, [ POWER7_PME_PM_VSU_4FLOP ] = { 251, 249, 243, 237, -1, -1 }, [ POWER7_PME_PM_VSU1_FIN ] = { 303, 301, 295, 289, -1, -1 }, [ POWER7_PME_PM_INST_PTEG_FROM_RL2L3_MOD ] = { 93, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_RUN_CYC ] = { -1, 225, -1, -1, -1, 0 }, [ POWER7_PME_PM_PTEG_FROM_RMEM ] = { -1, -1, 220, -1, -1, -1 }, [ POWER7_PME_PM_LSU_LRQ_S0_VALID ] = { 135, 130, 131, 123, -1, -1 }, [ POWER7_PME_PM_LSU0_LDF ] = { 159, 153, 153, 146, -1, -1 }, [ POWER7_PME_PM_FLUSH_COMPLETION ] = { -1, -1, 42, -1, -1, -1 }, [ POWER7_PME_PM_ST_MISS_L1 ] = { -1, -1, 228, -1, -1, -1 }, [ POWER7_PME_PM_L2_NODE_PUMP ] = { -1, -1, 97, -1, -1, -1 }, [ POWER7_PME_PM_INST_FROM_DL2L3_SHR ] = { -1, -1, 77, -1, -1, -1 }, [ POWER7_PME_PM_MRK_STALL_CMPLU_CYC ] = { -1, -1, 201, -1, -1, -1 }, [ POWER7_PME_PM_VSU1_DENORM ] = { 299, 297, 291, 285, -1, -1 }, [ POWER7_PME_PM_MRK_DATA_FROM_L31_SHR_CYC ] = { -1, 185, -1, -1, -1, -1 }, [ POWER7_PME_PM_GCT_USAGE_1TO2_SLOT ] = { 53, 54, 51, 53, -1, -1 }, [ POWER7_PME_PM_NEST_6 ] = { 215, 215, 210, 205, -1, -1 }, [ POWER7_PME_PM_INST_FROM_L3MISS ] = { -1, 82, -1, -1, -1, -1 }, [ POWER7_PME_PM_EE_OFF_EXT_INT ] = { 41, 42, 40, 39, -1, -1 }, [ POWER7_PME_PM_INST_PTEG_FROM_DMEM ] = { -1, 84, -1, -1, -1, -1 }, [ POWER7_PME_PM_INST_FROM_DL2L3_MOD ] = { -1, -1, 76, 76, -1, -1 }, [ POWER7_PME_PM_PMC6_OVERFLOW ] = { -1, -1, 216, -1, -1, -1 }, [ POWER7_PME_PM_VSU_2FLOP_DOUBLE ] = { 250, 248, 242, 236, -1, -1 }, [ POWER7_PME_PM_TLB_MISS ] = { -1, 244, -1, -1, -1, -1 }, [ POWER7_PME_PM_FXU_BUSY ] = { -1, 50, -1, -1, -1, -1 }, [ POWER7_PME_PM_L2_RCLD_DISP_FAIL_OTHER ] = { -1, 100, -1, -1, -1, -1 }, [ POWER7_PME_PM_LSU_REJECT_LMQ_FULL ] = { 141, 136, 136, 128, -1, -1 }, [ POWER7_PME_PM_IC_RELOAD_SHR ] = { 74, 71, 69, 69, -1, -1 }, [ POWER7_PME_PM_GRP_MRK ] = { 59, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_MRK_ST_NEST ] = { -1, 208, -1, -1, -1, -1 }, [ POWER7_PME_PM_VSU1_FSQRT_FDIV ] = { 307, 305, 299, 293, -1, -1 }, [ POWER7_PME_PM_LSU0_FLUSH_LRQ ] = { 154, 148, 148, 141, -1, -1 }, [ POWER7_PME_PM_LARX_LSU0 ] = { 115, 109, 109, 103, -1, -1 }, [ POWER7_PME_PM_IBUF_FULL_CYC ] = { 61, 59, 57, 57, -1, -1 }, [ POWER7_PME_PM_MRK_DATA_FROM_DL2L3_SHR_CYC ] = { -1, 178, -1, -1, -1, -1 }, [ POWER7_PME_PM_LSU_DC_PREF_STREAM_ALLOC ] = { 120, 114, 114, 109, -1, -1 }, [ POWER7_PME_PM_GRP_MRK_CYC ] = { 60, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_MRK_DATA_FROM_RL2L3_SHR_CYC ] = { -1, 189, -1, -1, -1, -1 }, [ POWER7_PME_PM_L2_GLOB_GUESS_CORRECT ] = { 102, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_LSU_REJECT_LHS ] = { 140, 135, 135, 127, -1, -1 }, [ POWER7_PME_PM_MRK_DATA_FROM_LMEM ] = { -1, -1, 182, 177, -1, -1 }, [ POWER7_PME_PM_INST_PTEG_FROM_L3 ] = { -1, 85, -1, -1, -1, -1 }, [ POWER7_PME_PM_FREQ_DOWN ] = { -1, -1, 48, -1, -1, -1 }, [ POWER7_PME_PM_INST_FROM_RL2L3_SHR ] = { 89, 83, -1, -1, -1, -1 }, [ POWER7_PME_PM_MRK_INST_ISSUED ] = { 195, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_PTEG_FROM_L3MISS ] = { -1, 223, -1, -1, -1, -1 }, [ POWER7_PME_PM_RUN_PURR ] = { -1, -1, -1, 215, -1, -1 }, [ POWER7_PME_PM_MRK_DATA_FROM_L3 ] = { 186, 183, -1, -1, -1, -1 }, [ POWER7_PME_PM_MRK_GRP_IC_MISS ] = { -1, -1, -1, 183, -1, -1 }, [ POWER7_PME_PM_CMPLU_STALL_DCACHE_MISS ] = { -1, 17, -1, -1, -1, -1 }, [ POWER7_PME_PM_PTEG_FROM_RL2L3_SHR ] = { -1, 224, 219, -1, -1, -1 }, [ POWER7_PME_PM_LSU_FLUSH_LRQ ] = { 124, 119, 120, 113, -1, -1 }, [ POWER7_PME_PM_MRK_DERAT_MISS_64K ] = { -1, 190, -1, -1, -1, -1 }, [ POWER7_PME_PM_INST_PTEG_FROM_DL2L3_MOD ] = { -1, -1, -1, 81, -1, -1 }, [ POWER7_PME_PM_L2_ST_MISS ] = { -1, 102, -1, -1, -1, -1 }, [ POWER7_PME_PM_LWSYNC ] = { 181, 175, 175, 168, -1, -1 }, [ POWER7_PME_PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE ] = { 153, 147, 147, 140, -1, -1 }, [ POWER7_PME_PM_MRK_PTEG_FROM_L21_SHR ] = { -1, -1, -1, 196, -1, -1 }, [ POWER7_PME_PM_MRK_LSU_FLUSH_LRQ ] = { 199, 197, 190, 188, -1, -1 }, [ POWER7_PME_PM_INST_IMC_MATCH_CMPL ] = { 90, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_MRK_INST_FIN ] = { -1, -1, 187, -1, -1, -1 }, [ POWER7_PME_PM_INST_FROM_L31_MOD ] = { 85, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_MRK_DTLB_MISS_64K ] = { -1, -1, 185, -1, -1, -1 }, [ POWER7_PME_PM_LSU_FIN ] = { -1, -1, 118, -1, -1, -1 }, [ POWER7_PME_PM_MRK_LSU_REJECT ] = { -1, -1, -1, 193, -1, -1 }, [ POWER7_PME_PM_L2_CO_FAIL_BUSY ] = { 101, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_DATA_FROM_L31_MOD ] = { 25, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_THERMAL_WARN ] = { 238, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_VSU0_4FLOP ] = { 273, 271, 265, 259, -1, -1 }, [ POWER7_PME_PM_BR_MPRED_CCACHE ] = { 4, 2, 3, 4, -1, -1 }, [ POWER7_PME_PM_L1_DEMAND_WRITE ] = { 97, 91, 91, 88, -1, -1 }, [ POWER7_PME_PM_FLUSH_BR_MPRED ] = { 43, 44, 41, 41, -1, -1 }, [ POWER7_PME_PM_MRK_DTLB_MISS_16G ] = { 192, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_MRK_PTEG_FROM_DMEM ] = { -1, 203, -1, -1, -1, -1 }, [ POWER7_PME_PM_L2_RCST_DISP ] = { -1, -1, 99, -1, -1, -1 }, [ POWER7_PME_PM_CMPLU_STALL ] = { -1, -1, -1, 18, -1, -1 }, [ POWER7_PME_PM_LSU_PARTIAL_CDF ] = { 138, 133, 134, 126, -1, -1 }, [ POWER7_PME_PM_DISP_CLB_HELD_SB ] = { 34, 35, 31, 33, -1, -1 }, [ POWER7_PME_PM_VSU0_FMA_DOUBLE ] = { 281, 279, 273, 267, -1, -1 }, [ POWER7_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { -1, -1, 49, -1, -1, -1 }, [ POWER7_PME_PM_IC_DEMAND_CYC ] = { 63, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_MRK_DATA_FROM_L21_SHR ] = { -1, -1, 181, 173, -1, -1 }, [ POWER7_PME_PM_MRK_LSU_FLUSH_UST ] = { 202, 200, 193, 191, -1, -1 }, [ POWER7_PME_PM_INST_PTEG_FROM_L3MISS ] = { -1, 87, -1, -1, -1, -1 }, [ POWER7_PME_PM_VSU_DENORM ] = { 253, 251, 245, 239, -1, -1 }, [ POWER7_PME_PM_MRK_LSU_PARTIAL_CDF ] = { 203, 201, 194, 192, -1, -1 }, [ POWER7_PME_PM_INST_FROM_L21_SHR ] = { -1, -1, 80, 78, -1, -1 }, [ POWER7_PME_PM_IC_PREF_WRITE ] = { 73, 70, 68, 68, -1, -1 }, [ POWER7_PME_PM_BR_PRED ] = { 9, 7, 8, 9, -1, -1 }, [ POWER7_PME_PM_INST_FROM_DMEM ] = { 81, 78, -1, -1, -1, -1 }, [ POWER7_PME_PM_IC_PREF_CANCEL_ALL ] = { 68, 65, 63, 63, -1, -1 }, [ POWER7_PME_PM_LSU_DC_PREF_STREAM_CONFIRM ] = { 121, 115, 115, 110, -1, -1 }, [ POWER7_PME_PM_MRK_LSU_FLUSH_SRQ ] = { 200, 198, 191, 189, -1, -1 }, [ POWER7_PME_PM_MRK_FIN_STALL_CYC ] = { 193, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_GCT_UTIL_11PLUS_SLOT ] = { 54, 55, 52, 54, -1, -1 }, [ POWER7_PME_PM_L2_RCST_DISP_FAIL_OTHER ] = { -1, -1, -1, 92, -1, -1 }, [ POWER7_PME_PM_VSU1_DD_ISSUED ] = { 298, 296, 290, 284, -1, -1 }, [ POWER7_PME_PM_PTEG_FROM_L31_SHR ] = { -1, 222, -1, -1, -1, -1 }, [ POWER7_PME_PM_DATA_FROM_L21_SHR ] = { -1, -1, 21, 25, -1, -1 }, [ POWER7_PME_PM_LSU0_NCLD ] = { 162, 156, 156, 149, -1, -1 }, [ POWER7_PME_PM_VSU1_4FLOP ] = { 296, 294, 288, 282, -1, -1 }, [ POWER7_PME_PM_VSU1_8FLOP ] = { 297, 295, 289, 283, -1, -1 }, [ POWER7_PME_PM_VSU_8FLOP ] = { 252, 250, 244, 238, -1, -1 }, [ POWER7_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { -1, 128, -1, -1, -1, -1 }, [ POWER7_PME_PM_DTLB_MISS_64K ] = { -1, -1, 39, -1, -1, -1 }, [ POWER7_PME_PM_THRD_CONC_RUN_INST ] = { -1, -1, 234, -1, -1, -1 }, [ POWER7_PME_PM_MRK_PTEG_FROM_L2 ] = { 205, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_VSU_FIN ] = { 256, 254, 248, 242, -1, -1 }, [ POWER7_PME_PM_MRK_DATA_FROM_L31_MOD ] = { 187, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_THRD_PRIO_0_1_CYC ] = { 242, 240, 235, 229, -1, -1 }, [ POWER7_PME_PM_DERAT_MISS_64K ] = { -1, 31, -1, -1, -1, -1 }, [ POWER7_PME_PM_PMC2_REWIND ] = { -1, -1, 214, -1, -1, -1 }, [ POWER7_PME_PM_INST_FROM_L2 ] = { 83, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_GRP_BR_MPRED_NONSPEC ] = { 57, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_INST_DISP ] = { -1, 77, 75, -1, -1, -1 }, [ POWER7_PME_PM_LSU0_DC_PREF_STREAM_CONFIRM ] = { 152, 146, 146, 139, -1, -1 }, [ POWER7_PME_PM_L1_DCACHE_RELOAD_VALID ] = { -1, -1, 90, -1, -1, -1 }, [ POWER7_PME_PM_VSU_SCALAR_DOUBLE_ISSUED ] = { 262, 260, 254, 248, -1, -1 }, [ POWER7_PME_PM_L3_PREF_HIT ] = { -1, -1, 103, -1, -1, -1 }, [ POWER7_PME_PM_MRK_PTEG_FROM_L31_MOD ] = { 206, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_MRK_FXU_FIN ] = { -1, 193, -1, -1, -1, -1 }, [ POWER7_PME_PM_PMC4_OVERFLOW ] = { 219, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_MRK_PTEG_FROM_L3 ] = { -1, 204, -1, -1, -1, -1 }, [ POWER7_PME_PM_LSU0_LMQ_LHR_MERGE ] = { 161, 155, 155, 148, -1, -1 }, [ POWER7_PME_PM_BTAC_HIT ] = { 17, 15, 15, 16, -1, -1 }, [ POWER7_PME_PM_IERAT_XLATE_WR_16MPLUS ] = { 79, 75, 73, 73, -1, -1 }, [ POWER7_PME_PM_L3_RD_BUSY ] = { -1, -1, -1, 101, -1, -1 }, [ POWER7_PME_PM_INST_FROM_L2MISS ] = { -1, -1, -1, 79, -1, -1 }, [ POWER7_PME_PM_LSU0_DC_PREF_STREAM_ALLOC ] = { 151, 145, 145, 138, -1, -1 }, [ POWER7_PME_PM_L2_ST ] = { 108, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_VSU0_DENORM ] = { 276, 274, 268, 262, -1, -1 }, [ POWER7_PME_PM_MRK_DATA_FROM_DL2L3_SHR ] = { -1, -1, 179, -1, -1, -1 }, [ POWER7_PME_PM_BR_PRED_CR_TA ] = { 12, 10, 11, 12, -1, -1 }, [ POWER7_PME_PM_VSU0_FCONV ] = { 277, 275, 269, 263, -1, -1 }, [ POWER7_PME_PM_MRK_LSU_FLUSH_ULD ] = { 201, 199, 192, 190, -1, -1 }, [ POWER7_PME_PM_BTAC_MISS ] = { 18, 16, 16, 17, -1, -1 }, [ POWER7_PME_PM_MRK_LD_MISS_EXPOSED_CYC_COUNT ] = { 197, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_MRK_DATA_FROM_L2 ] = { 185, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_VSU_FMA ] = { 257, 255, 249, 243, -1, -1 }, [ POWER7_PME_PM_LSU0_FLUSH_SRQ ] = { 155, 149, 149, 142, -1, -1 }, [ POWER7_PME_PM_LSU1_L1_PREF ] = { 173, 167, 167, 160, -1, -1 }, [ POWER7_PME_PM_IOPS_CMPL ] = { 94, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_L2_SYS_PUMP ] = { -1, -1, 102, -1, -1, -1 }, [ POWER7_PME_PM_L2_RCLD_BUSY_RC_FULL ] = { -1, -1, -1, 91, -1, -1 }, [ POWER7_PME_PM_BCPLUS8_RSLV_TAKEN ] = { 3, 1, 2, 2, -1, -1 }, [ POWER7_PME_PM_NEST_5 ] = { 214, 214, 209, 204, -1, -1 }, [ POWER7_PME_PM_LSU_LMQ_S0_ALLOC ] = { 132, 126, 127, 120, -1, -1 }, [ POWER7_PME_PM_FLUSH_DISP_SYNC ] = { 46, 47, 45, 44, -1, -1 }, [ POWER7_PME_PM_L2_IC_INV ] = { -1, 96, -1, -1, -1, -1 }, [ POWER7_PME_PM_MRK_DATA_FROM_L21_MOD_CYC ] = { -1, -1, -1, 172, -1, -1 }, [ POWER7_PME_PM_L3_PREF_LDST ] = { 112, 106, 105, 99, -1, -1 }, [ POWER7_PME_PM_LSU_SRQ_EMPTY_CYC ] = { -1, -1, -1, 131, -1, -1 }, [ POWER7_PME_PM_LSU_LMQ_S0_VALID ] = { 133, 127, 128, 121, -1, -1 }, [ POWER7_PME_PM_FLUSH_PARTIAL ] = { 48, 49, 47, 46, -1, -1 }, [ POWER7_PME_PM_VSU1_FMA_DOUBLE ] = { 305, 303, 297, 291, -1, -1 }, [ POWER7_PME_PM_1PLUS_PPC_DISP ] = { -1, -1, -1, 0, -1, -1 }, [ POWER7_PME_PM_DATA_FROM_L2MISS ] = { -1, 25, -1, 26, -1, -1 }, [ POWER7_PME_PM_SUSPENDED ] = { 236, 236, 231, 225, -1, -1 }, [ POWER7_PME_PM_VSU0_FMA ] = { 280, 278, 272, 266, -1, -1 }, [ POWER7_PME_PM_CMPLU_STALL_SCALAR ] = { -1, -1, -1, 22, -1, -1 }, [ POWER7_PME_PM_STCX_FAIL ] = { 235, 235, 230, 224, -1, -1 }, [ POWER7_PME_PM_VSU0_FSQRT_FDIV_DOUBLE ] = { 285, 283, 277, 271, -1, -1 }, [ POWER7_PME_PM_DC_PREF_DST ] = { 29, 30, 26, 28, -1, -1 }, [ POWER7_PME_PM_VSU1_SCAL_SINGLE_ISSUED ] = { 311, 309, 303, 297, -1, -1 }, [ POWER7_PME_PM_L3_HIT ] = { 109, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_L2_GLOB_GUESS_WRONG ] = { -1, 95, -1, -1, -1, -1 }, [ POWER7_PME_PM_MRK_DFU_FIN ] = { -1, 191, -1, -1, -1, -1 }, [ POWER7_PME_PM_INST_FROM_L1 ] = { 82, 79, 78, 77, -1, -1 }, [ POWER7_PME_PM_BRU_FIN ] = { 16, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_IC_DEMAND_REQ ] = { 67, 64, 62, 62, -1, -1 }, [ POWER7_PME_PM_VSU1_FSQRT_FDIV_DOUBLE ] = { 308, 306, 300, 294, -1, -1 }, [ POWER7_PME_PM_VSU1_FMA ] = { 304, 302, 296, 290, -1, -1 }, [ POWER7_PME_PM_MRK_LD_MISS_L1 ] = { -1, 195, -1, -1, -1, -1 }, [ POWER7_PME_PM_VSU0_2FLOP_DOUBLE ] = { 272, 270, 264, 258, -1, -1 }, [ POWER7_PME_PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM ] = { 122, 116, 116, 111, -1, -1 }, [ POWER7_PME_PM_INST_PTEG_FROM_L31_SHR ] = { -1, 86, -1, -1, -1, -1 }, [ POWER7_PME_PM_MRK_LSU_REJECT_ERAT_MISS ] = { -1, -1, 195, -1, -1, -1 }, [ POWER7_PME_PM_MRK_DATA_FROM_L2MISS ] = { -1, -1, -1, 174, -1, -1 }, [ POWER7_PME_PM_DATA_FROM_RL2L3_SHR ] = { 28, 29, -1, -1, -1, -1 }, [ POWER7_PME_PM_INST_FROM_PREF ] = { 87, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_VSU1_SQ ] = { 313, 311, 305, 299, -1, -1 }, [ POWER7_PME_PM_L2_LD_DISP ] = { -1, -1, 95, -1, -1, -1 }, [ POWER7_PME_PM_L2_DISP_ALL ] = { -1, -1, -1, 90, -1, -1 }, [ POWER7_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = { 241, -1, -1, -1, -1, -1 }, [ POWER7_PME_PM_VSU_FSQRT_FDIV_DOUBLE ] = { 261, 259, 253, 247, -1, -1 }, [ POWER7_PME_PM_BR_MPRED ] = { -1, -1, -1, 3, -1, -1 }, [ POWER7_PME_PM_VSU_1FLOP ] = { 248, 246, 240, 234, -1, -1 }, [ POWER7_PME_PM_HV_CYC ] = { -1, 58, -1, -1, -1, -1 }, [ POWER7_PME_PM_MRK_DATA_FROM_RL2L3_SHR ] = { 190, 188, -1, -1, -1, -1 }, [ POWER7_PME_PM_DTLB_MISS_16M ] = { -1, -1, -1, 38, -1, -1 }, [ POWER7_PME_PM_MRK_LSU_FIN ] = { -1, -1, -1, 186, -1, -1 }, [ POWER7_PME_PM_LSU1_LMQ_LHR_MERGE ] = { 176, 170, 170, 163, -1, -1 }, [ POWER7_PME_PM_IFU_FIN ] = { -1, -1, -1, 74, -1, -1 } }; static const unsigned long long power7_group_vecs[][POWER7_NUM_GROUP_VEC] = { [ POWER7_PME_PM_NEST_4 ] = { 0x2000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_IC_DEMAND_L2_BR_ALL ] = { 0x0000000000000000ULL, 0x0000000000040000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_PMC2_SAVED ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000001000ULL }, [ POWER7_PME_PM_CMPLU_STALL_DFU ] = { 0x0000000000000000ULL, 0x0000000004000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU0_16FLOP ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000008ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_NEST_3 ] = { 0x2000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_LSU_DERAT_MISS ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000800000000000ULL }, [ POWER7_PME_PM_MRK_ST_CMPL ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000040000000000ULL }, [ POWER7_PME_PM_L2_ST_DISP ] = { 0x0800000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_L2_CASTOUT_MOD ] = { 0x0000000000000000ULL, 0x0000000000000400ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_ISEG ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000800000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_INST_TIMEO ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0020000000000000ULL }, [ POWER7_PME_PM_L2_RCST_DISP_FAIL_ADDR ] = { 0x0100000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU1_DC_PREF_STREAM_CONFIRM ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0010000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_IERAT_WR_64K ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000020ULL }, [ POWER7_PME_PM_MRK_DTLB_MISS_16M ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000080000000000ULL }, [ POWER7_PME_PM_IERAT_MISS ] = { 0x0000000000080400ULL, 0x0000000000100000ULL, 0x0000000000000000ULL, 0x0000000000204020ULL }, [ POWER7_PME_PM_MRK_PTEG_FROM_LMEM ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0010000000000000ULL }, [ POWER7_PME_PM_FLOP ] = { 0x0000000000000000ULL, 0x0000000001000000ULL, 0x0000010000040000ULL, 0x0000000000020000ULL }, [ POWER7_PME_PM_THRD_PRIO_4_5_CYC ] = { 0x0001000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_BR_PRED_TA ] = { 0x0000000000000040ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_CMPLU_STALL_FXU ] = { 0x0000000000000000ULL, 0x0000000000400000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_EXT_INT ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000002080000000ULL, 0x0000000000800000ULL }, [ POWER7_PME_PM_VSU_FSQRT_FDIV ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000020010ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_LD_MISS_EXPOSED_CYC ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000800000000000ULL }, [ POWER7_PME_PM_LSU1_LDF ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0100000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_IC_WRITE_ALL ] = { 0x0000000000000000ULL, 0x0000000000040000ULL, 0x0000000800000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU0_SRQ_STFWD ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000800000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_PTEG_FROM_RL2L3_MOD ] = { 0x0000000041000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_DATA_FROM_L31_SHR ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000008000000ULL }, [ POWER7_PME_PM_DATA_FROM_L21_MOD ] = { 0x0000000000000000ULL, 0x0000000040000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU1_SCAL_DOUBLE_ISSUED ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000040ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU0_8FLOP ] = { 0x0000000000000000ULL, 0x0800000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_POWER_EVENT1 ] = { 0x0000000300000000ULL, 0x0000000000008000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_DISP_CLB_HELD_BAL ] = { 0x0000000000000000ULL, 0x0000000000004000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU1_2FLOP ] = { 0x0000000000000000ULL, 0x0400000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LWSYNC_HELD ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000400000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_INST_FROM_L21_MOD ] = { 0x0000000000000000ULL, 0x0000400000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_IC_REQ_ALL ] = { 0x0000000000000000ULL, 0x0000000000040000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_DSLB_MISS ] = { 0x00000000000c8400ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_L3_MISS ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0008000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU0_L1_PREF ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000008000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU_SCALAR_SINGLE_ISSUED ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000080ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0020000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_L2_INST ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000001ULL }, [ POWER7_PME_PM_VSU0_FRSP ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000002000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_FLUSH_DISP ] = { 0x0000003000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_PTEG_FROM_L2MISS ] = { 0x0000000010020000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU1_DQ_ISSUED ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000800ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_CMPLU_STALL_LSU ] = { 0x0000000000000000ULL, 0x0000000000800000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_DATA_FROM_DMEM ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000008000000ULL }, [ POWER7_PME_PM_LSU_FLUSH_ULD ] = { 0x000000c000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_PTEG_FROM_LMEM ] = { 0x0000000080c00000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_DERAT_MISS_16M ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000600000000000ULL }, [ POWER7_PME_PM_THRD_ALL_RUN_CYC ] = { 0x0000200000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_STALL_CMPLU_CYC_COUNT ] = { 0x0000000000000000ULL, 0x0000000002000000ULL, 0x0000000000000000ULL, 0x0200000000000000ULL }, [ POWER7_PME_PM_DATA_FROM_DL2L3_MOD ] = { 0x0000000000000000ULL, 0x0000012480000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU_FRSP ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000082000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_DATA_FROM_L21_MOD ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000020000000ULL }, [ POWER7_PME_PM_PMC1_OVERFLOW ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000600ULL }, [ POWER7_PME_PM_VSU0_SINGLE ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000008ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_PTEG_FROM_L3MISS ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0010000000000000ULL }, [ POWER7_PME_PM_MRK_PTEG_FROM_L31_SHR ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0004000000000000ULL }, [ POWER7_PME_PM_VSU0_VECTOR_SP_ISSUED ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000200ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU1_FEST ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000004000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_INST_DISP ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000020000000000ULL }, [ POWER7_PME_PM_VSU0_COMPLEX_ISSUED ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000400ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU1_FLUSH_UST ] = { 0x0000010000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_INST_CMPL ] = { 0x1ea80000e00c4001ULL, 0xe0f0070804120ce6ULL, 0x60007b087f80f3f7ULL, 0xdffffffffcb838ffULL }, [ POWER7_PME_PM_FXU_IDLE ] = { 0x0024000000000000ULL, 0x0000000000400000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU0_FLUSH_ULD ] = { 0x0000008000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_DATA_FROM_DL2L3_MOD ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000800000000ULL }, [ POWER7_PME_PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000100000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU1_REJECT_LMQ_FULL ] = { 0x0000000000000000ULL, 0x0000000000000040ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_INST_PTEG_FROM_L21_MOD ] = { 0x0000000006000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_GCT_UTIL_3TO6_SLOT ] = { 0x0000000000000000ULL, 0x0000000000000200ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_INST_FROM_RL2L3_MOD ] = { 0x0000000000000000ULL, 0x0022000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_SHL_CREATED ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0002000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_L2_ST_HIT ] = { 0x0400000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_DATA_FROM_DMEM ] = { 0x0000000000000000ULL, 0x0000068140000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_L3_LD_MISS ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0008000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { 0x0014000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_DISP_CLB_HELD_RES ] = { 0x0000000000000000ULL, 0x0000000000004000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_L2_SN_SX_I_DONE ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000004ULL }, [ POWER7_PME_PM_GRP_CMPL ] = { 0x0000000000000000ULL, 0x0000000000400000ULL, 0x0000010000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_BCPLUS8_CONV ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x2000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_STCX_CMPL ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x1800000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU0_2FLOP ] = { 0x0000000000000000ULL, 0x0400000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_L3_PREF_MISS ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0008000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU_SRQ_SYNC_CYC ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000001000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU_REJECT_ERAT_MISS ] = { 0x0000000000000000ULL, 0x0000000000000010ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_L1_ICACHE_MISS ] = { 0x0000000000000000ULL, 0x0000000000100000ULL, 0x0000000000000000ULL, 0x0000000000204000ULL }, [ POWER7_PME_PM_LSU1_FLUSH_SRQ ] = { 0x0000040000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LD_REF_L1_LSU0 ] = { 0x0000000400000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU0_FEST ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000004000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU_VECTOR_SINGLE_ISSUED ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000200ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_FREQ_UP ] = { 0x0000000300000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_DATA_FROM_LMEM ] = { 0x0000000000000000ULL, 0x0000068830000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU1_LDX ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0200000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_PMC3_OVERFLOW ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000600ULL }, [ POWER7_PME_PM_MRK_BR_MPRED ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000004000000ULL }, [ POWER7_PME_PM_SHL_MATCH ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0002000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_BR_TAKEN ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000004000000ULL }, [ POWER7_PME_PM_ISLB_MISS ] = { 0x0000000000080400ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_CYC ] = { 0x1eb0002020030001ULL, 0x0050000000120d22ULL, 0x27b1f912b0000000ULL, 0x100000c0028381dfULL }, [ POWER7_PME_PM_MRK_DATA_FROM_DRL2L3_MOD_CYC ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000800000000ULL }, [ POWER7_PME_PM_DISP_HELD_THERMAL ] = { 0x0000000200000000ULL, 0x0000000000003000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_INST_PTEG_FROM_RL2L3_SHR ] = { 0x0000000000200000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU1_SRQ_STFWD ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000800000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_GCT_NOSLOT_BR_MPRED ] = { 0x0000000000000000ULL, 0x0000000008000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_1PLUS_PPC_CMPL ] = { 0x0000000000000000ULL, 0x0000000000030000ULL, 0x0000000100000000ULL, 0x0000000000040000ULL }, [ POWER7_PME_PM_PTEG_FROM_DMEM ] = { 0x0000000080800000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU_2FLOP ] = { 0x0000000000000000ULL, 0x1000000000000000ULL, 0x0000000000000000ULL, 0x2000000000000000ULL }, [ POWER7_PME_PM_GCT_FULL_CYC ] = { 0x0000000000000000ULL, 0x0000000000000100ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_DATA_FROM_L3_CYC ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000100000000ULL }, [ POWER7_PME_PM_LSU_SRQ_S0_ALLOC ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000004000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_DERAT_MISS_4K ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000400000000000ULL }, [ POWER7_PME_PM_BR_MPRED_TA ] = { 0x0000000000000112ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_INST_PTEG_FROM_L2MISS ] = { 0x0000000008000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_DPU_HELD_POWER ] = { 0x0000000300000000ULL, 0x0000000000003000ULL, 0x0000000000000000ULL, 0x0000000000000080ULL }, [ POWER7_PME_PM_RUN_INST_CMPL ] = { 0xfffd2fffffffffffULL, 0xffffffffffffffffULL, 0xffffffffffffffffULL, 0xffffffffffffffffULL }, [ POWER7_PME_PM_MRK_VSU_FIN ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0100000000000000ULL }, [ POWER7_PME_PM_LSU_SRQ_S0_VALID ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000003000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_GCT_EMPTY_CYC ] = { 0x0000000000000000ULL, 0x0000000000000100ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_IOPS_DISP ] = { 0x0000000000000000ULL, 0x0000000008000000ULL, 0x0000200000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_RUN_SPURR ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000100ULL }, [ POWER7_PME_PM_PTEG_FROM_L21_MOD ] = { 0x0000000000100000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU0_1FLOP ] = { 0x0000000000000000ULL, 0x0400000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_SNOOP_TLBIE ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000002000ULL }, [ POWER7_PME_PM_DATA_FROM_L3MISS ] = { 0x0000000000000000ULL, 0x0000004c40000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU_SINGLE ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000008ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_DTLB_MISS_16G ] = { 0x0000000000001000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_CMPLU_STALL_VECTOR ] = { 0x0000000000000000ULL, 0x0000000002000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_FLUSH ] = { 0x000007a800000000ULL, 0x0000000000000000ULL, 0x0000020000000000ULL, 0x0000000001000000ULL }, [ POWER7_PME_PM_L2_LD_HIT ] = { 0x0400000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_NEST_2 ] = { 0x2000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU1_1FLOP ] = { 0x0000000000000000ULL, 0x0400000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_IC_PREF_REQ ] = { 0x0000080000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_L3_LD_HIT ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0001000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_GCT_NOSLOT_IC_MISS ] = { 0x0000000000000000ULL, 0x0000000008000000ULL, 0x0000000200000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_DISP_HELD ] = { 0x0000000000000000ULL, 0x0000000000001000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_L2_LD ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0400000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU_FLUSH_SRQ ] = { 0x0000044000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_DATA_FROM_L31_MOD_CYC ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000200000000ULL }, [ POWER7_PME_PM_L2_RCST_BUSY_RC_FULL ] = { 0x1000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_TB_BIT_TRANS ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000020080000000ULL, 0x0000000000800000ULL }, [ POWER7_PME_PM_THERMAL_MAX ] = { 0x0000000000000000ULL, 0x0000000000002000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU1_FLUSH_ULD ] = { 0x0000008000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU1_REJECT_LHS ] = { 0x0000000000000000ULL, 0x0000000000000008ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU_LRQ_S0_ALLOC ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000004000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_POWER_EVENT4 ] = { 0x0000000000000000ULL, 0x0000000000008000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_DATA_FROM_L31_SHR ] = { 0x0000000000000000ULL, 0x0000000120000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_BR_UNCOND ] = { 0x0000000000000010ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU1_DC_PREF_STREAM_ALLOC ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0040000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_PMC4_REWIND ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000800ULL }, [ POWER7_PME_PM_L2_RCLD_DISP ] = { 0x0140000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_THRD_PRIO_2_3_CYC ] = { 0x0001000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_PTEG_FROM_L2MISS ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0008000000000000ULL }, [ POWER7_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = { 0x8000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU_DERAT_MISS ] = { 0x0000000000038000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000008000ULL }, [ POWER7_PME_PM_IC_PREF_CANCEL_L2 ] = { 0x0000000000000000ULL, 0x0000000000080000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_GCT_UTIL_7TO10_SLOT ] = { 0x0000000000000000ULL, 0x0000000000000200ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_FIN_STALL_CYC_COUNT ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0200000000000000ULL }, [ POWER7_PME_PM_BR_PRED_CCACHE ] = { 0x00000000000003c6ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_ST_CMPL_INT ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000040000000000ULL }, [ POWER7_PME_PM_LSU_TWO_TABLEWALK_CYC ] = { 0x0000000400000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_DATA_FROM_L3MISS ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000100000000ULL }, [ POWER7_PME_PM_GCT_NOSLOT_CYC ] = { 0x0000000000000000ULL, 0x0000000008000100ULL, 0x0000040000000000ULL, 0x0000000002000000ULL }, [ POWER7_PME_PM_LSU_SET_MPRED ] = { 0x0000000000000000ULL, 0x0000000000000020ULL, 0x0000004000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_FLUSH_DISP_TLBIE ] = { 0x0000000800000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000002000ULL }, [ POWER7_PME_PM_VSU1_FCONV ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000001000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_NEST_1 ] = { 0x2000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_DERAT_MISS_16G ] = { 0x0000000000006000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_INST_FROM_LMEM ] = { 0x0000000000000000ULL, 0x00ad180000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = { 0x8000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_CMPLU_STALL_SCALAR_LONG ] = { 0x0000000000000000ULL, 0x0000000001000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_INST_PTEG_FROM_L2 ] = { 0x0000000008200000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_PTEG_FROM_L2 ] = { 0x0000000030100000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_DATA_FROM_L21_SHR_CYC ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000080000000ULL }, [ POWER7_PME_PM_MRK_DTLB_MISS_4K ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000180000000000ULL }, [ POWER7_PME_PM_VSU0_FPSCR ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000200ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU1_VECT_DOUBLE_ISSUED ] = { 0x0000000000000000ULL, 0x8000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_PTEG_FROM_RL2L3_MOD ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0010000000000000ULL }, [ POWER7_PME_PM_L2_LD_MISS ] = { 0x0200000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VMX_RESULT_SAT_1 ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000400ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_L1_PREF ] = { 0x0000000000000000ULL, 0x0100000000000000ULL, 0x0000008008000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_DATA_FROM_LMEM_CYC ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000001000000000ULL }, [ POWER7_PME_PM_GRP_IC_MISS_NONSPEC ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000200000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_SHL_MERGED ] = { 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POWER7_PME_PM_VSU1_FSQRT_FDIV ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000010ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU0_FLUSH_LRQ ] = { 0x0000020000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LARX_LSU0 ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0080000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_IBUF_FULL_CYC ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000008000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_DATA_FROM_DL2L3_SHR_CYC ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000800000000ULL }, [ POWER7_PME_PM_LSU_DC_PREF_STREAM_ALLOC ] = { 0x0000000000000000ULL, 0x0100000000000000ULL, 0x0040008000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_GRP_MRK_CYC ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0400000000000000ULL }, [ POWER7_PME_PM_MRK_DATA_FROM_RL2L3_SHR_CYC ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000400000000ULL }, [ POWER7_PME_PM_L2_GLOB_GUESS_CORRECT ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000020000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU_REJECT_LHS ] = { 0x0000000000000000ULL, 0x0000000000000008ULL, 0x0800000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_DATA_FROM_LMEM ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000020000000ULL }, [ POWER7_PME_PM_INST_PTEG_FROM_L3 ] = { 0x0000000000100000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_FREQ_DOWN ] = { 0x0000000100000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_INST_FROM_RL2L3_SHR ] = { 0x0000000000000000ULL, 0x0026800000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_INST_ISSUED ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000020000000000ULL }, [ POWER7_PME_PM_PTEG_FROM_L3MISS ] = { 0x0000000000430000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_RUN_PURR ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000010100ULL }, [ POWER7_PME_PM_MRK_DATA_FROM_L3 ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000100000000ULL }, [ POWER7_PME_PM_MRK_GRP_IC_MISS ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0100000000000000ULL }, [ POWER7_PME_PM_CMPLU_STALL_DCACHE_MISS ] = { 0x0000000000000000ULL, 0x0000000000200000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_PTEG_FROM_RL2L3_SHR ] = { 0x0000000041000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU_FLUSH_LRQ ] = { 0x0000024000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_DERAT_MISS_64K ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000600000000000ULL }, [ POWER7_PME_PM_INST_PTEG_FROM_DL2L3_MOD ] = { 0x0000000000100000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_L2_ST_MISS ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0400000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LWSYNC ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000500000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0020000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_PTEG_FROM_L21_SHR ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0001000000000000ULL }, [ POWER7_PME_PM_MRK_LSU_FLUSH_LRQ ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000008000000000ULL }, [ POWER7_PME_PM_INST_IMC_MATCH_CMPL ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x4000000040000000ULL, 0x0000000001000000ULL }, [ POWER7_PME_PM_MRK_INST_FIN ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000020000000000ULL }, [ POWER7_PME_PM_INST_FROM_L31_MOD ] = { 0x0000000000000000ULL, 0x0000400000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_DTLB_MISS_64K ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000180000000000ULL }, [ POWER7_PME_PM_LSU_FIN ] = { 0x0000000000000000ULL, 0x0200000000000000ULL, 0x0000000000200000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_LSU_REJECT ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0800010000000000ULL }, [ POWER7_PME_PM_L2_CO_FAIL_BUSY ] = { 0x0080000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_DATA_FROM_L31_MOD ] = { 0x0000000000000000ULL, 0x0000000080000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_THERMAL_WARN ] = { 0x0000000000000000ULL, 0x0000000000002000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU0_4FLOP ] = { 0x0000000000000000ULL, 0x0800000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_BR_MPRED_CCACHE ] = { 0x0000000000000212ULL, 0x0000000000000000ULL, 0x0000000400000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_L1_DEMAND_WRITE ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000800000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_FLUSH_BR_MPRED ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000004000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_DTLB_MISS_16G ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000100000000000ULL }, [ POWER7_PME_PM_MRK_PTEG_FROM_DMEM ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0001000000000000ULL }, [ POWER7_PME_PM_L2_RCST_DISP ] = { 0x0040000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_CMPLU_STALL ] = { 0x0000000000000000ULL, 0x0000000002000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU_PARTIAL_CDF ] = { 0x0000001000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_DISP_CLB_HELD_SB ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000040ULL }, [ POWER7_PME_PM_VSU0_FMA_DOUBLE ] = { 0x0000000000000000ULL, 0x4000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { 0x0014000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_IC_DEMAND_CYC ] = { 0x0000080000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_DATA_FROM_L21_SHR ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000080000000ULL }, [ POWER7_PME_PM_MRK_LSU_FLUSH_UST ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000004000000000ULL }, [ POWER7_PME_PM_INST_PTEG_FROM_L3MISS ] = { 0x0000000008000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU_DENORM ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000001ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_LSU_PARTIAL_CDF ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0080000000000000ULL }, [ POWER7_PME_PM_INST_FROM_L21_SHR ] = { 0x0000000000000000ULL, 0x0000c00000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_IC_PREF_WRITE ] = { 0x0000080000000000ULL, 0x0000000000000000ULL, 0x0000000800000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_BR_PRED ] = { 0x000000000000002cULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_INST_FROM_DMEM ] = { 0x0000000000000000ULL, 0x0088300000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_IC_PREF_CANCEL_ALL ] = { 0x0000000000000000ULL, 0x00000000000c0000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU_DC_PREF_STREAM_CONFIRM ] = { 0x0000000000000000ULL, 0x0100000000000000ULL, 0x0010000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_LSU_FLUSH_SRQ ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000008000000000ULL }, [ POWER7_PME_PM_MRK_FIN_STALL_CYC ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0100000000000000ULL }, [ POWER7_PME_PM_GCT_UTIL_11PLUS_SLOT ] = { 0x0000000000000000ULL, 0x0000000000000200ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_L2_RCST_DISP_FAIL_OTHER ] = { 0x0100000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU1_DD_ISSUED ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000800ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_PTEG_FROM_L31_SHR ] = { 0x0000000001000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_DATA_FROM_L21_SHR ] = { 0x0000000000000000ULL, 0x0000000300000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU0_NCLD ] = { 0x0000000000000000ULL, 0x0000000000000080ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU1_4FLOP ] = { 0x0000000000000000ULL, 0x0800000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU1_8FLOP ] = { 0x0000000000000000ULL, 0x0800000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU_8FLOP ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000100ULL, 0x2000000000000000ULL }, [ POWER7_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000100000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_DTLB_MISS_64K ] = { 0x0000000000001000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_THRD_CONC_RUN_INST ] = { 0x0000200000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000001000000ULL }, [ POWER7_PME_PM_MRK_PTEG_FROM_L2 ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0002000000000000ULL }, [ POWER7_PME_PM_VSU_FIN ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x00000000000e8002ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_DATA_FROM_L31_MOD ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000220000000ULL }, [ POWER7_PME_PM_THRD_PRIO_0_1_CYC ] = { 0x0001200000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_DERAT_MISS_64K ] = { 0x0000000000006000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_PMC2_REWIND ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000800ULL }, [ POWER7_PME_PM_INST_FROM_L2 ] = { 0x0000000000000000ULL, 0x0010080000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_GRP_BR_MPRED_NONSPEC ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000400000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_INST_DISP ] = { 0x0000000000000001ULL, 0x0000000000010001ULL, 0x4000000100000000ULL, 0x0000000003040000ULL }, [ POWER7_PME_PM_LSU0_DC_PREF_STREAM_CONFIRM ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0010000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_L1_DCACHE_RELOAD_VALID ] = { 0x0000000000000000ULL, 0x0000041000200007ULL, 0x0000002000000000ULL, 0x0000000000100000ULL }, [ POWER7_PME_PM_VSU_SCALAR_DOUBLE_ISSUED ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000040ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_L3_PREF_HIT ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0401000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_PTEG_FROM_L31_MOD ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0008000000000000ULL }, [ POWER7_PME_PM_MRK_FXU_FIN ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0040000000000000ULL }, [ POWER7_PME_PM_PMC4_OVERFLOW ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000200ULL }, [ POWER7_PME_PM_MRK_PTEG_FROM_L3 ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0008000000000000ULL }, [ POWER7_PME_PM_LSU0_LMQ_LHR_MERGE ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000400000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_BTAC_HIT ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x1000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_IERAT_XLATE_WR_16MPLUS ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000020ULL }, [ POWER7_PME_PM_L3_RD_BUSY ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0004000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_INST_FROM_L2MISS ] = { 0x0000000000000000ULL, 0x0005880000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU0_DC_PREF_STREAM_ALLOC ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0040000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_L2_ST ] = { 0x0200000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU0_DENORM ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000001ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_DATA_FROM_DL2L3_SHR ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000008000000ULL }, [ POWER7_PME_PM_BR_PRED_CR_TA ] = { 0x0000000000000020ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU0_FCONV ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000001000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_LSU_FLUSH_ULD ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000004000000000ULL }, [ POWER7_PME_PM_BTAC_MISS ] = { 0x0000000000000800ULL, 0x0000000000000000ULL, 0x1000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_LD_MISS_EXPOSED_CYC_COUNT ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000002000000000ULL }, [ POWER7_PME_PM_MRK_DATA_FROM_L2 ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000090000000ULL }, [ POWER7_PME_PM_VSU_FMA ] = { 0x0000000000000000ULL, 0x2000000000000000ULL, 0x0000000000030000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU0_FLUSH_SRQ ] = { 0x0000040000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU1_L1_PREF ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000008000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_IOPS_CMPL ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000200000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_L2_SYS_PUMP ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000002ULL }, [ POWER7_PME_PM_L2_RCLD_BUSY_RC_FULL ] = { 0x0040000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_BCPLUS8_RSLV_TAKEN ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x2000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_NEST_5 ] = { 0x4000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU_LMQ_S0_ALLOC ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000004000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_FLUSH_DISP_SYNC ] = { 0x0000000800000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_L2_IC_INV ] = { 0x0000000000000000ULL, 0x0000000000000800ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_DATA_FROM_L21_MOD_CYC ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000002000000000ULL }, [ POWER7_PME_PM_L3_PREF_LDST ] = { 0x0000000000000000ULL, 0x0100000000000000ULL, 0x0004000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU_SRQ_EMPTY_CYC ] = { 0x0000000000000000ULL, 0x0000000000000010ULL, 0x0000000000100000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU_LMQ_S0_VALID ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000002400000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_FLUSH_PARTIAL ] = { 0x0000001000000000ULL, 0x0000000000000000ULL, 0x0000004000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU1_FMA_DOUBLE ] = { 0x0000000000000000ULL, 0x4000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_1PLUS_PPC_DISP ] = { 0x0000000000000000ULL, 0x0000000000031001ULL, 0x0000000100000000ULL, 0x0000000000040000ULL }, [ POWER7_PME_PM_DATA_FROM_L2MISS ] = { 0x0000000000008000ULL, 0x0000005260000000ULL, 0x0000000000000000ULL, 0x0000000000100000ULL }, [ POWER7_PME_PM_SUSPENDED ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000100000000000ULL, 0x0000000000400000ULL }, [ POWER7_PME_PM_VSU0_FMA ] = { 0x0000000000000000ULL, 0x2000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_CMPLU_STALL_SCALAR ] = { 0x0000000000000000ULL, 0x0000000001000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_STCX_FAIL ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x1800000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU0_FSQRT_FDIV_DOUBLE ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000020ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_DC_PREF_DST ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0040000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU1_SCAL_SINGLE_ISSUED ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000080ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_L3_HIT ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0001000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_L2_GLOB_GUESS_WRONG ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000020000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_DFU_FIN ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0200000000000000ULL }, [ POWER7_PME_PM_INST_FROM_L1 ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000040000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_BRU_FIN ] = { 0x0000000000000008ULL, 0x0000000000000000ULL, 0x0000000000008000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_IC_DEMAND_REQ ] = { 0x8000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU1_FSQRT_FDIV_DOUBLE ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000020ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU1_FMA ] = { 0x0000000000000000ULL, 0x2000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_LD_MISS_L1 ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000004000000ULL }, [ POWER7_PME_PM_VSU0_2FLOP_DOUBLE ] = { 0x0000000000000000ULL, 0x1000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM ] = { 0x0000000000000000ULL, 0x0200000000000000ULL, 0x0020000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_INST_PTEG_FROM_L31_SHR ] = { 0x0000000004000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_LSU_REJECT_ERAT_MISS ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0800000000000000ULL }, [ POWER7_PME_PM_MRK_DATA_FROM_L2MISS ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000010000000ULL }, [ POWER7_PME_PM_DATA_FROM_RL2L3_SHR ] = { 0x0000000000000000ULL, 0x0000002680000004ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_INST_FROM_PREF ] = { 0x0000000000000000ULL, 0x0009000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU1_SQ ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000800ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_L2_LD_DISP ] = { 0x0800000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_L2_DISP_ALL ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x8000000000000000ULL, 0x0000000000000001ULL }, [ POWER7_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = { 0x0000200000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_VSU_FSQRT_FDIV_DOUBLE ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000020ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_BR_MPRED ] = { 0x0000000000000008ULL, 0x0000000000000000ULL, 0x0000046400000000ULL, 0x0000000002000000ULL }, [ POWER7_PME_PM_VSU_1FLOP ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000070100ULL, 0x2000000000000000ULL }, [ POWER7_PME_PM_HV_CYC ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000001100000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_DATA_FROM_RL2L3_SHR ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000040000000ULL }, [ POWER7_PME_PM_DTLB_MISS_16M ] = { 0x0000000000001000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_MRK_LSU_FIN ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000000000ULL, 0x10c0000000000000ULL }, [ POWER7_PME_PM_LSU1_LMQ_LHR_MERGE ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000000000400000ULL, 0x0000000000000000ULL }, [ POWER7_PME_PM_IFU_FIN ] = { 0x0000000000000000ULL, 0x0000000000000000ULL, 0x0000081000000000ULL, 0x0000000000000000ULL } }; static const pme_power_entry_t power7_pe[] = { [ POWER7_PME_PM_NEST_4 ] = { .pme_name = "PM_NEST_4", .pme_code = 0x87, .pme_short_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)", .pme_long_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_NEST_4], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_NEST_4] }, [ POWER7_PME_PM_IC_DEMAND_L2_BR_ALL ] = { .pme_name = "PM_IC_DEMAND_L2_BR_ALL", .pme_code = 0x4898, .pme_short_desc = " L2 I cache demand request due to BHT or redirect", .pme_long_desc = " L2 I cache demand request due to BHT or redirect", .pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_DEMAND_L2_BR_ALL], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_DEMAND_L2_BR_ALL] }, [ POWER7_PME_PM_PMC2_SAVED ] = { .pme_name = "PM_PMC2_SAVED", .pme_code = 0x10022, .pme_short_desc = "PMC2 Rewind Value saved", .pme_long_desc = "PMC2 was counting speculatively. The speculative condition was met and the counter value was committed by copying it to the backup register.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_PMC2_SAVED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_PMC2_SAVED] }, [ POWER7_PME_PM_CMPLU_STALL_DFU ] = { .pme_name = "PM_CMPLU_STALL_DFU", .pme_code = 0x2003c, .pme_short_desc = "Completion stall caused by Decimal Floating Point Unit", .pme_long_desc = "Completion stall caused by Decimal Floating Point Unit", .pme_event_ids = power7_event_ids[POWER7_PME_PM_CMPLU_STALL_DFU], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_CMPLU_STALL_DFU] }, [ POWER7_PME_PM_VSU0_16FLOP ] = { .pme_name = "PM_VSU0_16FLOP", .pme_code = 0xa0a4, .pme_short_desc = "Sixteen flops operation (SP vector versions of fdiv", .pme_long_desc = "fsqrt) ", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_16FLOP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_16FLOP] }, [ POWER7_PME_PM_NEST_3 ] = { .pme_name = "PM_NEST_3", .pme_code = 0x85, .pme_short_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)", .pme_long_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_NEST_3], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_NEST_3] }, [ POWER7_PME_PM_MRK_LSU_DERAT_MISS ] = { .pme_name = "PM_MRK_LSU_DERAT_MISS", .pme_code = 0x3d05a, .pme_short_desc = "Marked DERAT Miss", .pme_long_desc = "Marked DERAT Miss", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LSU_DERAT_MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LSU_DERAT_MISS] }, [ POWER7_PME_PM_MRK_ST_CMPL ] = { .pme_name = "PM_MRK_ST_CMPL", .pme_code = 0x10034, .pme_short_desc = "marked store finished (was complete)", .pme_long_desc = "A sampled store has completed (data home)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_ST_CMPL], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_ST_CMPL] }, [ POWER7_PME_PM_L2_ST_DISP ] = { .pme_name = "PM_L2_ST_DISP", .pme_code = 0x46180, .pme_short_desc = "All successful store dispatches", .pme_long_desc = "All successful store dispatches", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_ST_DISP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_ST_DISP] }, [ POWER7_PME_PM_L2_CASTOUT_MOD ] = { .pme_name = "PM_L2_CASTOUT_MOD", .pme_code = 0x16180, .pme_short_desc = "L2 Castouts - Modified (M", .pme_long_desc = " Mu", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_CASTOUT_MOD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_CASTOUT_MOD] }, [ POWER7_PME_PM_ISEG ] = { .pme_name = "PM_ISEG", .pme_code = 0x20a4, .pme_short_desc = "ISEG Exception", .pme_long_desc = "ISEG Exception", .pme_event_ids = power7_event_ids[POWER7_PME_PM_ISEG], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_ISEG] }, [ POWER7_PME_PM_MRK_INST_TIMEO ] = { .pme_name = "PM_MRK_INST_TIMEO", .pme_code = 0x40034, .pme_short_desc = "marked Instruction finish timeout ", .pme_long_desc = "The number of instructions finished since the last progress indicator from a marked instruction exceeded the threshold. The marked instruction was flushed.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_INST_TIMEO], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_INST_TIMEO] }, [ POWER7_PME_PM_L2_RCST_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2_RCST_DISP_FAIL_ADDR", .pme_code = 0x36282, .pme_short_desc = " L2 RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = " L2 RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_RCST_DISP_FAIL_ADDR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_RCST_DISP_FAIL_ADDR] }, [ POWER7_PME_PM_LSU1_DC_PREF_STREAM_CONFIRM ] = { .pme_name = "PM_LSU1_DC_PREF_STREAM_CONFIRM", .pme_code = 0xd0b6, .pme_short_desc = "LS1 'Dcache prefetch stream confirmed", .pme_long_desc = "LS1 'Dcache prefetch stream confirmed", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_DC_PREF_STREAM_CONFIRM], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_DC_PREF_STREAM_CONFIRM] }, [ POWER7_PME_PM_IERAT_WR_64K ] = { .pme_name = "PM_IERAT_WR_64K", .pme_code = 0x40be, .pme_short_desc = "large page 64k ", .pme_long_desc = "large page 64k ", .pme_event_ids = power7_event_ids[POWER7_PME_PM_IERAT_WR_64K], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_IERAT_WR_64K] }, [ POWER7_PME_PM_MRK_DTLB_MISS_16M ] = { .pme_name = "PM_MRK_DTLB_MISS_16M", .pme_code = 0x4d05e, .pme_short_desc = "Marked Data TLB misses for 16M page", .pme_long_desc = "Data TLB references to 16M pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DTLB_MISS_16M], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DTLB_MISS_16M] }, [ POWER7_PME_PM_IERAT_MISS ] = { .pme_name = "PM_IERAT_MISS", .pme_code = 0x100f6, .pme_short_desc = "IERAT Miss (Not implemented as DI on POWER6)", .pme_long_desc = "A translation request missed the Instruction Effective to Real Address Translation (ERAT) table", .pme_event_ids = power7_event_ids[POWER7_PME_PM_IERAT_MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_IERAT_MISS] }, [ POWER7_PME_PM_MRK_PTEG_FROM_LMEM ] = { .pme_name = "PM_MRK_PTEG_FROM_LMEM", .pme_code = 0x4d052, .pme_short_desc = "Marked PTEG loaded from local memory", .pme_long_desc = "A Page Table Entry was loaded into the ERAT from memory attached to the same module this proccessor is located on due to a marked load or store.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_PTEG_FROM_LMEM], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_PTEG_FROM_LMEM] }, [ POWER7_PME_PM_FLOP ] = { .pme_name = "PM_FLOP", .pme_code = 0x100f4, .pme_short_desc = "Floating Point Operation Finished", .pme_long_desc = "A floating point operation has completed", .pme_event_ids = power7_event_ids[POWER7_PME_PM_FLOP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_FLOP] }, [ POWER7_PME_PM_THRD_PRIO_4_5_CYC ] = { .pme_name = "PM_THRD_PRIO_4_5_CYC", .pme_code = 0x40b4, .pme_short_desc = " Cycles thread running at priority level 4 or 5", .pme_long_desc = " Cycles thread running at priority level 4 or 5", .pme_event_ids = power7_event_ids[POWER7_PME_PM_THRD_PRIO_4_5_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_THRD_PRIO_4_5_CYC] }, [ POWER7_PME_PM_BR_PRED_TA ] = { .pme_name = "PM_BR_PRED_TA", .pme_code = 0x40aa, .pme_short_desc = "Branch predict - target address", .pme_long_desc = "The target address of a branch instruction was predicted.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_BR_PRED_TA], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_BR_PRED_TA] }, [ POWER7_PME_PM_CMPLU_STALL_FXU ] = { .pme_name = "PM_CMPLU_STALL_FXU", .pme_code = 0x20014, .pme_short_desc = "Completion stall caused by FXU instruction", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point instruction.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_CMPLU_STALL_FXU], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_CMPLU_STALL_FXU] }, [ POWER7_PME_PM_EXT_INT ] = { .pme_name = "PM_EXT_INT", .pme_code = 0x200f8, .pme_short_desc = "external interrupt", .pme_long_desc = "An interrupt due to an external exception occurred", .pme_event_ids = power7_event_ids[POWER7_PME_PM_EXT_INT], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_EXT_INT] }, [ POWER7_PME_PM_VSU_FSQRT_FDIV ] = { .pme_name = "PM_VSU_FSQRT_FDIV", .pme_code = 0xa888, .pme_short_desc = "four flops operation (fdiv", .pme_long_desc = "fsqrt) Scalar Instructions only!", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_FSQRT_FDIV], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_FSQRT_FDIV] }, [ POWER7_PME_PM_MRK_LD_MISS_EXPOSED_CYC ] = { .pme_name = "PM_MRK_LD_MISS_EXPOSED_CYC", .pme_code = 0x1003e, .pme_short_desc = "Marked Load exposed Miss ", .pme_long_desc = "Marked Load exposed Miss ", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LD_MISS_EXPOSED_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LD_MISS_EXPOSED_CYC] }, [ POWER7_PME_PM_LSU1_LDF ] = { .pme_name = "PM_LSU1_LDF", .pme_code = 0xc086, .pme_short_desc = "LS1 Scalar Loads ", .pme_long_desc = "A floating point load was executed by LSU1", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_LDF], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_LDF] }, [ POWER7_PME_PM_IC_WRITE_ALL ] = { .pme_name = "PM_IC_WRITE_ALL", .pme_code = 0x488c, .pme_short_desc = "Icache sectors written", .pme_long_desc = " prefetch + demand", .pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_WRITE_ALL], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_WRITE_ALL] }, [ POWER7_PME_PM_LSU0_SRQ_STFWD ] = { .pme_name = "PM_LSU0_SRQ_STFWD", .pme_code = 0xc0a0, .pme_short_desc = "LS0 SRQ forwarded data to a load", .pme_long_desc = "Data from a store instruction was forwarded to a load on unit 0. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_SRQ_STFWD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_SRQ_STFWD] }, [ POWER7_PME_PM_PTEG_FROM_RL2L3_MOD ] = { .pme_name = "PM_PTEG_FROM_RL2L3_MOD", .pme_code = 0x1c052, .pme_short_desc = "PTEG loaded from remote L2 or L3 modified", .pme_long_desc = "A Page Table Entry was loaded into the ERAT with modified (M) data from an L2 or L3 on a remote module due to a demand load or store.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_PTEG_FROM_RL2L3_MOD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_PTEG_FROM_RL2L3_MOD] }, [ POWER7_PME_PM_MRK_DATA_FROM_L31_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L31_SHR", .pme_code = 0x1d04e, .pme_short_desc = "Marked data loaded from another L3 on same chip shared", .pme_long_desc = "Marked data loaded from another L3 on same chip shared", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_L31_SHR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_L31_SHR] }, [ POWER7_PME_PM_DATA_FROM_L21_MOD ] = { .pme_name = "PM_DATA_FROM_L21_MOD", .pme_code = 0x3c046, .pme_short_desc = "Data loaded from another L2 on same chip modified", .pme_long_desc = "Data loaded from another L2 on same chip modified", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_L21_MOD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_L21_MOD] }, [ POWER7_PME_PM_VSU1_SCAL_DOUBLE_ISSUED ] = { .pme_name = "PM_VSU1_SCAL_DOUBLE_ISSUED", .pme_code = 0xb08a, .pme_short_desc = "Double Precision scalar instruction issued on Pipe1", .pme_long_desc = "Double Precision scalar instruction issued on Pipe1", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_SCAL_DOUBLE_ISSUED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_SCAL_DOUBLE_ISSUED] }, [ POWER7_PME_PM_VSU0_8FLOP ] = { .pme_name = "PM_VSU0_8FLOP", .pme_code = 0xa0a0, .pme_short_desc = "eight flops operation (DP vector versions of fdiv", .pme_long_desc = "fsqrt and SP vector versions of fmadd", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_8FLOP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_8FLOP] }, [ POWER7_PME_PM_POWER_EVENT1 ] = { .pme_name = "PM_POWER_EVENT1", .pme_code = 0x1006e, .pme_short_desc = "Power Management Event 1", .pme_long_desc = "Power Management Event 1", .pme_event_ids = power7_event_ids[POWER7_PME_PM_POWER_EVENT1], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_POWER_EVENT1] }, [ POWER7_PME_PM_DISP_CLB_HELD_BAL ] = { .pme_name = "PM_DISP_CLB_HELD_BAL", .pme_code = 0x2092, .pme_short_desc = "Dispatch/CLB Hold: Balance", .pme_long_desc = "Dispatch/CLB Hold: Balance", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DISP_CLB_HELD_BAL], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DISP_CLB_HELD_BAL] }, [ POWER7_PME_PM_VSU1_2FLOP ] = { .pme_name = "PM_VSU1_2FLOP", .pme_code = 0xa09a, .pme_short_desc = "two flops operation (scalar fmadd", .pme_long_desc = " fnmadd", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_2FLOP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_2FLOP] }, [ POWER7_PME_PM_LWSYNC_HELD ] = { .pme_name = "PM_LWSYNC_HELD", .pme_code = 0x209a, .pme_short_desc = "LWSYNC held at dispatch", .pme_long_desc = "Cycles a LWSYNC instruction was held at dispatch. LWSYNC instructions are held at dispatch until all previous loads are done and all previous stores have issued. LWSYNC enters the Store Request Queue and is sent to the storage subsystem but does not wait for a response.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LWSYNC_HELD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LWSYNC_HELD] }, [ POWER7_PME_PM_INST_FROM_L21_MOD ] = { .pme_name = "PM_INST_FROM_L21_MOD", .pme_code = 0x34046, .pme_short_desc = "Instruction fetched from another L2 on same chip modified", .pme_long_desc = "Instruction fetched from another L2 on same chip modified", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_L21_MOD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_L21_MOD] }, [ POWER7_PME_PM_IC_REQ_ALL ] = { .pme_name = "PM_IC_REQ_ALL", .pme_code = 0x4888, .pme_short_desc = "Icache requests", .pme_long_desc = " prefetch + demand", .pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_REQ_ALL], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_REQ_ALL] }, [ POWER7_PME_PM_DSLB_MISS ] = { .pme_name = "PM_DSLB_MISS", .pme_code = 0xd090, .pme_short_desc = "Data SLB Miss - Total of all segment sizes", .pme_long_desc = "A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DSLB_MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DSLB_MISS] }, [ POWER7_PME_PM_L3_MISS ] = { .pme_name = "PM_L3_MISS", .pme_code = 0x1f082, .pme_short_desc = "L3 Misses ", .pme_long_desc = "L3 Misses ", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L3_MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L3_MISS] }, [ POWER7_PME_PM_LSU0_L1_PREF ] = { .pme_name = "PM_LSU0_L1_PREF", .pme_code = 0xd0b8, .pme_short_desc = " LS0 L1 cache data prefetches", .pme_long_desc = " LS0 L1 cache data prefetches", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_L1_PREF], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_L1_PREF] }, [ POWER7_PME_PM_VSU_SCALAR_SINGLE_ISSUED ] = { .pme_name = "PM_VSU_SCALAR_SINGLE_ISSUED", .pme_code = 0xb884, .pme_short_desc = "Single Precision scalar instruction issued on Pipe0", .pme_long_desc = "Single Precision scalar instruction issued on Pipe0", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_SCALAR_SINGLE_ISSUED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_SCALAR_SINGLE_ISSUED] }, [ POWER7_PME_PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE ] = { .pme_name = "PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE", .pme_code = 0xd0be, .pme_short_desc = "LS1 Dcache Strided prefetch stream confirmed", .pme_long_desc = "LS1 Dcache Strided prefetch stream confirmed", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE] }, [ POWER7_PME_PM_L2_INST ] = { .pme_name = "PM_L2_INST", .pme_code = 0x36080, .pme_short_desc = "Instruction Load Count", .pme_long_desc = "Instruction Load Count", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_INST], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_INST] }, [ POWER7_PME_PM_VSU0_FRSP ] = { .pme_name = "PM_VSU0_FRSP", .pme_code = 0xa0b4, .pme_short_desc = "Round to single precision instruction executed", .pme_long_desc = "Round to single precision instruction executed", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_FRSP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_FRSP] }, [ POWER7_PME_PM_FLUSH_DISP ] = { .pme_name = "PM_FLUSH_DISP", .pme_code = 0x2082, .pme_short_desc = "Dispatch flush", .pme_long_desc = "Dispatch flush", .pme_event_ids = power7_event_ids[POWER7_PME_PM_FLUSH_DISP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_FLUSH_DISP] }, [ POWER7_PME_PM_PTEG_FROM_L2MISS ] = { .pme_name = "PM_PTEG_FROM_L2MISS", .pme_code = 0x4c058, .pme_short_desc = "PTEG loaded from L2 miss", .pme_long_desc = "A Page Table Entry was loaded into the TLB but not from the local L2.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_PTEG_FROM_L2MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_PTEG_FROM_L2MISS] }, [ POWER7_PME_PM_VSU1_DQ_ISSUED ] = { .pme_name = "PM_VSU1_DQ_ISSUED", .pme_code = 0xb09a, .pme_short_desc = "128BIT Decimal Issued on Pipe1", .pme_long_desc = "128BIT Decimal Issued on Pipe1", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_DQ_ISSUED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_DQ_ISSUED] }, [ POWER7_PME_PM_CMPLU_STALL_LSU ] = { .pme_name = "PM_CMPLU_STALL_LSU", .pme_code = 0x20012, .pme_short_desc = "Completion stall caused by LSU instruction", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a load/store instruction.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_CMPLU_STALL_LSU], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_CMPLU_STALL_LSU] }, [ POWER7_PME_PM_MRK_DATA_FROM_DMEM ] = { .pme_name = "PM_MRK_DATA_FROM_DMEM", .pme_code = 0x1d04a, .pme_short_desc = "Marked data loaded from distant memory", .pme_long_desc = "The processor's Data Cache was reloaded with data from memory attached to a distant module due to a marked load.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_DMEM], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_DMEM] }, [ POWER7_PME_PM_LSU_FLUSH_ULD ] = { .pme_name = "PM_LSU_FLUSH_ULD", .pme_code = 0xc8b0, .pme_short_desc = "Flush: Unaligned Load", .pme_long_desc = "A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1). Combined Unit 0 + 1.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_FLUSH_ULD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_FLUSH_ULD] }, [ POWER7_PME_PM_PTEG_FROM_LMEM ] = { .pme_name = "PM_PTEG_FROM_LMEM", .pme_code = 0x4c052, .pme_short_desc = "PTEG loaded from local memory", .pme_long_desc = "A Page Table Entry was loaded into the TLB from memory attached to the same module this proccessor is located on.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_PTEG_FROM_LMEM], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_PTEG_FROM_LMEM] }, [ POWER7_PME_PM_MRK_DERAT_MISS_16M ] = { .pme_name = "PM_MRK_DERAT_MISS_16M", .pme_code = 0x3d05c, .pme_short_desc = "Marked DERAT misses for 16M page", .pme_long_desc = "A marked data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DERAT_MISS_16M], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DERAT_MISS_16M] }, [ POWER7_PME_PM_THRD_ALL_RUN_CYC ] = { .pme_name = "PM_THRD_ALL_RUN_CYC", .pme_code = 0x2000c, .pme_short_desc = "All Threads in run_cycles", .pme_long_desc = "Cycles when all threads had their run latches set. Operating systems use the run latch to indicate when they are doing useful work.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_THRD_ALL_RUN_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_THRD_ALL_RUN_CYC] }, [ POWER7_PME_PM_MRK_STALL_CMPLU_CYC_COUNT ] = { .pme_name = "PM_MRK_STALL_CMPLU_CYC_COUNT", .pme_code = 0x3003f, .pme_short_desc = "Marked Group Completion Stall cycles (use edge detect to count #)", .pme_long_desc = "Marked Group Completion Stall cycles (use edge detect to count #)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_STALL_CMPLU_CYC_COUNT], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_STALL_CMPLU_CYC_COUNT] }, [ POWER7_PME_PM_DATA_FROM_DL2L3_MOD ] = { .pme_name = "PM_DATA_FROM_DL2L3_MOD", .pme_code = 0x3c04c, .pme_short_desc = "Data loaded from distant L2 or L3 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a demand load", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_DL2L3_MOD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_DL2L3_MOD] }, [ POWER7_PME_PM_VSU_FRSP ] = { .pme_name = "PM_VSU_FRSP", .pme_code = 0xa8b4, .pme_short_desc = "Round to single precision instruction executed", .pme_long_desc = "Round to single precision instruction executed", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_FRSP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_FRSP] }, [ POWER7_PME_PM_MRK_DATA_FROM_L21_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L21_MOD", .pme_code = 0x3d046, .pme_short_desc = "Marked data loaded from another L2 on same chip modified", .pme_long_desc = "Marked data loaded from another L2 on same chip modified", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_L21_MOD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_L21_MOD] }, [ POWER7_PME_PM_PMC1_OVERFLOW ] = { .pme_name = "PM_PMC1_OVERFLOW", .pme_code = 0x20010, .pme_short_desc = "Overflow from counter 1", .pme_long_desc = "Overflows from PMC1 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_PMC1_OVERFLOW], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_PMC1_OVERFLOW] }, [ POWER7_PME_PM_VSU0_SINGLE ] = { .pme_name = "PM_VSU0_SINGLE", .pme_code = 0xa0a8, .pme_short_desc = "FPU single precision", .pme_long_desc = "VSU0 executed single precision instruction", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_SINGLE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_SINGLE] }, [ POWER7_PME_PM_MRK_PTEG_FROM_L3MISS ] = { .pme_name = "PM_MRK_PTEG_FROM_L3MISS", .pme_code = 0x2d058, .pme_short_desc = "Marked PTEG loaded from L3 miss", .pme_long_desc = "A Page Table Entry was loaded into the ERAT from beyond the L3 due to a marked load or store", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_PTEG_FROM_L3MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_PTEG_FROM_L3MISS] }, [ POWER7_PME_PM_MRK_PTEG_FROM_L31_SHR ] = { .pme_name = "PM_MRK_PTEG_FROM_L31_SHR", .pme_code = 0x2d056, .pme_short_desc = "Marked PTEG loaded from another L3 on same chip shared", .pme_long_desc = "Marked PTEG loaded from another L3 on same chip shared", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_PTEG_FROM_L31_SHR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_PTEG_FROM_L31_SHR] }, [ POWER7_PME_PM_VSU0_VECTOR_SP_ISSUED ] = { .pme_name = "PM_VSU0_VECTOR_SP_ISSUED", .pme_code = 0xb090, .pme_short_desc = "Single Precision vector instruction issued (executed)", .pme_long_desc = "Single Precision vector instruction issued (executed)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_VECTOR_SP_ISSUED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_VECTOR_SP_ISSUED] }, [ POWER7_PME_PM_VSU1_FEST ] = { .pme_name = "PM_VSU1_FEST", .pme_code = 0xa0ba, .pme_short_desc = "Estimate instruction executed", .pme_long_desc = "Estimate instruction executed", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_FEST], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_FEST] }, [ POWER7_PME_PM_MRK_INST_DISP ] = { .pme_name = "PM_MRK_INST_DISP", .pme_code = 0x20030, .pme_short_desc = "marked instruction dispatch", .pme_long_desc = "A marked instruction was dispatched", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_INST_DISP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_INST_DISP] }, [ POWER7_PME_PM_VSU0_COMPLEX_ISSUED ] = { .pme_name = "PM_VSU0_COMPLEX_ISSUED", .pme_code = 0xb096, .pme_short_desc = "Complex VMX instruction issued", .pme_long_desc = "Complex VMX instruction issued", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_COMPLEX_ISSUED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_COMPLEX_ISSUED] }, [ POWER7_PME_PM_LSU1_FLUSH_UST ] = { .pme_name = "PM_LSU1_FLUSH_UST", .pme_code = 0xc0b6, .pme_short_desc = "LS1 Flush: Unaligned Store", .pme_long_desc = "A store was flushed from unit 1 because it was unaligned (crossed a 4K boundary)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_FLUSH_UST], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_FLUSH_UST] }, [ POWER7_PME_PM_INST_CMPL ] = { .pme_name = "PM_INST_CMPL", .pme_code = 0x2, .pme_short_desc = "# PPC Instructions Finished", .pme_long_desc = "Number of PowerPC Instructions that completed.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_CMPL], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_CMPL] }, [ POWER7_PME_PM_FXU_IDLE ] = { .pme_name = "PM_FXU_IDLE", .pme_code = 0x1000e, .pme_short_desc = "fxu0 idle and fxu1 idle", .pme_long_desc = "FXU0 and FXU1 are both idle.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_FXU_IDLE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_FXU_IDLE] }, [ POWER7_PME_PM_LSU0_FLUSH_ULD ] = { .pme_name = "PM_LSU0_FLUSH_ULD", .pme_code = 0xc0b0, .pme_short_desc = "LS0 Flush: Unaligned Load", .pme_long_desc = "A load was flushed from unit 0 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_FLUSH_ULD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_FLUSH_ULD] }, [ POWER7_PME_PM_MRK_DATA_FROM_DL2L3_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_DL2L3_MOD", .pme_code = 0x3d04c, .pme_short_desc = "Marked data loaded from distant L2 or L3 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a marked load.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_DL2L3_MOD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_DL2L3_MOD] }, [ POWER7_PME_PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC ] = { .pme_name = "PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC", .pme_code = 0x3001c, .pme_short_desc = "ALL threads lsu empty (lmq and srq empty)", .pme_long_desc = "ALL threads lsu empty (lmq and srq empty)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC] }, [ POWER7_PME_PM_LSU1_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU1_REJECT_LMQ_FULL", .pme_code = 0xc0a6, .pme_short_desc = "LS1 Reject: LMQ Full (LHR)", .pme_long_desc = "Total cycles the Load Store Unit 1 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_REJECT_LMQ_FULL], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_REJECT_LMQ_FULL] }, [ POWER7_PME_PM_INST_PTEG_FROM_L21_MOD ] = { .pme_name = "PM_INST_PTEG_FROM_L21_MOD", .pme_code = 0x3e056, .pme_short_desc = "Instruction PTEG loaded from another L2 on same chip modified", .pme_long_desc = "Instruction PTEG loaded from another L2 on same chip modified", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_PTEG_FROM_L21_MOD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_PTEG_FROM_L21_MOD] }, [ POWER7_PME_PM_GCT_UTIL_3TO6_SLOT ] = { .pme_name = "PM_GCT_UTIL_3-6_SLOT", .pme_code = 0x209e, .pme_short_desc = "GCT Utilization 3-6 entries", .pme_long_desc = "GCT Utilization 3-6 entries", .pme_event_ids = power7_event_ids[POWER7_PME_PM_GCT_UTIL_3TO6_SLOT], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_GCT_UTIL_3TO6_SLOT] }, [ POWER7_PME_PM_INST_FROM_RL2L3_MOD ] = { .pme_name = "PM_INST_FROM_RL2L3_MOD", .pme_code = 0x14042, .pme_short_desc = "Instruction fetched from remote L2 or L3 modified", .pme_long_desc = "An instruction fetch group was fetched with modified (M) data from an L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_RL2L3_MOD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_RL2L3_MOD] }, [ POWER7_PME_PM_SHL_CREATED ] = { .pme_name = "PM_SHL_CREATED", .pme_code = 0x5082, .pme_short_desc = "SHL table entry Created", .pme_long_desc = "SHL table entry Created", .pme_event_ids = power7_event_ids[POWER7_PME_PM_SHL_CREATED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_SHL_CREATED] }, [ POWER7_PME_PM_L2_ST_HIT ] = { .pme_name = "PM_L2_ST_HIT", .pme_code = 0x46182, .pme_short_desc = "All successful store dispatches that were L2Hits", .pme_long_desc = "A store request hit in the L2 directory. This event includes all requests to this L2 from all sources. Total for all slices.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_ST_HIT], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_ST_HIT] }, [ POWER7_PME_PM_DATA_FROM_DMEM ] = { .pme_name = "PM_DATA_FROM_DMEM", .pme_code = 0x1c04a, .pme_short_desc = "Data loaded from distant memory", .pme_long_desc = "The processor's Data Cache was reloaded with data from memory attached to a distant module due to a demand load", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_DMEM], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_DMEM] }, [ POWER7_PME_PM_L3_LD_MISS ] = { .pme_name = "PM_L3_LD_MISS", .pme_code = 0x2f082, .pme_short_desc = "L3 demand LD Miss", .pme_long_desc = "L3 demand LD Miss", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L3_LD_MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L3_LD_MISS] }, [ POWER7_PME_PM_FXU1_BUSY_FXU0_IDLE ] = { .pme_name = "PM_FXU1_BUSY_FXU0_IDLE", .pme_code = 0x4000e, .pme_short_desc = "fxu0 idle and fxu1 busy. ", .pme_long_desc = "FXU0 was idle while FXU1 was busy", .pme_event_ids = power7_event_ids[POWER7_PME_PM_FXU1_BUSY_FXU0_IDLE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_FXU1_BUSY_FXU0_IDLE] }, [ POWER7_PME_PM_DISP_CLB_HELD_RES ] = { .pme_name = "PM_DISP_CLB_HELD_RES", .pme_code = 0x2094, .pme_short_desc = "Dispatch/CLB Hold: Resource", .pme_long_desc = "Dispatch/CLB Hold: Resource", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DISP_CLB_HELD_RES], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DISP_CLB_HELD_RES] }, [ POWER7_PME_PM_L2_SN_SX_I_DONE ] = { .pme_name = "PM_L2_SN_SX_I_DONE", .pme_code = 0x36382, .pme_short_desc = "SNP dispatched and went from Sx or Tx to Ix", .pme_long_desc = "SNP dispatched and went from Sx or Tx to Ix", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_SN_SX_I_DONE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_SN_SX_I_DONE] }, [ POWER7_PME_PM_GRP_CMPL ] = { .pme_name = "PM_GRP_CMPL", .pme_code = 0x30004, .pme_short_desc = "group completed", .pme_long_desc = "A group completed. Microcoded instructions that span multiple groups will generate this event once per group.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_GRP_CMPL], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_GRP_CMPL] }, [ POWER7_PME_PM_BCPLUS8_CONV ] = { .pme_name = "PM_BC+8_CONV", .pme_code = 0x40b8, .pme_short_desc = "BC+8 Converted", .pme_long_desc = "BC+8 Converted", .pme_event_ids = power7_event_ids[POWER7_PME_PM_BCPLUS8_CONV], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_BCPLUS8_CONV] }, [ POWER7_PME_PM_STCX_CMPL ] = { .pme_name = "PM_STCX_CMPL", .pme_code = 0xc098, .pme_short_desc = "STCX executed", .pme_long_desc = "Conditional stores with reservation completed", .pme_event_ids = power7_event_ids[POWER7_PME_PM_STCX_CMPL], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_STCX_CMPL] }, [ POWER7_PME_PM_VSU0_2FLOP ] = { .pme_name = "PM_VSU0_2FLOP", .pme_code = 0xa098, .pme_short_desc = "two flops operation (scalar fmadd", .pme_long_desc = " fnmadd", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_2FLOP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_2FLOP] }, [ POWER7_PME_PM_L3_PREF_MISS ] = { .pme_name = "PM_L3_PREF_MISS", .pme_code = 0x3f082, .pme_short_desc = "L3 Prefetch Directory Miss", .pme_long_desc = "L3 Prefetch Directory Miss", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L3_PREF_MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L3_PREF_MISS] }, [ POWER7_PME_PM_LSU_SRQ_SYNC_CYC ] = { .pme_name = "PM_LSU_SRQ_SYNC_CYC", .pme_code = 0xd096, .pme_short_desc = "A sync is in the SRQ", .pme_long_desc = "Cycles that a sync instruction is active in the Store Request Queue.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_SRQ_SYNC_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_SRQ_SYNC_CYC] }, [ POWER7_PME_PM_LSU_REJECT_ERAT_MISS ] = { .pme_name = "PM_LSU_REJECT_ERAT_MISS", .pme_code = 0x20064, .pme_short_desc = "LSU Reject due to ERAT (up to 2 per cycles)", .pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions due to an ERAT miss. Combined unit 0 + 1. Requests that miss the Derat are rejected and retried until the request hits in the Erat.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_REJECT_ERAT_MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_REJECT_ERAT_MISS] }, [ POWER7_PME_PM_L1_ICACHE_MISS ] = { .pme_name = "PM_L1_ICACHE_MISS", .pme_code = 0x200fc, .pme_short_desc = "Demand iCache Miss", .pme_long_desc = "An instruction fetch request missed the L1 cache.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L1_ICACHE_MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L1_ICACHE_MISS] }, [ POWER7_PME_PM_LSU1_FLUSH_SRQ ] = { .pme_name = "PM_LSU1_FLUSH_SRQ", .pme_code = 0xc0be, .pme_short_desc = "LS1 Flush: SRQ", .pme_long_desc = "Load Hit Store flush. A younger load was flushed from unit 1 because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. ", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_FLUSH_SRQ], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_FLUSH_SRQ] }, [ POWER7_PME_PM_LD_REF_L1_LSU0 ] = { .pme_name = "PM_LD_REF_L1_LSU0", .pme_code = 0xc080, .pme_short_desc = "LS0 L1 D cache load references counted at finish", .pme_long_desc = "Load references to Level 1 Data Cache, by unit 0.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LD_REF_L1_LSU0], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LD_REF_L1_LSU0] }, [ POWER7_PME_PM_VSU0_FEST ] = { .pme_name = "PM_VSU0_FEST", .pme_code = 0xa0b8, .pme_short_desc = "Estimate instruction executed", .pme_long_desc = "Estimate instruction executed", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_FEST], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_FEST] }, [ POWER7_PME_PM_VSU_VECTOR_SINGLE_ISSUED ] = { .pme_name = "PM_VSU_VECTOR_SINGLE_ISSUED", .pme_code = 0xb890, .pme_short_desc = "Single Precision vector instruction issued (executed)", .pme_long_desc = "Single Precision vector instruction issued (executed)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_VECTOR_SINGLE_ISSUED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_VECTOR_SINGLE_ISSUED] }, [ POWER7_PME_PM_FREQ_UP ] = { .pme_name = "PM_FREQ_UP", .pme_code = 0x4000c, .pme_short_desc = "Power Management: Above Threshold A", .pme_long_desc = "Processor frequency was sped up due to power management", .pme_event_ids = power7_event_ids[POWER7_PME_PM_FREQ_UP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_FREQ_UP] }, [ POWER7_PME_PM_DATA_FROM_LMEM ] = { .pme_name = "PM_DATA_FROM_LMEM", .pme_code = 0x3c04a, .pme_short_desc = "Data loaded from local memory", .pme_long_desc = "The processor's Data Cache was reloaded from memory attached to the same module this proccessor is located on.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_LMEM], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_LMEM] }, [ POWER7_PME_PM_LSU1_LDX ] = { .pme_name = "PM_LSU1_LDX", .pme_code = 0xc08a, .pme_short_desc = "LS1 Vector Loads", .pme_long_desc = "LS1 Vector Loads", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_LDX], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_LDX] }, [ POWER7_PME_PM_PMC3_OVERFLOW ] = { .pme_name = "PM_PMC3_OVERFLOW", .pme_code = 0x40010, .pme_short_desc = "Overflow from counter 3", .pme_long_desc = "Overflows from PMC3 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_PMC3_OVERFLOW], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_PMC3_OVERFLOW] }, [ POWER7_PME_PM_MRK_BR_MPRED ] = { .pme_name = "PM_MRK_BR_MPRED", .pme_code = 0x30036, .pme_short_desc = "Marked Branch Mispredicted", .pme_long_desc = "A marked branch was mispredicted", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_BR_MPRED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_BR_MPRED] }, [ POWER7_PME_PM_SHL_MATCH ] = { .pme_name = "PM_SHL_MATCH", .pme_code = 0x5086, .pme_short_desc = "SHL Table Match", .pme_long_desc = "SHL Table Match", .pme_event_ids = power7_event_ids[POWER7_PME_PM_SHL_MATCH], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_SHL_MATCH] }, [ POWER7_PME_PM_MRK_BR_TAKEN ] = { .pme_name = "PM_MRK_BR_TAKEN", .pme_code = 0x10036, .pme_short_desc = "Marked Branch Taken", .pme_long_desc = "A marked branch was taken", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_BR_TAKEN], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_BR_TAKEN] }, [ POWER7_PME_PM_ISLB_MISS ] = { .pme_name = "PM_ISLB_MISS", .pme_code = 0xd092, .pme_short_desc = "Instruction SLB Miss - Tota of all segment sizes", .pme_long_desc = "A SLB miss for an instruction fetch as occurred", .pme_event_ids = power7_event_ids[POWER7_PME_PM_ISLB_MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_ISLB_MISS] }, [ POWER7_PME_PM_CYC ] = { .pme_name = "PM_CYC", .pme_code = 0x1e, .pme_short_desc = "Cycles", .pme_long_desc = "Processor Cycles", .pme_event_ids = power7_event_ids[POWER7_PME_PM_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_CYC] }, [ POWER7_PME_PM_MRK_DATA_FROM_DRL2L3_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_DRL2L3_MOD_CYC", .pme_code = 0x4002a, .pme_short_desc = "Marked ld latency Data source 1011 (L2.75/L3.75 M different 4 chip node)", .pme_long_desc = "Marked ld latency Data source 1011 (L2.75/L3.75 M different 4 chip node)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_DRL2L3_MOD_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_DRL2L3_MOD_CYC] }, [ POWER7_PME_PM_DISP_HELD_THERMAL ] = { .pme_name = "PM_DISP_HELD_THERMAL", .pme_code = 0x30006, .pme_short_desc = "Dispatch Held due to Thermal", .pme_long_desc = "Dispatch Held due to Thermal", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DISP_HELD_THERMAL], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DISP_HELD_THERMAL] }, [ POWER7_PME_PM_INST_PTEG_FROM_RL2L3_SHR ] = { .pme_name = "PM_INST_PTEG_FROM_RL2L3_SHR", .pme_code = 0x2e054, .pme_short_desc = "Instruction PTEG loaded from remote L2 or L3 shared", .pme_long_desc = "Instruction PTEG loaded from remote L2 or L3 shared", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_PTEG_FROM_RL2L3_SHR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_PTEG_FROM_RL2L3_SHR] }, [ POWER7_PME_PM_LSU1_SRQ_STFWD ] = { .pme_name = "PM_LSU1_SRQ_STFWD", .pme_code = 0xc0a2, .pme_short_desc = "LS1 SRQ forwarded data to a load", .pme_long_desc = "Data from a store instruction was forwarded to a load on unit 1. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_SRQ_STFWD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_SRQ_STFWD] }, [ POWER7_PME_PM_GCT_NOSLOT_BR_MPRED ] = { .pme_name = "PM_GCT_NOSLOT_BR_MPRED", .pme_code = 0x4001a, .pme_short_desc = "GCT empty by branch mispredict", .pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread because of a branch misprediction.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_GCT_NOSLOT_BR_MPRED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_GCT_NOSLOT_BR_MPRED] }, [ POWER7_PME_PM_1PLUS_PPC_CMPL ] = { .pme_name = "PM_1PLUS_PPC_CMPL", .pme_code = 0x100f2, .pme_short_desc = "1 or more ppc insts finished", .pme_long_desc = "A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_1PLUS_PPC_CMPL], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_1PLUS_PPC_CMPL] }, [ POWER7_PME_PM_PTEG_FROM_DMEM ] = { .pme_name = "PM_PTEG_FROM_DMEM", .pme_code = 0x2c052, .pme_short_desc = "PTEG loaded from distant memory", .pme_long_desc = "A Page Table Entry was loaded into the ERAT with data from memory attached to a distant module due to a demand load or store.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_PTEG_FROM_DMEM], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_PTEG_FROM_DMEM] }, [ POWER7_PME_PM_VSU_2FLOP ] = { .pme_name = "PM_VSU_2FLOP", .pme_code = 0xa898, .pme_short_desc = "two flops operation (scalar fmadd", .pme_long_desc = " fnmadd", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_2FLOP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_2FLOP] }, [ POWER7_PME_PM_GCT_FULL_CYC ] = { .pme_name = "PM_GCT_FULL_CYC", .pme_code = 0x4086, .pme_short_desc = "Cycles No room in EAT", .pme_long_desc = "The Global Completion Table is completely full.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_GCT_FULL_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_GCT_FULL_CYC] }, [ POWER7_PME_PM_MRK_DATA_FROM_L3_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L3_CYC", .pme_code = 0x40020, .pme_short_desc = "Marked ld latency Data source 0001 (L3)", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_L3_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_L3_CYC] }, [ POWER7_PME_PM_LSU_SRQ_S0_ALLOC ] = { .pme_name = "PM_LSU_SRQ_S0_ALLOC", .pme_code = 0xd09d, .pme_short_desc = "Slot 0 of SRQ valid", .pme_long_desc = "Slot 0 of SRQ valid", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_SRQ_S0_ALLOC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_SRQ_S0_ALLOC] }, [ POWER7_PME_PM_MRK_DERAT_MISS_4K ] = { .pme_name = "PM_MRK_DERAT_MISS_4K", .pme_code = 0x1d05c, .pme_short_desc = "Marked DERAT misses for 4K page", .pme_long_desc = "A marked data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DERAT_MISS_4K], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DERAT_MISS_4K] }, [ POWER7_PME_PM_BR_MPRED_TA ] = { .pme_name = "PM_BR_MPRED_TA", .pme_code = 0x40ae, .pme_short_desc = "Branch mispredict - target address", .pme_long_desc = "A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_BR_MPRED_TA], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_BR_MPRED_TA] }, [ POWER7_PME_PM_INST_PTEG_FROM_L2MISS ] = { .pme_name = "PM_INST_PTEG_FROM_L2MISS", .pme_code = 0x4e058, .pme_short_desc = "Instruction PTEG loaded from L2 miss", .pme_long_desc = "Instruction PTEG loaded from L2 miss", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_PTEG_FROM_L2MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_PTEG_FROM_L2MISS] }, [ POWER7_PME_PM_DPU_HELD_POWER ] = { .pme_name = "PM_DPU_HELD_POWER", .pme_code = 0x20006, .pme_short_desc = "Dispatch Held due to Power Management", .pme_long_desc = "Cycles that Instruction Dispatch was held due to power management. More than one hold condition can exist at the same time", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DPU_HELD_POWER], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DPU_HELD_POWER] }, [ POWER7_PME_PM_RUN_INST_CMPL ] = { .pme_name = "PM_RUN_INST_CMPL", .pme_code = 0x400fa, .pme_short_desc = "Run_Instructions", .pme_long_desc = "Number of run instructions completed. ", .pme_event_ids = power7_event_ids[POWER7_PME_PM_RUN_INST_CMPL], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_RUN_INST_CMPL] }, [ POWER7_PME_PM_MRK_VSU_FIN ] = { .pme_name = "PM_MRK_VSU_FIN", .pme_code = 0x30032, .pme_short_desc = "vsu (fpu) marked instr finish", .pme_long_desc = "vsu (fpu) marked instr finish", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_VSU_FIN], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_VSU_FIN] }, [ POWER7_PME_PM_LSU_SRQ_S0_VALID ] = { .pme_name = "PM_LSU_SRQ_S0_VALID", .pme_code = 0xd09c, .pme_short_desc = "Slot 0 of SRQ valid", .pme_long_desc = "This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the SRQ is split between the two threads (16 entries each).", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_SRQ_S0_VALID], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_SRQ_S0_VALID] }, [ POWER7_PME_PM_GCT_EMPTY_CYC ] = { .pme_name = "PM_GCT_EMPTY_CYC", .pme_code = 0x20008, .pme_short_desc = "GCT empty", .pme_long_desc = " all threads", .pme_event_ids = power7_event_ids[POWER7_PME_PM_GCT_EMPTY_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_GCT_EMPTY_CYC] }, [ POWER7_PME_PM_IOPS_DISP ] = { .pme_name = "PM_IOPS_DISP", .pme_code = 0x30014, .pme_short_desc = "IOPS dispatched", .pme_long_desc = "IOPS dispatched", .pme_event_ids = power7_event_ids[POWER7_PME_PM_IOPS_DISP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_IOPS_DISP] }, [ POWER7_PME_PM_RUN_SPURR ] = { .pme_name = "PM_RUN_SPURR", .pme_code = 0x10008, .pme_short_desc = "Run SPURR", .pme_long_desc = "Run SPURR", .pme_event_ids = power7_event_ids[POWER7_PME_PM_RUN_SPURR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_RUN_SPURR] }, [ POWER7_PME_PM_PTEG_FROM_L21_MOD ] = { .pme_name = "PM_PTEG_FROM_L21_MOD", .pme_code = 0x3c056, .pme_short_desc = "PTEG loaded from another L2 on same chip modified", .pme_long_desc = "PTEG loaded from another L2 on same chip modified", .pme_event_ids = power7_event_ids[POWER7_PME_PM_PTEG_FROM_L21_MOD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_PTEG_FROM_L21_MOD] }, [ POWER7_PME_PM_VSU0_1FLOP ] = { .pme_name = "PM_VSU0_1FLOP", .pme_code = 0xa080, .pme_short_desc = "one flop (fadd", .pme_long_desc = " fmul", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_1FLOP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_1FLOP] }, [ POWER7_PME_PM_SNOOP_TLBIE ] = { .pme_name = "PM_SNOOP_TLBIE", .pme_code = 0xd0b2, .pme_short_desc = "TLBIE snoop", .pme_long_desc = "A tlbie was snooped from another processor.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_SNOOP_TLBIE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_SNOOP_TLBIE] }, [ POWER7_PME_PM_DATA_FROM_L3MISS ] = { .pme_name = "PM_DATA_FROM_L3MISS", .pme_code = 0x2c048, .pme_short_desc = "Demand LD - L3 Miss (not L2 hit and not L3 hit)", .pme_long_desc = "The processor's Data Cache was reloaded from beyond L3 due to a demand load", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_L3MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_L3MISS] }, [ POWER7_PME_PM_VSU_SINGLE ] = { .pme_name = "PM_VSU_SINGLE", .pme_code = 0xa8a8, .pme_short_desc = "Vector or Scalar single precision", .pme_long_desc = "Vector or Scalar single precision", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_SINGLE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_SINGLE] }, [ POWER7_PME_PM_DTLB_MISS_16G ] = { .pme_name = "PM_DTLB_MISS_16G", .pme_code = 0x1c05e, .pme_short_desc = "Data TLB miss for 16G page", .pme_long_desc = "Data TLB references to 16GB pages that missed the TLB. Page size is determined at TLB reload time.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DTLB_MISS_16G], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DTLB_MISS_16G] }, [ POWER7_PME_PM_CMPLU_STALL_VECTOR ] = { .pme_name = "PM_CMPLU_STALL_VECTOR", .pme_code = 0x2001c, .pme_short_desc = "Completion stall caused by Vector instruction", .pme_long_desc = "Completion stall caused by Vector instruction", .pme_event_ids = power7_event_ids[POWER7_PME_PM_CMPLU_STALL_VECTOR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_CMPLU_STALL_VECTOR] }, [ POWER7_PME_PM_FLUSH ] = { .pme_name = "PM_FLUSH", .pme_code = 0x400f8, .pme_short_desc = "Flush (any type)", .pme_long_desc = "Flushes occurred including LSU and Branch flushes.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_FLUSH], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_FLUSH] }, [ POWER7_PME_PM_L2_LD_HIT ] = { .pme_name = "PM_L2_LD_HIT", .pme_code = 0x36182, .pme_short_desc = "All successful load dispatches that were L2 hits", .pme_long_desc = "A load request (data or instruction) hit in the L2 directory. Includes speculative, prefetched, and demand requests. This event includes all requests to this L2 from all sources. Total for all slices", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_LD_HIT], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_LD_HIT] }, [ POWER7_PME_PM_NEST_2 ] = { .pme_name = "PM_NEST_2", .pme_code = 0x83, .pme_short_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)", .pme_long_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_NEST_2], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_NEST_2] }, [ POWER7_PME_PM_VSU1_1FLOP ] = { .pme_name = "PM_VSU1_1FLOP", .pme_code = 0xa082, .pme_short_desc = "one flop (fadd", .pme_long_desc = " fmul", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_1FLOP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_1FLOP] }, [ POWER7_PME_PM_IC_PREF_REQ ] = { .pme_name = "PM_IC_PREF_REQ", .pme_code = 0x408a, .pme_short_desc = "Instruction prefetch requests", .pme_long_desc = "An instruction prefetch request has been made.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_PREF_REQ], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_PREF_REQ] }, [ POWER7_PME_PM_L3_LD_HIT ] = { .pme_name = "PM_L3_LD_HIT", .pme_code = 0x2f080, .pme_short_desc = "L3 demand LD Hits", .pme_long_desc = "L3 demand LD Hits", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L3_LD_HIT], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L3_LD_HIT] }, [ POWER7_PME_PM_GCT_NOSLOT_IC_MISS ] = { .pme_name = "PM_GCT_NOSLOT_IC_MISS", .pme_code = 0x2001a, .pme_short_desc = "GCT empty by I cache miss", .pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread because of an Instruction Cache miss.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_GCT_NOSLOT_IC_MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_GCT_NOSLOT_IC_MISS] }, [ POWER7_PME_PM_DISP_HELD ] = { .pme_name = "PM_DISP_HELD", .pme_code = 0x10006, .pme_short_desc = "Dispatch Held", .pme_long_desc = "Dispatch Held", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DISP_HELD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DISP_HELD] }, [ POWER7_PME_PM_L2_LD ] = { .pme_name = "PM_L2_LD", .pme_code = 0x16080, .pme_short_desc = "Data Load Count", .pme_long_desc = "Data Load Count", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_LD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_LD] }, [ POWER7_PME_PM_LSU_FLUSH_SRQ ] = { .pme_name = "PM_LSU_FLUSH_SRQ", .pme_code = 0xc8bc, .pme_short_desc = "Flush: SRQ", .pme_long_desc = "Load Hit Store flush. A younger load was flushed because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. Combined Unit 0 + 1.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_FLUSH_SRQ], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_FLUSH_SRQ] }, [ POWER7_PME_PM_MRK_DATA_FROM_L31_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L31_MOD_CYC", .pme_code = 0x40026, .pme_short_desc = "Marked ld latency Data source 0111 (L3.1 M same chip)", .pme_long_desc = "Marked ld latency Data source 0111 (L3.1 M same chip)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_L31_MOD_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_L31_MOD_CYC] }, [ POWER7_PME_PM_L2_RCST_BUSY_RC_FULL ] = { .pme_name = "PM_L2_RCST_BUSY_RC_FULL", .pme_code = 0x26282, .pme_short_desc = " L2 activated Busy to the core for stores due to all RC full", .pme_long_desc = " L2 activated Busy to the core for stores due to all RC full", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_RCST_BUSY_RC_FULL], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_RCST_BUSY_RC_FULL] }, [ POWER7_PME_PM_TB_BIT_TRANS ] = { .pme_name = "PM_TB_BIT_TRANS", .pme_code = 0x300f8, .pme_short_desc = "Time Base bit transition", .pme_long_desc = "When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1 ", .pme_event_ids = power7_event_ids[POWER7_PME_PM_TB_BIT_TRANS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_TB_BIT_TRANS] }, [ POWER7_PME_PM_THERMAL_MAX ] = { .pme_name = "PM_THERMAL_MAX", .pme_code = 0x40006, .pme_short_desc = "Processor In Thermal MAX", .pme_long_desc = "The processor experienced a thermal overload condition. This bit is sticky, it remains set until cleared by software.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_THERMAL_MAX], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_THERMAL_MAX] }, [ POWER7_PME_PM_LSU1_FLUSH_ULD ] = { .pme_name = "PM_LSU1_FLUSH_ULD", .pme_code = 0xc0b2, .pme_short_desc = "LS 1 Flush: Unaligned Load", .pme_long_desc = "A load was flushed from unit 1 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1).", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_FLUSH_ULD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_FLUSH_ULD] }, [ POWER7_PME_PM_LSU1_REJECT_LHS ] = { .pme_name = "PM_LSU1_REJECT_LHS", .pme_code = 0xc0ae, .pme_short_desc = "LS1 Reject: Load Hit Store", .pme_long_desc = "Load Store Unit 1 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_REJECT_LHS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_REJECT_LHS] }, [ POWER7_PME_PM_LSU_LRQ_S0_ALLOC ] = { .pme_name = "PM_LSU_LRQ_S0_ALLOC", .pme_code = 0xd09f, .pme_short_desc = "Slot 0 of LRQ valid", .pme_long_desc = "Slot 0 of LRQ valid", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_LRQ_S0_ALLOC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_LRQ_S0_ALLOC] }, [ POWER7_PME_PM_POWER_EVENT4 ] = { .pme_name = "PM_POWER_EVENT4", .pme_code = 0x4006e, .pme_short_desc = "Power Management Event 4", .pme_long_desc = "Power Management Event 4", .pme_event_ids = power7_event_ids[POWER7_PME_PM_POWER_EVENT4], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_POWER_EVENT4] }, [ POWER7_PME_PM_DATA_FROM_L31_SHR ] = { .pme_name = "PM_DATA_FROM_L31_SHR", .pme_code = 0x1c04e, .pme_short_desc = "Data loaded from another L3 on same chip shared", .pme_long_desc = "Data loaded from another L3 on same chip shared", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_L31_SHR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_L31_SHR] }, [ POWER7_PME_PM_BR_UNCOND ] = { .pme_name = "PM_BR_UNCOND", .pme_code = 0x409e, .pme_short_desc = "Unconditional Branch", .pme_long_desc = "An unconditional branch was executed.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_BR_UNCOND], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_BR_UNCOND] }, [ POWER7_PME_PM_LSU1_DC_PREF_STREAM_ALLOC ] = { .pme_name = "PM_LSU1_DC_PREF_STREAM_ALLOC", .pme_code = 0xd0aa, .pme_short_desc = "LS 1 D cache new prefetch stream allocated", .pme_long_desc = "LS 1 D cache new prefetch stream allocated", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_DC_PREF_STREAM_ALLOC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_DC_PREF_STREAM_ALLOC] }, [ POWER7_PME_PM_PMC4_REWIND ] = { .pme_name = "PM_PMC4_REWIND", .pme_code = 0x10020, .pme_short_desc = "PMC4 Rewind Event", .pme_long_desc = "PMC4 was counting speculatively. The speculative condition was not met and the counter was restored to its previous value.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_PMC4_REWIND], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_PMC4_REWIND] }, [ POWER7_PME_PM_L2_RCLD_DISP ] = { .pme_name = "PM_L2_RCLD_DISP", .pme_code = 0x16280, .pme_short_desc = " L2 RC load dispatch attempt", .pme_long_desc = " L2 RC load dispatch attempt", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_RCLD_DISP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_RCLD_DISP] }, [ POWER7_PME_PM_THRD_PRIO_2_3_CYC ] = { .pme_name = "PM_THRD_PRIO_2_3_CYC", .pme_code = 0x40b2, .pme_short_desc = " Cycles thread running at priority level 2 or 3", .pme_long_desc = " Cycles thread running at priority level 2 or 3", .pme_event_ids = power7_event_ids[POWER7_PME_PM_THRD_PRIO_2_3_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_THRD_PRIO_2_3_CYC] }, [ POWER7_PME_PM_MRK_PTEG_FROM_L2MISS ] = { .pme_name = "PM_MRK_PTEG_FROM_L2MISS", .pme_code = 0x4d058, .pme_short_desc = "Marked PTEG loaded from L2 miss", .pme_long_desc = "A Page Table Entry was loaded into the ERAT but not from the local L2 due to a marked load or store.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_PTEG_FROM_L2MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_PTEG_FROM_L2MISS] }, [ POWER7_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = { .pme_name = "PM_IC_DEMAND_L2_BHT_REDIRECT", .pme_code = 0x4098, .pme_short_desc = " L2 I cache demand request due to BHT redirect", .pme_long_desc = "A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (CR mispredict).", .pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_DEMAND_L2_BHT_REDIRECT], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_DEMAND_L2_BHT_REDIRECT] }, [ POWER7_PME_PM_LSU_DERAT_MISS ] = { .pme_name = "PM_LSU_DERAT_MISS", .pme_code = 0x200f6, .pme_short_desc = "DERAT Reloaded due to a DERAT miss", .pme_long_desc = "Total D-ERAT Misses. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction. Combined Unit 0 + 1.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_DERAT_MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_DERAT_MISS] }, [ POWER7_PME_PM_IC_PREF_CANCEL_L2 ] = { .pme_name = "PM_IC_PREF_CANCEL_L2", .pme_code = 0x4094, .pme_short_desc = "L2 Squashed request", .pme_long_desc = "L2 Squashed request", .pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_PREF_CANCEL_L2], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_PREF_CANCEL_L2] }, [ POWER7_PME_PM_GCT_UTIL_7TO10_SLOT ] = { .pme_name = "PM_GCT_UTIL_7-10_SLOT", .pme_code = 0x20a0, .pme_short_desc = "GCT Utilization 7-10 entries", .pme_long_desc = "GCT Utilization 7-10 entries", .pme_event_ids = power7_event_ids[POWER7_PME_PM_GCT_UTIL_7TO10_SLOT], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_GCT_UTIL_7TO10_SLOT] }, [ POWER7_PME_PM_MRK_FIN_STALL_CYC_COUNT ] = { .pme_name = "PM_MRK_FIN_STALL_CYC_COUNT", .pme_code = 0x1003d, .pme_short_desc = "Marked instruction Finish Stall cycles (marked finish after NTC) (use edge detect to count #)", .pme_long_desc = "Marked instruction Finish Stall cycles (marked finish after NTC) (use edge detect to count #)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_FIN_STALL_CYC_COUNT], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_FIN_STALL_CYC_COUNT] }, [ POWER7_PME_PM_BR_PRED_CCACHE ] = { .pme_name = "PM_BR_PRED_CCACHE", .pme_code = 0x40a0, .pme_short_desc = "Count Cache Predictions", .pme_long_desc = "The count value of a Branch and Count instruction was predicted", .pme_event_ids = power7_event_ids[POWER7_PME_PM_BR_PRED_CCACHE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_BR_PRED_CCACHE] }, [ POWER7_PME_PM_MRK_ST_CMPL_INT ] = { .pme_name = "PM_MRK_ST_CMPL_INT", .pme_code = 0x30034, .pme_short_desc = "marked store complete (data home) with intervention", .pme_long_desc = "A marked store previously sent to the memory subsystem completed (data home) after requiring intervention", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_ST_CMPL_INT], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_ST_CMPL_INT] }, [ POWER7_PME_PM_LSU_TWO_TABLEWALK_CYC ] = { .pme_name = "PM_LSU_TWO_TABLEWALK_CYC", .pme_code = 0xd0a6, .pme_short_desc = "Cycles when two tablewalks pending on this thread", .pme_long_desc = "Cycles when two tablewalks pending on this thread", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_TWO_TABLEWALK_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_TWO_TABLEWALK_CYC] }, [ POWER7_PME_PM_MRK_DATA_FROM_L3MISS ] = { .pme_name = "PM_MRK_DATA_FROM_L3MISS", .pme_code = 0x2d048, .pme_short_desc = "Marked data loaded from L3 miss", .pme_long_desc = "DL1 was reloaded from beyond L3 due to a marked load.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_L3MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_L3MISS] }, [ POWER7_PME_PM_GCT_NOSLOT_CYC ] = { .pme_name = "PM_GCT_NOSLOT_CYC", .pme_code = 0x100f8, .pme_short_desc = "No itags assigned ", .pme_long_desc = "Cycles when the Global Completion Table has no slots from this thread.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_GCT_NOSLOT_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_GCT_NOSLOT_CYC] }, [ POWER7_PME_PM_LSU_SET_MPRED ] = { .pme_name = "PM_LSU_SET_MPRED", .pme_code = 0xc0a8, .pme_short_desc = "Line already in cache at reload time", .pme_long_desc = "Line already in cache at reload time", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_SET_MPRED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_SET_MPRED] }, [ POWER7_PME_PM_FLUSH_DISP_TLBIE ] = { .pme_name = "PM_FLUSH_DISP_TLBIE", .pme_code = 0x208a, .pme_short_desc = "Dispatch Flush: TLBIE", .pme_long_desc = "Dispatch Flush: TLBIE", .pme_event_ids = power7_event_ids[POWER7_PME_PM_FLUSH_DISP_TLBIE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_FLUSH_DISP_TLBIE] }, [ POWER7_PME_PM_VSU1_FCONV ] = { .pme_name = "PM_VSU1_FCONV", .pme_code = 0xa0b2, .pme_short_desc = "Convert instruction executed", .pme_long_desc = "Convert instruction executed", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_FCONV], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_FCONV] }, [ POWER7_PME_PM_NEST_1 ] = { .pme_name = "PM_NEST_1", .pme_code = 0x81, .pme_short_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)", .pme_long_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_NEST_1], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_NEST_1] }, [ POWER7_PME_PM_DERAT_MISS_16G ] = { .pme_name = "PM_DERAT_MISS_16G", .pme_code = 0x4c05c, .pme_short_desc = "DERAT misses for 16G page", .pme_long_desc = "A data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DERAT_MISS_16G], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DERAT_MISS_16G] }, [ POWER7_PME_PM_INST_FROM_LMEM ] = { .pme_name = "PM_INST_FROM_LMEM", .pme_code = 0x3404a, .pme_short_desc = "Instruction fetched from local memory", .pme_long_desc = "An instruction fetch group was fetched from memory attached to the same module this proccessor is located on. Fetch groups can contain up to 8 instructions", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_LMEM], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_LMEM] }, [ POWER7_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = { .pme_name = "PM_IC_DEMAND_L2_BR_REDIRECT", .pme_code = 0x409a, .pme_short_desc = " L2 I cache demand request due to branch redirect", .pme_long_desc = "A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (either ALL mispredicted or Target).", .pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_DEMAND_L2_BR_REDIRECT], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_DEMAND_L2_BR_REDIRECT] }, [ POWER7_PME_PM_CMPLU_STALL_SCALAR_LONG ] = { .pme_name = "PM_CMPLU_STALL_SCALAR_LONG", .pme_code = 0x20018, .pme_short_desc = "Completion stall caused by long latency scalar instruction", .pme_long_desc = "Completion stall caused by long latency scalar instruction", .pme_event_ids = power7_event_ids[POWER7_PME_PM_CMPLU_STALL_SCALAR_LONG], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_CMPLU_STALL_SCALAR_LONG] }, [ POWER7_PME_PM_INST_PTEG_FROM_L2 ] = { .pme_name = "PM_INST_PTEG_FROM_L2", .pme_code = 0x1e050, .pme_short_desc = "Instruction PTEG loaded from L2", .pme_long_desc = "Instruction PTEG loaded from L2", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_PTEG_FROM_L2], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_PTEG_FROM_L2] }, [ POWER7_PME_PM_PTEG_FROM_L2 ] = { .pme_name = "PM_PTEG_FROM_L2", .pme_code = 0x1c050, .pme_short_desc = "PTEG loaded from L2", .pme_long_desc = "A Page Table Entry was loaded into the ERAT from the local L2 due to a demand load or store.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_PTEG_FROM_L2], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_PTEG_FROM_L2] }, [ POWER7_PME_PM_MRK_DATA_FROM_L21_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L21_SHR_CYC", .pme_code = 0x20024, .pme_short_desc = "Marked ld latency Data source 0100 (L2.1 S)", .pme_long_desc = "Marked load latency Data source 0100 (L2.1 S)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_L21_SHR_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_L21_SHR_CYC] }, [ POWER7_PME_PM_MRK_DTLB_MISS_4K ] = { .pme_name = "PM_MRK_DTLB_MISS_4K", .pme_code = 0x2d05a, .pme_short_desc = "Marked Data TLB misses for 4K page", .pme_long_desc = "Data TLB references to 4KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DTLB_MISS_4K], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DTLB_MISS_4K] }, [ POWER7_PME_PM_VSU0_FPSCR ] = { .pme_name = "PM_VSU0_FPSCR", .pme_code = 0xb09c, .pme_short_desc = "Move to/from FPSCR type instruction issued on Pipe 0", .pme_long_desc = "Move to/from FPSCR type instruction issued on Pipe 0", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_FPSCR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_FPSCR] }, [ POWER7_PME_PM_VSU1_VECT_DOUBLE_ISSUED ] = { .pme_name = "PM_VSU1_VECT_DOUBLE_ISSUED", .pme_code = 0xb082, .pme_short_desc = "Double Precision vector instruction issued on Pipe1", .pme_long_desc = "Double Precision vector instruction issued on Pipe1", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_VECT_DOUBLE_ISSUED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_VECT_DOUBLE_ISSUED] }, [ POWER7_PME_PM_MRK_PTEG_FROM_RL2L3_MOD ] = { .pme_name = "PM_MRK_PTEG_FROM_RL2L3_MOD", .pme_code = 0x1d052, .pme_short_desc = "Marked PTEG loaded from remote L2 or L3 modified", .pme_long_desc = "A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a remote module due to a marked load or store.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_PTEG_FROM_RL2L3_MOD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_PTEG_FROM_RL2L3_MOD] }, [ POWER7_PME_PM_L2_LD_MISS ] = { .pme_name = "PM_L2_LD_MISS", .pme_code = 0x26080, .pme_short_desc = "Data Load Miss", .pme_long_desc = "Data Load Miss", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_LD_MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_LD_MISS] }, [ POWER7_PME_PM_VMX_RESULT_SAT_1 ] = { .pme_name = "PM_VMX_RESULT_SAT_1", .pme_code = 0xb0a0, .pme_short_desc = "Valid result with sat=1", .pme_long_desc = "Valid result with sat=1", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VMX_RESULT_SAT_1], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VMX_RESULT_SAT_1] }, [ POWER7_PME_PM_L1_PREF ] = { .pme_name = "PM_L1_PREF", .pme_code = 0xd8b8, .pme_short_desc = "L1 Prefetches", .pme_long_desc = "A request to prefetch data into the L1 was made", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L1_PREF], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L1_PREF] }, [ POWER7_PME_PM_MRK_DATA_FROM_LMEM_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_LMEM_CYC", .pme_code = 0x2002c, .pme_short_desc = "Marked ld latency Data Source 1100 (Local Memory)", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_LMEM_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_LMEM_CYC] }, [ POWER7_PME_PM_GRP_IC_MISS_NONSPEC ] = { .pme_name = "PM_GRP_IC_MISS_NONSPEC", .pme_code = 0x1000c, .pme_short_desc = "Group experienced non-speculative I cache miss", .pme_long_desc = "Number of groups, counted at completion, that have encountered an instruction cache miss.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_GRP_IC_MISS_NONSPEC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_GRP_IC_MISS_NONSPEC] }, [ POWER7_PME_PM_SHL_MERGED ] = { .pme_name = "PM_SHL_MERGED", .pme_code = 0x5084, .pme_short_desc = "SHL table entry merged with existing", .pme_long_desc = "SHL table entry merged with existing", .pme_event_ids = power7_event_ids[POWER7_PME_PM_SHL_MERGED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_SHL_MERGED] }, [ POWER7_PME_PM_DATA_FROM_L3 ] = { .pme_name = "PM_DATA_FROM_L3", .pme_code = 0x1c048, .pme_short_desc = "Data loaded from L3", .pme_long_desc = "The processor's Data Cache was reloaded from the local L3 due to a demand load.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_L3], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_L3] }, [ POWER7_PME_PM_LSU_FLUSH ] = { .pme_name = "PM_LSU_FLUSH", .pme_code = 0x208e, .pme_short_desc = "Flush initiated by LSU", .pme_long_desc = "A flush was initiated by the Load Store Unit.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_FLUSH], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_FLUSH] }, [ POWER7_PME_PM_LSU_SRQ_SYNC_COUNT ] = { .pme_name = "PM_LSU_SRQ_SYNC_COUNT", .pme_code = 0xd097, .pme_short_desc = "SRQ sync count (edge of PM_LSU_SRQ_SYNC_CYC)", .pme_long_desc = "SRQ sync count (edge of PM_LSU_SRQ_SYNC_CYC)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_SRQ_SYNC_COUNT], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_SRQ_SYNC_COUNT] }, [ POWER7_PME_PM_PMC2_OVERFLOW ] = { .pme_name = "PM_PMC2_OVERFLOW", .pme_code = 0x30010, .pme_short_desc = "Overflow from counter 2", .pme_long_desc = "Overflows from PMC2 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_PMC2_OVERFLOW], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_PMC2_OVERFLOW] }, [ POWER7_PME_PM_LSU_LDF ] = { .pme_name = "PM_LSU_LDF", .pme_code = 0xc884, .pme_short_desc = "All Scalar Loads", .pme_long_desc = "LSU executed Floating Point load instruction. Combined Unit 0 + 1.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_LDF], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_LDF] }, [ POWER7_PME_PM_POWER_EVENT3 ] = { .pme_name = "PM_POWER_EVENT3", .pme_code = 0x3006e, .pme_short_desc = "Power Management Event 3", .pme_long_desc = "Power Management Event 3", .pme_event_ids = power7_event_ids[POWER7_PME_PM_POWER_EVENT3], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_POWER_EVENT3] }, [ POWER7_PME_PM_DISP_WT ] = { .pme_name = "PM_DISP_WT", .pme_code = 0x30008, .pme_short_desc = "Dispatched Starved (not held", .pme_long_desc = " nothing to dispatch)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DISP_WT], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DISP_WT] }, [ POWER7_PME_PM_CMPLU_STALL_REJECT ] = { .pme_name = "PM_CMPLU_STALL_REJECT", .pme_code = 0x40016, .pme_short_desc = "Completion stall caused by reject", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a load/store reject. This is a subset of PM_CMPLU_STALL_LSU.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_CMPLU_STALL_REJECT], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_CMPLU_STALL_REJECT] }, [ POWER7_PME_PM_IC_BANK_CONFLICT ] = { .pme_name = "PM_IC_BANK_CONFLICT", .pme_code = 0x4082, .pme_short_desc = "Read blocked due to interleave conflict. ", .pme_long_desc = "Read blocked due to interleave conflict. ", .pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_BANK_CONFLICT], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_BANK_CONFLICT] }, [ POWER7_PME_PM_BR_MPRED_CR_TA ] = { .pme_name = "PM_BR_MPRED_CR_TA", .pme_code = 0x48ae, .pme_short_desc = "Branch mispredict - taken/not taken and target", .pme_long_desc = "Branch mispredict - taken/not taken and target", .pme_event_ids = power7_event_ids[POWER7_PME_PM_BR_MPRED_CR_TA], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_BR_MPRED_CR_TA] }, [ POWER7_PME_PM_L2_INST_MISS ] = { .pme_name = "PM_L2_INST_MISS", .pme_code = 0x36082, .pme_short_desc = "Instruction Load Misses", .pme_long_desc = "Instruction Load Misses", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_INST_MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_INST_MISS] }, [ POWER7_PME_PM_CMPLU_STALL_ERAT_MISS ] = { .pme_name = "PM_CMPLU_STALL_ERAT_MISS", .pme_code = 0x40018, .pme_short_desc = "Completion stall caused by ERAT miss", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered an ERAT miss. This is a subset of PM_CMPLU_STALL_REJECT.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_CMPLU_STALL_ERAT_MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_CMPLU_STALL_ERAT_MISS] }, [ POWER7_PME_PM_MRK_LSU_FLUSH ] = { .pme_name = "PM_MRK_LSU_FLUSH", .pme_code = 0xd08c, .pme_short_desc = "Flush: (marked) : All Cases", .pme_long_desc = "Marked flush initiated by LSU", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LSU_FLUSH], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LSU_FLUSH] }, [ POWER7_PME_PM_L2_LDST ] = { .pme_name = "PM_L2_LDST", .pme_code = 0x16880, .pme_short_desc = "Data Load+Store Count", .pme_long_desc = "Data Load+Store Count", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_LDST], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_LDST] }, [ POWER7_PME_PM_INST_FROM_L31_SHR ] = { .pme_name = "PM_INST_FROM_L31_SHR", .pme_code = 0x1404e, .pme_short_desc = "Instruction fetched from another L3 on same chip shared", .pme_long_desc = "Instruction fetched from another L3 on same chip shared", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_L31_SHR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_L31_SHR] }, [ POWER7_PME_PM_VSU0_FIN ] = { .pme_name = "PM_VSU0_FIN", .pme_code = 0xa0bc, .pme_short_desc = "VSU0 Finished an instruction", .pme_long_desc = "VSU0 Finished an instruction", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_FIN], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_FIN] }, [ POWER7_PME_PM_LARX_LSU ] = { .pme_name = "PM_LARX_LSU", .pme_code = 0xc894, .pme_short_desc = "Larx Finished", .pme_long_desc = "Larx Finished", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LARX_LSU], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LARX_LSU] }, [ POWER7_PME_PM_INST_FROM_RMEM ] = { .pme_name = "PM_INST_FROM_RMEM", .pme_code = 0x34042, .pme_short_desc = "Instruction fetched from remote memory", .pme_long_desc = "An instruction fetch group was fetched from memory attached to a different module than this proccessor is located on. Fetch groups can contain up to 8 instructions", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_RMEM], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_RMEM] }, [ POWER7_PME_PM_DISP_CLB_HELD_TLBIE ] = { .pme_name = "PM_DISP_CLB_HELD_TLBIE", .pme_code = 0x2096, .pme_short_desc = "Dispatch Hold: Due to TLBIE", .pme_long_desc = "Dispatch Hold: Due to TLBIE", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DISP_CLB_HELD_TLBIE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DISP_CLB_HELD_TLBIE] }, [ POWER7_PME_PM_MRK_DATA_FROM_DMEM_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_DMEM_CYC", .pme_code = 0x2002e, .pme_short_desc = "Marked ld latency Data Source 1110 (Distant Memory)", .pme_long_desc = "Marked ld latency Data Source 1110 (Distant Memory)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_DMEM_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_DMEM_CYC] }, [ POWER7_PME_PM_BR_PRED_CR ] = { .pme_name = "PM_BR_PRED_CR", .pme_code = 0x40a8, .pme_short_desc = "Branch predict - taken/not taken", .pme_long_desc = "A conditional branch instruction was predicted as taken or not taken.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_BR_PRED_CR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_BR_PRED_CR] }, [ POWER7_PME_PM_LSU_REJECT ] = { .pme_name = "PM_LSU_REJECT", .pme_code = 0x10064, .pme_short_desc = "LSU Reject (up to 2 per cycle)", .pme_long_desc = "The Load Store Unit rejected an instruction. Combined Unit 0 + 1", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_REJECT], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_REJECT] }, [ POWER7_PME_PM_CMPLU_STALL_END_GCT_NOSLOT ] = { .pme_name = "PM_CMPLU_STALL_END_GCT_NOSLOT", .pme_code = 0x10028, .pme_short_desc = "Count ended because GCT went empty", .pme_long_desc = "Count ended because GCT went empty", .pme_event_ids = power7_event_ids[POWER7_PME_PM_CMPLU_STALL_END_GCT_NOSLOT], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_CMPLU_STALL_END_GCT_NOSLOT] }, [ POWER7_PME_PM_LSU0_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU0_REJECT_LMQ_FULL", .pme_code = 0xc0a4, .pme_short_desc = "LS0 Reject: LMQ Full (LHR)", .pme_long_desc = "Total cycles the Load Store Unit 0 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_REJECT_LMQ_FULL], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_REJECT_LMQ_FULL] }, [ POWER7_PME_PM_VSU_FEST ] = { .pme_name = "PM_VSU_FEST", .pme_code = 0xa8b8, .pme_short_desc = "Estimate instruction executed", .pme_long_desc = "Estimate instruction executed", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_FEST], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_FEST] }, [ POWER7_PME_PM_PTEG_FROM_L3 ] = { .pme_name = "PM_PTEG_FROM_L3", .pme_code = 0x2c050, .pme_short_desc = "PTEG loaded from L3", .pme_long_desc = "A Page Table Entry was loaded into the TLB from the local L3 due to a demand load.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_PTEG_FROM_L3], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_PTEG_FROM_L3] }, [ POWER7_PME_PM_POWER_EVENT2 ] = { .pme_name = "PM_POWER_EVENT2", .pme_code = 0x2006e, .pme_short_desc = "Power Management Event 2", .pme_long_desc = "Power Management Event 2", .pme_event_ids = power7_event_ids[POWER7_PME_PM_POWER_EVENT2], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_POWER_EVENT2] }, [ POWER7_PME_PM_IC_PREF_CANCEL_PAGE ] = { .pme_name = "PM_IC_PREF_CANCEL_PAGE", .pme_code = 0x4090, .pme_short_desc = "Prefetch Canceled due to page boundary", .pme_long_desc = "Prefetch Canceled due to page boundary", .pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_PREF_CANCEL_PAGE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_PREF_CANCEL_PAGE] }, [ POWER7_PME_PM_VSU0_FSQRT_FDIV ] = { .pme_name = "PM_VSU0_FSQRT_FDIV", .pme_code = 0xa088, .pme_short_desc = "four flops operation (fdiv", .pme_long_desc = "fsqrt", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_FSQRT_FDIV], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_FSQRT_FDIV] }, [ POWER7_PME_PM_MRK_GRP_CMPL ] = { .pme_name = "PM_MRK_GRP_CMPL", .pme_code = 0x40030, .pme_short_desc = "Marked group complete", .pme_long_desc = "A group containing a sampled instruction completed. Microcoded instructions that span multiple groups will generate this event once per group.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_GRP_CMPL], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_GRP_CMPL] }, [ POWER7_PME_PM_VSU0_SCAL_DOUBLE_ISSUED ] = { .pme_name = "PM_VSU0_SCAL_DOUBLE_ISSUED", .pme_code = 0xb088, .pme_short_desc = "Double Precision scalar instruction issued on Pipe0", .pme_long_desc = "Double Precision scalar instruction issued on Pipe0", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_SCAL_DOUBLE_ISSUED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_SCAL_DOUBLE_ISSUED] }, [ POWER7_PME_PM_GRP_DISP ] = { .pme_name = "PM_GRP_DISP", .pme_code = 0x3000a, .pme_short_desc = "dispatch_success (Group Dispatched)", .pme_long_desc = "A group was dispatched", .pme_event_ids = power7_event_ids[POWER7_PME_PM_GRP_DISP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_GRP_DISP] }, [ POWER7_PME_PM_LSU0_LDX ] = { .pme_name = "PM_LSU0_LDX", .pme_code = 0xc088, .pme_short_desc = "LS0 Vector Loads", .pme_long_desc = "LS0 Vector Loads", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_LDX], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_LDX] }, [ POWER7_PME_PM_DATA_FROM_L2 ] = { .pme_name = "PM_DATA_FROM_L2", .pme_code = 0x1c040, .pme_short_desc = "Data loaded from L2", .pme_long_desc = "The processor's Data Cache was reloaded from the local L2 due to a demand load.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_L2], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_L2] }, [ POWER7_PME_PM_MRK_DATA_FROM_RL2L3_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_RL2L3_MOD", .pme_code = 0x1d042, .pme_short_desc = "Marked data loaded from remote L2 or L3 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a remote module due to a marked load.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_RL2L3_MOD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_RL2L3_MOD] }, [ POWER7_PME_PM_LD_REF_L1 ] = { .pme_name = "PM_LD_REF_L1", .pme_code = 0xc880, .pme_short_desc = " L1 D cache load references counted at finish", .pme_long_desc = " L1 D cache load references counted at finish", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LD_REF_L1], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LD_REF_L1] }, [ POWER7_PME_PM_VSU0_VECT_DOUBLE_ISSUED ] = { .pme_name = "PM_VSU0_VECT_DOUBLE_ISSUED", .pme_code = 0xb080, .pme_short_desc = "Double Precision vector instruction issued on Pipe0", .pme_long_desc = "Double Precision vector instruction issued on Pipe0", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_VECT_DOUBLE_ISSUED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_VECT_DOUBLE_ISSUED] }, [ POWER7_PME_PM_VSU1_2FLOP_DOUBLE ] = { .pme_name = "PM_VSU1_2FLOP_DOUBLE", .pme_code = 0xa08e, .pme_short_desc = "two flop DP vector operation (xvadddp", .pme_long_desc = " xvmuldp", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_2FLOP_DOUBLE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_2FLOP_DOUBLE] }, [ POWER7_PME_PM_THRD_PRIO_6_7_CYC ] = { .pme_name = "PM_THRD_PRIO_6_7_CYC", .pme_code = 0x40b6, .pme_short_desc = " Cycles thread running at priority level 6 or 7", .pme_long_desc = " Cycles thread running at priority level 6 or 7", .pme_event_ids = power7_event_ids[POWER7_PME_PM_THRD_PRIO_6_7_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_THRD_PRIO_6_7_CYC] }, [ POWER7_PME_PM_BR_MPRED_CR ] = { .pme_name = "PM_BR_MPRED_CR", .pme_code = 0x40ac, .pme_short_desc = "Branch mispredict - taken/not taken", .pme_long_desc = "A conditional branch instruction was incorrectly predicted as taken or not taken. The branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_BR_MPRED_CR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_BR_MPRED_CR] }, [ POWER7_PME_PM_LD_MISS_L1 ] = { .pme_name = "PM_LD_MISS_L1", .pme_code = 0x400f0, .pme_short_desc = "Load Missed L1", .pme_long_desc = "Load references that miss the Level 1 Data cache. Combined unit 0 + 1.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LD_MISS_L1], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LD_MISS_L1] }, [ POWER7_PME_PM_DATA_FROM_RL2L3_MOD ] = { .pme_name = "PM_DATA_FROM_RL2L3_MOD", .pme_code = 0x1c042, .pme_short_desc = "Data loaded from remote L2 or L3 modified", .pme_long_desc = "The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a remote module due to a demand load", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_RL2L3_MOD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_RL2L3_MOD] }, [ POWER7_PME_PM_LSU_SRQ_FULL_CYC ] = { .pme_name = "PM_LSU_SRQ_FULL_CYC", .pme_code = 0x1001a, .pme_short_desc = "Storage Queue is full and is blocking dispatch", .pme_long_desc = "Cycles the Store Request Queue is full.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_SRQ_FULL_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_SRQ_FULL_CYC] }, [ POWER7_PME_PM_TABLEWALK_CYC ] = { .pme_name = "PM_TABLEWALK_CYC", .pme_code = 0x10026, .pme_short_desc = "Cycles when a tablewalk (I or D) is active", .pme_long_desc = "Cycles doing instruction or data tablewalks", .pme_event_ids = power7_event_ids[POWER7_PME_PM_TABLEWALK_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_TABLEWALK_CYC] }, [ POWER7_PME_PM_MRK_PTEG_FROM_RMEM ] = { .pme_name = "PM_MRK_PTEG_FROM_RMEM", .pme_code = 0x3d052, .pme_short_desc = "Marked PTEG loaded from remote memory", .pme_long_desc = "A Page Table Entry was loaded into the ERAT. POWER6 does not have a TLB", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_PTEG_FROM_RMEM], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_PTEG_FROM_RMEM] }, [ POWER7_PME_PM_LSU_SRQ_STFWD ] = { .pme_name = "PM_LSU_SRQ_STFWD", .pme_code = 0xc8a0, .pme_short_desc = "Load got data from a store", .pme_long_desc = "Data from a store instruction was forwarded to a load. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. Combined Unit 0 + 1.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_SRQ_STFWD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_SRQ_STFWD] }, [ POWER7_PME_PM_INST_PTEG_FROM_RMEM ] = { .pme_name = "PM_INST_PTEG_FROM_RMEM", .pme_code = 0x3e052, .pme_short_desc = "Instruction PTEG loaded from remote memory", .pme_long_desc = "Instruction PTEG loaded from remote memory", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_PTEG_FROM_RMEM], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_PTEG_FROM_RMEM] }, [ POWER7_PME_PM_FXU0_FIN ] = { .pme_name = "PM_FXU0_FIN", .pme_code = 0x10004, .pme_short_desc = "FXU0 Finished", .pme_long_desc = "The Fixed Point unit 0 finished an instruction and produced a result. Instructions that finish may not necessary complete.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_FXU0_FIN], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_FXU0_FIN] }, [ POWER7_PME_PM_PTEG_FROM_L31_MOD ] = { .pme_name = "PM_PTEG_FROM_L31_MOD", .pme_code = 0x1c054, .pme_short_desc = "PTEG loaded from another L3 on same chip modified", .pme_long_desc = "PTEG loaded from another L3 on same chip modified", .pme_event_ids = power7_event_ids[POWER7_PME_PM_PTEG_FROM_L31_MOD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_PTEG_FROM_L31_MOD] }, [ POWER7_PME_PM_PMC5_OVERFLOW ] = { .pme_name = "PM_PMC5_OVERFLOW", .pme_code = 0x10024, .pme_short_desc = "Overflow from counter 5", .pme_long_desc = "Overflows from PMC5 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_PMC5_OVERFLOW], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_PMC5_OVERFLOW] }, [ POWER7_PME_PM_LD_REF_L1_LSU1 ] = { .pme_name = "PM_LD_REF_L1_LSU1", .pme_code = 0xc082, .pme_short_desc = "LS1 L1 D cache load references counted at finish", .pme_long_desc = "Load references to Level 1 Data Cache, by unit 1.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LD_REF_L1_LSU1], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LD_REF_L1_LSU1] }, [ POWER7_PME_PM_INST_PTEG_FROM_L21_SHR ] = { .pme_name = "PM_INST_PTEG_FROM_L21_SHR", .pme_code = 0x4e056, .pme_short_desc = "Instruction PTEG loaded from another L2 on same chip shared", .pme_long_desc = "Instruction PTEG loaded from another L2 on same chip shared", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_PTEG_FROM_L21_SHR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_PTEG_FROM_L21_SHR] }, [ POWER7_PME_PM_CMPLU_STALL_THRD ] = { .pme_name = "PM_CMPLU_STALL_THRD", .pme_code = 0x1001c, .pme_short_desc = "Completion Stalled due to thread conflict. Group ready to complete but it was another thread's turn", .pme_long_desc = "Completion Stalled due to thread conflict. Group ready to complete but it was another thread's turn", .pme_event_ids = power7_event_ids[POWER7_PME_PM_CMPLU_STALL_THRD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_CMPLU_STALL_THRD] }, [ POWER7_PME_PM_DATA_FROM_RMEM ] = { .pme_name = "PM_DATA_FROM_RMEM", .pme_code = 0x3c042, .pme_short_desc = "Data loaded from remote memory", .pme_long_desc = "The processor's Data Cache was reloaded from memory attached to a different module than this proccessor is located on.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_RMEM], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_RMEM] }, [ POWER7_PME_PM_VSU0_SCAL_SINGLE_ISSUED ] = { .pme_name = "PM_VSU0_SCAL_SINGLE_ISSUED", .pme_code = 0xb084, .pme_short_desc = "Single Precision scalar instruction issued on Pipe0", .pme_long_desc = "Single Precision scalar instruction issued on Pipe0", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_SCAL_SINGLE_ISSUED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_SCAL_SINGLE_ISSUED] }, [ POWER7_PME_PM_BR_MPRED_LSTACK ] = { .pme_name = "PM_BR_MPRED_LSTACK", .pme_code = 0x40a6, .pme_short_desc = "Branch Mispredict due to Link Stack", .pme_long_desc = "Branch Mispredict due to Link Stack", .pme_event_ids = power7_event_ids[POWER7_PME_PM_BR_MPRED_LSTACK], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_BR_MPRED_LSTACK] }, [ POWER7_PME_PM_NEST_8 ] = { .pme_name = "PM_NEST_8", .pme_code = 0x8f, .pme_short_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)", .pme_long_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_NEST_8], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_NEST_8] }, [ POWER7_PME_PM_MRK_DATA_FROM_RL2L3_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_RL2L3_MOD_CYC", .pme_code = 0x40028, .pme_short_desc = "Marked ld latency Data source 1001 (L2.5/L3.5 M same 4 chip node)", .pme_long_desc = "Marked ld latency Data source 1001 (L2.5/L3.5 M same 4 chip node)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_RL2L3_MOD_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_RL2L3_MOD_CYC] }, [ POWER7_PME_PM_LSU0_FLUSH_UST ] = { .pme_name = "PM_LSU0_FLUSH_UST", .pme_code = 0xc0b4, .pme_short_desc = "LS0 Flush: Unaligned Store", .pme_long_desc = "A store was flushed from unit 0 because it was unaligned (crossed a 4K boundary).", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_FLUSH_UST], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_FLUSH_UST] }, [ POWER7_PME_PM_LSU_NCST ] = { .pme_name = "PM_LSU_NCST", .pme_code = 0xc090, .pme_short_desc = "Non-cachable Stores sent to nest", .pme_long_desc = "Non-cachable Stores sent to nest", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_NCST], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_NCST] }, [ POWER7_PME_PM_BR_TAKEN ] = { .pme_name = "PM_BR_TAKEN", .pme_code = 0x20004, .pme_short_desc = "Branch Taken", .pme_long_desc = "A branch instruction was taken. This could have been a conditional branch or an unconditional branch", .pme_event_ids = power7_event_ids[POWER7_PME_PM_BR_TAKEN], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_BR_TAKEN] }, [ POWER7_PME_PM_INST_PTEG_FROM_LMEM ] = { .pme_name = "PM_INST_PTEG_FROM_LMEM", .pme_code = 0x4e052, .pme_short_desc = "Instruction PTEG loaded from local memory", .pme_long_desc = "Instruction PTEG loaded from local memory", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_PTEG_FROM_LMEM], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_PTEG_FROM_LMEM] }, [ POWER7_PME_PM_GCT_NOSLOT_BR_MPRED_IC_MISS ] = { .pme_name = "PM_GCT_NOSLOT_BR_MPRED_IC_MISS", .pme_code = 0x4001c, .pme_short_desc = "GCT empty by branch mispredict + IC miss", .pme_long_desc = "No slot in GCT caused by branch mispredict or I cache miss", .pme_event_ids = power7_event_ids[POWER7_PME_PM_GCT_NOSLOT_BR_MPRED_IC_MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_GCT_NOSLOT_BR_MPRED_IC_MISS] }, [ POWER7_PME_PM_DTLB_MISS_4K ] = { .pme_name = "PM_DTLB_MISS_4K", .pme_code = 0x2c05a, .pme_short_desc = "Data TLB miss for 4K page", .pme_long_desc = "Data TLB references to 4KB pages that missed the TLB. Page size is determined at TLB reload time.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DTLB_MISS_4K], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DTLB_MISS_4K] }, [ POWER7_PME_PM_PMC4_SAVED ] = { .pme_name = "PM_PMC4_SAVED", .pme_code = 0x30022, .pme_short_desc = "PMC4 Rewind Value saved (matched condition)", .pme_long_desc = "PMC4 was counting speculatively. The speculative condition was met and the counter value was committed by copying it to the backup register.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_PMC4_SAVED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_PMC4_SAVED] }, [ POWER7_PME_PM_VSU1_PERMUTE_ISSUED ] = { .pme_name = "PM_VSU1_PERMUTE_ISSUED", .pme_code = 0xb092, .pme_short_desc = "Permute VMX Instruction Issued", .pme_long_desc = "Permute VMX Instruction Issued", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_PERMUTE_ISSUED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_PERMUTE_ISSUED] }, [ POWER7_PME_PM_SLB_MISS ] = { .pme_name = "PM_SLB_MISS", .pme_code = 0xd890, .pme_short_desc = "Data + Instruction SLB Miss - Total of all segment sizes", .pme_long_desc = "Total of all Segment Lookaside Buffer (SLB) misses, Instructions + Data.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_SLB_MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_SLB_MISS] }, [ POWER7_PME_PM_LSU1_FLUSH_LRQ ] = { .pme_name = "PM_LSU1_FLUSH_LRQ", .pme_code = 0xc0ba, .pme_short_desc = "LS1 Flush: LRQ", .pme_long_desc = "Load Hit Load or Store Hit Load flush. A younger load was flushed from unit 1 because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_FLUSH_LRQ], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_FLUSH_LRQ] }, [ POWER7_PME_PM_DTLB_MISS ] = { .pme_name = "PM_DTLB_MISS", .pme_code = 0x300fc, .pme_short_desc = "TLB reload valid", .pme_long_desc = "Data TLB misses, all page sizes.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DTLB_MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DTLB_MISS] }, [ POWER7_PME_PM_VSU1_FRSP ] = { .pme_name = "PM_VSU1_FRSP", .pme_code = 0xa0b6, .pme_short_desc = "Round to single precision instruction executed", .pme_long_desc = "Round to single precision instruction executed", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_FRSP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_FRSP] }, [ POWER7_PME_PM_VSU_VECTOR_DOUBLE_ISSUED ] = { .pme_name = "PM_VSU_VECTOR_DOUBLE_ISSUED", .pme_code = 0xb880, .pme_short_desc = "Double Precision vector instruction issued on Pipe0", .pme_long_desc = "Double Precision vector instruction issued on Pipe0", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_VECTOR_DOUBLE_ISSUED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_VECTOR_DOUBLE_ISSUED] }, [ POWER7_PME_PM_L2_CASTOUT_SHR ] = { .pme_name = "PM_L2_CASTOUT_SHR", .pme_code = 0x16182, .pme_short_desc = "L2 Castouts - Shared (T", .pme_long_desc = " Te", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_CASTOUT_SHR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_CASTOUT_SHR] }, [ POWER7_PME_PM_NEST_7 ] = { .pme_name = "PM_NEST_7", .pme_code = 0x8d, .pme_short_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)", .pme_long_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_NEST_7], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_NEST_7] }, [ POWER7_PME_PM_DATA_FROM_DL2L3_SHR ] = { .pme_name = "PM_DATA_FROM_DL2L3_SHR", .pme_code = 0x3c044, .pme_short_desc = "Data loaded from distant L2 or L3 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a distant module due to a demand load", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_DL2L3_SHR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_DL2L3_SHR] }, [ POWER7_PME_PM_VSU1_STF ] = { .pme_name = "PM_VSU1_STF", .pme_code = 0xb08e, .pme_short_desc = "FPU store (SP or DP) issued on Pipe1", .pme_long_desc = "FPU store (SP or DP) issued on Pipe1", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_STF], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_STF] }, [ POWER7_PME_PM_ST_FIN ] = { .pme_name = "PM_ST_FIN", .pme_code = 0x200f0, .pme_short_desc = "Store Instructions Finished", .pme_long_desc = "Store requests sent to the nest.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_ST_FIN], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_ST_FIN] }, [ POWER7_PME_PM_PTEG_FROM_L21_SHR ] = { .pme_name = "PM_PTEG_FROM_L21_SHR", .pme_code = 0x4c056, .pme_short_desc = "PTEG loaded from another L2 on same chip shared", .pme_long_desc = "PTEG loaded from another L2 on same chip shared", .pme_event_ids = power7_event_ids[POWER7_PME_PM_PTEG_FROM_L21_SHR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_PTEG_FROM_L21_SHR] }, [ POWER7_PME_PM_L2_LOC_GUESS_WRONG ] = { .pme_name = "PM_L2_LOC_GUESS_WRONG", .pme_code = 0x26480, .pme_short_desc = "L2 guess loc and guess was not correct (ie data remote)", .pme_long_desc = "L2 guess loc and guess was not correct (ie data remote)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_LOC_GUESS_WRONG], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_LOC_GUESS_WRONG] }, [ POWER7_PME_PM_MRK_STCX_FAIL ] = { .pme_name = "PM_MRK_STCX_FAIL", .pme_code = 0xd08e, .pme_short_desc = "Marked STCX failed", .pme_long_desc = "A marked stcx (stwcx or stdcx) failed", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_STCX_FAIL], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_STCX_FAIL] }, [ POWER7_PME_PM_LSU0_REJECT_LHS ] = { .pme_name = "PM_LSU0_REJECT_LHS", .pme_code = 0xc0ac, .pme_short_desc = "LS0 Reject: Load Hit Store", .pme_long_desc = "Load Store Unit 0 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_REJECT_LHS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_REJECT_LHS] }, [ POWER7_PME_PM_IC_PREF_CANCEL_HIT ] = { .pme_name = "PM_IC_PREF_CANCEL_HIT", .pme_code = 0x4092, .pme_short_desc = "Prefetch Canceled due to icache hit", .pme_long_desc = "Prefetch Canceled due to icache hit", .pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_PREF_CANCEL_HIT], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_PREF_CANCEL_HIT] }, [ POWER7_PME_PM_L3_PREF_BUSY ] = { .pme_name = "PM_L3_PREF_BUSY", .pme_code = 0x4f080, .pme_short_desc = "Prefetch machines >= threshold (8", .pme_long_desc = "16", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L3_PREF_BUSY], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L3_PREF_BUSY] }, [ POWER7_PME_PM_MRK_BRU_FIN ] = { .pme_name = "PM_MRK_BRU_FIN", .pme_code = 0x2003a, .pme_short_desc = "bru marked instr finish", .pme_long_desc = "The branch unit finished a marked instruction. Instructions that finish may not necessary complete.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_BRU_FIN], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_BRU_FIN] }, [ POWER7_PME_PM_LSU1_NCLD ] = { .pme_name = "PM_LSU1_NCLD", .pme_code = 0xc08e, .pme_short_desc = "LS1 Non-cachable Loads counted at finish", .pme_long_desc = "A non-cacheable load was executed by Unit 0.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_NCLD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_NCLD] }, [ POWER7_PME_PM_INST_PTEG_FROM_L31_MOD ] = { .pme_name = "PM_INST_PTEG_FROM_L31_MOD", .pme_code = 0x1e054, .pme_short_desc = "Instruction PTEG loaded from another L3 on same chip modified", .pme_long_desc = "Instruction PTEG loaded from another L3 on same chip modified", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_PTEG_FROM_L31_MOD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_PTEG_FROM_L31_MOD] }, [ POWER7_PME_PM_LSU_NCLD ] = { .pme_name = "PM_LSU_NCLD", .pme_code = 0xc88c, .pme_short_desc = "Non-cachable Loads counted at finish", .pme_long_desc = "A non-cacheable load was executed. Combined Unit 0 + 1.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_NCLD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_NCLD] }, [ POWER7_PME_PM_LSU_LDX ] = { .pme_name = "PM_LSU_LDX", .pme_code = 0xc888, .pme_short_desc = "All Vector loads (vsx vector + vmx vector)", .pme_long_desc = "All Vector loads (vsx vector + vmx vector)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_LDX], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_LDX] }, [ POWER7_PME_PM_L2_LOC_GUESS_CORRECT ] = { .pme_name = "PM_L2_LOC_GUESS_CORRECT", .pme_code = 0x16480, .pme_short_desc = "L2 guess loc and guess was correct (ie data local)", .pme_long_desc = "L2 guess loc and guess was correct (ie data local)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_LOC_GUESS_CORRECT], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_LOC_GUESS_CORRECT] }, [ POWER7_PME_PM_THRESH_TIMEO ] = { .pme_name = "PM_THRESH_TIMEO", .pme_code = 0x10038, .pme_short_desc = "Threshold timeout event", .pme_long_desc = "The threshold timer expired", .pme_event_ids = power7_event_ids[POWER7_PME_PM_THRESH_TIMEO], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_THRESH_TIMEO] }, [ POWER7_PME_PM_L3_PREF_ST ] = { .pme_name = "PM_L3_PREF_ST", .pme_code = 0xd0ae, .pme_short_desc = "L3 cache ST prefetches", .pme_long_desc = "L3 cache ST prefetches", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L3_PREF_ST], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L3_PREF_ST] }, [ POWER7_PME_PM_DISP_CLB_HELD_SYNC ] = { .pme_name = "PM_DISP_CLB_HELD_SYNC", .pme_code = 0x2098, .pme_short_desc = "Dispatch/CLB Hold: Sync type instruction", .pme_long_desc = "Dispatch/CLB Hold: Sync type instruction", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DISP_CLB_HELD_SYNC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DISP_CLB_HELD_SYNC] }, [ POWER7_PME_PM_VSU_SIMPLE_ISSUED ] = { .pme_name = "PM_VSU_SIMPLE_ISSUED", .pme_code = 0xb894, .pme_short_desc = "Simple VMX instruction issued", .pme_long_desc = "Simple VMX instruction issued", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_SIMPLE_ISSUED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_SIMPLE_ISSUED] }, [ POWER7_PME_PM_VSU1_SINGLE ] = { .pme_name = "PM_VSU1_SINGLE", .pme_code = 0xa0aa, .pme_short_desc = "FPU single precision", .pme_long_desc = "VSU1 executed single precision instruction", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_SINGLE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_SINGLE] }, [ POWER7_PME_PM_DATA_TABLEWALK_CYC ] = { .pme_name = "PM_DATA_TABLEWALK_CYC", .pme_code = 0x3001a, .pme_short_desc = "Data Tablewalk Active", .pme_long_desc = "Cycles a translation tablewalk is active. While a tablewalk is active any request attempting to access the TLB will be rejected and retried.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_TABLEWALK_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_TABLEWALK_CYC] }, [ POWER7_PME_PM_L2_RC_ST_DONE ] = { .pme_name = "PM_L2_RC_ST_DONE", .pme_code = 0x36380, .pme_short_desc = "RC did st to line that was Tx or Sx", .pme_long_desc = "RC did st to line that was Tx or Sx", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_RC_ST_DONE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_RC_ST_DONE] }, [ POWER7_PME_PM_MRK_PTEG_FROM_L21_MOD ] = { .pme_name = "PM_MRK_PTEG_FROM_L21_MOD", .pme_code = 0x3d056, .pme_short_desc = "Marked PTEG loaded from another L2 on same chip modified", .pme_long_desc = "Marked PTEG loaded from another L2 on same chip modified", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_PTEG_FROM_L21_MOD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_PTEG_FROM_L21_MOD] }, [ POWER7_PME_PM_LARX_LSU1 ] = { .pme_name = "PM_LARX_LSU1", .pme_code = 0xc096, .pme_short_desc = "ls1 Larx Finished", .pme_long_desc = "A larx (lwarx or ldarx) was executed on side 1 ", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LARX_LSU1], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LARX_LSU1] }, [ POWER7_PME_PM_MRK_DATA_FROM_RMEM ] = { .pme_name = "PM_MRK_DATA_FROM_RMEM", .pme_code = 0x3d042, .pme_short_desc = "Marked data loaded from remote memory", .pme_long_desc = "The processor's Data Cache was reloaded due to a marked load from memory attached to a different module than this proccessor is located on.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_RMEM], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_RMEM] }, [ POWER7_PME_PM_DISP_CLB_HELD ] = { .pme_name = "PM_DISP_CLB_HELD", .pme_code = 0x2090, .pme_short_desc = "CLB Hold: Any Reason", .pme_long_desc = "CLB Hold: Any Reason", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DISP_CLB_HELD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DISP_CLB_HELD] }, [ POWER7_PME_PM_DERAT_MISS_4K ] = { .pme_name = "PM_DERAT_MISS_4K", .pme_code = 0x1c05c, .pme_short_desc = "DERAT misses for 4K page", .pme_long_desc = "A data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DERAT_MISS_4K], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DERAT_MISS_4K] }, [ POWER7_PME_PM_L2_RCLD_DISP_FAIL_ADDR ] = { .pme_name = "PM_L2_RCLD_DISP_FAIL_ADDR", .pme_code = 0x16282, .pme_short_desc = " L2 RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_long_desc = " L2 RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_RCLD_DISP_FAIL_ADDR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_RCLD_DISP_FAIL_ADDR] }, [ POWER7_PME_PM_SEG_EXCEPTION ] = { .pme_name = "PM_SEG_EXCEPTION", .pme_code = 0x28a4, .pme_short_desc = "ISEG + DSEG Exception", .pme_long_desc = "ISEG + DSEG Exception", .pme_event_ids = power7_event_ids[POWER7_PME_PM_SEG_EXCEPTION], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_SEG_EXCEPTION] }, [ POWER7_PME_PM_FLUSH_DISP_SB ] = { .pme_name = "PM_FLUSH_DISP_SB", .pme_code = 0x208c, .pme_short_desc = "Dispatch Flush: Scoreboard", .pme_long_desc = "Dispatch Flush: Scoreboard", .pme_event_ids = power7_event_ids[POWER7_PME_PM_FLUSH_DISP_SB], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_FLUSH_DISP_SB] }, [ POWER7_PME_PM_L2_DC_INV ] = { .pme_name = "PM_L2_DC_INV", .pme_code = 0x26182, .pme_short_desc = "Dcache invalidates from L2 ", .pme_long_desc = "The L2 invalidated a line in processor's data cache. This is caused by the L2 line being cast out or invalidated. Total for all slices", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_DC_INV], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_DC_INV] }, [ POWER7_PME_PM_PTEG_FROM_DL2L3_MOD ] = { .pme_name = "PM_PTEG_FROM_DL2L3_MOD", .pme_code = 0x4c054, .pme_short_desc = "PTEG loaded from distant L2 or L3 modified", .pme_long_desc = "A Page Table Entry was loaded into the ERAT with modified (M) data from an L2 or L3 on a distant module due to a demand load or store.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_PTEG_FROM_DL2L3_MOD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_PTEG_FROM_DL2L3_MOD] }, [ POWER7_PME_PM_DSEG ] = { .pme_name = "PM_DSEG", .pme_code = 0x20a6, .pme_short_desc = "DSEG Exception", .pme_long_desc = "DSEG Exception", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DSEG], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DSEG] }, [ POWER7_PME_PM_BR_PRED_LSTACK ] = { .pme_name = "PM_BR_PRED_LSTACK", .pme_code = 0x40a2, .pme_short_desc = "Link Stack Predictions", .pme_long_desc = "The target address of a Branch to Link instruction was predicted by the link stack.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_BR_PRED_LSTACK], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_BR_PRED_LSTACK] }, [ POWER7_PME_PM_VSU0_STF ] = { .pme_name = "PM_VSU0_STF", .pme_code = 0xb08c, .pme_short_desc = "FPU store (SP or DP) issued on Pipe0", .pme_long_desc = "FPU store (SP or DP) issued on Pipe0", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_STF], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_STF] }, [ POWER7_PME_PM_LSU_FX_FIN ] = { .pme_name = "PM_LSU_FX_FIN", .pme_code = 0x10066, .pme_short_desc = "LSU Finished a FX operation (up to 2 per cycle)", .pme_long_desc = "LSU Finished a FX operation (up to 2 per cycle)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_FX_FIN], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_FX_FIN] }, [ POWER7_PME_PM_DERAT_MISS_16M ] = { .pme_name = "PM_DERAT_MISS_16M", .pme_code = 0x3c05c, .pme_short_desc = "DERAT misses for 16M page", .pme_long_desc = "A data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DERAT_MISS_16M], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DERAT_MISS_16M] }, [ POWER7_PME_PM_MRK_PTEG_FROM_DL2L3_MOD ] = { .pme_name = "PM_MRK_PTEG_FROM_DL2L3_MOD", .pme_code = 0x4d054, .pme_short_desc = "Marked PTEG loaded from distant L2 or L3 modified", .pme_long_desc = "A Page Table Entry was loaded into the ERAT with modified (M) data from an L2 or L3 on a distant module due to a marked load or store.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_PTEG_FROM_DL2L3_MOD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_PTEG_FROM_DL2L3_MOD] }, [ POWER7_PME_PM_INST_FROM_L3 ] = { .pme_name = "PM_INST_FROM_L3", .pme_code = 0x14048, .pme_short_desc = "Instruction fetched from L3", .pme_long_desc = "An instruction fetch group was fetched from L3. Fetch Groups can contain up to 8 instructions", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_L3], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_L3] }, [ POWER7_PME_PM_MRK_IFU_FIN ] = { .pme_name = "PM_MRK_IFU_FIN", .pme_code = 0x3003a, .pme_short_desc = "IFU non-branch marked instruction finished", .pme_long_desc = "The Instruction Fetch Unit finished a marked instruction.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_IFU_FIN], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_IFU_FIN] }, [ POWER7_PME_PM_ITLB_MISS ] = { .pme_name = "PM_ITLB_MISS", .pme_code = 0x400fc, .pme_short_desc = "ITLB Reloaded (always zero on POWER6)", .pme_long_desc = "A TLB miss for an Instruction Fetch has occurred", .pme_event_ids = power7_event_ids[POWER7_PME_PM_ITLB_MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_ITLB_MISS] }, [ POWER7_PME_PM_VSU_STF ] = { .pme_name = "PM_VSU_STF", .pme_code = 0xb88c, .pme_short_desc = "FPU store (SP or DP) issued on Pipe0", .pme_long_desc = "FPU store (SP or DP) issued on Pipe0", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_STF], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_STF] }, [ POWER7_PME_PM_LSU_FLUSH_UST ] = { .pme_name = "PM_LSU_FLUSH_UST", .pme_code = 0xc8b4, .pme_short_desc = "Flush: Unaligned Store", .pme_long_desc = "A store was flushed because it was unaligned (crossed a 4K boundary). Combined Unit 0 + 1.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_FLUSH_UST], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_FLUSH_UST] }, [ POWER7_PME_PM_L2_LDST_MISS ] = { .pme_name = "PM_L2_LDST_MISS", .pme_code = 0x26880, .pme_short_desc = "Data Load+Store Miss", .pme_long_desc = "Data Load+Store Miss", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_LDST_MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_LDST_MISS] }, [ POWER7_PME_PM_FXU1_FIN ] = { .pme_name = "PM_FXU1_FIN", .pme_code = 0x40004, .pme_short_desc = "FXU1 Finished", .pme_long_desc = "The Fixed Point unit 1 finished an instruction and produced a result. Instructions that finish may not necessary complete.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_FXU1_FIN], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_FXU1_FIN] }, [ POWER7_PME_PM_SHL_DEALLOCATED ] = { .pme_name = "PM_SHL_DEALLOCATED", .pme_code = 0x5080, .pme_short_desc = "SHL Table entry deallocated", .pme_long_desc = "SHL Table entry deallocated", .pme_event_ids = power7_event_ids[POWER7_PME_PM_SHL_DEALLOCATED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_SHL_DEALLOCATED] }, [ POWER7_PME_PM_L2_SN_M_WR_DONE ] = { .pme_name = "PM_L2_SN_M_WR_DONE", .pme_code = 0x46382, .pme_short_desc = "SNP dispatched for a write and was M", .pme_long_desc = "SNP dispatched for a write and was M", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_SN_M_WR_DONE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_SN_M_WR_DONE] }, [ POWER7_PME_PM_LSU_REJECT_SET_MPRED ] = { .pme_name = "PM_LSU_REJECT_SET_MPRED", .pme_code = 0xc8a8, .pme_short_desc = "Reject: Set Predict Wrong", .pme_long_desc = "The Load Store Unit rejected an instruction because the cache set was improperly predicted. This is a fast reject and will be immediately redispatched. Combined Unit 0 + 1", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_REJECT_SET_MPRED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_REJECT_SET_MPRED] }, [ POWER7_PME_PM_L3_PREF_LD ] = { .pme_name = "PM_L3_PREF_LD", .pme_code = 0xd0ac, .pme_short_desc = "L3 cache LD prefetches", .pme_long_desc = "L3 cache LD prefetches", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L3_PREF_LD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L3_PREF_LD] }, [ POWER7_PME_PM_L2_SN_M_RD_DONE ] = { .pme_name = "PM_L2_SN_M_RD_DONE", .pme_code = 0x46380, .pme_short_desc = "SNP dispatched for a read and was M", .pme_long_desc = "SNP dispatched for a read and was M", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_SN_M_RD_DONE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_SN_M_RD_DONE] }, [ POWER7_PME_PM_MRK_DERAT_MISS_16G ] = { .pme_name = "PM_MRK_DERAT_MISS_16G", .pme_code = 0x4d05c, .pme_short_desc = "Marked DERAT misses for 16G page", .pme_long_desc = "A marked data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DERAT_MISS_16G], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DERAT_MISS_16G] }, [ POWER7_PME_PM_VSU_FCONV ] = { .pme_name = "PM_VSU_FCONV", .pme_code = 0xa8b0, .pme_short_desc = "Convert instruction executed", .pme_long_desc = "Convert instruction executed", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_FCONV], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_FCONV] }, [ POWER7_PME_PM_ANY_THRD_RUN_CYC ] = { .pme_name = "PM_ANY_THRD_RUN_CYC", .pme_code = 0x100fa, .pme_short_desc = "One of threads in run_cycles ", .pme_long_desc = "One of threads in run_cycles ", .pme_event_ids = power7_event_ids[POWER7_PME_PM_ANY_THRD_RUN_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_ANY_THRD_RUN_CYC] }, [ POWER7_PME_PM_LSU_LMQ_FULL_CYC ] = { .pme_name = "PM_LSU_LMQ_FULL_CYC", .pme_code = 0xd0a4, .pme_short_desc = "LMQ full", .pme_long_desc = "The Load Miss Queue was full.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_LMQ_FULL_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_LMQ_FULL_CYC] }, [ POWER7_PME_PM_MRK_LSU_REJECT_LHS ] = { .pme_name = "PM_MRK_LSU_REJECT_LHS", .pme_code = 0xd082, .pme_short_desc = " Reject(marked): Load Hit Store", .pme_long_desc = "The Load Store Unit rejected a marked load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LSU_REJECT_LHS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LSU_REJECT_LHS] }, [ POWER7_PME_PM_MRK_LD_MISS_L1_CYC ] = { .pme_name = "PM_MRK_LD_MISS_L1_CYC", .pme_code = 0x4003e, .pme_short_desc = "L1 data load miss cycles", .pme_long_desc = "L1 data load miss cycles", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LD_MISS_L1_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LD_MISS_L1_CYC] }, [ POWER7_PME_PM_MRK_DATA_FROM_L2_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L2_CYC", .pme_code = 0x20020, .pme_short_desc = "Marked ld latency Data source 0000 (L2 hit)", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_L2_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_L2_CYC] }, [ POWER7_PME_PM_INST_IMC_MATCH_DISP ] = { .pme_name = "PM_INST_IMC_MATCH_DISP", .pme_code = 0x30016, .pme_short_desc = "IMC Matches dispatched", .pme_long_desc = "IMC Matches dispatched", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_IMC_MATCH_DISP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_IMC_MATCH_DISP] }, [ POWER7_PME_PM_MRK_DATA_FROM_RMEM_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_RMEM_CYC", .pme_code = 0x4002c, .pme_short_desc = "Marked ld latency Data source 1101 (Memory same 4 chip node)", .pme_long_desc = "Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_RMEM_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_RMEM_CYC] }, [ POWER7_PME_PM_VSU0_SIMPLE_ISSUED ] = { .pme_name = "PM_VSU0_SIMPLE_ISSUED", .pme_code = 0xb094, .pme_short_desc = "Simple VMX instruction issued", .pme_long_desc = "Simple VMX instruction issued", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_SIMPLE_ISSUED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_SIMPLE_ISSUED] }, [ POWER7_PME_PM_CMPLU_STALL_DIV ] = { .pme_name = "PM_CMPLU_STALL_DIV", .pme_code = 0x40014, .pme_short_desc = "Completion stall caused by DIV instruction", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point divide instruction. This is a subset of PM_CMPLU_STALL_FXU.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_CMPLU_STALL_DIV], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_CMPLU_STALL_DIV] }, [ POWER7_PME_PM_MRK_PTEG_FROM_RL2L3_SHR ] = { .pme_name = "PM_MRK_PTEG_FROM_RL2L3_SHR", .pme_code = 0x2d054, .pme_short_desc = "Marked PTEG loaded from remote L2 or L3 shared", .pme_long_desc = "A Page Table Entry was loaded into the ERAT from memory attached to a different module than this proccessor is located on due to a marked load or store.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_PTEG_FROM_RL2L3_SHR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_PTEG_FROM_RL2L3_SHR] }, [ POWER7_PME_PM_VSU_FMA_DOUBLE ] = { .pme_name = "PM_VSU_FMA_DOUBLE", .pme_code = 0xa890, .pme_short_desc = "DP vector version of fmadd", .pme_long_desc = "fnmadd", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_FMA_DOUBLE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_FMA_DOUBLE] }, [ POWER7_PME_PM_VSU_4FLOP ] = { .pme_name = "PM_VSU_4FLOP", .pme_code = 0xa89c, .pme_short_desc = "four flops operation (scalar fdiv", .pme_long_desc = " fsqrt; DP vector version of fmadd", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_4FLOP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_4FLOP] }, [ POWER7_PME_PM_VSU1_FIN ] = { .pme_name = "PM_VSU1_FIN", .pme_code = 0xa0be, .pme_short_desc = "VSU1 Finished an instruction", .pme_long_desc = "VSU1 Finished an instruction", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_FIN], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_FIN] }, [ POWER7_PME_PM_INST_PTEG_FROM_RL2L3_MOD ] = { .pme_name = "PM_INST_PTEG_FROM_RL2L3_MOD", .pme_code = 0x1e052, .pme_short_desc = "Instruction PTEG loaded from remote L2 or L3 modified", .pme_long_desc = "Instruction PTEG loaded from remote L2 or L3 modified", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_PTEG_FROM_RL2L3_MOD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_PTEG_FROM_RL2L3_MOD] }, [ POWER7_PME_PM_RUN_CYC ] = { .pme_name = "PM_RUN_CYC", .pme_code = 0x200f4, .pme_short_desc = "Run_cycles", .pme_long_desc = "Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_RUN_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_RUN_CYC] }, [ POWER7_PME_PM_PTEG_FROM_RMEM ] = { .pme_name = "PM_PTEG_FROM_RMEM", .pme_code = 0x3c052, .pme_short_desc = "PTEG loaded from remote memory", .pme_long_desc = "A Page Table Entry was loaded into the TLB from memory attached to a different module than this proccessor is located on.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_PTEG_FROM_RMEM], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_PTEG_FROM_RMEM] }, [ POWER7_PME_PM_LSU_LRQ_S0_VALID ] = { .pme_name = "PM_LSU_LRQ_S0_VALID", .pme_code = 0xd09e, .pme_short_desc = "Slot 0 of LRQ valid", .pme_long_desc = "This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the LRQ is split between the two threads (16 entries each).", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_LRQ_S0_VALID], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_LRQ_S0_VALID] }, [ POWER7_PME_PM_LSU0_LDF ] = { .pme_name = "PM_LSU0_LDF", .pme_code = 0xc084, .pme_short_desc = "LS0 Scalar Loads", .pme_long_desc = "A floating point load was executed by LSU0", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_LDF], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_LDF] }, [ POWER7_PME_PM_FLUSH_COMPLETION ] = { .pme_name = "PM_FLUSH_COMPLETION", .pme_code = 0x30012, .pme_short_desc = "Completion Flush", .pme_long_desc = "Completion Flush", .pme_event_ids = power7_event_ids[POWER7_PME_PM_FLUSH_COMPLETION], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_FLUSH_COMPLETION] }, [ POWER7_PME_PM_ST_MISS_L1 ] = { .pme_name = "PM_ST_MISS_L1", .pme_code = 0x300f0, .pme_short_desc = "L1 D cache store misses", .pme_long_desc = "A store missed the dcache. Combined Unit 0 + 1.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_ST_MISS_L1], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_ST_MISS_L1] }, [ POWER7_PME_PM_L2_NODE_PUMP ] = { .pme_name = "PM_L2_NODE_PUMP", .pme_code = 0x36480, .pme_short_desc = "RC req that was a local (aka node) pump attempt", .pme_long_desc = "RC req that was a local (aka node) pump attempt", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_NODE_PUMP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_NODE_PUMP] }, [ POWER7_PME_PM_INST_FROM_DL2L3_SHR ] = { .pme_name = "PM_INST_FROM_DL2L3_SHR", .pme_code = 0x34044, .pme_short_desc = "Instruction fetched from distant L2 or L3 shared", .pme_long_desc = "An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_DL2L3_SHR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_DL2L3_SHR] }, [ POWER7_PME_PM_MRK_STALL_CMPLU_CYC ] = { .pme_name = "PM_MRK_STALL_CMPLU_CYC", .pme_code = 0x3003e, .pme_short_desc = "Marked Group Completion Stall cycles ", .pme_long_desc = "Marked Group Completion Stall cycles ", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_STALL_CMPLU_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_STALL_CMPLU_CYC] }, [ POWER7_PME_PM_VSU1_DENORM ] = { .pme_name = "PM_VSU1_DENORM", .pme_code = 0xa0ae, .pme_short_desc = "FPU denorm operand", .pme_long_desc = "VSU1 received denormalized data", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_DENORM], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_DENORM] }, [ POWER7_PME_PM_MRK_DATA_FROM_L31_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L31_SHR_CYC", .pme_code = 0x20026, .pme_short_desc = "Marked ld latency Data source 0110 (L3.1 S) ", .pme_long_desc = "Marked load latency Data source 0110 (L3.1 S) ", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_L31_SHR_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_L31_SHR_CYC] }, [ POWER7_PME_PM_GCT_USAGE_1TO2_SLOT ] = { .pme_name = "PM_GCT_USAGE_1-2_SLOT", .pme_code = 0x209c, .pme_short_desc = "GCT Utilization 1-2 entries", .pme_long_desc = "GCT Utilization 1-2 entries", .pme_event_ids = power7_event_ids[POWER7_PME_PM_GCT_USAGE_1TO2_SLOT], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_GCT_USAGE_1TO2_SLOT] }, [ POWER7_PME_PM_NEST_6 ] = { .pme_name = "PM_NEST_6", .pme_code = 0x8b, .pme_short_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)", .pme_long_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_NEST_6], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_NEST_6] }, [ POWER7_PME_PM_INST_FROM_L3MISS ] = { .pme_name = "PM_INST_FROM_L3MISS", .pme_code = 0x24048, .pme_short_desc = "Instruction fetched missed L3", .pme_long_desc = "An instruction fetch group was fetched from beyond L3. Fetch groups can contain up to 8 instructions.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_L3MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_L3MISS] }, [ POWER7_PME_PM_EE_OFF_EXT_INT ] = { .pme_name = "PM_EE_OFF_EXT_INT", .pme_code = 0x2080, .pme_short_desc = "ee off and external interrupt", .pme_long_desc = "Cycles when an interrupt due to an external exception is pending but external exceptions were masked.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_EE_OFF_EXT_INT], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_EE_OFF_EXT_INT] }, [ POWER7_PME_PM_INST_PTEG_FROM_DMEM ] = { .pme_name = "PM_INST_PTEG_FROM_DMEM", .pme_code = 0x2e052, .pme_short_desc = "Instruction PTEG loaded from distant memory", .pme_long_desc = "Instruction PTEG loaded from distant memory", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_PTEG_FROM_DMEM], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_PTEG_FROM_DMEM] }, [ POWER7_PME_PM_INST_FROM_DL2L3_MOD ] = { .pme_name = "PM_INST_FROM_DL2L3_MOD", .pme_code = 0x3404c, .pme_short_desc = "Instruction fetched from distant L2 or L3 modified", .pme_long_desc = "An instruction fetch group was fetched with modified (M) data from an L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_DL2L3_MOD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_DL2L3_MOD] }, [ POWER7_PME_PM_PMC6_OVERFLOW ] = { .pme_name = "PM_PMC6_OVERFLOW", .pme_code = 0x30024, .pme_short_desc = "Overflow from counter 6", .pme_long_desc = "Overflows from PMC6 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_PMC6_OVERFLOW], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_PMC6_OVERFLOW] }, [ POWER7_PME_PM_VSU_2FLOP_DOUBLE ] = { .pme_name = "PM_VSU_2FLOP_DOUBLE", .pme_code = 0xa88c, .pme_short_desc = "DP vector version of fmul", .pme_long_desc = " fsub", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_2FLOP_DOUBLE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_2FLOP_DOUBLE] }, [ POWER7_PME_PM_TLB_MISS ] = { .pme_name = "PM_TLB_MISS", .pme_code = 0x20066, .pme_short_desc = "TLB Miss (I + D)", .pme_long_desc = "Total of Data TLB mises + Instruction TLB misses", .pme_event_ids = power7_event_ids[POWER7_PME_PM_TLB_MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_TLB_MISS] }, [ POWER7_PME_PM_FXU_BUSY ] = { .pme_name = "PM_FXU_BUSY", .pme_code = 0x2000e, .pme_short_desc = "fxu0 busy and fxu1 busy.", .pme_long_desc = "Cycles when both FXU0 and FXU1 are busy.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_FXU_BUSY], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_FXU_BUSY] }, [ POWER7_PME_PM_L2_RCLD_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2_RCLD_DISP_FAIL_OTHER", .pme_code = 0x26280, .pme_short_desc = " L2 RC load dispatch attempt failed due to other reasons", .pme_long_desc = " L2 RC load dispatch attempt failed due to other reasons", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_RCLD_DISP_FAIL_OTHER], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_RCLD_DISP_FAIL_OTHER] }, [ POWER7_PME_PM_LSU_REJECT_LMQ_FULL ] = { .pme_name = "PM_LSU_REJECT_LMQ_FULL", .pme_code = 0xc8a4, .pme_short_desc = "Reject: LMQ Full (LHR)", .pme_long_desc = "Total cycles the Load Store Unit is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all the eight entries are full, subsequent load instructions are rejected. Combined unit 0 + 1.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_REJECT_LMQ_FULL], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_REJECT_LMQ_FULL] }, [ POWER7_PME_PM_IC_RELOAD_SHR ] = { .pme_name = "PM_IC_RELOAD_SHR", .pme_code = 0x4096, .pme_short_desc = "Reloading line to be shared between the threads", .pme_long_desc = "An Instruction Cache request was made by this thread and the cache line was already in the cache for the other thread. The line is marked valid for all threads.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_RELOAD_SHR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_RELOAD_SHR] }, [ POWER7_PME_PM_GRP_MRK ] = { .pme_name = "PM_GRP_MRK", .pme_code = 0x10031, .pme_short_desc = "IDU Marked Instruction", .pme_long_desc = "A group was sampled (marked). The group is called a marked group. One instruction within the group is tagged for detailed monitoring. The sampled instruction is called a marked instructions. Events associated with the marked instruction are annotated with the marked term.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_GRP_MRK], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_GRP_MRK] }, [ POWER7_PME_PM_MRK_ST_NEST ] = { .pme_name = "PM_MRK_ST_NEST", .pme_code = 0x20034, .pme_short_desc = "marked store sent to Nest", .pme_long_desc = "A sampled store has been sent to the memory subsystem", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_ST_NEST], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_ST_NEST] }, [ POWER7_PME_PM_VSU1_FSQRT_FDIV ] = { .pme_name = "PM_VSU1_FSQRT_FDIV", .pme_code = 0xa08a, .pme_short_desc = "four flops operation (fdiv", .pme_long_desc = "fsqrt", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_FSQRT_FDIV], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_FSQRT_FDIV] }, [ POWER7_PME_PM_LSU0_FLUSH_LRQ ] = { .pme_name = "PM_LSU0_FLUSH_LRQ", .pme_code = 0xc0b8, .pme_short_desc = "LS0 Flush: LRQ", .pme_long_desc = "Load Hit Load or Store Hit Load flush. A younger load was flushed from unit 0 because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_FLUSH_LRQ], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_FLUSH_LRQ] }, [ POWER7_PME_PM_LARX_LSU0 ] = { .pme_name = "PM_LARX_LSU0", .pme_code = 0xc094, .pme_short_desc = "ls0 Larx Finished", .pme_long_desc = "A larx (lwarx or ldarx) was executed on side 0 ", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LARX_LSU0], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LARX_LSU0] }, [ POWER7_PME_PM_IBUF_FULL_CYC ] = { .pme_name = "PM_IBUF_FULL_CYC", .pme_code = 0x4084, .pme_short_desc = "Cycles No room in ibuff", .pme_long_desc = "Cycles with the Instruction Buffer was full. The Instruction Buffer is a circular queue of 64 instructions per thread, organized as 16 groups of 4 instructions.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_IBUF_FULL_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_IBUF_FULL_CYC] }, [ POWER7_PME_PM_MRK_DATA_FROM_DL2L3_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_DL2L3_SHR_CYC", .pme_code = 0x2002a, .pme_short_desc = "Marked ld latency Data Source 1010 (Distant L2.75/L3.75 S)", .pme_long_desc = "Marked ld latency Data Source 1010 (Distant L2.75/L3.75 S)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_DL2L3_SHR_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_DL2L3_SHR_CYC] }, [ POWER7_PME_PM_LSU_DC_PREF_STREAM_ALLOC ] = { .pme_name = "PM_LSU_DC_PREF_STREAM_ALLOC", .pme_code = 0xd8a8, .pme_short_desc = "D cache new prefetch stream allocated", .pme_long_desc = "D cache new prefetch stream allocated", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_DC_PREF_STREAM_ALLOC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_DC_PREF_STREAM_ALLOC] }, [ POWER7_PME_PM_GRP_MRK_CYC ] = { .pme_name = "PM_GRP_MRK_CYC", .pme_code = 0x10030, .pme_short_desc = "cycles IDU marked instruction before dispatch", .pme_long_desc = "cycles IDU marked instruction before dispatch", .pme_event_ids = power7_event_ids[POWER7_PME_PM_GRP_MRK_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_GRP_MRK_CYC] }, [ POWER7_PME_PM_MRK_DATA_FROM_RL2L3_SHR_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_RL2L3_SHR_CYC", .pme_code = 0x20028, .pme_short_desc = "Marked ld latency Data Source 1000 (Remote L2.5/L3.5 S)", .pme_long_desc = "Marked load latency Data Source 1000 (Remote L2.5/L3.5 S)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_RL2L3_SHR_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_RL2L3_SHR_CYC] }, [ POWER7_PME_PM_L2_GLOB_GUESS_CORRECT ] = { .pme_name = "PM_L2_GLOB_GUESS_CORRECT", .pme_code = 0x16482, .pme_short_desc = "L2 guess glb and guess was correct (ie data remote)", .pme_long_desc = "L2 guess glb and guess was correct (ie data remote)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_GLOB_GUESS_CORRECT], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_GLOB_GUESS_CORRECT] }, [ POWER7_PME_PM_LSU_REJECT_LHS ] = { .pme_name = "PM_LSU_REJECT_LHS", .pme_code = 0xc8ac, .pme_short_desc = "Reject: Load Hit Store", .pme_long_desc = "The Load Store Unit rejected a load load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. Combined Unit 0 + 1", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_REJECT_LHS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_REJECT_LHS] }, [ POWER7_PME_PM_MRK_DATA_FROM_LMEM ] = { .pme_name = "PM_MRK_DATA_FROM_LMEM", .pme_code = 0x3d04a, .pme_short_desc = "Marked data loaded from local memory", .pme_long_desc = "The processor's Data Cache was reloaded due to a marked load from memory attached to the same module this proccessor is located on.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_LMEM], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_LMEM] }, [ POWER7_PME_PM_INST_PTEG_FROM_L3 ] = { .pme_name = "PM_INST_PTEG_FROM_L3", .pme_code = 0x2e050, .pme_short_desc = "Instruction PTEG loaded from L3", .pme_long_desc = "Instruction PTEG loaded from L3", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_PTEG_FROM_L3], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_PTEG_FROM_L3] }, [ POWER7_PME_PM_FREQ_DOWN ] = { .pme_name = "PM_FREQ_DOWN", .pme_code = 0x3000c, .pme_short_desc = "Frequency is being slewed down due to Power Management", .pme_long_desc = "Processor frequency was slowed down due to power management", .pme_event_ids = power7_event_ids[POWER7_PME_PM_FREQ_DOWN], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_FREQ_DOWN] }, [ POWER7_PME_PM_INST_FROM_RL2L3_SHR ] = { .pme_name = "PM_INST_FROM_RL2L3_SHR", .pme_code = 0x1404c, .pme_short_desc = "Instruction fetched from remote L2 or L3 shared", .pme_long_desc = "An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_RL2L3_SHR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_RL2L3_SHR] }, [ POWER7_PME_PM_MRK_INST_ISSUED ] = { .pme_name = "PM_MRK_INST_ISSUED", .pme_code = 0x10032, .pme_short_desc = "Marked instruction issued", .pme_long_desc = "A marked instruction was issued to an execution unit.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_INST_ISSUED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_INST_ISSUED] }, [ POWER7_PME_PM_PTEG_FROM_L3MISS ] = { .pme_name = "PM_PTEG_FROM_L3MISS", .pme_code = 0x2c058, .pme_short_desc = "PTEG loaded from L3 miss", .pme_long_desc = " Page Table Entry was loaded into the ERAT from beyond the L3 due to a demand load or store.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_PTEG_FROM_L3MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_PTEG_FROM_L3MISS] }, [ POWER7_PME_PM_RUN_PURR ] = { .pme_name = "PM_RUN_PURR", .pme_code = 0x400f4, .pme_short_desc = "Run_PURR", .pme_long_desc = "The Processor Utilization of Resources Register was incremented while the run latch was set. The PURR registers will be incremented roughly in the ratio in which the instructions are dispatched from the two threads. ", .pme_event_ids = power7_event_ids[POWER7_PME_PM_RUN_PURR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_RUN_PURR] }, [ POWER7_PME_PM_MRK_DATA_FROM_L3 ] = { .pme_name = "PM_MRK_DATA_FROM_L3", .pme_code = 0x1d048, .pme_short_desc = "Marked data loaded from L3", .pme_long_desc = "The processor's Data Cache was reloaded from the local L3 due to a marked load.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_L3], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_L3] }, [ POWER7_PME_PM_MRK_GRP_IC_MISS ] = { .pme_name = "PM_MRK_GRP_IC_MISS", .pme_code = 0x40038, .pme_short_desc = "Marked group experienced I cache miss", .pme_long_desc = "A group containing a marked (sampled) instruction experienced an instruction cache miss.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_GRP_IC_MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_GRP_IC_MISS] }, [ POWER7_PME_PM_CMPLU_STALL_DCACHE_MISS ] = { .pme_name = "PM_CMPLU_STALL_DCACHE_MISS", .pme_code = 0x20016, .pme_short_desc = " Completion stall caused by D cache miss", .pme_long_desc = "Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a Data Cache Miss. Data Cache Miss has higher priority than any other Load/Store delay, so if an instruction encounters multiple delays only the Data Cache Miss will be reported and the entire delay period will be charged to Data Cache Miss. This is a subset of PM_CMPLU_STALL_LSU.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_CMPLU_STALL_DCACHE_MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_CMPLU_STALL_DCACHE_MISS] }, [ POWER7_PME_PM_PTEG_FROM_RL2L3_SHR ] = { .pme_name = "PM_PTEG_FROM_RL2L3_SHR", .pme_code = 0x2c054, .pme_short_desc = "PTEG loaded from remote L2 or L3 shared", .pme_long_desc = "A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load or store.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_PTEG_FROM_RL2L3_SHR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_PTEG_FROM_RL2L3_SHR] }, [ POWER7_PME_PM_LSU_FLUSH_LRQ ] = { .pme_name = "PM_LSU_FLUSH_LRQ", .pme_code = 0xc8b8, .pme_short_desc = "Flush: LRQ", .pme_long_desc = "Load Hit Load or Store Hit Load flush. A younger load was flushed because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. Combined Unit 0 + 1.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_FLUSH_LRQ], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_FLUSH_LRQ] }, [ POWER7_PME_PM_MRK_DERAT_MISS_64K ] = { .pme_name = "PM_MRK_DERAT_MISS_64K", .pme_code = 0x2d05c, .pme_short_desc = "Marked DERAT misses for 64K page", .pme_long_desc = "A marked data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DERAT_MISS_64K], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DERAT_MISS_64K] }, [ POWER7_PME_PM_INST_PTEG_FROM_DL2L3_MOD ] = { .pme_name = "PM_INST_PTEG_FROM_DL2L3_MOD", .pme_code = 0x4e054, .pme_short_desc = "Instruction PTEG loaded from distant L2 or L3 modified", .pme_long_desc = "Instruction PTEG loaded from distant L2 or L3 modified", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_PTEG_FROM_DL2L3_MOD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_PTEG_FROM_DL2L3_MOD] }, [ POWER7_PME_PM_L2_ST_MISS ] = { .pme_name = "PM_L2_ST_MISS", .pme_code = 0x26082, .pme_short_desc = "Data Store Miss", .pme_long_desc = "Data Store Miss", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_ST_MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_ST_MISS] }, [ POWER7_PME_PM_LWSYNC ] = { .pme_name = "PM_LWSYNC", .pme_code = 0xd094, .pme_short_desc = "lwsync count (easier to use than IMC)", .pme_long_desc = "lwsync count (easier to use than IMC)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LWSYNC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LWSYNC] }, [ POWER7_PME_PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE ] = { .pme_name = "PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE", .pme_code = 0xd0bc, .pme_short_desc = "LS0 Dcache Strided prefetch stream confirmed", .pme_long_desc = "LS0 Dcache Strided prefetch stream confirmed", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE] }, [ POWER7_PME_PM_MRK_PTEG_FROM_L21_SHR ] = { .pme_name = "PM_MRK_PTEG_FROM_L21_SHR", .pme_code = 0x4d056, .pme_short_desc = "Marked PTEG loaded from another L2 on same chip shared", .pme_long_desc = "Marked PTEG loaded from another L2 on same chip shared", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_PTEG_FROM_L21_SHR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_PTEG_FROM_L21_SHR] }, [ POWER7_PME_PM_MRK_LSU_FLUSH_LRQ ] = { .pme_name = "PM_MRK_LSU_FLUSH_LRQ", .pme_code = 0xd088, .pme_short_desc = "Flush: (marked) LRQ", .pme_long_desc = "Load Hit Load or Store Hit Load flush. A marked load was flushed because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LSU_FLUSH_LRQ], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LSU_FLUSH_LRQ] }, [ POWER7_PME_PM_INST_IMC_MATCH_CMPL ] = { .pme_name = "PM_INST_IMC_MATCH_CMPL", .pme_code = 0x100f0, .pme_short_desc = "IMC Match Count", .pme_long_desc = "Number of instructions resulting from the marked instructions expansion that completed.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_IMC_MATCH_CMPL], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_IMC_MATCH_CMPL] }, [ POWER7_PME_PM_MRK_INST_FIN ] = { .pme_name = "PM_MRK_INST_FIN", .pme_code = 0x30030, .pme_short_desc = "marked instr finish any unit ", .pme_long_desc = "One of the execution units finished a marked instruction. Instructions that finish may not necessary complete", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_INST_FIN], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_INST_FIN] }, [ POWER7_PME_PM_INST_FROM_L31_MOD ] = { .pme_name = "PM_INST_FROM_L31_MOD", .pme_code = 0x14044, .pme_short_desc = "Instruction fetched from another L3 on same chip modified", .pme_long_desc = "Instruction fetched from another L3 on same chip modified", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_L31_MOD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_L31_MOD] }, [ POWER7_PME_PM_MRK_DTLB_MISS_64K ] = { .pme_name = "PM_MRK_DTLB_MISS_64K", .pme_code = 0x3d05e, .pme_short_desc = "Marked Data TLB misses for 64K page", .pme_long_desc = "Data TLB references to 64KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DTLB_MISS_64K], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DTLB_MISS_64K] }, [ POWER7_PME_PM_LSU_FIN ] = { .pme_name = "PM_LSU_FIN", .pme_code = 0x30066, .pme_short_desc = "LSU Finished an instruction (up to 2 per cycle)", .pme_long_desc = "LSU Finished an instruction (up to 2 per cycle)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_FIN], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_FIN] }, [ POWER7_PME_PM_MRK_LSU_REJECT ] = { .pme_name = "PM_MRK_LSU_REJECT", .pme_code = 0x40064, .pme_short_desc = "LSU marked reject (up to 2 per cycle)", .pme_long_desc = "LSU marked reject (up to 2 per cycle)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LSU_REJECT], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LSU_REJECT] }, [ POWER7_PME_PM_L2_CO_FAIL_BUSY ] = { .pme_name = "PM_L2_CO_FAIL_BUSY", .pme_code = 0x16382, .pme_short_desc = " L2 RC Cast Out dispatch attempt failed due to all CO machines busy", .pme_long_desc = " L2 RC Cast Out dispatch attempt failed due to all CO machines busy", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_CO_FAIL_BUSY], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_CO_FAIL_BUSY] }, [ POWER7_PME_PM_DATA_FROM_L31_MOD ] = { .pme_name = "PM_DATA_FROM_L31_MOD", .pme_code = 0x1c044, .pme_short_desc = "Data loaded from another L3 on same chip modified", .pme_long_desc = "Data loaded from another L3 on same chip modified", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_L31_MOD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_L31_MOD] }, [ POWER7_PME_PM_THERMAL_WARN ] = { .pme_name = "PM_THERMAL_WARN", .pme_code = 0x10016, .pme_short_desc = "Processor in Thermal Warning", .pme_long_desc = "Processor in Thermal Warning", .pme_event_ids = power7_event_ids[POWER7_PME_PM_THERMAL_WARN], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_THERMAL_WARN] }, [ POWER7_PME_PM_VSU0_4FLOP ] = { .pme_name = "PM_VSU0_4FLOP", .pme_code = 0xa09c, .pme_short_desc = "four flops operation (scalar fdiv", .pme_long_desc = " fsqrt; DP vector version of fmadd", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_4FLOP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_4FLOP] }, [ POWER7_PME_PM_BR_MPRED_CCACHE ] = { .pme_name = "PM_BR_MPRED_CCACHE", .pme_code = 0x40a4, .pme_short_desc = "Branch Mispredict due to Count Cache prediction", .pme_long_desc = "A branch instruction target was incorrectly predicted by the ccount cache. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_BR_MPRED_CCACHE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_BR_MPRED_CCACHE] }, [ POWER7_PME_PM_L1_DEMAND_WRITE ] = { .pme_name = "PM_L1_DEMAND_WRITE", .pme_code = 0x408c, .pme_short_desc = "Instruction Demand sectors wriittent into IL1", .pme_long_desc = "Instruction Demand sectors wriittent into IL1", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L1_DEMAND_WRITE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L1_DEMAND_WRITE] }, [ POWER7_PME_PM_FLUSH_BR_MPRED ] = { .pme_name = "PM_FLUSH_BR_MPRED", .pme_code = 0x2084, .pme_short_desc = "Flush caused by branch mispredict", .pme_long_desc = "A flush was caused by a branch mispredict.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_FLUSH_BR_MPRED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_FLUSH_BR_MPRED] }, [ POWER7_PME_PM_MRK_DTLB_MISS_16G ] = { .pme_name = "PM_MRK_DTLB_MISS_16G", .pme_code = 0x1d05e, .pme_short_desc = "Marked Data TLB misses for 16G page", .pme_long_desc = "Data TLB references to 16GB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DTLB_MISS_16G], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DTLB_MISS_16G] }, [ POWER7_PME_PM_MRK_PTEG_FROM_DMEM ] = { .pme_name = "PM_MRK_PTEG_FROM_DMEM", .pme_code = 0x2d052, .pme_short_desc = "Marked PTEG loaded from distant memory", .pme_long_desc = "A Page Table Entry was loaded into the ERAT from memory attached to a different module than this proccessor is located on due to a marked load or store.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_PTEG_FROM_DMEM], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_PTEG_FROM_DMEM] }, [ POWER7_PME_PM_L2_RCST_DISP ] = { .pme_name = "PM_L2_RCST_DISP", .pme_code = 0x36280, .pme_short_desc = " L2 RC store dispatch attempt", .pme_long_desc = " L2 RC store dispatch attempt", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_RCST_DISP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_RCST_DISP] }, [ POWER7_PME_PM_CMPLU_STALL ] = { .pme_name = "PM_CMPLU_STALL", .pme_code = 0x4000a, .pme_short_desc = "No groups completed", .pme_long_desc = " GCT not empty", .pme_event_ids = power7_event_ids[POWER7_PME_PM_CMPLU_STALL], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_CMPLU_STALL] }, [ POWER7_PME_PM_LSU_PARTIAL_CDF ] = { .pme_name = "PM_LSU_PARTIAL_CDF", .pme_code = 0xc0aa, .pme_short_desc = "A partial cacheline was returned from the L3", .pme_long_desc = "A partial cacheline was returned from the L3", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_PARTIAL_CDF], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_PARTIAL_CDF] }, [ POWER7_PME_PM_DISP_CLB_HELD_SB ] = { .pme_name = "PM_DISP_CLB_HELD_SB", .pme_code = 0x20a8, .pme_short_desc = "Dispatch/CLB Hold: Scoreboard", .pme_long_desc = "Dispatch/CLB Hold: Scoreboard", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DISP_CLB_HELD_SB], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DISP_CLB_HELD_SB] }, [ POWER7_PME_PM_VSU0_FMA_DOUBLE ] = { .pme_name = "PM_VSU0_FMA_DOUBLE", .pme_code = 0xa090, .pme_short_desc = "four flop DP vector operations (xvmadddp", .pme_long_desc = " xvnmadddp", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_FMA_DOUBLE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_FMA_DOUBLE] }, [ POWER7_PME_PM_FXU0_BUSY_FXU1_IDLE ] = { .pme_name = "PM_FXU0_BUSY_FXU1_IDLE", .pme_code = 0x3000e, .pme_short_desc = "fxu0 busy and fxu1 idle", .pme_long_desc = "FXU0 is busy while FXU1 was idle", .pme_event_ids = power7_event_ids[POWER7_PME_PM_FXU0_BUSY_FXU1_IDLE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_FXU0_BUSY_FXU1_IDLE] }, [ POWER7_PME_PM_IC_DEMAND_CYC ] = { .pme_name = "PM_IC_DEMAND_CYC", .pme_code = 0x10018, .pme_short_desc = "Cycles when a demand ifetch was pending", .pme_long_desc = "Cycles when a demand ifetch was pending", .pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_DEMAND_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_DEMAND_CYC] }, [ POWER7_PME_PM_MRK_DATA_FROM_L21_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_L21_SHR", .pme_code = 0x3d04e, .pme_short_desc = "Marked data loaded from another L2 on same chip shared", .pme_long_desc = "Marked data loaded from another L2 on same chip shared", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_L21_SHR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_L21_SHR] }, [ POWER7_PME_PM_MRK_LSU_FLUSH_UST ] = { .pme_name = "PM_MRK_LSU_FLUSH_UST", .pme_code = 0xd086, .pme_short_desc = "Flush: (marked) Unaligned Store", .pme_long_desc = "A marked store was flushed because it was unaligned", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LSU_FLUSH_UST], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LSU_FLUSH_UST] }, [ POWER7_PME_PM_INST_PTEG_FROM_L3MISS ] = { .pme_name = "PM_INST_PTEG_FROM_L3MISS", .pme_code = 0x2e058, .pme_short_desc = "Instruction PTEG loaded from L3 miss", .pme_long_desc = "Instruction PTEG loaded from L3 miss", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_PTEG_FROM_L3MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_PTEG_FROM_L3MISS] }, [ POWER7_PME_PM_VSU_DENORM ] = { .pme_name = "PM_VSU_DENORM", .pme_code = 0xa8ac, .pme_short_desc = "Vector or Scalar denorm operand", .pme_long_desc = "Vector or Scalar denorm operand", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_DENORM], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_DENORM] }, [ POWER7_PME_PM_MRK_LSU_PARTIAL_CDF ] = { .pme_name = "PM_MRK_LSU_PARTIAL_CDF", .pme_code = 0xd080, .pme_short_desc = "A partial cacheline was returned from the L3 for a marked load", .pme_long_desc = "A partial cacheline was returned from the L3 for a marked load", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LSU_PARTIAL_CDF], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LSU_PARTIAL_CDF] }, [ POWER7_PME_PM_INST_FROM_L21_SHR ] = { .pme_name = "PM_INST_FROM_L21_SHR", .pme_code = 0x3404e, .pme_short_desc = "Instruction fetched from another L2 on same chip shared", .pme_long_desc = "Instruction fetched from another L2 on same chip shared", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_L21_SHR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_L21_SHR] }, [ POWER7_PME_PM_IC_PREF_WRITE ] = { .pme_name = "PM_IC_PREF_WRITE", .pme_code = 0x408e, .pme_short_desc = "Instruction prefetch written into IL1", .pme_long_desc = "Number of Instruction Cache entries written because of prefetch. Prefetch entries are marked least recently used and are candidates for eviction if they are not needed to satify a demand fetch.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_PREF_WRITE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_PREF_WRITE] }, [ POWER7_PME_PM_BR_PRED ] = { .pme_name = "PM_BR_PRED", .pme_code = 0x409c, .pme_short_desc = "Branch Predictions made", .pme_long_desc = "A branch prediction was made. This could have been a target prediction, a condition prediction, or both", .pme_event_ids = power7_event_ids[POWER7_PME_PM_BR_PRED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_BR_PRED] }, [ POWER7_PME_PM_INST_FROM_DMEM ] = { .pme_name = "PM_INST_FROM_DMEM", .pme_code = 0x1404a, .pme_short_desc = "Instruction fetched from distant memory", .pme_long_desc = "An instruction fetch group was fetched from memory attached to a distant module. Fetch groups can contain up to 8 instructions", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_DMEM], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_DMEM] }, [ POWER7_PME_PM_IC_PREF_CANCEL_ALL ] = { .pme_name = "PM_IC_PREF_CANCEL_ALL", .pme_code = 0x4890, .pme_short_desc = "Prefetch Canceled due to page boundary or icache hit", .pme_long_desc = "Prefetch Canceled due to page boundary or icache hit", .pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_PREF_CANCEL_ALL], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_PREF_CANCEL_ALL] }, [ POWER7_PME_PM_LSU_DC_PREF_STREAM_CONFIRM ] = { .pme_name = "PM_LSU_DC_PREF_STREAM_CONFIRM", .pme_code = 0xd8b4, .pme_short_desc = "Dcache new prefetch stream confirmed", .pme_long_desc = "Dcache new prefetch stream confirmed", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_DC_PREF_STREAM_CONFIRM], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_DC_PREF_STREAM_CONFIRM] }, [ POWER7_PME_PM_MRK_LSU_FLUSH_SRQ ] = { .pme_name = "PM_MRK_LSU_FLUSH_SRQ", .pme_code = 0xd08a, .pme_short_desc = "Flush: (marked) SRQ", .pme_long_desc = "Load Hit Store flush. A marked load was flushed because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. ", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LSU_FLUSH_SRQ], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LSU_FLUSH_SRQ] }, [ POWER7_PME_PM_MRK_FIN_STALL_CYC ] = { .pme_name = "PM_MRK_FIN_STALL_CYC", .pme_code = 0x1003c, .pme_short_desc = "Marked instruction Finish Stall cycles (marked finish after NTC) ", .pme_long_desc = "Marked instruction Finish Stall cycles (marked finish after NTC) ", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_FIN_STALL_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_FIN_STALL_CYC] }, [ POWER7_PME_PM_GCT_UTIL_11PLUS_SLOT ] = { .pme_name = "PM_GCT_UTIL_11+_SLOT", .pme_code = 0x20a2, .pme_short_desc = "GCT Utilization 11+ entries", .pme_long_desc = "GCT Utilization 11+ entries", .pme_event_ids = power7_event_ids[POWER7_PME_PM_GCT_UTIL_11PLUS_SLOT], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_GCT_UTIL_11PLUS_SLOT] }, [ POWER7_PME_PM_L2_RCST_DISP_FAIL_OTHER ] = { .pme_name = "PM_L2_RCST_DISP_FAIL_OTHER", .pme_code = 0x46280, .pme_short_desc = " L2 RC store dispatch attempt failed due to other reasons", .pme_long_desc = " L2 RC store dispatch attempt failed due to other reasons", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_RCST_DISP_FAIL_OTHER], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_RCST_DISP_FAIL_OTHER] }, [ POWER7_PME_PM_VSU1_DD_ISSUED ] = { .pme_name = "PM_VSU1_DD_ISSUED", .pme_code = 0xb098, .pme_short_desc = "64BIT Decimal Issued on Pipe1", .pme_long_desc = "64BIT Decimal Issued on Pipe1", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_DD_ISSUED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_DD_ISSUED] }, [ POWER7_PME_PM_PTEG_FROM_L31_SHR ] = { .pme_name = "PM_PTEG_FROM_L31_SHR", .pme_code = 0x2c056, .pme_short_desc = "PTEG loaded from another L3 on same chip shared", .pme_long_desc = "PTEG loaded from another L3 on same chip shared", .pme_event_ids = power7_event_ids[POWER7_PME_PM_PTEG_FROM_L31_SHR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_PTEG_FROM_L31_SHR] }, [ POWER7_PME_PM_DATA_FROM_L21_SHR ] = { .pme_name = "PM_DATA_FROM_L21_SHR", .pme_code = 0x3c04e, .pme_short_desc = "Data loaded from another L2 on same chip shared", .pme_long_desc = "Data loaded from another L2 on same chip shared", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_L21_SHR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_L21_SHR] }, [ POWER7_PME_PM_LSU0_NCLD ] = { .pme_name = "PM_LSU0_NCLD", .pme_code = 0xc08c, .pme_short_desc = "LS0 Non-cachable Loads counted at finish", .pme_long_desc = "A non-cacheable load was executed by unit 0.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_NCLD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_NCLD] }, [ POWER7_PME_PM_VSU1_4FLOP ] = { .pme_name = "PM_VSU1_4FLOP", .pme_code = 0xa09e, .pme_short_desc = "four flops operation (scalar fdiv", .pme_long_desc = " fsqrt; DP vector version of fmadd", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_4FLOP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_4FLOP] }, [ POWER7_PME_PM_VSU1_8FLOP ] = { .pme_name = "PM_VSU1_8FLOP", .pme_code = 0xa0a2, .pme_short_desc = "eight flops operation (DP vector versions of fdiv", .pme_long_desc = "fsqrt and SP vector versions of fmadd", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_8FLOP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_8FLOP] }, [ POWER7_PME_PM_VSU_8FLOP ] = { .pme_name = "PM_VSU_8FLOP", .pme_code = 0xa8a0, .pme_short_desc = "eight flops operation (DP vector versions of fdiv", .pme_long_desc = "fsqrt and SP vector versions of fmadd", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_8FLOP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_8FLOP] }, [ POWER7_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_LMQ_SRQ_EMPTY_CYC", .pme_code = 0x2003e, .pme_short_desc = "LSU empty (lmq and srq empty)", .pme_long_desc = "Cycles when both the LMQ and SRQ are empty (LSU is idle)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC] }, [ POWER7_PME_PM_DTLB_MISS_64K ] = { .pme_name = "PM_DTLB_MISS_64K", .pme_code = 0x3c05e, .pme_short_desc = "Data TLB miss for 64K page", .pme_long_desc = "Data TLB references to 64KB pages that missed the TLB. Page size is determined at TLB reload time.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DTLB_MISS_64K], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DTLB_MISS_64K] }, [ POWER7_PME_PM_THRD_CONC_RUN_INST ] = { .pme_name = "PM_THRD_CONC_RUN_INST", .pme_code = 0x300f4, .pme_short_desc = "Concurrent Run Instructions", .pme_long_desc = "Instructions completed by this thread when both threads had their run latches set.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_THRD_CONC_RUN_INST], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_THRD_CONC_RUN_INST] }, [ POWER7_PME_PM_MRK_PTEG_FROM_L2 ] = { .pme_name = "PM_MRK_PTEG_FROM_L2", .pme_code = 0x1d050, .pme_short_desc = "Marked PTEG loaded from L2", .pme_long_desc = "A Page Table Entry was loaded into the ERAT from the local L2 due to a marked load or store.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_PTEG_FROM_L2], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_PTEG_FROM_L2] }, [ POWER7_PME_PM_VSU_FIN ] = { .pme_name = "PM_VSU_FIN", .pme_code = 0xa8bc, .pme_short_desc = "VSU0 Finished an instruction", .pme_long_desc = "VSU0 Finished an instruction", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_FIN], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_FIN] }, [ POWER7_PME_PM_MRK_DATA_FROM_L31_MOD ] = { .pme_name = "PM_MRK_DATA_FROM_L31_MOD", .pme_code = 0x1d044, .pme_short_desc = "Marked data loaded from another L3 on same chip modified", .pme_long_desc = "Marked data loaded from another L3 on same chip modified", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_L31_MOD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_L31_MOD] }, [ POWER7_PME_PM_THRD_PRIO_0_1_CYC ] = { .pme_name = "PM_THRD_PRIO_0_1_CYC", .pme_code = 0x40b0, .pme_short_desc = " Cycles thread running at priority level 0 or 1", .pme_long_desc = " Cycles thread running at priority level 0 or 1", .pme_event_ids = power7_event_ids[POWER7_PME_PM_THRD_PRIO_0_1_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_THRD_PRIO_0_1_CYC] }, [ POWER7_PME_PM_DERAT_MISS_64K ] = { .pme_name = "PM_DERAT_MISS_64K", .pme_code = 0x2c05c, .pme_short_desc = "DERAT misses for 64K page", .pme_long_desc = "A data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DERAT_MISS_64K], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DERAT_MISS_64K] }, [ POWER7_PME_PM_PMC2_REWIND ] = { .pme_name = "PM_PMC2_REWIND", .pme_code = 0x30020, .pme_short_desc = "PMC2 Rewind Event (did not match condition)", .pme_long_desc = "PMC2 was counting speculatively. The speculative condition was not met and the counter was restored to its previous value.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_PMC2_REWIND], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_PMC2_REWIND] }, [ POWER7_PME_PM_INST_FROM_L2 ] = { .pme_name = "PM_INST_FROM_L2", .pme_code = 0x14040, .pme_short_desc = "Instruction fetched from L2", .pme_long_desc = "An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_L2], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_L2] }, [ POWER7_PME_PM_GRP_BR_MPRED_NONSPEC ] = { .pme_name = "PM_GRP_BR_MPRED_NONSPEC", .pme_code = 0x1000a, .pme_short_desc = "Group experienced non-speculative branch redirect", .pme_long_desc = "Group experienced non-speculative branch redirect", .pme_event_ids = power7_event_ids[POWER7_PME_PM_GRP_BR_MPRED_NONSPEC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_GRP_BR_MPRED_NONSPEC] }, [ POWER7_PME_PM_INST_DISP ] = { .pme_name = "PM_INST_DISP", .pme_code = 0x200f2, .pme_short_desc = "# PPC Dispatched", .pme_long_desc = "Number of PowerPC instructions successfully dispatched.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_DISP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_DISP] }, [ POWER7_PME_PM_LSU0_DC_PREF_STREAM_CONFIRM ] = { .pme_name = "PM_LSU0_DC_PREF_STREAM_CONFIRM", .pme_code = 0xd0b4, .pme_short_desc = "LS0 Dcache prefetch stream confirmed", .pme_long_desc = "LS0 Dcache prefetch stream confirmed", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_DC_PREF_STREAM_CONFIRM], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_DC_PREF_STREAM_CONFIRM] }, [ POWER7_PME_PM_L1_DCACHE_RELOAD_VALID ] = { .pme_name = "PM_L1_DCACHE_RELOAD_VALID", .pme_code = 0x300f6, .pme_short_desc = "L1 reload data source valid", .pme_long_desc = "The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L1_DCACHE_RELOAD_VALID], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L1_DCACHE_RELOAD_VALID] }, [ POWER7_PME_PM_VSU_SCALAR_DOUBLE_ISSUED ] = { .pme_name = "PM_VSU_SCALAR_DOUBLE_ISSUED", .pme_code = 0xb888, .pme_short_desc = "Double Precision scalar instruction issued on Pipe0", .pme_long_desc = "Double Precision scalar instruction issued on Pipe0", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_SCALAR_DOUBLE_ISSUED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_SCALAR_DOUBLE_ISSUED] }, [ POWER7_PME_PM_L3_PREF_HIT ] = { .pme_name = "PM_L3_PREF_HIT", .pme_code = 0x3f080, .pme_short_desc = "L3 Prefetch Directory Hit", .pme_long_desc = "L3 Prefetch Directory Hit", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L3_PREF_HIT], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L3_PREF_HIT] }, [ POWER7_PME_PM_MRK_PTEG_FROM_L31_MOD ] = { .pme_name = "PM_MRK_PTEG_FROM_L31_MOD", .pme_code = 0x1d054, .pme_short_desc = "Marked PTEG loaded from another L3 on same chip modified", .pme_long_desc = "Marked PTEG loaded from another L3 on same chip modified", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_PTEG_FROM_L31_MOD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_PTEG_FROM_L31_MOD] }, [ POWER7_PME_PM_MRK_FXU_FIN ] = { .pme_name = "PM_MRK_FXU_FIN", .pme_code = 0x20038, .pme_short_desc = "fxu marked instr finish", .pme_long_desc = "One of the Fixed Point Units finished a marked instruction. Instructions that finish may not necessary complete.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_FXU_FIN], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_FXU_FIN] }, [ POWER7_PME_PM_PMC4_OVERFLOW ] = { .pme_name = "PM_PMC4_OVERFLOW", .pme_code = 0x10010, .pme_short_desc = "Overflow from counter 4", .pme_long_desc = "Overflows from PMC4 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_PMC4_OVERFLOW], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_PMC4_OVERFLOW] }, [ POWER7_PME_PM_MRK_PTEG_FROM_L3 ] = { .pme_name = "PM_MRK_PTEG_FROM_L3", .pme_code = 0x2d050, .pme_short_desc = "Marked PTEG loaded from L3", .pme_long_desc = "A Page Table Entry was loaded into the ERAT from the local L3 due to a marked load or store.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_PTEG_FROM_L3], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_PTEG_FROM_L3] }, [ POWER7_PME_PM_LSU0_LMQ_LHR_MERGE ] = { .pme_name = "PM_LSU0_LMQ_LHR_MERGE", .pme_code = 0xd098, .pme_short_desc = "LS0 Load Merged with another cacheline request", .pme_long_desc = "LS0 Load Merged with another cacheline request", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_LMQ_LHR_MERGE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_LMQ_LHR_MERGE] }, [ POWER7_PME_PM_BTAC_HIT ] = { .pme_name = "PM_BTAC_HIT", .pme_code = 0x508a, .pme_short_desc = "BTAC Correct Prediction", .pme_long_desc = "BTAC Correct Prediction", .pme_event_ids = power7_event_ids[POWER7_PME_PM_BTAC_HIT], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_BTAC_HIT] }, [ POWER7_PME_PM_IERAT_XLATE_WR_16MPLUS ] = { .pme_name = "PM_IERAT_XLATE_WR_16M+", .pme_code = 0x40bc, .pme_short_desc = "large page 16M+", .pme_long_desc = "large page 16M+", .pme_event_ids = power7_event_ids[POWER7_PME_PM_IERAT_XLATE_WR_16MPLUS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_IERAT_XLATE_WR_16MPLUS] }, [ POWER7_PME_PM_L3_RD_BUSY ] = { .pme_name = "PM_L3_RD_BUSY", .pme_code = 0x4f082, .pme_short_desc = "Rd machines busy >= threshold (2", .pme_long_desc = "4", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L3_RD_BUSY], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L3_RD_BUSY] }, [ POWER7_PME_PM_INST_FROM_L2MISS ] = { .pme_name = "PM_INST_FROM_L2MISS", .pme_code = 0x44048, .pme_short_desc = "Instruction fetched missed L2", .pme_long_desc = "An instruction fetch group was fetched from beyond the local L2.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_L2MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_L2MISS] }, [ POWER7_PME_PM_LSU0_DC_PREF_STREAM_ALLOC ] = { .pme_name = "PM_LSU0_DC_PREF_STREAM_ALLOC", .pme_code = 0xd0a8, .pme_short_desc = "LS0 D cache new prefetch stream allocated", .pme_long_desc = "LS0 D cache new prefetch stream allocated", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_DC_PREF_STREAM_ALLOC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_DC_PREF_STREAM_ALLOC] }, [ POWER7_PME_PM_L2_ST ] = { .pme_name = "PM_L2_ST", .pme_code = 0x16082, .pme_short_desc = "Data Store Count", .pme_long_desc = "Data Store Count", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_ST], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_ST] }, [ POWER7_PME_PM_VSU0_DENORM ] = { .pme_name = "PM_VSU0_DENORM", .pme_code = 0xa0ac, .pme_short_desc = "FPU denorm operand", .pme_long_desc = "VSU0 received denormalized data", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_DENORM], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_DENORM] }, [ POWER7_PME_PM_MRK_DATA_FROM_DL2L3_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_DL2L3_SHR", .pme_code = 0x3d044, .pme_short_desc = "Marked data loaded from distant L2 or L3 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a distant module due to a marked load.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_DL2L3_SHR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_DL2L3_SHR] }, [ POWER7_PME_PM_BR_PRED_CR_TA ] = { .pme_name = "PM_BR_PRED_CR_TA", .pme_code = 0x48aa, .pme_short_desc = "Branch predict - taken/not taken and target", .pme_long_desc = "Both the condition (taken or not taken) and the target address of a branch instruction was predicted.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_BR_PRED_CR_TA], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_BR_PRED_CR_TA] }, [ POWER7_PME_PM_VSU0_FCONV ] = { .pme_name = "PM_VSU0_FCONV", .pme_code = 0xa0b0, .pme_short_desc = "Convert instruction executed", .pme_long_desc = "Convert instruction executed", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_FCONV], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_FCONV] }, [ POWER7_PME_PM_MRK_LSU_FLUSH_ULD ] = { .pme_name = "PM_MRK_LSU_FLUSH_ULD", .pme_code = 0xd084, .pme_short_desc = "Flush: (marked) Unaligned Load", .pme_long_desc = "A marked load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LSU_FLUSH_ULD], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LSU_FLUSH_ULD] }, [ POWER7_PME_PM_BTAC_MISS ] = { .pme_name = "PM_BTAC_MISS", .pme_code = 0x5088, .pme_short_desc = "BTAC Mispredicted", .pme_long_desc = "BTAC Mispredicted", .pme_event_ids = power7_event_ids[POWER7_PME_PM_BTAC_MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_BTAC_MISS] }, [ POWER7_PME_PM_MRK_LD_MISS_EXPOSED_CYC_COUNT ] = { .pme_name = "PM_MRK_LD_MISS_EXPOSED_CYC_COUNT", .pme_code = 0x1003f, .pme_short_desc = "Marked Load exposed Miss (use edge detect to count #)", .pme_long_desc = "Marked Load exposed Miss (use edge detect to count #)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LD_MISS_EXPOSED_CYC_COUNT], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LD_MISS_EXPOSED_CYC_COUNT] }, [ POWER7_PME_PM_MRK_DATA_FROM_L2 ] = { .pme_name = "PM_MRK_DATA_FROM_L2", .pme_code = 0x1d040, .pme_short_desc = "Marked data loaded from L2", .pme_long_desc = "The processor's Data Cache was reloaded from the local L2 due to a marked load.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_L2], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_L2] }, [ POWER7_PME_PM_VSU_FMA ] = { .pme_name = "PM_VSU_FMA", .pme_code = 0xa884, .pme_short_desc = "two flops operation (fmadd", .pme_long_desc = " fnmadd", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_FMA], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_FMA] }, [ POWER7_PME_PM_LSU0_FLUSH_SRQ ] = { .pme_name = "PM_LSU0_FLUSH_SRQ", .pme_code = 0xc0bc, .pme_short_desc = "LS0 Flush: SRQ", .pme_long_desc = "Load Hit Store flush. A younger load was flushed from unit 0 because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. ", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU0_FLUSH_SRQ], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU0_FLUSH_SRQ] }, [ POWER7_PME_PM_LSU1_L1_PREF ] = { .pme_name = "PM_LSU1_L1_PREF", .pme_code = 0xd0ba, .pme_short_desc = " LS1 L1 cache data prefetches", .pme_long_desc = " LS1 L1 cache data prefetches", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_L1_PREF], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_L1_PREF] }, [ POWER7_PME_PM_IOPS_CMPL ] = { .pme_name = "PM_IOPS_CMPL", .pme_code = 0x10014, .pme_short_desc = "Internal Operations completed", .pme_long_desc = "Number of internal operations that completed.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_IOPS_CMPL], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_IOPS_CMPL] }, [ POWER7_PME_PM_L2_SYS_PUMP ] = { .pme_name = "PM_L2_SYS_PUMP", .pme_code = 0x36482, .pme_short_desc = "RC req that was a global (aka system) pump attempt", .pme_long_desc = "RC req that was a global (aka system) pump attempt", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_SYS_PUMP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_SYS_PUMP] }, [ POWER7_PME_PM_L2_RCLD_BUSY_RC_FULL ] = { .pme_name = "PM_L2_RCLD_BUSY_RC_FULL", .pme_code = 0x46282, .pme_short_desc = " L2 activated Busy to the core for loads due to all RC full", .pme_long_desc = " L2 activated Busy to the core for loads due to all RC full", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_RCLD_BUSY_RC_FULL], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_RCLD_BUSY_RC_FULL] }, [ POWER7_PME_PM_BCPLUS8_RSLV_TAKEN ] = { .pme_name = "PM_BC+8_RSLV_TAKEN", .pme_code = 0x40ba, .pme_short_desc = "BC+8 Resolve outcome was Taken", .pme_long_desc = " resulting in the conditional instruction being canceled", .pme_event_ids = power7_event_ids[POWER7_PME_PM_BCPLUS8_RSLV_TAKEN], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_BCPLUS8_RSLV_TAKEN] }, [ POWER7_PME_PM_NEST_5 ] = { .pme_name = "PM_NEST_5", .pme_code = 0x89, .pme_short_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)", .pme_long_desc = "PlaceHolder for Nest events (MC0/MC1/PB/GX)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_NEST_5], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_NEST_5] }, [ POWER7_PME_PM_LSU_LMQ_S0_ALLOC ] = { .pme_name = "PM_LSU_LMQ_S0_ALLOC", .pme_code = 0xd0a1, .pme_short_desc = "Slot 0 of LMQ valid", .pme_long_desc = "Slot 0 of LMQ valid", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_LMQ_S0_ALLOC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_LMQ_S0_ALLOC] }, [ POWER7_PME_PM_FLUSH_DISP_SYNC ] = { .pme_name = "PM_FLUSH_DISP_SYNC", .pme_code = 0x2088, .pme_short_desc = "Dispatch Flush: Sync", .pme_long_desc = "Dispatch Flush: Sync", .pme_event_ids = power7_event_ids[POWER7_PME_PM_FLUSH_DISP_SYNC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_FLUSH_DISP_SYNC] }, [ POWER7_PME_PM_L2_IC_INV ] = { .pme_name = "PM_L2_IC_INV", .pme_code = 0x26180, .pme_short_desc = "Icache Invalidates from L2 ", .pme_long_desc = "Icache Invalidates from L2 ", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_IC_INV], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_IC_INV] }, [ POWER7_PME_PM_MRK_DATA_FROM_L21_MOD_CYC ] = { .pme_name = "PM_MRK_DATA_FROM_L21_MOD_CYC", .pme_code = 0x40024, .pme_short_desc = "Marked ld latency Data source 0101 (L2.1 M same chip)", .pme_long_desc = "Marked ld latency Data source 0101 (L2.1 M same chip)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_L21_MOD_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_L21_MOD_CYC] }, [ POWER7_PME_PM_L3_PREF_LDST ] = { .pme_name = "PM_L3_PREF_LDST", .pme_code = 0xd8ac, .pme_short_desc = "L3 cache prefetches LD + ST", .pme_long_desc = "L3 cache prefetches LD + ST", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L3_PREF_LDST], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L3_PREF_LDST] }, [ POWER7_PME_PM_LSU_SRQ_EMPTY_CYC ] = { .pme_name = "PM_LSU_SRQ_EMPTY_CYC", .pme_code = 0x40008, .pme_short_desc = "ALL threads srq empty", .pme_long_desc = "The Store Request Queue is empty", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_SRQ_EMPTY_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_SRQ_EMPTY_CYC] }, [ POWER7_PME_PM_LSU_LMQ_S0_VALID ] = { .pme_name = "PM_LSU_LMQ_S0_VALID", .pme_code = 0xd0a0, .pme_short_desc = "Slot 0 of LMQ valid", .pme_long_desc = "This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the LRQ is split between the two threads (16 entries each).", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_LMQ_S0_VALID], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_LMQ_S0_VALID] }, [ POWER7_PME_PM_FLUSH_PARTIAL ] = { .pme_name = "PM_FLUSH_PARTIAL", .pme_code = 0x2086, .pme_short_desc = "Partial flush", .pme_long_desc = "Partial flush", .pme_event_ids = power7_event_ids[POWER7_PME_PM_FLUSH_PARTIAL], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_FLUSH_PARTIAL] }, [ POWER7_PME_PM_VSU1_FMA_DOUBLE ] = { .pme_name = "PM_VSU1_FMA_DOUBLE", .pme_code = 0xa092, .pme_short_desc = "four flop DP vector operations (xvmadddp", .pme_long_desc = " xvnmadddp", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_FMA_DOUBLE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_FMA_DOUBLE] }, [ POWER7_PME_PM_1PLUS_PPC_DISP ] = { .pme_name = "PM_1PLUS_PPC_DISP", .pme_code = 0x400f2, .pme_short_desc = "Cycles at least one Instr Dispatched", .pme_long_desc = "", .pme_event_ids = power7_event_ids[POWER7_PME_PM_1PLUS_PPC_DISP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_1PLUS_PPC_DISP] }, [ POWER7_PME_PM_DATA_FROM_L2MISS ] = { .pme_name = "PM_DATA_FROM_L2MISS", .pme_code = 0x200fe, .pme_short_desc = "Demand LD - L2 Miss (not L2 hit)", .pme_long_desc = "The processor's Data Cache was reloaded but not from the local L2.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_L2MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_L2MISS] }, [ POWER7_PME_PM_SUSPENDED ] = { .pme_name = "PM_SUSPENDED", .pme_code = 0x0, .pme_short_desc = "Counter OFF", .pme_long_desc = "The counter is suspended (does not count)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_SUSPENDED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_SUSPENDED] }, [ POWER7_PME_PM_VSU0_FMA ] = { .pme_name = "PM_VSU0_FMA", .pme_code = 0xa084, .pme_short_desc = "two flops operation (fmadd", .pme_long_desc = " fnmadd", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_FMA], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_FMA] }, [ POWER7_PME_PM_CMPLU_STALL_SCALAR ] = { .pme_name = "PM_CMPLU_STALL_SCALAR", .pme_code = 0x40012, .pme_short_desc = "Completion stall caused by FPU instruction", .pme_long_desc = "Completion stall caused by FPU instruction", .pme_event_ids = power7_event_ids[POWER7_PME_PM_CMPLU_STALL_SCALAR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_CMPLU_STALL_SCALAR] }, [ POWER7_PME_PM_STCX_FAIL ] = { .pme_name = "PM_STCX_FAIL", .pme_code = 0xc09a, .pme_short_desc = "STCX failed", .pme_long_desc = "A stcx (stwcx or stdcx) failed", .pme_event_ids = power7_event_ids[POWER7_PME_PM_STCX_FAIL], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_STCX_FAIL] }, [ POWER7_PME_PM_VSU0_FSQRT_FDIV_DOUBLE ] = { .pme_name = "PM_VSU0_FSQRT_FDIV_DOUBLE", .pme_code = 0xa094, .pme_short_desc = "eight flop DP vector operations (xvfdivdp", .pme_long_desc = " xvsqrtdp ", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_FSQRT_FDIV_DOUBLE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_FSQRT_FDIV_DOUBLE] }, [ POWER7_PME_PM_DC_PREF_DST ] = { .pme_name = "PM_DC_PREF_DST", .pme_code = 0xd0b0, .pme_short_desc = "Data Stream Touch", .pme_long_desc = "A prefetch stream was started using the DST instruction.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DC_PREF_DST], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DC_PREF_DST] }, [ POWER7_PME_PM_VSU1_SCAL_SINGLE_ISSUED ] = { .pme_name = "PM_VSU1_SCAL_SINGLE_ISSUED", .pme_code = 0xb086, .pme_short_desc = "Single Precision scalar instruction issued on Pipe1", .pme_long_desc = "Single Precision scalar instruction issued on Pipe1", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_SCAL_SINGLE_ISSUED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_SCAL_SINGLE_ISSUED] }, [ POWER7_PME_PM_L3_HIT ] = { .pme_name = "PM_L3_HIT", .pme_code = 0x1f080, .pme_short_desc = "L3 Hits", .pme_long_desc = "L3 Hits", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L3_HIT], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L3_HIT] }, [ POWER7_PME_PM_L2_GLOB_GUESS_WRONG ] = { .pme_name = "PM_L2_GLOB_GUESS_WRONG", .pme_code = 0x26482, .pme_short_desc = "L2 guess glb and guess was not correct (ie data local)", .pme_long_desc = "L2 guess glb and guess was not correct (ie data local)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_GLOB_GUESS_WRONG], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_GLOB_GUESS_WRONG] }, [ POWER7_PME_PM_MRK_DFU_FIN ] = { .pme_name = "PM_MRK_DFU_FIN", .pme_code = 0x20032, .pme_short_desc = "Decimal Unit marked Instruction Finish", .pme_long_desc = "The Decimal Floating Point Unit finished a marked instruction.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DFU_FIN], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DFU_FIN] }, [ POWER7_PME_PM_INST_FROM_L1 ] = { .pme_name = "PM_INST_FROM_L1", .pme_code = 0x4080, .pme_short_desc = "Instruction fetches from L1", .pme_long_desc = "An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_L1], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_L1] }, [ POWER7_PME_PM_BRU_FIN ] = { .pme_name = "PM_BRU_FIN", .pme_code = 0x10068, .pme_short_desc = "Branch Instruction Finished ", .pme_long_desc = "The Branch execution unit finished an instruction", .pme_event_ids = power7_event_ids[POWER7_PME_PM_BRU_FIN], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_BRU_FIN] }, [ POWER7_PME_PM_IC_DEMAND_REQ ] = { .pme_name = "PM_IC_DEMAND_REQ", .pme_code = 0x4088, .pme_short_desc = "Demand Instruction fetch request", .pme_long_desc = "Demand Instruction fetch request", .pme_event_ids = power7_event_ids[POWER7_PME_PM_IC_DEMAND_REQ], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_IC_DEMAND_REQ] }, [ POWER7_PME_PM_VSU1_FSQRT_FDIV_DOUBLE ] = { .pme_name = "PM_VSU1_FSQRT_FDIV_DOUBLE", .pme_code = 0xa096, .pme_short_desc = "eight flop DP vector operations (xvfdivdp", .pme_long_desc = " xvsqrtdp ", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_FSQRT_FDIV_DOUBLE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_FSQRT_FDIV_DOUBLE] }, [ POWER7_PME_PM_VSU1_FMA ] = { .pme_name = "PM_VSU1_FMA", .pme_code = 0xa086, .pme_short_desc = "two flops operation (fmadd", .pme_long_desc = " fnmadd", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_FMA], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_FMA] }, [ POWER7_PME_PM_MRK_LD_MISS_L1 ] = { .pme_name = "PM_MRK_LD_MISS_L1", .pme_code = 0x20036, .pme_short_desc = "Marked DL1 Demand Miss", .pme_long_desc = "Marked L1 D cache load misses", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LD_MISS_L1], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LD_MISS_L1] }, [ POWER7_PME_PM_VSU0_2FLOP_DOUBLE ] = { .pme_name = "PM_VSU0_2FLOP_DOUBLE", .pme_code = 0xa08c, .pme_short_desc = "two flop DP vector operation (xvadddp", .pme_long_desc = " xvmuldp", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU0_2FLOP_DOUBLE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU0_2FLOP_DOUBLE] }, [ POWER7_PME_PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM ] = { .pme_name = "PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM", .pme_code = 0xd8bc, .pme_short_desc = "Dcache Strided prefetch stream confirmed (software + hardware)", .pme_long_desc = "Dcache Strided prefetch stream confirmed (software + hardware)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM] }, [ POWER7_PME_PM_INST_PTEG_FROM_L31_SHR ] = { .pme_name = "PM_INST_PTEG_FROM_L31_SHR", .pme_code = 0x2e056, .pme_short_desc = "Instruction PTEG loaded from another L3 on same chip shared", .pme_long_desc = "Instruction PTEG loaded from another L3 on same chip shared", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_PTEG_FROM_L31_SHR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_PTEG_FROM_L31_SHR] }, [ POWER7_PME_PM_MRK_LSU_REJECT_ERAT_MISS ] = { .pme_name = "PM_MRK_LSU_REJECT_ERAT_MISS", .pme_code = 0x30064, .pme_short_desc = "LSU marked reject due to ERAT (up to 2 per cycle)", .pme_long_desc = "LSU marked reject due to ERAT (up to 2 per cycle)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LSU_REJECT_ERAT_MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LSU_REJECT_ERAT_MISS] }, [ POWER7_PME_PM_MRK_DATA_FROM_L2MISS ] = { .pme_name = "PM_MRK_DATA_FROM_L2MISS", .pme_code = 0x4d048, .pme_short_desc = "Marked data loaded missed L2", .pme_long_desc = "DL1 was reloaded from beyond L2 due to a marked demand load.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_L2MISS], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_L2MISS] }, [ POWER7_PME_PM_DATA_FROM_RL2L3_SHR ] = { .pme_name = "PM_DATA_FROM_RL2L3_SHR", .pme_code = 0x1c04c, .pme_short_desc = "Data loaded from remote L2 or L3 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DATA_FROM_RL2L3_SHR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DATA_FROM_RL2L3_SHR] }, [ POWER7_PME_PM_INST_FROM_PREF ] = { .pme_name = "PM_INST_FROM_PREF", .pme_code = 0x14046, .pme_short_desc = "Instruction fetched from prefetch", .pme_long_desc = "An instruction fetch group was fetched from the prefetch buffer. Fetch groups can contain up to 8 instructions", .pme_event_ids = power7_event_ids[POWER7_PME_PM_INST_FROM_PREF], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_INST_FROM_PREF] }, [ POWER7_PME_PM_VSU1_SQ ] = { .pme_name = "PM_VSU1_SQ", .pme_code = 0xb09e, .pme_short_desc = "Store Vector Issued on Pipe1", .pme_long_desc = "Store Vector Issued on Pipe1", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU1_SQ], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU1_SQ] }, [ POWER7_PME_PM_L2_LD_DISP ] = { .pme_name = "PM_L2_LD_DISP", .pme_code = 0x36180, .pme_short_desc = "All successful load dispatches", .pme_long_desc = "All successful load dispatches", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_LD_DISP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_LD_DISP] }, [ POWER7_PME_PM_L2_DISP_ALL ] = { .pme_name = "PM_L2_DISP_ALL", .pme_code = 0x46080, .pme_short_desc = "All successful LD/ST dispatches for this thread(i+d)", .pme_long_desc = "All successful LD/ST dispatches for this thread(i+d)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_L2_DISP_ALL], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_L2_DISP_ALL] }, [ POWER7_PME_PM_THRD_GRP_CMPL_BOTH_CYC ] = { .pme_name = "PM_THRD_GRP_CMPL_BOTH_CYC", .pme_code = 0x10012, .pme_short_desc = "Cycles group completed by both threads", .pme_long_desc = "Cycles that both threads completed.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_THRD_GRP_CMPL_BOTH_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_THRD_GRP_CMPL_BOTH_CYC] }, [ POWER7_PME_PM_VSU_FSQRT_FDIV_DOUBLE ] = { .pme_name = "PM_VSU_FSQRT_FDIV_DOUBLE", .pme_code = 0xa894, .pme_short_desc = "DP vector versions of fdiv", .pme_long_desc = "fsqrt ", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_FSQRT_FDIV_DOUBLE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_FSQRT_FDIV_DOUBLE] }, [ POWER7_PME_PM_BR_MPRED ] = { .pme_name = "PM_BR_MPRED", .pme_code = 0x400f6, .pme_short_desc = "Number of Branch Mispredicts", .pme_long_desc = "A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both", .pme_event_ids = power7_event_ids[POWER7_PME_PM_BR_MPRED], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_BR_MPRED] }, [ POWER7_PME_PM_VSU_1FLOP ] = { .pme_name = "PM_VSU_1FLOP", .pme_code = 0xa880, .pme_short_desc = "one flop (fadd", .pme_long_desc = " fmul", .pme_event_ids = power7_event_ids[POWER7_PME_PM_VSU_1FLOP], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_VSU_1FLOP] }, [ POWER7_PME_PM_HV_CYC ] = { .pme_name = "PM_HV_CYC", .pme_code = 0x2000a, .pme_short_desc = "cycles in hypervisor mode ", .pme_long_desc = "Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0)", .pme_event_ids = power7_event_ids[POWER7_PME_PM_HV_CYC], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_HV_CYC] }, [ POWER7_PME_PM_MRK_DATA_FROM_RL2L3_SHR ] = { .pme_name = "PM_MRK_DATA_FROM_RL2L3_SHR", .pme_code = 0x1d04c, .pme_short_desc = "Marked data loaded from remote L2 or L3 shared", .pme_long_desc = "The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a marked load", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_DATA_FROM_RL2L3_SHR], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_DATA_FROM_RL2L3_SHR] }, [ POWER7_PME_PM_DTLB_MISS_16M ] = { .pme_name = "PM_DTLB_MISS_16M", .pme_code = 0x4c05e, .pme_short_desc = "Data TLB miss for 16M page", .pme_long_desc = "Data TLB references to 16MB pages that missed the TLB. Page size is determined at TLB reload time.", .pme_event_ids = power7_event_ids[POWER7_PME_PM_DTLB_MISS_16M], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_DTLB_MISS_16M] }, [ POWER7_PME_PM_MRK_LSU_FIN ] = { .pme_name = "PM_MRK_LSU_FIN", .pme_code = 0x40032, .pme_short_desc = "Marked LSU instruction finished", .pme_long_desc = "One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete", .pme_event_ids = power7_event_ids[POWER7_PME_PM_MRK_LSU_FIN], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_MRK_LSU_FIN] }, [ POWER7_PME_PM_LSU1_LMQ_LHR_MERGE ] = { .pme_name = "PM_LSU1_LMQ_LHR_MERGE", .pme_code = 0xd09a, .pme_short_desc = "LS1 Load Merge with another cacheline request", .pme_long_desc = "LS1 Load Merge with another cacheline request", .pme_event_ids = power7_event_ids[POWER7_PME_PM_LSU1_LMQ_LHR_MERGE], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_LSU1_LMQ_LHR_MERGE] }, [ POWER7_PME_PM_IFU_FIN ] = { .pme_name = "PM_IFU_FIN", .pme_code = 0x40066, .pme_short_desc = "IFU Finished a (non-branch) instruction", .pme_long_desc = "The Instruction Fetch Unit finished an instruction", .pme_event_ids = power7_event_ids[POWER7_PME_PM_IFU_FIN], .pme_group_vector = power7_group_vecs[POWER7_PME_PM_IFU_FIN] } }; #define POWER7_PME_EVENT_COUNT 517 static const int power7_group_event_ids[][POWER7_NUM_EVENT_COUNTERS] = { [ 0 ] = { 21, 225, 75, 75, 0, 0 }, [ 1 ] = { 10, 11, 3, 8, 0, 0 }, [ 2 ] = { 9, 9, 9, 13, 0, 0 }, [ 3 ] = { 16, 13, 8, 3, 0, 0 }, [ 4 ] = { 5, 14, 7, 4, 0, 0 }, [ 5 ] = { 12, 4, 8, 11, 0, 0 }, [ 6 ] = { 10, 11, 10, 14, 0, 0 }, [ 7 ] = { 5, 9, 9, 13, 0, 0 }, [ 8 ] = { 8, 9, 9, 13, 0, 0 }, [ 9 ] = { 4, 9, 9, 13, 0, 0 }, [ 10 ] = { 77, 40, 89, 221, 0, 0 }, [ 11 ] = { 18, 244, 38, 87, 0, 0 }, [ 12 ] = { 40, 41, 39, 38, 0, 0 }, [ 13 ] = { 30, 31, 27, 29, 0, 0 }, [ 14 ] = { 80, 31, 27, 29, 0, 0 }, [ 15 ] = { 39, 25, 117, 105, 0, 0 }, [ 16 ] = { 21, 223, 117, 214, 0, 0 }, [ 17 ] = { 21, 223, 117, 212, 0, 0 }, [ 18 ] = { 39, 82, 74, 214, 0, 0 }, [ 19 ] = { 77, 40, 89, 75, 0, 0 }, [ 20 ] = { 223, 85, 218, 81, 0, 0 }, [ 21 ] = { 91, 221, 85, 210, 0, 0 }, [ 22 ] = { 224, 223, 86, 213, 0, 0 }, [ 23 ] = { 93, 220, 220, 213, 0, 0 }, [ 24 ] = { 225, 222, 219, 211, 0, 0 }, [ 25 ] = { 92, 84, 84, 84, 0, 0 }, [ 26 ] = { 92, 86, 84, 82, 0, 0 }, [ 27 ] = { 91, 87, 86, 83, 0, 0 }, [ 28 ] = { 223, 221, 220, 212, 0, 0 }, [ 29 ] = { 223, 221, 74, 23, 0, 0 }, [ 30 ] = { 225, 224, 74, 210, 0, 0 }, [ 31 ] = { 80, 220, 220, 213, 0, 0 }, [ 32 ] = { 222, 38, 48, 47, 0, 0 }, [ 33 ] = { 222, 38, 34, 47, 0, 0 }, [ 34 ] = { 117, 112, 113, 137, 0, 0 }, [ 35 ] = { 46, 48, 44, 40, 0, 0 }, [ 36 ] = { 48, 45, 119, 126, 0, 0 }, [ 37 ] = { 44, 23, 42, 40, 0, 0 }, [ 38 ] = { 126, 122, 120, 114, 0, 0 }, [ 39 ] = { 126, 150, 165, 40, 0, 0 }, [ 40 ] = { 127, 151, 166, 40, 0, 0 }, [ 41 ] = { 124, 148, 163, 40, 0, 0 }, [ 42 ] = { 125, 149, 164, 40, 0, 0 }, [ 43 ] = { 63, 69, 69, 68, 0, 0 }, [ 44 ] = { 0, 0, 0, 0, 0, 0 }, [ 45 ] = { 241, 239, 234, 229, 0, 0 }, [ 46 ] = { 0, 0, 0, 0, 0, 0 }, [ 47 ] = { 0, 0, 0, 0, 0, 0 }, [ 48 ] = { 242, 241, 237, 232, 0, 0 }, [ 49 ] = { 0, 0, 0, 0, 0, 0 }, [ 50 ] = { 49, 50, 49, 48, 0, 0 }, [ 51 ] = { 50, 225, 74, 49, 0, 0 }, [ 52 ] = { 21, 50, 49, 48, 0, 0 }, [ 53 ] = { 49, 50, 17, 75, 0, 0 }, [ 54 ] = { 106, 100, 99, 91, 0, 0 }, [ 55 ] = { 101, 23, 98, 75, 0, 0 }, [ 56 ] = { 106, 100, 100, 92, 0, 0 }, [ 57 ] = { 108, 97, 74, 23, 0, 0 }, [ 58 ] = { 80, 23, 96, 96, 0, 0 }, [ 59 ] = { 80, 23, 95, 95, 0, 0 }, [ 60 ] = { 107, 101, 74, 23, 0, 0 }, [ 61 ] = { 210, 211, 207, 203, 0, 0 }, [ 62 ] = { 214, 215, 211, 207, 0, 0 }, [ 63 ] = { 64, 63, 62, 58, 0, 0 }, [ 64 ] = { 23, 77, 90, 0, 0, 0 }, [ 65 ] = { 24, 23, 90, 75, 0, 0 }, [ 66 ] = { 27, 29, 90, 75, 0, 0 }, [ 67 ] = { 139, 157, 172, 127, 0, 0 }, [ 68 ] = { 139, 134, 137, 131, 0, 0 }, [ 69 ] = { 142, 138, 17, 75, 0, 0 }, [ 70 ] = { 141, 158, 173, 75, 0, 0 }, [ 71 ] = { 136, 156, 171, 75, 0, 0 }, [ 72 ] = { 52, 51, 50, 23, 0, 0 }, [ 73 ] = { 53, 56, 54, 54, 0, 0 }, [ 74 ] = { 99, 94, 74, 23, 0, 0 }, [ 75 ] = { 100, 96, 74, 23, 0, 0 }, [ 76 ] = { 37, 38, 34, 0, 0, 0 }, [ 77 ] = { 238, 38, 34, 226, 0, 0 }, [ 78 ] = { 32, 34, 33, 34, 0, 0 }, [ 79 ] = { 222, 219, 217, 209, 0, 0 }, [ 80 ] = { 0, 77, 56, 0, 0, 0 }, [ 81 ] = { 0, 23, 74, 0, 0, 0 }, [ 82 ] = { 75, 73, 63, 60, 0, 0 }, [ 83 ] = { 71, 66, 65, 63, 0, 0 }, [ 84 ] = { 77, 92, 74, 23, 0, 0 }, [ 85 ] = { 23, 17, 90, 20, 0, 0 }, [ 86 ] = { 49, 19, 55, 19, 0, 0 }, [ 87 ] = { 237, 20, 25, 21, 0, 0 }, [ 88 ] = { 42, 21, 201, 22, 0, 0 }, [ 89 ] = { 19, 22, 202, 18, 0, 0 }, [ 90 ] = { 20, 18, 74, 52, 0, 0 }, [ 91 ] = { 52, 53, 87, 51, 0, 0 }, [ 92 ] = { 23, 26, 24, 27, 0, 0 }, [ 93 ] = { 24, 27, 23, 26, 0, 0 }, [ 94 ] = { 22, 28, 20, 26, 0, 0 }, [ 95 ] = { 25, 29, 18, 24, 0, 0 }, [ 96 ] = { 26, 24, 19, 25, 0, 0 }, [ 97 ] = { 27, 29, 21, 26, 0, 0 }, [ 98 ] = { 28, 28, 18, 24, 0, 0 }, [ 99 ] = { 80, 26, 22, 27, 0, 0 }, [ 100 ] = { 23, 25, 90, 105, 0, 0 }, [ 101 ] = { 27, 29, 19, 24, 0, 0 }, [ 102 ] = { 23, 25, 22, 214, 0, 0 }, [ 103 ] = { 27, 24, 24, 27, 0, 0 }, [ 104 ] = { 30, 76, 19, 24, 0, 0 }, [ 105 ] = { 22, 76, 24, 27, 0, 0 }, [ 106 ] = { 22, 76, 90, 27, 0, 0 }, [ 107 ] = { 83, 80, 81, 79, 0, 0 }, [ 108 ] = { 84, 78, 76, 80, 0, 0 }, [ 109 ] = { 81, 82, 77, 76, 0, 0 }, [ 110 ] = { 85, 81, 79, 78, 0, 0 }, [ 111 ] = { 86, 83, 80, 79, 0, 0 }, [ 112 ] = { 87, 82, 81, 79, 0, 0 }, [ 113 ] = { 88, 83, 77, 76, 0, 0 }, [ 114 ] = { 89, 82, 81, 79, 0, 0 }, [ 115 ] = { 87, 78, 82, 80, 0, 0 }, [ 116 ] = { 83, 80, 74, 23, 0, 0 }, [ 117 ] = { 88, 83, 81, 75, 0, 0 }, [ 118 ] = { 21, 76, 77, 76, 0, 0 }, [ 119 ] = { 81, 76, 82, 80, 0, 0 }, [ 120 ] = { 120, 106, 115, 89, 0, 0 }, [ 121 ] = { 122, 111, 118, 105, 0, 0 }, [ 122 ] = { 270, 291, 263, 280, 0, 0 }, [ 123 ] = { 273, 294, 266, 283, 0, 0 }, [ 124 ] = { 249, 248, 264, 281, 0, 0 }, [ 125 ] = { 280, 302, 249, 75, 0, 0 }, [ 126 ] = { 281, 303, 250, 75, 0, 0 }, [ 127 ] = { 267, 289, 307, 75, 0, 0 }, [ 128 ] = { 253, 274, 291, 75, 0, 0 }, [ 129 ] = { 256, 277, 295, 75, 0, 0 }, [ 130 ] = { 266, 288, 306, 75, 0, 0 }, [ 131 ] = { 265, 287, 304, 255, 0, 0 }, [ 132 ] = { 260, 282, 299, 75, 0, 0 }, [ 133 ] = { 261, 283, 300, 75, 0, 0 }, [ 134 ] = { 262, 284, 302, 75, 0, 0 }, [ 135 ] = { 263, 285, 303, 75, 0, 0 }, [ 136 ] = { 248, 249, 244, 75, 0, 0 }, [ 137 ] = { 268, 290, 274, 75, 0, 0 }, [ 138 ] = { 264, 286, 267, 233, 0, 0 }, [ 139 ] = { 298, 298, 301, 299, 0, 0 }, [ 140 ] = { 254, 275, 293, 75, 0, 0 }, [ 141 ] = { 259, 281, 298, 75, 0, 0 }, [ 142 ] = { 255, 276, 294, 75, 0, 0 }, [ 143 ] = { 16, 225, 74, 242, 0, 0 }, [ 144 ] = { 129, 264, 249, 234, 0, 0 }, [ 145 ] = { 260, 254, 249, 234, 0, 0 }, [ 146 ] = { 42, 254, 247, 234, 0, 0 }, [ 147 ] = { 266, 254, 251, 240, 0, 0 }, [ 148 ] = { 131, 128, 129, 131, 0, 0 }, [ 149 ] = { 128, 132, 118, 112, 0, 0 }, [ 150 ] = { 161, 170, 128, 119, 0, 0 }, [ 151 ] = { 147, 159, 174, 75, 0, 0 }, [ 152 ] = { 149, 142, 140, 75, 0, 0 }, [ 153 ] = { 146, 130, 128, 75, 0, 0 }, [ 154 ] = { 132, 129, 139, 75, 0, 0 }, [ 155 ] = { 98, 152, 167, 75, 0, 0 }, [ 156 ] = { 105, 99, 17, 75, 0, 0 }, [ 157 ] = { 102, 95, 17, 75, 0, 0 }, [ 158 ] = { 90, 79, 83, 75, 0, 0 }, [ 159 ] = { 41, 43, 232, 23, 0, 0 }, [ 160 ] = { 0, 58, 75, 0, 0, 0 }, [ 161 ] = { 58, 53, 17, 52, 0, 0 }, [ 162 ] = { 57, 4, 3, 3, 0, 0 }, [ 163 ] = { 97, 70, 71, 75, 0, 0 }, [ 164 ] = { 246, 58, 17, 74, 0, 0 }, [ 165 ] = { 7, 43, 90, 3, 0, 0 }, [ 166 ] = { 43, 49, 138, 3, 0, 0 }, [ 167 ] = { 144, 114, 92, 57, 0, 0 }, [ 168 ] = { 42, 23, 55, 75, 0, 0 }, [ 169 ] = { 80, 233, 232, 40, 0, 0 }, [ 170 ] = { 52, 233, 38, 3, 0, 0 }, [ 171 ] = { 21, 23, 74, 74, 0, 0 }, [ 172 ] = { 236, 23, 175, 75, 0, 0 }, [ 173 ] = { 94, 23, 87, 75, 0, 0 }, [ 174 ] = { 181, 23, 176, 75, 0, 0 }, [ 175 ] = { 21, 226, 88, 36, 0, 0 }, [ 176 ] = { 109, 103, 103, 23, 0, 0 }, [ 177 ] = { 229, 227, 225, 219, 0, 0 }, [ 178 ] = { 111, 107, 105, 101, 0, 0 }, [ 179 ] = { 110, 104, 106, 97, 0, 0 }, [ 180 ] = { 21, 115, 146, 154, 0, 0 }, [ 181 ] = { 21, 116, 147, 155, 0, 0 }, [ 182 ] = { 29, 114, 145, 153, 0, 0 }, [ 183 ] = { 115, 110, 17, 102, 0, 0 }, [ 184 ] = { 21, 123, 153, 161, 0, 0 }, [ 185 ] = { 21, 124, 154, 162, 0, 0 }, [ 186 ] = { 103, 102, 103, 23, 0, 0 }, [ 187 ] = { 114, 135, 229, 224, 0, 0 }, [ 188 ] = { 17, 16, 229, 224, 0, 0 }, [ 189 ] = { 2, 1, 17, 75, 0, 0 }, [ 190 ] = { 90, 77, 83, 75, 0, 0 }, [ 191 ] = { 104, 98, 94, 90, 0, 0 }, [ 192 ] = { 80, 23, 93, 90, 0, 0 }, [ 193 ] = { 80, 23, 102, 214, 0, 0 }, [ 194 ] = { 80, 23, 101, 94, 0, 0 }, [ 195 ] = { 80, 23, 97, 214, 0, 0 }, [ 196 ] = { 80, 225, 17, 93, 0, 0 }, [ 197 ] = { 77, 75, 72, 75, 0, 0 }, [ 198 ] = { 31, 35, 17, 75, 0, 0 }, [ 199 ] = { 21, 38, 35, 75, 0, 0 }, [ 200 ] = { 226, 225, 17, 215, 0, 0 }, [ 201 ] = { 219, 218, 213, 208, 0, 0 }, [ 202 ] = { 221, 218, 216, 208, 0, 0 }, [ 203 ] = { 220, 225, 214, 75, 0, 0 }, [ 204 ] = { 218, 225, 215, 75, 0, 0 }, [ 205 ] = { 47, 37, 227, 75, 0, 0 }, [ 206 ] = { 77, 92, 228, 105, 0, 0 }, [ 207 ] = { 21, 117, 38, 87, 0, 0 }, [ 208 ] = { 1, 225, 17, 215, 0, 0 }, [ 209 ] = { 42, 225, 17, 214, 0, 0 }, [ 210 ] = { 0, 225, 75, 0, 0, 0 }, [ 211 ] = { 80, 233, 228, 105, 0, 0 }, [ 212 ] = { 80, 25, 90, 105, 0, 0 }, [ 213 ] = { 77, 92, 74, 87, 0, 0 }, [ 214 ] = { 236, 236, 231, 225, 0, 0 }, [ 215 ] = { 80, 43, 232, 23, 0, 0 }, [ 216 ] = { 90, 77, 234, 40, 0, 0 }, [ 217 ] = { 52, 77, 17, 3, 0, 0 }, [ 218 ] = { 183, 195, 177, 75, 0, 0 }, [ 219 ] = { 188, 179, 179, 75, 0, 0 }, [ 220 ] = { 185, 181, 74, 174, 0, 0 }, [ 221 ] = { 187, 76, 180, 177, 0, 0 }, [ 222 ] = { 189, 188, 183, 75, 0, 0 }, [ 223 ] = { 185, 182, 181, 75, 0, 0 }, [ 224 ] = { 186, 186, 74, 175, 0, 0 }, [ 225 ] = { 187, 185, 74, 176, 0, 0 }, [ 226 ] = { 189, 189, 74, 178, 0, 0 }, [ 227 ] = { 80, 178, 178, 171, 0, 0 }, [ 228 ] = { 80, 187, 183, 179, 0, 0 }, [ 229 ] = { 197, 180, 74, 172, 0, 0 }, [ 230 ] = { 201, 200, 74, 23, 0, 0 }, [ 231 ] = { 80, 23, 190, 189, 0, 0 }, [ 232 ] = { 204, 196, 74, 193, 0, 0 }, [ 233 ] = { 195, 194, 187, 75, 0, 0 }, [ 234 ] = { 208, 208, 200, 75, 0, 0 }, [ 235 ] = { 80, 192, 185, 181, 0, 0 }, [ 236 ] = { 192, 192, 185, 75, 0, 0 }, [ 237 ] = { 80, 190, 184, 180, 0, 0 }, [ 238 ] = { 191, 190, 184, 75, 0, 0 }, [ 239 ] = { 196, 76, 188, 185, 0, 0 }, [ 240 ] = { 80, 203, 197, 196, 0, 0 }, [ 241 ] = { 205, 207, 199, 75, 0, 0 }, [ 242 ] = { 80, 205, 197, 195, 0, 0 }, [ 243 ] = { 206, 204, 74, 197, 0, 0 }, [ 244 ] = { 207, 206, 74, 198, 0, 0 }, [ 245 ] = { 209, 76, 186, 184, 0, 0 }, [ 246 ] = { 80, 193, 186, 186, 0, 0 }, [ 247 ] = { 80, 177, 194, 186, 0, 0 }, [ 248 ] = { 193, 76, 204, 183, 0, 0 }, [ 249 ] = { 194, 191, 202, 75, 0, 0 }, [ 250 ] = { 60, 225, 74, 182, 0, 0 }, [ 251 ] = { 204, 76, 195, 193, 0, 0 }, [ 252 ] = { 21, 23, 74, 186, 0, 0 }, [ 253 ] = { 248, 249, 244, 235, 0, 0 }, [ 254 ] = { 80, 233, 228, 106, 0, 0 }, [ 255 ] = { 80, 233, 111, 105, 0, 0 } }; static pmg_power_group_t power7_groups[] = { [ 0 ] = { .pmg_name = "pm_utilization", .pmg_desc = "CPI and utilization data", .pmg_event_ids = power7_group_event_ids[0], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000001ef4f202ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 1 ] = { .pmg_name = "pm_branch1", .pmg_desc = "Branch operations", .pmg_event_ids = power7_group_event_ids[1], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x44440000a0a2a4aeULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 2 ] = { .pmg_name = "pm_branch2", .pmg_desc = "Branch operations", .pmg_event_ids = power7_group_event_ids[2], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x444400009ca8a0a2ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 3 ] = { .pmg_name = "pm_branch3", .pmg_desc = "Branch operations", .pmg_event_ids = power7_group_event_ids[3], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0040000068049cf6ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 4 ] = { .pmg_name = "pm_branch4", .pmg_desc = "Branch operations", .pmg_event_ids = power7_group_event_ids[4], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x44440000ac9eaea4ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 5 ] = { .pmg_name = "pm_branch5", .pmg_desc = "Branch operations", .pmg_event_ids = power7_group_event_ids[5], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4444000caaae9ca8ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 6 ] = { .pmg_name = "pm_branch6", .pmg_desc = "Branch operations", .pmg_event_ids = power7_group_event_ids[6], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x44440000a0a2a8aaULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 7 ] = { .pmg_name = "pm_branch7", .pmg_desc = "Branch operations", .pmg_event_ids = power7_group_event_ids[7], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x44440000aca8a0a2ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 8 ] = { .pmg_name = "pm_branch8", .pmg_desc = "Branch operations", .pmg_event_ids = power7_group_event_ids[8], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x44440000aea8a0a2ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 9 ] = { .pmg_name = "pm_branch9", .pmg_desc = "Branch operations", .pmg_event_ids = power7_group_event_ids[9], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x44440000a4a8a0a2ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 10 ] = { .pmg_name = "pm_slb_miss", .pmg_desc = "SLB Misses", .pmg_event_ids = power7_group_event_ids[10], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0ddd0001f6909290ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 11 ] = { .pmg_name = "pm_tlb_miss", .pmg_desc = "TLB Misses", .pmg_event_ids = power7_group_event_ids[11], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x500000008866fcfcULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 12 ] = { .pmg_name = "pm_dtlb_miss", .pmg_desc = "DTLB Misses", .pmg_event_ids = power7_group_event_ids[12], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xcccc00005e5e5e5eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 13 ] = { .pmg_name = "pm_derat_miss1", .pmg_desc = "DERAT misses", .pmg_event_ids = power7_group_event_ids[13], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xcccc00005c5c5c5cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 14 ] = { .pmg_name = "pm_derat_miss2", .pmg_desc = "DERAT misses", .pmg_event_ids = power7_group_event_ids[14], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0ccc0000025c5c5cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 15 ] = { .pmg_name = "pm_misc_miss1", .pmg_desc = "Misses", .pmg_event_ids = power7_group_event_ids[15], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xd0c0000090fe5af0ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 16 ] = { .pmg_name = "pm_misc_miss2", .pmg_desc = "Misses", .pmg_event_ids = power7_group_event_ids[16], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0cc000001e585afaULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 17 ] = { .pmg_name = "pm_misc_miss3", .pmg_desc = "Misses", .pmg_event_ids = power7_group_event_ids[17], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0ccc00001e585a58ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 18 ] = { .pmg_name = "pm_misc_miss4", .pmg_desc = "Misses", .pmg_event_ids = power7_group_event_ids[18], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xd4000000904802faULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 19 ] = { .pmg_name = "pm_misc_miss5", .pmg_desc = "Misses", .pmg_event_ids = power7_group_event_ids[19], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0dd00000f6909202ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 20 ] = { .pmg_name = "pm_pteg1", .pmg_desc = "PTEG sources", .pmg_event_ids = power7_group_event_ids[20], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xcece000050505654ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 21 ] = { .pmg_name = "pm_pteg2", .pmg_desc = "PTEG sources", .pmg_event_ids = power7_group_event_ids[21], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xecec000050505454ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 22 ] = { .pmg_name = "pm_pteg3", .pmg_desc = "PTEG sources", .pmg_event_ids = power7_group_event_ids[22], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xccec000054585252ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 23 ] = { .pmg_name = "pm_pteg4", .pmg_desc = "PTEG sources", .pmg_event_ids = power7_group_event_ids[23], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xeccc000052525252ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 24 ] = { .pmg_name = "pm_pteg5", .pmg_desc = "PTEG sources", .pmg_event_ids = power7_group_event_ids[24], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xcccc000052565456ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 25 ] = { .pmg_name = "pm_pteg6", .pmg_desc = "PTEG sources", .pmg_event_ids = power7_group_event_ids[25], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xeeee000054525652ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 26 ] = { .pmg_name = "pm_pteg7", .pmg_desc = "PTEG sources", .pmg_event_ids = power7_group_event_ids[26], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xeeee000054565656ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 27 ] = { .pmg_name = "pm_pteg8", .pmg_desc = "PTEG sources", .pmg_event_ids = power7_group_event_ids[27], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xeeee000050585258ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 28 ] = { .pmg_name = "pm_pteg9", .pmg_desc = "PTEG sources", .pmg_event_ids = power7_group_event_ids[28], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xcccc000050505258ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 29 ] = { .pmg_name = "pm_pteg10", .pmg_desc = "PTEG sources", .pmg_event_ids = power7_group_event_ids[29], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xcc0000005050021eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 30 ] = { .pmg_name = "pm_pteg11", .pmg_desc = "PTEG sources", .pmg_event_ids = power7_group_event_ids[30], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xcc0c000052540254ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 31 ] = { .pmg_name = "pm_pteg12", .pmg_desc = "PTEG sources", .pmg_event_ids = power7_group_event_ids[31], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0ccc000002525252ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 32 ] = { .pmg_name = "pm_freq1", .pmg_desc = "Frequency events", .pmg_event_ids = power7_group_event_ids[32], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000006e060c0cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 33 ] = { .pmg_name = "pm_freq2", .pmg_desc = "Frequency events", .pmg_event_ids = power7_group_event_ids[33], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000006e06060cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 34 ] = { .pmg_name = "pm_L1_ref", .pmg_desc = "L1 references", .pmg_event_ids = power7_group_event_ids[34], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xcccd0008808082a6ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 35 ] = { .pmg_name = "pm_flush1", .pmg_desc = "Flushes", .pmg_event_ids = power7_group_event_ids[35], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x22200000888a8cf8ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 36 ] = { .pmg_name = "pm_flush2", .pmg_desc = "Flushes", .pmg_event_ids = power7_group_event_ids[36], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x222c000086828eaaULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 37 ] = { .pmg_name = "pm_flush", .pmg_desc = "Flushes", .pmg_event_ids = power7_group_event_ids[37], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x20000000821e12f8ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 38 ] = { .pmg_name = "pm_lsu_flush1", .pmg_desc = "LSU Flush", .pmg_event_ids = power7_group_event_ids[38], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xcccc000fb0b4b8bcULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 39 ] = { .pmg_name = "pm_lsu_flush2", .pmg_desc = "LSU Flush ULD", .pmg_event_ids = power7_group_event_ids[39], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xccc00008b0b0b2f8ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 40 ] = { .pmg_name = "pm_lsu_flush3", .pmg_desc = "LSU Flush UST", .pmg_event_ids = power7_group_event_ids[40], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xccc00008b4b4b6f8ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 41 ] = { .pmg_name = "pm_lsu_flush4", .pmg_desc = "LSU Flush LRQ", .pmg_event_ids = power7_group_event_ids[41], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xccc00008b8b8baf8ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 42 ] = { .pmg_name = "pm_lsu_flush5", .pmg_desc = "LSU Flush SRQ", .pmg_event_ids = power7_group_event_ids[42], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xccc00008bcbcbef8ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 43 ] = { .pmg_name = "pm_prefetch", .pmg_desc = "I cache Prefetches", .pmg_event_ids = power7_group_event_ids[43], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x04440000188a968eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 44 ] = { .pmg_name = "", .pmg_desc = "", .pmg_event_ids = power7_group_event_ids[44], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000000000000ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 45 ] = { .pmg_name = "pm_thread_cyc2", .pmg_desc = "Thread cycles", .pmg_event_ids = power7_group_event_ids[45], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00040000120cf4b0ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 46 ] = { .pmg_name = "", .pmg_desc = "", .pmg_event_ids = power7_group_event_ids[46], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000000000000ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 47 ] = { .pmg_name = "", .pmg_desc = "", .pmg_event_ids = power7_group_event_ids[47], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000000000000ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 48 ] = { .pmg_name = "pm_thread_cyc5", .pmg_desc = "Thread cycles", .pmg_event_ids = power7_group_event_ids[48], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x44440000b0b2b4b6ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 49 ] = { .pmg_name = "", .pmg_desc = "", .pmg_event_ids = power7_group_event_ids[49], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000000000000ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 50 ] = { .pmg_name = "pm_fxu1", .pmg_desc = "FXU events", .pmg_event_ids = power7_group_event_ids[50], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000000e0e0e0eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 51 ] = { .pmg_name = "pm_fxu2", .pmg_desc = "FXU events", .pmg_event_ids = power7_group_event_ids[51], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000004f40204ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 52 ] = { .pmg_name = "pm_fxu3", .pmg_desc = "FXU events", .pmg_event_ids = power7_group_event_ids[52], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000001e0e0e0eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 53 ] = { .pmg_name = "pm_fxu4", .pmg_desc = "FXU events", .pmg_event_ids = power7_group_event_ids[53], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000000e0e1e02ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 54 ] = { .pmg_name = "pm_L2_RCLD", .pmg_desc = "L2 RC load events ", .pmg_event_ids = power7_group_event_ids[54], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x6666400080808082ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 55 ] = { .pmg_name = "pm_L2_RC", .pmg_desc = "RC related events", .pmg_event_ids = power7_group_event_ids[55], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x60606000821e8002ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 56 ] = { .pmg_name = "pm_L2_RCST", .pmg_desc = "L2 RC Store Events", .pmg_event_ids = power7_group_event_ids[56], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x6666400080808280ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 57 ] = { .pmg_name = "pm_L2_ldst_1", .pmg_desc = "L2 load/store ", .pmg_event_ids = power7_group_event_ids[57], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x660000008280021eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 58 ] = { .pmg_name = "pm_L2_ldst_2", .pmg_desc = "L2 load/store ", .pmg_event_ids = power7_group_event_ids[58], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00662000021e8282ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 59 ] = { .pmg_name = "pm_L2_ldst_3", .pmg_desc = "L2 load/store ", .pmg_event_ids = power7_group_event_ids[59], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00662000021e8080ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 60 ] = { .pmg_name = "pm_L2_RCSTLD", .pmg_desc = "L2 RC Load/Store Events", .pmg_event_ids = power7_group_event_ids[60], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x660040008282021eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 61 ] = { .pmg_name = "pm_nest1", .pmg_desc = "Nest Events", .pmg_event_ids = power7_group_event_ids[61], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000081838587ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 62 ] = { .pmg_name = "pm_nest2", .pmg_desc = "Nest Events", .pmg_event_ids = power7_group_event_ids[62], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000898b8d8fULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 63 ] = { .pmg_name = "pm_L2_redir_pref", .pmg_desc = "L2 redirect and prefetch", .pmg_event_ids = power7_group_event_ids[63], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x44440000989a8882ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 64 ] = { .pmg_name = "pm_dlatencies1", .pmg_desc = "Data latencies", .pmg_event_ids = power7_group_event_ids[64], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xc000000040f2f6f2ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 65 ] = { .pmg_name = "pm_dlatencies2", .pmg_desc = "Data latencies", .pmg_event_ids = power7_group_event_ids[65], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xc0000000481ef602ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 66 ] = { .pmg_name = "pm_dlatencies3", .pmg_desc = "Data latencies", .pmg_event_ids = power7_group_event_ids[66], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xcc0000004244f602ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 67 ] = { .pmg_name = "pm_rejects1", .pmg_desc = "Reject event", .pmg_event_ids = power7_group_event_ids[67], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0ccc000164acaeacULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 68 ] = { .pmg_name = "pm_rejects2", .pmg_desc = "Reject events", .pmg_event_ids = power7_group_event_ids[68], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00c000026464a808ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 69 ] = { .pmg_name = "pm_rejects3", .pmg_desc = "Set mispredictions rejects", .pmg_event_ids = power7_group_event_ids[69], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xcc000008a8a81e02ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 70 ] = { .pmg_name = "pm_lsu_reject", .pmg_desc = "LSU Reject Event", .pmg_event_ids = power7_group_event_ids[70], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xccc00008a4a4a602ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 71 ] = { .pmg_name = "pm_lsu_ncld", .pmg_desc = "Non cachable loads", .pmg_event_ids = power7_group_event_ids[71], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xccc000088c8c8e02ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 72 ] = { .pmg_name = "pm_gct1", .pmg_desc = "GCT events", .pmg_event_ids = power7_group_event_ids[72], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00400000f808861eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 73 ] = { .pmg_name = "pm_gct2", .pmg_desc = "GCT Events", .pmg_event_ids = power7_group_event_ids[73], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x222200009c9ea0a2ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 74 ] = { .pmg_name = "pm_L2_castout_invalidate_1", .pmg_desc = "L2 castout and invalidate events", .pmg_event_ids = power7_group_event_ids[74], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x660020008082021eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 75 ] = { .pmg_name = "pm_L2_castout_invalidate_2", .pmg_desc = "L2 castout and invalidate events", .pmg_event_ids = power7_group_event_ids[75], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x660020008280021eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 76 ] = { .pmg_name = "pm_disp_held1", .pmg_desc = "Dispatch held conditions", .pmg_event_ids = power7_group_event_ids[76], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000060606f2ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 77 ] = { .pmg_name = "pm_disp_held2", .pmg_desc = "Dispatch held conditions", .pmg_event_ids = power7_group_event_ids[77], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000016060606ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 78 ] = { .pmg_name = "pm_disp_clb_held", .pmg_desc = "Display CLB held conditions", .pmg_event_ids = power7_group_event_ids[78], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x2222000092949698ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 79 ] = { .pmg_name = "pm_power", .pmg_desc = "Power Events", .pmg_event_ids = power7_group_event_ids[79], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000006e6e6e6eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 80 ] = { .pmg_name = "pm_dispatch1", .pmg_desc = "Groups and instructions dispatched", .pmg_event_ids = power7_group_event_ids[80], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000f2f20af2ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 81 ] = { .pmg_name = "pm_dispatch2", .pmg_desc = "Groups and instructions dispatched", .pmg_event_ids = power7_group_event_ids[81], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000f21e02f2ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 82 ] = { .pmg_name = "pm_ic", .pmg_desc = "I cache operations", .pmg_event_ids = power7_group_event_ids[82], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4444000f888c9098ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 83 ] = { .pmg_name = "pm_ic_pref_cancel", .pmg_desc = "Instruction pre-fetched cancelled", .pmg_event_ids = power7_group_event_ids[83], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4444000190929490ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 84 ] = { .pmg_name = "pm_ic_miss", .pmg_desc = "Icache and Ierat miss events", .pmg_event_ids = power7_group_event_ids[84], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000f6fc021eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 85 ] = { .pmg_name = "pm_cpi_stack1", .pmg_desc = "CPI stack breakdown", .pmg_event_ids = power7_group_event_ids[85], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xc00000004016f618ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 86 ] = { .pmg_name = "pm_cpi_stack2", .pmg_desc = "CPI stack breakdown", .pmg_event_ids = power7_group_event_ids[86], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000000e140414ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 87 ] = { .pmg_name = "pm_cpi_stack3", .pmg_desc = "CPI stack breakdown", .pmg_event_ids = power7_group_event_ids[87], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000026121a16ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 88 ] = { .pmg_name = "pm_cpi_stack4", .pmg_desc = "CPI stack breakdown", .pmg_event_ids = power7_group_event_ids[88], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000f4183e12ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 89 ] = { .pmg_name = "pm_cpi_stack5", .pmg_desc = "CPI stack breakdown", .pmg_event_ids = power7_group_event_ids[89], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000281c3f0aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 90 ] = { .pmg_name = "pm_cpi_stack6", .pmg_desc = "CPI stack breakdown", .pmg_event_ids = power7_group_event_ids[90], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000001c3c021cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 91 ] = { .pmg_name = "pm_cpi_stack7", .pmg_desc = "CPI stack breakdown", .pmg_event_ids = power7_group_event_ids[91], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000f81a141aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 92 ] = { .pmg_name = "pm_dsource1", .pmg_desc = "Data source information", .pmg_event_ids = power7_group_event_ids[92], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xcccc000040404242ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 93 ] = { .pmg_name = "pm_dsource2", .pmg_desc = "Data source information", .pmg_event_ids = power7_group_event_ids[93], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xcccc000048464a48ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 94 ] = { .pmg_name = "pm_dsource3", .pmg_desc = "Data source information", .pmg_event_ids = power7_group_event_ids[94], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xcccc00004a484648ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 95 ] = { .pmg_name = "pm_dsource4", .pmg_desc = "Data source information", .pmg_event_ids = power7_group_event_ids[95], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xcccc000044444c44ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 96 ] = { .pmg_name = "pm_dsource5", .pmg_desc = "Data source information", .pmg_event_ids = power7_group_event_ids[96], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xcccc00004e424446ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 97 ] = { .pmg_name = "pm_dsource6", .pmg_desc = "Data source information", .pmg_event_ids = power7_group_event_ids[97], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xcccc000042444e48ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 98 ] = { .pmg_name = "pm_dsource7", .pmg_desc = "Data source information", .pmg_event_ids = power7_group_event_ids[98], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xcccc00004c484c44ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 99 ] = { .pmg_name = "pm_dsource8", .pmg_desc = "Data source information", .pmg_event_ids = power7_group_event_ids[99], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0c0c00000240fe42ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 100 ] = { .pmg_name = "pm_dsource9", .pmg_desc = "Data source information", .pmg_event_ids = power7_group_event_ids[100], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xc000000040fef6f0ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 101 ] = { .pmg_name = "pm_dsource10", .pmg_desc = "Data source information", .pmg_event_ids = power7_group_event_ids[101], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xcccc000042444444ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 102 ] = { .pmg_name = "pm_dsource11", .pmg_desc = "Data source information", .pmg_event_ids = power7_group_event_ids[102], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xc000000040fefefaULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 103 ] = { .pmg_name = "pm_dsource12", .pmg_desc = "Data source information", .pmg_event_ids = power7_group_event_ids[103], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xcccc000042424242ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 104 ] = { .pmg_name = "pm_dsource13", .pmg_desc = "Data source information", .pmg_event_ids = power7_group_event_ids[104], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xc0cc00005c024444ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 105 ] = { .pmg_name = "pm_dsource14", .pmg_desc = "Data source information", .pmg_event_ids = power7_group_event_ids[105], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xc0cc00004a024242ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 106 ] = { .pmg_name = "pm_dsource15", .pmg_desc = "Data source information", .pmg_event_ids = power7_group_event_ids[106], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xc00c00004a02f642ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 107 ] = { .pmg_name = "pm_isource1", .pmg_desc = "Instruction source information", .pmg_event_ids = power7_group_event_ids[107], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4444000040404a48ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 108 ] = { .pmg_name = "pm_isource2", .pmg_desc = "Instruction source information", .pmg_event_ids = power7_group_event_ids[108], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4444000048424c42ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 109 ] = { .pmg_name = "pm_isource3", .pmg_desc = "Instruction source information", .pmg_event_ids = power7_group_event_ids[109], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x444400004a484444ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 110 ] = { .pmg_name = "pm_isource4", .pmg_desc = "Instruction source information", .pmg_event_ids = power7_group_event_ids[110], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4444000044464646ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 111 ] = { .pmg_name = "pm_isource5", .pmg_desc = "Instruction source information", .pmg_event_ids = power7_group_event_ids[111], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x444400004e444e48ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 112 ] = { .pmg_name = "pm_isource6", .pmg_desc = "Instruction source information", .pmg_event_ids = power7_group_event_ids[112], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4444000046484a48ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 113 ] = { .pmg_name = "pm_isource7", .pmg_desc = "Instruction source information", .pmg_event_ids = power7_group_event_ids[113], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4444000042444444ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 114 ] = { .pmg_name = "pm_isource8", .pmg_desc = "Instruction source information", .pmg_event_ids = power7_group_event_ids[114], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x444400004c484a48ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 115 ] = { .pmg_name = "pm_isource9", .pmg_desc = "Instruction source information", .pmg_event_ids = power7_group_event_ids[115], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4444000046424242ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 116 ] = { .pmg_name = "pm_isource10", .pmg_desc = "Instruction source information", .pmg_event_ids = power7_group_event_ids[116], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x440000004040021eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 117 ] = { .pmg_name = "pm_isource11", .pmg_desc = "Instruction source information", .pmg_event_ids = power7_group_event_ids[117], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x4440000042444a02ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 118 ] = { .pmg_name = "pm_isource12", .pmg_desc = "Instruction source information", .pmg_event_ids = power7_group_event_ids[118], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x004400001e024444ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 119 ] = { .pmg_name = "pm_isource13", .pmg_desc = "Instruction source information", .pmg_event_ids = power7_group_event_ids[119], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x404400004a024242ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 120 ] = { .pmg_name = "pm_prefetch1", .pmg_desc = "Prefetch events", .pmg_event_ids = power7_group_event_ids[120], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xdddd000fa8acb4b8ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 121 ] = { .pmg_name = "pm_prefetch2", .pmg_desc = "Prefetch events", .pmg_event_ids = power7_group_event_ids[121], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xdc00000cbc8066f0ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 122 ] = { .pmg_name = "pm_vsu0", .pmg_desc = "VSU Execution", .pmg_event_ids = power7_group_event_ids[122], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xaaaa00008082989aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 123 ] = { .pmg_name = "pm_vsu1", .pmg_desc = "VSU Execution", .pmg_event_ids = power7_group_event_ids[123], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xaaaa00009c9ea0a2ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 124 ] = { .pmg_name = "pm_vsu2", .pmg_desc = "VSU Execution", .pmg_event_ids = power7_group_event_ids[124], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xaaaa000c988c8c8eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 125 ] = { .pmg_name = "pm_vsu3", .pmg_desc = "VSU Execution", .pmg_event_ids = power7_group_event_ids[125], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xaaa0000284868402ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 126 ] = { .pmg_name = "pm_vsu4", .pmg_desc = "VSU Execution", .pmg_event_ids = power7_group_event_ids[126], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xaaa0000290929002ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 127 ] = { .pmg_name = "pm_vsu5", .pmg_desc = "VSU Execution", .pmg_event_ids = power7_group_event_ids[127], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xbbb0000880808202ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 128 ] = { .pmg_name = "pm_vsu6", .pmg_desc = "VSU Execution", .pmg_event_ids = power7_group_event_ids[128], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xaaa00008acacae02ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 129 ] = { .pmg_name = "pm_vsu7", .pmg_desc = "VSU Execution", .pmg_event_ids = power7_group_event_ids[129], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xaaa00008bcbcbe02ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 130 ] = { .pmg_name = "pm_vsu8", .pmg_desc = "VSU Execution", .pmg_event_ids = power7_group_event_ids[130], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xbbb000088c8c8e02ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 131 ] = { .pmg_name = "pm_vsu9", .pmg_desc = "VSU Execution", .pmg_event_ids = power7_group_event_ids[131], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xaaaa0008a8a8aaa4ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 132 ] = { .pmg_name = "pm_vsu10", .pmg_desc = "VSU Execution", .pmg_event_ids = power7_group_event_ids[132], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xaaa0000888888a02ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 133 ] = { .pmg_name = "pm_vsu11", .pmg_desc = "VSU Execution", .pmg_event_ids = power7_group_event_ids[133], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xaaa0000894949602ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 134 ] = { .pmg_name = "pm_vsu12", .pmg_desc = "VSU Execution", .pmg_event_ids = power7_group_event_ids[134], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xbbb0000888888a02ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 135 ] = { .pmg_name = "pm_vsu13", .pmg_desc = "VSU Execution", .pmg_event_ids = power7_group_event_ids[135], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xbbb0000884848602ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 136 ] = { .pmg_name = "pm_vsu14", .pmg_desc = "VSU Execution", .pmg_event_ids = power7_group_event_ids[136], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xaaa0000e809ca002ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 137 ] = { .pmg_name = "pm_vsu15", .pmg_desc = "VSU Execution", .pmg_event_ids = power7_group_event_ids[137], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xbbb0000890909c02ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 138 ] = { .pmg_name = "pm_vsu16", .pmg_desc = "VSU Execution", .pmg_event_ids = power7_group_event_ids[138], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xbbbb0008949496a0ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 139 ] = { .pmg_name = "pm_vsu17", .pmg_desc = "VSU Execution", .pmg_event_ids = power7_group_event_ids[139], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xbbbb0000989a929eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 140 ] = { .pmg_name = "pm_vsu18", .pmg_desc = "VSU Execution", .pmg_event_ids = power7_group_event_ids[140], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xaaa00008b0b0b202ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 141 ] = { .pmg_name = "pm_vsu19", .pmg_desc = "VSU Execution", .pmg_event_ids = power7_group_event_ids[141], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xaaa00008b4b4b602ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 142 ] = { .pmg_name = "pm_vsu20", .pmg_desc = "VSU Execution", .pmg_event_ids = power7_group_event_ids[142], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xaaa00008b8b8ba02ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 143 ] = { .pmg_name = "pm_vsu21", .pmg_desc = "VSU Execution", .pmg_event_ids = power7_group_event_ids[143], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000a000168f402bcULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 144 ] = { .pmg_name = "pm_vsu22", .pmg_desc = "VSU Execution", .pmg_event_ids = power7_group_event_ids[144], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xcbaa000f848c8480ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 145 ] = { .pmg_name = "pm_vsu23", .pmg_desc = "VSU Execution", .pmg_event_ids = power7_group_event_ids[145], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xaaaa000f88bc8480ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 146 ] = { .pmg_name = "pm_vsu24", .pmg_desc = "VSU Execution", .pmg_event_ids = power7_group_event_ids[146], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0aaa0007f4bcb880ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 147 ] = { .pmg_name = "pm_vsu25", .pmg_desc = "VSU Execution", .pmg_event_ids = power7_group_event_ids[147], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xbaaa000f8cbcb4b0ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 148 ] = { .pmg_name = "pm_lsu1", .pmg_desc = "LSU LMQ SRQ events", .pmg_event_ids = power7_group_event_ids[148], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xd0000000a43e1c08ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 149 ] = { .pmg_name = "pm_lsu2", .pmg_desc = "LSU events", .pmg_event_ids = power7_group_event_ids[149], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0c0200006690668eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 150 ] = { .pmg_name = "pm_lsu_lmq", .pmg_desc = "LSU LMQ Events", .pmg_event_ids = power7_group_event_ids[150], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xdddd0000989aa0a4ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 151 ] = { .pmg_name = "pm_lsu_srq1", .pmg_desc = "Store Request Queue Info", .pmg_event_ids = power7_group_event_ids[151], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xccc00008a0a0a202ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 152 ] = { .pmg_name = "pm_lsu_srq2", .pmg_desc = "Store Request Queue Info", .pmg_event_ids = power7_group_event_ids[152], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xddd0000096979c02ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 153 ] = { .pmg_name = "pm_lsu_s0_valid", .pmg_desc = "LSU Events", .pmg_event_ids = power7_group_event_ids[153], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xddd000009c9ea002ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 154 ] = { .pmg_name = "pm_lsu_s0_alloc", .pmg_desc = "LSU Events", .pmg_event_ids = power7_group_event_ids[154], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xddd00000a19f9d02ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 155 ] = { .pmg_name = "pm_l1_pref", .pmg_desc = "L1 pref Events", .pmg_event_ids = power7_group_event_ids[155], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xddd00008b8b8ba02ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 156 ] = { .pmg_name = "pm_l2_guess_1", .pmg_desc = "L2_Guess_events", .pmg_event_ids = power7_group_event_ids[156], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x6600800080801e02ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 157 ] = { .pmg_name = "pm_l2_guess_2", .pmg_desc = "L2_Guess_events", .pmg_event_ids = power7_group_event_ids[157], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x6600800082821e02ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 158 ] = { .pmg_name = "pm_misc1", .pmg_desc = "Misc events", .pmg_event_ids = power7_group_event_ids[158], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x04000000f0801602ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 159 ] = { .pmg_name = "pm_misc2", .pmg_desc = "Misc events", .pmg_event_ids = power7_group_event_ids[159], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x2000000080f8f81eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 160 ] = { .pmg_name = "pm_misc3", .pmg_desc = "Misc events", .pmg_event_ids = power7_group_event_ids[160], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000f20af2f2ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 161 ] = { .pmg_name = "pm_misc4", .pmg_desc = "Misc events", .pmg_event_ids = power7_group_event_ids[161], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000000c1a1e1cULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 162 ] = { .pmg_name = "pm_misc5", .pmg_desc = "Misc events", .pmg_event_ids = power7_group_event_ids[162], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x044000040aaea4f6ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 163 ] = { .pmg_name = "pm_misc6", .pmg_desc = "Misc events", .pmg_event_ids = power7_group_event_ids[163], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x444000028c8e8c02ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 164 ] = { .pmg_name = "pm_misc7", .pmg_desc = "Misc events", .pmg_event_ids = power7_group_event_ids[164], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000380a1e66ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 165 ] = { .pmg_name = "pm_misc8", .pmg_desc = "Misc events", .pmg_event_ids = power7_group_event_ids[165], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x40000000a6f8f6f6ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 166 ] = { .pmg_name = "pm_misc9", .pmg_desc = "Misc events", .pmg_event_ids = power7_group_event_ids[166], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x22c000008486a8f6ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 167 ] = { .pmg_name = "pm_misc10", .pmg_desc = "Misc events", .pmg_event_ids = power7_group_event_ids[167], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0dd400061aa8b884ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 168 ] = { .pmg_name = "pm_misc11", .pmg_desc = "Misc events", .pmg_event_ids = power7_group_event_ids[168], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000f41e0402ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 169 ] = { .pmg_name = "pm_misc_12", .pmg_desc = "Misc Events", .pmg_event_ids = power7_group_event_ids[169], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000002f0f8f8ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 170 ] = { .pmg_name = "pm_misc_13", .pmg_desc = "Misc Events", .pmg_event_ids = power7_group_event_ids[170], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000f8f0fcf6ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 171 ] = { .pmg_name = "pm_misc_14", .pmg_desc = "Misc Events", .pmg_event_ids = power7_group_event_ids[171], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000001e1e0266ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 172 ] = { .pmg_name = "pm_suspend", .pmg_desc = "SUSPENDED events", .pmg_event_ids = power7_group_event_ids[172], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00d00000001e9402ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 173 ] = { .pmg_name = "pm_iops", .pmg_desc = "Internal Operations events", .pmg_event_ids = power7_group_event_ids[173], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000141e1402ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 174 ] = { .pmg_name = "pm_sync", .pmg_desc = "sync", .pmg_event_ids = power7_group_event_ids[174], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xd0200000941e9a02ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 175 ] = { .pmg_name = "pm_seg", .pmg_desc = "Segment events", .pmg_event_ids = power7_group_event_ids[175], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x022200041ea4a4a6ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 176 ] = { .pmg_name = "pm_l3_hit", .pmg_desc = "L3 Hit Events", .pmg_event_ids = power7_group_event_ids[176], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xfff000008080801eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 177 ] = { .pmg_name = "pm_shl", .pmg_desc = "Shell Events", .pmg_event_ids = power7_group_event_ids[177], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x5555000080828486ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 178 ] = { .pmg_name = "pm_l3_pref", .pmg_desc = "L3 Prefetch events", .pmg_event_ids = power7_group_event_ids[178], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xdddf0002acaeac82ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 179 ] = { .pmg_name = "pm_l3", .pmg_desc = "L3 events", .pmg_event_ids = power7_group_event_ids[179], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xffff000082828280ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 180 ] = { .pmg_name = "pm_streams1", .pmg_desc = "Streams", .pmg_event_ids = power7_group_event_ids[180], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0ddd00041eb4b4b6ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 181 ] = { .pmg_name = "pm_streams2", .pmg_desc = "Streams", .pmg_event_ids = power7_group_event_ids[181], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0ddd00041ebcbcbeULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 182 ] = { .pmg_name = "pm_streams3", .pmg_desc = "Streams", .pmg_event_ids = power7_group_event_ids[182], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xdddd0004b0a8a8aaULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 183 ] = { .pmg_name = "pm_larx", .pmg_desc = "LARX", .pmg_event_ids = power7_group_event_ids[183], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xcc0c000194961e94ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 184 ] = { .pmg_name = "pm_ldf", .pmg_desc = "Floating Point loads", .pmg_event_ids = power7_group_event_ids[184], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0ccc00041e848486ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 185 ] = { .pmg_name = "pm_ldx", .pmg_desc = "Vector Load", .pmg_event_ids = power7_group_event_ids[185], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0ccc00041e88888aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 186 ] = { .pmg_name = "pm_l2_ld_st", .pmg_desc = "L2 load and store events", .pmg_event_ids = power7_group_event_ids[186], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x66f000008082801eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 187 ] = { .pmg_name = "pm_stcx", .pmg_desc = "STCX", .pmg_event_ids = power7_group_event_ids[187], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xcccc000c94ac989aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 188 ] = { .pmg_name = "pm_btac", .pmg_desc = "BTAC", .pmg_event_ids = power7_group_event_ids[188], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x55cc00008a88989aULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 189 ] = { .pmg_name = "pm_br_bc", .pmg_desc = "Branch BC events", .pmg_event_ids = power7_group_event_ids[189], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x44000000b8ba1e02ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 190 ] = { .pmg_name = "pm_inst_imc ", .pmg_desc = "inst imc events", .pmg_event_ids = power7_group_event_ids[190], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000f0f21602ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 191 ] = { .pmg_name = "pm_l2_misc1", .pmg_desc = "L2 load/store Miss events", .pmg_event_ids = power7_group_event_ids[191], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x6666000c80808280ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 192 ] = { .pmg_name = "pm_l2_misc2", .pmg_desc = "L2 Events", .pmg_event_ids = power7_group_event_ids[192], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00660000021e8080ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 193 ] = { .pmg_name = "pm_l2_misc3", .pmg_desc = "L2 Events", .pmg_event_ids = power7_group_event_ids[193], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00608000021e82faULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 194 ] = { .pmg_name = "pm_l2_misc4", .pmg_desc = "L2 Events", .pmg_event_ids = power7_group_event_ids[194], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00666000021e8282ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 195 ] = { .pmg_name = "pm_l2_misc5", .pmg_desc = "L2 Events", .pmg_event_ids = power7_group_event_ids[195], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00608000021e80faULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 196 ] = { .pmg_name = "pm_l2_misc6", .pmg_desc = "L2 Events", .pmg_event_ids = power7_group_event_ids[196], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0006600002f41e80ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 197 ] = { .pmg_name = "pm_ierat", .pmg_desc = "IERAT Events", .pmg_event_ids = power7_group_event_ids[197], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x04400000f6bcbe02ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 198 ] = { .pmg_name = "pm_disp_clb", .pmg_desc = "Dispatch CLB Events", .pmg_event_ids = power7_group_event_ids[198], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x2200000090a81e02ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 199 ] = { .pmg_name = "pm_dpu", .pmg_desc = "DPU Events", .pmg_event_ids = power7_group_event_ids[199], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000001e060802ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 200 ] = { .pmg_name = "pm_cpu_util", .pmg_desc = "Basic CPU utilization", .pmg_event_ids = power7_group_event_ids[200], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000008f41ef4ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 201 ] = { .pmg_name = "pm_overflow1", .pmg_desc = "Overflow events", .pmg_event_ids = power7_group_event_ids[201], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000010101010ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 202 ] = { .pmg_name = "pm_overflow2", .pmg_desc = "Overflow events", .pmg_event_ids = power7_group_event_ids[202], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000024102410ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 203 ] = { .pmg_name = "pm_rewind", .pmg_desc = "Rewind events", .pmg_event_ids = power7_group_event_ids[203], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000020f42002ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 204 ] = { .pmg_name = "pm_saved", .pmg_desc = "Saved Events", .pmg_event_ids = power7_group_event_ids[204], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000022f42202ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 205 ] = { .pmg_name = "pm_tlbie", .pmg_desc = "TLBIE Events", .pmg_event_ids = power7_group_event_ids[205], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x22d000008a96b202ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 206 ] = { .pmg_name = "pm_id_miss_erat_l1", .pmg_desc = "Instruction/Data miss from ERAT/L1 cache", .pmg_event_ids = power7_group_event_ids[206], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000f6fcf0f0ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 207 ] = { .pmg_name = "pm_id_miss_erat_tlab", .pmg_desc = "Instruction/Data miss from ERAT/TLB", .pmg_event_ids = power7_group_event_ids[207], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000001ef6fcfcULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 208 ] = { .pmg_name = "pm_compat_utilization1", .pmg_desc = "Basic CPU utilization", .pmg_event_ids = power7_group_event_ids[208], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000faf41ef4ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 209 ] = { .pmg_name = "pm_compat_utilization2", .pmg_desc = "CPI and utilization data", .pmg_event_ids = power7_group_event_ids[209], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000f4f41efaULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 210 ] = { .pmg_name = "pm_compat_cpi_1plus_ppc", .pmg_desc = "Misc CPI and utilization data", .pmg_event_ids = power7_group_event_ids[210], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000f2f4f2f2ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 211 ] = { .pmg_name = "pm_compat_l1_dcache_load_store_miss", .pmg_desc = "L1 D-Cache load/store miss", .pmg_event_ids = power7_group_event_ids[211], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000002f0f0f0ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 212 ] = { .pmg_name = "pm_compat_l1_cache_load", .pmg_desc = "L1 Cache loads", .pmg_event_ids = power7_group_event_ids[212], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000002fef6f0ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 213 ] = { .pmg_name = "pm_compat_instruction_directory", .pmg_desc = "Instruction Directory", .pmg_event_ids = power7_group_event_ids[213], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000f6fc02fcULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 214 ] = { .pmg_name = "pm_compat_suspend", .pmg_desc = "Suspend Events", .pmg_event_ids = power7_group_event_ids[214], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000000000000ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 215 ] = { .pmg_name = "pm_compat_misc_events1", .pmg_desc = "Misc Events", .pmg_event_ids = power7_group_event_ids[215], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000002f8f81eULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 216 ] = { .pmg_name = "pm_compat_misc_events2", .pmg_desc = "Misc Events", .pmg_event_ids = power7_group_event_ids[216], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000f0f2f4f8ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 217 ] = { .pmg_name = "pm_compat_misc_events3", .pmg_desc = "Misc Events", .pmg_event_ids = power7_group_event_ids[217], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00000000f8f21ef6ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 218 ] = { .pmg_name = "pm_mrk_br", .pmg_desc = "Marked Branch events", .pmg_event_ids = power7_group_event_ids[218], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000036363602ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 219 ] = { .pmg_name = "pm_mrk_dsource1", .pmg_desc = "Marked data sources", .pmg_event_ids = power7_group_event_ids[219], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xddd000004e424402ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 220 ] = { .pmg_name = "pm_mrk_dsource2", .pmg_desc = "Marked data sources", .pmg_event_ids = power7_group_event_ids[220], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xd00d000040200248ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 221 ] = { .pmg_name = "pm_mrk_dsource3", .pmg_desc = "Marked data sources", .pmg_event_ids = power7_group_event_ids[221], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xd0dd000044024642ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 222 ] = { .pmg_name = "pm_mrk_dsource4", .pmg_desc = "Marked data sources", .pmg_event_ids = power7_group_event_ids[222], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xddd0000042444202ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 223 ] = { .pmg_name = "pm_mrk_dsource5", .pmg_desc = "Marked data sources", .pmg_event_ids = power7_group_event_ids[223], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xd0d0000040244e02ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 224 ] = { .pmg_name = "pm_mrk_dsource6", .pmg_desc = "Marked data sources", .pmg_event_ids = power7_group_event_ids[224], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xdd00000048480220ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 225 ] = { .pmg_name = "pm_mrk_dsource7", .pmg_desc = "Marked data sources", .pmg_event_ids = power7_group_event_ids[225], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xd000000044260226ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 226 ] = { .pmg_name = "pm_mrk_dsource8", .pmg_desc = "Marked data sources", .pmg_event_ids = power7_group_event_ids[226], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xd000000042280228ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 227 ] = { .pmg_name = "pm_mrk_dsource9", .pmg_desc = "Marked data sources", .pmg_event_ids = power7_group_event_ids[227], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00d00000022a4c2aULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 228 ] = { .pmg_name = "pm_mrk_dsource10", .pmg_desc = "Marked data sources", .pmg_event_ids = power7_group_event_ids[228], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00d00000022c422cULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 229 ] = { .pmg_name = "pm_mrk_dsource11", .pmg_desc = "Marked data sources", .pmg_event_ids = power7_group_event_ids[229], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000003f2e0224ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 230 ] = { .pmg_name = "pm_mrk_lsu_flush1", .pmg_desc = "Marked LSU Flush", .pmg_event_ids = power7_group_event_ids[230], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xdd0000008486021eULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 231 ] = { .pmg_name = "pm_mrk_lsu_flush2", .pmg_desc = "Marked LSU Flush", .pmg_event_ids = power7_group_event_ids[231], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00dd0000021e888aULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 232 ] = { .pmg_name = "pm_mrk_rejects", .pmg_desc = "Marked rejects", .pmg_event_ids = power7_group_event_ids[232], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xdd000000828c0264ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 233 ] = { .pmg_name = "pm_mrk_inst", .pmg_desc = "Marked instruction events", .pmg_event_ids = power7_group_event_ids[233], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000032303002ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 234 ] = { .pmg_name = "pm_mrk_st", .pmg_desc = "Marked stores events", .pmg_event_ids = power7_group_event_ids[234], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000034343402ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 235 ] = { .pmg_name = "pm_mrk_dtlb_miss1", .pmg_desc = "Marked Data TLB Miss", .pmg_event_ids = power7_group_event_ids[235], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0ddd0000025e5e5eULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 236 ] = { .pmg_name = "pm_mrk_dtlb_miss2", .pmg_desc = "Marked Data TLB Miss", .pmg_event_ids = power7_group_event_ids[236], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xddd000005e5e5e02ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 237 ] = { .pmg_name = "pm_mrk_derat_miss1", .pmg_desc = "Marked DERAT Miss events", .pmg_event_ids = power7_group_event_ids[237], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0ddd0000025c5c5cULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 238 ] = { .pmg_name = "pm_mrk_derat_miss2", .pmg_desc = "Marked DERAT Miss events", .pmg_event_ids = power7_group_event_ids[238], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xddd000005c5c5c02ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 239 ] = { .pmg_name = "pm_mrk_misc_miss", .pmg_desc = "marked Miss Events", .pmg_event_ids = power7_group_event_ids[239], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00d000003e025a3eULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 240 ] = { .pmg_name = "pm_mrk_pteg1", .pmg_desc = "Marked PTEG", .pmg_event_ids = power7_group_event_ids[240], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0ddd000002525656ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 241 ] = { .pmg_name = "pm_mrk_pteg2", .pmg_desc = "Marked PTEG", .pmg_event_ids = power7_group_event_ids[241], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xddd0000050545202ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 242 ] = { .pmg_name = "pm_mrk_pteg3", .pmg_desc = "Marked PTEG", .pmg_event_ids = power7_group_event_ids[242], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0ddd000002565654ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 243 ] = { .pmg_name = "pm_mrk_pteg4", .pmg_desc = "Marked PTEG", .pmg_event_ids = power7_group_event_ids[243], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xdd0d000054500258ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 244 ] = { .pmg_name = "pm_mrk_pteg5", .pmg_desc = "Marked PTEG", .pmg_event_ids = power7_group_event_ids[244], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xdd0d000052580252ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 245 ] = { .pmg_name = "pm_mrk_misc1", .pmg_desc = "Marked misc events", .pmg_event_ids = power7_group_event_ids[245], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xd00000008e023a34ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 246 ] = { .pmg_name = "pm_mrk_misc2", .pmg_desc = "Marked misc events", .pmg_event_ids = power7_group_event_ids[246], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000002383a32ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 247 ] = { .pmg_name = "pm_mrk_misc3", .pmg_desc = "Marked misc events", .pmg_event_ids = power7_group_event_ids[247], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00d00000023a8032ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 248 ] = { .pmg_name = "pm_mrk_misc4", .pmg_desc = "Marked misc events", .pmg_event_ids = power7_group_event_ids[248], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000003c023238ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 249 ] = { .pmg_name = "pm_mrk_misc5", .pmg_desc = "Marked misc events", .pmg_event_ids = power7_group_event_ids[249], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000003d323f02ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 250 ] = { .pmg_name = "pm_mrk_misc6", .pmg_desc = "Marked misc events", .pmg_event_ids = power7_group_event_ids[250], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x0000000030f40230ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 251 ] = { .pmg_name = "pm_mrk_misc7", .pmg_desc = "Marked misc events", .pmg_event_ids = power7_group_event_ids[251], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xd000000082026464ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 252 ] = { .pmg_name = "pm_mrk_misc8", .pmg_desc = "Marked misc events", .pmg_event_ids = power7_group_event_ids[252], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000000001e1e0232ULL, .pmg_mmcra = 0x0000000000000001ULL }, [ 253 ] = { .pmg_name = "pm_vsu15", .pmg_desc = "FP ops", .pmg_event_ids = power7_group_event_ids[253], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0xaaaa000f809ca098ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 254 ] = { .pmg_name = "pm_l1_dcache_accesses", .pmg_desc = "L1 D-Cache accesses", .pmg_event_ids = power7_group_event_ids[254], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x000c000102f0f080ULL, .pmg_mmcra = 0x0000000000000000ULL }, [ 255 ] = { .pmg_name = "pm_loads_and_stores", .pmg_desc = "Load and Store instructions", .pmg_event_ids = power7_group_event_ids[255], .pmg_mmcr0 = 0x0000000000000000ULL, .pmg_mmcr1 = 0x00c0000202f080f0ULL, .pmg_mmcra = 0x0000000000000000ULL } }; #endif papi-5.5.1/src/libpfm-3.y/lib/powerpc_reg.h0000644000307100002310000000647113013651450020365 0ustar yarkhangraduate/* * These definitions were taken from the reg.h file which, until Linux * 2.6.18, resided in /usr/include/asm-ppc64. Most of the unneeded * definitions have been removed, but there are still a few in this file * that are currently unused by libpfm. */ #ifndef _POWER_REG_H #define _POWER_REG_H #define __stringify_1(x) #x #define __stringify(x) __stringify_1(x) #define mfspr(rn) ({unsigned long rval; \ asm volatile("mfspr %0," __stringify(rn) \ : "=r" (rval)); rval;}) /* Special Purpose Registers (SPRNs)*/ #define SPRN_PVR 0x11F /* Processor Version Register */ /* Performance monitor SPRs */ #define SPRN_MMCR0 795 #define MMCR0_FC 0x80000000UL /* freeze counters */ #define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */ #define MMCR0_KERNEL_DISABLE MMCR0_FCS #define MMCR0_FCP 0x20000000UL /* freeze in problem state */ #define MMCR0_PROBLEM_DISABLE MMCR0_FCP #define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */ #define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */ #define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */ #define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */ #define MMCR0_TBEE 0x00400000UL /* time base exception enable */ #define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/ #define MMCR0_PMCjCE 0x00004000UL /* PMCj count enable*/ #define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */ #define MMCR0_PMAO 0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */ #define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads */ #define MMCR0_FC1_4 0x00000020UL /* freeze counters 1 - 4 on POWER5/5+ */ #define MMCR0_FC5_6 0x00000010UL /* freeze counters 5 & 6 on POWER5/5+ */ #define MMCR0_FCTI 0x00000008UL /* freeze counters in tags inactive mode */ #define MMCR0_FCTA 0x00000004UL /* freeze counters in tags active mode */ #define MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */ #define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */ #define SPRN_MMCR1 798 #define SPRN_MMCRA 0x312 #define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */ #define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */ #define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */ #define SPRN_PMC1 787 #define SPRN_PMC2 788 #define SPRN_PMC3 789 #define SPRN_PMC4 790 #define SPRN_PMC5 791 #define SPRN_PMC6 792 #define SPRN_PMC7 793 #define SPRN_PMC8 794 #define SPRN_SIAR 780 #define SPRN_SDAR 781 /* Processor Version Register (PVR) field extraction */ #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ #define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ #define __is_processor(pv) (PVR_VER(mfspr(SPRN_PVR)) == (pv)) /* 64-bit processors */ /* XXX the prefix should be PVR_, we'll do a global sweep to fix it one day */ #define PV_NORTHSTAR 0x0033 #define PV_PULSAR 0x0034 #define PV_POWER4 0x0035 #define PV_ICESTAR 0x0036 #define PV_SSTAR 0x0037 #define PV_POWER4p 0x0038 #define PV_970 0x0039 #define PV_POWER5 0x003A #define PV_POWER5p 0x003B #define PV_970FX 0x003C #define PV_POWER6 0x003E #define PV_POWER7 0x003F #define PV_630 0x0040 #define PV_630p 0x0041 #define PV_970MP 0x0044 #define PV_970GX 0x0045 #define PV_BE 0x0070 #endif /* _POWER_REG_H */ papi-5.5.1/src/libpfm-3.y/lib/pfmlib_montecito.c0000644000307100002310000021173213013651450021374 0ustar yarkhangraduate/* * pfmlib_montecito.c : support for the Dual-Core Itanium2 processor * * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include /* public headers */ #include /* private headers */ #include "pfmlib_priv.h" /* library private */ #include "pfmlib_priv_ia64.h" /* architecture private */ #include "pfmlib_montecito_priv.h" /* PMU private */ #include "montecito_events.h" /* PMU private */ #define is_ear(i) event_is_ear(montecito_pe+(i)) #define is_ear_tlb(i) event_is_ear_tlb(montecito_pe+(i)) #define is_ear_alat(i) event_is_ear_alat(montecito_pe+(i)) #define is_ear_cache(i) event_is_ear_cache(montecito_pe+(i)) #define is_iear(i) event_is_iear(montecito_pe+(i)) #define is_dear(i) event_is_dear(montecito_pe+(i)) #define is_etb(i) event_is_etb(montecito_pe+(i)) #define has_opcm(i) event_opcm_ok(montecito_pe+(i)) #define has_iarr(i) event_iarr_ok(montecito_pe+(i)) #define has_darr(i) event_darr_ok(montecito_pe+(i)) #define has_all(i) event_all_ok(montecito_pe+(i)) #define has_mesi(i) event_mesi_ok(montecito_pe+(i)) #define evt_use_opcm(e) ((e)->pfp_mont_opcm1.opcm_used != 0 || (e)->pfp_mont_opcm2.opcm_used !=0) #define evt_use_irange(e) ((e)->pfp_mont_irange.rr_used) #define evt_use_drange(e) ((e)->pfp_mont_drange.rr_used) #define evt_grp(e) (int)montecito_pe[e].pme_qualifiers.pme_qual.pme_group #define evt_set(e) (int)montecito_pe[e].pme_qualifiers.pme_qual.pme_set #define evt_umask(e) montecito_pe[e].pme_umask #define evt_type(e) (int)montecito_pe[e].pme_type #define evt_caf(e) (int)montecito_pe[e].pme_caf #define FINE_MODE_BOUNDARY_BITS 16 #define FINE_MODE_MASK ~((1U< PMC0 * 1 -> PMC1 * n -> PMCn * * The following are in the model specific rr_br[]: * IBR0 -> 0 * IBR1 -> 1 * ... * IBR7 -> 7 * DBR0 -> 0 * DBR1 -> 1 * ... * DBR7 -> 7 * * We do not use a mapping table, instead we make up the * values on the fly given the base. */ static int pfm_mont_detect(void) { int tmp; int ret = PFMLIB_ERR_NOTSUPP; tmp = pfm_ia64_get_cpu_family(); if (tmp == 0x20) { ret = PFMLIB_SUCCESS; } return ret; } /* * Check the event for incompatibilities. This is useful * for L1D and L2D related events. Due to wire limitations, * some caches events are separated into sets. There * are 6 sets for the L1D cache group and 8 sets for L2D group. * It is NOT possible to simultaneously measure events from * differents sets for L1D. For instance, you cannot * measure events from set0 and set1 in L1D cache group. The L2D * group allows up to two different sets to be active at the same * time. The first set is selected by the event in PMC4 and the second * set by the event in PMC6. Once the set is selected for PMC4, * the same set is locked for PMC5 and PMC8. Similarly, once the * set is selected for PMC6, the same set is locked for PMC7 and * PMC9. * * This function verifies that only one set of L1D is selected * and that no more than 2 sets are selected for L2D */ static int check_cross_groups(pfmlib_input_param_t *inp, unsigned int *l1d_event, unsigned long *l2d_set1_mask, unsigned long *l2d_set2_mask) { int g, s, s1, s2; unsigned int cnt = inp->pfp_event_count; pfmlib_event_t *e = inp->pfp_events; unsigned int i, j; unsigned long l2d_mask1 = 0, l2d_mask2 = 0; unsigned int l1d_event_idx = UNEXISTING_SET; /* * Let check the L1D constraint first * * There is no umask restriction for this group */ for (i=0; i < cnt; i++) { g = evt_grp(e[i].event); s = evt_set(e[i].event); if (g != PFMLIB_MONT_EVT_L1D_CACHE_GRP) continue; DPRINT("i=%u g=%d s=%d\n", i, g, s); l1d_event_idx = i; for (j=i+1; j < cnt; j++) { if (evt_grp(e[j].event) != g) continue; /* * if there is another event from the same group * but with a different set, then we return an error */ if (evt_set(e[j].event) != s) return PFMLIB_ERR_EVTSET; } } /* * Check that we have only up to two distinct * sets for L2D */ s1 = s2 = -1; for (i=0; i < cnt; i++) { g = evt_grp(e[i].event); if (g != PFMLIB_MONT_EVT_L2D_CACHE_GRP) continue; s = evt_set(e[i].event); /* * we have seen this set before, continue */ if (s1 == s) { l2d_mask1 |= 1UL << i; continue; } if (s2 == s) { l2d_mask2 |= 1UL << i; continue; } /* * record first of second set seen */ if (s1 == -1) { s1 = s; l2d_mask1 |= 1UL << i; } else if (s2 == -1) { s2 = s; l2d_mask2 |= 1UL << i; } else { /* * found a third set, that's not possible */ return PFMLIB_ERR_EVTSET; } } *l1d_event = l1d_event_idx; *l2d_set1_mask = l2d_mask1; *l2d_set2_mask = l2d_mask2; return PFMLIB_SUCCESS; } /* * Certain prefetch events must be treated specially when instruction range restriction * is used because they can only be constrained by IBRP1 in fine-mode. Other events * will use IBRP0 if tagged as a demand fetch OR IBPR1 if tagged as a prefetch match. * * Events which can be qualified by the two pairs depending on their tag: * - ISB_BUNPAIRS_IN * - L1I_FETCH_RAB_HIT * - L1I_FETCH_ISB_HIT * - L1I_FILLS * * This function returns the number of qualifying prefetch events found */ static int prefetch_events[]={ PME_MONT_L1I_PREFETCHES, PME_MONT_L1I_STRM_PREFETCHES, PME_MONT_L2I_PREFETCHES }; #define NPREFETCH_EVENTS sizeof(prefetch_events)/sizeof(int) static int prefetch_dual_events[]= { PME_MONT_ISB_BUNPAIRS_IN, PME_MONT_L1I_FETCH_RAB_HIT, PME_MONT_L1I_FETCH_ISB_HIT, PME_MONT_L1I_FILLS }; #define NPREFETCH_DUAL_EVENTS sizeof(prefetch_dual_events)/sizeof(int) /* * prefetch events must use IBRP1, unless they are dual and the user specified * PFMLIB_MONT_IRR_DEMAND_FETCH in rr_flags */ static int check_prefetch_events(pfmlib_input_param_t *inp, pfmlib_mont_input_rr_t *irr, unsigned int *count, int *base_idx, int *dup) { int code; int prefetch_codes[NPREFETCH_EVENTS]; int prefetch_dual_codes[NPREFETCH_DUAL_EVENTS]; unsigned int i, j; int c, flags; int found = 0, found_ibrp0 = 0, found_ibrp1 = 0; flags = irr->rr_flags & (PFMLIB_MONT_IRR_DEMAND_FETCH|PFMLIB_MONT_IRR_PREFETCH_MATCH); for(i=0; i < NPREFETCH_EVENTS; i++) { pfm_get_event_code(prefetch_events[i], &code); prefetch_codes[i] = code; } for(i=0; i < NPREFETCH_DUAL_EVENTS; i++) { pfm_get_event_code(prefetch_dual_events[i], &code); prefetch_dual_codes[i] = code; } for(i=0; i < inp->pfp_event_count; i++) { pfm_get_event_code(inp->pfp_events[i].event, &c); for(j=0; j < NPREFETCH_EVENTS; j++) { if (c == prefetch_codes[j]) { found++; found_ibrp1++; } } /* * for the dual events, users must specify one or both of the * PFMLIB_MONT_IRR_DEMAND_FETCH or PFMLIB_MONT_IRR_PREFETCH_MATCH */ for(j=0; j < NPREFETCH_DUAL_EVENTS; j++) { if (c == prefetch_dual_codes[j]) { found++; if (flags == 0) return PFMLIB_ERR_IRRFLAGS; if (flags & PFMLIB_MONT_IRR_DEMAND_FETCH) found_ibrp0++; if (flags & PFMLIB_MONT_IRR_PREFETCH_MATCH) found_ibrp1++; } } } *count = found; *dup = 0; /* * if both found_ibrp0 and found_ibrp1 > 0, then we need to duplicate * the range in ibrp0 to ibrp1. */ if (found) { *base_idx = found_ibrp0 ? 0 : 2; if (found_ibrp1 && found_ibrp0) *dup = 1; } return 0; } /* * look for CPU_OP_CYCLES_QUAL * Return: * 1 if found * 0 otherwise */ static int has_cpu_cycles_qual(pfmlib_input_param_t *inp) { unsigned int i; int code, c; pfm_get_event_code(PME_MONT_CPU_OP_CYCLES_QUAL, &code); for(i=0; i < inp->pfp_event_count; i++) { pfm_get_event_code(inp->pfp_events[i].event, &c); if (c == code) return 1; } return 0; } /* * IA64_INST_RETIRED (and subevents) is the only event which can be measured on all * 4 IBR when non-fine mode is not possible. * * This function returns: * - the number of events match the IA64_INST_RETIRED code * - in retired_mask to bottom 4 bits indicates which of the 4 INST_RETIRED event * is present */ static unsigned int check_inst_retired_events(pfmlib_input_param_t *inp, unsigned long *retired_mask) { int code; int c; unsigned int i, count, found = 0; unsigned long umask, mask; pfm_get_event_code(PME_MONT_IA64_INST_RETIRED, &code); count = inp->pfp_event_count; mask = 0; for(i=0; i < count; i++) { pfm_get_event_code(inp->pfp_events[i].event, &c); if (c == code) { pfm_mont_get_event_umask(inp->pfp_events[i].event, &umask); switch(umask) { case 0: mask |= 1; break; case 1: mask |= 2; break; case 2: mask |= 4; break; case 3: mask |= 8; break; } found++; } } if (retired_mask) *retired_mask = mask; return found; } static int check_fine_mode_possible(pfmlib_mont_input_rr_t *rr, int n) { pfmlib_mont_input_rr_desc_t *lim = rr->rr_limits; int i; for(i=0; i < n; i++) { if ((lim[i].rr_start & FINE_MODE_MASK) != (lim[i].rr_end & FINE_MODE_MASK)) return 0; } return 1; } /* * mode = 0 -> check code (enforce bundle alignment) * mode = 1 -> check data */ static int check_intervals(pfmlib_mont_input_rr_t *irr, int mode, unsigned int *n_intervals) { unsigned int i; pfmlib_mont_input_rr_desc_t *lim = irr->rr_limits; for(i=0; i < 4; i++) { /* end marker */ if (lim[i].rr_start == 0 && lim[i].rr_end == 0) break; /* invalid entry */ if (lim[i].rr_start >= lim[i].rr_end) return PFMLIB_ERR_IRRINVAL; if (mode == 0 && (lim[i].rr_start & 0xf || lim[i].rr_end & 0xf)) return PFMLIB_ERR_IRRALIGN; } *n_intervals = i; return PFMLIB_SUCCESS; } /* * It is not possible to measure more than one of the * L2D_OZQ_CANCELS0, L2D_OZQ_CANCELS1 at the same time. */ static int cancel_events[]= { PME_MONT_L2D_OZQ_CANCELS0_ACQ, PME_MONT_L2D_OZQ_CANCELS1_ANY }; #define NCANCEL_EVENTS sizeof(cancel_events)/sizeof(int) static int check_cancel_events(pfmlib_input_param_t *inp) { unsigned int i, j, count; int code; int cancel_codes[NCANCEL_EVENTS]; int idx = -1; for(i=0; i < NCANCEL_EVENTS; i++) { pfm_get_event_code(cancel_events[i], &code); cancel_codes[i] = code; } count = inp->pfp_event_count; for(i=0; i < count; i++) { for (j=0; j < NCANCEL_EVENTS; j++) { pfm_get_event_code(inp->pfp_events[i].event, &code); if (code == cancel_codes[j]) { if (idx != -1) { return PFMLIB_ERR_INVAL; } idx = inp->pfp_events[i].event; } } } return PFMLIB_SUCCESS; } /* * Automatically dispatch events to corresponding counters following constraints. */ static unsigned int l2d_set1_cnts[]={ 4, 5, 8 }; static unsigned int l2d_set2_cnts[]={ 6, 7, 9 }; static int pfm_mont_dispatch_counters(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfmlib_mont_input_param_t *param = mod_in; pfm_mont_pmc_reg_t reg; pfmlib_event_t *e; pfmlib_reg_t *pc, *pd; pfmlib_regmask_t avail_cntrs, impl_cntrs; unsigned int i,j, k, max_cnt; unsigned int assign[PMU_MONT_NUM_COUNTERS]; unsigned int m, cnt; unsigned int l1d_set; unsigned long l2d_set1_mask, l2d_set2_mask, evt_mask, mesi; unsigned long not_assigned_events, cnt_mask; int l2d_set1_p, l2d_set2_p; int ret; e = inp->pfp_events; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; cnt = inp->pfp_event_count; if (PFMLIB_DEBUG()) for (m=0; m < cnt; m++) { DPRINT("ev[%d]=%s counters=0x%lx\n", m, montecito_pe[e[m].event].pme_name, montecito_pe[e[m].event].pme_counters); } if (cnt > PMU_MONT_NUM_COUNTERS) return PFMLIB_ERR_TOOMANY; l1d_set = UNEXISTING_SET; ret = check_cross_groups(inp, &l1d_set, &l2d_set1_mask, &l2d_set2_mask); if (ret != PFMLIB_SUCCESS) return ret; ret = check_cancel_events(inp); if (ret != PFMLIB_SUCCESS) return ret; /* * at this point, we know that: * - we have at most 1 L1D set * - we have at most 2 L2D sets * - cancel events are compatible */ DPRINT("l1d_set=%u l2d_set1_mask=0x%lx l2d_set2_mask=0x%lx\n", l1d_set, l2d_set1_mask, l2d_set2_mask); /* * first, place L1D cache event in PMC5 * * this is the strongest constraint */ pfm_get_impl_counters(&impl_cntrs); pfm_regmask_andnot(&avail_cntrs, &impl_cntrs, &inp->pfp_unavail_pmcs); not_assigned_events = 0; DPRINT("avail_cntrs=0x%lx\n", avail_cntrs.bits[0]); /* * we do not check ALL_THRD here because at least * one event has to be in PMC5 for this group */ if (l1d_set != UNEXISTING_SET) { if (!pfm_regmask_isset(&avail_cntrs, 5)) return PFMLIB_ERR_NOASSIGN; assign[l1d_set] = 5; pfm_regmask_clr(&avail_cntrs, 5); } l2d_set1_p = l2d_set2_p = 0; /* * assign L2D set1 and set2 counters */ for (i=0; i < cnt ; i++) { evt_mask = 1UL << i; /* * place l2d set1 events. First 3 go to designated * counters, the rest is placed elsewhere in the final * pass */ if (l2d_set1_p < 3 && (l2d_set1_mask & evt_mask)) { assign[i] = l2d_set1_cnts[l2d_set1_p]; if (!pfm_regmask_isset(&avail_cntrs, assign[i])) return PFMLIB_ERR_NOASSIGN; pfm_regmask_clr(&avail_cntrs, assign[i]); l2d_set1_p++; continue; } /* * same as above but for l2d set2 */ if (l2d_set2_p < 3 && (l2d_set2_mask & evt_mask)) { assign[i] = l2d_set2_cnts[l2d_set2_p]; if (!pfm_regmask_isset(&avail_cntrs, assign[i])) return PFMLIB_ERR_NOASSIGN; pfm_regmask_clr(&avail_cntrs, assign[i]); l2d_set2_p++; continue; } /* * if not l2d nor l1d, then defer placement until final pass */ if (i != l1d_set) not_assigned_events |= evt_mask; DPRINT("phase 1: i=%u avail_cntrs=0x%lx l2d_set1_p=%d l2d_set2_p=%d not_assigned=0x%lx\n", i, avail_cntrs.bits[0], l2d_set1_p, l2d_set2_p, not_assigned_events); } /* * assign BUS_* ER_* events (work only in PMC4-PMC9) */ evt_mask = not_assigned_events; for (i=0; evt_mask ; i++, evt_mask >>=1) { if ((evt_mask & 0x1) == 0) continue; cnt_mask = montecito_pe[e[i].event].pme_counters; /* * only interested in events with restricted set of counters */ if (cnt_mask == 0xfff0) continue; for(j=0; cnt_mask; j++, cnt_mask >>=1) { if ((cnt_mask & 0x1) == 0) continue; DPRINT("phase 2: i=%d j=%d cnt_mask=0x%lx avail_cntrs=0x%lx not_assigned_evnts=0x%lx\n", i, j, cnt_mask, avail_cntrs.bits[0], not_assigned_events); if (!pfm_regmask_isset(&avail_cntrs, j)) continue; assign[i] = j; not_assigned_events &= ~(1UL << i); pfm_regmask_clr(&avail_cntrs, j); break; } if (cnt_mask == 0) return PFMLIB_ERR_NOASSIGN; } /* * assign the rest of the events (no constraints) */ evt_mask = not_assigned_events; max_cnt = PMU_MONT_FIRST_COUNTER + PMU_MONT_NUM_COUNTERS; for (i=0, j=0; evt_mask ; i++, evt_mask >>=1) { DPRINT("phase 3a: i=%d j=%d evt_mask=0x%lx avail_cntrs=0x%lx not_assigned_evnts=0x%lx\n", i, j, evt_mask, avail_cntrs.bits[0], not_assigned_events); if ((evt_mask & 0x1) == 0) continue; while(j < max_cnt && !pfm_regmask_isset(&avail_cntrs, j)) { DPRINT("phase 3: i=%d j=%d evt_mask=0x%lx avail_cntrs=0x%lx not_assigned_evnts=0x%lx\n", i, j, evt_mask, avail_cntrs.bits[0], not_assigned_events); j++; } if (j == max_cnt) return PFMLIB_ERR_NOASSIGN; assign[i] = j; j++; } for (j=0; j < cnt ; j++ ) { mesi = 0; /* * XXX: we do not support .all placement just yet */ if (param && param->pfp_mont_counters[j].flags & PFMLIB_MONT_FL_EVT_ALL_THRD) { DPRINT(".all mode is not yet supported by libpfm\n"); return PFMLIB_ERR_NOTSUPP; } if (has_mesi(e[j].event)) { for(k=0;k< e[j].num_masks; k++) { mesi |= 1UL << e[j].unit_masks[k]; } /* by default we capture everything */ if (mesi == 0) mesi = 0xf; } reg.pmc_val = 0; /* clear all, bits 26-27 must be zero for proper operations */ /* if plm is 0, then assume not specified per-event and use default */ reg.pmc_plm = inp->pfp_events[j].plm ? inp->pfp_events[j].plm : inp->pfp_dfl_plm; reg.pmc_oi = 0; /* let the user/OS deal with this field */ reg.pmc_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc_thres = param ? param->pfp_mont_counters[j].thres: 0; reg.pmc_ism = 0x2; /* force IA-64 mode */ reg.pmc_umask = is_ear(e[j].event) ? 0x0 : montecito_pe[e[j].event].pme_umask; reg.pmc_es = montecito_pe[e[j].event].pme_code; reg.pmc_all = 0; /* XXX force self for now */ reg.pmc_m = (mesi>>3) & 0x1; reg.pmc_e = (mesi>>2) & 0x1; reg.pmc_s = (mesi>>1) & 0x1; reg.pmc_i = mesi & 0x1; /* * Note that we don't force PMC4.pmc_ena = 1 because the kernel takes care of this for us. * This way we don't have to program something in PMC4 even when we don't use it */ pc[j].reg_num = assign[j]; pc[j].reg_value = reg.pmc_val; pc[j].reg_addr = pc[j].reg_alt_addr = assign[j]; pd[j].reg_num = assign[j]; pd[j].reg_addr = pd[j].reg_alt_addr = assign[j]; __pfm_vbprintf("[PMC%u(pmc%u)=0x%06lx m=%d e=%d s=%d i=%d thres=%d all=%d es=0x%02x plm=%d umask=0x%x pm=%d ism=0x%x oi=%d] %s\n", assign[j], assign[j], reg.pmc_val, reg.pmc_m, reg.pmc_e, reg.pmc_s, reg.pmc_i, reg.pmc_thres, reg.pmc_all, reg.pmc_es,reg.pmc_plm, reg.pmc_umask, reg.pmc_pm, reg.pmc_ism, reg.pmc_oi, montecito_pe[e[j].event].pme_name); __pfm_vbprintf("[PMD%u(pmd%u)]\n", pd[j].reg_num, pd[j].reg_num); } /* number of PMC registers programmed */ outp->pfp_pmc_count = cnt; outp->pfp_pmd_count = cnt; return PFMLIB_SUCCESS; } static int pfm_dispatch_iear(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfm_mont_pmc_reg_t reg; pfmlib_mont_input_param_t *param = mod_in; pfmlib_reg_t *pc, *pd; pfmlib_mont_input_param_t fake_param; unsigned int pos1, pos2; unsigned int i, count; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; pos1 = outp->pfp_pmc_count; pos2 = outp->pfp_pmd_count; count = inp->pfp_event_count; for (i=0; i < count; i++) { if (is_iear(inp->pfp_events[i].event)) break; } if (param == NULL || param->pfp_mont_iear.ear_used == 0) { /* * case 3: no I-EAR event, no (or nothing) in param->pfp_mont_iear.ear_used */ if (i == count) return PFMLIB_SUCCESS; memset(&fake_param, 0, sizeof(fake_param)); param = &fake_param; /* * case 1: extract all information for event (name) */ pfm_mont_get_ear_mode(inp->pfp_events[i].event, ¶m->pfp_mont_iear.ear_mode); param->pfp_mont_iear.ear_umask = evt_umask(inp->pfp_events[i].event); DPRINT("I-EAR event with no info\n"); } /* * case 2: ear_used=1, event is defined, we use the param info as it is more precise * case 4: ear_used=1, no event (free running I-EAR), use param info */ reg.pmc_val = 0; if (param->pfp_mont_iear.ear_mode == PFMLIB_MONT_EAR_TLB_MODE) { /* if plm is 0, then assume not specified per-event and use default */ reg.pmc37_mont_tlb_reg.iear_plm = param->pfp_mont_iear.ear_plm ? param->pfp_mont_iear.ear_plm : inp->pfp_dfl_plm; reg.pmc37_mont_tlb_reg.iear_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc37_mont_tlb_reg.iear_ct = 0x0; reg.pmc37_mont_tlb_reg.iear_umask = param->pfp_mont_iear.ear_umask; } else if (param->pfp_mont_iear.ear_mode == PFMLIB_MONT_EAR_CACHE_MODE) { /* if plm is 0, then assume not specified per-event and use default */ reg.pmc37_mont_cache_reg.iear_plm = param->pfp_mont_iear.ear_plm ? param->pfp_mont_iear.ear_plm : inp->pfp_dfl_plm; reg.pmc37_mont_cache_reg.iear_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc37_mont_cache_reg.iear_ct = 0x1; reg.pmc37_mont_cache_reg.iear_umask = param->pfp_mont_iear.ear_umask; } else { DPRINT("ALAT mode not supported in I-EAR mode\n"); return PFMLIB_ERR_INVAL; } if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 37)) return PFMLIB_ERR_NOASSIGN; pc[pos1].reg_num = 37; /* PMC37 is I-EAR config register */ pc[pos1].reg_value = reg.pmc_val; pc[pos1].reg_addr = pc[pos1].reg_alt_addr = 37; pos1++; pd[pos2].reg_num = 34; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 34; pos2++; pd[pos2].reg_num = 35; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 35; pos2++; if (param->pfp_mont_iear.ear_mode == PFMLIB_MONT_EAR_TLB_MODE) { __pfm_vbprintf("[PMC37(pmc37)=0x%lx ctb=tlb plm=%d pm=%d umask=0x%x]\n", reg.pmc_val, reg.pmc37_mont_tlb_reg.iear_plm, reg.pmc37_mont_tlb_reg.iear_pm, reg.pmc37_mont_tlb_reg.iear_umask); } else { __pfm_vbprintf("[PMC37(pmc37)=0x%lx ctb=cache plm=%d pm=%d umask=0x%x]\n", reg.pmc_val, reg.pmc37_mont_cache_reg.iear_plm, reg.pmc37_mont_cache_reg.iear_pm, reg.pmc37_mont_cache_reg.iear_umask); } __pfm_vbprintf("[PMD34(pmd34)]\n[PMD35(pmd35)\n"); /* update final number of entries used */ outp->pfp_pmc_count = pos1; outp->pfp_pmd_count = pos2; return PFMLIB_SUCCESS; } static int pfm_dispatch_dear(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfm_mont_pmc_reg_t reg; pfmlib_mont_input_param_t *param = mod_in; pfmlib_reg_t *pc, *pd; pfmlib_mont_input_param_t fake_param; unsigned int pos1, pos2; unsigned int i, count; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; pos1 = outp->pfp_pmc_count; pos2 = outp->pfp_pmd_count; count = inp->pfp_event_count; for (i=0; i < count; i++) { if (is_dear(inp->pfp_events[i].event)) break; } if (param == NULL || param->pfp_mont_dear.ear_used == 0) { /* * case 3: no D-EAR event, no (or nothing) in param->pfp_mont_dear.ear_used */ if (i == count) return PFMLIB_SUCCESS; memset(&fake_param, 0, sizeof(fake_param)); param = &fake_param; /* * case 1: extract all information for event (name) */ pfm_mont_get_ear_mode(inp->pfp_events[i].event, ¶m->pfp_mont_dear.ear_mode); param->pfp_mont_dear.ear_umask = evt_umask(inp->pfp_events[i].event); DPRINT("D-EAR event with no info\n"); } /* sanity check on the mode */ if ( param->pfp_mont_dear.ear_mode != PFMLIB_MONT_EAR_CACHE_MODE && param->pfp_mont_dear.ear_mode != PFMLIB_MONT_EAR_TLB_MODE && param->pfp_mont_dear.ear_mode != PFMLIB_MONT_EAR_ALAT_MODE) return PFMLIB_ERR_INVAL; /* * case 2: ear_used=1, event is defined, we use the param info as it is more precise * case 4: ear_used=1, no event (free running D-EAR), use param info */ reg.pmc_val = 0; /* if plm is 0, then assume not specified per-event and use default */ reg.pmc40_mont_reg.dear_plm = param->pfp_mont_dear.ear_plm ? param->pfp_mont_dear.ear_plm : inp->pfp_dfl_plm; reg.pmc40_mont_reg.dear_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc40_mont_reg.dear_mode = param->pfp_mont_dear.ear_mode; reg.pmc40_mont_reg.dear_umask = param->pfp_mont_dear.ear_umask; reg.pmc40_mont_reg.dear_ism = 0x2; /* force IA-64 mode */ if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 40)) return PFMLIB_ERR_NOASSIGN; pc[pos1].reg_num = 40; /* PMC11 is D-EAR config register */ pc[pos1].reg_value = reg.pmc_val; pc[pos1].reg_addr = pc[pos1].reg_alt_addr = 40; pos1++; pd[pos2].reg_num = 32; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 32; pos2++; pd[pos2].reg_num = 33; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 33; pos2++; pd[pos2].reg_num = 36; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 36; pos2++; __pfm_vbprintf("[PMC40(pmc40)=0x%lx mode=%s plm=%d pm=%d ism=0x%x umask=0x%x]\n", reg.pmc_val, reg.pmc40_mont_reg.dear_mode == 0 ? "L1D" : (reg.pmc40_mont_reg.dear_mode == 1 ? "L1DTLB" : "ALAT"), reg.pmc40_mont_reg.dear_plm, reg.pmc40_mont_reg.dear_pm, reg.pmc40_mont_reg.dear_ism, reg.pmc40_mont_reg.dear_umask); __pfm_vbprintf("[PMD32(pmd32)]\n[PMD33(pmd33)\nPMD36(pmd36)\n"); /* update final number of entries used */ outp->pfp_pmc_count = pos1; outp->pfp_pmd_count = pos2; return PFMLIB_SUCCESS; } static int pfm_dispatch_opcm(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in, pfmlib_output_param_t *outp, pfmlib_mont_output_param_t *mod_out) { pfmlib_mont_input_param_t *param = mod_in; pfmlib_reg_t *pc = outp->pfp_pmcs; pfm_mont_pmc_reg_t reg1, reg2, pmc36; unsigned int i, has_1st_pair, has_2nd_pair, count; unsigned int pos = outp->pfp_pmc_count; int used_pmc32, used_pmc34; if (param == NULL) return PFMLIB_SUCCESS; #define PMC36_DFL_VAL 0xfffffff0 /* * mandatory default value for PMC36 as described in the documentation * all monitoring is opcode constrained. Better make sure the match/mask * is set to match everything! It looks weird for the default value! */ pmc36.pmc_val = PMC36_DFL_VAL; reg1.pmc_val = 0x030f01ffffffffff; reg2.pmc_val = 0; used_pmc32 = param->pfp_mont_opcm1.opcm_used; used_pmc34 = param->pfp_mont_opcm2.opcm_used; /* * check in any feature is used. * PMC36 must be setup when opcode matching is used OR when code range restriction is used */ if (used_pmc32 == 0 && used_pmc34 == 0 && param->pfp_mont_irange.rr_used == 0) return 0; /* * check for rr_nbr_used to make sure that the range request produced something on output */ if (used_pmc32 || (param->pfp_mont_irange.rr_used && mod_out->pfp_mont_irange.rr_nbr_used) ) { /* * if not used, ignore all bits */ if (used_pmc32) { reg1.pmc32_34_mont_reg.opcm_mask = param->pfp_mont_opcm1.opcm_mask; reg1.pmc32_34_mont_reg.opcm_b = param->pfp_mont_opcm1.opcm_b; reg1.pmc32_34_mont_reg.opcm_f = param->pfp_mont_opcm1.opcm_f; reg1.pmc32_34_mont_reg.opcm_i = param->pfp_mont_opcm1.opcm_i; reg1.pmc32_34_mont_reg.opcm_m = param->pfp_mont_opcm1.opcm_m; reg2.pmc33_35_mont_reg.opcm_match = param->pfp_mont_opcm1.opcm_match; } if (param->pfp_mont_irange.rr_used) { reg1.pmc32_34_mont_reg.opcm_ig_ad = 0; reg1.pmc32_34_mont_reg.opcm_inv = param->pfp_mont_irange.rr_flags & PFMLIB_MONT_RR_INV ? 1 : 0; } else { /* clear range restriction fields when none is used */ reg1.pmc32_34_mont_reg.opcm_ig_ad = 1; reg1.pmc32_34_mont_reg.opcm_inv = 0; } if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 32)) return PFMLIB_ERR_NOASSIGN; pc[pos].reg_num = 32; pc[pos].reg_value = reg1.pmc_val; pc[pos].reg_addr = pc[pos].reg_alt_addr = 32; pos++; /* * will be constrained by PMC32 */ if (used_pmc32) { if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 33)) return PFMLIB_ERR_NOASSIGN; /* * used pmc33 only when we have active opcode matching */ pc[pos].reg_num = 33; pc[pos].reg_value = reg2.pmc_val; pc[pos].reg_addr = pc[pos].reg_alt_addr = 33; pos++; has_1st_pair = has_2nd_pair = 0; count = inp->pfp_event_count; for(i=0; i < count; i++) { if (inp->pfp_events[i].event == PME_MONT_IA64_TAGGED_INST_RETIRED_IBRP0_PMC32_33) has_1st_pair=1; if (inp->pfp_events[i].event == PME_MONT_IA64_TAGGED_INST_RETIRED_IBRP2_PMC32_33) has_2nd_pair=1; } if (has_1st_pair || has_2nd_pair == 0) pmc36.pmc36_mont_reg.opcm_ch0_ig_opcm = 0; if (has_2nd_pair || has_1st_pair == 0) pmc36.pmc36_mont_reg.opcm_ch2_ig_opcm = 0; } __pfm_vbprintf("[PMC32(pmc32)=0x%lx m=%d i=%d f=%d b=%d mask=0x%lx inv=%d ig_ad=%d]\n", reg1.pmc_val, reg1.pmc32_34_mont_reg.opcm_m, reg1.pmc32_34_mont_reg.opcm_i, reg1.pmc32_34_mont_reg.opcm_f, reg1.pmc32_34_mont_reg.opcm_b, reg1.pmc32_34_mont_reg.opcm_mask, reg1.pmc32_34_mont_reg.opcm_inv, reg1.pmc32_34_mont_reg.opcm_ig_ad); if (used_pmc32) __pfm_vbprintf("[PMC33(pmc33)=0x%lx match=0x%lx]\n", reg2.pmc_val, reg2.pmc33_35_mont_reg.opcm_match); } /* * will be constrained by PMC34 */ if (used_pmc34) { reg1.pmc_val = 0x01ffffffffff; /* pmc34 default value */ reg2.pmc_val = 0; reg1.pmc32_34_mont_reg.opcm_mask = param->pfp_mont_opcm2.opcm_mask; reg1.pmc32_34_mont_reg.opcm_b = param->pfp_mont_opcm2.opcm_b; reg1.pmc32_34_mont_reg.opcm_f = param->pfp_mont_opcm2.opcm_f; reg1.pmc32_34_mont_reg.opcm_i = param->pfp_mont_opcm2.opcm_i; reg1.pmc32_34_mont_reg.opcm_m = param->pfp_mont_opcm2.opcm_m; reg2.pmc33_35_mont_reg.opcm_match = param->pfp_mont_opcm2.opcm_match; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 34)) return PFMLIB_ERR_NOASSIGN; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 35)) return PFMLIB_ERR_NOASSIGN; pc[pos].reg_num = 34; pc[pos].reg_value = reg1.pmc_val; pc[pos].reg_addr = pc[pos].reg_alt_addr = 34; pos++; pc[pos].reg_num = 35; pc[pos].reg_value = reg2.pmc_val; pc[pos].reg_addr = pc[pos].reg_alt_addr = 35; pos++; has_1st_pair = has_2nd_pair = 0; count = inp->pfp_event_count; for(i=0; i < count; i++) { if (inp->pfp_events[i].event == PME_MONT_IA64_TAGGED_INST_RETIRED_IBRP1_PMC34_35) has_1st_pair=1; if (inp->pfp_events[i].event == PME_MONT_IA64_TAGGED_INST_RETIRED_IBRP3_PMC34_35) has_2nd_pair=1; } if (has_1st_pair || has_2nd_pair == 0) pmc36.pmc36_mont_reg.opcm_ch1_ig_opcm = 0; if (has_2nd_pair || has_1st_pair == 0) pmc36.pmc36_mont_reg.opcm_ch3_ig_opcm = 0; __pfm_vbprintf("[PMC34(pmc34)=0x%lx m=%d i=%d f=%d b=%d mask=0x%lx]\n", reg1.pmc_val, reg1.pmc32_34_mont_reg.opcm_m, reg1.pmc32_34_mont_reg.opcm_i, reg1.pmc32_34_mont_reg.opcm_f, reg1.pmc32_34_mont_reg.opcm_b, reg1.pmc32_34_mont_reg.opcm_mask); __pfm_vbprintf("[PMC35(pmc35)=0x%lx match=0x%lx]\n", reg2.pmc_val, reg2.pmc33_35_mont_reg.opcm_match); } if (pmc36.pmc_val != PMC36_DFL_VAL) { if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 36)) return PFMLIB_ERR_NOASSIGN; pc[pos].reg_num = 36; pc[pos].reg_value = pmc36.pmc_val; pc[pos].reg_addr = pc[pos].reg_alt_addr = 36; pos++; __pfm_vbprintf("[PMC36(pmc36)=0x%lx ch0_ig_op=%d ch1_ig_op=%d ch2_ig_op=%d ch3_ig_op=%d]\n", pmc36.pmc_val, pmc36.pmc36_mont_reg.opcm_ch0_ig_opcm, pmc36.pmc36_mont_reg.opcm_ch1_ig_opcm, pmc36.pmc36_mont_reg.opcm_ch2_ig_opcm, pmc36.pmc36_mont_reg.opcm_ch3_ig_opcm); } outp->pfp_pmc_count = pos; return PFMLIB_SUCCESS; } static int pfm_dispatch_etb(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfmlib_event_t *e= inp->pfp_events; pfm_mont_pmc_reg_t reg; pfmlib_mont_input_param_t *param = mod_in; pfmlib_reg_t *pc, *pd; pfmlib_mont_input_param_t fake_param; int found_etb = 0, found_bad_dear = 0; int has_etb_param; unsigned int i, pos1, pos2; unsigned int count; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; pos1 = outp->pfp_pmc_count; pos2 = outp->pfp_pmd_count; /* * explicit ETB settings */ has_etb_param = param && param->pfp_mont_etb.etb_used; reg.pmc_val = 0UL; /* * we need to scan all events looking for DEAR ALAT/TLB due to incompatibility. * In this case PMC39 must be forced to zero */ count = inp->pfp_event_count; for (i=0; i < count; i++) { if (is_etb(e[i].event)) found_etb = 1; /* * keep track of the first ETB event */ /* look only for DEAR TLB */ if (is_dear(e[i].event) && (is_ear_tlb(e[i].event) || is_ear_alat(e[i].event))) { found_bad_dear = 1; } } DPRINT("found_etb=%d found_bar_dear=%d\n", found_etb, found_bad_dear); /* * did not find D-EAR TLB/ALAT event, need to check param structure */ if (found_bad_dear == 0 && param && param->pfp_mont_dear.ear_used == 1) { if ( param->pfp_mont_dear.ear_mode == PFMLIB_MONT_EAR_TLB_MODE || param->pfp_mont_dear.ear_mode == PFMLIB_MONT_EAR_ALAT_MODE) found_bad_dear = 1; } /* * no explicit ETB event and no special case to deal with (cover part of case 3) */ if (found_etb == 0 && has_etb_param == 0 && found_bad_dear == 0) return PFMLIB_SUCCESS; if (has_etb_param == 0) { /* * case 3: no ETB event, etb_used=0 but found_bad_dear=1, need to cleanup PMC12 */ if (found_etb == 0) goto assign_zero; /* * case 1: we have a ETB event but no param, default setting is to capture * all branches. */ memset(&fake_param, 0, sizeof(fake_param)); param = &fake_param; param->pfp_mont_etb.etb_tm = 0x3; /* all branches */ param->pfp_mont_etb.etb_ptm = 0x3; /* all branches */ param->pfp_mont_etb.etb_ppm = 0x3; /* all branches */ param->pfp_mont_etb.etb_brt = 0x0; /* all branches */ DPRINT("ETB event with no info\n"); } /* * case 2: ETB event in the list, param provided * case 4: no ETB event, param provided (free running mode) */ reg.pmc39_mont_reg.etbc_plm = param->pfp_mont_etb.etb_plm ? param->pfp_mont_etb.etb_plm : inp->pfp_dfl_plm; reg.pmc39_mont_reg.etbc_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc39_mont_reg.etbc_ds = 0; /* 1 is reserved */ reg.pmc39_mont_reg.etbc_tm = param->pfp_mont_etb.etb_tm & 0x3; reg.pmc39_mont_reg.etbc_ptm = param->pfp_mont_etb.etb_ptm & 0x3; reg.pmc39_mont_reg.etbc_ppm = param->pfp_mont_etb.etb_ppm & 0x3; reg.pmc39_mont_reg.etbc_brt = param->pfp_mont_etb.etb_brt & 0x3; /* * if DEAR-ALAT or DEAR-TLB is set then PMC12 must be set to zero (see documentation p. 87) * * D-EAR ALAT/TLB and ETB cannot be used at the same time. * From documentation: PMC12 must be zero in this mode; else the wrong IP for misses * coming right after a mispredicted branch. * * D-EAR cache is fine. */ assign_zero: if (found_bad_dear && reg.pmc_val != 0UL) return PFMLIB_ERR_EVTINCOMP; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 39)) return PFMLIB_ERR_NOASSIGN; pc[pos1].reg_num = 39; pc[pos1].reg_value = reg.pmc_val; pc[pos1].reg_addr = pc[pos1].reg_alt_addr = 39; pos1++; __pfm_vbprintf("[PMC39(pmc39)=0x%lx plm=%d pm=%d ds=%d tm=%d ptm=%d ppm=%d brt=%d]\n", reg.pmc_val, reg.pmc39_mont_reg.etbc_plm, reg.pmc39_mont_reg.etbc_pm, reg.pmc39_mont_reg.etbc_ds, reg.pmc39_mont_reg.etbc_tm, reg.pmc39_mont_reg.etbc_ptm, reg.pmc39_mont_reg.etbc_ppm, reg.pmc39_mont_reg.etbc_brt); /* * only add ETB PMDs when actually using BTB. * Not needed when dealing with D-EAR TLB and DEAR-ALAT * PMC39 restriction */ if (found_etb || has_etb_param) { pd[pos2].reg_num = 38; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 38; pos2++; pd[pos2].reg_num = 39; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 39; pos2++; __pfm_vbprintf("[PMD38(pmd38)]\n[PMD39(pmd39)\n"); for(i=48; i < 64; i++, pos2++) { pd[pos2].reg_num = i; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = i; __pfm_vbprintf("[PMD%u(pmd%u)]\n", pd[pos2].reg_num, pd[pos2].reg_num); } } /* update final number of entries used */ outp->pfp_pmc_count = pos1; outp->pfp_pmd_count = pos2; return PFMLIB_SUCCESS; } static void do_normal_rr(unsigned long start, unsigned long end, pfmlib_reg_t *br, int nbr, int dir, int *idx, int *reg_idx, int plm) { unsigned long size, l_addr, c; unsigned long l_offs = 0, r_offs = 0; unsigned long l_size, r_size; dbreg_t db; int p2; if (nbr < 1 || end <= start) return; size = end - start; DPRINT("start=0x%016lx end=0x%016lx size=0x%lx bytes (%lu bundles) nbr=%d dir=%d\n", start, end, size, size >> 4, nbr, dir); p2 = pfm_ia64_fls(size); c = ALIGN_DOWN(end, p2); DPRINT("largest power of two possible: 2^%d=0x%lx, crossing=0x%016lx\n", p2, 1UL << p2, c); if ((c - (1UL<= start) { l_addr = c - (1UL << p2); } else { p2--; if ((c + (1UL<>l_offs: 0x%lx\n", l_offs); } } else if (dir == 1 && r_size != 0 && nbr == 1) { p2++; l_addr = start; if (PFMLIB_DEBUG()) { r_offs = l_addr+(1UL<>r_offs: 0x%lx\n", r_offs); } } l_size = l_addr - start; r_size = end - l_addr-(1UL<>largest chunk: 2^%d @0x%016lx-0x%016lx\n", p2, l_addr, l_addr+(1UL<>before: 0x%016lx-0x%016lx\n", start, l_addr); if (r_size && !r_offs) printf(">>after : 0x%016lx-0x%016lx\n", l_addr+(1UL<>1; if (nbr & 0x1) { /* * our simple heuristic is: * we assign the largest number of registers to the largest * of the two chunks */ if (l_size > r_size) { l_nbr++; } else { r_nbr++; } } do_normal_rr(start, l_addr, br, l_nbr, 0, idx, reg_idx, plm); do_normal_rr(l_addr+(1UL<rr_start, in_rr->rr_end, n_pairs, fine_mode ? ", fine_mode" : "", rr_flags & PFMLIB_MONT_RR_INV ? ", inversed" : ""); __pfm_vbprintf("start offset: -0x%lx end_offset: +0x%lx\n", out_rr->rr_soff, out_rr->rr_eoff); for (j=0; j < n_pairs; j++, base_idx+=2) { d.val = dbr[base_idx+1].reg_value; r_end = dbr[base_idx].reg_value+((~(d.db.db_mask)) & ~(0xffUL << 56)); if (fine_mode) __pfm_vbprintf("brp%u: db%u: 0x%016lx db%u: plm=0x%x mask=0x%016lx\n", dbr[base_idx].reg_num>>1, dbr[base_idx].reg_num, dbr[base_idx].reg_value, dbr[base_idx+1].reg_num, d.db.db_plm, d.db.db_mask); else __pfm_vbprintf("brp%u: db%u: 0x%016lx db%u: plm=0x%x mask=0x%016lx end=0x%016lx\n", dbr[base_idx].reg_num>>1, dbr[base_idx].reg_num, dbr[base_idx].reg_value, dbr[base_idx+1].reg_num, d.db.db_plm, d.db.db_mask, r_end); } } /* * base_idx = base register index to use (for IBRP1, base_idx = 2) */ static int compute_fine_rr(pfmlib_mont_input_rr_t *irr, int dfl_plm, int n, int *base_idx, pfmlib_mont_output_rr_t *orr) { int i; pfmlib_reg_t *br; pfmlib_mont_input_rr_desc_t *in_rr; pfmlib_mont_output_rr_desc_t *out_rr; unsigned long addr; int reg_idx; dbreg_t db; in_rr = irr->rr_limits; out_rr = orr->rr_infos; br = orr->rr_br+orr->rr_nbr_used; reg_idx = *base_idx; db.val = 0; db.db.db_mask = FINE_MODE_MASK; if (n > 2) return PFMLIB_ERR_IRRTOOMANY; for (i=0; i < n; i++, reg_idx += 2, in_rr++, br+= 4) { /* * setup lower limit pair * * because of the PMU can only see addresses on a 2-bundle boundary, we must align * down to the closest bundle-pair aligned address. 5 => 32-byte aligned address */ addr = ALIGN_DOWN(in_rr->rr_start, 5); out_rr->rr_soff = in_rr->rr_start - addr; /* * adjust plm for each range */ db.db.db_plm = in_rr->rr_plm ? in_rr->rr_plm : (unsigned long)dfl_plm; br[0].reg_num = reg_idx; br[0].reg_value = addr; br[0].reg_addr = br[0].reg_alt_addr = 1+reg_idx; br[1].reg_num = reg_idx+1; br[1].reg_value = db.val; br[1].reg_addr = br[1].reg_alt_addr = 1+reg_idx+1; /* * setup upper limit pair * * * In fine mode, the bundle address stored in the upper limit debug * registers is included in the count, so we substract 0x10 to exclude it. * * because of the PMU bug, we align the (corrected) end to the nearest * 32-byte aligned address + 0x10. With this correction and depending * on the correction, we may count one * * */ addr = in_rr->rr_end - 0x10; if ((addr & 0x1f) == 0) addr += 0x10; out_rr->rr_eoff = addr - in_rr->rr_end + 0x10; br[2].reg_num = reg_idx+4; br[2].reg_value = addr; br[2].reg_addr = br[2].reg_alt_addr = 1+reg_idx+4; br[3].reg_num = reg_idx+5; br[3].reg_value = db.val; br[3].reg_addr = br[3].reg_alt_addr = 1+reg_idx+5; if (PFMLIB_VERBOSE()) print_one_range(in_rr, out_rr, br, 0, 2, 1, irr->rr_flags); } orr->rr_nbr_used += i<<2; /* update base_idx, for subsequent calls */ *base_idx = reg_idx; return PFMLIB_SUCCESS; } /* * base_idx = base register index to use (for IBRP1, base_idx = 2) */ static int compute_single_rr(pfmlib_mont_input_rr_t *irr, int dfl_plm, int *base_idx, pfmlib_mont_output_rr_t *orr) { unsigned long size, end, start; unsigned long p_start, p_end; pfmlib_mont_input_rr_desc_t *in_rr; pfmlib_mont_output_rr_desc_t *out_rr; pfmlib_reg_t *br; dbreg_t db; int reg_idx; int l, m; in_rr = irr->rr_limits; out_rr = orr->rr_infos; br = orr->rr_br+orr->rr_nbr_used; start = in_rr->rr_start; end = in_rr->rr_end; size = end - start; reg_idx = *base_idx; l = pfm_ia64_fls(size); m = l; if (size & ((1UL << l)-1)) { if (l>62) { printf("range: [0x%lx-0x%lx] too big\n", start, end); return PFMLIB_ERR_IRRTOOBIG; } m++; } DPRINT("size=%ld, l=%d m=%d, internal: 0x%lx full: 0x%lx\n", size, l, m, 1UL << l, 1UL << m); for (; m < 64; m++) { p_start = ALIGN_DOWN(start, m); p_end = p_start+(1UL<= end) goto found; } return PFMLIB_ERR_IRRINVAL; found: DPRINT("m=%d p_start=0x%lx p_end=0x%lx\n", m, p_start,p_end); /* when the event is not IA64_INST_RETIRED, then we MUST use ibrp0 */ br[0].reg_num = reg_idx; br[0].reg_value = p_start; br[0].reg_addr = br[0].reg_alt_addr = 1+reg_idx; db.val = 0; db.db.db_mask = ~((1UL << m)-1); db.db.db_plm = in_rr->rr_plm ? in_rr->rr_plm : (unsigned long)dfl_plm; br[1].reg_num = reg_idx + 1; br[1].reg_value = db.val; br[1].reg_addr = br[1].reg_alt_addr = 1+reg_idx+1; out_rr->rr_soff = start - p_start; out_rr->rr_eoff = p_end - end; if (PFMLIB_VERBOSE()) print_one_range(in_rr, out_rr, br, 0, 1, 0, irr->rr_flags); orr->rr_nbr_used += 2; /* update base_idx, for subsequent calls */ *base_idx = reg_idx; return PFMLIB_SUCCESS; } static int compute_normal_rr(pfmlib_mont_input_rr_t *irr, int dfl_plm, int n, int *base_idx, pfmlib_mont_output_rr_t *orr) { pfmlib_mont_input_rr_desc_t *in_rr; pfmlib_mont_output_rr_desc_t *out_rr; unsigned long r_end; pfmlib_reg_t *br; dbreg_t d; int i, j; int br_index, reg_idx, prev_index; in_rr = irr->rr_limits; out_rr = orr->rr_infos; br = orr->rr_br+orr->rr_nbr_used; reg_idx = *base_idx; br_index = 0; for (i=0; i < n; i++, in_rr++, out_rr++) { /* * running out of registers */ if (br_index == 8) break; prev_index = br_index; do_normal_rr( in_rr->rr_start, in_rr->rr_end, br, 4 - (reg_idx>>1), /* how many pairs available */ 0, &br_index, ®_idx, in_rr->rr_plm ? in_rr->rr_plm : dfl_plm); DPRINT("br_index=%d reg_idx=%d\n", br_index, reg_idx); /* * compute offsets */ out_rr->rr_soff = out_rr->rr_eoff = 0; for(j=prev_index; j < br_index; j+=2) { d.val = br[j+1].reg_value; r_end = br[j].reg_value+((~(d.db.db_mask)+1) & ~(0xffUL << 56)); if (br[j].reg_value <= in_rr->rr_start) out_rr->rr_soff = in_rr->rr_start - br[j].reg_value; if (r_end >= in_rr->rr_end) out_rr->rr_eoff = r_end - in_rr->rr_end; } if (PFMLIB_VERBOSE()) print_one_range(in_rr, out_rr, br, prev_index, (br_index-prev_index)>>1, 0, irr->rr_flags); } /* do not have enough registers to cover all the ranges */ if (br_index == 8 && i < n) return PFMLIB_ERR_TOOMANY; orr->rr_nbr_used += br_index; /* update base_idx, for subsequent calls */ *base_idx = reg_idx; return PFMLIB_SUCCESS; } static int pfm_dispatch_irange(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in, pfmlib_output_param_t *outp, pfmlib_mont_output_param_t *mod_out) { pfm_mont_pmc_reg_t reg; pfmlib_mont_input_param_t *param = mod_in; pfmlib_mont_input_rr_t *irr; pfmlib_mont_output_rr_t *orr; pfmlib_reg_t *pc = outp->pfp_pmcs; unsigned long retired_mask; unsigned int i, pos = outp->pfp_pmc_count, count; unsigned int retired_only, retired_count, fine_mode, prefetch_count; unsigned int n_intervals; int base_idx = 0, dup = 0; int ret; if (param == NULL) return PFMLIB_SUCCESS; if (param->pfp_mont_irange.rr_used == 0) return PFMLIB_SUCCESS; if (mod_out == NULL) return PFMLIB_ERR_INVAL; irr = ¶m->pfp_mont_irange; orr = &mod_out->pfp_mont_irange; ret = check_intervals(irr, 0, &n_intervals); if (ret != PFMLIB_SUCCESS) return ret; if (n_intervals < 1) return PFMLIB_ERR_IRRINVAL; retired_count = check_inst_retired_events(inp, &retired_mask); retired_only = retired_count == inp->pfp_event_count; fine_mode = irr->rr_flags & PFMLIB_MONT_RR_NO_FINE_MODE ? 0 : check_fine_mode_possible(irr, n_intervals); DPRINT("n_intervals=%d retired_only=%d retired_count=%d fine_mode=%d\n", n_intervals, retired_only, retired_count, fine_mode); /* * On montecito, there are more constraints on what can be measured with irange. * * - The fine mode is the best because you directly set the lower and upper limits of * the range. This uses 2 ibr pairs for range (ibrp0/ibrp2 and ibp1/ibrp3). Therefore * at most 2 fine mode ranges can be defined. The boundaries of the range must be in the * same 64KB page. The fine mode works will all events. * * - if the fine mode fails, then for all events, except IA64_TAGGED_INST_RETIRED_*, only * the first pair of ibr is available: ibrp0. This imposes some severe restrictions on the * size and alignement of the range. It can be bigger than 64KB and must be properly aligned * on its size. The library relaxes these constraints by allowing the covered areas to be * larger than the expected range. It may start before and end after the requested range. * You can determine the amount of overrun in either direction for each range by looking at * the rr_soff (start offset) and rr_eoff (end offset). * * - if the events include certain prefetch events then only IBRP1 can be used. * See 3.3.5.2 Exception 1. * * - Finally, when the events are ONLY IA64_TAGGED_INST_RETIRED_* then all IBR pairs can be used * to cover the range giving us more flexibility to approximate the range when it is not * properly aligned on its size (see 10.3.5.2 Exception 2). But the corresponding * IA64_TAGGED_INST_RETIRED_* must be present. */ if (fine_mode == 0 && retired_only == 0 && n_intervals > 1) return PFMLIB_ERR_IRRTOOMANY; /* we do not default to non-fine mode to support more ranges */ if (n_intervals > 2 && fine_mode == 1) return PFMLIB_ERR_IRRTOOMANY; ret = check_prefetch_events(inp, irr, &prefetch_count, &base_idx, &dup); if (ret) return ret; DPRINT("prefetch_count=%u base_idx=%d dup=%d\n", prefetch_count, base_idx, dup); /* * CPU_OP_CYCLES.QUAL supports code range restrictions but it returns * meaningful values (fine/coarse mode) only when IBRP1 is not used. */ if ((base_idx > 0 || dup) && has_cpu_cycles_qual(inp)) return PFMLIB_ERR_FEATCOMB; if (fine_mode == 0) { if (retired_only) { /* can take multiple intervals */ ret = compute_normal_rr(irr, inp->pfp_dfl_plm, n_intervals, &base_idx, orr); } else { /* unless we have only prefetch and instruction retired events, * we cannot satisfy the request because the other events cannot * be measured on anything but IBRP0. */ if ((prefetch_count+retired_count) != inp->pfp_event_count) return PFMLIB_ERR_FEATCOMB; ret = compute_single_rr(irr, inp->pfp_dfl_plm, &base_idx, orr); if (ret == PFMLIB_SUCCESS && dup) ret = compute_single_rr(irr, inp->pfp_dfl_plm, &base_idx, orr); } } else { if (prefetch_count && n_intervals != 1) return PFMLIB_ERR_IRRTOOMANY; /* except is retired_only, can take only one interval */ ret = compute_fine_rr(irr, inp->pfp_dfl_plm, n_intervals, &base_idx, orr); if (ret == PFMLIB_SUCCESS && dup) ret = compute_fine_rr(irr, inp->pfp_dfl_plm, n_intervals, &base_idx, orr); } if (ret != PFMLIB_SUCCESS) return ret == PFMLIB_ERR_TOOMANY ? PFMLIB_ERR_IRRTOOMANY : ret; reg.pmc_val = 0xdb6; /* default value */ count = orr->rr_nbr_used; for (i=0; i < count; i++) { switch(orr->rr_br[i].reg_num) { case 0: reg.pmc38_mont_reg.iarc_ig_ibrp0 = 0; break; case 2: reg.pmc38_mont_reg.iarc_ig_ibrp1 = 0; break; case 4: reg.pmc38_mont_reg.iarc_ig_ibrp2 = 0; break; case 6: reg.pmc38_mont_reg.iarc_ig_ibrp3 = 0; break; } } if (fine_mode) { reg.pmc38_mont_reg.iarc_fine = 1; } else if (retired_only) { /* * we need to check that the user provided all the events needed to cover * all the ibr pairs used to cover the range */ if ((retired_mask & 0x1) == 0 && reg.pmc38_mont_reg.iarc_ig_ibrp0 == 0) return PFMLIB_ERR_IRRINVAL; if ((retired_mask & 0x2) == 0 && reg.pmc38_mont_reg.iarc_ig_ibrp1 == 0) return PFMLIB_ERR_IRRINVAL; if ((retired_mask & 0x4) == 0 && reg.pmc38_mont_reg.iarc_ig_ibrp2 == 0) return PFMLIB_ERR_IRRINVAL; if ((retired_mask & 0x8) == 0 && reg.pmc38_mont_reg.iarc_ig_ibrp3 == 0) return PFMLIB_ERR_IRRINVAL; } if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 38)) return PFMLIB_ERR_NOASSIGN; pc[pos].reg_num = 38; pc[pos].reg_value = reg.pmc_val; pc[pos].reg_addr = pc[pos].reg_alt_addr = 38; pos++; __pfm_vbprintf("[PMC38(pmc38)=0x%lx ig_ibrp0=%d ig_ibrp1=%d ig_ibrp2=%d ig_ibrp3=%d fine=%d]\n", reg.pmc_val, reg.pmc38_mont_reg.iarc_ig_ibrp0, reg.pmc38_mont_reg.iarc_ig_ibrp1, reg.pmc38_mont_reg.iarc_ig_ibrp2, reg.pmc38_mont_reg.iarc_ig_ibrp3, reg.pmc38_mont_reg.iarc_fine); outp->pfp_pmc_count = pos; return PFMLIB_SUCCESS; } static const unsigned long iod_tab[8]={ /* --- */ 3, /* --D */ 2, /* -O- */ 3, /* should not be used */ /* -OD */ 0, /* =IOD safe because default IBR is harmless */ /* I-- */ 1, /* =IO safe because by defaut OPC is turned off */ /* I-D */ 0, /* =IOD safe because by default opc is turned off */ /* IO- */ 1, /* IOD */ 0 }; /* * IMPORTANT: MUST BE CALLED *AFTER* pfm_dispatch_irange() to make sure we see * the irange programming to adjust pmc41. */ static int pfm_dispatch_drange(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in, pfmlib_output_param_t *outp, pfmlib_mont_output_param_t *mod_out) { pfmlib_mont_input_param_t *param = mod_in; pfmlib_reg_t *pc = outp->pfp_pmcs; pfmlib_mont_input_rr_t *irr; pfmlib_mont_output_rr_t *orr, *orr2; pfm_mont_pmc_reg_t pmc38; pfm_mont_pmc_reg_t reg; unsigned int i, pos = outp->pfp_pmc_count; int iod_codes[4], dfl_val_pmc32, dfl_val_pmc34; unsigned int n_intervals; int ret; int base_idx = 0; int fine_mode = 0; #define DR_USED 0x1 /* data range is used */ #define OP_USED 0x2 /* opcode matching is used */ #define IR_USED 0x4 /* code range is used */ if (param == NULL) return PFMLIB_SUCCESS; /* * if only pmc32/pmc33 opcode matching is used, we do not need to change * the default value of pmc41 regardless of the events being measured. */ if ( param->pfp_mont_drange.rr_used == 0 && param->pfp_mont_irange.rr_used == 0) return PFMLIB_SUCCESS; /* * it seems like the ignored bits need to have special values * otherwise this does not work. */ reg.pmc_val = 0x2078fefefefe; /* * initialize iod codes */ iod_codes[0] = iod_codes[1] = iod_codes[2] = iod_codes[3] = 0; /* * setup default iod value, we need to separate because * if drange is used we do not know in advance which DBR will be used * therefore we need to apply dfl_val later */ dfl_val_pmc32 = param->pfp_mont_opcm1.opcm_used ? OP_USED : 0; dfl_val_pmc34 = param->pfp_mont_opcm2.opcm_used ? OP_USED : 0; if (param->pfp_mont_drange.rr_used == 1) { if (mod_out == NULL) return PFMLIB_ERR_INVAL; irr = ¶m->pfp_mont_drange; orr = &mod_out->pfp_mont_drange; ret = check_intervals(irr, 1, &n_intervals); if (ret != PFMLIB_SUCCESS) return ret; if (n_intervals < 1) return PFMLIB_ERR_DRRINVAL; ret = compute_normal_rr(irr, inp->pfp_dfl_plm, n_intervals, &base_idx, orr); if (ret != PFMLIB_SUCCESS) { return ret == PFMLIB_ERR_TOOMANY ? PFMLIB_ERR_DRRTOOMANY : ret; } /* * Update iod_codes to reflect the use of the DBR constraint. */ for (i=0; i < orr->rr_nbr_used; i++) { if (orr->rr_br[i].reg_num == 0) iod_codes[0] |= DR_USED | dfl_val_pmc32; if (orr->rr_br[i].reg_num == 2) iod_codes[1] |= DR_USED | dfl_val_pmc34; if (orr->rr_br[i].reg_num == 4) iod_codes[2] |= DR_USED | dfl_val_pmc32; if (orr->rr_br[i].reg_num == 6) iod_codes[3] |= DR_USED | dfl_val_pmc34; } } /* * XXX: assume dispatch_irange executed before calling this function */ if (param->pfp_mont_irange.rr_used == 1) { orr2 = &mod_out->pfp_mont_irange; if (mod_out == NULL) return PFMLIB_ERR_INVAL; /* * we need to find out whether or not the irange is using * fine mode. If this is the case, then we only need to * program pmc41 for the ibr pairs which designate the lower * bounds of a range. For instance, if IBRP0/IBRP2 are used, * then we only need to program pmc13.cfg_dbrp0 and pmc13.ena_dbrp0, * the PMU will automatically use IBRP2, even though pmc13.ena_dbrp2=0. */ for(i=0; i <= pos; i++) { if (pc[i].reg_num == 38) { pmc38.pmc_val = pc[i].reg_value; if (pmc38.pmc38_mont_reg.iarc_fine == 1) fine_mode = 1; break; } } /* * Update to reflect the use of the IBR constraint */ for (i=0; i < orr2->rr_nbr_used; i++) { if (orr2->rr_br[i].reg_num == 0) iod_codes[0] |= IR_USED | dfl_val_pmc32; if (orr2->rr_br[i].reg_num == 2) iod_codes[1] |= IR_USED | dfl_val_pmc34; if (fine_mode == 0 && orr2->rr_br[i].reg_num == 4) iod_codes[2] |= IR_USED | dfl_val_pmc32; if (fine_mode == 0 && orr2->rr_br[i].reg_num == 6) iod_codes[3] |= IR_USED | dfl_val_pmc34; } } if (param->pfp_mont_irange.rr_used == 0 && param->pfp_mont_drange.rr_used ==0) { iod_codes[0] = iod_codes[2] = dfl_val_pmc32; iod_codes[1] = iod_codes[3] = dfl_val_pmc34; } /* * update the cfg dbrpX field. If we put a constraint on a cfg dbrp, then * we must enable it in the corresponding ena_dbrpX */ reg.pmc41_mont_reg.darc_ena_dbrp0 = iod_codes[0] ? 1 : 0; reg.pmc41_mont_reg.darc_cfg_dtag0 = iod_tab[iod_codes[0]]; reg.pmc41_mont_reg.darc_ena_dbrp1 = iod_codes[1] ? 1 : 0; reg.pmc41_mont_reg.darc_cfg_dtag1 = iod_tab[iod_codes[1]]; reg.pmc41_mont_reg.darc_ena_dbrp2 = iod_codes[2] ? 1 : 0; reg.pmc41_mont_reg.darc_cfg_dtag2 = iod_tab[iod_codes[2]]; reg.pmc41_mont_reg.darc_ena_dbrp3 = iod_codes[3] ? 1 : 0; reg.pmc41_mont_reg.darc_cfg_dtag3 = iod_tab[iod_codes[3]]; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 41)) return PFMLIB_ERR_NOASSIGN; pc[pos].reg_num = 41; pc[pos].reg_value = reg.pmc_val; pc[pos].reg_addr = pc[pos].reg_alt_addr = 41; pos++; __pfm_vbprintf("[PMC41(pmc41)=0x%lx cfg_dtag0=%d cfg_dtag1=%d cfg_dtag2=%d cfg_dtag3=%d ena_dbrp0=%d ena_dbrp1=%d ena_dbrp2=%d ena_dbrp3=%d]\n", reg.pmc_val, reg.pmc41_mont_reg.darc_cfg_dtag0, reg.pmc41_mont_reg.darc_cfg_dtag1, reg.pmc41_mont_reg.darc_cfg_dtag2, reg.pmc41_mont_reg.darc_cfg_dtag3, reg.pmc41_mont_reg.darc_ena_dbrp0, reg.pmc41_mont_reg.darc_ena_dbrp1, reg.pmc41_mont_reg.darc_ena_dbrp2, reg.pmc41_mont_reg.darc_ena_dbrp3); outp->pfp_pmc_count = pos; return PFMLIB_SUCCESS; } static int check_qualifier_constraints(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in) { pfmlib_mont_input_param_t *param = mod_in; pfmlib_event_t *e = inp->pfp_events; unsigned int i, count; count = inp->pfp_event_count; for(i=0; i < count; i++) { /* * skip check for counter which requested it. Use at your own risk. * No all counters have necessarily been validated for use with * qualifiers. Typically the event is counted as if no constraint * existed. */ if (param->pfp_mont_counters[i].flags & PFMLIB_MONT_FL_EVT_NO_QUALCHECK) continue; if (evt_use_irange(param) && has_iarr(e[i].event) == 0) return PFMLIB_ERR_FEATCOMB; if (evt_use_drange(param) && has_darr(e[i].event) == 0) return PFMLIB_ERR_FEATCOMB; if (evt_use_opcm(param) && has_opcm(e[i].event) == 0) return PFMLIB_ERR_FEATCOMB; } return PFMLIB_SUCCESS; } static int check_range_plm(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in) { pfmlib_mont_input_param_t *param = mod_in; unsigned int i, count; if (param->pfp_mont_drange.rr_used == 0 && param->pfp_mont_irange.rr_used == 0) return PFMLIB_SUCCESS; /* * range restriction applies to all events, therefore we must have a consistent * set of plm and they must match the pfp_dfl_plm which is used to setup the debug * registers */ count = inp->pfp_event_count; for(i=0; i < count; i++) { if (inp->pfp_events[i].plm && inp->pfp_events[i].plm != inp->pfp_dfl_plm) return PFMLIB_ERR_FEATCOMB; } return PFMLIB_SUCCESS; } static int pfm_dispatch_ipear(pfmlib_input_param_t *inp, pfmlib_mont_input_param_t *mod_in, pfmlib_output_param_t *outp) { pfm_mont_pmc_reg_t reg; pfmlib_mont_input_param_t *param = mod_in; pfmlib_event_t *e = inp->pfp_events; pfmlib_reg_t *pc, *pd; unsigned int pos1, pos2; unsigned int i, count; pc = outp->pfp_pmcs; pd = outp->pfp_pmds; pos1 = outp->pfp_pmc_count; pos2 = outp->pfp_pmd_count; /* * check if there is something to do */ if (param == NULL || param->pfp_mont_ipear.ipear_used == 0) return PFMLIB_SUCCESS; /* * we need to look for use of ETB, because IP-EAR and ETB cannot be used at the * same time */ if (param->pfp_mont_etb.etb_used) return PFMLIB_ERR_FEATCOMB; /* * look for implicit ETB used because of BRANCH_EVENT */ count = inp->pfp_event_count; for (i=0; i < count; i++) { if (is_etb(e[i].event)) return PFMLIB_ERR_FEATCOMB; } reg.pmc_val = 0; reg.pmc42_mont_reg.ipear_plm = param->pfp_mont_ipear.ipear_plm ? param->pfp_mont_ipear.ipear_plm : inp->pfp_dfl_plm; reg.pmc42_mont_reg.ipear_pm = inp->pfp_flags & PFMLIB_PFP_SYSTEMWIDE ? 1 : 0; reg.pmc42_mont_reg.ipear_mode = 4; reg.pmc42_mont_reg.ipear_delay = param->pfp_mont_ipear.ipear_delay; if (pfm_regmask_isset(&inp->pfp_unavail_pmcs, 42)) return PFMLIB_ERR_NOASSIGN; pc[pos1].reg_num = 42; pc[pos1].reg_value = reg.pmc_val; pc[pos1].reg_addr = pc[pos1].reg_alt_addr = 42; pos1++; __pfm_vbprintf("[PMC42(pmc42)=0x%lx plm=%d pm=%d mode=%d delay=%d]\n", reg.pmc_val, reg.pmc42_mont_reg.ipear_plm, reg.pmc42_mont_reg.ipear_pm, reg.pmc42_mont_reg.ipear_mode, reg.pmc42_mont_reg.ipear_delay); pd[pos2].reg_num = 38; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 38; pos2++; pd[pos2].reg_num = 39; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = 39; pos2++; __pfm_vbprintf("[PMD38(pmd38)]\n[PMD39(pmd39)\n"); for(i=48; i < 64; i++, pos2++) { pd[pos2].reg_num = i; pd[pos2].reg_addr = pd[pos2].reg_alt_addr = i; __pfm_vbprintf("[PMD%u(pmd%u)]\n", pd[pos2].reg_num, pd[pos2].reg_num); } outp->pfp_pmc_count = pos1; outp->pfp_pmd_count = pos2; return PFMLIB_SUCCESS; } static int pfm_mont_dispatch_events(pfmlib_input_param_t *inp, void *model_in, pfmlib_output_param_t *outp, void *model_out) { int ret; pfmlib_mont_input_param_t *mod_in = (pfmlib_mont_input_param_t *)model_in; pfmlib_mont_output_param_t *mod_out = (pfmlib_mont_output_param_t *)model_out; /* * nothing will come out of this combination */ if (mod_out && mod_in == NULL) return PFMLIB_ERR_INVAL; /* check opcode match, range restriction qualifiers */ if (mod_in && check_qualifier_constraints(inp, mod_in) != PFMLIB_SUCCESS) return PFMLIB_ERR_FEATCOMB; /* check for problems with range restriction and per-event plm */ if (mod_in && check_range_plm(inp, mod_in) != PFMLIB_SUCCESS) return PFMLIB_ERR_FEATCOMB; ret = pfm_mont_dispatch_counters(inp, mod_in, outp); if (ret != PFMLIB_SUCCESS) return ret; /* now check for I-EAR */ ret = pfm_dispatch_iear(inp, mod_in, outp); if (ret != PFMLIB_SUCCESS) return ret; /* now check for D-EAR */ ret = pfm_dispatch_dear(inp, mod_in, outp); if (ret != PFMLIB_SUCCESS) return ret; /* XXX: must be done before dispatch_opcm() and dispatch_drange() */ ret = pfm_dispatch_irange(inp, mod_in, outp, mod_out);; if (ret != PFMLIB_SUCCESS) return ret; ret = pfm_dispatch_drange(inp, mod_in, outp, mod_out);; if (ret != PFMLIB_SUCCESS) return ret; /* now check for Opcode matchers */ ret = pfm_dispatch_opcm(inp, mod_in, outp, mod_out); if (ret != PFMLIB_SUCCESS) return ret; /* now check for ETB */ ret = pfm_dispatch_etb(inp, mod_in, outp); if (ret != PFMLIB_SUCCESS) return ret; /* now check for IP-EAR */ ret = pfm_dispatch_ipear(inp, mod_in, outp); return ret; } /* XXX: return value is also error code */ int pfm_mont_get_event_maxincr(unsigned int i, unsigned int *maxincr) { if (i >= PME_MONT_EVENT_COUNT || maxincr == NULL) return PFMLIB_ERR_INVAL; *maxincr = montecito_pe[i].pme_maxincr; return PFMLIB_SUCCESS; } int pfm_mont_is_ear(unsigned int i) { return i < PME_MONT_EVENT_COUNT && is_ear(i); } int pfm_mont_is_dear(unsigned int i) { return i < PME_MONT_EVENT_COUNT && is_dear(i); } int pfm_mont_is_dear_tlb(unsigned int i) { return i < PME_MONT_EVENT_COUNT && is_dear(i) && is_ear_tlb(i); } int pfm_mont_is_dear_cache(unsigned int i) { return i < PME_MONT_EVENT_COUNT && is_dear(i) && is_ear_cache(i); } int pfm_mont_is_dear_alat(unsigned int i) { return i < PME_MONT_EVENT_COUNT && is_ear_alat(i); } int pfm_mont_is_iear(unsigned int i) { return i < PME_MONT_EVENT_COUNT && is_iear(i); } int pfm_mont_is_iear_tlb(unsigned int i) { return i < PME_MONT_EVENT_COUNT && is_iear(i) && is_ear_tlb(i); } int pfm_mont_is_iear_cache(unsigned int i) { return i < PME_MONT_EVENT_COUNT && is_iear(i) && is_ear_cache(i); } int pfm_mont_is_etb(unsigned int i) { return i < PME_MONT_EVENT_COUNT && is_etb(i); } int pfm_mont_support_iarr(unsigned int i) { return i < PME_MONT_EVENT_COUNT && has_iarr(i); } int pfm_mont_support_darr(unsigned int i) { return i < PME_MONT_EVENT_COUNT && has_darr(i); } int pfm_mont_support_opcm(unsigned int i) { return i < PME_MONT_EVENT_COUNT && has_opcm(i); } int pfm_mont_support_all(unsigned int i) { return i < PME_MONT_EVENT_COUNT && has_all(i); } int pfm_mont_get_ear_mode(unsigned int i, pfmlib_mont_ear_mode_t *m) { pfmlib_mont_ear_mode_t r; if (!is_ear(i) || m == NULL) return PFMLIB_ERR_INVAL; r = PFMLIB_MONT_EAR_TLB_MODE; if (is_ear_tlb(i)) goto done; r = PFMLIB_MONT_EAR_CACHE_MODE; if (is_ear_cache(i)) goto done; r = PFMLIB_MONT_EAR_ALAT_MODE; if (is_ear_alat(i)) goto done; return PFMLIB_ERR_INVAL; done: *m = r; return PFMLIB_SUCCESS; } static int pfm_mont_get_event_code(unsigned int i, unsigned int cnt, int *code) { if (cnt != PFMLIB_CNT_FIRST && (cnt < 4 || cnt > 15)) return PFMLIB_ERR_INVAL; *code = (int)montecito_pe[i].pme_code; return PFMLIB_SUCCESS; } /* * This function is accessible directly to the user */ int pfm_mont_get_event_umask(unsigned int i, unsigned long *umask) { if (i >= PME_MONT_EVENT_COUNT || umask == NULL) return PFMLIB_ERR_INVAL; *umask = evt_umask(i); return PFMLIB_SUCCESS; } int pfm_mont_get_event_group(unsigned int i, int *grp) { if (i >= PME_MONT_EVENT_COUNT || grp == NULL) return PFMLIB_ERR_INVAL; *grp = evt_grp(i); return PFMLIB_SUCCESS; } int pfm_mont_get_event_set(unsigned int i, int *set) { if (i >= PME_MONT_EVENT_COUNT || set == NULL) return PFMLIB_ERR_INVAL; *set = evt_set(i) == 0xf ? PFMLIB_MONT_EVT_NO_SET : evt_set(i); return PFMLIB_SUCCESS; } int pfm_mont_get_event_type(unsigned int i, int *type) { if (i >= PME_MONT_EVENT_COUNT || type == NULL) return PFMLIB_ERR_INVAL; *type = evt_caf(i); return PFMLIB_SUCCESS; } /* external interface */ int pfm_mont_irange_is_fine(pfmlib_output_param_t *outp, pfmlib_mont_output_param_t *mod_out) { pfmlib_mont_output_param_t *param = mod_out; pfm_mont_pmc_reg_t reg; unsigned int i, count; /* some sanity checks */ if (outp == NULL || param == NULL) return 0; if (outp->pfp_pmc_count >= PFMLIB_MAX_PMCS) return 0; if (param->pfp_mont_irange.rr_nbr_used == 0) return 0; /* * we look for pmc38 as it contains the bit indicating if fine mode is used */ count = outp->pfp_pmc_count; for(i=0; i < count; i++) { if (outp->pfp_pmcs[i].reg_num == 38) goto found; } return 0; found: reg.pmc_val = outp->pfp_pmcs[i].reg_value; return reg.pmc38_mont_reg.iarc_fine ? 1 : 0; } static char * pfm_mont_get_event_name(unsigned int i) { return montecito_pe[i].pme_name; } static void pfm_mont_get_event_counters(unsigned int j, pfmlib_regmask_t *counters) { unsigned int i; unsigned long m; memset(counters, 0, sizeof(*counters)); m =montecito_pe[j].pme_counters; for(i=0; m ; i++, m>>=1) { if (m & 0x1) pfm_regmask_set(counters, i); } } static void pfm_mont_get_impl_pmcs(pfmlib_regmask_t *impl_pmcs) { unsigned int i = 0; for(i=0; i < 16; i++) pfm_regmask_set(impl_pmcs, i); for(i=32; i < 43; i++) pfm_regmask_set(impl_pmcs, i); } static void pfm_mont_get_impl_pmds(pfmlib_regmask_t *impl_pmds) { unsigned int i = 0; for(i=4; i < 16; i++) pfm_regmask_set(impl_pmds, i); for(i=32; i < 40; i++) pfm_regmask_set(impl_pmds, i); for(i=48; i < 64; i++) pfm_regmask_set(impl_pmds, i); } static void pfm_mont_get_impl_counters(pfmlib_regmask_t *impl_counters) { unsigned int i = 0; /* counter pmds are contiguous */ for(i=4; i < 16; i++) pfm_regmask_set(impl_counters, i); } static void pfm_mont_get_hw_counter_width(unsigned int *width) { *width = PMU_MONT_COUNTER_WIDTH; } static int pfm_mont_get_event_description(unsigned int ev, char **str) { char *s; s = montecito_pe[ev].pme_desc; if (s) { *str = strdup(s); } else { *str = NULL; } return PFMLIB_SUCCESS; } static int pfm_mont_get_cycle_event(pfmlib_event_t *e) { e->event = PME_MONT_CPU_OP_CYCLES_ALL; return PFMLIB_SUCCESS; } static int pfm_mont_get_inst_retired(pfmlib_event_t *e) { e->event = PME_MONT_IA64_INST_RETIRED; return PFMLIB_SUCCESS; } static unsigned int pfm_mont_get_num_event_masks(unsigned int event) { return has_mesi(event) ? 4 : 0; } static char * pfm_mont_get_event_mask_name(unsigned int event, unsigned int mask) { switch(mask) { case 0: return "I"; case 1: return "S"; case 2: return "E"; case 3: return "M"; } return NULL; } static int pfm_mont_get_event_mask_desc(unsigned int event, unsigned int mask, char **desc) { switch(mask) { case 0: *desc = strdup("invalid"); break; case 1: *desc = strdup("shared"); break; case 2: *desc = strdup("exclusive"); break; case 3: *desc = strdup("modified"); break; default: return PFMLIB_ERR_INVAL; } return PFMLIB_SUCCESS; } static int pfm_mont_get_event_mask_code(unsigned int event, unsigned int mask, unsigned int *code) { *code = mask; return PFMLIB_SUCCESS; } pfm_pmu_support_t montecito_support={ .pmu_name = "dual-core Itanium 2", .pmu_type = PFMLIB_MONTECITO_PMU, .pme_count = PME_MONT_EVENT_COUNT, .pmc_count = PMU_MONT_NUM_PMCS, .pmd_count = PMU_MONT_NUM_PMDS, .num_cnt = PMU_MONT_NUM_COUNTERS, .get_event_code = pfm_mont_get_event_code, .get_event_name = pfm_mont_get_event_name, .get_event_counters = pfm_mont_get_event_counters, .dispatch_events = pfm_mont_dispatch_events, .pmu_detect = pfm_mont_detect, .get_impl_pmcs = pfm_mont_get_impl_pmcs, .get_impl_pmds = pfm_mont_get_impl_pmds, .get_impl_counters = pfm_mont_get_impl_counters, .get_hw_counter_width = pfm_mont_get_hw_counter_width, .get_event_desc = pfm_mont_get_event_description, .get_cycle_event = pfm_mont_get_cycle_event, .get_inst_retired_event = pfm_mont_get_inst_retired, .get_num_event_masks = pfm_mont_get_num_event_masks, .get_event_mask_name = pfm_mont_get_event_mask_name, .get_event_mask_desc = pfm_mont_get_event_mask_desc, .get_event_mask_code = pfm_mont_get_event_mask_code }; papi-5.5.1/src/libpfm-3.y/lib/pfmlib_crayx2.c0000644000307100002310000003500413013651450020577 0ustar yarkhangraduate/* * Copyright (c) 2007 Cray Inc. * Contributed by Steve Kaufmann based on code from * Copyright (c) 2001-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include "pfmlib_priv.h" #include "pfmlib_crayx2_priv.h" #include "crayx2_events.h" #define CRAYX2_NO_REDUNDANT 0 /* if>0 an error if chip:ctr:ev repeated */ typedef enum { CTR_REDUNDANT = -2, /* event on counter repeated */ CTR_CONFLICT = -1, /* event on counter not the same as previous */ CTR_OK = 0 /* event on counter open */ } counter_use_t; static int pfm_crayx2_get_event_code (unsigned int i, unsigned int cnt, int *code) { if (cnt != PFMLIB_CNT_FIRST && cnt > crayx2_support.num_cnt) { DPRINT ("return: count %d exceeded #counters\n", cnt); return PFMLIB_ERR_INVAL; } else if (i >= crayx2_support.pme_count) { DPRINT ("return: event index %d exceeded #events\n", i); return PFMLIB_ERR_INVAL; } *code = crayx2_pe[i].pme_code; DPRINT ("return: event code is %#x\n", *code); return PFMLIB_SUCCESS; } static char * pfm_crayx2_get_event_name (unsigned int i) { if (i >= crayx2_support.pme_count) { DPRINT ("return: event index %d exceeded #events\n", i); return NULL; } DPRINT ("return: event name '%s'\n", crayx2_pe[i].pme_name); return (char *) crayx2_pe[i].pme_name; } static void pfm_crayx2_get_event_counters (unsigned int j, pfmlib_regmask_t *counters) { unsigned int i; memset (counters, 0, sizeof (*counters)); DPRINT ("event counters for %d counters\n", PMU_CRAYX2_NUM_COUNTERS); for (i=0; ipfp_event_count, inp->pfp_dfl_plm, inp->pfp_flags); for (i=0; ipfp_event_count; i++) { DPRINT (" %3d: event %3d plm %#3x flags %#8lx num_masks %d\n", i, inp->pfp_events[i].event, inp->pfp_events[i].plm, inp->pfp_events[i].flags, inp->pfp_events[i].num_masks); for (j=0; jpfp_events[i].num_masks; j++) { DPRINT (" unit-mask-%2d: %d\n", j, inp->pfp_events[i].unit_masks[j]); } } } /* Better have at least one event specified and not exceed limit. */ if (inp->pfp_event_count == 0) { DPRINT ("return: event count is 0\n"); return PFMLIB_ERR_INVAL; } else if (inp->pfp_event_count > PMU_CRAYX2_NUM_COUNTERS) { DPRINT ("return: event count exceeds max %d\n", PMU_CRAYX2_NUM_COUNTERS); return PFMLIB_ERR_TOOMANY; } memset (Pused, 0, sizeof(Pused)); memset (Cused, 0, sizeof(Cused)); memset (Mused, 0, sizeof(Mused)); /* Loop through the input parameters describing the events. */ for (i=0; ipfp_event_count; i++) { unsigned int code, chip, ctr, ev, chipno; counter_use_t ret; /* Acquire details describing this event code: * o which substrate/chip it is on * o which counter on the chip * o which event on the counter */ code = inp->pfp_events[i].event; chip = crayx2_pe[code].pme_chip; ctr = crayx2_pe[code].pme_ctr; ev = crayx2_pe[code].pme_event; chipno = crayx2_pe[code].pme_chipno; DPRINT ("%3d: code %3d chip %1d ctr %2d ev %1d chipno %2d\n", code, i, chip, ctr, ev, chipno); /* These priviledge levels are not recognized. */ if (inp->pfp_events[i].plm != 0) { DPRINT ("%3d: priviledge level %#x per event not allowed\n", i, inp->pfp_events[i].plm); return PFMLIB_ERR_INVAL; } /* No masks exist. */ if (inp->pfp_events[i].num_masks > 0) { DPRINT ("too many masks for event\n"); return PFMLIB_ERR_TOOMANY; } /* The event code. Set-up the event selection mask for * the PMC of the respective chip. Check if more than * one event on the same counter is selected. */ if (chip == PME_CRAYX2_CHIP_CPU) { ret = pfm_crayx2_counter_use (ctr, ev, &Pused[chipno], &Pevents); } else if (chip == PME_CRAYX2_CHIP_CACHE) { ret = pfm_crayx2_counter_use (ctr, ev, &Cused[chipno], &Cevents); } else if (chip == PME_CRAYX2_CHIP_MEMORY) { ret = pfm_crayx2_counter_use (ctr, ev, &Mused[chipno], &Mevents); } else { DPRINT ("return: invalid chip\n"); return PFMLIB_ERR_INVAL; } /* Each chip's counter can only count one event. */ if (ret == CTR_CONFLICT) { DPRINT ("return: ctr conflict\n"); return PFMLIB_ERR_EVTINCOMP; } else if (ret == CTR_REDUNDANT) { #if (CRAYX2_NO_REDUNDANT != 0) DPRINT ("return: ctr redundant\n"); return PFMLIB_ERR_EVTMANY; #else DPRINT ("warning: ctr redundant\n"); #endif /* CRAYX2_NO_REDUNDANT */ } /* Set up the output PMDs. */ outp->pfp_pmds[npmds].reg_num = crayx2_pe[code].pme_base + ctr + chipno*crayx2_pe[code].pme_nctrs; outp->pfp_pmds[npmds].reg_addr = 0; outp->pfp_pmds[npmds].reg_alt_addr = 0; outp->pfp_pmds[npmds].reg_value = 0; npmds++; } outp->pfp_pmd_count = npmds; if (PFMLIB_DEBUG ( )) { DPRINT ("P event mask %#16lx\n", Pevents); DPRINT ("C event mask %#16lx\n", Cevents); DPRINT ("M event mask %#16lx\n", Mevents); DPRINT ("PMDs: pmd_count %d\n", outp->pfp_pmd_count); for (i=0; ipfp_pmd_count; i++) { DPRINT (" %3d: reg_value %3lld reg_num %3d reg_addr %#16llx\n", i, outp->pfp_pmds[i].reg_value, outp->pfp_pmds[i].reg_num, outp->pfp_pmds[i].reg_addr); } } /* Set up the PMC basics for the chips that will be doing * some counting. */ if (pfm_crayx2_chip_use (Pused, PME_CRAYX2_CPU_CHIPS) > 0) { uint64_t Pctrl = PFM_CPU_START; uint64_t Pen = PFM_ENABLE_RW; if (inp->pfp_dfl_plm & (PFM_PLM0 | PFM_PLM1)) { Pen |= PFM_ENABLE_KERNEL; } if (inp->pfp_dfl_plm & PFM_PLM2) { Pen |= PFM_ENABLE_EXL; } if (inp->pfp_dfl_plm & PFM_PLM3) { Pen |= PFM_ENABLE_USER; } /* First of three CPU PMC registers. */ base_pmc = PMU_CRAYX2_CPU_PMC_BASE; outp->pfp_pmcs[npmcs].reg_value = Pctrl; outp->pfp_pmcs[npmcs].reg_num = base_pmc + PMC_CONTROL; outp->pfp_pmcs[npmcs].reg_addr = 0; outp->pfp_pmcs[npmcs].reg_alt_addr = 0; npmcs++; outp->pfp_pmcs[npmcs].reg_value = Pevents; outp->pfp_pmcs[npmcs].reg_num = base_pmc + PMC_EVENTS; outp->pfp_pmcs[npmcs].reg_addr = 0; outp->pfp_pmcs[npmcs].reg_alt_addr = 0; npmcs++; outp->pfp_pmcs[npmcs].reg_value = Pen; outp->pfp_pmcs[npmcs].reg_num = base_pmc + PMC_ENABLE; outp->pfp_pmcs[npmcs].reg_addr = 0; outp->pfp_pmcs[npmcs].reg_alt_addr = 0; npmcs++; } if (pfm_crayx2_chip_use (Cused, PME_CRAYX2_CACHE_CHIPS) > 0) { uint64_t Cctrl = PFM_CACHE_START; uint64_t Cen = PFM_ENABLE_RW; /* domains N/A */ /* Second of three Cache PMC registers. */ base_pmc = PMU_CRAYX2_CACHE_PMC_BASE; outp->pfp_pmcs[npmcs].reg_value = Cctrl; outp->pfp_pmcs[npmcs].reg_num = base_pmc + PMC_CONTROL; outp->pfp_pmcs[npmcs].reg_addr = 0; outp->pfp_pmcs[npmcs].reg_alt_addr = 0; npmcs++; outp->pfp_pmcs[npmcs].reg_value = Cevents; outp->pfp_pmcs[npmcs].reg_num = base_pmc + PMC_EVENTS; outp->pfp_pmcs[npmcs].reg_addr = 0; outp->pfp_pmcs[npmcs].reg_alt_addr = 0; npmcs++; outp->pfp_pmcs[npmcs].reg_value = Cen; outp->pfp_pmcs[npmcs].reg_num = base_pmc + PMC_ENABLE; outp->pfp_pmcs[npmcs].reg_addr = 0; outp->pfp_pmcs[npmcs].reg_alt_addr = 0; npmcs++; } if (pfm_crayx2_chip_use (Mused, PME_CRAYX2_MEMORY_CHIPS) > 0) { uint64_t Mctrl = PFM_MEM_START; uint64_t Men = PFM_ENABLE_RW; /* domains N/A */ /* Third of three Memory PMC registers. */ base_pmc = PMU_CRAYX2_MEMORY_PMC_BASE; outp->pfp_pmcs[npmcs].reg_value = Mctrl; outp->pfp_pmcs[npmcs].reg_num = base_pmc + PMC_CONTROL; outp->pfp_pmcs[npmcs].reg_addr = 0; outp->pfp_pmcs[npmcs].reg_alt_addr = 0; npmcs++; outp->pfp_pmcs[npmcs].reg_value = Mevents; outp->pfp_pmcs[npmcs].reg_num = base_pmc + PMC_EVENTS; outp->pfp_pmcs[npmcs].reg_addr = 0; outp->pfp_pmcs[npmcs].reg_alt_addr = 0; npmcs++; outp->pfp_pmcs[npmcs].reg_value = Men; outp->pfp_pmcs[npmcs].reg_num = base_pmc + PMC_ENABLE; outp->pfp_pmcs[npmcs].reg_addr = 0; outp->pfp_pmcs[npmcs].reg_alt_addr = 0; npmcs++; } outp->pfp_pmc_count = npmcs; if (PFMLIB_DEBUG ( )) { DPRINT ("PMCs: pmc_count %d\n", outp->pfp_pmc_count); for (i=0; ipfp_pmc_count; i++) { DPRINT (" %3d: reg_value %#16llx reg_num %3d reg_addr %#16llx\n", i, outp->pfp_pmcs[i].reg_value, outp->pfp_pmcs[i].reg_num, outp->pfp_pmcs[i].reg_addr); } } return PFMLIB_SUCCESS; } static int pfm_crayx2_pmu_detect (void) { char buffer[128]; int ret; DPRINT ("detect the PMU attributes\n"); ret = __pfm_getcpuinfo_attr ("vendor_id", buffer, sizeof(buffer)); if (ret != 0 || strcasecmp (buffer, "Cray") != 0) { DPRINT ("return: no 'Cray' vendor_id\n"); return PFMLIB_ERR_NOTSUPP; } ret = __pfm_getcpuinfo_attr ("type", buffer, sizeof(buffer)); if (ret != 0 || strcasecmp (buffer, "craynv2") != 0) { DPRINT ("return: no 'craynv2' type\n"); return PFMLIB_ERR_NOTSUPP; } DPRINT ("Cray X2 nv2 found\n"); return PFMLIB_SUCCESS; } static void pfm_crayx2_get_impl_pmcs (pfmlib_regmask_t *impl_pmcs) { unsigned int i; DPRINT ("entered with PMC_COUNT %d\n", PMU_CRAYX2_PMC_COUNT); for (i=0; ievent = PME_CRAYX2_CYCLES; DPRINT ("return: event code for cycles %#x\n", e->event); return PFMLIB_SUCCESS; } static int pfm_crayx2_get_inst_retired (pfmlib_event_t *e) { e->event = PME_CRAYX2_INSTR_GRADUATED; DPRINT ("return: event code for retired instr %#x\n", e->event); return PFMLIB_SUCCESS; } /* Register the constants and the access functions. */ pfm_pmu_support_t crayx2_support = { .pmu_name = PMU_CRAYX2_NAME, .pmu_type = PFMLIB_CRAYX2_PMU, .pme_count = PME_CRAYX2_EVENT_COUNT, .pmc_count = PMU_CRAYX2_PMC_COUNT, .pmd_count = PMU_CRAYX2_PMD_COUNT, .num_cnt = PMU_CRAYX2_NUM_COUNTERS, .get_event_code = pfm_crayx2_get_event_code, .get_event_name = pfm_crayx2_get_event_name, .get_event_counters = pfm_crayx2_get_event_counters, .dispatch_events = pfm_crayx2_dispatch_events, .pmu_detect = pfm_crayx2_pmu_detect, .get_impl_pmcs = pfm_crayx2_get_impl_pmcs, .get_impl_pmds = pfm_crayx2_get_impl_pmds, .get_impl_counters = pfm_crayx2_get_impl_counters, .get_hw_counter_width = pfm_crayx2_get_hw_counter_width, .get_event_desc = pfm_crayx2_get_event_desc, .get_num_event_masks = pfm_crayx2_get_num_event_masks, .get_event_mask_name = pfm_crayx2_get_event_mask_name, .get_event_mask_code = pfm_crayx2_get_event_mask_code, .get_event_mask_desc = pfm_crayx2_get_event_mask_desc, .get_cycle_event = pfm_crayx2_get_cycle_event, .get_inst_retired_event = pfm_crayx2_get_inst_retired }; papi-5.5.1/src/libpfm-3.y/lib/ultra12_events.h0000644000307100002310000000666613013651450020735 0ustar yarkhangraduatestatic pme_sparc_entry_t ultra12_pe[] = { /* These two must always be first. */ { .pme_name = "Cycle_cnt", .pme_desc = "Accumulated cycles", .pme_ctrl = PME_CTRL_S0 | PME_CTRL_S1, .pme_val = 0x0, }, { .pme_name = "Instr_cnt", .pme_desc = "Number of instructions completed", .pme_ctrl = PME_CTRL_S0 | PME_CTRL_S1, .pme_val = 0x1, }, { .pme_name = "Dispatch0_IC_miss", .pme_desc = "I-buffer is empty from I-Cache miss", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x2, }, /* PIC0 events for UltraSPARC-I/II/IIi/IIe */ { .pme_name = "Dispatch0_storeBuf", .pme_desc = "Store buffer can not hold additional stores", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x3, }, { .pme_name = "IC_ref", .pme_desc = "I-cache references", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x8, }, { .pme_name = "DC_rd", .pme_desc = "D-cache read references (including accesses that subsequently trap)", .pme_ctrl = PME_CTRL_S0, .pme_val = 0x9, }, { .pme_name = "DC_wr", .pme_desc = "D-cache write references (including accesses that subsequently trap)", .pme_ctrl = PME_CTRL_S0, .pme_val = 0xa, }, { .pme_name = "Load_use", .pme_desc = "An instruction in the execute stage depends on an earlier load result that is not yet available", .pme_ctrl = PME_CTRL_S0, .pme_val = 0xb, }, { .pme_name = "EC_ref", .pme_desc = "Total E-cache references", .pme_ctrl = PME_CTRL_S0, .pme_val = 0xc, }, { .pme_name = "EC_write_hit_RDO", .pme_desc = "E-cache hits that do a read for ownership UPA transaction", .pme_ctrl = PME_CTRL_S0, .pme_val = 0xd, }, { .pme_name = "EC_snoop_inv", .pme_desc = "E-cache invalidates from the following UPA transactions: S_INV_REQ, S_CPI_REQ", .pme_ctrl = PME_CTRL_S0, .pme_val = 0xe, }, { .pme_name = "EC_rd_hit", .pme_desc = "E-cache read hits from D-cache misses", .pme_ctrl = PME_CTRL_S0, .pme_val = 0xf, }, /* PIC1 events for UltraSPARC-I/II/IIi/IIe */ { .pme_name = "Dispatch0_mispred", .pme_desc = "I-buffer is empty from Branch misprediction", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x2, }, { .pme_name = "Dispatch0_FP_use", .pme_desc = "First instruction in the group depends on an earlier floating point result that is not yet available", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x3, }, { .pme_name = "IC_hit", .pme_desc = "I-cache hits", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x8, }, { .pme_name = "DC_rd_hit", .pme_desc = "D-cache read hits", .pme_ctrl = PME_CTRL_S1, .pme_val = 0x9, }, { .pme_name = "DC_wr_hit", .pme_desc = "D-cache write hits", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xa, }, { .pme_name = "Load_use_RAW", .pme_desc = "There is a load use in the execute stage and there is a read-after-write hazard on the oldest outstanding load", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xb, }, { .pme_name = "EC_hit", .pme_desc = "Total E-cache hits", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xc, }, { .pme_name = "EC_wb", .pme_desc = "E-cache misses that do writebacks", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xd, }, { .pme_name = "EC_snoop_cb", .pme_desc = "E-cache snoop copy-backs from the following UPA transactions: S_CPB_REQ, S_CPI_REQ, S_CPD_REQ, S_CPB_MIS_REQ", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xe, }, { .pme_name = "EC_ic_hit", .pme_desc = "E-cache read hits from I-cache misses", .pme_ctrl = PME_CTRL_S1, .pme_val = 0xf, }, }; #define PME_ULTRA12_EVENT_COUNT (sizeof(ultra12_pe)/sizeof(pme_sparc_entry_t)) papi-5.5.1/src/libpfm-3.y/lib/itanium2_events.h0000644000307100002310000027467013013651450021175 0ustar yarkhangraduate/* * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ /* * This file is generated automatically * !! DO NOT CHANGE !! */ static pme_ita2_entry_t itanium2_pe []={ #define PME_ITA2_ALAT_CAPACITY_MISS_ALL 0 { "ALAT_CAPACITY_MISS_ALL", {0x30058}, 0xf0, 2, {0xf00007}, "ALAT Entry Replaced -- both integer and floating point instructions"}, #define PME_ITA2_ALAT_CAPACITY_MISS_FP 1 { "ALAT_CAPACITY_MISS_FP", {0x20058}, 0xf0, 2, {0xf00007}, "ALAT Entry Replaced -- only floating point instructions"}, #define PME_ITA2_ALAT_CAPACITY_MISS_INT 2 { "ALAT_CAPACITY_MISS_INT", {0x10058}, 0xf0, 2, {0xf00007}, "ALAT Entry Replaced -- only integer instructions"}, #define PME_ITA2_BACK_END_BUBBLE_ALL 3 { "BACK_END_BUBBLE_ALL", {0x0}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe -- Front-end, RSE, EXE, FPU/L1D stall or a pipeline flush due to an exception/branch misprediction"}, #define PME_ITA2_BACK_END_BUBBLE_FE 4 { "BACK_END_BUBBLE_FE", {0x10000}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe -- front-end"}, #define PME_ITA2_BACK_END_BUBBLE_L1D_FPU_RSE 5 { "BACK_END_BUBBLE_L1D_FPU_RSE", {0x20000}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe -- L1D_FPU or RSE."}, #define PME_ITA2_BE_BR_MISPRED_DETAIL_ANY 6 { "BE_BR_MISPRED_DETAIL_ANY", {0x61}, 0xf0, 1, {0xf00003}, "BE Branch Misprediction Detail -- any back-end (be) mispredictions"}, #define PME_ITA2_BE_BR_MISPRED_DETAIL_PFS 7 { "BE_BR_MISPRED_DETAIL_PFS", {0x30061}, 0xf0, 1, {0xf00003}, "BE Branch Misprediction Detail -- only back-end pfs mispredictions for taken branches"}, #define PME_ITA2_BE_BR_MISPRED_DETAIL_ROT 8 { "BE_BR_MISPRED_DETAIL_ROT", {0x20061}, 0xf0, 1, {0xf00003}, "BE Branch Misprediction Detail -- only back-end rotate mispredictions"}, #define PME_ITA2_BE_BR_MISPRED_DETAIL_STG 9 { "BE_BR_MISPRED_DETAIL_STG", {0x10061}, 0xf0, 1, {0xf00003}, "BE Branch Misprediction Detail -- only back-end stage mispredictions"}, #define PME_ITA2_BE_EXE_BUBBLE_ALL 10 { "BE_EXE_BUBBLE_ALL", {0x2}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe"}, #define PME_ITA2_BE_EXE_BUBBLE_ARCR 11 { "BE_EXE_BUBBLE_ARCR", {0x40002}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to AR or CR dependency"}, #define PME_ITA2_BE_EXE_BUBBLE_ARCR_PR_CANCEL_BANK 12 { "BE_EXE_BUBBLE_ARCR_PR_CANCEL_BANK", {0x80002}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- ARCR, PR, CANCEL or BANK_SWITCH"}, #define PME_ITA2_BE_EXE_BUBBLE_BANK_SWITCH 13 { "BE_EXE_BUBBLE_BANK_SWITCH", {0x70002}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to bank switching."}, #define PME_ITA2_BE_EXE_BUBBLE_CANCEL 14 { "BE_EXE_BUBBLE_CANCEL", {0x60002}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to a canceled load"}, #define PME_ITA2_BE_EXE_BUBBLE_FRALL 15 { "BE_EXE_BUBBLE_FRALL", {0x20002}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to FR/FR or FR/load dependency"}, #define PME_ITA2_BE_EXE_BUBBLE_GRALL 16 { "BE_EXE_BUBBLE_GRALL", {0x10002}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to GR/GR or GR/load dependency"}, #define PME_ITA2_BE_EXE_BUBBLE_GRGR 17 { "BE_EXE_BUBBLE_GRGR", {0x50002}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to GR/GR dependency"}, #define PME_ITA2_BE_EXE_BUBBLE_PR 18 { "BE_EXE_BUBBLE_PR", {0x30002}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to Execution Unit Stalls -- Back-end was stalled by exe due to PR dependency"}, #define PME_ITA2_BE_FLUSH_BUBBLE_ALL 19 { "BE_FLUSH_BUBBLE_ALL", {0x4}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to Flushes. -- Back-end was stalled due to either an exception/interruption or branch misprediction flush"}, #define PME_ITA2_BE_FLUSH_BUBBLE_BRU 20 { "BE_FLUSH_BUBBLE_BRU", {0x10004}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to Flushes. -- Back-end was stalled due to a branch misprediction flush"}, #define PME_ITA2_BE_FLUSH_BUBBLE_XPN 21 { "BE_FLUSH_BUBBLE_XPN", {0x20004}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to Flushes. -- Back-end was stalled due to an exception/interruption flush"}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_ALL 22 { "BE_L1D_FPU_BUBBLE_ALL", {0xca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D or FPU"}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_FPU 23 { "BE_L1D_FPU_BUBBLE_FPU", {0x100ca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by FPU."}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D 24 { "BE_L1D_FPU_BUBBLE_L1D", {0x200ca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D. This includes all stalls caused by the L1 pipeline (created in the L1D stage of the L1 pipeline which corresponds to the DET stage of the main pipe)."}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_DCS 25 { "BE_L1D_FPU_BUBBLE_L1D_DCS", {0x800ca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to DCS requiring a stall"}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_DCURECIR 26 { "BE_L1D_FPU_BUBBLE_L1D_DCURECIR", {0x400ca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to DCU recirculating"}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_FILLCONF 27 { "BE_L1D_FPU_BUBBLE_L1D_FILLCONF", {0x700ca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due a store in conflict with a returning fill."}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_FULLSTBUF 28 { "BE_L1D_FPU_BUBBLE_L1D_FULLSTBUF", {0x300ca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to store buffer being full"}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_HPW 29 { "BE_L1D_FPU_BUBBLE_L1D_HPW", {0x500ca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to Hardware Page Walker"}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_L2BPRESS 30 { "BE_L1D_FPU_BUBBLE_L1D_L2BPRESS", {0x900ca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to L2 Back Pressure"}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_LDCHK 31 { "BE_L1D_FPU_BUBBLE_L1D_LDCHK", {0xc00ca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to architectural ordering conflict"}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_LDCONF 32 { "BE_L1D_FPU_BUBBLE_L1D_LDCONF", {0xb00ca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to architectural ordering conflict"}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_NAT 33 { "BE_L1D_FPU_BUBBLE_L1D_NAT", {0xd00ca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to L1D data return needing recirculated NaT generation."}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_NATCONF 34 { "BE_L1D_FPU_BUBBLE_L1D_NATCONF", {0xf00ca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to ld8.fill conflict with st8.spill not written to unat."}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_STBUFRECIR 35 { "BE_L1D_FPU_BUBBLE_L1D_STBUFRECIR", {0xe00ca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to store buffer cancel needing recirculate."}, #define PME_ITA2_BE_L1D_FPU_BUBBLE_L1D_TLB 36 { "BE_L1D_FPU_BUBBLE_L1D_TLB", {0xa00ca}, 0xf0, 1, {0x5210000}, "Full Pipe Bubbles in Main Pipe due to FPU or L1D Cache -- Back-end was stalled by L1D due to L2DTLB to L1DTLB transfer"}, #define PME_ITA2_BE_LOST_BW_DUE_TO_FE_ALL 37 { "BE_LOST_BW_DUE_TO_FE_ALL", {0x72}, 0xf0, 2, {0xf00000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- count regardless of cause"}, #define PME_ITA2_BE_LOST_BW_DUE_TO_FE_BI 38 { "BE_LOST_BW_DUE_TO_FE_BI", {0x90072}, 0xf0, 2, {0xf00000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by branch initialization stall"}, #define PME_ITA2_BE_LOST_BW_DUE_TO_FE_BRQ 39 { "BE_LOST_BW_DUE_TO_FE_BRQ", {0xa0072}, 0xf0, 2, {0xf00000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by branch retirement queue stall"}, #define PME_ITA2_BE_LOST_BW_DUE_TO_FE_BR_ILOCK 40 { "BE_LOST_BW_DUE_TO_FE_BR_ILOCK", {0xc0072}, 0xf0, 2, {0xf00000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by branch interlock stall"}, #define PME_ITA2_BE_LOST_BW_DUE_TO_FE_BUBBLE 41 { "BE_LOST_BW_DUE_TO_FE_BUBBLE", {0xd0072}, 0xf0, 2, {0xf00000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by branch resteer bubble stall"}, #define PME_ITA2_BE_LOST_BW_DUE_TO_FE_FEFLUSH 42 { "BE_LOST_BW_DUE_TO_FE_FEFLUSH", {0x10072}, 0xf0, 2, {0xf00000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by a front-end flush"}, #define PME_ITA2_BE_LOST_BW_DUE_TO_FE_FILL_RECIRC 43 { "BE_LOST_BW_DUE_TO_FE_FILL_RECIRC", {0x80072}, 0xf0, 2, {0xf00000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by a recirculate for a cache line fill operation"}, #define PME_ITA2_BE_LOST_BW_DUE_TO_FE_IBFULL 44 { "BE_LOST_BW_DUE_TO_FE_IBFULL", {0x50072}, 0xf0, 2, {0xf00000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- (* meaningless for this event *)"}, #define PME_ITA2_BE_LOST_BW_DUE_TO_FE_IMISS 45 { "BE_LOST_BW_DUE_TO_FE_IMISS", {0x60072}, 0xf0, 2, {0xf00000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by instruction cache miss stall"}, #define PME_ITA2_BE_LOST_BW_DUE_TO_FE_PLP 46 { "BE_LOST_BW_DUE_TO_FE_PLP", {0xb0072}, 0xf0, 2, {0xf00000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by perfect loop prediction stall"}, #define PME_ITA2_BE_LOST_BW_DUE_TO_FE_TLBMISS 47 { "BE_LOST_BW_DUE_TO_FE_TLBMISS", {0x70072}, 0xf0, 2, {0xf00000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by TLB stall"}, #define PME_ITA2_BE_LOST_BW_DUE_TO_FE_UNREACHED 48 { "BE_LOST_BW_DUE_TO_FE_UNREACHED", {0x40072}, 0xf0, 2, {0xf00000}, "Invalid Bundles if BE Not Stalled for Other Reasons. -- only if caused by unreachable bundle"}, #define PME_ITA2_BE_RSE_BUBBLE_ALL 49 { "BE_RSE_BUBBLE_ALL", {0x1}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE"}, #define PME_ITA2_BE_RSE_BUBBLE_AR_DEP 50 { "BE_RSE_BUBBLE_AR_DEP", {0x20001}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to AR dependencies"}, #define PME_ITA2_BE_RSE_BUBBLE_BANK_SWITCH 51 { "BE_RSE_BUBBLE_BANK_SWITCH", {0x10001}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to bank switching"}, #define PME_ITA2_BE_RSE_BUBBLE_LOADRS 52 { "BE_RSE_BUBBLE_LOADRS", {0x50001}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to loadrs calculations"}, #define PME_ITA2_BE_RSE_BUBBLE_OVERFLOW 53 { "BE_RSE_BUBBLE_OVERFLOW", {0x30001}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to need to spill"}, #define PME_ITA2_BE_RSE_BUBBLE_UNDERFLOW 54 { "BE_RSE_BUBBLE_UNDERFLOW", {0x40001}, 0xf0, 1, {0xf00000}, "Full Pipe Bubbles in Main Pipe due to RSE Stalls -- Back-end was stalled by RSE due to need to fill"}, #define PME_ITA2_BRANCH_EVENT 55 { "BRANCH_EVENT", {0x111}, 0xf0, 1, {0xf00003}, "Branch Event Captured"}, #define PME_ITA2_BR_MISPRED_DETAIL_ALL_ALL_PRED 56 { "BR_MISPRED_DETAIL_ALL_ALL_PRED", {0x5b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- All branch types regardless of prediction result"}, #define PME_ITA2_BR_MISPRED_DETAIL_ALL_CORRECT_PRED 57 { "BR_MISPRED_DETAIL_ALL_CORRECT_PRED", {0x1005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- All branch types, correctly predicted branches (outcome and target)"}, #define PME_ITA2_BR_MISPRED_DETAIL_ALL_WRONG_PATH 58 { "BR_MISPRED_DETAIL_ALL_WRONG_PATH", {0x2005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- All branch types, mispredicted branches due to wrong branch direction"}, #define PME_ITA2_BR_MISPRED_DETAIL_ALL_WRONG_TARGET 59 { "BR_MISPRED_DETAIL_ALL_WRONG_TARGET", {0x3005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- All branch types, mispredicted branches due to wrong target for taken branches"}, #define PME_ITA2_BR_MISPRED_DETAIL_IPREL_ALL_PRED 60 { "BR_MISPRED_DETAIL_IPREL_ALL_PRED", {0x4005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- Only IP relative branches, regardless of prediction result"}, #define PME_ITA2_BR_MISPRED_DETAIL_IPREL_CORRECT_PRED 61 { "BR_MISPRED_DETAIL_IPREL_CORRECT_PRED", {0x5005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- Only IP relative branches, correctly predicted branches (outcome and target)"}, #define PME_ITA2_BR_MISPRED_DETAIL_IPREL_WRONG_PATH 62 { "BR_MISPRED_DETAIL_IPREL_WRONG_PATH", {0x6005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- Only IP relative branches, mispredicted branches due to wrong branch direction"}, #define PME_ITA2_BR_MISPRED_DETAIL_IPREL_WRONG_TARGET 63 { "BR_MISPRED_DETAIL_IPREL_WRONG_TARGET", {0x7005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- Only IP relative branches, mispredicted branches due to wrong target for taken branches"}, #define PME_ITA2_BR_MISPRED_DETAIL_NTRETIND_ALL_PRED 64 { "BR_MISPRED_DETAIL_NTRETIND_ALL_PRED", {0xc005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- Only non-return indirect branches, regardless of prediction result"}, #define PME_ITA2_BR_MISPRED_DETAIL_NTRETIND_CORRECT_PRED 65 { "BR_MISPRED_DETAIL_NTRETIND_CORRECT_PRED", {0xd005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- Only non-return indirect branches, correctly predicted branches (outcome and target)"}, #define PME_ITA2_BR_MISPRED_DETAIL_NTRETIND_WRONG_PATH 66 { "BR_MISPRED_DETAIL_NTRETIND_WRONG_PATH", {0xe005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- Only non-return indirect branches, mispredicted branches due to wrong branch direction"}, #define PME_ITA2_BR_MISPRED_DETAIL_NTRETIND_WRONG_TARGET 67 { "BR_MISPRED_DETAIL_NTRETIND_WRONG_TARGET", {0xf005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- Only non-return indirect branches, mispredicted branches due to wrong target for taken branches"}, #define PME_ITA2_BR_MISPRED_DETAIL_RETURN_ALL_PRED 68 { "BR_MISPRED_DETAIL_RETURN_ALL_PRED", {0x8005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- Only return type branches, regardless of prediction result"}, #define PME_ITA2_BR_MISPRED_DETAIL_RETURN_CORRECT_PRED 69 { "BR_MISPRED_DETAIL_RETURN_CORRECT_PRED", {0x9005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- Only return type branches, correctly predicted branches (outcome and target)"}, #define PME_ITA2_BR_MISPRED_DETAIL_RETURN_WRONG_PATH 70 { "BR_MISPRED_DETAIL_RETURN_WRONG_PATH", {0xa005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- Only return type branches, mispredicted branches due to wrong branch direction"}, #define PME_ITA2_BR_MISPRED_DETAIL_RETURN_WRONG_TARGET 71 { "BR_MISPRED_DETAIL_RETURN_WRONG_TARGET", {0xb005b}, 0xf0, 3, {0xf00003}, "FE Branch Mispredict Detail -- Only return type branches, mispredicted branches due to wrong target for taken branches"}, #define PME_ITA2_BR_MISPRED_DETAIL2_ALL_ALL_UNKNOWN_PRED 72 { "BR_MISPRED_DETAIL2_ALL_ALL_UNKNOWN_PRED", {0x68}, 0xf0, 2, {0xf00003}, "FE Branch Mispredict Detail (Unknown Path Component) -- All branch types, branches with unknown path prediction"}, #define PME_ITA2_BR_MISPRED_DETAIL2_ALL_UNKNOWN_PATH_CORRECT_PRED 73 { "BR_MISPRED_DETAIL2_ALL_UNKNOWN_PATH_CORRECT_PRED", {0x10068}, 0xf0, 2, {0xf00003}, "FE Branch Mispredict Detail (Unknown Path Component) -- All branch types, branches with unknown path prediction and correctly predicted branch (outcome & target)"}, #define PME_ITA2_BR_MISPRED_DETAIL2_ALL_UNKNOWN_PATH_WRONG_PATH 74 { "BR_MISPRED_DETAIL2_ALL_UNKNOWN_PATH_WRONG_PATH", {0x20068}, 0xf0, 2, {0xf00003}, "FE Branch Mispredict Detail (Unknown Path Component) -- All branch types, branches with unknown path prediction and wrong branch direction"}, #define PME_ITA2_BR_MISPRED_DETAIL2_IPREL_ALL_UNKNOWN_PRED 75 { "BR_MISPRED_DETAIL2_IPREL_ALL_UNKNOWN_PRED", {0x40068}, 0xf0, 2, {0xf00003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only IP relative branches, branches with unknown path prediction"}, #define PME_ITA2_BR_MISPRED_DETAIL2_IPREL_UNKNOWN_PATH_CORRECT_PRED 76 { "BR_MISPRED_DETAIL2_IPREL_UNKNOWN_PATH_CORRECT_PRED", {0x50068}, 0xf0, 2, {0xf00003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only IP relative branches, branches with unknown path prediction and correct predicted branch (outcome & target)"}, #define PME_ITA2_BR_MISPRED_DETAIL2_IPREL_UNKNOWN_PATH_WRONG_PATH 77 { "BR_MISPRED_DETAIL2_IPREL_UNKNOWN_PATH_WRONG_PATH", {0x60068}, 0xf0, 2, {0xf00003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only IP relative branches, branches with unknown path prediction and wrong branch direction"}, #define PME_ITA2_BR_MISPRED_DETAIL2_NRETIND_ALL_UNKNOWN_PRED 78 { "BR_MISPRED_DETAIL2_NRETIND_ALL_UNKNOWN_PRED", {0xc0068}, 0xf0, 2, {0xf00003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only non-return indirect branches, branches with unknown path prediction"}, #define PME_ITA2_BR_MISPRED_DETAIL2_NRETIND_UNKNOWN_PATH_CORRECT_PRED 79 { "BR_MISPRED_DETAIL2_NRETIND_UNKNOWN_PATH_CORRECT_PRED", {0xd0068}, 0xf0, 2, {0xf00003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only non-return indirect branches, branches with unknown path prediction and correct predicted branch (outcome & target)"}, #define PME_ITA2_BR_MISPRED_DETAIL2_NRETIND_UNKNOWN_PATH_WRONG_PATH 80 { "BR_MISPRED_DETAIL2_NRETIND_UNKNOWN_PATH_WRONG_PATH", {0xe0068}, 0xf0, 2, {0xf00003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only non-return indirect branches, branches with unknown path prediction and wrong branch direction"}, #define PME_ITA2_BR_MISPRED_DETAIL2_RETURN_ALL_UNKNOWN_PRED 81 { "BR_MISPRED_DETAIL2_RETURN_ALL_UNKNOWN_PRED", {0x80068}, 0xf0, 2, {0xf00003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only return type branches, branches with unknown path prediction"}, #define PME_ITA2_BR_MISPRED_DETAIL2_RETURN_UNKNOWN_PATH_CORRECT_PRED 82 { "BR_MISPRED_DETAIL2_RETURN_UNKNOWN_PATH_CORRECT_PRED", {0x90068}, 0xf0, 2, {0xf00003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only return type branches, branches with unknown path prediction and correct predicted branch (outcome & target)"}, #define PME_ITA2_BR_MISPRED_DETAIL2_RETURN_UNKNOWN_PATH_WRONG_PATH 83 { "BR_MISPRED_DETAIL2_RETURN_UNKNOWN_PATH_WRONG_PATH", {0xa0068}, 0xf0, 2, {0xf00003}, "FE Branch Mispredict Detail (Unknown Path Component) -- Only return type branches, branches with unknown path prediction and wrong branch direction"}, #define PME_ITA2_BR_PATH_PRED_ALL_MISPRED_NOTTAKEN 84 { "BR_PATH_PRED_ALL_MISPRED_NOTTAKEN", {0x54}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- All branch types, incorrectly predicted path and not taken branch"}, #define PME_ITA2_BR_PATH_PRED_ALL_MISPRED_TAKEN 85 { "BR_PATH_PRED_ALL_MISPRED_TAKEN", {0x10054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- All branch types, incorrectly predicted path and taken branch"}, #define PME_ITA2_BR_PATH_PRED_ALL_OKPRED_NOTTAKEN 86 { "BR_PATH_PRED_ALL_OKPRED_NOTTAKEN", {0x20054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- All branch types, correctly predicted path and not taken branch"}, #define PME_ITA2_BR_PATH_PRED_ALL_OKPRED_TAKEN 87 { "BR_PATH_PRED_ALL_OKPRED_TAKEN", {0x30054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- All branch types, correctly predicted path and taken branch"}, #define PME_ITA2_BR_PATH_PRED_IPREL_MISPRED_NOTTAKEN 88 { "BR_PATH_PRED_IPREL_MISPRED_NOTTAKEN", {0x40054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- Only IP relative branches, incorrectly predicted path and not taken branch"}, #define PME_ITA2_BR_PATH_PRED_IPREL_MISPRED_TAKEN 89 { "BR_PATH_PRED_IPREL_MISPRED_TAKEN", {0x50054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- Only IP relative branches, incorrectly predicted path and taken branch"}, #define PME_ITA2_BR_PATH_PRED_IPREL_OKPRED_NOTTAKEN 90 { "BR_PATH_PRED_IPREL_OKPRED_NOTTAKEN", {0x60054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- Only IP relative branches, correctly predicted path and not taken branch"}, #define PME_ITA2_BR_PATH_PRED_IPREL_OKPRED_TAKEN 91 { "BR_PATH_PRED_IPREL_OKPRED_TAKEN", {0x70054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- Only IP relative branches, correctly predicted path and taken branch"}, #define PME_ITA2_BR_PATH_PRED_NRETIND_MISPRED_NOTTAKEN 92 { "BR_PATH_PRED_NRETIND_MISPRED_NOTTAKEN", {0xc0054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- Only non-return indirect branches, incorrectly predicted path and not taken branch"}, #define PME_ITA2_BR_PATH_PRED_NRETIND_MISPRED_TAKEN 93 { "BR_PATH_PRED_NRETIND_MISPRED_TAKEN", {0xd0054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- Only non-return indirect branches, incorrectly predicted path and taken branch"}, #define PME_ITA2_BR_PATH_PRED_NRETIND_OKPRED_NOTTAKEN 94 { "BR_PATH_PRED_NRETIND_OKPRED_NOTTAKEN", {0xe0054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- Only non-return indirect branches, correctly predicted path and not taken branch"}, #define PME_ITA2_BR_PATH_PRED_NRETIND_OKPRED_TAKEN 95 { "BR_PATH_PRED_NRETIND_OKPRED_TAKEN", {0xf0054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- Only non-return indirect branches, correctly predicted path and taken branch"}, #define PME_ITA2_BR_PATH_PRED_RETURN_MISPRED_NOTTAKEN 96 { "BR_PATH_PRED_RETURN_MISPRED_NOTTAKEN", {0x80054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- Only return type branches, incorrectly predicted path and not taken branch"}, #define PME_ITA2_BR_PATH_PRED_RETURN_MISPRED_TAKEN 97 { "BR_PATH_PRED_RETURN_MISPRED_TAKEN", {0x90054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- Only return type branches, incorrectly predicted path and taken branch"}, #define PME_ITA2_BR_PATH_PRED_RETURN_OKPRED_NOTTAKEN 98 { "BR_PATH_PRED_RETURN_OKPRED_NOTTAKEN", {0xa0054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- Only return type branches, correctly predicted path and not taken branch"}, #define PME_ITA2_BR_PATH_PRED_RETURN_OKPRED_TAKEN 99 { "BR_PATH_PRED_RETURN_OKPRED_TAKEN", {0xb0054}, 0xf0, 3, {0xf00003}, "FE Branch Path Prediction Detail -- Only return type branches, correctly predicted path and taken branch"}, #define PME_ITA2_BR_PATH_PRED2_ALL_UNKNOWNPRED_NOTTAKEN 100 { "BR_PATH_PRED2_ALL_UNKNOWNPRED_NOTTAKEN", {0x6a}, 0xf0, 2, {0xf00003}, "FE Branch Path Prediction Detail (Unknown pred component) -- All branch types, unknown predicted path and not taken branch (which impacts OKPRED_NOTTAKEN)"}, #define PME_ITA2_BR_PATH_PRED2_ALL_UNKNOWNPRED_TAKEN 101 { "BR_PATH_PRED2_ALL_UNKNOWNPRED_TAKEN", {0x1006a}, 0xf0, 2, {0xf00003}, "FE Branch Path Prediction Detail (Unknown pred component) -- All branch types, unknown predicted path and taken branch (which impacts MISPRED_TAKEN)"}, #define PME_ITA2_BR_PATH_PRED2_IPREL_UNKNOWNPRED_NOTTAKEN 102 { "BR_PATH_PRED2_IPREL_UNKNOWNPRED_NOTTAKEN", {0x4006a}, 0xf0, 2, {0xf00003}, "FE Branch Path Prediction Detail (Unknown pred component) -- Only IP relative branches, unknown predicted path and not taken branch (which impacts OKPRED_NOTTAKEN)"}, #define PME_ITA2_BR_PATH_PRED2_IPREL_UNKNOWNPRED_TAKEN 103 { "BR_PATH_PRED2_IPREL_UNKNOWNPRED_TAKEN", {0x5006a}, 0xf0, 2, {0xf00003}, "FE Branch Path Prediction Detail (Unknown pred component) -- Only IP relative branches, unknown predicted path and taken branch (which impacts MISPRED_TAKEN)"}, #define PME_ITA2_BR_PATH_PRED2_NRETIND_UNKNOWNPRED_NOTTAKEN 104 { "BR_PATH_PRED2_NRETIND_UNKNOWNPRED_NOTTAKEN", {0xc006a}, 0xf0, 2, {0xf00003}, "FE Branch Path Prediction Detail (Unknown pred component) -- Only non-return indirect branches, unknown predicted path and not taken branch (which impacts OKPRED_NOTTAKEN)"}, #define PME_ITA2_BR_PATH_PRED2_NRETIND_UNKNOWNPRED_TAKEN 105 { "BR_PATH_PRED2_NRETIND_UNKNOWNPRED_TAKEN", {0xd006a}, 0xf0, 2, {0xf00003}, "FE Branch Path Prediction Detail (Unknown pred component) -- Only non-return indirect branches, unknown predicted path and taken branch (which impacts MISPRED_TAKEN)"}, #define PME_ITA2_BR_PATH_PRED2_RETURN_UNKNOWNPRED_NOTTAKEN 106 { "BR_PATH_PRED2_RETURN_UNKNOWNPRED_NOTTAKEN", {0x8006a}, 0xf0, 2, {0xf00003}, "FE Branch Path Prediction Detail (Unknown pred component) -- Only return type branches, unknown predicted path and not taken branch (which impacts OKPRED_NOTTAKEN)"}, #define PME_ITA2_BR_PATH_PRED2_RETURN_UNKNOWNPRED_TAKEN 107 { "BR_PATH_PRED2_RETURN_UNKNOWNPRED_TAKEN", {0x9006a}, 0xf0, 2, {0xf00003}, "FE Branch Path Prediction Detail (Unknown pred component) -- Only return type branches, unknown predicted path and taken branch (which impacts MISPRED_TAKEN)"}, #define PME_ITA2_BUS_ALL_ANY 108 { "BUS_ALL_ANY", {0x30087}, 0xf0, 1, {0xf00000}, "Bus Transactions -- CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_ALL_IO 109 { "BUS_ALL_IO", {0x10087}, 0xf0, 1, {0xf00000}, "Bus Transactions -- non-CPU priority agents"}, #define PME_ITA2_BUS_ALL_SELF 110 { "BUS_ALL_SELF", {0x20087}, 0xf0, 1, {0xf00000}, "Bus Transactions -- local processor"}, #define PME_ITA2_BUS_BACKSNP_REQ_THIS 111 { "BUS_BACKSNP_REQ_THIS", {0x1008e}, 0xf0, 1, {0xf00000}, "Bus Back Snoop Requests -- Counts the number of bus back snoop me requests"}, #define PME_ITA2_BUS_BRQ_LIVE_REQ_HI 112 { "BUS_BRQ_LIVE_REQ_HI", {0x9c}, 0xf0, 2, {0xf00000}, "BRQ Live Requests (upper 2 bits)"}, #define PME_ITA2_BUS_BRQ_LIVE_REQ_LO 113 { "BUS_BRQ_LIVE_REQ_LO", {0x9b}, 0xf0, 7, {0xf00000}, "BRQ Live Requests (lower 3 bits)"}, #define PME_ITA2_BUS_BRQ_REQ_INSERTED 114 { "BUS_BRQ_REQ_INSERTED", {0x9d}, 0xf0, 1, {0xf00000}, "BRQ Requests Inserted"}, #define PME_ITA2_BUS_DATA_CYCLE 115 { "BUS_DATA_CYCLE", {0x88}, 0xf0, 1, {0xf00000}, "Valid Data Cycle on the Bus"}, #define PME_ITA2_BUS_HITM 116 { "BUS_HITM", {0x84}, 0xf0, 1, {0xf00000}, "Bus Hit Modified Line Transactions"}, #define PME_ITA2_BUS_IO_ANY 117 { "BUS_IO_ANY", {0x30090}, 0xf0, 1, {0xf00000}, "IA-32 Compatible IO Bus Transactions -- CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_IO_IO 118 { "BUS_IO_IO", {0x10090}, 0xf0, 1, {0xf00000}, "IA-32 Compatible IO Bus Transactions -- non-CPU priority agents"}, #define PME_ITA2_BUS_IO_SELF 119 { "BUS_IO_SELF", {0x20090}, 0xf0, 1, {0xf00000}, "IA-32 Compatible IO Bus Transactions -- local processor"}, #define PME_ITA2_BUS_IOQ_LIVE_REQ_HI 120 { "BUS_IOQ_LIVE_REQ_HI", {0x98}, 0xf0, 2, {0xf00000}, "Inorder Bus Queue Requests (upper 2 bits)"}, #define PME_ITA2_BUS_IOQ_LIVE_REQ_LO 121 { "BUS_IOQ_LIVE_REQ_LO", {0x97}, 0xf0, 3, {0xf00000}, "Inorder Bus Queue Requests (lower2 bitst)"}, #define PME_ITA2_BUS_LOCK_ANY 122 { "BUS_LOCK_ANY", {0x30093}, 0xf0, 1, {0xf00000}, "IA-32 Compatible Bus Lock Transactions -- CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_LOCK_SELF 123 { "BUS_LOCK_SELF", {0x20093}, 0xf0, 1, {0xf00000}, "IA-32 Compatible Bus Lock Transactions -- local processor"}, #define PME_ITA2_BUS_MEMORY_ALL_ANY 124 { "BUS_MEMORY_ALL_ANY", {0xf008a}, 0xf0, 1, {0xf00000}, "Bus Memory Transactions -- All bus transactions from CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_MEMORY_ALL_IO 125 { "BUS_MEMORY_ALL_IO", {0xd008a}, 0xf0, 1, {0xf00000}, "Bus Memory Transactions -- All bus transactions from non-CPU priority agents"}, #define PME_ITA2_BUS_MEMORY_ALL_SELF 126 { "BUS_MEMORY_ALL_SELF", {0xe008a}, 0xf0, 1, {0xf00000}, "Bus Memory Transactions -- All bus transactions from local processor"}, #define PME_ITA2_BUS_MEMORY_EQ_128BYTE_ANY 127 { "BUS_MEMORY_EQ_128BYTE_ANY", {0x7008a}, 0xf0, 1, {0xf00000}, "Bus Memory Transactions -- number of full cache line transactions (BRL, BRIL, BWL) from CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_MEMORY_EQ_128BYTE_IO 128 { "BUS_MEMORY_EQ_128BYTE_IO", {0x5008a}, 0xf0, 1, {0xf00000}, "Bus Memory Transactions -- number of full cache line transactions (BRL, BRIL, BWL) from non-CPU priority agents"}, #define PME_ITA2_BUS_MEMORY_EQ_128BYTE_SELF 129 { "BUS_MEMORY_EQ_128BYTE_SELF", {0x6008a}, 0xf0, 1, {0xf00000}, "Bus Memory Transactions -- number of full cache line transactions (BRL, BRIL, BWL) from local processor"}, #define PME_ITA2_BUS_MEMORY_LT_128BYTE_ANY 130 { "BUS_MEMORY_LT_128BYTE_ANY", {0xb008a}, 0xf0, 1, {0xf00000}, "Bus Memory Transactions -- number of less than full cache line transactions (BRP, BWP) CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_MEMORY_LT_128BYTE_IO 131 { "BUS_MEMORY_LT_128BYTE_IO", {0x9008a}, 0xf0, 1, {0xf00000}, "Bus Memory Transactions -- number of less than full cache line transactions (BRP, BWP) from non-CPU priority agents"}, #define PME_ITA2_BUS_MEMORY_LT_128BYTE_SELF 132 { "BUS_MEMORY_LT_128BYTE_SELF", {0xa008a}, 0xf0, 1, {0xf00000}, "Bus Memory Transactions -- number of less than full cache line transactions (BRP, BWP) local processor"}, #define PME_ITA2_BUS_MEM_READ_ALL_ANY 133 { "BUS_MEM_READ_ALL_ANY", {0xf008b}, 0xf0, 1, {0xf00000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- All memory read transactions from CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_MEM_READ_ALL_IO 134 { "BUS_MEM_READ_ALL_IO", {0xd008b}, 0xf0, 1, {0xf00000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- All memory read transactions from non-CPU priority agents"}, #define PME_ITA2_BUS_MEM_READ_ALL_SELF 135 { "BUS_MEM_READ_ALL_SELF", {0xe008b}, 0xf0, 1, {0xf00000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- All memory read transactions from local processor"}, #define PME_ITA2_BUS_MEM_READ_BIL_ANY 136 { "BUS_MEM_READ_BIL_ANY", {0x3008b}, 0xf0, 1, {0xf00000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of BIL 0-byte memory read invalidate transactions from CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_MEM_READ_BIL_IO 137 { "BUS_MEM_READ_BIL_IO", {0x1008b}, 0xf0, 1, {0xf00000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of BIL 0-byte memory read invalidate transactions from non-CPU priority agents"}, #define PME_ITA2_BUS_MEM_READ_BIL_SELF 138 { "BUS_MEM_READ_BIL_SELF", {0x2008b}, 0xf0, 1, {0xf00000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of BIL 0-byte memory read invalidate transactions from local processor"}, #define PME_ITA2_BUS_MEM_READ_BRIL_ANY 139 { "BUS_MEM_READ_BRIL_ANY", {0xb008b}, 0xf0, 1, {0xf00000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read invalidate transactions from CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_MEM_READ_BRIL_IO 140 { "BUS_MEM_READ_BRIL_IO", {0x9008b}, 0xf0, 1, {0xf00000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read invalidate transactions from non-CPU priority agents"}, #define PME_ITA2_BUS_MEM_READ_BRIL_SELF 141 { "BUS_MEM_READ_BRIL_SELF", {0xa008b}, 0xf0, 1, {0xf00000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read invalidate transactions from local processor"}, #define PME_ITA2_BUS_MEM_READ_BRL_ANY 142 { "BUS_MEM_READ_BRL_ANY", {0x7008b}, 0xf0, 1, {0xf00000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read transactions from CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_MEM_READ_BRL_IO 143 { "BUS_MEM_READ_BRL_IO", {0x5008b}, 0xf0, 1, {0xf00000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read transactions from non-CPU priority agents"}, #define PME_ITA2_BUS_MEM_READ_BRL_SELF 144 { "BUS_MEM_READ_BRL_SELF", {0x6008b}, 0xf0, 1, {0xf00000}, "Full Cache Line D/I Memory RD, RD Invalidate, and BRIL -- Number of full cache line memory read transactions from local processor"}, #define PME_ITA2_BUS_MEM_READ_OUT_HI 145 { "BUS_MEM_READ_OUT_HI", {0x94}, 0xf0, 2, {0xf00000}, "Outstanding Memory Read Transactions (upper 2 bits)"}, #define PME_ITA2_BUS_MEM_READ_OUT_LO 146 { "BUS_MEM_READ_OUT_LO", {0x95}, 0xf0, 7, {0xf00000}, "Outstanding Memory Read Transactions (lower 3 bits)"}, #define PME_ITA2_BUS_OOQ_LIVE_REQ_HI 147 { "BUS_OOQ_LIVE_REQ_HI", {0x9a}, 0xf0, 2, {0xf00000}, "Out-of-order Bus Queue Requests (upper 2 bits)"}, #define PME_ITA2_BUS_OOQ_LIVE_REQ_LO 148 { "BUS_OOQ_LIVE_REQ_LO", {0x99}, 0xf0, 7, {0xf00000}, "Out-of-order Bus Queue Requests (lower 3 bits)"}, #define PME_ITA2_BUS_RD_DATA_ANY 149 { "BUS_RD_DATA_ANY", {0x3008c}, 0xf0, 1, {0xf00000}, "Bus Read Data Transactions -- CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_RD_DATA_IO 150 { "BUS_RD_DATA_IO", {0x1008c}, 0xf0, 1, {0xf00000}, "Bus Read Data Transactions -- non-CPU priority agents"}, #define PME_ITA2_BUS_RD_DATA_SELF 151 { "BUS_RD_DATA_SELF", {0x2008c}, 0xf0, 1, {0xf00000}, "Bus Read Data Transactions -- local processor"}, #define PME_ITA2_BUS_RD_HIT 152 { "BUS_RD_HIT", {0x80}, 0xf0, 1, {0xf00000}, "Bus Read Hit Clean Non-local Cache Transactions"}, #define PME_ITA2_BUS_RD_HITM 153 { "BUS_RD_HITM", {0x81}, 0xf0, 1, {0xf00000}, "Bus Read Hit Modified Non-local Cache Transactions"}, #define PME_ITA2_BUS_RD_INVAL_ALL_HITM 154 { "BUS_RD_INVAL_ALL_HITM", {0x83}, 0xf0, 1, {0xf00000}, "Bus BRIL Burst Transaction Results in HITM"}, #define PME_ITA2_BUS_RD_INVAL_HITM 155 { "BUS_RD_INVAL_HITM", {0x82}, 0xf0, 1, {0xf00000}, "Bus BIL Transaction Results in HITM"}, #define PME_ITA2_BUS_RD_IO_ANY 156 { "BUS_RD_IO_ANY", {0x30091}, 0xf0, 1, {0xf00000}, "IA-32 Compatible IO Read Transactions -- CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_RD_IO_IO 157 { "BUS_RD_IO_IO", {0x10091}, 0xf0, 1, {0xf00000}, "IA-32 Compatible IO Read Transactions -- non-CPU priority agents"}, #define PME_ITA2_BUS_RD_IO_SELF 158 { "BUS_RD_IO_SELF", {0x20091}, 0xf0, 1, {0xf00000}, "IA-32 Compatible IO Read Transactions -- local processor"}, #define PME_ITA2_BUS_RD_PRTL_ANY 159 { "BUS_RD_PRTL_ANY", {0x3008d}, 0xf0, 1, {0xf00000}, "Bus Read Partial Transactions -- CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_RD_PRTL_IO 160 { "BUS_RD_PRTL_IO", {0x1008d}, 0xf0, 1, {0xf00000}, "Bus Read Partial Transactions -- non-CPU priority agents"}, #define PME_ITA2_BUS_RD_PRTL_SELF 161 { "BUS_RD_PRTL_SELF", {0x2008d}, 0xf0, 1, {0xf00000}, "Bus Read Partial Transactions -- local processor"}, #define PME_ITA2_BUS_SNOOPQ_REQ 162 { "BUS_SNOOPQ_REQ", {0x96}, 0xf0, 7, {0xf00000}, "Bus Snoop Queue Requests"}, #define PME_ITA2_BUS_SNOOPS_ANY 163 { "BUS_SNOOPS_ANY", {0x30086}, 0xf0, 1, {0xf00000}, "Bus Snoops Total -- CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_SNOOPS_IO 164 { "BUS_SNOOPS_IO", {0x10086}, 0xf0, 1, {0xf00000}, "Bus Snoops Total -- non-CPU priority agents"}, #define PME_ITA2_BUS_SNOOPS_SELF 165 { "BUS_SNOOPS_SELF", {0x20086}, 0xf0, 1, {0xf00000}, "Bus Snoops Total -- local processor"}, #define PME_ITA2_BUS_SNOOPS_HITM_ANY 166 { "BUS_SNOOPS_HITM_ANY", {0x30085}, 0xf0, 1, {0xf00000}, "Bus Snoops HIT Modified Cache Line -- CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_SNOOPS_HITM_SELF 167 { "BUS_SNOOPS_HITM_SELF", {0x20085}, 0xf0, 1, {0xf00000}, "Bus Snoops HIT Modified Cache Line -- local processor"}, #define PME_ITA2_BUS_SNOOP_STALL_CYCLES_ANY 168 { "BUS_SNOOP_STALL_CYCLES_ANY", {0x3008f}, 0xf0, 1, {0xf00000}, "Bus Snoop Stall Cycles (from any agent) -- CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_SNOOP_STALL_CYCLES_SELF 169 { "BUS_SNOOP_STALL_CYCLES_SELF", {0x2008f}, 0xf0, 1, {0xf00000}, "Bus Snoop Stall Cycles (from any agent) -- local processor"}, #define PME_ITA2_BUS_WR_WB_ALL_ANY 170 { "BUS_WR_WB_ALL_ANY", {0xf0092}, 0xf0, 1, {0xf00000}, "Bus Write Back Transactions -- CPU or non-CPU (all transactions)."}, #define PME_ITA2_BUS_WR_WB_ALL_IO 171 { "BUS_WR_WB_ALL_IO", {0xd0092}, 0xf0, 1, {0xf00000}, "Bus Write Back Transactions -- non-CPU priority agents"}, #define PME_ITA2_BUS_WR_WB_ALL_SELF 172 { "BUS_WR_WB_ALL_SELF", {0xe0092}, 0xf0, 1, {0xf00000}, "Bus Write Back Transactions -- local processor"}, #define PME_ITA2_BUS_WR_WB_CCASTOUT_ANY 173 { "BUS_WR_WB_CCASTOUT_ANY", {0xb0092}, 0xf0, 1, {0xf00000}, "Bus Write Back Transactions -- CPU or non-CPU (all transactions)/Only 0-byte transactions with write back attribute (clean cast outs) will be counted"}, #define PME_ITA2_BUS_WR_WB_CCASTOUT_SELF 174 { "BUS_WR_WB_CCASTOUT_SELF", {0xa0092}, 0xf0, 1, {0xf00000}, "Bus Write Back Transactions -- local processor/Only 0-byte transactions with write back attribute (clean cast outs) will be counted"}, #define PME_ITA2_BUS_WR_WB_EQ_128BYTE_ANY 175 { "BUS_WR_WB_EQ_128BYTE_ANY", {0x70092}, 0xf0, 1, {0xf00000}, "Bus Write Back Transactions -- CPU or non-CPU (all transactions)./Only cache line transactions with write back or write coalesce attributes will be counted."}, #define PME_ITA2_BUS_WR_WB_EQ_128BYTE_IO 176 { "BUS_WR_WB_EQ_128BYTE_IO", {0x50092}, 0xf0, 1, {0xf00000}, "Bus Write Back Transactions -- non-CPU priority agents/Only cache line transactions with write back or write coalesce attributes will be counted."}, #define PME_ITA2_BUS_WR_WB_EQ_128BYTE_SELF 177 { "BUS_WR_WB_EQ_128BYTE_SELF", {0x60092}, 0xf0, 1, {0xf00000}, "Bus Write Back Transactions -- local processor/Only cache line transactions with write back or write coalesce attributes will be counted."}, #define PME_ITA2_CPU_CPL_CHANGES 178 { "CPU_CPL_CHANGES", {0x13}, 0xf0, 1, {0xf00000}, "Privilege Level Changes"}, #define PME_ITA2_CPU_CYCLES 179 { "CPU_CYCLES", {0x12}, 0xf0, 1, {0xf00000}, "CPU Cycles"}, #define PME_ITA2_DATA_DEBUG_REGISTER_FAULT 180 { "DATA_DEBUG_REGISTER_FAULT", {0x52}, 0xf0, 1, {0xf00000}, "Fault Due to Data Debug Reg. Match to Load/Store Instruction"}, #define PME_ITA2_DATA_DEBUG_REGISTER_MATCHES 181 { "DATA_DEBUG_REGISTER_MATCHES", {0xc6}, 0xf0, 1, {0xf00007}, "Data Debug Register Matches Data Address of Memory Reference."}, #define PME_ITA2_DATA_EAR_ALAT 182 { "DATA_EAR_ALAT", {0x6c8}, 0xf0, 1, {0xf00007}, "Data EAR ALAT"}, #define PME_ITA2_DATA_EAR_CACHE_LAT1024 183 { "DATA_EAR_CACHE_LAT1024", {0x805c8}, 0xf0, 1, {0xf00007}, "Data EAR Cache -- >= 1024 Cycles"}, #define PME_ITA2_DATA_EAR_CACHE_LAT128 184 { "DATA_EAR_CACHE_LAT128", {0x505c8}, 0xf0, 1, {0xf00007}, "Data EAR Cache -- >= 128 Cycles"}, #define PME_ITA2_DATA_EAR_CACHE_LAT16 185 { "DATA_EAR_CACHE_LAT16", {0x205c8}, 0xf0, 1, {0xf00007}, "Data EAR Cache -- >= 16 Cycles"}, #define PME_ITA2_DATA_EAR_CACHE_LAT2048 186 { "DATA_EAR_CACHE_LAT2048", {0x905c8}, 0xf0, 1, {0xf00007}, "Data EAR Cache -- >= 2048 Cycles"}, #define PME_ITA2_DATA_EAR_CACHE_LAT256 187 { "DATA_EAR_CACHE_LAT256", {0x605c8}, 0xf0, 1, {0xf00007}, "Data EAR Cache -- >= 256 Cycles"}, #define PME_ITA2_DATA_EAR_CACHE_LAT32 188 { "DATA_EAR_CACHE_LAT32", {0x305c8}, 0xf0, 1, {0xf00007}, "Data EAR Cache -- >= 32 Cycles"}, #define PME_ITA2_DATA_EAR_CACHE_LAT4 189 { "DATA_EAR_CACHE_LAT4", {0x5c8}, 0xf0, 1, {0xf00007}, "Data EAR Cache -- >= 4 Cycles"}, #define PME_ITA2_DATA_EAR_CACHE_LAT4096 190 { "DATA_EAR_CACHE_LAT4096", {0xa05c8}, 0xf0, 1, {0xf00007}, "Data EAR Cache -- >= 4096 Cycles"}, #define PME_ITA2_DATA_EAR_CACHE_LAT512 191 { "DATA_EAR_CACHE_LAT512", {0x705c8}, 0xf0, 1, {0xf00007}, "Data EAR Cache -- >= 512 Cycles"}, #define PME_ITA2_DATA_EAR_CACHE_LAT64 192 { "DATA_EAR_CACHE_LAT64", {0x405c8}, 0xf0, 1, {0xf00007}, "Data EAR Cache -- >= 64 Cycles"}, #define PME_ITA2_DATA_EAR_CACHE_LAT8 193 { "DATA_EAR_CACHE_LAT8", {0x105c8}, 0xf0, 1, {0xf00007}, "Data EAR Cache -- >= 8 Cycles"}, #define PME_ITA2_DATA_EAR_EVENTS 194 { "DATA_EAR_EVENTS", {0xc8}, 0xf0, 1, {0xf00007}, "L1 Data Cache EAR Events"}, #define PME_ITA2_DATA_EAR_TLB_ALL 195 { "DATA_EAR_TLB_ALL", {0xe04c8}, 0xf0, 1, {0xf00007}, "Data EAR TLB -- All L1 DTLB Misses"}, #define PME_ITA2_DATA_EAR_TLB_FAULT 196 { "DATA_EAR_TLB_FAULT", {0x804c8}, 0xf0, 1, {0xf00007}, "Data EAR TLB -- DTLB Misses which produce a software fault"}, #define PME_ITA2_DATA_EAR_TLB_L2DTLB 197 { "DATA_EAR_TLB_L2DTLB", {0x204c8}, 0xf0, 1, {0xf00007}, "Data EAR TLB -- L1 DTLB Misses which hit L2 DTLB"}, #define PME_ITA2_DATA_EAR_TLB_L2DTLB_OR_FAULT 198 { "DATA_EAR_TLB_L2DTLB_OR_FAULT", {0xa04c8}, 0xf0, 1, {0xf00007}, "Data EAR TLB -- L1 DTLB Misses which hit L2 DTLB or produce a software fault"}, #define PME_ITA2_DATA_EAR_TLB_L2DTLB_OR_VHPT 199 { "DATA_EAR_TLB_L2DTLB_OR_VHPT", {0x604c8}, 0xf0, 1, {0xf00007}, "Data EAR TLB -- L1 DTLB Misses which hit L2 DTLB or VHPT"}, #define PME_ITA2_DATA_EAR_TLB_VHPT 200 { "DATA_EAR_TLB_VHPT", {0x404c8}, 0xf0, 1, {0xf00007}, "Data EAR TLB -- L1 DTLB Misses which hit VHPT"}, #define PME_ITA2_DATA_EAR_TLB_VHPT_OR_FAULT 201 { "DATA_EAR_TLB_VHPT_OR_FAULT", {0xc04c8}, 0xf0, 1, {0xf00007}, "Data EAR TLB -- L1 DTLB Misses which hit VHPT or produce a software fault"}, #define PME_ITA2_DATA_REFERENCES_SET0 202 { "DATA_REFERENCES_SET0", {0xc3}, 0xf0, 4, {0x5010007}, "Data Memory References Issued to Memory Pipeline"}, #define PME_ITA2_DATA_REFERENCES_SET1 203 { "DATA_REFERENCES_SET1", {0xc5}, 0xf0, 4, {0x5110007}, "Data Memory References Issued to Memory Pipeline"}, #define PME_ITA2_DISP_STALLED 204 { "DISP_STALLED", {0x49}, 0xf0, 1, {0xf00000}, "Number of Cycles Dispersal Stalled"}, #define PME_ITA2_DTLB_INSERTS_HPW 205 { "DTLB_INSERTS_HPW", {0xc9}, 0xf0, 4, {0xf00007}, "Hardware Page Walker Installs to DTLB"}, #define PME_ITA2_DTLB_INSERTS_HPW_RETIRED 206 { "DTLB_INSERTS_HPW_RETIRED", {0x2c}, 0xf0, 4, {0xf00007}, "VHPT Entries Inserted into DTLB by the Hardware Page Walker"}, #define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL_ALL_PRED 207 { "ENCBR_MISPRED_DETAIL_ALL_ALL_PRED", {0x63}, 0xf0, 3, {0xf00003}, "Number of Encoded Branches Retired -- All encoded branches regardless of prediction result"}, #define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL_CORRECT_PRED 208 { "ENCBR_MISPRED_DETAIL_ALL_CORRECT_PRED", {0x10063}, 0xf0, 3, {0xf00003}, "Number of Encoded Branches Retired -- All encoded branches, correctly predicted branches (outcome and target)"}, #define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL_WRONG_PATH 209 { "ENCBR_MISPRED_DETAIL_ALL_WRONG_PATH", {0x20063}, 0xf0, 3, {0xf00003}, "Number of Encoded Branches Retired -- All encoded branches, mispredicted branches due to wrong branch direction"}, #define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL_WRONG_TARGET 210 { "ENCBR_MISPRED_DETAIL_ALL_WRONG_TARGET", {0x30063}, 0xf0, 3, {0xf00003}, "Number of Encoded Branches Retired -- All encoded branches, mispredicted branches due to wrong target for taken branches"}, #define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL2_ALL_PRED 211 { "ENCBR_MISPRED_DETAIL_ALL2_ALL_PRED", {0xc0063}, 0xf0, 3, {0xf00003}, "Number of Encoded Branches Retired -- Only non-return indirect branches, regardless of prediction result"}, #define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL2_CORRECT_PRED 212 { "ENCBR_MISPRED_DETAIL_ALL2_CORRECT_PRED", {0xd0063}, 0xf0, 3, {0xf00003}, "Number of Encoded Branches Retired -- Only non-return indirect branches, correctly predicted branches (outcome and target)"}, #define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL2_WRONG_PATH 213 { "ENCBR_MISPRED_DETAIL_ALL2_WRONG_PATH", {0xe0063}, 0xf0, 3, {0xf00003}, "Number of Encoded Branches Retired -- Only non-return indirect branches, mispredicted branches due to wrong branch direction"}, #define PME_ITA2_ENCBR_MISPRED_DETAIL_ALL2_WRONG_TARGET 214 { "ENCBR_MISPRED_DETAIL_ALL2_WRONG_TARGET", {0xf0063}, 0xf0, 3, {0xf00003}, "Number of Encoded Branches Retired -- Only non-return indirect branches, mispredicted branches due to wrong target for taken branches"}, #define PME_ITA2_ENCBR_MISPRED_DETAIL_OVERSUB_ALL_PRED 215 { "ENCBR_MISPRED_DETAIL_OVERSUB_ALL_PRED", {0x80063}, 0xf0, 3, {0xf00003}, "Number of Encoded Branches Retired -- Only return type branches, regardless of prediction result"}, #define PME_ITA2_ENCBR_MISPRED_DETAIL_OVERSUB_CORRECT_PRED 216 { "ENCBR_MISPRED_DETAIL_OVERSUB_CORRECT_PRED", {0x90063}, 0xf0, 3, {0xf00003}, "Number of Encoded Branches Retired -- Only return type branches, correctly predicted branches (outcome and target)"}, #define PME_ITA2_ENCBR_MISPRED_DETAIL_OVERSUB_WRONG_PATH 217 { "ENCBR_MISPRED_DETAIL_OVERSUB_WRONG_PATH", {0xa0063}, 0xf0, 3, {0xf00003}, "Number of Encoded Branches Retired -- Only return type branches, mispredicted branches due to wrong branch direction"}, #define PME_ITA2_ENCBR_MISPRED_DETAIL_OVERSUB_WRONG_TARGET 218 { "ENCBR_MISPRED_DETAIL_OVERSUB_WRONG_TARGET", {0xb0063}, 0xf0, 3, {0xf00003}, "Number of Encoded Branches Retired -- Only return type branches, mispredicted branches due to wrong target for taken branches"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_ALL 219 { "EXTERN_DP_PINS_0_TO_3_ALL", {0xf009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin3 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0 220 { "EXTERN_DP_PINS_0_TO_3_PIN0", {0x1009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin0 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1 221 { "EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1", {0x3009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin0 or pin1 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1_OR_PIN2 222 { "EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1_OR_PIN2", {0x7009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin0 or pin1 or pin2 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1_OR_PIN3 223 { "EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1_OR_PIN3", {0xb009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin0 or pin1 or pin3 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN2 224 { "EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN2", {0x5009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin0 or pin2 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN2_OR_PIN3 225 { "EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN2_OR_PIN3", {0xd009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin0 or pin2 or pin3 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN3 226 { "EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN3", {0x9009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin0 or pin3 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN1 227 { "EXTERN_DP_PINS_0_TO_3_PIN1", {0x2009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin1 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN2 228 { "EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN2", {0x6009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin1 or pin2 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN2_OR_PIN3 229 { "EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN2_OR_PIN3", {0xe009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin1 or pin2 or pin3 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN3 230 { "EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN3", {0xa009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin1 or pin3 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN2 231 { "EXTERN_DP_PINS_0_TO_3_PIN2", {0x4009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin2 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN2_OR_PIN3 232 { "EXTERN_DP_PINS_0_TO_3_PIN2_OR_PIN3", {0xc009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin2 or pin3 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_0_TO_3_PIN3 233 { "EXTERN_DP_PINS_0_TO_3_PIN3", {0x8009e}, 0xf0, 1, {0xf00000}, "DP Pins 0-3 Asserted -- include pin3 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_4_TO_5_ALL 234 { "EXTERN_DP_PINS_4_TO_5_ALL", {0x3009f}, 0xf0, 1, {0xf00000}, "DP Pins 4-5 Asserted -- include pin5 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_4_TO_5_PIN4 235 { "EXTERN_DP_PINS_4_TO_5_PIN4", {0x1009f}, 0xf0, 1, {0xf00000}, "DP Pins 4-5 Asserted -- include pin4 assertion"}, #define PME_ITA2_EXTERN_DP_PINS_4_TO_5_PIN5 236 { "EXTERN_DP_PINS_4_TO_5_PIN5", {0x2009f}, 0xf0, 1, {0xf00000}, "DP Pins 4-5 Asserted -- include pin5 assertion"}, #define PME_ITA2_FE_BUBBLE_ALL 237 { "FE_BUBBLE_ALL", {0x71}, 0xf0, 1, {0xf00000}, "Bubbles Seen by FE -- count regardless of cause"}, #define PME_ITA2_FE_BUBBLE_ALLBUT_FEFLUSH_BUBBLE 238 { "FE_BUBBLE_ALLBUT_FEFLUSH_BUBBLE", {0xb0071}, 0xf0, 1, {0xf00000}, "Bubbles Seen by FE -- ALL except FEFLUSH and BUBBLE"}, #define PME_ITA2_FE_BUBBLE_ALLBUT_IBFULL 239 { "FE_BUBBLE_ALLBUT_IBFULL", {0xc0071}, 0xf0, 1, {0xf00000}, "Bubbles Seen by FE -- ALL except IBFULl"}, #define PME_ITA2_FE_BUBBLE_BRANCH 240 { "FE_BUBBLE_BRANCH", {0x90071}, 0xf0, 1, {0xf00000}, "Bubbles Seen by FE -- only if caused by any of 4 branch recirculates"}, #define PME_ITA2_FE_BUBBLE_BUBBLE 241 { "FE_BUBBLE_BUBBLE", {0xd0071}, 0xf0, 1, {0xf00000}, "Bubbles Seen by FE -- only if caused by branch bubble stall"}, #define PME_ITA2_FE_BUBBLE_FEFLUSH 242 { "FE_BUBBLE_FEFLUSH", {0x10071}, 0xf0, 1, {0xf00000}, "Bubbles Seen by FE -- only if caused by a front-end flush"}, #define PME_ITA2_FE_BUBBLE_FILL_RECIRC 243 { "FE_BUBBLE_FILL_RECIRC", {0x80071}, 0xf0, 1, {0xf00000}, "Bubbles Seen by FE -- only if caused by a recirculate for a cache line fill operation"}, #define PME_ITA2_FE_BUBBLE_GROUP1 244 { "FE_BUBBLE_GROUP1", {0x30071}, 0xf0, 1, {0xf00000}, "Bubbles Seen by FE -- BUBBLE or BRANCH"}, #define PME_ITA2_FE_BUBBLE_GROUP2 245 { "FE_BUBBLE_GROUP2", {0x40071}, 0xf0, 1, {0xf00000}, "Bubbles Seen by FE -- IMISS or TLBMISS"}, #define PME_ITA2_FE_BUBBLE_GROUP3 246 { "FE_BUBBLE_GROUP3", {0xa0071}, 0xf0, 1, {0xf00000}, "Bubbles Seen by FE -- FILL_RECIRC or BRANCH"}, #define PME_ITA2_FE_BUBBLE_IBFULL 247 { "FE_BUBBLE_IBFULL", {0x50071}, 0xf0, 1, {0xf00000}, "Bubbles Seen by FE -- only if caused by instruction buffer full stall"}, #define PME_ITA2_FE_BUBBLE_IMISS 248 { "FE_BUBBLE_IMISS", {0x60071}, 0xf0, 1, {0xf00000}, "Bubbles Seen by FE -- only if caused by instruction cache miss stall"}, #define PME_ITA2_FE_BUBBLE_TLBMISS 249 { "FE_BUBBLE_TLBMISS", {0x70071}, 0xf0, 1, {0xf00000}, "Bubbles Seen by FE -- only if caused by TLB stall"}, #define PME_ITA2_FE_LOST_BW_ALL 250 { "FE_LOST_BW_ALL", {0x70}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Entrance to IB -- count regardless of cause"}, #define PME_ITA2_FE_LOST_BW_BI 251 { "FE_LOST_BW_BI", {0x90070}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Entrance to IB -- only if caused by branch initialization stall"}, #define PME_ITA2_FE_LOST_BW_BRQ 252 { "FE_LOST_BW_BRQ", {0xa0070}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Entrance to IB -- only if caused by branch retirement queue stall"}, #define PME_ITA2_FE_LOST_BW_BR_ILOCK 253 { "FE_LOST_BW_BR_ILOCK", {0xc0070}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Entrance to IB -- only if caused by branch interlock stall"}, #define PME_ITA2_FE_LOST_BW_BUBBLE 254 { "FE_LOST_BW_BUBBLE", {0xd0070}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Entrance to IB -- only if caused by branch resteer bubble stall"}, #define PME_ITA2_FE_LOST_BW_FEFLUSH 255 { "FE_LOST_BW_FEFLUSH", {0x10070}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Entrance to IB -- only if caused by a front-end flush"}, #define PME_ITA2_FE_LOST_BW_FILL_RECIRC 256 { "FE_LOST_BW_FILL_RECIRC", {0x80070}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Entrance to IB -- only if caused by a recirculate for a cache line fill operation"}, #define PME_ITA2_FE_LOST_BW_IBFULL 257 { "FE_LOST_BW_IBFULL", {0x50070}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Entrance to IB -- only if caused by instruction buffer full stall"}, #define PME_ITA2_FE_LOST_BW_IMISS 258 { "FE_LOST_BW_IMISS", {0x60070}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Entrance to IB -- only if caused by instruction cache miss stall"}, #define PME_ITA2_FE_LOST_BW_PLP 259 { "FE_LOST_BW_PLP", {0xb0070}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Entrance to IB -- only if caused by perfect loop prediction stall"}, #define PME_ITA2_FE_LOST_BW_TLBMISS 260 { "FE_LOST_BW_TLBMISS", {0x70070}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Entrance to IB -- only if caused by TLB stall"}, #define PME_ITA2_FE_LOST_BW_UNREACHED 261 { "FE_LOST_BW_UNREACHED", {0x40070}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Entrance to IB -- only if caused by unreachable bundle"}, #define PME_ITA2_FP_FAILED_FCHKF 262 { "FP_FAILED_FCHKF", {0x6}, 0xf0, 1, {0xf00001}, "Failed fchkf"}, #define PME_ITA2_FP_FALSE_SIRSTALL 263 { "FP_FALSE_SIRSTALL", {0x5}, 0xf0, 1, {0xf00001}, "SIR Stall Without a Trap"}, #define PME_ITA2_FP_FLUSH_TO_ZERO 264 { "FP_FLUSH_TO_ZERO", {0xb}, 0xf0, 2, {0xf00001}, "FP Result Flushed to Zero"}, #define PME_ITA2_FP_OPS_RETIRED 265 { "FP_OPS_RETIRED", {0x9}, 0xf0, 4, {0xf00001}, "Retired FP Operations"}, #define PME_ITA2_FP_TRUE_SIRSTALL 266 { "FP_TRUE_SIRSTALL", {0x3}, 0xf0, 1, {0xf00001}, "SIR stall asserted and leads to a trap"}, #define PME_ITA2_HPW_DATA_REFERENCES 267 { "HPW_DATA_REFERENCES", {0x2d}, 0xf0, 4, {0xf00007}, "Data Memory References to VHPT"}, #define PME_ITA2_IA32_INST_RETIRED 268 { "IA32_INST_RETIRED", {0x59}, 0xf0, 2, {0xf00000}, "IA-32 Instructions Retired"}, #define PME_ITA2_IA32_ISA_TRANSITIONS 269 { "IA32_ISA_TRANSITIONS", {0x7}, 0xf0, 1, {0xf00000}, "IA-64 to/from IA-32 ISA Transitions"}, #define PME_ITA2_IA64_INST_RETIRED 270 { "IA64_INST_RETIRED", {0x8}, 0xf0, 6, {0xf00003}, "Retired IA-64 Instructions, alias to IA64_INST_RETIRED_THIS"}, #define PME_ITA2_IA64_INST_RETIRED_THIS 271 { "IA64_INST_RETIRED_THIS", {0x8}, 0xf0, 6, {0xf00003}, "Retired IA-64 Instructions -- Retired IA-64 Instructions"}, #define PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP0_PMC8 272 { "IA64_TAGGED_INST_RETIRED_IBRP0_PMC8", {0x8}, 0xf0, 6, {0xf00003}, "Retired Tagged Instructions -- Instruction tagged by Instruction Breakpoint Pair 0 and opcode matcher PMC8. Code executed with PSR.is=1 is included."}, #define PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP1_PMC9 273 { "IA64_TAGGED_INST_RETIRED_IBRP1_PMC9", {0x10008}, 0xf0, 6, {0xf00003}, "Retired Tagged Instructions -- Instruction tagged by Instruction Breakpoint Pair 1 and opcode matcher PMC9. Code executed with PSR.is=1 is included."}, #define PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP2_PMC8 274 { "IA64_TAGGED_INST_RETIRED_IBRP2_PMC8", {0x20008}, 0xf0, 6, {0xf00003}, "Retired Tagged Instructions -- Instruction tagged by Instruction Breakpoint Pair 2 and opcode matcher PMC8. Code executed with PSR.is=1 is not included."}, #define PME_ITA2_IA64_TAGGED_INST_RETIRED_IBRP3_PMC9 275 { "IA64_TAGGED_INST_RETIRED_IBRP3_PMC9", {0x30008}, 0xf0, 6, {0xf00003}, "Retired Tagged Instructions -- Instruction tagged by Instruction Breakpoint Pair 3 and opcode matcher PMC9. Code executed with PSR.is=1 is not included."}, #define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_ALL 276 { "IDEAL_BE_LOST_BW_DUE_TO_FE_ALL", {0x73}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Exit from IB -- count regardless of cause"}, #define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_BI 277 { "IDEAL_BE_LOST_BW_DUE_TO_FE_BI", {0x90073}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Exit from IB -- only if caused by branch initialization stall"}, #define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_BRQ 278 { "IDEAL_BE_LOST_BW_DUE_TO_FE_BRQ", {0xa0073}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Exit from IB -- only if caused by branch retirement queue stall"}, #define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_BR_ILOCK 279 { "IDEAL_BE_LOST_BW_DUE_TO_FE_BR_ILOCK", {0xc0073}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Exit from IB -- only if caused by branch interlock stall"}, #define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_BUBBLE 280 { "IDEAL_BE_LOST_BW_DUE_TO_FE_BUBBLE", {0xd0073}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Exit from IB -- only if caused by branch resteer bubble stall"}, #define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_FEFLUSH 281 { "IDEAL_BE_LOST_BW_DUE_TO_FE_FEFLUSH", {0x10073}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Exit from IB -- only if caused by a front-end flush"}, #define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_FILL_RECIRC 282 { "IDEAL_BE_LOST_BW_DUE_TO_FE_FILL_RECIRC", {0x80073}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Exit from IB -- only if caused by a recirculate for a cache line fill operation"}, #define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_IBFULL 283 { "IDEAL_BE_LOST_BW_DUE_TO_FE_IBFULL", {0x50073}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Exit from IB -- (* meaningless for this event *)"}, #define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_IMISS 284 { "IDEAL_BE_LOST_BW_DUE_TO_FE_IMISS", {0x60073}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Exit from IB -- only if caused by instruction cache miss stall"}, #define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_PLP 285 { "IDEAL_BE_LOST_BW_DUE_TO_FE_PLP", {0xb0073}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Exit from IB -- only if caused by perfect loop prediction stall"}, #define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_TLBMISS 286 { "IDEAL_BE_LOST_BW_DUE_TO_FE_TLBMISS", {0x70073}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Exit from IB -- only if caused by TLB stall"}, #define PME_ITA2_IDEAL_BE_LOST_BW_DUE_TO_FE_UNREACHED 287 { "IDEAL_BE_LOST_BW_DUE_TO_FE_UNREACHED", {0x40073}, 0xf0, 2, {0xf00000}, "Invalid Bundles at the Exit from IB -- only if caused by unreachable bundle"}, #define PME_ITA2_INST_CHKA_LDC_ALAT_ALL 288 { "INST_CHKA_LDC_ALAT_ALL", {0x30056}, 0xf0, 2, {0xf00007}, "Retired chk.a and ld.c Instructions -- both integer and floating point instructions"}, #define PME_ITA2_INST_CHKA_LDC_ALAT_FP 289 { "INST_CHKA_LDC_ALAT_FP", {0x20056}, 0xf0, 2, {0xf00007}, "Retired chk.a and ld.c Instructions -- only floating point instructions"}, #define PME_ITA2_INST_CHKA_LDC_ALAT_INT 290 { "INST_CHKA_LDC_ALAT_INT", {0x10056}, 0xf0, 2, {0xf00007}, "Retired chk.a and ld.c Instructions -- only integer instructions"}, #define PME_ITA2_INST_DISPERSED 291 { "INST_DISPERSED", {0x4d}, 0xf0, 6, {0xf00001}, "Syllables Dispersed from REN to REG stage"}, #define PME_ITA2_INST_FAILED_CHKA_LDC_ALAT_ALL 292 { "INST_FAILED_CHKA_LDC_ALAT_ALL", {0x30057}, 0xf0, 1, {0xf00007}, "Failed chk.a and ld.c Instructions -- both integer and floating point instructions"}, #define PME_ITA2_INST_FAILED_CHKA_LDC_ALAT_FP 293 { "INST_FAILED_CHKA_LDC_ALAT_FP", {0x20057}, 0xf0, 1, {0xf00007}, "Failed chk.a and ld.c Instructions -- only floating point instructions"}, #define PME_ITA2_INST_FAILED_CHKA_LDC_ALAT_INT 294 { "INST_FAILED_CHKA_LDC_ALAT_INT", {0x10057}, 0xf0, 1, {0xf00007}, "Failed chk.a and ld.c Instructions -- only integer instructions"}, #define PME_ITA2_INST_FAILED_CHKS_RETIRED_ALL 295 { "INST_FAILED_CHKS_RETIRED_ALL", {0x30055}, 0xf0, 1, {0xf00000}, "Failed chk.s Instructions -- both integer and floating point instructions"}, #define PME_ITA2_INST_FAILED_CHKS_RETIRED_FP 296 { "INST_FAILED_CHKS_RETIRED_FP", {0x20055}, 0xf0, 1, {0xf00000}, "Failed chk.s Instructions -- only floating point instructions"}, #define PME_ITA2_INST_FAILED_CHKS_RETIRED_INT 297 { "INST_FAILED_CHKS_RETIRED_INT", {0x10055}, 0xf0, 1, {0xf00000}, "Failed chk.s Instructions -- only integer instructions"}, #define PME_ITA2_ISB_BUNPAIRS_IN 298 { "ISB_BUNPAIRS_IN", {0x46}, 0xf0, 1, {0xf00001}, "Bundle Pairs Written from L2 into FE"}, #define PME_ITA2_ITLB_MISSES_FETCH_ALL 299 { "ITLB_MISSES_FETCH_ALL", {0x30047}, 0xf0, 1, {0xf00001}, "ITLB Misses Demand Fetch -- All tlb misses will be counted. Note that this is not equal to sum of the L1ITLB and L2ITLB umasks because any access could be a miss in L1ITLB and L2ITLB."}, #define PME_ITA2_ITLB_MISSES_FETCH_L1ITLB 300 { "ITLB_MISSES_FETCH_L1ITLB", {0x10047}, 0xf0, 1, {0xf00001}, "ITLB Misses Demand Fetch -- All misses in L1ITLB will be counted. even if L1ITLB is not updated for an access (Uncacheable/nat page/not present page/faulting/some flushed), it will be counted here."}, #define PME_ITA2_ITLB_MISSES_FETCH_L2ITLB 301 { "ITLB_MISSES_FETCH_L2ITLB", {0x20047}, 0xf0, 1, {0xf00001}, "ITLB Misses Demand Fetch -- All misses in L1ITLB which also missed in L2ITLB will be counted."}, #define PME_ITA2_L1DTLB_TRANSFER 302 { "L1DTLB_TRANSFER", {0xc0}, 0xf0, 1, {0x5010007}, "L1DTLB Misses That Hit in the L2DTLB for Accesses Counted in L1D_READS"}, #define PME_ITA2_L1D_READS_SET0 303 { "L1D_READS_SET0", {0xc2}, 0xf0, 2, {0x5010007}, "L1 Data Cache Reads"}, #define PME_ITA2_L1D_READS_SET1 304 { "L1D_READS_SET1", {0xc4}, 0xf0, 2, {0x5110007}, "L1 Data Cache Reads"}, #define PME_ITA2_L1D_READ_MISSES_ALL 305 { "L1D_READ_MISSES_ALL", {0xc7}, 0xf0, 2, {0x5110007}, "L1 Data Cache Read Misses -- all L1D read misses will be counted."}, #define PME_ITA2_L1D_READ_MISSES_RSE_FILL 306 { "L1D_READ_MISSES_RSE_FILL", {0x100c7}, 0xf0, 2, {0x5110007}, "L1 Data Cache Read Misses -- only L1D read misses caused by RSE fills will be counted"}, #define PME_ITA2_L1ITLB_INSERTS_HPW 307 { "L1ITLB_INSERTS_HPW", {0x48}, 0xf0, 1, {0xf00001}, "L1ITLB Hardware Page Walker Inserts"}, #define PME_ITA2_L1I_EAR_CACHE_LAT0 308 { "L1I_EAR_CACHE_LAT0", {0x400343}, 0xf0, 1, {0xf00001}, "L1I EAR Cache -- > 0 Cycles (All L1 Misses)"}, #define PME_ITA2_L1I_EAR_CACHE_LAT1024 309 { "L1I_EAR_CACHE_LAT1024", {0xc00343}, 0xf0, 1, {0xf00001}, "L1I EAR Cache -- >= 1024 Cycles"}, #define PME_ITA2_L1I_EAR_CACHE_LAT128 310 { "L1I_EAR_CACHE_LAT128", {0xf00343}, 0xf0, 1, {0xf00001}, "L1I EAR Cache -- >= 128 Cycles"}, #define PME_ITA2_L1I_EAR_CACHE_LAT16 311 { "L1I_EAR_CACHE_LAT16", {0xfc0343}, 0xf0, 1, {0xf00001}, "L1I EAR Cache -- >= 16 Cycles"}, #define PME_ITA2_L1I_EAR_CACHE_LAT256 312 { "L1I_EAR_CACHE_LAT256", {0xe00343}, 0xf0, 1, {0xf00001}, "L1I EAR Cache -- >= 256 Cycles"}, #define PME_ITA2_L1I_EAR_CACHE_LAT32 313 { "L1I_EAR_CACHE_LAT32", {0xf80343}, 0xf0, 1, {0xf00001}, "L1I EAR Cache -- >= 32 Cycles"}, #define PME_ITA2_L1I_EAR_CACHE_LAT4 314 { "L1I_EAR_CACHE_LAT4", {0xff0343}, 0xf0, 1, {0xf00001}, "L1I EAR Cache -- >= 4 Cycles"}, #define PME_ITA2_L1I_EAR_CACHE_LAT4096 315 { "L1I_EAR_CACHE_LAT4096", {0x800343}, 0xf0, 1, {0xf00001}, "L1I EAR Cache -- >= 4096 Cycles"}, #define PME_ITA2_L1I_EAR_CACHE_LAT8 316 { "L1I_EAR_CACHE_LAT8", {0xfe0343}, 0xf0, 1, {0xf00001}, "L1I EAR Cache -- >= 8 Cycles"}, #define PME_ITA2_L1I_EAR_CACHE_RAB 317 { "L1I_EAR_CACHE_RAB", {0x343}, 0xf0, 1, {0xf00001}, "L1I EAR Cache -- RAB HIT"}, #define PME_ITA2_L1I_EAR_EVENTS 318 { "L1I_EAR_EVENTS", {0x43}, 0xf0, 1, {0xf00001}, "Instruction EAR Events"}, #define PME_ITA2_L1I_EAR_TLB_ALL 319 { "L1I_EAR_TLB_ALL", {0x70243}, 0xf0, 1, {0xf00001}, "L1I EAR TLB -- All L1 ITLB Misses"}, #define PME_ITA2_L1I_EAR_TLB_FAULT 320 { "L1I_EAR_TLB_FAULT", {0x40243}, 0xf0, 1, {0xf00001}, "L1I EAR TLB -- ITLB Misses which produced a fault"}, #define PME_ITA2_L1I_EAR_TLB_L2TLB 321 { "L1I_EAR_TLB_L2TLB", {0x10243}, 0xf0, 1, {0xf00001}, "L1I EAR TLB -- L1 ITLB Misses which hit L2 ITLB"}, #define PME_ITA2_L1I_EAR_TLB_L2TLB_OR_FAULT 322 { "L1I_EAR_TLB_L2TLB_OR_FAULT", {0x50243}, 0xf0, 1, {0xf00001}, "L1I EAR TLB -- L1 ITLB Misses which hit L2 ITLB or produce a software fault"}, #define PME_ITA2_L1I_EAR_TLB_L2TLB_OR_VHPT 323 { "L1I_EAR_TLB_L2TLB_OR_VHPT", {0x30243}, 0xf0, 1, {0xf00001}, "L1I EAR TLB -- L1 ITLB Misses which hit L2 ITLB or VHPT"}, #define PME_ITA2_L1I_EAR_TLB_VHPT 324 { "L1I_EAR_TLB_VHPT", {0x20243}, 0xf0, 1, {0xf00001}, "L1I EAR TLB -- L1 ITLB Misses which hit VHPT"}, #define PME_ITA2_L1I_EAR_TLB_VHPT_OR_FAULT 325 { "L1I_EAR_TLB_VHPT_OR_FAULT", {0x60243}, 0xf0, 1, {0xf00001}, "L1I EAR TLB -- L1 ITLB Misses which hit VHPT or produce a software fault"}, #define PME_ITA2_L1I_FETCH_ISB_HIT 326 { "L1I_FETCH_ISB_HIT", {0x66}, 0xf0, 1, {0xf00001}, "\"Just-In-Time\" Instruction Fetch Hitting in and Being Bypassed from ISB"}, #define PME_ITA2_L1I_FETCH_RAB_HIT 327 { "L1I_FETCH_RAB_HIT", {0x65}, 0xf0, 1, {0xf00001}, "Instruction Fetch Hitting in RAB"}, #define PME_ITA2_L1I_FILLS 328 { "L1I_FILLS", {0x41}, 0xf0, 1, {0xf00001}, "L1 Instruction Cache Fills"}, #define PME_ITA2_L1I_PREFETCHES 329 { "L1I_PREFETCHES", {0x44}, 0xf0, 1, {0xf00001}, "L1 Instruction Prefetch Requests"}, #define PME_ITA2_L1I_PREFETCH_STALL_ALL 330 { "L1I_PREFETCH_STALL_ALL", {0x30067}, 0xf0, 1, {0xf00000}, "Prefetch Pipeline Stalls -- Number of clocks prefetch pipeline is stalled"}, #define PME_ITA2_L1I_PREFETCH_STALL_FLOW 331 { "L1I_PREFETCH_STALL_FLOW", {0x20067}, 0xf0, 1, {0xf00000}, "Prefetch Pipeline Stalls -- Number of clocks flow is not asserted"}, #define PME_ITA2_L1I_PURGE 332 { "L1I_PURGE", {0x4b}, 0xf0, 1, {0xf00001}, "L1ITLB Purges Handled by L1I"}, #define PME_ITA2_L1I_PVAB_OVERFLOW 333 { "L1I_PVAB_OVERFLOW", {0x69}, 0xf0, 1, {0xf00000}, "PVAB Overflow"}, #define PME_ITA2_L1I_RAB_ALMOST_FULL 334 { "L1I_RAB_ALMOST_FULL", {0x64}, 0xf0, 1, {0xf00000}, "Is RAB Almost Full?"}, #define PME_ITA2_L1I_RAB_FULL 335 { "L1I_RAB_FULL", {0x60}, 0xf0, 1, {0xf00000}, "Is RAB Full?"}, #define PME_ITA2_L1I_READS 336 { "L1I_READS", {0x40}, 0xf0, 1, {0xf00001}, "L1 Instruction Cache Reads"}, #define PME_ITA2_L1I_SNOOP 337 { "L1I_SNOOP", {0x4a}, 0xf0, 1, {0xf00007}, "Snoop Requests Handled by L1I"}, #define PME_ITA2_L1I_STRM_PREFETCHES 338 { "L1I_STRM_PREFETCHES", {0x5f}, 0xf0, 1, {0xf00001}, "L1 Instruction Cache Line Prefetch Requests"}, #define PME_ITA2_L2DTLB_MISSES 339 { "L2DTLB_MISSES", {0xc1}, 0xf0, 4, {0x5010007}, "L2DTLB Misses"}, #define PME_ITA2_L2_BAD_LINES_SELECTED_ANY 340 { "L2_BAD_LINES_SELECTED_ANY", {0xb9}, 0xf0, 4, {0x4320007}, "Valid Line Replaced When Invalid Line Is Available -- Valid line replaced when invalid line is available"}, #define PME_ITA2_L2_BYPASS_L2_DATA1 341 { "L2_BYPASS_L2_DATA1", {0xb8}, 0xf0, 1, {0x4320007}, "Count L2 Bypasses -- Count only L2 data bypasses (L1D to L2A)"}, #define PME_ITA2_L2_BYPASS_L2_DATA2 342 { "L2_BYPASS_L2_DATA2", {0x100b8}, 0xf0, 1, {0x4320007}, "Count L2 Bypasses -- Count only L2 data bypasses (L1W to L2I)"}, #define PME_ITA2_L2_BYPASS_L2_INST1 343 { "L2_BYPASS_L2_INST1", {0x400b8}, 0xf0, 1, {0x4320007}, "Count L2 Bypasses -- Count only L2 instruction bypasses (L1D to L2A)"}, #define PME_ITA2_L2_BYPASS_L2_INST2 344 { "L2_BYPASS_L2_INST2", {0x500b8}, 0xf0, 1, {0x4320007}, "Count L2 Bypasses -- Count only L2 instruction bypasses (L1W to L2I)"}, #define PME_ITA2_L2_BYPASS_L3_DATA1 345 { "L2_BYPASS_L3_DATA1", {0x200b8}, 0xf0, 1, {0x4320007}, "Count L2 Bypasses -- Count only L3 data bypasses (L1D to L2A)"}, #define PME_ITA2_L2_BYPASS_L3_INST1 346 { "L2_BYPASS_L3_INST1", {0x600b8}, 0xf0, 1, {0x4320007}, "Count L2 Bypasses -- Count only L3 instruction bypasses (L1D to L2A)"}, #define PME_ITA2_L2_DATA_REFERENCES_L2_ALL 347 { "L2_DATA_REFERENCES_L2_ALL", {0x300b2}, 0xf0, 4, {0x4120007}, "Data Read/Write Access to L2 -- count both read and write operations (semaphores will count as 2)"}, #define PME_ITA2_L2_DATA_REFERENCES_L2_DATA_READS 348 { "L2_DATA_REFERENCES_L2_DATA_READS", {0x100b2}, 0xf0, 4, {0x4120007}, "Data Read/Write Access to L2 -- count only data read and semaphore operations."}, #define PME_ITA2_L2_DATA_REFERENCES_L2_DATA_WRITES 349 { "L2_DATA_REFERENCES_L2_DATA_WRITES", {0x200b2}, 0xf0, 4, {0x4120007}, "Data Read/Write Access to L2 -- count only data write and semaphore operations"}, #define PME_ITA2_L2_FILLB_FULL_THIS 350 { "L2_FILLB_FULL_THIS", {0xbf}, 0xf0, 1, {0x4520000}, "L2D Fill Buffer Is Full -- L2 Fill buffer is full"}, #define PME_ITA2_L2_FORCE_RECIRC_ANY 351 { "L2_FORCE_RECIRC_ANY", {0xb4}, 0x10, 4, {0x4220007}, "Forced Recirculates -- count forced recirculates regardless of cause. SMC_HIT, TRAN_PREF & SNP_OR_L3 will not be included here."}, #define PME_ITA2_L2_FORCE_RECIRC_FILL_HIT 352 { "L2_FORCE_RECIRC_FILL_HIT", {0x900b4}, 0x10, 4, {0x4220007}, "Forced Recirculates -- count only those caused by an L2 miss which hit in the fill buffer."}, #define PME_ITA2_L2_FORCE_RECIRC_FRC_RECIRC 353 { "L2_FORCE_RECIRC_FRC_RECIRC", {0xe00b4}, 0x10, 4, {0x4220007}, "Forced Recirculates -- caused by an L2 miss when a force recirculate already existed"}, #define PME_ITA2_L2_FORCE_RECIRC_IPF_MISS 354 { "L2_FORCE_RECIRC_IPF_MISS", {0xa00b4}, 0x10, 4, {0x4220007}, "Forced Recirculates -- caused by L2 miss when instruction prefetch buffer miss already existed"}, #define PME_ITA2_L2_FORCE_RECIRC_L1W 355 { "L2_FORCE_RECIRC_L1W", {0x200b4}, 0x10, 4, {0x4220007}, "Forced Recirculates -- count only those caused by forced limbo"}, #define PME_ITA2_L2_FORCE_RECIRC_OZQ_MISS 356 { "L2_FORCE_RECIRC_OZQ_MISS", {0xc00b4}, 0x10, 4, {0x4220007}, "Forced Recirculates -- caused by an L2 miss when an OZQ miss already existed"}, #define PME_ITA2_L2_FORCE_RECIRC_SAME_INDEX 357 { "L2_FORCE_RECIRC_SAME_INDEX", {0xd00b4}, 0x10, 4, {0x4220007}, "Forced Recirculates -- caused by an L2 miss when a miss to the same index already existed"}, #define PME_ITA2_L2_FORCE_RECIRC_SMC_HIT 358 { "L2_FORCE_RECIRC_SMC_HIT", {0x100b4}, 0x10, 4, {0x4220007}, "Forced Recirculates -- count only those caused by SMC hits due to an ifetch and load to same cache line or a pending WT store"}, #define PME_ITA2_L2_FORCE_RECIRC_SNP_OR_L3 359 { "L2_FORCE_RECIRC_SNP_OR_L3", {0x600b4}, 0x10, 4, {0x4220007}, "Forced Recirculates -- count only those caused by a snoop or L3 issue"}, #define PME_ITA2_L2_FORCE_RECIRC_TAG_NOTOK 360 { "L2_FORCE_RECIRC_TAG_NOTOK", {0x400b4}, 0x10, 4, {0x4220007}, "Forced Recirculates -- count only those caused by L2 hits caused by in flight snoops, stores with a sibling miss to the same index, sibling probe to the same line or pending sync.ia instructions."}, #define PME_ITA2_L2_FORCE_RECIRC_TRAN_PREF 361 { "L2_FORCE_RECIRC_TRAN_PREF", {0x500b4}, 0x10, 4, {0x4220007}, "Forced Recirculates -- count only those caused by transforms to prefetches"}, #define PME_ITA2_L2_FORCE_RECIRC_VIC_BUF_FULL 362 { "L2_FORCE_RECIRC_VIC_BUF_FULL", {0xb00b4}, 0x10, 4, {0x4220007}, "Forced Recirculates -- count only those caused by an L2 miss with victim buffer full"}, #define PME_ITA2_L2_FORCE_RECIRC_VIC_PEND 363 { "L2_FORCE_RECIRC_VIC_PEND", {0x800b4}, 0x10, 4, {0x4220007}, "Forced Recirculates -- count only those caused by an L2 miss with pending victim"}, #define PME_ITA2_L2_GOT_RECIRC_IFETCH_ANY 364 { "L2_GOT_RECIRC_IFETCH_ANY", {0x800ba}, 0xf0, 1, {0x4420007}, "Instruction Fetch Recirculates Received by L2D -- Instruction fetch recirculates received by L2"}, #define PME_ITA2_L2_GOT_RECIRC_OZQ_ACC 365 { "L2_GOT_RECIRC_OZQ_ACC", {0xb6}, 0xf0, 1, {0x4220007}, "Counts Number of OZQ Accesses Recirculated to L1D"}, #define PME_ITA2_L2_IFET_CANCELS_ANY 366 { "L2_IFET_CANCELS_ANY", {0xa1}, 0xf0, 1, {0x4020007}, "Instruction Fetch Cancels by the L2 -- total instruction fetch cancels by L2"}, #define PME_ITA2_L2_IFET_CANCELS_BYPASS 367 { "L2_IFET_CANCELS_BYPASS", {0x200a1}, 0xf0, 1, {0x4020007}, "Instruction Fetch Cancels by the L2 -- ifetch cancels due to bypassing"}, #define PME_ITA2_L2_IFET_CANCELS_CHG_PRIO 368 { "L2_IFET_CANCELS_CHG_PRIO", {0xc00a1}, 0xf0, 1, {0x4020007}, "Instruction Fetch Cancels by the L2 -- ifetch cancels due to change priority"}, #define PME_ITA2_L2_IFET_CANCELS_DATA_RD 369 { "L2_IFET_CANCELS_DATA_RD", {0x700a1}, 0xf0, 1, {0x4020007}, "Instruction Fetch Cancels by the L2 -- ifetch/prefetch cancels due to a data read"}, #define PME_ITA2_L2_IFET_CANCELS_DIDNT_RECIR 370 { "L2_IFET_CANCELS_DIDNT_RECIR", {0x400a1}, 0xf0, 1, {0x4020007}, "Instruction Fetch Cancels by the L2 -- ifetch cancels because it did not recirculate"}, #define PME_ITA2_L2_IFET_CANCELS_IFETCH_BYP 371 { "L2_IFET_CANCELS_IFETCH_BYP", {0xd00a1}, 0xf0, 1, {0x4020007}, "Instruction Fetch Cancels by the L2 -- due to ifetch bypass during last clock"}, #define PME_ITA2_L2_IFET_CANCELS_PREEMPT 372 { "L2_IFET_CANCELS_PREEMPT", {0x800a1}, 0xf0, 1, {0x4020007}, "Instruction Fetch Cancels by the L2 -- ifetch cancels due to preempts"}, #define PME_ITA2_L2_IFET_CANCELS_RECIR_OVER_SUB 373 { "L2_IFET_CANCELS_RECIR_OVER_SUB", {0x500a1}, 0xf0, 1, {0x4020007}, "Instruction Fetch Cancels by the L2 -- ifetch cancels because of recirculate oversubscription"}, #define PME_ITA2_L2_IFET_CANCELS_ST_FILL_WB 374 { "L2_IFET_CANCELS_ST_FILL_WB", {0x600a1}, 0xf0, 1, {0x4020007}, "Instruction Fetch Cancels by the L2 -- ifetch cancels due to a store or fill or write back"}, #define PME_ITA2_L2_INST_DEMAND_READS 375 { "L2_INST_DEMAND_READS", {0x42}, 0xf0, 1, {0xf00001}, "L2 Instruction Demand Fetch Requests"}, #define PME_ITA2_L2_INST_PREFETCHES 376 { "L2_INST_PREFETCHES", {0x45}, 0xf0, 1, {0xf00001}, "L2 Instruction Prefetch Requests"}, #define PME_ITA2_L2_ISSUED_RECIRC_IFETCH_ANY 377 { "L2_ISSUED_RECIRC_IFETCH_ANY", {0x800b9}, 0xf0, 1, {0x4420007}, "Instruction Fetch Recirculates Issued by L2 -- Instruction fetch recirculates issued by L2"}, #define PME_ITA2_L2_ISSUED_RECIRC_OZQ_ACC 378 { "L2_ISSUED_RECIRC_OZQ_ACC", {0xb5}, 0xf0, 1, {0x4220007}, "Count Number of Times a Recirculate Issue Was Attempted and Not Preempted"}, #define PME_ITA2_L2_L3ACCESS_CANCEL_ANY 379 { "L2_L3ACCESS_CANCEL_ANY", {0x900b0}, 0x10, 1, {0x4120007}, "Canceled L3 Accesses -- count cancels due to any reason. This umask will count more than the sum of all the other umasks. It will count things that weren't committed accesses when they reached L1w, but the L2 attempted to bypass them to the L3 anyway (speculatively). This will include accesses made repeatedly while the main pipeline is stalled and the L1d is attempting to recirculate an access down the L1d pipeline. Thus, an access could get counted many times before it really does get bypassed to the L3. It is a measure of how many times we asserted a request to the L3 but didn't confirm it."}, #define PME_ITA2_L2_L3ACCESS_CANCEL_DFETCH 380 { "L2_L3ACCESS_CANCEL_DFETCH", {0xa00b0}, 0x10, 1, {0x4120007}, "Canceled L3 Accesses -- data fetches"}, #define PME_ITA2_L2_L3ACCESS_CANCEL_EBL_REJECT 381 { "L2_L3ACCESS_CANCEL_EBL_REJECT", {0x800b0}, 0x10, 1, {0x4120007}, "Canceled L3 Accesses -- ebl rejects"}, #define PME_ITA2_L2_L3ACCESS_CANCEL_FILLD_FULL 382 { "L2_L3ACCESS_CANCEL_FILLD_FULL", {0x200b0}, 0x10, 1, {0x4120007}, "Canceled L3 Accesses -- filld being full"}, #define PME_ITA2_L2_L3ACCESS_CANCEL_IFETCH 383 { "L2_L3ACCESS_CANCEL_IFETCH", {0xb00b0}, 0xf0, 1, {0x4120007}, "Canceled L3 Accesses -- instruction fetches"}, #define PME_ITA2_L2_L3ACCESS_CANCEL_INV_L3_BYP 384 { "L2_L3ACCESS_CANCEL_INV_L3_BYP", {0x600b0}, 0x10, 1, {0x4120007}, "Canceled L3 Accesses -- invalid L3 bypasses"}, #define PME_ITA2_L2_L3ACCESS_CANCEL_SPEC_L3_BYP 385 { "L2_L3ACCESS_CANCEL_SPEC_L3_BYP", {0x100b0}, 0x10, 1, {0x4120007}, "Canceled L3 Accesses -- speculative L3 bypasses"}, #define PME_ITA2_L2_L3ACCESS_CANCEL_UC_BLOCKED 386 { "L2_L3ACCESS_CANCEL_UC_BLOCKED", {0x500b0}, 0x10, 1, {0x4120007}, "Canceled L3 Accesses -- Uncacheable blocked L3 Accesses"}, #define PME_ITA2_L2_MISSES 387 { "L2_MISSES", {0xcb}, 0xf0, 1, {0xf00007}, "L2 Misses"}, #define PME_ITA2_L2_OPS_ISSUED_FP_LOAD 388 { "L2_OPS_ISSUED_FP_LOAD", {0x900b8}, 0xf0, 4, {0x4420007}, "Different Operations Issued by L2D -- Count only valid floating point loads"}, #define PME_ITA2_L2_OPS_ISSUED_INT_LOAD 389 { "L2_OPS_ISSUED_INT_LOAD", {0x800b8}, 0xf0, 4, {0x4420007}, "Different Operations Issued by L2D -- Count only valid integer loads"}, #define PME_ITA2_L2_OPS_ISSUED_NST_NLD 390 { "L2_OPS_ISSUED_NST_NLD", {0xc00b8}, 0xf0, 4, {0x4420007}, "Different Operations Issued by L2D -- Count only valid non-load, no-store accesses"}, #define PME_ITA2_L2_OPS_ISSUED_RMW 391 { "L2_OPS_ISSUED_RMW", {0xa00b8}, 0xf0, 4, {0x4420007}, "Different Operations Issued by L2D -- Count only valid read_modify_write stores"}, #define PME_ITA2_L2_OPS_ISSUED_STORE 392 { "L2_OPS_ISSUED_STORE", {0xb00b8}, 0xf0, 4, {0x4420007}, "Different Operations Issued by L2D -- Count only valid non-read_modify_write stores"}, #define PME_ITA2_L2_OZDB_FULL_THIS 393 { "L2_OZDB_FULL_THIS", {0xbd}, 0xf0, 1, {0x4520000}, "L2 OZ Data Buffer Is Full -- L2 OZ Data Buffer is full"}, #define PME_ITA2_L2_OZQ_ACQUIRE 394 { "L2_OZQ_ACQUIRE", {0xa2}, 0xf0, 1, {0x4020000}, "Clocks With Acquire Ordering Attribute Existed in L2 OZQ"}, #define PME_ITA2_L2_OZQ_CANCELS0_ANY 395 { "L2_OZQ_CANCELS0_ANY", {0xa0}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Late or Any) -- counts the total OZ Queue cancels"}, #define PME_ITA2_L2_OZQ_CANCELS0_LATE_ACQUIRE 396 { "L2_OZQ_CANCELS0_LATE_ACQUIRE", {0x300a0}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Late or Any) -- counts the late cancels caused by acquires"}, #define PME_ITA2_L2_OZQ_CANCELS0_LATE_BYP_EFFRELEASE 397 { "L2_OZQ_CANCELS0_LATE_BYP_EFFRELEASE", {0x400a0}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Late or Any) -- counts the late cancels caused by L1D to L2A bypass effective releases"}, #define PME_ITA2_L2_OZQ_CANCELS0_LATE_RELEASE 398 { "L2_OZQ_CANCELS0_LATE_RELEASE", {0x200a0}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Late or Any) -- counts the late cancels caused by releases"}, #define PME_ITA2_L2_OZQ_CANCELS0_LATE_SPEC_BYP 399 { "L2_OZQ_CANCELS0_LATE_SPEC_BYP", {0x100a0}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Late or Any) -- counts the late cancels caused by speculative bypasses"}, #define PME_ITA2_L2_OZQ_CANCELS1_BANK_CONF 400 { "L2_OZQ_CANCELS1_BANK_CONF", {0x100ac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- bank conflicts"}, #define PME_ITA2_L2_OZQ_CANCELS1_CANC_L2M_ST 401 { "L2_OZQ_CANCELS1_CANC_L2M_ST", {0x600ac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- caused by a canceled store in L2M"}, #define PME_ITA2_L2_OZQ_CANCELS1_CCV 402 { "L2_OZQ_CANCELS1_CCV", {0x900ac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- a ccv"}, #define PME_ITA2_L2_OZQ_CANCELS1_ECC 403 { "L2_OZQ_CANCELS1_ECC", {0xf00ac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- ECC hardware detecting a problem"}, #define PME_ITA2_L2_OZQ_CANCELS1_HPW_IFETCH_CONF 404 { "L2_OZQ_CANCELS1_HPW_IFETCH_CONF", {0x500ac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- a ifetch conflict (canceling HPW?)"}, #define PME_ITA2_L2_OZQ_CANCELS1_L1DF_L2M 405 { "L2_OZQ_CANCELS1_L1DF_L2M", {0xe00ac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- L1D fill in L2M"}, #define PME_ITA2_L2_OZQ_CANCELS1_L1_FILL_CONF 406 { "L2_OZQ_CANCELS1_L1_FILL_CONF", {0x700ac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- an L1 fill conflict"}, #define PME_ITA2_L2_OZQ_CANCELS1_L2A_ST_MAT 407 { "L2_OZQ_CANCELS1_L2A_ST_MAT", {0xd00ac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- a store match in L2A"}, #define PME_ITA2_L2_OZQ_CANCELS1_L2D_ST_MAT 408 { "L2_OZQ_CANCELS1_L2D_ST_MAT", {0x200ac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- a store match in L2D"}, #define PME_ITA2_L2_OZQ_CANCELS1_L2M_ST_MAT 409 { "L2_OZQ_CANCELS1_L2M_ST_MAT", {0xb00ac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- a store match in L2M"}, #define PME_ITA2_L2_OZQ_CANCELS1_MFA 410 { "L2_OZQ_CANCELS1_MFA", {0xc00ac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- a memory fence instruction"}, #define PME_ITA2_L2_OZQ_CANCELS1_REL 411 { "L2_OZQ_CANCELS1_REL", {0xac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- caused by release"}, #define PME_ITA2_L2_OZQ_CANCELS1_SEM 412 { "L2_OZQ_CANCELS1_SEM", {0xa00ac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- a semaphore"}, #define PME_ITA2_L2_OZQ_CANCELS1_ST_FILL_CONF 413 { "L2_OZQ_CANCELS1_ST_FILL_CONF", {0x800ac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- a store fill conflict"}, #define PME_ITA2_L2_OZQ_CANCELS1_SYNC 414 { "L2_OZQ_CANCELS1_SYNC", {0x400ac}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 1) -- caused by sync.i"}, #define PME_ITA2_L2_OZQ_CANCELS2_ACQ 415 { "L2_OZQ_CANCELS2_ACQ", {0x400a8}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 2) -- caused by an acquire"}, #define PME_ITA2_L2_OZQ_CANCELS2_CANC_L2C_ST 416 { "L2_OZQ_CANCELS2_CANC_L2C_ST", {0x100a8}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 2) -- caused by a canceled store in L2C"}, #define PME_ITA2_L2_OZQ_CANCELS2_CANC_L2D_ST 417 { "L2_OZQ_CANCELS2_CANC_L2D_ST", {0xd00a8}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 2) -- caused by a canceled store in L2D"}, #define PME_ITA2_L2_OZQ_CANCELS2_DIDNT_RECIRC 418 { "L2_OZQ_CANCELS2_DIDNT_RECIRC", {0x900a8}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 2) -- caused because it did not recirculate"}, #define PME_ITA2_L2_OZQ_CANCELS2_D_IFET 419 { "L2_OZQ_CANCELS2_D_IFET", {0xf00a8}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 2) -- a demand ifetch"}, #define PME_ITA2_L2_OZQ_CANCELS2_L2C_ST_MAT 420 { "L2_OZQ_CANCELS2_L2C_ST_MAT", {0x200a8}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 2) -- a store match in L2C"}, #define PME_ITA2_L2_OZQ_CANCELS2_L2FILL_ST_CONF 421 { "L2_OZQ_CANCELS2_L2FILL_ST_CONF", {0x800a8}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 2) -- a L2fill and store conflict in L2C"}, #define PME_ITA2_L2_OZQ_CANCELS2_OVER_SUB 422 { "L2_OZQ_CANCELS2_OVER_SUB", {0xc00a8}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 2) -- oversubscription"}, #define PME_ITA2_L2_OZQ_CANCELS2_OZ_DATA_CONF 423 { "L2_OZQ_CANCELS2_OZ_DATA_CONF", {0x600a8}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 2) -- an OZ data conflict"}, #define PME_ITA2_L2_OZQ_CANCELS2_READ_WB_CONF 424 { "L2_OZQ_CANCELS2_READ_WB_CONF", {0x500a8}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 2) -- a write back conflict (canceling read?)"}, #define PME_ITA2_L2_OZQ_CANCELS2_RECIRC_OVER_SUB 425 { "L2_OZQ_CANCELS2_RECIRC_OVER_SUB", {0xa8}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 2) -- caused by a recirculate oversubscription"}, #define PME_ITA2_L2_OZQ_CANCELS2_SCRUB 426 { "L2_OZQ_CANCELS2_SCRUB", {0x300a8}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 2) -- 32/64 byte HPW/L2D fill which needs scrub"}, #define PME_ITA2_L2_OZQ_CANCELS2_WEIRD 427 { "L2_OZQ_CANCELS2_WEIRD", {0xa00a8}, 0xf0, 4, {0x4020007}, "L2 OZQ Cancels (Specific Reason Set 2) -- counts the cancels caused by attempted 5-cycle bypasses for non-aligned accesses and bypasses blocking recirculates for too long"}, #define PME_ITA2_L2_OZQ_FULL_THIS 428 { "L2_OZQ_FULL_THIS", {0xbc}, 0xf0, 1, {0x4520000}, "L2D OZQ Is Full -- L2D OZQ is full"}, #define PME_ITA2_L2_OZQ_RELEASE 429 { "L2_OZQ_RELEASE", {0xa3}, 0xf0, 1, {0x4020000}, "Clocks With Release Ordering Attribute Existed in L2 OZQ"}, #define PME_ITA2_L2_REFERENCES 430 { "L2_REFERENCES", {0xb1}, 0xf0, 4, {0x4120007}, "Requests Made To L2"}, #define PME_ITA2_L2_STORE_HIT_SHARED_ANY 431 { "L2_STORE_HIT_SHARED_ANY", {0xba}, 0xf0, 2, {0x4320007}, "Store Hit a Shared Line -- Store hit a shared line"}, #define PME_ITA2_L2_SYNTH_PROBE 432 { "L2_SYNTH_PROBE", {0xb7}, 0xf0, 1, {0x4220007}, "Synthesized Probe"}, #define PME_ITA2_L2_VICTIMB_FULL_THIS 433 { "L2_VICTIMB_FULL_THIS", {0xbe}, 0xf0, 1, {0x4520000}, "L2D Victim Buffer Is Full -- L2D victim buffer is full"}, #define PME_ITA2_L3_LINES_REPLACED 434 { "L3_LINES_REPLACED", {0xdf}, 0xf0, 1, {0xf00000}, "L3 Cache Lines Replaced"}, #define PME_ITA2_L3_MISSES 435 { "L3_MISSES", {0xdc}, 0xf0, 1, {0xf00007}, "L3 Misses"}, #define PME_ITA2_L3_READS_ALL_ALL 436 { "L3_READS_ALL_ALL", {0xf00dd}, 0xf0, 1, {0xf00007}, "L3 Reads -- L3 Read References"}, #define PME_ITA2_L3_READS_ALL_HIT 437 { "L3_READS_ALL_HIT", {0xd00dd}, 0xf0, 1, {0xf00007}, "L3 Reads -- L3 Read Hits"}, #define PME_ITA2_L3_READS_ALL_MISS 438 { "L3_READS_ALL_MISS", {0xe00dd}, 0xf0, 1, {0xf00007}, "L3 Reads -- L3 Read Misses"}, #define PME_ITA2_L3_READS_DATA_READ_ALL 439 { "L3_READS_DATA_READ_ALL", {0xb00dd}, 0xf0, 1, {0xf00007}, "L3 Reads -- L3 Load References (excludes reads for ownership used to satisfy stores)"}, #define PME_ITA2_L3_READS_DATA_READ_HIT 440 { "L3_READS_DATA_READ_HIT", {0x900dd}, 0xf0, 1, {0xf00007}, "L3 Reads -- L3 Load Hits (excludes reads for ownership used to satisfy stores)"}, #define PME_ITA2_L3_READS_DATA_READ_MISS 441 { "L3_READS_DATA_READ_MISS", {0xa00dd}, 0xf0, 1, {0xf00007}, "L3 Reads -- L3 Load Misses (excludes reads for ownership used to satisfy stores)"}, #define PME_ITA2_L3_READS_DINST_FETCH_ALL 442 { "L3_READS_DINST_FETCH_ALL", {0x300dd}, 0xf0, 1, {0xf00007}, "L3 Reads -- L3 Demand Instruction References"}, #define PME_ITA2_L3_READS_DINST_FETCH_HIT 443 { "L3_READS_DINST_FETCH_HIT", {0x100dd}, 0xf0, 1, {0xf00007}, "L3 Reads -- L3 Demand Instruction Fetch Hits"}, #define PME_ITA2_L3_READS_DINST_FETCH_MISS 444 { "L3_READS_DINST_FETCH_MISS", {0x200dd}, 0xf0, 1, {0xf00007}, "L3 Reads -- L3 Demand Instruction Fetch Misses"}, #define PME_ITA2_L3_READS_INST_FETCH_ALL 445 { "L3_READS_INST_FETCH_ALL", {0x700dd}, 0xf0, 1, {0xf00007}, "L3 Reads -- L3 Instruction Fetch and Prefetch References"}, #define PME_ITA2_L3_READS_INST_FETCH_HIT 446 { "L3_READS_INST_FETCH_HIT", {0x500dd}, 0xf0, 1, {0xf00007}, "L3 Reads -- L3 Instruction Fetch and Prefetch Hits"}, #define PME_ITA2_L3_READS_INST_FETCH_MISS 447 { "L3_READS_INST_FETCH_MISS", {0x600dd}, 0xf0, 1, {0xf00007}, "L3 Reads -- L3 Instruction Fetch and Prefetch Misses"}, #define PME_ITA2_L3_REFERENCES 448 { "L3_REFERENCES", {0xdb}, 0xf0, 1, {0xf00007}, "L3 References"}, #define PME_ITA2_L3_WRITES_ALL_ALL 449 { "L3_WRITES_ALL_ALL", {0xf00de}, 0xf0, 1, {0xf00007}, "L3 Writes -- L3 Write References"}, #define PME_ITA2_L3_WRITES_ALL_HIT 450 { "L3_WRITES_ALL_HIT", {0xd00de}, 0xf0, 1, {0xf00007}, "L3 Writes -- L3 Write Hits"}, #define PME_ITA2_L3_WRITES_ALL_MISS 451 { "L3_WRITES_ALL_MISS", {0xe00de}, 0xf0, 1, {0xf00007}, "L3 Writes -- L3 Write Misses"}, #define PME_ITA2_L3_WRITES_DATA_WRITE_ALL 452 { "L3_WRITES_DATA_WRITE_ALL", {0x700de}, 0xf0, 1, {0xf00007}, "L3 Writes -- L3 Store References (excludes L2 write backs, includes L3 read for ownership requests that satisfy stores)"}, #define PME_ITA2_L3_WRITES_DATA_WRITE_HIT 453 { "L3_WRITES_DATA_WRITE_HIT", {0x500de}, 0xf0, 1, {0xf00007}, "L3 Writes -- L3 Store Hits (excludes L2 write backs, includes L3 read for ownership requests that satisfy stores)"}, #define PME_ITA2_L3_WRITES_DATA_WRITE_MISS 454 { "L3_WRITES_DATA_WRITE_MISS", {0x600de}, 0xf0, 1, {0xf00007}, "L3 Writes -- L3 Store Misses (excludes L2 write backs, includes L3 read for ownership requests that satisfy stores)"}, #define PME_ITA2_L3_WRITES_L2_WB_ALL 455 { "L3_WRITES_L2_WB_ALL", {0xb00de}, 0xf0, 1, {0xf00007}, "L3 Writes -- L2 Write Back References"}, #define PME_ITA2_L3_WRITES_L2_WB_HIT 456 { "L3_WRITES_L2_WB_HIT", {0x900de}, 0xf0, 1, {0xf00007}, "L3 Writes -- L2 Write Back Hits"}, #define PME_ITA2_L3_WRITES_L2_WB_MISS 457 { "L3_WRITES_L2_WB_MISS", {0xa00de}, 0xf0, 1, {0xf00007}, "L3 Writes -- L2 Write Back Misses"}, #define PME_ITA2_LOADS_RETIRED 458 { "LOADS_RETIRED", {0xcd}, 0xf0, 4, {0x5310007}, "Retired Loads"}, #define PME_ITA2_MEM_READ_CURRENT_ANY 459 { "MEM_READ_CURRENT_ANY", {0x30089}, 0xf0, 1, {0xf00000}, "Current Mem Read Transactions On Bus -- CPU or non-CPU (all transactions)."}, #define PME_ITA2_MEM_READ_CURRENT_IO 460 { "MEM_READ_CURRENT_IO", {0x10089}, 0xf0, 1, {0xf00000}, "Current Mem Read Transactions On Bus -- non-CPU priority agents"}, #define PME_ITA2_MISALIGNED_LOADS_RETIRED 461 { "MISALIGNED_LOADS_RETIRED", {0xce}, 0xf0, 4, {0x5310007}, "Retired Misaligned Load Instructions"}, #define PME_ITA2_MISALIGNED_STORES_RETIRED 462 { "MISALIGNED_STORES_RETIRED", {0xd2}, 0xf0, 2, {0x5410007}, "Retired Misaligned Store Instructions"}, #define PME_ITA2_NOPS_RETIRED 463 { "NOPS_RETIRED", {0x50}, 0xf0, 6, {0xf00003}, "Retired NOP Instructions"}, #define PME_ITA2_PREDICATE_SQUASHED_RETIRED 464 { "PREDICATE_SQUASHED_RETIRED", {0x51}, 0xf0, 6, {0xf00003}, "Instructions Squashed Due to Predicate Off"}, #define PME_ITA2_RSE_CURRENT_REGS_2_TO_0 465 { "RSE_CURRENT_REGS_2_TO_0", {0x2b}, 0xf0, 7, {0xf00000}, "Current RSE Registers (Bits 2:0)"}, #define PME_ITA2_RSE_CURRENT_REGS_5_TO_3 466 { "RSE_CURRENT_REGS_5_TO_3", {0x2a}, 0xf0, 7, {0xf00000}, "Current RSE Registers (Bits 5:3)"}, #define PME_ITA2_RSE_CURRENT_REGS_6 467 { "RSE_CURRENT_REGS_6", {0x26}, 0xf0, 1, {0xf00000}, "Current RSE Registers (Bit 6)"}, #define PME_ITA2_RSE_DIRTY_REGS_2_TO_0 468 { "RSE_DIRTY_REGS_2_TO_0", {0x29}, 0xf0, 7, {0xf00000}, "Dirty RSE Registers (Bits 2:0)"}, #define PME_ITA2_RSE_DIRTY_REGS_5_TO_3 469 { "RSE_DIRTY_REGS_5_TO_3", {0x28}, 0xf0, 7, {0xf00000}, "Dirty RSE Registers (Bits 5:3)"}, #define PME_ITA2_RSE_DIRTY_REGS_6 470 { "RSE_DIRTY_REGS_6", {0x24}, 0xf0, 1, {0xf00000}, "Dirty RSE Registers (Bit 6)"}, #define PME_ITA2_RSE_EVENT_RETIRED 471 { "RSE_EVENT_RETIRED", {0x32}, 0xf0, 1, {0xf00000}, "Retired RSE operations"}, #define PME_ITA2_RSE_REFERENCES_RETIRED_ALL 472 { "RSE_REFERENCES_RETIRED_ALL", {0x30020}, 0xf0, 2, {0xf00007}, "RSE Accesses -- Both RSE loads and stores will be counted."}, #define PME_ITA2_RSE_REFERENCES_RETIRED_LOAD 473 { "RSE_REFERENCES_RETIRED_LOAD", {0x10020}, 0xf0, 2, {0xf00007}, "RSE Accesses -- Only RSE loads will be counted."}, #define PME_ITA2_RSE_REFERENCES_RETIRED_STORE 474 { "RSE_REFERENCES_RETIRED_STORE", {0x20020}, 0xf0, 2, {0xf00007}, "RSE Accesses -- Only RSE stores will be counted."}, #define PME_ITA2_SERIALIZATION_EVENTS 475 { "SERIALIZATION_EVENTS", {0x53}, 0xf0, 1, {0xf00000}, "Number of srlz.i Instructions"}, #define PME_ITA2_STORES_RETIRED 476 { "STORES_RETIRED", {0xd1}, 0xf0, 2, {0x5410007}, "Retired Stores"}, #define PME_ITA2_SYLL_NOT_DISPERSED_ALL 477 { "SYLL_NOT_DISPERSED_ALL", {0xf004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Counts all syllables not dispersed. NOTE: Any combination of b0000-b1111 is valid."}, #define PME_ITA2_SYLL_NOT_DISPERSED_EXPL 478 { "SYLL_NOT_DISPERSED_EXPL", {0x1004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Count syllables not dispersed due to explicit stop bits. These consist of programmer specified architected S-bit and templates 1 and 5. Dispersal takes a 6-syllable (3-syllable) hit for every template 1/5 in bundle 0(1). Dispersal takes a 3-syllable (0 syllable) hit for every S-bit in bundle 0(1)"}, #define PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_FE 479 { "SYLL_NOT_DISPERSED_EXPL_OR_FE", {0x5004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Count syllables not dispersed due to explicit stop bits or front-end not providing valid bundles or providing valid illegal templates."}, #define PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_FE_OR_MLI 480 { "SYLL_NOT_DISPERSED_EXPL_OR_FE_OR_MLI", {0xd004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Count syllables not dispersed due to explicit stop bits or due to front-end not providing valid bundles or providing valid illegal templates or due to MLI bundle and resteers to non-0 syllable."}, #define PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_IMPL 481 { "SYLL_NOT_DISPERSED_EXPL_OR_IMPL", {0x3004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Count syllables not dispersed due to explicit/implicit stop bits."}, #define PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_IMPL_OR_FE 482 { "SYLL_NOT_DISPERSED_EXPL_OR_IMPL_OR_FE", {0x7004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Count syllables not dispersed due to explicit or implicit stop bits or due to front-end not providing valid bundles or providing valid illegal template."}, #define PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_IMPL_OR_MLI 483 { "SYLL_NOT_DISPERSED_EXPL_OR_IMPL_OR_MLI", {0xb004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Count syllables not dispersed due to explicit or implicit stop bits or due to MLI bundle and resteers to non-0 syllable."}, #define PME_ITA2_SYLL_NOT_DISPERSED_EXPL_OR_MLI 484 { "SYLL_NOT_DISPERSED_EXPL_OR_MLI", {0x9004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Count syllables not dispersed due to explicit stop bits or to MLI bundle and resteers to non-0 syllable."}, #define PME_ITA2_SYLL_NOT_DISPERSED_FE 485 { "SYLL_NOT_DISPERSED_FE", {0x4004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Count syllables not dispersed due to front-end not providing valid bundles or providing valid illegal templates. Dispersal takes a 3-syllable hit for every invalid bundle or valid illegal template from front-end. Bundle 1 with front-end fault, is counted here (3-syllable hit).."}, #define PME_ITA2_SYLL_NOT_DISPERSED_FE_OR_MLI 486 { "SYLL_NOT_DISPERSED_FE_OR_MLI", {0xc004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Count syllables not dispersed due to MLI bundle and resteers to non-0 syllable or due to front-end not providing valid bundles or providing valid illegal templates."}, #define PME_ITA2_SYLL_NOT_DISPERSED_IMPL 487 { "SYLL_NOT_DISPERSED_IMPL", {0x2004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Count syllables not dispersed due to implicit stop bits. These consist of all of the non-architected stop bits (asymmetry, oversubscription, implicit). Dispersal takes a 6-syllable(3-syllable) hit for every implicit stop bits in bundle 0(1)."}, #define PME_ITA2_SYLL_NOT_DISPERSED_IMPL_OR_FE 488 { "SYLL_NOT_DISPERSED_IMPL_OR_FE", {0x6004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Count syllables not dispersed due to implicit stop bits or to front-end not providing valid bundles or providing valid illegal templates."}, #define PME_ITA2_SYLL_NOT_DISPERSED_IMPL_OR_FE_OR_MLI 489 { "SYLL_NOT_DISPERSED_IMPL_OR_FE_OR_MLI", {0xe004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Count syllables not dispersed due to implicit stop bits or due to front-end not providing valid bundles or providing valid illegal templates or due to MLI bundle and resteers to non-0 syllable."}, #define PME_ITA2_SYLL_NOT_DISPERSED_IMPL_OR_MLI 490 { "SYLL_NOT_DISPERSED_IMPL_OR_MLI", {0xa004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Count syllables not dispersed due to implicit stop bits or to MLI bundle and resteers to non-0 syllable."}, #define PME_ITA2_SYLL_NOT_DISPERSED_MLI 491 { "SYLL_NOT_DISPERSED_MLI", {0x8004e}, 0xf0, 5, {0xf00001}, "Syllables Not Dispersed -- Count syllables not dispersed due to MLI bundle and resteers to non-0 syllable. Dispersal takes a 1 syllable hit for each MLI bundle . Dispersal could take 0-2 syllable hit depending on which syllable we resteer to. Bundle 1 with front-end fault which is split, is counted here (0-2 syllable hit)."}, #define PME_ITA2_SYLL_OVERCOUNT_ALL 492 { "SYLL_OVERCOUNT_ALL", {0x3004f}, 0xf0, 2, {0xf00001}, "Syllables Overcounted -- syllables overcounted in implicit & explicit bucket"}, #define PME_ITA2_SYLL_OVERCOUNT_EXPL 493 { "SYLL_OVERCOUNT_EXPL", {0x1004f}, 0xf0, 2, {0xf00001}, "Syllables Overcounted -- Only syllables overcounted in the explicit bucket"}, #define PME_ITA2_SYLL_OVERCOUNT_IMPL 494 { "SYLL_OVERCOUNT_IMPL", {0x2004f}, 0xf0, 2, {0xf00001}, "Syllables Overcounted -- Only syllables overcounted in the implicit bucket"}, #define PME_ITA2_UC_LOADS_RETIRED 495 { "UC_LOADS_RETIRED", {0xcf}, 0xf0, 4, {0x5310007}, "Retired Uncacheable Loads"}, #define PME_ITA2_UC_STORES_RETIRED 496 { "UC_STORES_RETIRED", {0xd0}, 0xf0, 2, {0x5410007}, "Retired Uncacheable Stores"}, }; #define PME_ITA2_EVENT_COUNT 497 papi-5.5.1/src/libpfm-3.y/lib/pfmlib_core_priv.h0000644000307100002310000000534413013651450021370 0ustar yarkhangraduate/* * Copyright (c) 2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #ifndef __PFMLIB_CORE_PRIV_H__ #define __PFMLIB_CORE_PRIV_H__ #define PFMLIB_CORE_MAX_UMASK 32 typedef struct { char *pme_uname; /* unit mask name */ char *pme_udesc; /* event/umask description */ unsigned int pme_ucode; /* unit mask code */ unsigned int pme_flags; /* unit mask flags */ } pme_core_umask_t; typedef struct { char *pme_name; /* event name */ char *pme_desc; /* event description */ unsigned int pme_code; /* event code */ unsigned int pme_numasks; /* number of umasks */ unsigned int pme_flags; /* flags */ pme_core_umask_t pme_umasks[PFMLIB_CORE_MAX_UMASK]; /* umask desc */ } pme_core_entry_t; /* * pme_flags value (event and unit mask) */ /* event or unit-mask level constraints */ #define PFMLIB_CORE_FIXED0 0x02 /* event supported by FIXED_CTR0, can work on generic counters */ #define PFMLIB_CORE_FIXED1 0x04 /* event supported by FIXED_CTR1, can work on generic counters */ #define PFMLIB_CORE_FIXED2_ONLY 0x08 /* works only on FIXED_CTR2 */ /* event-level constraints */ #define PFMLIB_CORE_UMASK_NCOMBO 0x01 /* unit mask cannot be combined (default: combination ok) */ #define PFMLIB_CORE_CSPEC 0x40 /* requires a core specification */ #define PFMLIB_CORE_PEBS 0x20 /* support PEBS (precise event) */ #define PFMLIB_CORE_PMC0 0x10 /* works only on IA32_PMC0 */ #define PFMLIB_CORE_PMC1 0x80 /* works only on IA32_PMC1 */ #define PFMLIB_CORE_MESI 0x100 /* requires MESI */ #endif /* __PFMLIB_CORE_PRIV_H__ */ papi-5.5.1/src/libpfm-3.y/lib/powerpc_events.h0000644000307100002310000000225513013651450021110 0ustar yarkhangraduate/* * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. * * powerpc_events.h */ #ifndef _POWERPC_EVENTS_H_ #define _POWERPC_EVENTS_H_ #define PME_INSTR_COMPLETED 1 #endif papi-5.5.1/src/libpfm-3.y/lib/pfmlib_power_priv.h0000644000307100002310000000165313013651450021573 0ustar yarkhangraduate/****************************/ /* THIS IS OPEN SOURCE CODE */ /****************************/ #ifndef __PFMLIB_POWER_PRIV_H__ #define __PFMLIB_POWER_PRIV_H__ /* * File: pfmlib_power_priv.h * CVS: * Author: Corey Ashford * cjashfor@us.ibm.com * Mods: * * * (C) Copyright IBM Corporation, 2007. All Rights Reserved. * Contributed by Corey Ashford * * Note: This code was automatically generated and should not be modified by * hand. * */ typedef struct { char *pme_name; unsigned pme_code; char *pme_short_desc; char *pme_long_desc; const int *pme_event_ids; const unsigned long long *pme_group_vector; } pme_power_entry_t; typedef struct { char *pmg_name; char *pmg_desc; const int *pmg_event_ids; unsigned long long pmg_mmcr0; unsigned long long pmg_mmcr1; unsigned long long pmg_mmcra; } pmg_power_group_t; #endif papi-5.5.1/src/libpfm-3.y/lib/crayx2_events.h0000644000307100002310000311152713013651450020647 0ustar yarkhangraduate/* * Copyright (c) 2007 Cray Inc. * Contributed by Steve Kaufmann based on code from * Copyright (c) 2001-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef __CRAYX2_EVENTS_H__ #define __CRAYX2_EVENTS_H__ 1 #include "pfmlib_crayx2_priv.h" /* ***************************************************************** ******* THIS TABLE IS GENERATED AUTOMATICALLY ******* MODIFICATIONS REQUIRED FOR THE EVENT NAMES ******* OR EVENT DESCRIPTIONS SHOULD BE MADE TO ******* THE TEXT FILE AND THE TABLE REGENERATED ******* Sat Nov 10 14:40:30 CST 2007 ***************************************************************** */ static pme_crayx2_entry_t crayx2_pe[ ] = { /* P Counter 0 Event 0 */ { .pme_name = "CYCLES", .pme_desc = "Cycles.", .pme_code = 0, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 0, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 0 Event 1 */ { .pme_name = "CYCLES", .pme_desc = "Cycles.", .pme_code = 1, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 0, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 0 Event 2 */ { .pme_name = "CYCLES", .pme_desc = "Cycles.", .pme_code = 2, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 0, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 0 Event 3 */ { .pme_name = "CYCLES", .pme_desc = "Cycles.", .pme_code = 3, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 0, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 1 Event 0 */ { .pme_name = "INST_GRAD", .pme_desc = "Number of instructions graduated.", .pme_code = 4, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 1, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 1 Event 1 */ { .pme_name = "INST_GRAD", .pme_desc = "Number of instructions graduated.", .pme_code = 5, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 1, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 1 Event 2 */ { .pme_name = "INST_GRAD", .pme_desc = "Number of instructions graduated.", .pme_code = 6, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 1, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 1 Event 3 */ { .pme_name = "INST_GRAD", .pme_desc = "Number of instructions graduated.", .pme_code = 7, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 1, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 2 Event 0 */ { .pme_name = "INST_DISPATCH", .pme_desc = "Number of instructions dispatched.", .pme_code = 8, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 2, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 2 Event 1 */ { .pme_name = "ITLB_MISS", .pme_desc = "Number of Instruction TLB misses.", .pme_code = 9, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 2, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 2 Event 2 */ { .pme_name = "JB_CORRECT", .pme_desc = "Number of jumps and branches predicted correctly.", .pme_code = 10, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 2, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 2 Event 3 */ { .pme_name = "STALL_VU_FUG1", .pme_desc = "CPs VU stalled waiting for FUG 1.", .pme_code = 11, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 2, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 3 Event 0 */ { .pme_name = "INST_SYNCS", .pme_desc = "Number of synchronization instructions graduated g=02.", .pme_code = 12, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 3, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 3 Event 1 */ { .pme_name = "INST_GSYNCS", .pme_desc = "Number of Gsync instructions graduated g=02 & f=0-3.", .pme_code = 13, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 3, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 3 Event 2 */ { .pme_name = "STALL_DU_ICACHE", .pme_desc = "CPs dispatch stalled waiting for instruction from Icache.", .pme_code = 14, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 3, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 3 Event 3 */ { .pme_name = "STALL_VU_FUG2", .pme_desc = "CPs VU stalled waiting for FUG 2.", .pme_code = 15, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 3, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 4 Event 0 */ { .pme_name = "INST_AMO", .pme_desc = "Number of AMO instructions graduated g=04.", .pme_code = 16, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 4, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 4 Event 1 */ { .pme_name = "ICACHE_FETCH", .pme_desc = "Number of instruction fetch requests to memory.", .pme_code = 17, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 4, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 4 Event 2 */ { .pme_name = "STALL_DU_BRANCH_PRED", .pme_desc = "CPs Dispatch stalled waiting for branch prediction register.", .pme_code = 18, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 4, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 4 Event 3 */ { .pme_name = "STALL_VU_FUG3", .pme_desc = "CPs VU stalled waiting for FUG 3.", .pme_code = 19, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 4, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 5 Event 0 */ { .pme_name = "INST_A", .pme_desc = "Number of A register instructions graduated g=05,40,42,43.", .pme_code = 20, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 5, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 5 Event 1 */ { .pme_name = "ICACHE_HIT", .pme_desc = "Number of Icache hits.", .pme_code = 21, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 5, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 5 Event 2 */ { .pme_name = "STALL_DU_AREG", .pme_desc = "CPs instruction dispatch stalled waiting for free A register.", .pme_code = 22, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 5, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 5 Event 3 */ { .pme_name = "STALL_VU", .pme_desc = "CPs VU is stalled with a valid instruction.", .pme_code = 23, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 5, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 6 Event 0 */ { .pme_name = "INST_S_INT", .pme_desc = "Number of S register integer instructions graduated g=60,62 & t1=1,63.", .pme_code = 24, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 6, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 6 Event 1 */ { .pme_name = "INST_MSYNCS", .pme_desc = "Number of Msync instructions graduated g=02 & f=20-22.", .pme_code = 25, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 6, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 6 Event 2 */ { .pme_name = "STALL_DU_ACT_LIST_FULL", .pme_desc = "CPs dispatch stalled waiting for active list entry.", .pme_code = 26, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 6, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 6 Event 3 */ { .pme_name = "STALL_VU_NO_INST", .pme_desc = "CPs VU has no valid instruction.", .pme_code = 27, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 6, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 7 Event 0 */ { .pme_name = "INST_S_FP", .pme_desc = "Number of S register FP instructions graduated g=62 & t1=0.", .pme_code = 28, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 7, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 7 Event 1 */ { .pme_name = "STLB_MISS", .pme_desc = "Number of Scalar TLB misses.", .pme_code = 29, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 7, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 7 Event 2 */ { .pme_name = "STALL_DU_SREG", .pme_desc = "CPs instruction dispatch stalled waiting for free S register.", .pme_code = 30, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 7, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 7 Event 3 */ { .pme_name = "STALL_VU_VR", .pme_desc = "CPs VU is stalled waiting for busy V Reg.", .pme_code = 31, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 7, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 8 Event 0 */ { .pme_name = "INST_MISC", .pme_desc = "Number of Misc. scalar instructions graduated g=00, 01, 03, 06, 34.", .pme_code = 32, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 8, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 8 Event 1 */ { .pme_name = "VTLB_MISS", .pme_desc = "Number of vector TLB misses.", .pme_code = 33, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 8, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 8 Event 2 */ { .pme_name = "STALL_DU_INST", .pme_desc = "CPs dispatch stalled due to an instruction such as a Gsync or Lsync FP that stops dispatch until it executes.", .pme_code = 34, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 8, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 8 Event 3 */ { .pme_name = "STALL_VLSU_NO_INST", .pme_desc = "CPs VLSU has no valid instruction.", .pme_code = 35, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 8, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 9 Event 0 */ { .pme_name = "INST_JB", .pme_desc = "Number of Jump and Branch instructions graduated g=50-57, 70-76.", .pme_code = 36, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 9, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 9 Event 1 */ { .pme_name = "ICACHE_MISS", .pme_desc = "Number of Icache misses.", .pme_code = 37, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 9, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 9 Event 2 */ { .pme_name = "STALL_GRAD", .pme_desc = "CPs no instructions graduate for any reason.", .pme_code = 38, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 9, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 9 Event 3 */ { .pme_name = "STALL_VLSU_LB", .pme_desc = "CPs VLSU stalled waiting for load buffers (LB).", .pme_code = 39, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 9, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 10 Event 0 */ { .pme_name = "INST_MEM", .pme_desc = "Number of A and S register load and store instructions graduated g=41, 44-47, 61, 64-67.", .pme_code = 40, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 10, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 10 Event 1 */ { .pme_name = "ICACHE_HIT_PEND", .pme_desc = "Number of Icache hits to blocks with allocations pending.", .pme_code = 41, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 10, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 10 Event 2 */ { .pme_name = "STALL_GRAD_NO_INST", .pme_desc = "CPs no instructions graduated due to empty active list.", .pme_code = 42, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 10, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 10 Event 3 */ { .pme_name = "STALL_VLSU_SB", .pme_desc = "CPs VLSU stalled waiting for store buffer (SB).", .pme_code = 43, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 10, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 11 Event 0 */ { .pme_name = "INST_VFUG1", .pme_desc = "Number of vector FUG 1 instructions graduated g=20-27, f=0-7,60-77 Add, sub, compare.", .pme_code = 44, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 11, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 11 Event 1 */ { .pme_name = "TLB_MISS", .pme_desc = "Total number of TLB misses including ITLB, STLB, and VTLB.", .pme_code = 45, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 11, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 11 Event 2 */ { .pme_name = "STALL_GRAD_AX_INST", .pme_desc = "CPs no instructions graduate and an A FUG instruction is at the head of the active list g=5, 40, 42, 43.", .pme_code = 46, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 11, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 11 Event 3 */ { .pme_name = "STALL_VLSU_RB", .pme_desc = "CPs VLSU stalled waiting for request buffer (RB).", .pme_code = 47, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 11, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 12 Event 0 */ { .pme_name = "INST_VFUG2", .pme_desc = "Number of vector FUG 2 instructions graduated g=20-27, f=30-37 (multiply, shift).", .pme_code = 48, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 12, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 12 Event 1 */ { .pme_name = "DCACHE_HIT", .pme_desc = "Number of A or S loads that hit in the Dcache.", .pme_code = 49, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 12, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 12 Event 2 */ { .pme_name = "STALL_GRAD_SX_INST", .pme_desc = "CPs no instructions graduate and an S FUG instruction is at the head of the active list g=60, 62, 63.", .pme_code = 50, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 12, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 12 Event 3 */ { .pme_name = "STALL_VLSU_VM", .pme_desc = "CPs VLSU stalled waiting for VU vector mask (VM).", .pme_code = 51, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 12, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 13 Event 0 */ { .pme_name = "INST_VFUG3", .pme_desc = "Number of vector FUG 3 instructions graduated g=20-27, f=10-27, 40-57, 77 div, sqrt, abs, cpsign, compress, merge, logical, bmm.", .pme_code = 52, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 13, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 13 Event 1 */ { .pme_name = "DCACHE_MISS", .pme_desc = "Number of A or S loads that miss in the Dcache.", .pme_code = 53, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 13, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 13 Event 2 */ { .pme_name = "STALL_GRAD_FP_INST", .pme_desc = "CPs no instructions graduate and an S FP instruction is at the head of the active list g=62, t1=0.", .pme_code = 54, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 13, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 13 Event 3 */ { .pme_name = "STALL_VLSU_SREF", .pme_desc = "CPs VLSU stalled waiting for prior scalar instruction reference sent.", .pme_code = 55, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 13, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 14 Event 0 */ { .pme_name = "VOPS_EXT_FUG3", .pme_desc = "Number of vector FUG 3 external operations g=20-27 f=25,57,77 compress, merge, bmm.", .pme_code = 56, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 14, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 14 Event 1 */ { .pme_name = "DCACHE_HIT_PEND", .pme_desc = "Number of scalar loads that hit in the Dcache and in the FOQ and the load is merged with a pending allocation.", .pme_code = 57, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 14, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 14 Event 2 */ { .pme_name = "STALL_GRAD_LOAD_INST", .pme_desc = "CPs no instructions graduate and a scalar load is at the head of the active list.", .pme_code = 58, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 14, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 14 Event 3 */ { .pme_name = "STALL_VLSU_INDEX", .pme_desc = "CPS VLSU stalled waiting for busy scatter or gather index register.", .pme_code = 59, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 14, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 15 Event 0 */ { .pme_name = "VOPS_LOG_FUG3", .pme_desc = "Number of vector FUG 3 logical operations.", .pme_code = 60, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 15, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 15 Event 1 */ { .pme_name = "DCACHE_HIT_WORD", .pme_desc = "Number of scalar loads that hit in the Dcache and hit in the FOQ and were not merged with a pending allocation.", .pme_code = 61, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 15, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 15 Event 2 */ { .pme_name = "STALL_GRAD_STORE_INST", .pme_desc = "CPs no instructions graduate and a scalar store is at the head of the active list.", .pme_code = 62, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 15, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 15 Event 3 */ { .pme_name = "STALL_VLSU_FOM", .pme_desc = "CPs VLSU stalled in forced order mode.", .pme_code = 63, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 15, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 16 Event 0 */ { .pme_name = "INST_V", .pme_desc = "Number of elemental vector instructions graduated g=20-27, 30-33.", .pme_code = 64, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 16, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 16 Event 1 */ { .pme_name = "INST_V_INT", .pme_desc = "Number of elemental vector integer instructions graduated g=20-27 & t1=", .pme_code = 65, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 16, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 16 Event 2 */ { .pme_name = "INST_V_FP", .pme_desc = "Number of elemental vector FP instructions graduated g=20-27 & t1=0.", .pme_code = 66, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 16, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 16 Event 3 */ { .pme_name = "INST_V_MEM", .pme_desc = "Number of elemental vector memory instructions graduated g=30-33.", .pme_code = 67, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 16, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 17 Event 0 */ { .pme_name = "VOPS_VL", .pme_desc = "Inst_V * Current VL.", .pme_code = 68, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 17, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 17 Event 1 */ { .pme_name = "DCACHE_INVAL_V", .pme_desc = "Number of Dcache invalidates due to vector stores.", .pme_code = 69, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 17, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 17 Event 2 */ { .pme_name = "VOPS_VL_32-BIT", .pme_desc = "Inst_V * Current VL for 32-bit operations only.", .pme_code = 70, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 17, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 17 Event 3 */ { .pme_name = "STALL_VLSU", .pme_desc = "Stall vector load store for any reason.", .pme_code = 71, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 17, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 18 Event 0 */ { .pme_name = "VOPS_INT_ADD", .pme_desc = "Number of selected vector integer add operations g=20-27 & f=0-3 & t1=", .pme_code = 72, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 18, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 18 Event 1 */ { .pme_name = "DCACHE_INVAL_L2", .pme_desc = "Number of Dcache invalidates from L2 cache.", .pme_code = 73, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 18, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 18 Event 2 */ { .pme_name = "STALL_GRAD_XFER_INST", .pme_desc = "Number of CPs no instruction graduates and an A to S or S to A move is at the head of the active list.", .pme_code = 74, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 18, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 18 Event 3 */ { .pme_name = "STALL_VU_VM", .pme_desc = "CPs VU stalled waiting for vector mask.", .pme_code = 75, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 18, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 19 Event 0 */ { .pme_name = "VOPS_FP_ADD", .pme_desc = "Number of selected vector FP add operations g=20-27 & f=0-3 & t1=0.", .pme_code = 76, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 19, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 19 Event 1 */ { .pme_name = "DCACHE_INVALIDATE", .pme_desc = "Total Number of Dcache invalidates.", .pme_code = 77, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 19, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 19 Event 2 */ { .pme_name = "STALL_GRAD_VXFER_INST", .pme_desc = "CPs no instruction graduates and a V to A or V to S move is at the head of the active list.", .pme_code = 78, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 19, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 19 Event 3 */ { .pme_name = "STALL_VU_VR_MEM", .pme_desc = "CPs VU is stalled waiting on a busy vector register being loaded from memory.", .pme_code = 79, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 19, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 20 Event 0 */ { .pme_name = "VOPS_INT_LOG", .pme_desc = "Number of selected vector integer logical operations g=20-27 & f=10-27 & t1=1.", .pme_code = 80, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 20, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 20 Event 1 */ { .pme_name = "BRANCH_PRED", .pme_desc = "Number of branches predicted.", .pme_code = 81, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 20, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 20 Event 2 */ { .pme_name = "STALL_GRAD_VLSU_INST", .pme_desc = "Number of CPs no instruction graduates and a vector load, store, or AMO instruction is at the head of the active list.", .pme_code = 82, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 20, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 20 Event 3 */ { .pme_name = "STALL_VU_TLB", .pme_desc = "CPs VU stalled waiting for a memory translation.", .pme_code = 83, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 20, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 21 Event 0 */ { .pme_name = "VOPS_FP_DIV", .pme_desc = "Number of selected vector FP divide and sqrt operations g=20-27 & f=10-11 & t1=0.", .pme_code = 84, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 21, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 21 Event 1 */ { .pme_name = "BRANCH_CORRECT", .pme_desc = "Number of branches predicted correctly.", .pme_code = 85, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 21, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 21 Event 2 */ { .pme_name = "STALL_SLSQ_DEST", .pme_desc = "SLS issue stall for FOQ, PARB, ORB full or Lsync vs active.", .pme_code = 86, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 21, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 21 Event 3 */ { .pme_name = "STALL_VLSU_VK_PORT", .pme_desc = "CPs VLSU stalled waiting for scatter or gather index register read port.", .pme_code = 87, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 21, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 22 Event 0 */ { .pme_name = "VOPS_INT_SHIFT", .pme_desc = "Number of selected vector integer shift operations g=20-27 & f=30-37 & t1=", .pme_code = 88, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 22, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 22 Event 1 */ { .pme_name = "JTB_PRED", .pme_desc = "Number of jumps predicted g=57 & f=0,20.", .pme_code = 89, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 22, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 22 Event 2 */ { .pme_name = "STALL_GRAD_ARQ_DEST", .pme_desc = "Stall arq issue due to vdispatch, control unit, or A to S full.", .pme_code = 90, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 22, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 22 Event 3 */ { .pme_name = "STALL_VLSU_ADR_PORT", .pme_desc = "CPs VLSU stalled waiting for address read port.", .pme_code = 91, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 22, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 23 Event 0 */ { .pme_name = "VOPS_FP_MULT", .pme_desc = "Number of selected vector FP multiply operations g=20-27 & f=30-37 & t1=0.", .pme_code = 92, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 23, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 23 Event 1 */ { .pme_name = "JTB_CORRECT", .pme_desc = "Number of jumps predicted correctly g=57 & f=0,20.", .pme_code = 93, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 23, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 23 Event 2 */ { .pme_name = "STALL_SRQ_DEST", .pme_desc = "Stall srq issue due to vdispatch or S to A full.", .pme_code = 94, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 23, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 23 Event 3 */ { .pme_name = "STALL_VLSU_MISC", .pme_desc = "CPs VLSU stalled due to miscellaneous instructions.", .pme_code = 95, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 23, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 24 Event 0 */ { .pme_name = "VOPS_LOAD_INDEX", .pme_desc = "Number of selected vector load indexed references g=30-33 & f2=1 & f0=0.", .pme_code = 96, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 24, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 24 Event 1 */ { .pme_name = "VOPS_INT_MISC", .pme_desc = "Number of selected vector integer misc. operations g=20-27 & f=40-77 & t1=", .pme_code = 97, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 24, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 24 Event 2 */ { .pme_name = "INST_LSYNCVS", .pme_desc = "Number of LsyncVS instructions graduated.", .pme_code = 98, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 24, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 24 Event 3 */ { .pme_name = "VOPS_VL_64-BIT", .pme_desc = "Inst_V * Current VL for 64-bit operations only.", .pme_code = 99, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 24, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 25 Event 0 */ { .pme_name = "VOPS_STORE_INDEX", .pme_desc = "Number of selected vector store indexed references g=30-33 & f2=1 & f0=1", .pme_code = 100, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 25, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 25 Event 1 */ { .pme_name = "JRS_PRED", .pme_desc = "Number of return jumps predicted g=57, f=40.", .pme_code = 101, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 25, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 25 Event 2 */ { .pme_name = "STALL_SLSQ_PARB", .pme_desc = "Number of CPs SLS issue stalled due to PARB full.", .pme_code = 102, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 25, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 25 Event 3 */ { .pme_name = "", .pme_desc = "", .pme_code = 103, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 25, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 26 Event 0 */ { .pme_name = "VOPS_LOADS", .pme_desc = "Number of selected vector load references g=30-33 & f0=0.", .pme_code = 104, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 26, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 26 Event 1 */ { .pme_name = "JRS_CORRECT", .pme_desc = "Number of return jumps predicted correctly g=57, f=40.", .pme_code = 105, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 26, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 26 Event 2 */ { .pme_name = "STALL_SLSQ_ORB", .pme_desc = "Number of CPs SLS issue stalled due to all ORB entries in use.", .pme_code = 106, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 26, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 26 Event 3 */ { .pme_name = "STALL_VU_MISC", .pme_desc = "CPs VU stalled due to miscellaneous instructions.", .pme_code = 107, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 26, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 27 Event 0 */ { .pme_name = "VOPS_STORE", .pme_desc = "Number of selected vector store references g=30-33 & f0=", .pme_code = 108, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 27, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 27 Event 1 */ { .pme_name = "INST_MEM_ALLOC", .pme_desc = "Number of A and S register memory instructions that allocate.", .pme_code = 109, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 27, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 27 Event 2 */ { .pme_name = "STALL_SLSQ_FOQ", .pme_desc = "Number of CPs SLS issue stalled due to full FOQ.", .pme_code = 110, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 27, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 27 Event 3 */ { .pme_name = "STALL_VDU_NO_INST_VU", .pme_desc = "CPs VDU and VU have no valid instructions.", .pme_code = 111, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 27, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 28 Event 0 */ { .pme_name = "VOPS_LOAD_STRIDE", .pme_desc = "Number of selected vector load references that were stride >2 or <-2.", .pme_code = 112, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 28, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 28 Event 1 */ { .pme_name = "INST_SYSCALL", .pme_desc = "Number of syscall instructions graduated g=01.", .pme_code = 113, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 28, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 28 Event 2 */ { .pme_name = "STALL_SLSQ_LSYNC_VS", .pme_desc = "Number of CPs SLS issue is stalled due to active Lsync vs instruction.", .pme_code = 114, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 28, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 28 Event 3 */ { .pme_name = "STALL_VDU_SOP_VU", .pme_desc = "Number of CPs vector issue has no instructions and the next instruction is waiting on an S reg operand.", .pme_code = 115, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 28, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 29 Event 0 */ { .pme_name = "VOPS_STORE_STRIDE", .pme_desc = "Number of selected vector store references that were stride >2 or <-2.", .pme_code = 116, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 29, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 29 Event 1 */ { .pme_name = "", .pme_desc = "", .pme_code = 117, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 29, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 29 Event 2 */ { .pme_name = "", .pme_desc = "", .pme_code = 118, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 29, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 29 Event 3 */ { .pme_name = "STALL_VDU_NO_INST_VLSU", .pme_desc = "CPs VDU and VLSU have no valid instructions.", .pme_code = 119, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 29, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 30 Event 0 */ { .pme_name = "VOPS_LOAD_ALLOC", .pme_desc = "Number of selected vector load references that were marked allocate (cache line requests count as 1).", .pme_code = 120, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 30, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 30 Event 1 */ { .pme_name = "INST_LOAD", .pme_desc = "Number of A or S memory loads g=44, 45, 41 & f0=0, 64, 65, 61 & f0=0.", .pme_code = 121, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 30, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 30 Event 2 */ { .pme_name = "EXCEPTIONS_TAKEN", .pme_desc = "Taken exception count.", .pme_code = 122, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 30, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 30 Event 3 */ { .pme_name = "STALL_VDU_SCM_VLSU", .pme_desc = "CPs VDU stalled waiting for scalar commit and VLSU has no valid instruction.", .pme_code = 123, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 30, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 31 Event 0 */ { .pme_name = "VOPS_STORE_ALLOC", .pme_desc = "Number of selected vector stores references that were marked allocate (cache line requests count as 1).", .pme_code = 124, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 31, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 31 Event 1 */ { .pme_name = "BRANCH_TAKEN", .pme_desc = "Number of taken branches.", .pme_code = 125, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 31, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 31 Event 2 */ { .pme_name = "INST_LSYNCSV", .pme_desc = "Number of graduated Lsync SV instructions.", .pme_code = 126, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 31, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* P Counter 31 Event 3 */ { .pme_name = "STALL_VDU_SCM_VU", .pme_desc = "CPs VDU stalled waiting for scalar commit and VU has no valid instruction.", .pme_code = 127, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CPU, .pme_ctr = 31, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CPU_PMD_BASE, .pme_nctrs = PME_CRAYX2_CPU_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CPU_CHIPS }, /* C Counter 0 Event 0 */ { .pme_name = "REQUESTS", .pme_desc = "Processor requests processed.", .pme_code = 128, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 0, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 0 Event 1 */ { .pme_name = "L2_MISSES", .pme_desc = "Cache line allocations.", .pme_code = 129, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 0, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 0 Event 2 */ { .pme_name = "M_OUT_BUSY", .pme_desc = "Cycles W chip output port busy.", .pme_code = 130, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 0, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 0 Event 3 */ { .pme_name = "REPLAYED", .pme_desc = "Requests sent to replay queue.", .pme_code = 131, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 0, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 1 Event 0 */ { .pme_name = "ALLOC_REQUESTS", .pme_desc = "Allocating requests (Read, ReadUC, ReadShared, ReadUCShared, ReadMod, SWrite, VWrite).", .pme_code = 132, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 1, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 1 Event 1 */ { .pme_name = "", .pme_desc = "", .pme_code = 133, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 1, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 1 Event 2 */ { .pme_name = "M_OUT_BLOCK", .pme_desc = "CyclesWchip output port blocked (something to send but no flow control credits).", .pme_code = 134, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 1, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 1 Event 3 */ { .pme_name = "LS/VS", .pme_desc = "Replayed Ls or Vs Requests sent to the replay queue.", .pme_code = 135, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 1, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 2 Event 0 */ { .pme_name = "DWORDS_ALLOCATED", .pme_desc = "Dwords written into L2 from L3 (excluding updates).", .pme_code = 136, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 2, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 2 Event 1 */ { .pme_name = "", .pme_desc = "", .pme_code = 137, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 2, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 2 Event 2 */ { .pme_name = "NW_OUT_BUSY", .pme_desc = "Cycles NIF output port busy.", .pme_code = 138, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 2, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 2 Event 3 */ { .pme_name = "REPLAY_PENDING", .pme_desc = "Requests sent to replay queue because the line was in PendingReq state.", .pme_code = 139, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 2, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 3 Event 0 */ { .pme_name = "DWORDS_EVICTED", .pme_desc = "Dwords written back to L3.", .pme_code = 140, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 3, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 3 Event 1 */ { .pme_name = "CACHE_LINE_EVICTIONS", .pme_desc = "Cache lines evicted due to new allocations.", .pme_code = 141, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 3, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 3 Event 2 */ { .pme_name = "NW_OUT_BLOCK", .pme_desc = "Cycles NIF output port blocked (something to send but no flow control credits).", .pme_code = 142, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 3, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 3 Event 3 */ { .pme_name = "REPLAY_ALLOC", .pme_desc = "Requests sent to replay queue because a line could not be allocated due to all ways pending.", .pme_code = 143, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 3, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 4 Event 0 */ { .pme_name = "ALLOC_WRITE_TO_L2", .pme_desc = "Dwords written to L2 by local allocating write requests.", .pme_code = 144, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 4, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 4 Event 1 */ { .pme_name = "DROPS", .pme_desc = "Drops sent to directory.", .pme_code = 145, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 4, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 4 Event 2 */ { .pme_name = "", .pme_desc = "", .pme_code = 146, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 4, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 4 Event 3 */ { .pme_name = "REPLAY_WAKEUPS", .pme_desc = "Replay queue wakeups.", .pme_code = 147, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 4, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 5 Event 0 */ { .pme_name = "NON_ALLOC_WRITE_TO_L2", .pme_desc = "Dwords written to L2 by local non-allocating write requests.", .pme_code = 148, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 5, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 5 Event 1 */ { .pme_name = "WRITE_BACKS", .pme_desc = "WriteBacks sent to directory.", .pme_code = 149, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 5, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 5 Event 2 */ { .pme_name = "", .pme_desc = "", .pme_code = 150, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 5, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 5 Event 3 */ { .pme_name = "REPLAY_MATCHES", .pme_desc = "Requests matched during replay wakeups (Replay_Matches/Replay_Wakeups=avg. number of matches per wakeup).", .pme_code = 151, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 5, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 6 Event 0 */ { .pme_name = "NON_ALLOC_WRITE_TO_L3", .pme_desc = "Dwords written to L3 by local non-allocating write requests.", .pme_code = 152, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 6, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 6 Event 1 */ { .pme_name = "FWD_REQ", .pme_desc = "Forwarded requests received (FlushReq, FwdRead, FwdReadShared, FwdGet).", .pme_code = 153, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 6, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 6 Event 2 */ { .pme_name = "", .pme_desc = "", .pme_code = 154, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 6, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 6 Event 3 */ { .pme_name = "", .pme_desc = "", .pme_code = 155, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 6, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 7 Event 0 */ { .pme_name = "ALLOC_READ_FROM_L2", .pme_desc = "Dwords read from L2 by local allocating read requests.", .pme_code = 156, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 7, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 7 Event 1 */ { .pme_name = "FWD_READ_ALL", .pme_desc = "FwdReads and FwdReadShared received.", .pme_code = 157, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 7, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 7 Event 2 */ { .pme_name = "STALL_RP_FULL_NW", .pme_desc = "Cycles NW request queue stalled due to replay queue full.", .pme_code = 158, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 7, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 7 Event 3 */ { .pme_name = "ALLOC_NO_FILL", .pme_desc = "ReadMods sent to directory when the entire line is dirty.", .pme_code = 159, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 7, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 8 Event 0 */ { .pme_name = "NON_ALLOC_READ_FROM_L2", .pme_desc = "Dwords read from L2 by local non-allocating read requests.", .pme_code = 160, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 8, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 8 Event 1 */ { .pme_name = "FWD_READ_SHARED_RECV", .pme_desc = "FwdReadShareds received.", .pme_code = 161, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 8, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 8 Event 2 */ { .pme_name = "STALL_RP_FULL_PROC", .pme_desc = "Cycles Ls/Vs request queue stalled due to replay queue full.", .pme_code = 162, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 8, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 8 Event 3 */ { .pme_name = "UPGRADES", .pme_desc = "ReadMods sent to directory when the line was currently in ShClean state.", .pme_code = 163, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 8, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 9 Event 0 */ { .pme_name = "NON_ALLOC_READ_FROM_L3", .pme_desc = "Dwords read from L3 by local non-allocating read requests.", .pme_code = 164, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 9, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 9 Event 1 */ { .pme_name = "FWD_GET_RECV", .pme_desc = "FwdGets received.", .pme_code = 165, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 9, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 9 Event 2 */ { .pme_name = "STALL_TB_FULL", .pme_desc = "Cycles bank request queue stalled due to transient buffer full.", .pme_code = 166, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 9, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 9 Event 3 */ { .pme_name = "", .pme_desc = "", .pme_code = 167, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 9, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 10 Event 0 */ { .pme_name = "NETWORK_WRITE_TO_L2", .pme_desc = "Dwords written to L2 by remote write requests.", .pme_code = 168, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 10, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 10 Event 1 */ { .pme_name = "FLUSH_REQ", .pme_desc = "FlushReqs received.", .pme_code = 169, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 10, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 10 Event 2 */ { .pme_name = "STALL_VWRITENA", .pme_desc = "Cycles bank request queue stalled due to VWriteNA bit being set.", .pme_code = 170, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 10, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 10 Event 3 */ { .pme_name = "", .pme_desc = "", .pme_code = 171, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 10, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 11 Event 0 */ { .pme_name = "NETWORK_WRITE_TO_L3", .pme_desc = "Dwords written to L3 by remote write requests.", .pme_code = 172, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 11, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 11 Event 1 */ { .pme_name = "UPDATES_RECV", .pme_desc = "Updates received.", .pme_code = 173, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 11, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 11 Event 2 */ { .pme_name = "PROT_ENGINE_IDLE_NO_REQUEST", .pme_desc = "Cycles protocol engine idle due to no new requests to process.", .pme_code = 174, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 11, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 11 Event 3 */ { .pme_name = "READ_DATA_TO_VECTOR_UNIT_PIPE_0_3", .pme_desc = "Swords delivered to vector unit via pipes 0 - 3.", .pme_code = 175, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 11, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 12 Event 0 */ { .pme_name = "NETWORK_READ_FROM_L2", .pme_desc = "Dwords read from L2 by remote read requests.", .pme_code = 176, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 12, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 12 Event 1 */ { .pme_name = "", .pme_desc = "", .pme_code = 177, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 12, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 12 Event 2 */ { .pme_name = "UPDATE_NACK_SENT", .pme_desc = "UpdateNacks sent.", .pme_code = 178, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 12, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 12 Event 3 */ { .pme_name = "READ_DATA_TO_VECTOR_UNIT_PIPE_4_7", .pme_desc = "Swords delivered to vector unit via pipes 4 - 7.", .pme_code = 179, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 12, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 13 Event 0 */ { .pme_name = "NETWORK_READ_FROM_L3", .pme_desc = "Dwords read from L3 by remote read requests.", .pme_code = 180, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 13, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 13 Event 1 */ { .pme_name = "NACKS_SENT", .pme_desc = "FlushAcks and UpdateNacks sent (these happen when there's a race b/w a forwarded request and an eviction by the current owner).", .pme_code = 181, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 13, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 13 Event 2 */ { .pme_name = "INVAL_RECV", .pme_desc = "Inval packets received from the directory.", .pme_code = 182, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 13, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 13 Event 3 */ { .pme_name = "READ_DATA_TO_SCALAR_UNIT", .pme_desc = "Dwords delivered to scalar unit.", .pme_code = 183, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 13, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 14 Event 0 */ { .pme_name = "REMOTE_READS", .pme_desc = "Dwords read from remote nodes.", .pme_code = 184, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 14, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 14 Event 1 */ { .pme_name = "LOCAL_INVAL", .pme_desc = "Local writes that cause invals of other Dcaches.", .pme_code = 185, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 14, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 14 Event 2 */ { .pme_name = "MARKED_REQS", .pme_desc = "Memory requests sent with TID 0.", .pme_code = 186, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 14, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 14 Event 3 */ { .pme_name = "READ_DATA_TO_ICACHE", .pme_desc = "Dwords delivered to Icache.", .pme_code = 187, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 14, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 15 Event 0 */ { .pme_name = "REMOTE_WRITES", .pme_desc = "Dwords written to remote nodes.", .pme_code = 188, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 15, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 15 Event 1 */ { .pme_name = "DCACHE_INVAL_EVENTS", .pme_desc = "State transitions (evictions, directory Invals or forwards, processor writes) requiring Dcache invals.", .pme_code = 189, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 15, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 15 Event 2 */ { .pme_name = "MARKED_CYCLES", .pme_desc = "Cycles with a TID 0 request outstanding.", .pme_code = 190, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 15, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* C Counter 15 Event 3 */ { .pme_name = "READ_DATA_TO_NIF", .pme_desc = "Dwords delivered to NIF.", .pme_code = 191, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_CACHE, .pme_ctr = 15, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_CACHE_PMD_BASE, .pme_nctrs = PME_CRAYX2_CACHE_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_CACHE_CHIPS }, /* M Counter 0 Event 0 */ { .pme_name = "W_IN_IDLE_0@0", .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 0)", .pme_code = 192, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_0@1", .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 1)", .pme_code = 193, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 0, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_0@2", .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 2)", .pme_code = 194, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 0, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_0@3", .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 3)", .pme_code = 195, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 0, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_0@4", .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 4)", .pme_code = 196, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 0, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_0@5", .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 5)", .pme_code = 197, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 0, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_0@6", .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 6)", .pme_code = 198, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 0, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_0@7", .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 7)", .pme_code = 199, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 0, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_0@8", .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 8)", .pme_code = 200, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 0, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_0@9", .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 9)", .pme_code = 201, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 0, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_0@10", .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 10)", .pme_code = 202, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 0, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_0@11", .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 11)", .pme_code = 203, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 0, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_0@12", .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 12)", .pme_code = 204, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 0, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_0@13", .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 13)", .pme_code = 205, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 0, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_0@14", .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 14)", .pme_code = 206, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 0, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_0@15", .pme_desc = "Wclk cycles BW2MD input port 0 is idle (no flits in either VC0 or VC2). (M chip 15)", .pme_code = 207, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 0, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 0 Event 1 */ { .pme_name = "STALL_REPLAY_FULL@0", .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 0)", .pme_code = 208, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_REPLAY_FULL@1", .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 1)", .pme_code = 209, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 1, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_REPLAY_FULL@2", .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 2)", .pme_code = 210, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 1, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_REPLAY_FULL@3", .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 3)", .pme_code = 211, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 1, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_REPLAY_FULL@4", .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 4)", .pme_code = 212, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 1, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_REPLAY_FULL@5", .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 5)", .pme_code = 213, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 1, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_REPLAY_FULL@6", .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 6)", .pme_code = 214, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 1, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_REPLAY_FULL@7", .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 7)", .pme_code = 215, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 1, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_REPLAY_FULL@8", .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 8)", .pme_code = 216, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 1, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_REPLAY_FULL@9", .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 9)", .pme_code = 217, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 1, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_REPLAY_FULL@10", .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 10)", .pme_code = 218, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 1, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_REPLAY_FULL@11", .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 11)", .pme_code = 219, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 1, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_REPLAY_FULL@12", .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 12)", .pme_code = 220, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 1, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_REPLAY_FULL@13", .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 13)", .pme_code = 221, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 1, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_REPLAY_FULL@14", .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 14)", .pme_code = 222, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 1, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_REPLAY_FULL@15", .pme_desc = "Wclk cycles protocol engine request queue stalled due to replay queue full (sum of 4 engines). (M chip 15)", .pme_code = 223, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 1, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 0 Event 2 */ { .pme_name = "W_OUT_IDLE_0@0", .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 0)", .pme_code = 224, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_0@1", .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 1)", .pme_code = 225, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 2, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_0@2", .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 2)", .pme_code = 226, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 2, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_0@3", .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 3)", .pme_code = 227, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 2, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_0@4", .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 4)", .pme_code = 228, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 2, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_0@5", .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 5)", .pme_code = 229, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 2, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_0@6", .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 6)", .pme_code = 230, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 2, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_0@7", .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 7)", .pme_code = 231, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 2, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_0@8", .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 8)", .pme_code = 232, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 2, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_0@9", .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 9)", .pme_code = 233, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 2, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_0@10", .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 10)", .pme_code = 234, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 2, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_0@11", .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 11)", .pme_code = 235, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 2, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_0@12", .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 12)", .pme_code = 236, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 2, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_0@13", .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 13)", .pme_code = 237, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 2, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_0@14", .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 14)", .pme_code = 238, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 2, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_0@15", .pme_desc = "Wclk cycles MD2BW output port 0 is idle (no flits flowing). (M chip 15)", .pme_code = 239, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 2, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 0 Event 3 */ { .pme_name = "@0", .pme_desc = "", .pme_code = 240, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@1", .pme_desc = "", .pme_code = 241, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 3, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@2", .pme_desc = "", .pme_code = 242, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 3, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@3", .pme_desc = "", .pme_code = 243, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 3, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@4", .pme_desc = "", .pme_code = 244, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 3, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@5", .pme_desc = "", .pme_code = 245, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 3, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@6", .pme_desc = "", .pme_code = 246, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 3, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@7", .pme_desc = "", .pme_code = 247, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 3, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@8", .pme_desc = "", .pme_code = 248, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 3, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@9", .pme_desc = "", .pme_code = 249, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 3, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@10", .pme_desc = "", .pme_code = 250, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 3, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@11", .pme_desc = "", .pme_code = 251, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 3, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@12", .pme_desc = "", .pme_code = 252, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 3, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@13", .pme_desc = "", .pme_code = 253, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 3, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@14", .pme_desc = "", .pme_code = 254, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 3, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@15", .pme_desc = "", .pme_code = 255, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 0, .pme_event = 3, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 1 Event 0 */ { .pme_name = "W_IN_IDLE_1@0", .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 0)", .pme_code = 256, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_1@1", .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 1)", .pme_code = 257, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 0, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_1@2", .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 2)", .pme_code = 258, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 0, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_1@3", .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 3)", .pme_code = 259, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 0, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_1@4", .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 4)", .pme_code = 260, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 0, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_1@5", .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 5)", .pme_code = 261, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 0, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_1@6", .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 6)", .pme_code = 262, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 0, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_1@7", .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 7)", .pme_code = 263, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 0, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_1@8", .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 8)", .pme_code = 264, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 0, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_1@9", .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 9)", .pme_code = 265, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 0, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_1@10", .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 10)", .pme_code = 266, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 0, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_1@11", .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 11)", .pme_code = 267, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 0, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_1@12", .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 12)", .pme_code = 268, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 0, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_1@13", .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 13)", .pme_code = 269, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 0, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_1@14", .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 14)", .pme_code = 270, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 0, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_1@15", .pme_desc = "Wclk cycles BW2MD input port 1 is idle (no flits in either VC0 or VC2). (M chip 15)", .pme_code = 271, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 0, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 1 Event 1 */ { .pme_name = "STALL_TDB_FULL@0", .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 0)", .pme_code = 272, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_TDB_FULL@1", .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 1)", .pme_code = 273, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 1, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_TDB_FULL@2", .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 2)", .pme_code = 274, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 1, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_TDB_FULL@3", .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 3)", .pme_code = 275, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 1, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_TDB_FULL@4", .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 4)", .pme_code = 276, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 1, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_TDB_FULL@5", .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 5)", .pme_code = 277, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 1, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_TDB_FULL@6", .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 6)", .pme_code = 278, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 1, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_TDB_FULL@7", .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 7)", .pme_code = 279, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 1, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_TDB_FULL@8", .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 8)", .pme_code = 280, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 1, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_TDB_FULL@9", .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 9)", .pme_code = 281, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 1, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_TDB_FULL@10", .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 10)", .pme_code = 282, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 1, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_TDB_FULL@11", .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 11)", .pme_code = 283, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 1, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_TDB_FULL@12", .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 12)", .pme_code = 284, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 1, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_TDB_FULL@13", .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 13)", .pme_code = 285, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 1, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_TDB_FULL@14", .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 14)", .pme_code = 286, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 1, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_TDB_FULL@15", .pme_desc = "Wclk cycles protocol engine request queue stalled due to transient directory buffer full (sum of 4 engines). (M chip 15)", .pme_code = 287, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 1, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 1 Event 2 */ { .pme_name = "W_OUT_IDLE_1@0", .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 0)", .pme_code = 288, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_1@1", .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 1)", .pme_code = 289, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 2, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_1@2", .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 2)", .pme_code = 290, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 2, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_1@3", .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 3)", .pme_code = 291, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 2, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_1@4", .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 4)", .pme_code = 292, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 2, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_1@5", .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 5)", .pme_code = 293, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 2, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_1@6", .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 6)", .pme_code = 294, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 2, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_1@7", .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 7)", .pme_code = 295, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 2, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_1@8", .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 8)", .pme_code = 296, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 2, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_1@9", .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 9)", .pme_code = 297, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 2, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_1@10", .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 10)", .pme_code = 298, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 2, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_1@11", .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 11)", .pme_code = 299, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 2, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_1@12", .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 12)", .pme_code = 300, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 2, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_1@13", .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 13)", .pme_code = 301, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 2, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_1@14", .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 14)", .pme_code = 302, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 2, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_1@15", .pme_desc = "Wclk cycles MD2BW output port 1 is idle (no flits flowing). (M chip 15)", .pme_code = 303, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 2, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 1 Event 3 */ { .pme_name = "FWD_READ_SHARED_SENT@0", .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 0)", .pme_code = 304, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ_SHARED_SENT@1", .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 1)", .pme_code = 305, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 3, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ_SHARED_SENT@2", .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 2)", .pme_code = 306, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 3, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ_SHARED_SENT@3", .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 3)", .pme_code = 307, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 3, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ_SHARED_SENT@4", .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 4)", .pme_code = 308, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 3, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ_SHARED_SENT@5", .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 5)", .pme_code = 309, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 3, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ_SHARED_SENT@6", .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 6)", .pme_code = 310, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 3, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ_SHARED_SENT@7", .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 7)", .pme_code = 311, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 3, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ_SHARED_SENT@8", .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 8)", .pme_code = 312, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 3, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ_SHARED_SENT@9", .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 9)", .pme_code = 313, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 3, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ_SHARED_SENT@10", .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 10)", .pme_code = 314, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 3, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ_SHARED_SENT@11", .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 11)", .pme_code = 315, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 3, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ_SHARED_SENT@12", .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 12)", .pme_code = 316, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 3, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ_SHARED_SENT@13", .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 13)", .pme_code = 317, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 3, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ_SHARED_SENT@14", .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 14)", .pme_code = 318, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 3, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ_SHARED_SENT@15", .pme_desc = "FwdReadShared packets sent (Exclusive -> PendFwd transition). (M chip 15)", .pme_code = 319, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 1, .pme_event = 3, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 2 Event 0 */ { .pme_name = "UPDATES_SENT@0", .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 0)", .pme_code = 320, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATES_SENT@1", .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 1)", .pme_code = 321, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 0, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATES_SENT@2", .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 2)", .pme_code = 322, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 0, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATES_SENT@3", .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 3)", .pme_code = 323, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 0, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATES_SENT@4", .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 4)", .pme_code = 324, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 0, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATES_SENT@5", .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 5)", .pme_code = 325, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 0, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATES_SENT@6", .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 6)", .pme_code = 326, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 0, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATES_SENT@7", .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 7)", .pme_code = 327, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 0, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATES_SENT@8", .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 8)", .pme_code = 328, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 0, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATES_SENT@9", .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 9)", .pme_code = 329, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 0, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATES_SENT@10", .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 10)", .pme_code = 330, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 0, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATES_SENT@11", .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 11)", .pme_code = 331, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 0, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATES_SENT@12", .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 12)", .pme_code = 332, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 0, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATES_SENT@13", .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 13)", .pme_code = 333, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 0, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATES_SENT@14", .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 14)", .pme_code = 334, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 0, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATES_SENT@15", .pme_desc = "Puts that cause an Update to be sent to owner. (M chip 15)", .pme_code = 335, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 0, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 2 Event 1 */ { .pme_name = "STALL_MM_RESPQ@0", .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 0)", .pme_code = 336, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM_RESPQ@1", .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 1)", .pme_code = 337, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 1, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM_RESPQ@2", .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 2)", .pme_code = 338, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 1, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM_RESPQ@3", .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 3)", .pme_code = 339, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 1, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM_RESPQ@4", .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 4)", .pme_code = 340, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 1, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM_RESPQ@5", .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 5)", .pme_code = 341, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 1, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM_RESPQ@6", .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 6)", .pme_code = 342, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 1, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM_RESPQ@7", .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 7)", .pme_code = 343, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 1, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM_RESPQ@8", .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 8)", .pme_code = 344, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 1, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM_RESPQ@9", .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 9)", .pme_code = 345, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 1, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM_RESPQ@10", .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 10)", .pme_code = 346, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 1, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM_RESPQ@11", .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 11)", .pme_code = 347, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 1, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM_RESPQ@12", .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 12)", .pme_code = 348, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 1, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM_RESPQ@13", .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 13)", .pme_code = 349, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 1, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM_RESPQ@14", .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 14)", .pme_code = 350, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 1, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM_RESPQ@15", .pme_desc = "Wclk cycles protocol engine request queue stalled due to MM VN1 response queue full (sum of 4 engines). (M chip 15)", .pme_code = 351, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 1, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 2 Event 2 */ { .pme_name = "W_OUT_IDLE_2@0", .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 0)", .pme_code = 352, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_2@1", .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 1)", .pme_code = 353, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 2, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_2@2", .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 2)", .pme_code = 354, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 2, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_2@3", .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 3)", .pme_code = 355, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 2, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_2@4", .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 4)", .pme_code = 356, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 2, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_2@5", .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 5)", .pme_code = 357, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 2, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_2@6", .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 6)", .pme_code = 358, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 2, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_2@7", .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 7)", .pme_code = 359, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 2, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_2@8", .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 8)", .pme_code = 360, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 2, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_2@9", .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 9)", .pme_code = 361, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 2, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_2@10", .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 10)", .pme_code = 362, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 2, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_2@11", .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 11)", .pme_code = 363, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 2, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_2@12", .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 12)", .pme_code = 364, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 2, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_2@13", .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 13)", .pme_code = 365, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 2, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_2@14", .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 14)", .pme_code = 366, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 2, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_2@15", .pme_desc = "Wclk cycles MD2BW output port 2 is idle (no flits flowing). (M chip 15)", .pme_code = 367, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 2, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 2 Event 3 */ { .pme_name = "W_IN_IDLE_2@0", .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 0)", .pme_code = 368, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_2@1", .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 1)", .pme_code = 369, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 3, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_2@2", .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 2)", .pme_code = 370, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 3, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_2@3", .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 3)", .pme_code = 371, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 3, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_2@4", .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 4)", .pme_code = 372, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 3, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_2@5", .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 5)", .pme_code = 373, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 3, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_2@6", .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 6)", .pme_code = 374, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 3, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_2@7", .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 7)", .pme_code = 375, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 3, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_2@8", .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 8)", .pme_code = 376, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 3, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_2@9", .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 9)", .pme_code = 377, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 3, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_2@10", .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 10)", .pme_code = 378, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 3, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_2@11", .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 11)", .pme_code = 379, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 3, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_2@12", .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 12)", .pme_code = 380, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 3, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_2@13", .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 13)", .pme_code = 381, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 3, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_2@14", .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 14)", .pme_code = 382, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 3, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_2@15", .pme_desc = "Wclk cycles BW2MD input port 2 is idle (no flits in either VC0 or VC2). (M chip 15)", .pme_code = 383, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 2, .pme_event = 3, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 3 Event 0 */ { .pme_name = "NON_CACHED@0", .pme_desc = "Read requests satisfied from non-cached state. (M chip 0)", .pme_code = 384, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NON_CACHED@1", .pme_desc = "Read requests satisfied from non-cached state. (M chip 1)", .pme_code = 385, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 0, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NON_CACHED@2", .pme_desc = "Read requests satisfied from non-cached state. (M chip 2)", .pme_code = 386, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 0, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NON_CACHED@3", .pme_desc = "Read requests satisfied from non-cached state. (M chip 3)", .pme_code = 387, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 0, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NON_CACHED@4", .pme_desc = "Read requests satisfied from non-cached state. (M chip 4)", .pme_code = 388, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 0, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NON_CACHED@5", .pme_desc = "Read requests satisfied from non-cached state. (M chip 5)", .pme_code = 389, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 0, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NON_CACHED@6", .pme_desc = "Read requests satisfied from non-cached state. (M chip 6)", .pme_code = 390, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 0, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NON_CACHED@7", .pme_desc = "Read requests satisfied from non-cached state. (M chip 7)", .pme_code = 391, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 0, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NON_CACHED@8", .pme_desc = "Read requests satisfied from non-cached state. (M chip 8)", .pme_code = 392, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 0, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NON_CACHED@9", .pme_desc = "Read requests satisfied from non-cached state. (M chip 9)", .pme_code = 393, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 0, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NON_CACHED@10", .pme_desc = "Read requests satisfied from non-cached state. (M chip 10)", .pme_code = 394, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 0, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NON_CACHED@11", .pme_desc = "Read requests satisfied from non-cached state. (M chip 11)", .pme_code = 395, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 0, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NON_CACHED@12", .pme_desc = "Read requests satisfied from non-cached state. (M chip 12)", .pme_code = 396, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 0, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NON_CACHED@13", .pme_desc = "Read requests satisfied from non-cached state. (M chip 13)", .pme_code = 397, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 0, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NON_CACHED@14", .pme_desc = "Read requests satisfied from non-cached state. (M chip 14)", .pme_code = 398, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 0, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NON_CACHED@15", .pme_desc = "Read requests satisfied from non-cached state. (M chip 15)", .pme_code = 399, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 0, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 3 Event 1 */ { .pme_name = "STALL_ASSOC@0", .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 0)", .pme_code = 400, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_ASSOC@1", .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 1)", .pme_code = 401, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 1, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_ASSOC@2", .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 2)", .pme_code = 402, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 1, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_ASSOC@3", .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 3)", .pme_code = 403, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 1, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_ASSOC@4", .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 4)", .pme_code = 404, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 1, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_ASSOC@5", .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 5)", .pme_code = 405, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 1, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_ASSOC@6", .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 6)", .pme_code = 406, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 1, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_ASSOC@7", .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 7)", .pme_code = 407, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 1, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_ASSOC@8", .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 8)", .pme_code = 408, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 1, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_ASSOC@9", .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 9)", .pme_code = 409, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 1, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_ASSOC@10", .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 10)", .pme_code = 410, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 1, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_ASSOC@11", .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 11)", .pme_code = 411, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 1, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_ASSOC@12", .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 12)", .pme_code = 412, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 1, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_ASSOC@13", .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 13)", .pme_code = 413, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 1, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_ASSOC@14", .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 14)", .pme_code = 414, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 1, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_ASSOC@15", .pme_desc = "Wclk cycles protocol engine request queue stalled due to temporary over-subscription of directory ways. (M chip 15)", .pme_code = 415, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 1, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 3 Event 2 */ { .pme_name = "W_OUT_IDLE_3@0", .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 0)", .pme_code = 416, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_3@1", .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 1)", .pme_code = 417, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 2, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_3@2", .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 2)", .pme_code = 418, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 2, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_3@3", .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 3)", .pme_code = 419, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 2, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_3@4", .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 4)", .pme_code = 420, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 2, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_3@5", .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 5)", .pme_code = 421, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 2, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_3@6", .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 6)", .pme_code = 422, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 2, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_3@7", .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 7)", .pme_code = 423, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 2, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_3@8", .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 8)", .pme_code = 424, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 2, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_3@9", .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 9)", .pme_code = 425, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 2, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_3@10", .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 10)", .pme_code = 426, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 2, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_3@11", .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 11)", .pme_code = 427, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 2, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_3@12", .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 12)", .pme_code = 428, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 2, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_3@13", .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 13)", .pme_code = 429, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 2, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_3@14", .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 14)", .pme_code = 430, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 2, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_IDLE_3@15", .pme_desc = "Wclk cycles MD2BW output port 3 is idle (no flits flowing). (M chip 15)", .pme_code = 431, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 2, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 3 Event 3 */ { .pme_name = "W_IN_IDLE_3@0", .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 0)", .pme_code = 432, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_3@1", .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 1)", .pme_code = 433, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 3, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_3@2", .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 2)", .pme_code = 434, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 3, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_3@3", .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 3)", .pme_code = 435, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 3, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_3@4", .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 4)", .pme_code = 436, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 3, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_3@5", .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 5)", .pme_code = 437, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 3, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_3@6", .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 6)", .pme_code = 438, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 3, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_3@7", .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 7)", .pme_code = 439, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 3, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_3@8", .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 8)", .pme_code = 440, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 3, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_3@9", .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 9)", .pme_code = 441, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 3, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_3@10", .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 10)", .pme_code = 442, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 3, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_3@11", .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 11)", .pme_code = 443, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 3, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_3@12", .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 12)", .pme_code = 444, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 3, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_3@13", .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 13)", .pme_code = 445, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 3, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_3@14", .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 14)", .pme_code = 446, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 3, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_IDLE_3@15", .pme_desc = "Wclk cycles BW2MD input port 3 is idle (no flits in either VC0 or VC2). (M chip 15)", .pme_code = 447, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 3, .pme_event = 3, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 4 Event 0 */ { .pme_name = "READ_REQ_SHARED@0", .pme_desc = "Read requests satisfied from the Shared state. (M chip 0)", .pme_code = 448, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "READ_REQ_SHARED@1", .pme_desc = "Read requests satisfied from the Shared state. (M chip 1)", .pme_code = 449, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 0, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "READ_REQ_SHARED@2", .pme_desc = "Read requests satisfied from the Shared state. (M chip 2)", .pme_code = 450, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 0, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "READ_REQ_SHARED@3", .pme_desc = "Read requests satisfied from the Shared state. (M chip 3)", .pme_code = 451, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 0, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "READ_REQ_SHARED@4", .pme_desc = "Read requests satisfied from the Shared state. (M chip 4)", .pme_code = 452, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 0, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "READ_REQ_SHARED@5", .pme_desc = "Read requests satisfied from the Shared state. (M chip 5)", .pme_code = 453, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 0, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "READ_REQ_SHARED@6", .pme_desc = "Read requests satisfied from the Shared state. (M chip 6)", .pme_code = 454, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 0, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "READ_REQ_SHARED@7", .pme_desc = "Read requests satisfied from the Shared state. (M chip 7)", .pme_code = 455, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 0, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "READ_REQ_SHARED@8", .pme_desc = "Read requests satisfied from the Shared state. (M chip 8)", .pme_code = 456, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 0, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "READ_REQ_SHARED@9", .pme_desc = "Read requests satisfied from the Shared state. (M chip 9)", .pme_code = 457, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 0, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "READ_REQ_SHARED@10", .pme_desc = "Read requests satisfied from the Shared state. (M chip 10)", .pme_code = 458, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 0, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "READ_REQ_SHARED@11", .pme_desc = "Read requests satisfied from the Shared state. (M chip 11)", .pme_code = 459, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 0, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "READ_REQ_SHARED@12", .pme_desc = "Read requests satisfied from the Shared state. (M chip 12)", .pme_code = 460, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 0, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "READ_REQ_SHARED@13", .pme_desc = "Read requests satisfied from the Shared state. (M chip 13)", .pme_code = 461, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 0, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "READ_REQ_SHARED@14", .pme_desc = "Read requests satisfied from the Shared state. (M chip 14)", .pme_code = 462, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 0, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "READ_REQ_SHARED@15", .pme_desc = "Read requests satisfied from the Shared state. (M chip 15)", .pme_code = 463, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 0, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 4 Event 1 */ { .pme_name = "STALL_VN1_BLOCKED@0", .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 0)", .pme_code = 464, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_VN1_BLOCKED@1", .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 1)", .pme_code = 465, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 1, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_VN1_BLOCKED@2", .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 2)", .pme_code = 466, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 1, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_VN1_BLOCKED@3", .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 3)", .pme_code = 467, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 1, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_VN1_BLOCKED@4", .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 4)", .pme_code = 468, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 1, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_VN1_BLOCKED@5", .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 5)", .pme_code = 469, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 1, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_VN1_BLOCKED@6", .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 6)", .pme_code = 470, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 1, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_VN1_BLOCKED@7", .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 7)", .pme_code = 471, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 1, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_VN1_BLOCKED@8", .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 8)", .pme_code = 472, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 1, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_VN1_BLOCKED@9", .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 9)", .pme_code = 473, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 1, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_VN1_BLOCKED@10", .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 10)", .pme_code = 474, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 1, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_VN1_BLOCKED@11", .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 11)", .pme_code = 475, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 1, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_VN1_BLOCKED@12", .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 12)", .pme_code = 476, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 1, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_VN1_BLOCKED@13", .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 13)", .pme_code = 477, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 1, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_VN1_BLOCKED@14", .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 14)", .pme_code = 478, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 1, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_VN1_BLOCKED@15", .pme_desc = "Wclk cycles protocol engine request queue stalled due to virtual network 1 output blocked. (M chip 15)", .pme_code = 479, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 1, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 4 Event 2 */ { .pme_name = "W_IN_FLOWING_0@0", .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 0)", .pme_code = 480, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_0@1", .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 1)", .pme_code = 481, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 2, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_0@2", .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 2)", .pme_code = 482, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 2, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_0@3", .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 3)", .pme_code = 483, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 2, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_0@4", .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 4)", .pme_code = 484, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 2, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_0@5", .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 5)", .pme_code = 485, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 2, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_0@6", .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 6)", .pme_code = 486, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 2, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_0@7", .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 7)", .pme_code = 487, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 2, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_0@8", .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 8)", .pme_code = 488, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 2, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_0@9", .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 9)", .pme_code = 489, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 2, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_0@10", .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 10)", .pme_code = 490, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 2, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_0@11", .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 11)", .pme_code = 491, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 2, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_0@12", .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 12)", .pme_code = 492, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 2, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_0@13", .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 13)", .pme_code = 493, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 2, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_0@14", .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 14)", .pme_code = 494, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 2, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_0@15", .pme_desc = "Wclk cycles BW2MD input port 0 has a flit flowing (on either VC0 or VC2). (M chip 15)", .pme_code = 495, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 2, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 4 Event 3 */ { .pme_name = "W_OUT_FLOWING_0@0", .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 0)", .pme_code = 496, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_0@1", .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 1)", .pme_code = 497, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 3, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_0@2", .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 2)", .pme_code = 498, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 3, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_0@3", .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 3)", .pme_code = 499, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 3, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_0@4", .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 4)", .pme_code = 500, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 3, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_0@5", .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 5)", .pme_code = 501, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 3, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_0@6", .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 6)", .pme_code = 502, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 3, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_0@7", .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 7)", .pme_code = 503, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 3, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_0@8", .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 8)", .pme_code = 504, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 3, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_0@9", .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 9)", .pme_code = 505, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 3, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_0@10", .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 10)", .pme_code = 506, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 3, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_0@11", .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 11)", .pme_code = 507, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 3, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_0@12", .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 12)", .pme_code = 508, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 3, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_0@13", .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 13)", .pme_code = 509, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 3, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_0@14", .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 14)", .pme_code = 510, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 3, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_0@15", .pme_desc = "Wclk cycles MD2BW output port 0 has a flit flowing. (M chip 15)", .pme_code = 511, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 4, .pme_event = 3, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 5 Event 0 */ { .pme_name = "FWD_REQ_TO_OWNER@0", .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 0)", .pme_code = 512, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_REQ_TO_OWNER@1", .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 1)", .pme_code = 513, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 0, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_REQ_TO_OWNER@2", .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 2)", .pme_code = 514, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 0, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_REQ_TO_OWNER@3", .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 3)", .pme_code = 515, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 0, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_REQ_TO_OWNER@4", .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 4)", .pme_code = 516, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 0, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_REQ_TO_OWNER@5", .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 5)", .pme_code = 517, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 0, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_REQ_TO_OWNER@6", .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 6)", .pme_code = 518, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 0, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_REQ_TO_OWNER@7", .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 7)", .pme_code = 519, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 0, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_REQ_TO_OWNER@8", .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 8)", .pme_code = 520, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 0, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_REQ_TO_OWNER@9", .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 9)", .pme_code = 521, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 0, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_REQ_TO_OWNER@10", .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 10)", .pme_code = 522, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 0, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_REQ_TO_OWNER@11", .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 11)", .pme_code = 523, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 0, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_REQ_TO_OWNER@12", .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 12)", .pme_code = 524, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 0, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_REQ_TO_OWNER@13", .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 13)", .pme_code = 525, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 0, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_REQ_TO_OWNER@14", .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 14)", .pme_code = 526, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 0, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_REQ_TO_OWNER@15", .pme_desc = "Requests forwarded to current owner (FwdRead, FwdReadShared, FlushReq, FwdGet, Update). (M chip 15)", .pme_code = 527, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 0, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 5 Event 1 */ { .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@0", .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 0)", .pme_code = 528, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@1", .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 1)", .pme_code = 529, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 1, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@2", .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 2)", .pme_code = 530, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 1, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@3", .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 3)", .pme_code = 531, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 1, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@4", .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 4)", .pme_code = 532, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 1, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@5", .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 5)", .pme_code = 533, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 1, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@6", .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 6)", .pme_code = 534, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 1, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@7", .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 7)", .pme_code = 535, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 1, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@8", .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 8)", .pme_code = 536, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 1, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@9", .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 9)", .pme_code = 537, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 1, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@10", .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 10)", .pme_code = 538, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 1, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@11", .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 11)", .pme_code = 539, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 1, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@12", .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 12)", .pme_code = 540, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 1, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@13", .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 13)", .pme_code = 541, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 1, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@14", .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 14)", .pme_code = 542, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 1, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PROT_ENGINE_IDLE_NO_PACKETS@15", .pme_desc = "Wclk cycles protocol engine idle due to no new packets to process. Note: The maximum packet acceptance rate into the MD is 1 packet every 2 Wclk periods. (M chip 15)", .pme_code = 543, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 1, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 5 Event 2 */ { .pme_name = "W_IN_FLOWING_1@0", .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 0)", .pme_code = 544, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_1@1", .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 1)", .pme_code = 545, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 2, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_1@2", .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 2)", .pme_code = 546, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 2, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_1@3", .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 3)", .pme_code = 547, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 2, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_1@4", .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 4)", .pme_code = 548, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 2, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_1@5", .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 5)", .pme_code = 549, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 2, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_1@6", .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 6)", .pme_code = 550, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 2, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_1@7", .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 7)", .pme_code = 551, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 2, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_1@8", .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 8)", .pme_code = 552, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 2, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_1@9", .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 9)", .pme_code = 553, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 2, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_1@10", .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 10)", .pme_code = 554, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 2, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_1@11", .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 11)", .pme_code = 555, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 2, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_1@12", .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 12)", .pme_code = 556, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 2, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_1@13", .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 13)", .pme_code = 557, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 2, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_1@14", .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 14)", .pme_code = 558, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 2, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_1@15", .pme_desc = "Wclk cycles BW2MD input port 1 has a flit flowing (on either VC0 or VC2). (M chip 15)", .pme_code = 559, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 2, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 5 Event 3 */ { .pme_name = "FWD_READ@0", .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 0)", .pme_code = 560, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ@1", .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 1)", .pme_code = 561, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 3, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ@2", .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 2)", .pme_code = 562, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 3, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ@3", .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 3)", .pme_code = 563, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 3, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ@4", .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 4)", .pme_code = 564, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 3, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ@5", .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 5)", .pme_code = 565, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 3, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ@6", .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 6)", .pme_code = 566, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 3, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ@7", .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 7)", .pme_code = 567, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 3, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ@8", .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 8)", .pme_code = 568, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 3, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ@9", .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 9)", .pme_code = 569, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 3, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ@10", .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 10)", .pme_code = 570, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 3, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ@11", .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 11)", .pme_code = 571, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 3, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ@12", .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 12)", .pme_code = 572, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 3, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ@13", .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 13)", .pme_code = 573, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 3, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ@14", .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 14)", .pme_code = 574, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 3, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_READ@15", .pme_desc = "FwdRead packets sent (Exclusive -> PendFwd transition). (M chip 15)", .pme_code = 575, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 5, .pme_event = 3, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 6 Event 0 */ { .pme_name = "SUPPLY_INV@0", .pme_desc = "SupplyInv packets received. (M chip 0)", .pme_code = 576, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_INV@1", .pme_desc = "SupplyInv packets received. (M chip 1)", .pme_code = 577, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 0, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_INV@2", .pme_desc = "SupplyInv packets received. (M chip 2)", .pme_code = 578, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 0, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_INV@3", .pme_desc = "SupplyInv packets received. (M chip 3)", .pme_code = 579, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 0, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_INV@4", .pme_desc = "SupplyInv packets received. (M chip 4)", .pme_code = 580, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 0, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_INV@5", .pme_desc = "SupplyInv packets received. (M chip 5)", .pme_code = 581, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 0, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_INV@6", .pme_desc = "SupplyInv packets received. (M chip 6)", .pme_code = 582, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 0, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_INV@7", .pme_desc = "SupplyInv packets received. (M chip 7)", .pme_code = 583, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 0, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_INV@8", .pme_desc = "SupplyInv packets received. (M chip 8)", .pme_code = 584, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 0, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_INV@9", .pme_desc = "SupplyInv packets received. (M chip 9)", .pme_code = 585, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 0, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_INV@10", .pme_desc = "SupplyInv packets received. (M chip 10)", .pme_code = 586, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 0, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_INV@11", .pme_desc = "SupplyInv packets received. (M chip 11)", .pme_code = 587, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 0, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_INV@12", .pme_desc = "SupplyInv packets received. (M chip 12)", .pme_code = 588, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 0, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_INV@13", .pme_desc = "SupplyInv packets received. (M chip 13)", .pme_code = 589, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 0, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_INV@14", .pme_desc = "SupplyInv packets received. (M chip 14)", .pme_code = 590, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 0, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_INV@15", .pme_desc = "SupplyInv packets received. (M chip 15)", .pme_code = 591, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 0, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 6 Event 1 */ { .pme_name = "NUM_REPLAY@0", .pme_desc = "Requests sent through replay queue. (M chip 0)", .pme_code = 592, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NUM_REPLAY@1", .pme_desc = "Requests sent through replay queue. (M chip 1)", .pme_code = 593, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 1, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NUM_REPLAY@2", .pme_desc = "Requests sent through replay queue. (M chip 2)", .pme_code = 594, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 1, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NUM_REPLAY@3", .pme_desc = "Requests sent through replay queue. (M chip 3)", .pme_code = 595, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 1, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NUM_REPLAY@4", .pme_desc = "Requests sent through replay queue. (M chip 4)", .pme_code = 596, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 1, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NUM_REPLAY@5", .pme_desc = "Requests sent through replay queue. (M chip 5)", .pme_code = 597, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 1, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NUM_REPLAY@6", .pme_desc = "Requests sent through replay queue. (M chip 6)", .pme_code = 598, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 1, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NUM_REPLAY@7", .pme_desc = "Requests sent through replay queue. (M chip 7)", .pme_code = 599, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 1, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NUM_REPLAY@8", .pme_desc = "Requests sent through replay queue. (M chip 8)", .pme_code = 600, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 1, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NUM_REPLAY@9", .pme_desc = "Requests sent through replay queue. (M chip 9)", .pme_code = 601, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 1, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NUM_REPLAY@10", .pme_desc = "Requests sent through replay queue. (M chip 10)", .pme_code = 602, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 1, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NUM_REPLAY@11", .pme_desc = "Requests sent through replay queue. (M chip 11)", .pme_code = 603, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 1, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NUM_REPLAY@12", .pme_desc = "Requests sent through replay queue. (M chip 12)", .pme_code = 604, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 1, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NUM_REPLAY@13", .pme_desc = "Requests sent through replay queue. (M chip 13)", .pme_code = 605, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 1, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NUM_REPLAY@14", .pme_desc = "Requests sent through replay queue. (M chip 14)", .pme_code = 606, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 1, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NUM_REPLAY@15", .pme_desc = "Requests sent through replay queue. (M chip 15)", .pme_code = 607, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 1, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 6 Event 2 */ { .pme_name = "W_IN_FLOWING_2@0", .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 0)", .pme_code = 608, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_2@1", .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 1)", .pme_code = 609, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 2, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_2@2", .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 2)", .pme_code = 610, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 2, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_2@3", .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 3)", .pme_code = 611, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 2, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_2@4", .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 4)", .pme_code = 612, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 2, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_2@5", .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 5)", .pme_code = 613, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 2, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_2@6", .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 6)", .pme_code = 614, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 2, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_2@7", .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 7)", .pme_code = 615, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 2, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_2@8", .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 8)", .pme_code = 616, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 2, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_2@9", .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 9)", .pme_code = 617, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 2, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_2@10", .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 10)", .pme_code = 618, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 2, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_2@11", .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 11)", .pme_code = 619, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 2, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_2@12", .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 12)", .pme_code = 620, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 2, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_2@13", .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 13)", .pme_code = 621, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 2, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_2@14", .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 14)", .pme_code = 622, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 2, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_2@15", .pme_desc = "Wclk cycles BW2MD input port 2 has a flit flowing (on either VC0 or VC2). (M chip 15)", .pme_code = 623, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 2, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 6 Event 3 */ { .pme_name = "INVAL_1@0", .pme_desc = "Invalidations sent to a single BW. (M chip 0)", .pme_code = 624, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_1@1", .pme_desc = "Invalidations sent to a single BW. (M chip 1)", .pme_code = 625, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 3, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_1@2", .pme_desc = "Invalidations sent to a single BW. (M chip 2)", .pme_code = 626, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 3, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_1@3", .pme_desc = "Invalidations sent to a single BW. (M chip 3)", .pme_code = 627, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 3, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_1@4", .pme_desc = "Invalidations sent to a single BW. (M chip 4)", .pme_code = 628, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 3, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_1@5", .pme_desc = "Invalidations sent to a single BW. (M chip 5)", .pme_code = 629, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 3, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_1@6", .pme_desc = "Invalidations sent to a single BW. (M chip 6)", .pme_code = 630, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 3, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_1@7", .pme_desc = "Invalidations sent to a single BW. (M chip 7)", .pme_code = 631, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 3, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_1@8", .pme_desc = "Invalidations sent to a single BW. (M chip 8)", .pme_code = 632, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 3, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_1@9", .pme_desc = "Invalidations sent to a single BW. (M chip 9)", .pme_code = 633, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 3, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_1@10", .pme_desc = "Invalidations sent to a single BW. (M chip 10)", .pme_code = 634, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 3, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_1@11", .pme_desc = "Invalidations sent to a single BW. (M chip 11)", .pme_code = 635, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 3, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_1@12", .pme_desc = "Invalidations sent to a single BW. (M chip 12)", .pme_code = 636, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 3, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_1@13", .pme_desc = "Invalidations sent to a single BW. (M chip 13)", .pme_code = 637, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 3, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_1@14", .pme_desc = "Invalidations sent to a single BW. (M chip 14)", .pme_code = 638, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 3, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_1@15", .pme_desc = "Invalidations sent to a single BW. (M chip 15)", .pme_code = 639, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 6, .pme_event = 3, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 7 Event 0 */ { .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@0", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 0)", .pme_code = 640, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@1", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 1)", .pme_code = 641, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 0, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@2", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 2)", .pme_code = 642, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 0, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@3", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 3)", .pme_code = 643, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 0, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@4", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 4)", .pme_code = 644, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 0, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@5", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 5)", .pme_code = 645, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 0, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@6", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 6)", .pme_code = 646, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 0, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@7", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 7)", .pme_code = 647, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 0, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@8", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 8)", .pme_code = 648, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 0, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@9", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 9)", .pme_code = 649, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 0, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@10", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 10)", .pme_code = 650, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 0, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@11", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 11)", .pme_code = 651, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 0, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@12", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 12)", .pme_code = 652, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 0, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@13", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 13)", .pme_code = 653, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 0, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@14", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 14)", .pme_code = 654, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 0, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_HIT@15", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 hit. (M chip 15)", .pme_code = 655, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 0, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 7 Event 1 */ { .pme_name = "@0", .pme_desc = "", .pme_code = 656, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@1", .pme_desc = "", .pme_code = 657, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 1, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@2", .pme_desc = "", .pme_code = 658, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 1, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@3", .pme_desc = "", .pme_code = 659, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 1, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@4", .pme_desc = "", .pme_code = 660, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 1, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@5", .pme_desc = "", .pme_code = 661, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 1, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@6", .pme_desc = "", .pme_code = 662, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 1, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@7", .pme_desc = "", .pme_code = 663, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 1, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@8", .pme_desc = "", .pme_code = 664, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 1, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@9", .pme_desc = "", .pme_code = 665, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 1, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@10", .pme_desc = "", .pme_code = 666, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 1, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@11", .pme_desc = "", .pme_code = 667, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 1, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@12", .pme_desc = "", .pme_code = 668, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 1, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@13", .pme_desc = "", .pme_code = 669, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 1, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@14", .pme_desc = "", .pme_code = 670, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 1, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@15", .pme_desc = "", .pme_code = 671, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 1, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 7 Event 2 */ { .pme_name = "W_IN_FLOWING_3@0", .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 0)", .pme_code = 672, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_3@1", .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 1)", .pme_code = 673, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 2, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_3@2", .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 2)", .pme_code = 674, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 2, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_3@3", .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 3)", .pme_code = 675, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 2, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_3@4", .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 4)", .pme_code = 676, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 2, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_3@5", .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 5)", .pme_code = 677, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 2, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_3@6", .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 6)", .pme_code = 678, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 2, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_3@7", .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 7)", .pme_code = 679, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 2, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_3@8", .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 8)", .pme_code = 680, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 2, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_3@9", .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 9)", .pme_code = 681, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 2, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_3@10", .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 10)", .pme_code = 682, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 2, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_3@11", .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 11)", .pme_code = 683, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 2, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_3@12", .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 12)", .pme_code = 684, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 2, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_3@13", .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 13)", .pme_code = 685, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 2, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_3@14", .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 14)", .pme_code = 686, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 2, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_FLOWING_3@15", .pme_desc = "Wclk cycles BW2MD input port 3 has a flit flowing (on either VC0 or VC2). (M chip 15)", .pme_code = 687, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 2, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 7 Event 3 */ { .pme_name = "INVAL_2@0", .pme_desc = "Invalidations sent to two BWs. (M chip 0)", .pme_code = 688, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_2@1", .pme_desc = "Invalidations sent to two BWs. (M chip 1)", .pme_code = 689, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 3, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_2@2", .pme_desc = "Invalidations sent to two BWs. (M chip 2)", .pme_code = 690, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 3, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_2@3", .pme_desc = "Invalidations sent to two BWs. (M chip 3)", .pme_code = 691, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 3, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_2@4", .pme_desc = "Invalidations sent to two BWs. (M chip 4)", .pme_code = 692, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 3, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_2@5", .pme_desc = "Invalidations sent to two BWs. (M chip 5)", .pme_code = 693, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 3, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_2@6", .pme_desc = "Invalidations sent to two BWs. (M chip 6)", .pme_code = 694, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 3, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_2@7", .pme_desc = "Invalidations sent to two BWs. (M chip 7)", .pme_code = 695, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 3, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_2@8", .pme_desc = "Invalidations sent to two BWs. (M chip 8)", .pme_code = 696, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 3, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_2@9", .pme_desc = "Invalidations sent to two BWs. (M chip 9)", .pme_code = 697, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 3, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_2@10", .pme_desc = "Invalidations sent to two BWs. (M chip 10)", .pme_code = 698, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 3, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_2@11", .pme_desc = "Invalidations sent to two BWs. (M chip 11)", .pme_code = 699, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 3, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_2@12", .pme_desc = "Invalidations sent to two BWs. (M chip 12)", .pme_code = 700, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 3, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_2@13", .pme_desc = "Invalidations sent to two BWs. (M chip 13)", .pme_code = 701, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 3, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_2@14", .pme_desc = "Invalidations sent to two BWs. (M chip 14)", .pme_code = 702, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 3, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_2@15", .pme_desc = "Invalidations sent to two BWs. (M chip 15)", .pme_code = 703, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 7, .pme_event = 3, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 8 Event 0 */ { .pme_name = "SUPPLY_SH@0", .pme_desc = "SupplySh packets received. (M chip 0)", .pme_code = 704, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_SH@1", .pme_desc = "SupplySh packets received. (M chip 1)", .pme_code = 705, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 0, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_SH@2", .pme_desc = "SupplySh packets received. (M chip 2)", .pme_code = 706, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 0, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_SH@3", .pme_desc = "SupplySh packets received. (M chip 3)", .pme_code = 707, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 0, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_SH@4", .pme_desc = "SupplySh packets received. (M chip 4)", .pme_code = 708, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 0, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_SH@5", .pme_desc = "SupplySh packets received. (M chip 5)", .pme_code = 709, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 0, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_SH@6", .pme_desc = "SupplySh packets received. (M chip 6)", .pme_code = 710, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 0, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_SH@7", .pme_desc = "SupplySh packets received. (M chip 7)", .pme_code = 711, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 0, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_SH@8", .pme_desc = "SupplySh packets received. (M chip 8)", .pme_code = 712, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 0, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_SH@9", .pme_desc = "SupplySh packets received. (M chip 9)", .pme_code = 713, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 0, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_SH@10", .pme_desc = "SupplySh packets received. (M chip 10)", .pme_code = 714, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 0, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_SH@11", .pme_desc = "SupplySh packets received. (M chip 11)", .pme_code = 715, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 0, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_SH@12", .pme_desc = "SupplySh packets received. (M chip 12)", .pme_code = 716, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 0, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_SH@13", .pme_desc = "SupplySh packets received. (M chip 13)", .pme_code = 717, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 0, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_SH@14", .pme_desc = "SupplySh packets received. (M chip 14)", .pme_code = 718, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 0, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_SH@15", .pme_desc = "SupplySh packets received. (M chip 15)", .pme_code = 719, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 0, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 8 Event 1 */ { .pme_name = "STALL_MM@0", .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 0)", .pme_code = 720, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM@1", .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 1)", .pme_code = 721, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 1, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM@2", .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 2)", .pme_code = 722, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 1, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM@3", .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 3)", .pme_code = 723, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 1, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM@4", .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 4)", .pme_code = 724, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 1, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM@5", .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 5)", .pme_code = 725, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 1, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM@6", .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 6)", .pme_code = 726, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 1, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM@7", .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 7)", .pme_code = 727, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 1, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM@8", .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 8)", .pme_code = 728, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 1, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM@9", .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 9)", .pme_code = 729, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 1, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM@10", .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 10)", .pme_code = 730, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 1, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM@11", .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 11)", .pme_code = 731, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 1, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM@12", .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 12)", .pme_code = 732, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 1, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM@13", .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 13)", .pme_code = 733, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 1, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM@14", .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 14)", .pme_code = 734, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 1, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "STALL_MM@15", .pme_desc = "Wclk cycles protocol engine request queue stalled due to back-pressure from memory manager. (M chip 15)", .pme_code = 735, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 1, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 8 Event 2 */ { .pme_name = "W_IN_WAITING_0@0", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 0)", .pme_code = 736, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_0@1", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 1)", .pme_code = 737, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 2, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_0@2", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 2)", .pme_code = 738, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 2, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_0@3", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 3)", .pme_code = 739, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 2, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_0@4", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 4)", .pme_code = 740, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 2, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_0@5", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 5)", .pme_code = 741, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 2, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_0@6", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 6)", .pme_code = 742, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 2, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_0@7", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 7)", .pme_code = 743, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 2, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_0@8", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 8)", .pme_code = 744, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 2, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_0@9", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 9)", .pme_code = 745, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 2, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_0@10", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 10)", .pme_code = 746, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 2, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_0@11", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 11)", .pme_code = 747, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 2, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_0@12", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 12)", .pme_code = 748, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 2, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_0@13", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 13)", .pme_code = 749, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 2, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_0@14", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 14)", .pme_code = 750, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 2, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_0@15", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 15)", .pme_code = 751, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 2, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 8 Event 3 */ { .pme_name = "W_OUT_FLOWING_1@0", .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 0)", .pme_code = 752, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_1@1", .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 1)", .pme_code = 753, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 3, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_1@2", .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 2)", .pme_code = 754, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 3, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_1@3", .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 3)", .pme_code = 755, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 3, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_1@4", .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 4)", .pme_code = 756, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 3, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_1@5", .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 5)", .pme_code = 757, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 3, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_1@6", .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 6)", .pme_code = 758, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 3, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_1@7", .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 7)", .pme_code = 759, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 3, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_1@8", .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 8)", .pme_code = 760, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 3, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_1@9", .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 9)", .pme_code = 761, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 3, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_1@10", .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 10)", .pme_code = 762, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 3, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_1@11", .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 11)", .pme_code = 763, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 3, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_1@12", .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 12)", .pme_code = 764, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 3, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_1@13", .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 13)", .pme_code = 765, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 3, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_1@14", .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 14)", .pme_code = 766, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 3, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_1@15", .pme_desc = "Wclk cycles MD2BW output port 1 has a flit flowing. (M chip 15)", .pme_code = 767, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 8, .pme_event = 3, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 9 Event 0 */ { .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@0", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 0)", .pme_code = 768, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@1", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 1)", .pme_code = 769, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 0, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@2", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 2)", .pme_code = 770, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 0, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@3", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 3)", .pme_code = 771, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 0, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@4", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 4)", .pme_code = 772, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 0, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@5", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 5)", .pme_code = 773, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 0, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@6", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 6)", .pme_code = 774, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 0, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@7", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 7)", .pme_code = 775, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 0, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@8", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 8)", .pme_code = 776, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 0, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@9", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 9)", .pme_code = 777, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 0, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@10", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 10)", .pme_code = 778, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 0, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@11", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 11)", .pme_code = 779, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 0, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@12", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 12)", .pme_code = 780, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 0, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@13", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 13)", .pme_code = 781, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 0, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@14", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 14)", .pme_code = 782, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 0, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_GETS_4DWORDS_L3_MISS@15", .pme_desc = "NGet or Get Full cache line requests to MDs - L3 miss. (M chip 15)", .pme_code = 783, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 0, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 9 Event 1 */ { .pme_name = "SECTION_BUSY@0", .pme_desc = "Wclk cycles MD pipeline busy. (M chip 0)", .pme_code = 784, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SECTION_BUSY@1", .pme_desc = "Wclk cycles MD pipeline busy. (M chip 1)", .pme_code = 785, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 1, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SECTION_BUSY@2", .pme_desc = "Wclk cycles MD pipeline busy. (M chip 2)", .pme_code = 786, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 1, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SECTION_BUSY@3", .pme_desc = "Wclk cycles MD pipeline busy. (M chip 3)", .pme_code = 787, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 1, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SECTION_BUSY@4", .pme_desc = "Wclk cycles MD pipeline busy. (M chip 4)", .pme_code = 788, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 1, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SECTION_BUSY@5", .pme_desc = "Wclk cycles MD pipeline busy. (M chip 5)", .pme_code = 789, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 1, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SECTION_BUSY@6", .pme_desc = "Wclk cycles MD pipeline busy. (M chip 6)", .pme_code = 790, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 1, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SECTION_BUSY@7", .pme_desc = "Wclk cycles MD pipeline busy. (M chip 7)", .pme_code = 791, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 1, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SECTION_BUSY@8", .pme_desc = "Wclk cycles MD pipeline busy. (M chip 8)", .pme_code = 792, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 1, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SECTION_BUSY@9", .pme_desc = "Wclk cycles MD pipeline busy. (M chip 9)", .pme_code = 793, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 1, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SECTION_BUSY@10", .pme_desc = "Wclk cycles MD pipeline busy. (M chip 10)", .pme_code = 794, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 1, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SECTION_BUSY@11", .pme_desc = "Wclk cycles MD pipeline busy. (M chip 11)", .pme_code = 795, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 1, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SECTION_BUSY@12", .pme_desc = "Wclk cycles MD pipeline busy. (M chip 12)", .pme_code = 796, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 1, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SECTION_BUSY@13", .pme_desc = "Wclk cycles MD pipeline busy. (M chip 13)", .pme_code = 797, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 1, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SECTION_BUSY@14", .pme_desc = "Wclk cycles MD pipeline busy. (M chip 14)", .pme_code = 798, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 1, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SECTION_BUSY@15", .pme_desc = "Wclk cycles MD pipeline busy. (M chip 15)", .pme_code = 799, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 1, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 9 Event 2 */ { .pme_name = "W_IN_WAITING_1@0", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 0)", .pme_code = 800, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_1@1", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 1)", .pme_code = 801, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 2, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_1@2", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 2)", .pme_code = 802, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 2, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_1@3", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 3)", .pme_code = 803, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 2, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_1@4", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 4)", .pme_code = 804, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 2, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_1@5", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 5)", .pme_code = 805, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 2, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_1@6", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 6)", .pme_code = 806, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 2, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_1@7", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 7)", .pme_code = 807, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 2, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_1@8", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 8)", .pme_code = 808, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 2, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_1@9", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 9)", .pme_code = 809, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 2, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_1@10", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 10)", .pme_code = 810, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 2, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_1@11", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 11)", .pme_code = 811, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 2, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_1@12", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 12)", .pme_code = 812, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 2, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_1@13", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 13)", .pme_code = 813, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 2, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_1@14", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 14)", .pme_code = 814, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 2, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_1@15", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 15)", .pme_code = 815, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 2, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 9 Event 3 */ { .pme_name = "W_OUT_FLOWING_2@0", .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 0)", .pme_code = 816, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_2@1", .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 1)", .pme_code = 817, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 3, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_2@2", .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 2)", .pme_code = 818, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 3, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_2@3", .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 3)", .pme_code = 819, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 3, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_2@4", .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 4)", .pme_code = 820, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 3, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_2@5", .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 5)", .pme_code = 821, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 3, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_2@6", .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 6)", .pme_code = 822, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 3, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_2@7", .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 7)", .pme_code = 823, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 3, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_2@8", .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 8)", .pme_code = 824, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 3, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_2@9", .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 9)", .pme_code = 825, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 3, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_2@10", .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 10)", .pme_code = 826, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 3, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_2@11", .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 11)", .pme_code = 827, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 3, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_2@12", .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 12)", .pme_code = 828, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 3, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_2@13", .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 13)", .pme_code = 829, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 3, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_2@14", .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 14)", .pme_code = 830, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 3, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_2@15", .pme_desc = "Wclk cycles MD2BW output port 2 has a flit flowing. (M chip 15)", .pme_code = 831, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 9, .pme_event = 3, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 10 Event 0 */ { .pme_name = "SUPPLY_EXCL@0", .pme_desc = "SupplyExcl packets received. (M chip 0)", .pme_code = 832, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_EXCL@1", .pme_desc = "SupplyExcl packets received. (M chip 1)", .pme_code = 833, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 0, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_EXCL@2", .pme_desc = "SupplyExcl packets received. (M chip 2)", .pme_code = 834, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 0, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_EXCL@3", .pme_desc = "SupplyExcl packets received. (M chip 3)", .pme_code = 835, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 0, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_EXCL@4", .pme_desc = "SupplyExcl packets received. (M chip 4)", .pme_code = 836, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 0, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_EXCL@5", .pme_desc = "SupplyExcl packets received. (M chip 5)", .pme_code = 837, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 0, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_EXCL@6", .pme_desc = "SupplyExcl packets received. (M chip 6)", .pme_code = 838, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 0, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_EXCL@7", .pme_desc = "SupplyExcl packets received. (M chip 7)", .pme_code = 839, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 0, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_EXCL@8", .pme_desc = "SupplyExcl packets received. (M chip 8)", .pme_code = 840, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 0, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_EXCL@9", .pme_desc = "SupplyExcl packets received. (M chip 9)", .pme_code = 841, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 0, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_EXCL@10", .pme_desc = "SupplyExcl packets received. (M chip 10)", .pme_code = 842, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 0, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_EXCL@11", .pme_desc = "SupplyExcl packets received. (M chip 11)", .pme_code = 843, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 0, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_EXCL@12", .pme_desc = "SupplyExcl packets received. (M chip 12)", .pme_code = 844, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 0, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_EXCL@13", .pme_desc = "SupplyExcl packets received. (M chip 13)", .pme_code = 845, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 0, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_EXCL@14", .pme_desc = "SupplyExcl packets received. (M chip 14)", .pme_code = 846, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 0, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "SUPPLY_EXCL@15", .pme_desc = "SupplyExcl packets received. (M chip 15)", .pme_code = 847, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 0, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 10 Event 1 */ { .pme_name = "W_OUT_FLOWING_3@0", .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 0)", .pme_code = 848, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_3@1", .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 1)", .pme_code = 849, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 1, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_3@2", .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 2)", .pme_code = 850, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 1, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_3@3", .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 3)", .pme_code = 851, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 1, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_3@4", .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 4)", .pme_code = 852, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 1, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_3@5", .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 5)", .pme_code = 853, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 1, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_3@6", .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 6)", .pme_code = 854, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 1, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_3@7", .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 7)", .pme_code = 855, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 1, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_3@8", .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 8)", .pme_code = 856, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 1, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_3@9", .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 9)", .pme_code = 857, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 1, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_3@10", .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 10)", .pme_code = 858, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 1, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_3@11", .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 11)", .pme_code = 859, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 1, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_3@12", .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 12)", .pme_code = 860, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 1, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_3@13", .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 13)", .pme_code = 861, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 1, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_3@14", .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 14)", .pme_code = 862, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 1, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_FLOWING_3@15", .pme_desc = "Wclk cycles MD2BW output port 3 has a flit flowing. (M chip 15)", .pme_code = 863, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 1, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 10 Event 2 */ { .pme_name = "W_IN_WAITING_2@0", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 0)", .pme_code = 864, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_2@1", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 1)", .pme_code = 865, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 2, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_2@2", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 2)", .pme_code = 866, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 2, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_2@3", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 3)", .pme_code = 867, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 2, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_2@4", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 4)", .pme_code = 868, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 2, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_2@5", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 5)", .pme_code = 869, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 2, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_2@6", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 6)", .pme_code = 870, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 2, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_2@7", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 7)", .pme_code = 871, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 2, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_2@8", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 8)", .pme_code = 872, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 2, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_2@9", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 9)", .pme_code = 873, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 2, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_2@10", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 10)", .pme_code = 874, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 2, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_2@11", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 11)", .pme_code = 875, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 2, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_2@12", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 12)", .pme_code = 876, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 2, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_2@13", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 13)", .pme_code = 877, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 2, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_2@14", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 14)", .pme_code = 878, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 2, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_2@15", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 15)", .pme_code = 879, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 2, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 10 Event 3 */ { .pme_name = "INVAL_3@0", .pme_desc = "Invalidations sent to three BWs. (M chip 0)", .pme_code = 880, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_3@1", .pme_desc = "Invalidations sent to three BWs. (M chip 1)", .pme_code = 881, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 3, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_3@2", .pme_desc = "Invalidations sent to three BWs. (M chip 2)", .pme_code = 882, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 3, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_3@3", .pme_desc = "Invalidations sent to three BWs. (M chip 3)", .pme_code = 883, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 3, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_3@4", .pme_desc = "Invalidations sent to three BWs. (M chip 4)", .pme_code = 884, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 3, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_3@5", .pme_desc = "Invalidations sent to three BWs. (M chip 5)", .pme_code = 885, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 3, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_3@6", .pme_desc = "Invalidations sent to three BWs. (M chip 6)", .pme_code = 886, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 3, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_3@7", .pme_desc = "Invalidations sent to three BWs. (M chip 7)", .pme_code = 887, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 3, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_3@8", .pme_desc = "Invalidations sent to three BWs. (M chip 8)", .pme_code = 888, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 3, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_3@9", .pme_desc = "Invalidations sent to three BWs. (M chip 9)", .pme_code = 889, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 3, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_3@10", .pme_desc = "Invalidations sent to three BWs. (M chip 10)", .pme_code = 890, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 3, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_3@11", .pme_desc = "Invalidations sent to three BWs. (M chip 11)", .pme_code = 891, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 3, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_3@12", .pme_desc = "Invalidations sent to three BWs. (M chip 12)", .pme_code = 892, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 3, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_3@13", .pme_desc = "Invalidations sent to three BWs. (M chip 13)", .pme_code = 893, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 3, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_3@14", .pme_desc = "Invalidations sent to three BWs. (M chip 14)", .pme_code = 894, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 3, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_3@15", .pme_desc = "Invalidations sent to three BWs. (M chip 15)", .pme_code = 895, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 10, .pme_event = 3, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 11 Event 0 */ { .pme_name = "NACKS_RECV@0", .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 0)", .pme_code = 896, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NACKS_RECV@1", .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 1)", .pme_code = 897, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 0, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NACKS_RECV@2", .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 2)", .pme_code = 898, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 0, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NACKS_RECV@3", .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 3)", .pme_code = 899, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 0, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NACKS_RECV@4", .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 4)", .pme_code = 900, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 0, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NACKS_RECV@5", .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 5)", .pme_code = 901, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 0, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NACKS_RECV@6", .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 6)", .pme_code = 902, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 0, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NACKS_RECV@7", .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 7)", .pme_code = 903, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 0, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NACKS_RECV@8", .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 8)", .pme_code = 904, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 0, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NACKS_RECV@9", .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 9)", .pme_code = 905, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 0, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NACKS_RECV@10", .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 10)", .pme_code = 906, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 0, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NACKS_RECV@11", .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 11)", .pme_code = 907, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 0, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NACKS_RECV@12", .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 12)", .pme_code = 908, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 0, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NACKS_RECV@13", .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 13)", .pme_code = 909, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 0, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NACKS_RECV@14", .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 14)", .pme_code = 910, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 0, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "NACKS_RECV@15", .pme_desc = "FlushAck and Update Nack packets received (race between forwarded request and eviction by owner). (M chip 15)", .pme_code = 911, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 0, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 11 Event 1 */ { .pme_name = "W_OUT_BLOCK_CRED_0@0", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 0)", .pme_code = 912, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_0@1", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 1)", .pme_code = 913, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 1, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_0@2", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 2)", .pme_code = 914, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 1, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_0@3", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 3)", .pme_code = 915, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 1, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_0@4", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 4)", .pme_code = 916, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 1, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_0@5", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 5)", .pme_code = 917, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 1, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_0@6", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 6)", .pme_code = 918, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 1, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_0@7", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 7)", .pme_code = 919, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 1, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_0@8", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 8)", .pme_code = 920, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 1, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_0@9", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 9)", .pme_code = 921, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 1, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_0@10", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 10)", .pme_code = 922, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 1, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_0@11", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 11)", .pme_code = 923, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 1, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_0@12", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 12)", .pme_code = 924, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 1, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_0@13", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 13)", .pme_code = 925, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 1, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_0@14", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 14)", .pme_code = 926, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 1, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_0@15", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to lack of credits. (M chip 15)", .pme_code = 927, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 1, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 11 Event 2 */ { .pme_name = "W_IN_WAITING_3@0", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 0)", .pme_code = 928, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_3@1", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 1)", .pme_code = 929, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 2, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_3@2", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 2)", .pme_code = 930, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 2, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_3@3", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 3)", .pme_code = 931, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 2, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_3@4", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 4)", .pme_code = 932, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 2, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_3@5", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 5)", .pme_code = 933, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 2, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_3@6", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 6)", .pme_code = 934, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 2, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_3@7", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 7)", .pme_code = 935, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 2, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_3@8", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 8)", .pme_code = 936, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 2, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_3@9", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 9)", .pme_code = 937, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 2, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_3@10", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 10)", .pme_code = 938, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 2, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_3@11", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 11)", .pme_code = 939, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 2, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_3@12", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 12)", .pme_code = 940, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 2, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_3@13", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 13)", .pme_code = 941, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 2, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_3@14", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 14)", .pme_code = 942, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 2, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_WAITING_3@15", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that failed to win arbitration (on either VC0 or VC2). (M chip 15)", .pme_code = 943, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 2, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 11 Event 3 */ { .pme_name = "INVAL_4@0", .pme_desc = "Invalidations sent to four BWs. (M chip 0)", .pme_code = 944, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_4@1", .pme_desc = "Invalidations sent to four BWs. (M chip 1)", .pme_code = 945, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 3, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_4@2", .pme_desc = "Invalidations sent to four BWs. (M chip 2)", .pme_code = 946, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 3, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_4@3", .pme_desc = "Invalidations sent to four BWs. (M chip 3)", .pme_code = 947, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 3, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_4@4", .pme_desc = "Invalidations sent to four BWs. (M chip 4)", .pme_code = 948, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 3, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_4@5", .pme_desc = "Invalidations sent to four BWs. (M chip 5)", .pme_code = 949, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 3, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_4@6", .pme_desc = "Invalidations sent to four BWs. (M chip 6)", .pme_code = 950, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 3, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_4@7", .pme_desc = "Invalidations sent to four BWs. (M chip 7)", .pme_code = 951, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 3, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_4@8", .pme_desc = "Invalidations sent to four BWs. (M chip 8)", .pme_code = 952, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 3, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_4@9", .pme_desc = "Invalidations sent to four BWs. (M chip 9)", .pme_code = 953, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 3, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_4@10", .pme_desc = "Invalidations sent to four BWs. (M chip 10)", .pme_code = 954, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 3, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_4@11", .pme_desc = "Invalidations sent to four BWs. (M chip 11)", .pme_code = 955, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 3, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_4@12", .pme_desc = "Invalidations sent to four BWs. (M chip 12)", .pme_code = 956, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 3, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_4@13", .pme_desc = "Invalidations sent to four BWs. (M chip 13)", .pme_code = 957, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 3, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_4@14", .pme_desc = "Invalidations sent to four BWs. (M chip 14)", .pme_code = 958, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 3, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_4@15", .pme_desc = "Invalidations sent to four BWs. (M chip 15)", .pme_code = 959, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 11, .pme_event = 3, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 12 Event 0 */ { .pme_name = "UPDATE_NACK_RECV@0", .pme_desc = "UpdateNacks received. (M chip 0)", .pme_code = 960, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATE_NACK_RECV@1", .pme_desc = "UpdateNacks received. (M chip 1)", .pme_code = 961, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 0, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATE_NACK_RECV@2", .pme_desc = "UpdateNacks received. (M chip 2)", .pme_code = 962, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 0, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATE_NACK_RECV@3", .pme_desc = "UpdateNacks received. (M chip 3)", .pme_code = 963, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 0, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATE_NACK_RECV@4", .pme_desc = "UpdateNacks received. (M chip 4)", .pme_code = 964, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 0, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATE_NACK_RECV@5", .pme_desc = "UpdateNacks received. (M chip 5)", .pme_code = 965, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 0, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATE_NACK_RECV@6", .pme_desc = "UpdateNacks received. (M chip 6)", .pme_code = 966, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 0, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATE_NACK_RECV@7", .pme_desc = "UpdateNacks received. (M chip 7)", .pme_code = 967, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 0, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATE_NACK_RECV@8", .pme_desc = "UpdateNacks received. (M chip 8)", .pme_code = 968, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 0, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATE_NACK_RECV@9", .pme_desc = "UpdateNacks received. (M chip 9)", .pme_code = 969, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 0, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATE_NACK_RECV@10", .pme_desc = "UpdateNacks received. (M chip 10)", .pme_code = 970, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 0, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATE_NACK_RECV@11", .pme_desc = "UpdateNacks received. (M chip 11)", .pme_code = 971, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 0, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATE_NACK_RECV@12", .pme_desc = "UpdateNacks received. (M chip 12)", .pme_code = 972, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 0, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATE_NACK_RECV@13", .pme_desc = "UpdateNacks received. (M chip 13)", .pme_code = 973, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 0, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATE_NACK_RECV@14", .pme_desc = "UpdateNacks received. (M chip 14)", .pme_code = 974, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 0, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "UPDATE_NACK_RECV@15", .pme_desc = "UpdateNacks received. (M chip 15)", .pme_code = 975, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 0, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 12 Event 1 */ { .pme_name = "W_OUT_BLOCK_CRED_1@0", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 0)", .pme_code = 976, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_1@1", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 1)", .pme_code = 977, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 1, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_1@2", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 2)", .pme_code = 978, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 1, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_1@3", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 3)", .pme_code = 979, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 1, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_1@4", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 4)", .pme_code = 980, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 1, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_1@5", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 5)", .pme_code = 981, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 1, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_1@6", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 6)", .pme_code = 982, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 1, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_1@7", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 7)", .pme_code = 983, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 1, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_1@8", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 8)", .pme_code = 984, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 1, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_1@9", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 9)", .pme_code = 985, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 1, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_1@10", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 10)", .pme_code = 986, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 1, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_1@11", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 11)", .pme_code = 987, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 1, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_1@12", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 12)", .pme_code = 988, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 1, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_1@13", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 13)", .pme_code = 989, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 1, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_1@14", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 14)", .pme_code = 990, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 1, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_1@15", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to lack of credits. (M chip 15)", .pme_code = 991, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 1, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 12 Event 2 */ { .pme_name = "W_IN_BLOCKED_0@0", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 0)", .pme_code = 992, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_0@1", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 1)", .pme_code = 993, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 2, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_0@2", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 2)", .pme_code = 994, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 2, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_0@3", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 3)", .pme_code = 995, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 2, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_0@4", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 4)", .pme_code = 996, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 2, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_0@5", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 5)", .pme_code = 997, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 2, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_0@6", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 6)", .pme_code = 998, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 2, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_0@7", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 7)", .pme_code = 999, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 2, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_0@8", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 8)", .pme_code = 1000, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 2, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_0@9", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 9)", .pme_code = 1001, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 2, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_0@10", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 10)", .pme_code = 1002, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 2, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_0@11", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 11)", .pme_code = 1003, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 2, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_0@12", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 12)", .pme_code = 1004, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 2, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_0@13", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 13)", .pme_code = 1005, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 2, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_0@14", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 14)", .pme_code = 1006, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 2, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_0@15", .pme_desc = "Wclk cycles BW2MD input port 0 has a packet waiting that is blocked due to MD full. (M chip 15)", .pme_code = 1007, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 2, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 12 Event 3 */ { .pme_name = "FWD_GET_SENT@0", .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 0)", .pme_code = 1008, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_GET_SENT@1", .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 1)", .pme_code = 1009, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 3, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_GET_SENT@2", .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 2)", .pme_code = 1010, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 3, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_GET_SENT@3", .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 3)", .pme_code = 1011, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 3, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_GET_SENT@4", .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 4)", .pme_code = 1012, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 3, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_GET_SENT@5", .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 5)", .pme_code = 1013, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 3, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_GET_SENT@6", .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 6)", .pme_code = 1014, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 3, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_GET_SENT@7", .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 7)", .pme_code = 1015, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 3, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_GET_SENT@8", .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 8)", .pme_code = 1016, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 3, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_GET_SENT@9", .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 9)", .pme_code = 1017, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 3, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_GET_SENT@10", .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 10)", .pme_code = 1018, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 3, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_GET_SENT@11", .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 11)", .pme_code = 1019, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 3, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_GET_SENT@12", .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 12)", .pme_code = 1020, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 3, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_GET_SENT@13", .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 13)", .pme_code = 1021, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 3, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_GET_SENT@14", .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 14)", .pme_code = 1022, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 3, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FWD_GET_SENT@15", .pme_desc = "FwdGet packets sent (Exclusive -> PendFwd transition). (M chip 15)", .pme_code = 1023, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 12, .pme_event = 3, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 13 Event 0 */ { .pme_name = "PEND_DROP@0", .pme_desc = "Times entering PendDrop state (from Shared). (M chip 0)", .pme_code = 1024, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PEND_DROP@1", .pme_desc = "Times entering PendDrop state (from Shared). (M chip 1)", .pme_code = 1025, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 0, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PEND_DROP@2", .pme_desc = "Times entering PendDrop state (from Shared). (M chip 2)", .pme_code = 1026, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 0, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PEND_DROP@3", .pme_desc = "Times entering PendDrop state (from Shared). (M chip 3)", .pme_code = 1027, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 0, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PEND_DROP@4", .pme_desc = "Times entering PendDrop state (from Shared). (M chip 4)", .pme_code = 1028, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 0, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PEND_DROP@5", .pme_desc = "Times entering PendDrop state (from Shared). (M chip 5)", .pme_code = 1029, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 0, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PEND_DROP@6", .pme_desc = "Times entering PendDrop state (from Shared). (M chip 6)", .pme_code = 1030, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 0, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PEND_DROP@7", .pme_desc = "Times entering PendDrop state (from Shared). (M chip 7)", .pme_code = 1031, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 0, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PEND_DROP@8", .pme_desc = "Times entering PendDrop state (from Shared). (M chip 8)", .pme_code = 1032, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 0, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PEND_DROP@9", .pme_desc = "Times entering PendDrop state (from Shared). (M chip 9)", .pme_code = 1033, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 0, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PEND_DROP@10", .pme_desc = "Times entering PendDrop state (from Shared). (M chip 10)", .pme_code = 1034, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 0, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PEND_DROP@11", .pme_desc = "Times entering PendDrop state (from Shared). (M chip 11)", .pme_code = 1035, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 0, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PEND_DROP@12", .pme_desc = "Times entering PendDrop state (from Shared). (M chip 12)", .pme_code = 1036, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 0, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PEND_DROP@13", .pme_desc = "Times entering PendDrop state (from Shared). (M chip 13)", .pme_code = 1037, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 0, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PEND_DROP@14", .pme_desc = "Times entering PendDrop state (from Shared). (M chip 14)", .pme_code = 1038, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 0, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "PEND_DROP@15", .pme_desc = "Times entering PendDrop state (from Shared). (M chip 15)", .pme_code = 1039, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 0, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 13 Event 1 */ { .pme_name = "LINE_EVICTIONS@0", .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 0)", .pme_code = 1040, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "LINE_EVICTIONS@1", .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 1)", .pme_code = 1041, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 1, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "LINE_EVICTIONS@2", .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 2)", .pme_code = 1042, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 1, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "LINE_EVICTIONS@3", .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 3)", .pme_code = 1043, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 1, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "LINE_EVICTIONS@4", .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 4)", .pme_code = 1044, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 1, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "LINE_EVICTIONS@5", .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 5)", .pme_code = 1045, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 1, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "LINE_EVICTIONS@6", .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 6)", .pme_code = 1046, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 1, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "LINE_EVICTIONS@7", .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 7)", .pme_code = 1047, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 1, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "LINE_EVICTIONS@8", .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 8)", .pme_code = 1048, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 1, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "LINE_EVICTIONS@9", .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 9)", .pme_code = 1049, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 1, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "LINE_EVICTIONS@10", .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 10)", .pme_code = 1050, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 1, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "LINE_EVICTIONS@11", .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 11)", .pme_code = 1051, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 1, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "LINE_EVICTIONS@12", .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 12)", .pme_code = 1052, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 1, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "LINE_EVICTIONS@13", .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 13)", .pme_code = 1053, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 1, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "LINE_EVICTIONS@14", .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 14)", .pme_code = 1054, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 1, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "LINE_EVICTIONS@15", .pme_desc = "Counts lines that are evicted. Note: doesn't count AMO forced evictions. Also note that the counter will increment if the line is not dirty and it is evicted. (M chip 15)", .pme_code = 1055, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 1, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 13 Event 2 */ { .pme_name = "W_IN_BLOCKED_1@0", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 0)", .pme_code = 1056, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_1@1", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 1)", .pme_code = 1057, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 2, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_1@2", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 2)", .pme_code = 1058, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 2, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_1@3", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 3)", .pme_code = 1059, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 2, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_1@4", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 4)", .pme_code = 1060, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 2, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_1@5", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 5)", .pme_code = 1061, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 2, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_1@6", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 6)", .pme_code = 1062, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 2, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_1@7", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 7)", .pme_code = 1063, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 2, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_1@8", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 8)", .pme_code = 1064, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 2, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_1@9", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 9)", .pme_code = 1065, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 2, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_1@10", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 10)", .pme_code = 1066, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 2, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_1@11", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 11)", .pme_code = 1067, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 2, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_1@12", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 12)", .pme_code = 1068, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 2, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_1@13", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 13)", .pme_code = 1069, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 2, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_1@14", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 14)", .pme_code = 1070, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 2, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_1@15", .pme_desc = "Wclk cycles BW2MD input port 1 has a packet waiting that is blocked due to MD full. (M chip 15)", .pme_code = 1071, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 2, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 13 Event 3 */ { .pme_name = "FLUSH_REQ_PACKETS@0", .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 0)", .pme_code = 1072, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FLUSH_REQ_PACKETS@1", .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 1)", .pme_code = 1073, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 3, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FLUSH_REQ_PACKETS@2", .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 2)", .pme_code = 1074, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 3, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FLUSH_REQ_PACKETS@3", .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 3)", .pme_code = 1075, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 3, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FLUSH_REQ_PACKETS@4", .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 4)", .pme_code = 1076, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 3, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FLUSH_REQ_PACKETS@5", .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 5)", .pme_code = 1077, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 3, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FLUSH_REQ_PACKETS@6", .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 6)", .pme_code = 1078, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 3, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FLUSH_REQ_PACKETS@7", .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 7)", .pme_code = 1079, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 3, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FLUSH_REQ_PACKETS@8", .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 8)", .pme_code = 1080, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 3, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FLUSH_REQ_PACKETS@9", .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 9)", .pme_code = 1081, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 3, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FLUSH_REQ_PACKETS@10", .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 10)", .pme_code = 1082, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 3, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FLUSH_REQ_PACKETS@11", .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 11)", .pme_code = 1083, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 3, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FLUSH_REQ_PACKETS@12", .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 12)", .pme_code = 1084, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 3, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FLUSH_REQ_PACKETS@13", .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 13)", .pme_code = 1085, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 3, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FLUSH_REQ_PACKETS@14", .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 14)", .pme_code = 1086, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 3, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "FLUSH_REQ_PACKETS@15", .pme_desc = "FlushReq packets sent (Exclusive -> PendFwd transition). (M chip 15)", .pme_code = 1087, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 13, .pme_event = 3, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 14 Event 0 */ { .pme_name = "INVAL_EVENTS@0", .pme_desc = "Invalidation events (any number of sharers). (M chip 0)", .pme_code = 1088, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_EVENTS@1", .pme_desc = "Invalidation events (any number of sharers). (M chip 1)", .pme_code = 1089, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 0, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_EVENTS@2", .pme_desc = "Invalidation events (any number of sharers). (M chip 2)", .pme_code = 1090, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 0, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_EVENTS@3", .pme_desc = "Invalidation events (any number of sharers). (M chip 3)", .pme_code = 1091, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 0, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_EVENTS@4", .pme_desc = "Invalidation events (any number of sharers). (M chip 4)", .pme_code = 1092, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 0, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_EVENTS@5", .pme_desc = "Invalidation events (any number of sharers). (M chip 5)", .pme_code = 1093, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 0, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_EVENTS@6", .pme_desc = "Invalidation events (any number of sharers). (M chip 6)", .pme_code = 1094, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 0, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_EVENTS@7", .pme_desc = "Invalidation events (any number of sharers). (M chip 7)", .pme_code = 1095, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 0, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_EVENTS@8", .pme_desc = "Invalidation events (any number of sharers). (M chip 8)", .pme_code = 1096, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 0, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_EVENTS@9", .pme_desc = "Invalidation events (any number of sharers). (M chip 9)", .pme_code = 1097, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 0, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_EVENTS@10", .pme_desc = "Invalidation events (any number of sharers). (M chip 10)", .pme_code = 1098, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 0, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_EVENTS@11", .pme_desc = "Invalidation events (any number of sharers). (M chip 11)", .pme_code = 1099, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 0, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_EVENTS@12", .pme_desc = "Invalidation events (any number of sharers). (M chip 12)", .pme_code = 1100, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 0, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_EVENTS@13", .pme_desc = "Invalidation events (any number of sharers). (M chip 13)", .pme_code = 1101, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 0, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_EVENTS@14", .pme_desc = "Invalidation events (any number of sharers). (M chip 14)", .pme_code = 1102, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 0, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "INVAL_EVENTS@15", .pme_desc = "Invalidation events (any number of sharers). (M chip 15)", .pme_code = 1103, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 0, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 14 Event 1 */ { .pme_name = "L3_LINE_HIT_GLOBAL@0", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 0)", .pme_code = 1104, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_GLOBAL@1", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 1)", .pme_code = 1105, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 1, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_GLOBAL@2", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 2)", .pme_code = 1106, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 1, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_GLOBAL@3", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 3)", .pme_code = 1107, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 1, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_GLOBAL@4", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 4)", .pme_code = 1108, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 1, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_GLOBAL@5", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 5)", .pme_code = 1109, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 1, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_GLOBAL@6", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 6)", .pme_code = 1110, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 1, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_GLOBAL@7", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 7)", .pme_code = 1111, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 1, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_GLOBAL@8", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 8)", .pme_code = 1112, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 1, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_GLOBAL@9", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 9)", .pme_code = 1113, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 1, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_GLOBAL@10", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 10)", .pme_code = 1114, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 1, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_GLOBAL@11", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 11)", .pme_code = 1115, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 1, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_GLOBAL@12", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 12)", .pme_code = 1116, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 1, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_GLOBAL@13", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 13)", .pme_code = 1117, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 1, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_GLOBAL@14", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 14)", .pme_code = 1118, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 1, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_GLOBAL@15", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was global. (M chip 15)", .pme_code = 1119, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 1, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 14 Event 2 */ { .pme_name = "W_IN_BLOCKED_2@0", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 0)", .pme_code = 1120, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_2@1", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 1)", .pme_code = 1121, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 2, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_2@2", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 2)", .pme_code = 1122, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 2, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_2@3", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 3)", .pme_code = 1123, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 2, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_2@4", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 4)", .pme_code = 1124, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 2, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_2@5", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 5)", .pme_code = 1125, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 2, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_2@6", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 6)", .pme_code = 1126, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 2, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_2@7", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 7)", .pme_code = 1127, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 2, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_2@8", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 8)", .pme_code = 1128, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 2, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_2@9", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 9)", .pme_code = 1129, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 2, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_2@10", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 10)", .pme_code = 1130, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 2, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_2@11", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 11)", .pme_code = 1131, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 2, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_2@12", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 12)", .pme_code = 1132, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 2, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_2@13", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 13)", .pme_code = 1133, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 2, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_2@14", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 14)", .pme_code = 1134, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 2, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_2@15", .pme_desc = "Wclk cycles BW2MD input port 2 has a packet waiting that is blocked due to MD full. (M chip 15)", .pme_code = 1135, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 2, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 14 Event 3 */ { .pme_name = "W_OUT_BLOCK_CRED_2@0", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 0)", .pme_code = 1136, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_2@1", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 1)", .pme_code = 1137, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 3, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_2@2", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 2)", .pme_code = 1138, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 3, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_2@3", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 3)", .pme_code = 1139, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 3, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_2@4", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 4)", .pme_code = 1140, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 3, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_2@5", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 5)", .pme_code = 1141, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 3, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_2@6", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 6)", .pme_code = 1142, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 3, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_2@7", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 7)", .pme_code = 1143, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 3, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_2@8", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 8)", .pme_code = 1144, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 3, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_2@9", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 9)", .pme_code = 1145, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 3, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_2@10", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 10)", .pme_code = 1146, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 3, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_2@11", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 11)", .pme_code = 1147, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 3, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_2@12", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 12)", .pme_code = 1148, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 3, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_2@13", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 13)", .pme_code = 1149, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 3, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_2@14", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 14)", .pme_code = 1150, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 3, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_2@15", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to lack of credits. (M chip 15)", .pme_code = 1151, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 14, .pme_event = 3, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 15 Event 0 */ { .pme_name = "REQUEST_ALLOC_NO_FILL@0", .pme_desc = "Allocating no fill requests. (M chip 0)", .pme_code = 1152, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_ALLOC_NO_FILL@1", .pme_desc = "Allocating no fill requests. (M chip 1)", .pme_code = 1153, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 0, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_ALLOC_NO_FILL@2", .pme_desc = "Allocating no fill requests. (M chip 2)", .pme_code = 1154, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 0, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_ALLOC_NO_FILL@3", .pme_desc = "Allocating no fill requests. (M chip 3)", .pme_code = 1155, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 0, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_ALLOC_NO_FILL@4", .pme_desc = "Allocating no fill requests. (M chip 4)", .pme_code = 1156, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 0, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_ALLOC_NO_FILL@5", .pme_desc = "Allocating no fill requests. (M chip 5)", .pme_code = 1157, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 0, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_ALLOC_NO_FILL@6", .pme_desc = "Allocating no fill requests. (M chip 6)", .pme_code = 1158, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 0, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_ALLOC_NO_FILL@7", .pme_desc = "Allocating no fill requests. (M chip 7)", .pme_code = 1159, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 0, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_ALLOC_NO_FILL@8", .pme_desc = "Allocating no fill requests. (M chip 8)", .pme_code = 1160, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 0, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_ALLOC_NO_FILL@9", .pme_desc = "Allocating no fill requests. (M chip 9)", .pme_code = 1161, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 0, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_ALLOC_NO_FILL@10", .pme_desc = "Allocating no fill requests. (M chip 10)", .pme_code = 1162, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 0, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_ALLOC_NO_FILL@11", .pme_desc = "Allocating no fill requests. (M chip 11)", .pme_code = 1163, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 0, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_ALLOC_NO_FILL@12", .pme_desc = "Allocating no fill requests. (M chip 12)", .pme_code = 1164, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 0, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_ALLOC_NO_FILL@13", .pme_desc = "Allocating no fill requests. (M chip 13)", .pme_code = 1165, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 0, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_ALLOC_NO_FILL@14", .pme_desc = "Allocating no fill requests. (M chip 14)", .pme_code = 1166, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 0, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_ALLOC_NO_FILL@15", .pme_desc = "Allocating no fill requests. (M chip 15)", .pme_code = 1167, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 0, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 15 Event 1 */ { .pme_name = "L3_LINE_HIT_SHARED@0", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 0)", .pme_code = 1168, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_SHARED@1", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 1)", .pme_code = 1169, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 1, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_SHARED@2", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 2)", .pme_code = 1170, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 1, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_SHARED@3", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 3)", .pme_code = 1171, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 1, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_SHARED@4", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 4)", .pme_code = 1172, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 1, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_SHARED@5", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 5)", .pme_code = 1173, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 1, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_SHARED@6", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 6)", .pme_code = 1174, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 1, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_SHARED@7", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 7)", .pme_code = 1175, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 1, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_SHARED@8", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 8)", .pme_code = 1176, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 1, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_SHARED@9", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 9)", .pme_code = 1177, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 1, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_SHARED@10", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 10)", .pme_code = 1178, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 1, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_SHARED@11", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 11)", .pme_code = 1179, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 1, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_SHARED@12", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 12)", .pme_code = 1180, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 1, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_SHARED@13", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 13)", .pme_code = 1181, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 1, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_SHARED@14", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 14)", .pme_code = 1182, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 1, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "L3_LINE_HIT_SHARED@15", .pme_desc = "Allocating read requests that hit out of L3 cached data and state was shared. (M chip 15)", .pme_code = 1183, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 1, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 15 Event 2 */ { .pme_name = "W_IN_BLOCKED_3@0", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 0)", .pme_code = 1184, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_3@1", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 1)", .pme_code = 1185, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 2, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_3@2", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 2)", .pme_code = 1186, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 2, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_3@3", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 3)", .pme_code = 1187, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 2, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_3@4", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 4)", .pme_code = 1188, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 2, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_3@5", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 5)", .pme_code = 1189, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 2, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_3@6", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 6)", .pme_code = 1190, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 2, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_3@7", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 7)", .pme_code = 1191, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 2, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_3@8", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 8)", .pme_code = 1192, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 2, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_3@9", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 9)", .pme_code = 1193, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 2, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_3@10", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 10)", .pme_code = 1194, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 2, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_3@11", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 11)", .pme_code = 1195, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 2, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_3@12", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 12)", .pme_code = 1196, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 2, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_3@13", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 13)", .pme_code = 1197, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 2, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_3@14", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 14)", .pme_code = 1198, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 2, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_IN_BLOCKED_3@15", .pme_desc = "Wclk cycles BW2MD input port 3 has a packet waiting that is blocked due to MD full. (M chip 15)", .pme_code = 1199, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 2, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 15 Event 3 */ { .pme_name = "W_OUT_BLOCK_CRED_3@0", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 0)", .pme_code = 1200, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_3@1", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 1)", .pme_code = 1201, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 3, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_3@2", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 2)", .pme_code = 1202, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 3, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_3@3", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 3)", .pme_code = 1203, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 3, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_3@4", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 4)", .pme_code = 1204, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 3, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_3@5", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 5)", .pme_code = 1205, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 3, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_3@6", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 6)", .pme_code = 1206, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 3, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_3@7", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 7)", .pme_code = 1207, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 3, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_3@8", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 8)", .pme_code = 1208, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 3, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_3@9", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 9)", .pme_code = 1209, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 3, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_3@10", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 10)", .pme_code = 1210, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 3, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_3@11", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 11)", .pme_code = 1211, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 3, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_3@12", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 12)", .pme_code = 1212, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 3, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_3@13", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 13)", .pme_code = 1213, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 3, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_3@14", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 14)", .pme_code = 1214, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 3, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CRED_3@15", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to lack of credits. (M chip 15)", .pme_code = 1215, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 15, .pme_event = 3, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 16 Event 0 */ { .pme_name = "REQUEST_1DWORD_L3_HIT@0", .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 0)", .pme_code = 1216, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_HIT@1", .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 1)", .pme_code = 1217, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 0, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_HIT@2", .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 2)", .pme_code = 1218, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 0, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_HIT@3", .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 3)", .pme_code = 1219, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 0, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_HIT@4", .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 4)", .pme_code = 1220, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 0, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_HIT@5", .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 5)", .pme_code = 1221, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 0, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_HIT@6", .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 6)", .pme_code = 1222, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 0, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_HIT@7", .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 7)", .pme_code = 1223, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 0, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_HIT@8", .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 8)", .pme_code = 1224, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 0, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_HIT@9", .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 9)", .pme_code = 1225, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 0, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_HIT@10", .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 10)", .pme_code = 1226, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 0, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_HIT@11", .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 11)", .pme_code = 1227, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 0, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_HIT@12", .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 12)", .pme_code = 1228, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 0, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_HIT@13", .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 13)", .pme_code = 1229, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 0, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_HIT@14", .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 14)", .pme_code = 1230, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 0, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_HIT@15", .pme_desc = "Single DWord Get and NGet requests to MDs - L3 hit. (M chip 15)", .pme_code = 1231, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 0, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 16 Event 1 */ { .pme_name = "AMOS@0", .pme_desc = "AMOs to local memory (memory manager). (M chip 0)", .pme_code = 1232, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMOS@1", .pme_desc = "AMOs to local memory (memory manager). (M chip 1)", .pme_code = 1233, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 1, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMOS@2", .pme_desc = "AMOs to local memory (memory manager). (M chip 2)", .pme_code = 1234, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 1, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMOS@3", .pme_desc = "AMOs to local memory (memory manager). (M chip 3)", .pme_code = 1235, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 1, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMOS@4", .pme_desc = "AMOs to local memory (memory manager). (M chip 4)", .pme_code = 1236, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 1, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMOS@5", .pme_desc = "AMOs to local memory (memory manager). (M chip 5)", .pme_code = 1237, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 1, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMOS@6", .pme_desc = "AMOs to local memory (memory manager). (M chip 6)", .pme_code = 1238, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 1, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMOS@7", .pme_desc = "AMOs to local memory (memory manager). (M chip 7)", .pme_code = 1239, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 1, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMOS@8", .pme_desc = "AMOs to local memory (memory manager). (M chip 8)", .pme_code = 1240, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 1, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMOS@9", .pme_desc = "AMOs to local memory (memory manager). (M chip 9)", .pme_code = 1241, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 1, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMOS@10", .pme_desc = "AMOs to local memory (memory manager). (M chip 10)", .pme_code = 1242, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 1, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMOS@11", .pme_desc = "AMOs to local memory (memory manager). (M chip 11)", .pme_code = 1243, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 1, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMOS@12", .pme_desc = "AMOs to local memory (memory manager). (M chip 12)", .pme_code = 1244, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 1, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMOS@13", .pme_desc = "AMOs to local memory (memory manager). (M chip 13)", .pme_code = 1245, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 1, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMOS@14", .pme_desc = "AMOs to local memory (memory manager). (M chip 14)", .pme_code = 1246, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 1, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMOS@15", .pme_desc = "AMOs to local memory (memory manager). (M chip 15)", .pme_code = 1247, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 1, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 16 Event 2 */ { .pme_name = "MM0_ANY_BANK_BUSY@0", .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 0)", .pme_code = 1248, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ANY_BANK_BUSY@1", .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 1)", .pme_code = 1249, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 2, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ANY_BANK_BUSY@2", .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 2)", .pme_code = 1250, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 2, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ANY_BANK_BUSY@3", .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 3)", .pme_code = 1251, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 2, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ANY_BANK_BUSY@4", .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 4)", .pme_code = 1252, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 2, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ANY_BANK_BUSY@5", .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 5)", .pme_code = 1253, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 2, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ANY_BANK_BUSY@6", .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 6)", .pme_code = 1254, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 2, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ANY_BANK_BUSY@7", .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 7)", .pme_code = 1255, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 2, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ANY_BANK_BUSY@8", .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 8)", .pme_code = 1256, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 2, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ANY_BANK_BUSY@9", .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 9)", .pme_code = 1257, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 2, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ANY_BANK_BUSY@10", .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 10)", .pme_code = 1258, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 2, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ANY_BANK_BUSY@11", .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 11)", .pme_code = 1259, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 2, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ANY_BANK_BUSY@12", .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 12)", .pme_code = 1260, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 2, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ANY_BANK_BUSY@13", .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 13)", .pme_code = 1261, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 2, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ANY_BANK_BUSY@14", .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 14)", .pme_code = 1262, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 2, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ANY_BANK_BUSY@15", .pme_desc = "Wclk cycles that any back is busy in MM0. (M chip 15)", .pme_code = 1263, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 2, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 16 Event 3 */ { .pme_name = "W_OUT_BLOCK_CHN_0@0", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 0)", .pme_code = 1264, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_0@1", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 1)", .pme_code = 1265, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 3, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_0@2", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 2)", .pme_code = 1266, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 3, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_0@3", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 3)", .pme_code = 1267, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 3, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_0@4", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 4)", .pme_code = 1268, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 3, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_0@5", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 5)", .pme_code = 1269, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 3, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_0@6", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 6)", .pme_code = 1270, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 3, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_0@7", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 7)", .pme_code = 1271, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 3, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_0@8", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 8)", .pme_code = 1272, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 3, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_0@9", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 9)", .pme_code = 1273, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 3, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_0@10", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 10)", .pme_code = 1274, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 3, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_0@11", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 11)", .pme_code = 1275, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 3, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_0@12", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 12)", .pme_code = 1276, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 3, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_0@13", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 13)", .pme_code = 1277, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 3, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_0@14", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 14)", .pme_code = 1278, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 3, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_0@15", .pme_desc = "Wclk cycles MD2BW output port 0 is blocked due to channel back-pressure. (M chip 15)", .pme_code = 1279, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 16, .pme_event = 3, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 17 Event 0 */ { .pme_name = "REQUEST_4DWORDS_L3_HIT@0", .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 0)", .pme_code = 1280, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_HIT@1", .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 1)", .pme_code = 1281, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 0, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_HIT@2", .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 2)", .pme_code = 1282, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 0, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_HIT@3", .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 3)", .pme_code = 1283, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 0, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_HIT@4", .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 4)", .pme_code = 1284, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 0, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_HIT@5", .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 5)", .pme_code = 1285, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 0, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_HIT@6", .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 6)", .pme_code = 1286, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 0, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_HIT@7", .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 7)", .pme_code = 1287, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 0, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_HIT@8", .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 8)", .pme_code = 1288, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 0, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_HIT@9", .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 9)", .pme_code = 1289, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 0, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_HIT@10", .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 10)", .pme_code = 1290, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 0, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_HIT@11", .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 11)", .pme_code = 1291, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 0, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_HIT@12", .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 12)", .pme_code = 1292, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 0, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_HIT@13", .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 13)", .pme_code = 1293, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 0, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_HIT@14", .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 14)", .pme_code = 1294, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 0, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_HIT@15", .pme_desc = "Allocating read requests to MDs - L3 hit. (M chip 15)", .pme_code = 1295, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 0, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 17 Event 1 */ { .pme_name = "AMO_MISSES@0", .pme_desc = "Misses in AMO cache (memory manager). (M chip 0)", .pme_code = 1296, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMO_MISSES@1", .pme_desc = "Misses in AMO cache (memory manager). (M chip 1)", .pme_code = 1297, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 1, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMO_MISSES@2", .pme_desc = "Misses in AMO cache (memory manager). (M chip 2)", .pme_code = 1298, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 1, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMO_MISSES@3", .pme_desc = "Misses in AMO cache (memory manager). (M chip 3)", .pme_code = 1299, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 1, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMO_MISSES@4", .pme_desc = "Misses in AMO cache (memory manager). (M chip 4)", .pme_code = 1300, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 1, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMO_MISSES@5", .pme_desc = "Misses in AMO cache (memory manager). (M chip 5)", .pme_code = 1301, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 1, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMO_MISSES@6", .pme_desc = "Misses in AMO cache (memory manager). (M chip 6)", .pme_code = 1302, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 1, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMO_MISSES@7", .pme_desc = "Misses in AMO cache (memory manager). (M chip 7)", .pme_code = 1303, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 1, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMO_MISSES@8", .pme_desc = "Misses in AMO cache (memory manager). (M chip 8)", .pme_code = 1304, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 1, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMO_MISSES@9", .pme_desc = "Misses in AMO cache (memory manager). (M chip 9)", .pme_code = 1305, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 1, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMO_MISSES@10", .pme_desc = "Misses in AMO cache (memory manager). (M chip 10)", .pme_code = 1306, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 1, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMO_MISSES@11", .pme_desc = "Misses in AMO cache (memory manager). (M chip 11)", .pme_code = 1307, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 1, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMO_MISSES@12", .pme_desc = "Misses in AMO cache (memory manager). (M chip 12)", .pme_code = 1308, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 1, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMO_MISSES@13", .pme_desc = "Misses in AMO cache (memory manager). (M chip 13)", .pme_code = 1309, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 1, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMO_MISSES@14", .pme_desc = "Misses in AMO cache (memory manager). (M chip 14)", .pme_code = 1310, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 1, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "AMO_MISSES@15", .pme_desc = "Misses in AMO cache (memory manager). (M chip 15)", .pme_code = 1311, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 1, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 17 Event 2 */ { .pme_name = "MM0_ACCUM_BANK_BUSY@0", .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 0)", .pme_code = 1312, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ACCUM_BANK_BUSY@1", .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 1)", .pme_code = 1313, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 2, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ACCUM_BANK_BUSY@2", .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 2)", .pme_code = 1314, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 2, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ACCUM_BANK_BUSY@3", .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 3)", .pme_code = 1315, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 2, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ACCUM_BANK_BUSY@4", .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 4)", .pme_code = 1316, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 2, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ACCUM_BANK_BUSY@5", .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 5)", .pme_code = 1317, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 2, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ACCUM_BANK_BUSY@6", .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 6)", .pme_code = 1318, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 2, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ACCUM_BANK_BUSY@7", .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 7)", .pme_code = 1319, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 2, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ACCUM_BANK_BUSY@8", .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 8)", .pme_code = 1320, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 2, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ACCUM_BANK_BUSY@9", .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 9)", .pme_code = 1321, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 2, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ACCUM_BANK_BUSY@10", .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 10)", .pme_code = 1322, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 2, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ACCUM_BANK_BUSY@11", .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 11)", .pme_code = 1323, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 2, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ACCUM_BANK_BUSY@12", .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 12)", .pme_code = 1324, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 2, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ACCUM_BANK_BUSY@13", .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 13)", .pme_code = 1325, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 2, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ACCUM_BANK_BUSY@14", .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 14)", .pme_code = 1326, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 2, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM0_ACCUM_BANK_BUSY@15", .pme_desc = "Accumulation of the MM0 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 15)", .pme_code = 1327, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 2, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 17 Event 3 */ { .pme_name = "W_OUT_BLOCK_CHN_1@0", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 0)", .pme_code = 1328, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_1@1", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 1)", .pme_code = 1329, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 3, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_1@2", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 2)", .pme_code = 1330, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 3, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_1@3", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 3)", .pme_code = 1331, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 3, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_1@4", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 4)", .pme_code = 1332, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 3, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_1@5", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 5)", .pme_code = 1333, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 3, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_1@6", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 6)", .pme_code = 1334, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 3, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_1@7", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 7)", .pme_code = 1335, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 3, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_1@8", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 8)", .pme_code = 1336, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 3, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_1@9", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 9)", .pme_code = 1337, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 3, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_1@10", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 10)", .pme_code = 1338, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 3, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_1@11", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 11)", .pme_code = 1339, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 3, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_1@12", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 12)", .pme_code = 1340, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 3, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_1@13", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 13)", .pme_code = 1341, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 3, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_1@14", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 14)", .pme_code = 1342, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 3, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_1@15", .pme_desc = "Wclk cycles MD2BW output port 1 is blocked due to channel back-pressure. (M chip 15)", .pme_code = 1343, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 17, .pme_event = 3, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 18 Event 0 */ { .pme_name = "REQUEST_1DWORD@0", .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 0)", .pme_code = 1344, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD@1", .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 1)", .pme_code = 1345, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 0, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD@2", .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 2)", .pme_code = 1346, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 0, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD@3", .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 3)", .pme_code = 1347, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 0, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD@4", .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 4)", .pme_code = 1348, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 0, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD@5", .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 5)", .pme_code = 1349, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 0, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD@6", .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 6)", .pme_code = 1350, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 0, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD@7", .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 7)", .pme_code = 1351, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 0, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD@8", .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 8)", .pme_code = 1352, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 0, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD@9", .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 9)", .pme_code = 1353, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 0, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD@10", .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 10)", .pme_code = 1354, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 0, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD@11", .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 11)", .pme_code = 1355, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 0, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD@12", .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 12)", .pme_code = 1356, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 0, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD@13", .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 13)", .pme_code = 1357, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 0, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD@14", .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 14)", .pme_code = 1358, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 0, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD@15", .pme_desc = "Single DWord Get and NGet requests to MDs. (M chip 15)", .pme_code = 1359, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 0, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 18 Event 1 */ { .pme_name = "RETRIES_MM@0", .pme_desc = "Memory Manager retries. (M chip 0)", .pme_code = 1360, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "RETRIES_MM@1", .pme_desc = "Memory Manager retries. (M chip 1)", .pme_code = 1361, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 1, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "RETRIES_MM@2", .pme_desc = "Memory Manager retries. (M chip 2)", .pme_code = 1362, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 1, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "RETRIES_MM@3", .pme_desc = "Memory Manager retries. (M chip 3)", .pme_code = 1363, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 1, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "RETRIES_MM@4", .pme_desc = "Memory Manager retries. (M chip 4)", .pme_code = 1364, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 1, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "RETRIES_MM@5", .pme_desc = "Memory Manager retries. (M chip 5)", .pme_code = 1365, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 1, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "RETRIES_MM@6", .pme_desc = "Memory Manager retries. (M chip 6)", .pme_code = 1366, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 1, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "RETRIES_MM@7", .pme_desc = "Memory Manager retries. (M chip 7)", .pme_code = 1367, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 1, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "RETRIES_MM@8", .pme_desc = "Memory Manager retries. (M chip 8)", .pme_code = 1368, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 1, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "RETRIES_MM@9", .pme_desc = "Memory Manager retries. (M chip 9)", .pme_code = 1369, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 1, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "RETRIES_MM@10", .pme_desc = "Memory Manager retries. (M chip 10)", .pme_code = 1370, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 1, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "RETRIES_MM@11", .pme_desc = "Memory Manager retries. (M chip 11)", .pme_code = 1371, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 1, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "RETRIES_MM@12", .pme_desc = "Memory Manager retries. (M chip 12)", .pme_code = 1372, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 1, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "RETRIES_MM@13", .pme_desc = "Memory Manager retries. (M chip 13)", .pme_code = 1373, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 1, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "RETRIES_MM@14", .pme_desc = "Memory Manager retries. (M chip 14)", .pme_code = 1374, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 1, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "RETRIES_MM@15", .pme_desc = "Memory Manager retries. (M chip 15)", .pme_code = 1375, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 1, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 18 Event 2 */ { .pme_name = "MM1_ANY_BANK_BUSY@0", .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 0)", .pme_code = 1376, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ANY_BANK_BUSY@1", .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 1)", .pme_code = 1377, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 2, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ANY_BANK_BUSY@2", .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 2)", .pme_code = 1378, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 2, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ANY_BANK_BUSY@3", .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 3)", .pme_code = 1379, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 2, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ANY_BANK_BUSY@4", .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 4)", .pme_code = 1380, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 2, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ANY_BANK_BUSY@5", .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 5)", .pme_code = 1381, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 2, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ANY_BANK_BUSY@6", .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 6)", .pme_code = 1382, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 2, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ANY_BANK_BUSY@7", .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 7)", .pme_code = 1383, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 2, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ANY_BANK_BUSY@8", .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 8)", .pme_code = 1384, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 2, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ANY_BANK_BUSY@9", .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 9)", .pme_code = 1385, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 2, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ANY_BANK_BUSY@10", .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 10)", .pme_code = 1386, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 2, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ANY_BANK_BUSY@11", .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 11)", .pme_code = 1387, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 2, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ANY_BANK_BUSY@12", .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 12)", .pme_code = 1388, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 2, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ANY_BANK_BUSY@13", .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 13)", .pme_code = 1389, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 2, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ANY_BANK_BUSY@14", .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 14)", .pme_code = 1390, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 2, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ANY_BANK_BUSY@15", .pme_desc = "Wclk cycles that any bank is busy in MM1. (M chip 15)", .pme_code = 1391, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 2, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 18 Event 3 */ { .pme_name = "W_OUT_BLOCK_CHN_2@0", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 0)", .pme_code = 1392, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_2@1", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 1)", .pme_code = 1393, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 3, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_2@2", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 2)", .pme_code = 1394, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 3, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_2@3", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 3)", .pme_code = 1395, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 3, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_2@4", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 4)", .pme_code = 1396, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 3, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_2@5", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 5)", .pme_code = 1397, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 3, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_2@6", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 6)", .pme_code = 1398, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 3, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_2@7", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 7)", .pme_code = 1399, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 3, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_2@8", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 8)", .pme_code = 1400, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 3, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_2@9", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 9)", .pme_code = 1401, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 3, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_2@10", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 10)", .pme_code = 1402, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 3, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_2@11", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 11)", .pme_code = 1403, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 3, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_2@12", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 12)", .pme_code = 1404, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 3, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_2@13", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 13)", .pme_code = 1405, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 3, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_2@14", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 14)", .pme_code = 1406, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 3, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_2@15", .pme_desc = "Wclk cycles MD2BW output port 2 is blocked due to channel back-pressure. (M chip 15)", .pme_code = 1407, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 18, .pme_event = 3, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 19 Event 0 */ { .pme_name = "REQUEST_4DWORDS@0", .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 0)", .pme_code = 1408, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS@1", .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 1)", .pme_code = 1409, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 0, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS@2", .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 2)", .pme_code = 1410, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 0, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS@3", .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 3)", .pme_code = 1411, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 0, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS@4", .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 4)", .pme_code = 1412, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 0, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS@5", .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 5)", .pme_code = 1413, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 0, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS@6", .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 6)", .pme_code = 1414, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 0, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS@7", .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 7)", .pme_code = 1415, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 0, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS@8", .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 8)", .pme_code = 1416, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 0, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS@9", .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 9)", .pme_code = 1417, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 0, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS@10", .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 10)", .pme_code = 1418, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 0, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS@11", .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 11)", .pme_code = 1419, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 0, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS@12", .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 12)", .pme_code = 1420, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 0, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS@13", .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 13)", .pme_code = 1421, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 0, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS@14", .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 14)", .pme_code = 1422, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 0, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS@15", .pme_desc = "Allocating read, Get and NGet full cache line requests to MDs. (M chip 15)", .pme_code = 1423, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 0, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 19 Event 1 */ { .pme_name = "@0", .pme_desc = "", .pme_code = 1424, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@1", .pme_desc = "", .pme_code = 1425, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 1, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@2", .pme_desc = "", .pme_code = 1426, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 1, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@3", .pme_desc = "", .pme_code = 1427, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 1, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@4", .pme_desc = "", .pme_code = 1428, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 1, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@5", .pme_desc = "", .pme_code = 1429, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 1, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@6", .pme_desc = "", .pme_code = 1430, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 1, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@7", .pme_desc = "", .pme_code = 1431, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 1, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@8", .pme_desc = "", .pme_code = 1432, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 1, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@9", .pme_desc = "", .pme_code = 1433, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 1, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@10", .pme_desc = "", .pme_code = 1434, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 1, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@11", .pme_desc = "", .pme_code = 1435, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 1, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@12", .pme_desc = "", .pme_code = 1436, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 1, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@13", .pme_desc = "", .pme_code = 1437, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 1, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@14", .pme_desc = "", .pme_code = 1438, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 1, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@15", .pme_desc = "", .pme_code = 1439, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 1, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 19 Event 2 */ { .pme_name = "MM1_ACCUM_BANK_BUSY@0", .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 0)", .pme_code = 1440, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ACCUM_BANK_BUSY@1", .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 1)", .pme_code = 1441, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 2, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ACCUM_BANK_BUSY@2", .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 2)", .pme_code = 1442, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 2, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ACCUM_BANK_BUSY@3", .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 3)", .pme_code = 1443, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 2, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ACCUM_BANK_BUSY@4", .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 4)", .pme_code = 1444, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 2, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ACCUM_BANK_BUSY@5", .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 5)", .pme_code = 1445, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 2, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ACCUM_BANK_BUSY@6", .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 6)", .pme_code = 1446, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 2, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ACCUM_BANK_BUSY@7", .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 7)", .pme_code = 1447, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 2, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ACCUM_BANK_BUSY@8", .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 8)", .pme_code = 1448, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 2, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ACCUM_BANK_BUSY@9", .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 9)", .pme_code = 1449, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 2, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ACCUM_BANK_BUSY@10", .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 10)", .pme_code = 1450, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 2, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ACCUM_BANK_BUSY@11", .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 11)", .pme_code = 1451, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 2, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ACCUM_BANK_BUSY@12", .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 12)", .pme_code = 1452, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 2, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ACCUM_BANK_BUSY@13", .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 13)", .pme_code = 1453, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 2, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ACCUM_BANK_BUSY@14", .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 14)", .pme_code = 1454, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 2, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM1_ACCUM_BANK_BUSY@15", .pme_desc = "Accumulation of the MM1 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 15)", .pme_code = 1455, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 2, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 19 Event 3 */ { .pme_name = "W_OUT_BLOCK_CHN_3@0", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 0)", .pme_code = 1456, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_3@1", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 1)", .pme_code = 1457, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 3, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_3@2", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 2)", .pme_code = 1458, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 3, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_3@3", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 3)", .pme_code = 1459, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 3, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_3@4", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 4)", .pme_code = 1460, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 3, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_3@5", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 5)", .pme_code = 1461, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 3, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_3@6", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 6)", .pme_code = 1462, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 3, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_3@7", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 7)", .pme_code = 1463, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 3, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_3@8", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 8)", .pme_code = 1464, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 3, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_3@9", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 9)", .pme_code = 1465, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 3, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_3@10", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 10)", .pme_code = 1466, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 3, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_3@11", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 11)", .pme_code = 1467, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 3, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_3@12", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 12)", .pme_code = 1468, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 3, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_3@13", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 13)", .pme_code = 1469, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 3, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_3@14", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 14)", .pme_code = 1470, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 3, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_BLOCK_CHN_3@15", .pme_desc = "Wclk cycles MD2BW output port 3 is blocked due to channel back-pressure. (M chip 15)", .pme_code = 1471, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 19, .pme_event = 3, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 20 Event 0 */ { .pme_name = "REQUESTS_0@0", .pme_desc = "Read or write requests from port 0 to MDs. (M chip 0)", .pme_code = 1472, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_0@1", .pme_desc = "Read or write requests from port 0 to MDs. (M chip 1)", .pme_code = 1473, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 0, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_0@2", .pme_desc = "Read or write requests from port 0 to MDs. (M chip 2)", .pme_code = 1474, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 0, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_0@3", .pme_desc = "Read or write requests from port 0 to MDs. (M chip 3)", .pme_code = 1475, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 0, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_0@4", .pme_desc = "Read or write requests from port 0 to MDs. (M chip 4)", .pme_code = 1476, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 0, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_0@5", .pme_desc = "Read or write requests from port 0 to MDs. (M chip 5)", .pme_code = 1477, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 0, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_0@6", .pme_desc = "Read or write requests from port 0 to MDs. (M chip 6)", .pme_code = 1478, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 0, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_0@7", .pme_desc = "Read or write requests from port 0 to MDs. (M chip 7)", .pme_code = 1479, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 0, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_0@8", .pme_desc = "Read or write requests from port 0 to MDs. (M chip 8)", .pme_code = 1480, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 0, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_0@9", .pme_desc = "Read or write requests from port 0 to MDs. (M chip 9)", .pme_code = 1481, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 0, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_0@10", .pme_desc = "Read or write requests from port 0 to MDs. (M chip 10)", .pme_code = 1482, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 0, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_0@11", .pme_desc = "Read or write requests from port 0 to MDs. (M chip 11)", .pme_code = 1483, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 0, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_0@12", .pme_desc = "Read or write requests from port 0 to MDs. (M chip 12)", .pme_code = 1484, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 0, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_0@13", .pme_desc = "Read or write requests from port 0 to MDs. (M chip 13)", .pme_code = 1485, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 0, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_0@14", .pme_desc = "Read or write requests from port 0 to MDs. (M chip 14)", .pme_code = 1486, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 0, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_0@15", .pme_desc = "Read or write requests from port 0 to MDs. (M chip 15)", .pme_code = 1487, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 0, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 20 Event 1 */ { .pme_name = "REQUEST_1DWORD_L3_MISS@0", .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 0)", .pme_code = 1488, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_MISS@1", .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 1)", .pme_code = 1489, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 1, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_MISS@2", .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 2)", .pme_code = 1490, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 1, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_MISS@3", .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 3)", .pme_code = 1491, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 1, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_MISS@4", .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 4)", .pme_code = 1492, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 1, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_MISS@5", .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 5)", .pme_code = 1493, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 1, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_MISS@6", .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 6)", .pme_code = 1494, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 1, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_MISS@7", .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 7)", .pme_code = 1495, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 1, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_MISS@8", .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 8)", .pme_code = 1496, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 1, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_MISS@9", .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 9)", .pme_code = 1497, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 1, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_MISS@10", .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 10)", .pme_code = 1498, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 1, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_MISS@11", .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 11)", .pme_code = 1499, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 1, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_MISS@12", .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 12)", .pme_code = 1500, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 1, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_MISS@13", .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 13)", .pme_code = 1501, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 1, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_MISS@14", .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 14)", .pme_code = 1502, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 1, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1DWORD_L3_MISS@15", .pme_desc = "Single DWord get requests to MDs - L3 miss. (M chip 15)", .pme_code = 1503, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 1, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 20 Event 2 */ { .pme_name = "MM2_ANY_BANK_BUSY@0", .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 0)", .pme_code = 1504, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ANY_BANK_BUSY@1", .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 1)", .pme_code = 1505, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 2, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ANY_BANK_BUSY@2", .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 2)", .pme_code = 1506, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 2, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ANY_BANK_BUSY@3", .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 3)", .pme_code = 1507, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 2, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ANY_BANK_BUSY@4", .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 4)", .pme_code = 1508, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 2, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ANY_BANK_BUSY@5", .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 5)", .pme_code = 1509, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 2, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ANY_BANK_BUSY@6", .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 6)", .pme_code = 1510, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 2, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ANY_BANK_BUSY@7", .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 7)", .pme_code = 1511, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 2, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ANY_BANK_BUSY@8", .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 8)", .pme_code = 1512, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 2, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ANY_BANK_BUSY@9", .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 9)", .pme_code = 1513, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 2, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ANY_BANK_BUSY@10", .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 10)", .pme_code = 1514, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 2, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ANY_BANK_BUSY@11", .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 11)", .pme_code = 1515, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 2, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ANY_BANK_BUSY@12", .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 12)", .pme_code = 1516, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 2, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ANY_BANK_BUSY@13", .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 13)", .pme_code = 1517, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 2, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ANY_BANK_BUSY@14", .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 14)", .pme_code = 1518, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 2, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ANY_BANK_BUSY@15", .pme_desc = "Wclk cycles that any bank is busy in MM2. (M chip 15)", .pme_code = 1519, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 2, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 20 Event 3 */ { .pme_name = "W_OUT_QUEUE_BP_0@0", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 0)", .pme_code = 1520, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_0@1", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 1)", .pme_code = 1521, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 3, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_0@2", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 2)", .pme_code = 1522, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 3, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_0@3", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 3)", .pme_code = 1523, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 3, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_0@4", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 4)", .pme_code = 1524, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 3, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_0@5", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 5)", .pme_code = 1525, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 3, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_0@6", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 6)", .pme_code = 1526, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 3, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_0@7", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 7)", .pme_code = 1527, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 3, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_0@8", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 8)", .pme_code = 1528, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 3, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_0@9", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 9)", .pme_code = 1529, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 3, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_0@10", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 10)", .pme_code = 1530, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 3, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_0@11", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 11)", .pme_code = 1531, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 3, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_0@12", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 12)", .pme_code = 1532, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 3, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_0@13", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 13)", .pme_code = 1533, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 3, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_0@14", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 14)", .pme_code = 1534, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 3, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_0@15", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 0 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 15)", .pme_code = 1535, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 20, .pme_event = 3, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 21 Event 0 */ { .pme_name = "REQUESTS_1@0", .pme_desc = "Read or write requests from port 1 to MDs. (M chip 0)", .pme_code = 1536, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_1@1", .pme_desc = "Read or write requests from port 1 to MDs. (M chip 1)", .pme_code = 1537, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 0, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_1@2", .pme_desc = "Read or write requests from port 1 to MDs. (M chip 2)", .pme_code = 1538, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 0, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_1@3", .pme_desc = "Read or write requests from port 1 to MDs. (M chip 3)", .pme_code = 1539, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 0, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_1@4", .pme_desc = "Read or write requests from port 1 to MDs. (M chip 4)", .pme_code = 1540, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 0, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_1@5", .pme_desc = "Read or write requests from port 1 to MDs. (M chip 5)", .pme_code = 1541, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 0, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_1@6", .pme_desc = "Read or write requests from port 1 to MDs. (M chip 6)", .pme_code = 1542, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 0, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_1@7", .pme_desc = "Read or write requests from port 1 to MDs. (M chip 7)", .pme_code = 1543, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 0, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_1@8", .pme_desc = "Read or write requests from port 1 to MDs. (M chip 8)", .pme_code = 1544, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 0, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_1@9", .pme_desc = "Read or write requests from port 1 to MDs. (M chip 9)", .pme_code = 1545, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 0, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_1@10", .pme_desc = "Read or write requests from port 1 to MDs. (M chip 10)", .pme_code = 1546, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 0, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_1@11", .pme_desc = "Read or write requests from port 1 to MDs. (M chip 11)", .pme_code = 1547, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 0, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_1@12", .pme_desc = "Read or write requests from port 1 to MDs. (M chip 12)", .pme_code = 1548, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 0, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_1@13", .pme_desc = "Read or write requests from port 1 to MDs. (M chip 13)", .pme_code = 1549, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 0, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_1@14", .pme_desc = "Read or write requests from port 1 to MDs. (M chip 14)", .pme_code = 1550, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 0, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_1@15", .pme_desc = "Read or write requests from port 1 to MDs. (M chip 15)", .pme_code = 1551, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 0, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 21 Event 1 */ { .pme_name = "REQUEST_4DWORDS_L3_MISS@0", .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 0)", .pme_code = 1552, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_MISS@1", .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 1)", .pme_code = 1553, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 1, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_MISS@2", .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 2)", .pme_code = 1554, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 1, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_MISS@3", .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 3)", .pme_code = 1555, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 1, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_MISS@4", .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 4)", .pme_code = 1556, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 1, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_MISS@5", .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 5)", .pme_code = 1557, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 1, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_MISS@6", .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 6)", .pme_code = 1558, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 1, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_MISS@7", .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 7)", .pme_code = 1559, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 1, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_MISS@8", .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 8)", .pme_code = 1560, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 1, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_MISS@9", .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 9)", .pme_code = 1561, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 1, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_MISS@10", .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 10)", .pme_code = 1562, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 1, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_MISS@11", .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 11)", .pme_code = 1563, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 1, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_MISS@12", .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 12)", .pme_code = 1564, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 1, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_MISS@13", .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 13)", .pme_code = 1565, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 1, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_MISS@14", .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 14)", .pme_code = 1566, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 1, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_4DWORDS_L3_MISS@15", .pme_desc = "Allocating read requests to MDs - L3 miss. (M chip 15)", .pme_code = 1567, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 1, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 21 Event 2 */ { .pme_name = "MM2_ACCUM_BANK_BUSY@0", .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 0)", .pme_code = 1568, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ACCUM_BANK_BUSY@1", .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 1)", .pme_code = 1569, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 2, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ACCUM_BANK_BUSY@2", .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 2)", .pme_code = 1570, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 2, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ACCUM_BANK_BUSY@3", .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 3)", .pme_code = 1571, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 2, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ACCUM_BANK_BUSY@4", .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 4)", .pme_code = 1572, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 2, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ACCUM_BANK_BUSY@5", .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 5)", .pme_code = 1573, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 2, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ACCUM_BANK_BUSY@6", .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 6)", .pme_code = 1574, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 2, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ACCUM_BANK_BUSY@7", .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 7)", .pme_code = 1575, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 2, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ACCUM_BANK_BUSY@8", .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 8)", .pme_code = 1576, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 2, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ACCUM_BANK_BUSY@9", .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 9)", .pme_code = 1577, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 2, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ACCUM_BANK_BUSY@10", .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 10)", .pme_code = 1578, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 2, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ACCUM_BANK_BUSY@11", .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 11)", .pme_code = 1579, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 2, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ACCUM_BANK_BUSY@12", .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 12)", .pme_code = 1580, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 2, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ACCUM_BANK_BUSY@13", .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 13)", .pme_code = 1581, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 2, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ACCUM_BANK_BUSY@14", .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 14)", .pme_code = 1582, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 2, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM2_ACCUM_BANK_BUSY@15", .pme_desc = "Accumulation of the MM2 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 15)", .pme_code = 1583, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 2, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 21 Event 3 */ { .pme_name = "W_OUT_QUEUE_BP_1@0", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 0)", .pme_code = 1584, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_1@1", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 1)", .pme_code = 1585, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 3, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_1@2", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 2)", .pme_code = 1586, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 3, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_1@3", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 3)", .pme_code = 1587, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 3, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_1@4", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 4)", .pme_code = 1588, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 3, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_1@5", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 5)", .pme_code = 1589, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 3, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_1@6", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 6)", .pme_code = 1590, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 3, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_1@7", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 7)", .pme_code = 1591, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 3, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_1@8", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 8)", .pme_code = 1592, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 3, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_1@9", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 9)", .pme_code = 1593, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 3, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_1@10", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 10)", .pme_code = 1594, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 3, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_1@11", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 11)", .pme_code = 1595, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 3, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_1@12", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 12)", .pme_code = 1596, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 3, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_1@13", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 13)", .pme_code = 1597, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 3, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_1@14", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 14)", .pme_code = 1598, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 3, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_1@15", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 1 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 15)", .pme_code = 1599, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 21, .pme_event = 3, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 22 Event 0 */ { .pme_name = "REQUESTS_2@0", .pme_desc = "Read or write requests from port 2 to MDs. (M chip 0)", .pme_code = 1600, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_2@1", .pme_desc = "Read or write requests from port 2 to MDs. (M chip 1)", .pme_code = 1601, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 0, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_2@2", .pme_desc = "Read or write requests from port 2 to MDs. (M chip 2)", .pme_code = 1602, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 0, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_2@3", .pme_desc = "Read or write requests from port 2 to MDs. (M chip 3)", .pme_code = 1603, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 0, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_2@4", .pme_desc = "Read or write requests from port 2 to MDs. (M chip 4)", .pme_code = 1604, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 0, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_2@5", .pme_desc = "Read or write requests from port 2 to MDs. (M chip 5)", .pme_code = 1605, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 0, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_2@6", .pme_desc = "Read or write requests from port 2 to MDs. (M chip 6)", .pme_code = 1606, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 0, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_2@7", .pme_desc = "Read or write requests from port 2 to MDs. (M chip 7)", .pme_code = 1607, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 0, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_2@8", .pme_desc = "Read or write requests from port 2 to MDs. (M chip 8)", .pme_code = 1608, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 0, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_2@9", .pme_desc = "Read or write requests from port 2 to MDs. (M chip 9)", .pme_code = 1609, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 0, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_2@10", .pme_desc = "Read or write requests from port 2 to MDs. (M chip 10)", .pme_code = 1610, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 0, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_2@11", .pme_desc = "Read or write requests from port 2 to MDs. (M chip 11)", .pme_code = 1611, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 0, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_2@12", .pme_desc = "Read or write requests from port 2 to MDs. (M chip 12)", .pme_code = 1612, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 0, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_2@13", .pme_desc = "Read or write requests from port 2 to MDs. (M chip 13)", .pme_code = 1613, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 0, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_2@14", .pme_desc = "Read or write requests from port 2 to MDs. (M chip 14)", .pme_code = 1614, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 0, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_2@15", .pme_desc = "Read or write requests from port 2 to MDs. (M chip 15)", .pme_code = 1615, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 0, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 22 Event 1 */ { .pme_name = "REQUEST_1SWORD@0", .pme_desc = "Single SWord requests to MDs. (M chip 0)", .pme_code = 1616, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1SWORD@1", .pme_desc = "Single SWord requests to MDs. (M chip 1)", .pme_code = 1617, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 1, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1SWORD@2", .pme_desc = "Single SWord requests to MDs. (M chip 2)", .pme_code = 1618, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 1, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1SWORD@3", .pme_desc = "Single SWord requests to MDs. (M chip 3)", .pme_code = 1619, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 1, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1SWORD@4", .pme_desc = "Single SWord requests to MDs. (M chip 4)", .pme_code = 1620, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 1, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1SWORD@5", .pme_desc = "Single SWord requests to MDs. (M chip 5)", .pme_code = 1621, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 1, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1SWORD@6", .pme_desc = "Single SWord requests to MDs. (M chip 6)", .pme_code = 1622, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 1, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1SWORD@7", .pme_desc = "Single SWord requests to MDs. (M chip 7)", .pme_code = 1623, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 1, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1SWORD@8", .pme_desc = "Single SWord requests to MDs. (M chip 8)", .pme_code = 1624, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 1, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1SWORD@9", .pme_desc = "Single SWord requests to MDs. (M chip 9)", .pme_code = 1625, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 1, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1SWORD@10", .pme_desc = "Single SWord requests to MDs. (M chip 10)", .pme_code = 1626, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 1, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1SWORD@11", .pme_desc = "Single SWord requests to MDs. (M chip 11)", .pme_code = 1627, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 1, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1SWORD@12", .pme_desc = "Single SWord requests to MDs. (M chip 12)", .pme_code = 1628, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 1, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1SWORD@13", .pme_desc = "Single SWord requests to MDs. (M chip 13)", .pme_code = 1629, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 1, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1SWORD@14", .pme_desc = "Single SWord requests to MDs. (M chip 14)", .pme_code = 1630, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 1, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUEST_1SWORD@15", .pme_desc = "Single SWord requests to MDs. (M chip 15)", .pme_code = 1631, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 1, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 22 Event 2 */ { .pme_name = "MM3_ANY_BANK_BUSY@0", .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 0)", .pme_code = 1632, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ANY_BANK_BUSY@1", .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 1)", .pme_code = 1633, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 2, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ANY_BANK_BUSY@2", .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 2)", .pme_code = 1634, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 2, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ANY_BANK_BUSY@3", .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 3)", .pme_code = 1635, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 2, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ANY_BANK_BUSY@4", .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 4)", .pme_code = 1636, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 2, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ANY_BANK_BUSY@5", .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 5)", .pme_code = 1637, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 2, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ANY_BANK_BUSY@6", .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 6)", .pme_code = 1638, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 2, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ANY_BANK_BUSY@7", .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 7)", .pme_code = 1639, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 2, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ANY_BANK_BUSY@8", .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 8)", .pme_code = 1640, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 2, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ANY_BANK_BUSY@9", .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 9)", .pme_code = 1641, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 2, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ANY_BANK_BUSY@10", .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 10)", .pme_code = 1642, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 2, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ANY_BANK_BUSY@11", .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 11)", .pme_code = 1643, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 2, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ANY_BANK_BUSY@12", .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 12)", .pme_code = 1644, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 2, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ANY_BANK_BUSY@13", .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 13)", .pme_code = 1645, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 2, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ANY_BANK_BUSY@14", .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 14)", .pme_code = 1646, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 2, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ANY_BANK_BUSY@15", .pme_desc = "Wclk cycles that any bank is busy in MM3. (M chip 15)", .pme_code = 1647, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 2, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 22 Event 3 */ { .pme_name = "W_OUT_QUEUE_BP_2@0", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 0)", .pme_code = 1648, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_2@1", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 1)", .pme_code = 1649, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 3, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_2@2", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 2)", .pme_code = 1650, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 3, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_2@3", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 3)", .pme_code = 1651, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 3, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_2@4", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 4)", .pme_code = 1652, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 3, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_2@5", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 5)", .pme_code = 1653, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 3, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_2@6", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 6)", .pme_code = 1654, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 3, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_2@7", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 7)", .pme_code = 1655, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 3, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_2@8", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 8)", .pme_code = 1656, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 3, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_2@9", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 9)", .pme_code = 1657, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 3, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_2@10", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 10)", .pme_code = 1658, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 3, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_2@11", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 11)", .pme_code = 1659, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 3, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_2@12", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 12)", .pme_code = 1660, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 3, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_2@13", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 13)", .pme_code = 1661, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 3, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_2@14", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 14)", .pme_code = 1662, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 3, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_2@15", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 2 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 15)", .pme_code = 1663, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 22, .pme_event = 3, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 23 Event 0 */ { .pme_name = "REQUESTS_3@0", .pme_desc = "Read or write requests from port 3 to MDs. (M chip 0)", .pme_code = 1664, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_3@1", .pme_desc = "Read or write requests from port 3 to MDs. (M chip 1)", .pme_code = 1665, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 0, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_3@2", .pme_desc = "Read or write requests from port 3 to MDs. (M chip 2)", .pme_code = 1666, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 0, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_3@3", .pme_desc = "Read or write requests from port 3 to MDs. (M chip 3)", .pme_code = 1667, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 0, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_3@4", .pme_desc = "Read or write requests from port 3 to MDs. (M chip 4)", .pme_code = 1668, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 0, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_3@5", .pme_desc = "Read or write requests from port 3 to MDs. (M chip 5)", .pme_code = 1669, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 0, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_3@6", .pme_desc = "Read or write requests from port 3 to MDs. (M chip 6)", .pme_code = 1670, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 0, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_3@7", .pme_desc = "Read or write requests from port 3 to MDs. (M chip 7)", .pme_code = 1671, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 0, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_3@8", .pme_desc = "Read or write requests from port 3 to MDs. (M chip 8)", .pme_code = 1672, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 0, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_3@9", .pme_desc = "Read or write requests from port 3 to MDs. (M chip 9)", .pme_code = 1673, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 0, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_3@10", .pme_desc = "Read or write requests from port 3 to MDs. (M chip 10)", .pme_code = 1674, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 0, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_3@11", .pme_desc = "Read or write requests from port 3 to MDs. (M chip 11)", .pme_code = 1675, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 0, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_3@12", .pme_desc = "Read or write requests from port 3 to MDs. (M chip 12)", .pme_code = 1676, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 0, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_3@13", .pme_desc = "Read or write requests from port 3 to MDs. (M chip 13)", .pme_code = 1677, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 0, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_3@14", .pme_desc = "Read or write requests from port 3 to MDs. (M chip 14)", .pme_code = 1678, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 0, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "REQUESTS_3@15", .pme_desc = "Read or write requests from port 3 to MDs. (M chip 15)", .pme_code = 1679, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 0, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 23 Event 1 */ { .pme_name = "@0", .pme_desc = "", .pme_code = 1680, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@1", .pme_desc = "", .pme_code = 1681, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 1, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@2", .pme_desc = "", .pme_code = 1682, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 1, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@3", .pme_desc = "", .pme_code = 1683, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 1, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@4", .pme_desc = "", .pme_code = 1684, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 1, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@5", .pme_desc = "", .pme_code = 1685, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 1, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@6", .pme_desc = "", .pme_code = 1686, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 1, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@7", .pme_desc = "", .pme_code = 1687, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 1, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@8", .pme_desc = "", .pme_code = 1688, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 1, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@9", .pme_desc = "", .pme_code = 1689, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 1, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@10", .pme_desc = "", .pme_code = 1690, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 1, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@11", .pme_desc = "", .pme_code = 1691, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 1, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@12", .pme_desc = "", .pme_code = 1692, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 1, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@13", .pme_desc = "", .pme_code = 1693, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 1, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@14", .pme_desc = "", .pme_code = 1694, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 1, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@15", .pme_desc = "", .pme_code = 1695, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 1, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 23 Event 2 */ { .pme_name = "MM3_ACCUM_BANK_BUSY@0", .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 0)", .pme_code = 1696, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ACCUM_BANK_BUSY@1", .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 1)", .pme_code = 1697, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 2, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ACCUM_BANK_BUSY@2", .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 2)", .pme_code = 1698, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 2, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ACCUM_BANK_BUSY@3", .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 3)", .pme_code = 1699, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 2, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ACCUM_BANK_BUSY@4", .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 4)", .pme_code = 1700, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 2, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ACCUM_BANK_BUSY@5", .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 5)", .pme_code = 1701, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 2, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ACCUM_BANK_BUSY@6", .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 6)", .pme_code = 1702, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 2, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ACCUM_BANK_BUSY@7", .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 7)", .pme_code = 1703, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 2, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ACCUM_BANK_BUSY@8", .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 8)", .pme_code = 1704, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 2, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ACCUM_BANK_BUSY@9", .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 9)", .pme_code = 1705, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 2, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ACCUM_BANK_BUSY@10", .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 10)", .pme_code = 1706, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 2, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ACCUM_BANK_BUSY@11", .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 11)", .pme_code = 1707, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 2, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ACCUM_BANK_BUSY@12", .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 12)", .pme_code = 1708, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 2, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ACCUM_BANK_BUSY@13", .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 13)", .pme_code = 1709, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 2, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ACCUM_BANK_BUSY@14", .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 14)", .pme_code = 1710, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 2, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "MM3_ACCUM_BANK_BUSY@15", .pme_desc = "Accumulation of the MM3 memory banks are busy in Mclks. There are 8 banks per MM and this counter will be +1 every Mclk that 1 bank is busy, +2 every Mclk that 2 banks are busy, etc. (M chip 15)", .pme_code = 1711, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 2, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 23 Event 3 */ { .pme_name = "W_OUT_QUEUE_BP_3@0", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 0)", .pme_code = 1712, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_3@1", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 1)", .pme_code = 1713, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 3, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_3@2", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 2)", .pme_code = 1714, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 3, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_3@3", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 3)", .pme_code = 1715, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 3, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_3@4", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 4)", .pme_code = 1716, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 3, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_3@5", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 5)", .pme_code = 1717, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 3, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_3@6", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 6)", .pme_code = 1718, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 3, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_3@7", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 7)", .pme_code = 1719, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 3, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_3@8", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 8)", .pme_code = 1720, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 3, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_3@9", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 9)", .pme_code = 1721, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 3, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_3@10", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 10)", .pme_code = 1722, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 3, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_3@11", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 11)", .pme_code = 1723, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 3, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_3@12", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 12)", .pme_code = 1724, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 3, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_3@13", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 13)", .pme_code = 1725, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 3, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_3@14", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 14)", .pme_code = 1726, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 3, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_OUT_QUEUE_BP_3@15", .pme_desc = "One of the input FIFOs that is destined for MD2BW output port 3 is full and asserting back-pressure to the MD (Wclk cycles). (M chip 15)", .pme_code = 1727, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 23, .pme_event = 3, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 24 Event 0 */ { .pme_name = "W_SWORD_PUTS@0", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 0)", .pme_code = 1728, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_PUTS@1", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 1)", .pme_code = 1729, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 0, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_PUTS@2", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 2)", .pme_code = 1730, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 0, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_PUTS@3", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 3)", .pme_code = 1731, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 0, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_PUTS@4", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 4)", .pme_code = 1732, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 0, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_PUTS@5", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 5)", .pme_code = 1733, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 0, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_PUTS@6", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 6)", .pme_code = 1734, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 0, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_PUTS@7", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 7)", .pme_code = 1735, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 0, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_PUTS@8", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 8)", .pme_code = 1736, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 0, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_PUTS@9", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 9)", .pme_code = 1737, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 0, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_PUTS@10", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 10)", .pme_code = 1738, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 0, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_PUTS@11", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 11)", .pme_code = 1739, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 0, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_PUTS@12", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 12)", .pme_code = 1740, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 0, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_PUTS@13", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 13)", .pme_code = 1741, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 0, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_PUTS@14", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 14)", .pme_code = 1742, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 0, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_PUTS@15", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with Put commands. Counts up to 2 SWords per memory directory per clock period. (M chip 15)", .pme_code = 1743, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 0, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 24 Event 1 */ { .pme_name = "@0", .pme_desc = "", .pme_code = 1744, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@1", .pme_desc = "", .pme_code = 1745, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 1, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@2", .pme_desc = "", .pme_code = 1746, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 1, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@3", .pme_desc = "", .pme_code = 1747, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 1, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@4", .pme_desc = "", .pme_code = 1748, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 1, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@5", .pme_desc = "", .pme_code = 1749, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 1, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@6", .pme_desc = "", .pme_code = 1750, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 1, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@7", .pme_desc = "", .pme_code = 1751, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 1, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@8", .pme_desc = "", .pme_code = 1752, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 1, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@9", .pme_desc = "", .pme_code = 1753, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 1, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@10", .pme_desc = "", .pme_code = 1754, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 1, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@11", .pme_desc = "", .pme_code = 1755, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 1, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@12", .pme_desc = "", .pme_code = 1756, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 1, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@13", .pme_desc = "", .pme_code = 1757, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 1, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@14", .pme_desc = "", .pme_code = 1758, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 1, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@15", .pme_desc = "", .pme_code = 1759, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 1, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 24 Event 2 */ { .pme_name = "@0", .pme_desc = "", .pme_code = 1760, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@1", .pme_desc = "", .pme_code = 1761, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 2, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@2", .pme_desc = "", .pme_code = 1762, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 2, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@3", .pme_desc = "", .pme_code = 1763, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 2, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@4", .pme_desc = "", .pme_code = 1764, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 2, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@5", .pme_desc = "", .pme_code = 1765, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 2, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@6", .pme_desc = "", .pme_code = 1766, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 2, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@7", .pme_desc = "", .pme_code = 1767, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 2, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@8", .pme_desc = "", .pme_code = 1768, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 2, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@9", .pme_desc = "", .pme_code = 1769, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 2, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@10", .pme_desc = "", .pme_code = 1770, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 2, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@11", .pme_desc = "", .pme_code = 1771, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 2, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@12", .pme_desc = "", .pme_code = 1772, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 2, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@13", .pme_desc = "", .pme_code = 1773, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 2, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@14", .pme_desc = "", .pme_code = 1774, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 2, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@15", .pme_desc = "", .pme_code = 1775, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 2, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 24 Event 3 */ { .pme_name = "@0", .pme_desc = "", .pme_code = 1776, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@1", .pme_desc = "", .pme_code = 1777, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 3, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@2", .pme_desc = "", .pme_code = 1778, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 3, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@3", .pme_desc = "", .pme_code = 1779, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 3, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@4", .pme_desc = "", .pme_code = 1780, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 3, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@5", .pme_desc = "", .pme_code = 1781, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 3, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@6", .pme_desc = "", .pme_code = 1782, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 3, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@7", .pme_desc = "", .pme_code = 1783, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 3, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@8", .pme_desc = "", .pme_code = 1784, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 3, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@9", .pme_desc = "", .pme_code = 1785, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 3, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@10", .pme_desc = "", .pme_code = 1786, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 3, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@11", .pme_desc = "", .pme_code = 1787, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 3, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@12", .pme_desc = "", .pme_code = 1788, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 3, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@13", .pme_desc = "", .pme_code = 1789, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 3, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@14", .pme_desc = "", .pme_code = 1790, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 3, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@15", .pme_desc = "", .pme_code = 1791, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 24, .pme_event = 3, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 25 Event 0 */ { .pme_name = "W_SWORD_NPUTS@0", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 0)", .pme_code = 1792, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NPUTS@1", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 1)", .pme_code = 1793, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 0, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NPUTS@2", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 2)", .pme_code = 1794, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 0, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NPUTS@3", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 3)", .pme_code = 1795, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 0, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NPUTS@4", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 4)", .pme_code = 1796, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 0, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NPUTS@5", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 5)", .pme_code = 1797, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 0, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NPUTS@6", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 6)", .pme_code = 1798, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 0, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NPUTS@7", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 7)", .pme_code = 1799, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 0, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NPUTS@8", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 8)", .pme_code = 1800, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 0, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NPUTS@9", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 9)", .pme_code = 1801, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 0, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NPUTS@10", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 10)", .pme_code = 1802, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 0, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NPUTS@11", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 11)", .pme_code = 1803, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 0, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NPUTS@12", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 12)", .pme_code = 1804, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 0, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NPUTS@13", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 13)", .pme_code = 1805, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 0, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NPUTS@14", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 14)", .pme_code = 1806, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 0, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NPUTS@15", .pme_desc = "Count of the total number of SWords that are written to memory or the L3 cache with NPut commands. Counts up to 2 SWords per memory directory per clock period. (M chip 15)", .pme_code = 1807, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 0, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 25 Event 1 */ { .pme_name = "@0", .pme_desc = "", .pme_code = 1808, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@1", .pme_desc = "", .pme_code = 1809, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 1, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@2", .pme_desc = "", .pme_code = 1810, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 1, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@3", .pme_desc = "", .pme_code = 1811, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 1, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@4", .pme_desc = "", .pme_code = 1812, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 1, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@5", .pme_desc = "", .pme_code = 1813, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 1, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@6", .pme_desc = "", .pme_code = 1814, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 1, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@7", .pme_desc = "", .pme_code = 1815, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 1, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@8", .pme_desc = "", .pme_code = 1816, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 1, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@9", .pme_desc = "", .pme_code = 1817, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 1, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@10", .pme_desc = "", .pme_code = 1818, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 1, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@11", .pme_desc = "", .pme_code = 1819, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 1, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@12", .pme_desc = "", .pme_code = 1820, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 1, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@13", .pme_desc = "", .pme_code = 1821, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 1, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@14", .pme_desc = "", .pme_code = 1822, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 1, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@15", .pme_desc = "", .pme_code = 1823, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 1, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 25 Event 2 */ { .pme_name = "@0", .pme_desc = "", .pme_code = 1824, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@1", .pme_desc = "", .pme_code = 1825, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 2, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@2", .pme_desc = "", .pme_code = 1826, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 2, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@3", .pme_desc = "", .pme_code = 1827, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 2, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@4", .pme_desc = "", .pme_code = 1828, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 2, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@5", .pme_desc = "", .pme_code = 1829, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 2, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@6", .pme_desc = "", .pme_code = 1830, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 2, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@7", .pme_desc = "", .pme_code = 1831, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 2, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@8", .pme_desc = "", .pme_code = 1832, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 2, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@9", .pme_desc = "", .pme_code = 1833, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 2, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@10", .pme_desc = "", .pme_code = 1834, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 2, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@11", .pme_desc = "", .pme_code = 1835, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 2, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@12", .pme_desc = "", .pme_code = 1836, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 2, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@13", .pme_desc = "", .pme_code = 1837, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 2, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@14", .pme_desc = "", .pme_code = 1838, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 2, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@15", .pme_desc = "", .pme_code = 1839, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 2, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 25 Event 3 */ { .pme_name = "@0", .pme_desc = "", .pme_code = 1840, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@1", .pme_desc = "", .pme_code = 1841, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 3, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@2", .pme_desc = "", .pme_code = 1842, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 3, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@3", .pme_desc = "", .pme_code = 1843, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 3, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@4", .pme_desc = "", .pme_code = 1844, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 3, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@5", .pme_desc = "", .pme_code = 1845, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 3, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@6", .pme_desc = "", .pme_code = 1846, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 3, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@7", .pme_desc = "", .pme_code = 1847, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 3, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@8", .pme_desc = "", .pme_code = 1848, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 3, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@9", .pme_desc = "", .pme_code = 1849, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 3, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@10", .pme_desc = "", .pme_code = 1850, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 3, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@11", .pme_desc = "", .pme_code = 1851, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 3, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@12", .pme_desc = "", .pme_code = 1852, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 3, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@13", .pme_desc = "", .pme_code = 1853, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 3, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@14", .pme_desc = "", .pme_code = 1854, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 3, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@15", .pme_desc = "", .pme_code = 1855, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 25, .pme_event = 3, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 26 Event 0 */ { .pme_name = "W_SWORD_GETS@0", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 0)", .pme_code = 1856, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_GETS@1", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 1)", .pme_code = 1857, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 0, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_GETS@2", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 2)", .pme_code = 1858, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 0, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_GETS@3", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 3)", .pme_code = 1859, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 0, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_GETS@4", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 4)", .pme_code = 1860, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 0, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_GETS@5", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 5)", .pme_code = 1861, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 0, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_GETS@6", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 6)", .pme_code = 1862, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 0, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_GETS@7", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 7)", .pme_code = 1863, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 0, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_GETS@8", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 8)", .pme_code = 1864, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 0, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_GETS@9", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 9)", .pme_code = 1865, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 0, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_GETS@10", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 10)", .pme_code = 1866, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 0, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_GETS@11", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 11)", .pme_code = 1867, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 0, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_GETS@12", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 12)", .pme_code = 1868, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 0, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_GETS@13", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 13)", .pme_code = 1869, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 0, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_GETS@14", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 14)", .pme_code = 1870, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 0, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_GETS@15", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with Get commands. Counts up to 2 SWords per memory directory per clock period. (M chip 15)", .pme_code = 1871, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 0, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 26 Event 1 */ { .pme_name = "@0", .pme_desc = "", .pme_code = 1872, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@1", .pme_desc = "", .pme_code = 1873, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 1, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@2", .pme_desc = "", .pme_code = 1874, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 1, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@3", .pme_desc = "", .pme_code = 1875, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 1, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@4", .pme_desc = "", .pme_code = 1876, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 1, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@5", .pme_desc = "", .pme_code = 1877, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 1, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@6", .pme_desc = "", .pme_code = 1878, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 1, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@7", .pme_desc = "", .pme_code = 1879, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 1, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@8", .pme_desc = "", .pme_code = 1880, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 1, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@9", .pme_desc = "", .pme_code = 1881, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 1, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@10", .pme_desc = "", .pme_code = 1882, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 1, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@11", .pme_desc = "", .pme_code = 1883, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 1, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@12", .pme_desc = "", .pme_code = 1884, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 1, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@13", .pme_desc = "", .pme_code = 1885, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 1, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@14", .pme_desc = "", .pme_code = 1886, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 1, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@15", .pme_desc = "", .pme_code = 1887, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 1, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 26 Event 2 */ { .pme_name = "@0", .pme_desc = "", .pme_code = 1888, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@1", .pme_desc = "", .pme_code = 1889, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 2, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@2", .pme_desc = "", .pme_code = 1890, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 2, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@3", .pme_desc = "", .pme_code = 1891, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 2, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@4", .pme_desc = "", .pme_code = 1892, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 2, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@5", .pme_desc = "", .pme_code = 1893, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 2, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@6", .pme_desc = "", .pme_code = 1894, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 2, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@7", .pme_desc = "", .pme_code = 1895, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 2, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@8", .pme_desc = "", .pme_code = 1896, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 2, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@9", .pme_desc = "", .pme_code = 1897, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 2, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@10", .pme_desc = "", .pme_code = 1898, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 2, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@11", .pme_desc = "", .pme_code = 1899, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 2, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@12", .pme_desc = "", .pme_code = 1900, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 2, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@13", .pme_desc = "", .pme_code = 1901, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 2, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@14", .pme_desc = "", .pme_code = 1902, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 2, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@15", .pme_desc = "", .pme_code = 1903, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 2, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 26 Event 3 */ { .pme_name = "@0", .pme_desc = "", .pme_code = 1904, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@1", .pme_desc = "", .pme_code = 1905, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 3, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@2", .pme_desc = "", .pme_code = 1906, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 3, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@3", .pme_desc = "", .pme_code = 1907, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 3, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@4", .pme_desc = "", .pme_code = 1908, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 3, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@5", .pme_desc = "", .pme_code = 1909, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 3, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@6", .pme_desc = "", .pme_code = 1910, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 3, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@7", .pme_desc = "", .pme_code = 1911, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 3, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@8", .pme_desc = "", .pme_code = 1912, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 3, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@9", .pme_desc = "", .pme_code = 1913, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 3, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@10", .pme_desc = "", .pme_code = 1914, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 3, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@11", .pme_desc = "", .pme_code = 1915, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 3, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@12", .pme_desc = "", .pme_code = 1916, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 3, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@13", .pme_desc = "", .pme_code = 1917, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 3, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@14", .pme_desc = "", .pme_code = 1918, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 3, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@15", .pme_desc = "", .pme_code = 1919, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 26, .pme_event = 3, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 27 Event 0 */ { .pme_name = "W_SWORD_NGETS@0", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 0)", .pme_code = 1920, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 0, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NGETS@1", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 1)", .pme_code = 1921, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 0, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NGETS@2", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 2)", .pme_code = 1922, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 0, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NGETS@3", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 3)", .pme_code = 1923, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 0, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NGETS@4", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 4)", .pme_code = 1924, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 0, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NGETS@5", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 5)", .pme_code = 1925, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 0, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NGETS@6", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 6)", .pme_code = 1926, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 0, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NGETS@7", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 7)", .pme_code = 1927, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 0, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NGETS@8", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 8)", .pme_code = 1928, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 0, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NGETS@9", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 9)", .pme_code = 1929, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 0, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NGETS@10", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 10)", .pme_code = 1930, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 0, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NGETS@11", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 11)", .pme_code = 1931, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 0, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NGETS@12", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 12)", .pme_code = 1932, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 0, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NGETS@13", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 13)", .pme_code = 1933, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 0, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NGETS@14", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 14)", .pme_code = 1934, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 0, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "W_SWORD_NGETS@15", .pme_desc = "Count of the total number of SWords that are read from memory or the L3 cache with NGet commands. Counts up to 2 SWords per memory directory per clock period. (M chip 15)", .pme_code = 1935, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 0, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 27 Event 1 */ { .pme_name = "@0", .pme_desc = "", .pme_code = 1936, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 1, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@1", .pme_desc = "", .pme_code = 1937, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 1, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@2", .pme_desc = "", .pme_code = 1938, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 1, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@3", .pme_desc = "", .pme_code = 1939, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 1, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@4", .pme_desc = "", .pme_code = 1940, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 1, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@5", .pme_desc = "", .pme_code = 1941, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 1, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@6", .pme_desc = "", .pme_code = 1942, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 1, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@7", .pme_desc = "", .pme_code = 1943, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 1, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@8", .pme_desc = "", .pme_code = 1944, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 1, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@9", .pme_desc = "", .pme_code = 1945, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 1, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@10", .pme_desc = "", .pme_code = 1946, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 1, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@11", .pme_desc = "", .pme_code = 1947, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 1, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@12", .pme_desc = "", .pme_code = 1948, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 1, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@13", .pme_desc = "", .pme_code = 1949, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 1, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@14", .pme_desc = "", .pme_code = 1950, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 1, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@15", .pme_desc = "", .pme_code = 1951, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 1, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 27 Event 2 */ { .pme_name = "@0", .pme_desc = "", .pme_code = 1952, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 2, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@1", .pme_desc = "", .pme_code = 1953, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 2, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@2", .pme_desc = "", .pme_code = 1954, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 2, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@3", .pme_desc = "", .pme_code = 1955, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 2, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@4", .pme_desc = "", .pme_code = 1956, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 2, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@5", .pme_desc = "", .pme_code = 1957, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 2, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@6", .pme_desc = "", .pme_code = 1958, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 2, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@7", .pme_desc = "", .pme_code = 1959, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 2, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@8", .pme_desc = "", .pme_code = 1960, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 2, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@9", .pme_desc = "", .pme_code = 1961, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 2, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@10", .pme_desc = "", .pme_code = 1962, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 2, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@11", .pme_desc = "", .pme_code = 1963, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 2, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@12", .pme_desc = "", .pme_code = 1964, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 2, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@13", .pme_desc = "", .pme_code = 1965, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 2, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@14", .pme_desc = "", .pme_code = 1966, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 2, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@15", .pme_desc = "", .pme_code = 1967, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 2, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, /* M Counter 27 Event 3 */ { .pme_name = "@0", .pme_desc = "", .pme_code = 1968, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 3, .pme_chipno = 0, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@1", .pme_desc = "", .pme_code = 1969, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 3, .pme_chipno = 1, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@2", .pme_desc = "", .pme_code = 1970, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 3, .pme_chipno = 2, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@3", .pme_desc = "", .pme_code = 1971, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 3, .pme_chipno = 3, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@4", .pme_desc = "", .pme_code = 1972, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 3, .pme_chipno = 4, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@5", .pme_desc = "", .pme_code = 1973, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 3, .pme_chipno = 5, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@6", .pme_desc = "", .pme_code = 1974, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 3, .pme_chipno = 6, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@7", .pme_desc = "", .pme_code = 1975, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 3, .pme_chipno = 7, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@8", .pme_desc = "", .pme_code = 1976, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 3, .pme_chipno = 8, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@9", .pme_desc = "", .pme_code = 1977, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 3, .pme_chipno = 9, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@10", .pme_desc = "", .pme_code = 1978, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 3, .pme_chipno = 10, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@11", .pme_desc = "", .pme_code = 1979, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 3, .pme_chipno = 11, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@12", .pme_desc = "", .pme_code = 1980, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 3, .pme_chipno = 12, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@13", .pme_desc = "", .pme_code = 1981, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 3, .pme_chipno = 13, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@14", .pme_desc = "", .pme_code = 1982, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 3, .pme_chipno = 14, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, { .pme_name = "@15", .pme_desc = "", .pme_code = 1983, .pme_flags = 0x0, .pme_numasks = 0, .pme_chip = PME_CRAYX2_CHIP_MEMORY, .pme_ctr = 27, .pme_event = 3, .pme_chipno = 15, .pme_base = PMU_CRAYX2_MEMORY_PMD_BASE, .pme_nctrs = PME_CRAYX2_MEMORY_CTRS_PER_CHIP, .pme_nchips = PME_CRAYX2_MEMORY_CHIPS }, }; #define PME_CRAYX2_CYCLES 0 #define PME_CRAYX2_INSTR_GRADUATED 4 #define PME_CRAYX2_EVENT_COUNT (sizeof(crayx2_pe)/sizeof(pme_crayx2_entry_t)) #endif /* __CRAYX2_EVENTS_H__ */ papi-5.5.1/src/libpfm-3.y/lib/intel_wsm_unc_events.h0000644000307100002310000010305413013651450022276 0ustar yarkhangraduate/* * Copyright (c) 2010 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ static pme_nhm_entry_t intel_wsm_unc_pe[]={ /* * BEGIN uncore events */ { .pme_name = "UNC_CLK_UNHALTED", .pme_desc = "Uncore clockticks.", .pme_code = 0x0000, .pme_flags = PFMLIB_NHM_UNC_FIXED, }, { .pme_name = "UNC_DRAM_OPEN", .pme_desc = "DRAM open comamnds issued for read or write", .pme_code = 0x60, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CH0", .pme_udesc = "DRAM Channel 0 open comamnds issued for read or write", .pme_ucode = 0x01, }, { .pme_uname = "CH1", .pme_udesc = "DRAM Channel 1 open comamnds issued for read or write", .pme_ucode = 0x02, }, { .pme_uname = "CH2", .pme_udesc = "DRAM Channel 2 open comamnds issued for read or write", .pme_ucode = 0x04, }, }, .pme_numasks = 3 }, { .pme_name = "UNC_GC_OCCUPANCY", .pme_desc = "Number of queue entries", .pme_code = 0x02, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "READ_TRACKER", .pme_udesc = "in the read tracker", .pme_ucode = 0x01, }, }, .pme_numasks = 1 }, { .pme_name = "UNC_DRAM_PAGE_CLOSE", .pme_desc = "DRAM page close due to idle timer expiration", .pme_code = 0x61, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CH0", .pme_udesc = "DRAM Channel 0 page close", .pme_ucode = 0x01, }, { .pme_uname = "CH1", .pme_udesc = "DRAM Channel 1 page close", .pme_ucode = 0x02, }, { .pme_uname = "CH2", .pme_udesc = "DRAM Channel 2 page close", .pme_ucode = 0x04, }, }, .pme_numasks = 3 }, { .pme_name = "UNC_DRAM_PAGE_MISS", .pme_desc = "DRAM Channel 0 page miss", .pme_code = 0x62, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CH0", .pme_udesc = "DRAM Channel 0 page miss", .pme_ucode = 0x01, }, { .pme_uname = "CH1", .pme_udesc = "DRAM Channel 1 page miss", .pme_ucode = 0x02, }, { .pme_uname = "CH2", .pme_udesc = "DRAM Channel 2 page miss", .pme_ucode = 0x04, }, }, .pme_numasks = 3 }, { .pme_name = "UNC_DRAM_PRE_ALL", .pme_desc = "DRAM Channel 0 precharge all commands", .pme_code = 0x66, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CH0", .pme_udesc = "DRAM Channel 0 precharge all commands", .pme_ucode = 0x01, }, { .pme_uname = "CH1", .pme_udesc = "DRAM Channel 1 precharge all commands", .pme_ucode = 0x02, }, { .pme_uname = "CH2", .pme_udesc = "DRAM Channel 2 precharge all commands", .pme_ucode = 0x04, }, }, .pme_numasks = 3 }, { .pme_name = "UNC_DRAM_THERMAL_THROTTLED", .pme_desc = "uncore cycles DRAM was throttled due to its temperature being above thermal throttling threshold", .pme_code = 0x0167, .pme_flags = PFMLIB_NHM_UNC, }, { .pme_name = "UNC_DRAM_READ_CAS", .pme_desc = "DRAM Channel 0 read CAS commands", .pme_code = 0x63, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CH0", .pme_udesc = "DRAM Channel 0 read CAS commands", .pme_ucode = 0x01, }, { .pme_uname = "AUTOPRE_CH0", .pme_udesc = "DRAM Channel 0 read CAS auto page close commands", .pme_ucode = 0x02, }, { .pme_uname = "CH1", .pme_udesc = "DRAM Channel 1 read CAS commands", .pme_ucode = 0x04, }, { .pme_uname = "AUTOPRE_CH1", .pme_udesc = "DRAM Channel 1 read CAS auto page close commands", .pme_ucode = 0x08, }, { .pme_uname = "CH2", .pme_udesc = "DRAM Channel 2 read CAS commands", .pme_ucode = 0x10, }, { .pme_uname = "AUTOPRE_CH2", .pme_udesc = "DRAM Channel 2 read CAS auto page close commands", .pme_ucode = 0x20, }, }, .pme_numasks = 6 }, { .pme_name = "UNC_DRAM_REFRESH", .pme_desc = "DRAM Channel 0 refresh commands", .pme_code = 0x65, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CH0", .pme_udesc = "DRAM Channel 0 refresh commands", .pme_ucode = 0x01, }, { .pme_uname = "CH1", .pme_udesc = "DRAM Channel 1 refresh commands", .pme_ucode = 0x02, }, { .pme_uname = "CH2", .pme_udesc = "DRAM Channel 2 refresh commands", .pme_ucode = 0x04, }, }, .pme_numasks = 3 }, { .pme_name = "UNC_DRAM_WRITE_CAS", .pme_desc = "DRAM Channel 0 write CAS commands", .pme_code = 0x64, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CH0", .pme_udesc = "DRAM Channel 0 write CAS commands", .pme_ucode = 0x01, }, { .pme_uname = "AUTOPRE_CH0", .pme_udesc = "DRAM Channel 0 write CAS auto page close commands", .pme_ucode = 0x02, }, { .pme_uname = "CH1", .pme_udesc = "DRAM Channel 1 write CAS commands", .pme_ucode = 0x04, }, { .pme_uname = "AUTOPRE_CH1", .pme_udesc = "DRAM Channel 1 write CAS auto page close commands", .pme_ucode = 0x08, }, { .pme_uname = "CH2", .pme_udesc = "DRAM Channel 2 write CAS commands", .pme_ucode = 0x10, }, { .pme_uname = "AUTOPRE_CH2", .pme_udesc = "DRAM Channel 2 write CAS auto page close commands", .pme_ucode = 0x20, }, }, .pme_numasks = 6 }, { .pme_name = "UNC_GQ_ALLOC", .pme_desc = "GQ read tracker requests", .pme_code = 0x03, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "READ_TRACKER", .pme_udesc = "GQ read tracker requests", .pme_ucode = 0x01, }, { .pme_uname = "RT_LLC_MISS", .pme_udesc = "GQ read tracker LLC misses", .pme_ucode = 0x02, }, { .pme_uname = "RT_TO_LLC_RESP", .pme_udesc = "GQ read tracker LLC requests", .pme_ucode = 0x04, }, { .pme_uname = "RT_TO_RTID_ACQUIRED", .pme_udesc = "GQ read tracker LLC miss to RTID acquired", .pme_ucode = 0x08, }, { .pme_uname = "WT_TO_RTID_ACQUIRED", .pme_udesc = "GQ write tracker LLC miss to RTID acquired", .pme_ucode = 0x10, }, { .pme_uname = "WRITE_TRACKER", .pme_udesc = "GQ write tracker LLC misses", .pme_ucode = 0x20, }, { .pme_uname = "PEER_PROBE_TRACKER", .pme_udesc = "GQ peer probe tracker requests", .pme_ucode = 0x40, }, }, .pme_numasks = 7 }, { .pme_name = "UNC_GQ_CYCLES_FULL", .pme_desc = "Cycles GQ read tracker is full.", .pme_code = 0x00, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "READ_TRACKER", .pme_udesc = "Cycles GQ read tracker is full.", .pme_ucode = 0x01, }, { .pme_uname = "WRITE_TRACKER", .pme_udesc = "Cycles GQ write tracker is full.", .pme_ucode = 0x02, }, { .pme_uname = "PEER_PROBE_TRACKER", .pme_udesc = "Cycles GQ peer probe tracker is full.", .pme_ucode = 0x04, }, }, .pme_numasks = 3 }, { .pme_name = "UNC_GQ_CYCLES_NOT_EMPTY", .pme_desc = "Cycles GQ read tracker is busy", .pme_code = 0x01, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "READ_TRACKER", .pme_udesc = "Cycles GQ read tracker is busy", .pme_ucode = 0x01, }, { .pme_uname = "WRITE_TRACKER", .pme_udesc = "Cycles GQ write tracker is busy", .pme_ucode = 0x02, }, { .pme_uname = "PEER_PROBE_TRACKER", .pme_udesc = "Cycles GQ peer probe tracker is busy", .pme_ucode = 0x04, }, }, .pme_numasks = 3 }, { .pme_name = "UNC_GQ_DATA_FROM", .pme_desc = "Cycles GQ data is imported", .pme_code = 0x04, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "QPI", .pme_udesc = "Cycles GQ data is imported from Quickpath interface", .pme_ucode = 0x01, }, { .pme_uname = "QMC", .pme_udesc = "Cycles GQ data is imported from Quickpath memory interface", .pme_ucode = 0x02, }, { .pme_uname = "LLC", .pme_udesc = "Cycles GQ data is imported from LLC", .pme_ucode = 0x04, }, { .pme_uname = "CORES_02", .pme_udesc = "Cycles GQ data is imported from Cores 0 and 2", .pme_ucode = 0x08, }, { .pme_uname = "CORES_13", .pme_udesc = "Cycles GQ data is imported from Cores 1 and 3", .pme_ucode = 0x10, }, }, .pme_numasks = 5 }, { .pme_name = "UNC_GQ_DATA_TO", .pme_desc = "Cycles GQ data is exported", .pme_code = 0x05, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "QPI_QMC", .pme_udesc = "Cycles GQ data sent to the QPI or QMC", .pme_ucode = 0x01, }, { .pme_uname = "LLC", .pme_udesc = "Cycles GQ data sent to LLC", .pme_ucode = 0x02, }, { .pme_uname = "CORES", .pme_udesc = "Cycles GQ data sent to cores", .pme_ucode = 0x04, }, }, .pme_numasks = 3 }, { .pme_name = "UNC_LLC_HITS", .pme_desc = "Number of LLC read hits", .pme_code = 0x08, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "READ", .pme_udesc = "Number of LLC read hits", .pme_ucode = 0x01, }, { .pme_uname = "WRITE", .pme_udesc = "Number of LLC write hits", .pme_ucode = 0x02, }, { .pme_uname = "PROBE", .pme_udesc = "Number of LLC peer probe hits", .pme_ucode = 0x04, }, { .pme_uname = "ANY", .pme_udesc = "Number of LLC hits", .pme_ucode = 0x03, }, }, .pme_numasks = 4 }, { .pme_name = "UNC_LLC_LINES_IN", .pme_desc = "LLC lines allocated in M state", .pme_code = 0x0A, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "M_STATE", .pme_udesc = "LLC lines allocated in M state", .pme_ucode = 0x01, }, { .pme_uname = "E_STATE", .pme_udesc = "LLC lines allocated in E state", .pme_ucode = 0x02, }, { .pme_uname = "S_STATE", .pme_udesc = "LLC lines allocated in S state", .pme_ucode = 0x04, }, { .pme_uname = "F_STATE", .pme_udesc = "LLC lines allocated in F state", .pme_ucode = 0x08, }, { .pme_uname = "ANY", .pme_udesc = "LLC lines allocated", .pme_ucode = 0x0F, }, }, .pme_numasks = 5 }, { .pme_name = "UNC_LLC_LINES_OUT", .pme_desc = "LLC lines victimized in M state", .pme_code = 0x0B, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "M_STATE", .pme_udesc = "LLC lines victimized in M state", .pme_ucode = 0x01, }, { .pme_uname = "E_STATE", .pme_udesc = "LLC lines victimized in E state", .pme_ucode = 0x02, }, { .pme_uname = "S_STATE", .pme_udesc = "LLC lines victimized in S state", .pme_ucode = 0x04, }, { .pme_uname = "I_STATE", .pme_udesc = "LLC lines victimized in I state", .pme_ucode = 0x08, }, { .pme_uname = "F_STATE", .pme_udesc = "LLC lines victimized in F state", .pme_ucode = 0x10, }, { .pme_uname = "ANY", .pme_udesc = "LLC lines victimized", .pme_ucode = 0x1F, }, }, .pme_numasks = 6 }, { .pme_name = "UNC_LLC_MISS", .pme_desc = "Number of LLC read misses", .pme_code = 0x09, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "READ", .pme_udesc = "Number of LLC read misses", .pme_ucode = 0x01, }, { .pme_uname = "WRITE", .pme_udesc = "Number of LLC write misses", .pme_ucode = 0x02, }, { .pme_uname = "PROBE", .pme_udesc = "Number of LLC peer probe misses", .pme_ucode = 0x04, }, { .pme_uname = "ANY", .pme_udesc = "Number of LLC misses", .pme_ucode = 0x03, }, }, .pme_numasks = 4 }, { .pme_name = "UNC_QHL_ADDRESS_CONFLICTS", .pme_desc = "QHL 2 way address conflicts", .pme_code = 0x24, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "2WAY", .pme_udesc = "QHL 2 way address conflicts", .pme_ucode = 0x02, }, { .pme_uname = "3WAY", .pme_udesc = "QHL 3 way address conflicts", .pme_ucode = 0x04, }, }, .pme_numasks = 2 }, { .pme_name = "UNC_QHL_CONFLICT_CYCLES", .pme_desc = "QHL IOH Tracker conflict cycles", .pme_code = 0x25, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "IOH", .pme_udesc = "QHL IOH Tracker conflict cycles", .pme_ucode = 0x01, }, { .pme_uname = "REMOTE", .pme_udesc = "QHL Remote Tracker conflict cycles", .pme_ucode = 0x02, }, { .pme_uname = "LOCAL", .pme_udesc = "QHL Local Tracker conflict cycles", .pme_ucode = 0x04, }, }, .pme_numasks = 3 }, { .pme_name = "UNC_QHL_CYCLES_FULL", .pme_desc = "Cycles QHL Remote Tracker is full", .pme_code = 0x21, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "REMOTE", .pme_udesc = "Cycles QHL Remote Tracker is full", .pme_ucode = 0x02, }, { .pme_uname = "LOCAL", .pme_udesc = "Cycles QHL Local Tracker is full", .pme_ucode = 0x04, }, { .pme_uname = "IOH", .pme_udesc = "Cycles QHL IOH Tracker is full", .pme_ucode = 0x01, }, }, .pme_numasks = 3 }, { .pme_name = "UNC_QHL_CYCLES_NOT_EMPTY", .pme_desc = "Cycles QHL Tracker is not empty", .pme_code = 0x22, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "IOH", .pme_udesc = "Cycles QHL IOH is busy", .pme_ucode = 0x01, }, { .pme_uname = "REMOTE", .pme_udesc = "Cycles QHL Remote Tracker is busy", .pme_ucode = 0x02, }, { .pme_uname = "LOCAL", .pme_udesc = "Cycles QHL Local Tracker is busy", .pme_ucode = 0x04, }, }, .pme_numasks = 3 }, { .pme_name = "UNC_QHL_FRC_ACK_CNFLTS", .pme_desc = "QHL FrcAckCnflts sent to local home", .pme_code = 0x33, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "LOCAL", .pme_udesc = "QHL FrcAckCnflts sent to local home", .pme_ucode = 0x04, }, }, .pme_numasks = 1 }, { .pme_name = "UNC_QHL_SLEEPS", .pme_desc = "number of occurrences a request was put to sleep", .pme_code = 0x34, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "IOH_ORDER", .pme_udesc = "due to IOH ordering (write after read) conflicts", .pme_ucode = 0x01, }, { .pme_uname = "REMOTE_ORDER", .pme_udesc = "due to remote socket ordering (write after read) conflicts", .pme_ucode = 0x02, }, { .pme_uname = "LOCAL_ORDER", .pme_udesc = "due to local socket ordering (write after read) conflicts", .pme_ucode = 0x04, }, { .pme_uname = "IOH_CONFLICT", .pme_udesc = "due to IOH address conflicts", .pme_ucode = 0x08, }, { .pme_uname = "REMOTE_CONFLICT", .pme_udesc = "due to remote socket address conflicts", .pme_ucode = 0x10, }, { .pme_uname = "LOCAL_CONFLICT", .pme_udesc = "due to local socket address conflicts", .pme_ucode = 0x20, }, }, .pme_numasks = 6 }, { .pme_name = "UNC_QHL_OCCUPANCY", .pme_desc = "Cycles QHL Tracker Allocate to Deallocate Read Occupancy", .pme_code = 0x23, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "IOH", .pme_udesc = "Cycles QHL IOH Tracker Allocate to Deallocate Read Occupancy", .pme_ucode = 0x01, }, { .pme_uname = "REMOTE", .pme_udesc = "Cycles QHL Remote Tracker Allocate to Deallocate Read Occupancy", .pme_ucode = 0x02, }, { .pme_uname = "LOCAL", .pme_udesc = "Cycles QHL Local Tracker Allocate to Deallocate Read Occupancy", .pme_ucode = 0x04, }, }, .pme_numasks = 3 }, { .pme_name = "UNC_QHL_REQUESTS", .pme_desc = "Quickpath Home Logic local read requests", .pme_code = 0x20, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "LOCAL_READS", .pme_udesc = "Quickpath Home Logic local read requests", .pme_ucode = 0x10, }, { .pme_uname = "LOCAL_WRITES", .pme_udesc = "Quickpath Home Logic local write requests", .pme_ucode = 0x20, }, { .pme_uname = "REMOTE_READS", .pme_udesc = "Quickpath Home Logic remote read requests", .pme_ucode = 0x04, }, { .pme_uname = "IOH_READS", .pme_udesc = "Quickpath Home Logic IOH read requests", .pme_ucode = 0x01, }, { .pme_uname = "IOH_WRITES", .pme_udesc = "Quickpath Home Logic IOH write requests", .pme_ucode = 0x02, }, { .pme_uname = "REMOTE_WRITES", .pme_udesc = "Quickpath Home Logic remote write requests", .pme_ucode = 0x08, }, }, .pme_numasks = 6 }, { .pme_name = "UNC_QHL_TO_QMC_BYPASS", .pme_desc = "Number of requests to QMC that bypass QHL", .pme_code = 0x0126, .pme_flags = PFMLIB_NHM_UNC, }, { .pme_name = "UNC_QMC_BUSY", .pme_desc = "Cycles QMC busy with a read request", .pme_code = 0x29, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "READ_CH0", .pme_udesc = "Cycles QMC channel 0 busy with a read request", .pme_ucode = 0x01, }, { .pme_uname = "READ_CH1", .pme_udesc = "Cycles QMC channel 1 busy with a read request", .pme_ucode = 0x02, }, { .pme_uname = "READ_CH2", .pme_udesc = "Cycles QMC channel 2 busy with a read request", .pme_ucode = 0x04, }, { .pme_uname = "WRITE_CH0", .pme_udesc = "Cycles QMC channel 0 busy with a write request", .pme_ucode = 0x08, }, { .pme_uname = "WRITE_CH1", .pme_udesc = "Cycles QMC channel 1 busy with a write request", .pme_ucode = 0x10, }, { .pme_uname = "WRITE_CH2", .pme_udesc = "Cycles QMC channel 2 busy with a write request", .pme_ucode = 0x20, }, }, .pme_numasks = 6 }, { .pme_name = "UNC_QMC_CANCEL", .pme_desc = "QMC cancels", .pme_code = 0x30, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CH0", .pme_udesc = "QMC channel 0 cancels", .pme_ucode = 0x01, }, { .pme_uname = "CH1", .pme_udesc = "QMC channel 1 cancels", .pme_ucode = 0x02, }, { .pme_uname = "CH2", .pme_udesc = "QMC channel 2 cancels", .pme_ucode = 0x04, }, { .pme_uname = "ANY", .pme_udesc = "QMC cancels", .pme_ucode = 0x07, }, }, .pme_numasks = 4 }, { .pme_name = "UNC_QMC_CRITICAL_PRIORITY_READS", .pme_desc = "QMC critical priority read requests", .pme_code = 0x2E, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CH0", .pme_udesc = "QMC channel 0 critical priority read requests", .pme_ucode = 0x01, }, { .pme_uname = "CH1", .pme_udesc = "QMC channel 1 critical priority read requests", .pme_ucode = 0x02, }, { .pme_uname = "CH2", .pme_udesc = "QMC channel 2 critical priority read requests", .pme_ucode = 0x04, }, { .pme_uname = "ANY", .pme_udesc = "QMC critical priority read requests", .pme_ucode = 0x07, }, }, .pme_numasks = 4 }, { .pme_name = "UNC_QMC_HIGH_PRIORITY_READS", .pme_desc = "QMC high priority read requests", .pme_code = 0x2D, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CH0", .pme_udesc = "QMC channel 0 high priority read requests", .pme_ucode = 0x01, }, { .pme_uname = "CH1", .pme_udesc = "QMC channel 1 high priority read requests", .pme_ucode = 0x02, }, { .pme_uname = "CH2", .pme_udesc = "QMC channel 2 high priority read requests", .pme_ucode = 0x04, }, { .pme_uname = "ANY", .pme_udesc = "QMC high priority read requests", .pme_ucode = 0x07, }, }, .pme_numasks = 4 }, { .pme_name = "UNC_QMC_ISOC_FULL", .pme_desc = "Cycles DRAM full with isochronous (ISOC) read requests", .pme_code = 0x28, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "READ_CH0", .pme_udesc = "Cycles DRAM channel 0 full with isochronous read requests", .pme_ucode = 0x01, }, { .pme_uname = "READ_CH1", .pme_udesc = "Cycles DRAM channel 1 full with isochronous read requests", .pme_ucode = 0x02, }, { .pme_uname = "READ_CH2", .pme_udesc = "Cycles DRAM channel 2 full with isochronous read requests", .pme_ucode = 0x04, }, { .pme_uname = "WRITE_CH0", .pme_udesc = "Cycles DRAM channel 0 full with isochronous write requests", .pme_ucode = 0x08, }, { .pme_uname = "WRITE_CH1", .pme_udesc = "Cycles DRAM channel 1 full with isochronous write requests", .pme_ucode = 0x10, }, { .pme_uname = "WRITE_CH2", .pme_udesc = "Cycles DRAM channel 2 full with isochronous write requests", .pme_ucode = 0x20, }, }, .pme_numasks = 6 }, { .pme_name = "UNC_IMC_ISOC_OCCUPANCY", .pme_desc = "IMC isochronous (ISOC) Read Occupancy", .pme_code = 0x2B, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CH0", .pme_udesc = "IMC channel 0 isochronous read request occupancy", .pme_ucode = 0x01, }, { .pme_uname = "CH1", .pme_udesc = "IMC channel 1 isochronous read request occupancy", .pme_ucode = 0x02, }, { .pme_uname = "CH2", .pme_udesc = "IMC channel 2 isochronous read request occupancy", .pme_ucode = 0x04, }, { .pme_uname = "ANY", .pme_udesc = "IMC isochronous read request occupancy", .pme_ucode = 0x07, }, }, .pme_numasks = 4 }, { .pme_name = "UNC_QMC_NORMAL_READS", .pme_desc = "QMC normal read requests", .pme_code = 0x2C, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CH0", .pme_udesc = "QMC channel 0 normal read requests", .pme_ucode = 0x01, }, { .pme_uname = "CH1", .pme_udesc = "QMC channel 1 normal read requests", .pme_ucode = 0x02, }, { .pme_uname = "CH2", .pme_udesc = "QMC channel 2 normal read requests", .pme_ucode = 0x04, }, { .pme_uname = "ANY", .pme_udesc = "QMC normal read requests", .pme_ucode = 0x07, }, }, .pme_numasks = 4 }, { .pme_name = "UNC_QMC_OCCUPANCY", .pme_desc = "QMC Occupancy", .pme_code = 0x2A, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CH0", .pme_udesc = "IMC channel 0 normal read request occupancy", .pme_ucode = 0x01, }, { .pme_uname = "CH1", .pme_udesc = "IMC channel 1 normal read request occupancy", .pme_ucode = 0x02, }, { .pme_uname = "CH2", .pme_udesc = "IMC channel 2 normal read request occupancy", .pme_ucode = 0x04, }, }, .pme_numasks = 3 }, { .pme_name = "UNC_QMC_PRIORITY_UPDATES", .pme_desc = "QMC priority updates", .pme_code = 0x31, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CH0", .pme_udesc = "QMC channel 0 priority updates", .pme_ucode = 0x01, }, { .pme_uname = "CH1", .pme_udesc = "QMC channel 1 priority updates", .pme_ucode = 0x02, }, { .pme_uname = "CH2", .pme_udesc = "QMC channel 2 priority updates", .pme_ucode = 0x04, }, { .pme_uname = "ANY", .pme_udesc = "QMC priority updates", .pme_ucode = 0x07, }, }, .pme_numasks = 4 }, { .pme_name = "UNC_IMC_RETRY", .pme_desc = "Number of IMC DRAM channel retries (retries occur in RAS mode only)", .pme_code = 0x32, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CH0", .pme_udesc = "channel 0", .pme_ucode = 0x01, }, { .pme_uname = "CH1", .pme_udesc = "channel 1", .pme_ucode = 0x02, }, { .pme_uname = "CH2", .pme_udesc = "channel 2", .pme_ucode = 0x04, }, { .pme_uname = "ANY", .pme_udesc = "any channel", .pme_ucode = 0x07, }, }, .pme_numasks = 4 }, { .pme_name = "UNC_QMC_WRITES", .pme_desc = "QMC cache line writes", .pme_code = 0x2F, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "FULL_CH0", .pme_udesc = "QMC channel 0 full cache line writes", .pme_ucode = 0x01, }, { .pme_uname = "FULL_CH1", .pme_udesc = "QMC channel 1 full cache line writes", .pme_ucode = 0x02, }, { .pme_uname = "FULL_CH2", .pme_udesc = "QMC channel 2 full cache line writes", .pme_ucode = 0x04, }, { .pme_uname = "FULL_ANY", .pme_udesc = "QMC full cache line writes", .pme_ucode = 0x07, }, { .pme_uname = "PARTIAL_CH0", .pme_udesc = "QMC channel 0 partial cache line writes", .pme_ucode = 0x08, }, { .pme_uname = "PARTIAL_CH1", .pme_udesc = "QMC channel 1 partial cache line writes", .pme_ucode = 0x10, }, { .pme_uname = "PARTIAL_CH2", .pme_udesc = "QMC channel 2 partial cache line writes", .pme_ucode = 0x20, }, { .pme_uname = "PARTIAL_ANY", .pme_udesc = "QMC partial cache line writes", .pme_ucode = 0x38, }, }, .pme_numasks = 8 }, { .pme_name = "UNC_QPI_RX_NO_PPT_CREDIT", .pme_desc = "Link 0 snoop stalls due to no PPT entry", .pme_code = 0x43, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "STALLS_LINK_0", .pme_udesc = "Link 0 snoop stalls due to no PPT entry", .pme_ucode = 0x01, }, { .pme_uname = "STALLS_LINK_1", .pme_udesc = "Link 1 snoop stalls due to no PPT entry", .pme_ucode = 0x02, }, }, .pme_numasks = 2 }, { .pme_name = "UNC_QPI_TX_HEADER", .pme_desc = "Cycles link 0 outbound header busy", .pme_code = 0x42, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "BUSY_LINK_0", .pme_udesc = "Cycles link 0 outbound header busy", .pme_ucode = 0x02, }, { .pme_uname = "BUSY_LINK_1", .pme_udesc = "Cycles link 1 outbound header busy", .pme_ucode = 0x08, }, }, .pme_numasks = 2 }, { .pme_name = "UNC_QPI_TX_STALLED_MULTI_FLIT", .pme_desc = "Cycles QPI outbound stalls", .pme_code = 0x41, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "DRS_LINK_0", .pme_udesc = "Cycles QPI outbound link 0 DRS stalled", .pme_ucode = 0x01, }, { .pme_uname = "NCB_LINK_0", .pme_udesc = "Cycles QPI outbound link 0 NCB stalled", .pme_ucode = 0x02, }, { .pme_uname = "NCS_LINK_0", .pme_udesc = "Cycles QPI outbound link 0 NCS stalled", .pme_ucode = 0x04, }, { .pme_uname = "DRS_LINK_1", .pme_udesc = "Cycles QPI outbound link 1 DRS stalled", .pme_ucode = 0x08, }, { .pme_uname = "NCB_LINK_1", .pme_udesc = "Cycles QPI outbound link 1 NCB stalled", .pme_ucode = 0x10, }, { .pme_uname = "NCS_LINK_1", .pme_udesc = "Cycles QPI outbound link 1 NCS stalled", .pme_ucode = 0x20, }, { .pme_uname = "LINK_0", .pme_udesc = "Cycles QPI outbound link 0 multi flit stalled", .pme_ucode = 0x07, }, { .pme_uname = "LINK_1", .pme_udesc = "Cycles QPI outbound link 1 multi flit stalled", .pme_ucode = 0x38, }, }, .pme_numasks = 8 }, { .pme_name = "UNC_QPI_TX_STALLED_SINGLE_FLIT", .pme_desc = "Cycles QPI outbound link stalls", .pme_code = 0x40, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "HOME_LINK_0", .pme_udesc = "Cycles QPI outbound link 0 HOME stalled", .pme_ucode = 0x01, }, { .pme_uname = "SNOOP_LINK_0", .pme_udesc = "Cycles QPI outbound link 0 SNOOP stalled", .pme_ucode = 0x02, }, { .pme_uname = "NDR_LINK_0", .pme_udesc = "Cycles QPI outbound link 0 NDR stalled", .pme_ucode = 0x04, }, { .pme_uname = "HOME_LINK_1", .pme_udesc = "Cycles QPI outbound link 1 HOME stalled", .pme_ucode = 0x08, }, { .pme_uname = "SNOOP_LINK_1", .pme_udesc = "Cycles QPI outbound link 1 SNOOP stalled", .pme_ucode = 0x10, }, { .pme_uname = "NDR_LINK_1", .pme_udesc = "Cycles QPI outbound link 1 NDR stalled", .pme_ucode = 0x20, }, { .pme_uname = "LINK_0", .pme_udesc = "Cycles QPI outbound link 0 single flit stalled", .pme_ucode = 0x07, }, { .pme_uname = "LINK_1", .pme_udesc = "Cycles QPI outbound link 1 single flit stalled", .pme_ucode = 0x38, }, }, .pme_numasks = 8 }, { .pme_name = "UNC_SNP_RESP_TO_LOCAL_HOME", .pme_desc = "Local home snoop response", .pme_code = 0x06, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "I_STATE", .pme_udesc = "Local home snoop response - LLC does not have cache line", .pme_ucode = 0x01, }, { .pme_uname = "S_STATE", .pme_udesc = "Local home snoop response - LLC has cache line in S state", .pme_ucode = 0x02, }, { .pme_uname = "FWD_S_STATE", .pme_udesc = "Local home snoop response - LLC forwarding cache line in S state.", .pme_ucode = 0x04, }, { .pme_uname = "FWD_I_STATE", .pme_udesc = "Local home snoop response - LLC has forwarded a modified cache line", .pme_ucode = 0x08, }, { .pme_uname = "CONFLICT", .pme_udesc = "Local home conflict snoop response", .pme_ucode = 0x10, }, { .pme_uname = "WB", .pme_udesc = "Local home snoop response - LLC has cache line in the M state", .pme_ucode = 0x20, }, }, .pme_numasks = 6 }, { .pme_name = "UNC_SNP_RESP_TO_REMOTE_HOME", .pme_desc = "Remote home snoop response", .pme_code = 0x07, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "I_STATE", .pme_udesc = "Remote home snoop response - LLC does not have cache line", .pme_ucode = 0x01, }, { .pme_uname = "S_STATE", .pme_udesc = "Remote home snoop response - LLC has cache line in S state", .pme_ucode = 0x02, }, { .pme_uname = "FWD_S_STATE", .pme_udesc = "Remote home snoop response - LLC forwarding cache line in S state.", .pme_ucode = 0x04, }, { .pme_uname = "FWD_I_STATE", .pme_udesc = "Remote home snoop response - LLC has forwarded a modified cache line", .pme_ucode = 0x08, }, { .pme_uname = "CONFLICT", .pme_udesc = "Remote home conflict snoop response", .pme_ucode = 0x10, }, { .pme_uname = "WB", .pme_udesc = "Remote home snoop response - LLC has cache line in the M state", .pme_ucode = 0x20, }, { .pme_uname = "HITM", .pme_udesc = "Remote home snoop response - LLC HITM", .pme_ucode = 0x24, }, }, .pme_numasks = 7 }, { .pme_name = "UNC_THERMAL_THROTTLING_TEMP", .pme_desc = "uncore cycles that the PCU records core temperature above threshold", .pme_code = 0x80, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CORE_0", .pme_udesc = "Core 0", .pme_ucode = 0x01, }, { .pme_uname = "CORE_1", .pme_udesc = "Core 1", .pme_ucode = 0x02, }, { .pme_uname = "CORE_2", .pme_udesc = "Core 2", .pme_ucode = 0x04, }, { .pme_uname = "CORE_3", .pme_udesc = "Core 3", .pme_ucode = 0x08, }, }, .pme_numasks = 4 }, { .pme_name = "UNC_THERMAL_THROTTLED_TEMP", .pme_desc = "uncore cycles that the PCU records that core is in power throttled state due to temperature being above threshold", .pme_code = 0x81, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CORE_0", .pme_udesc = "Core 0", .pme_ucode = 0x01, }, { .pme_uname = "CORE_1", .pme_udesc = "Core 1", .pme_ucode = 0x02, }, { .pme_uname = "CORE_2", .pme_udesc = "Core 2", .pme_ucode = 0x04, }, { .pme_uname = "CORE_3", .pme_udesc = "Core 3", .pme_ucode = 0x08, }, }, .pme_numasks = 4 }, { .pme_name = "UNC_PROCHOT_ASSERTION", .pme_desc = "Number of system ssertions of PROCHOT indicating the entire processor has exceeded the thermal limit", .pme_code = 0x0182, }, { .pme_name = "UNC_THERMAL_THROTTLING_PROCHOT", .pme_desc = "uncore cycles that the PCU records that core is in power throttled state due PROCHOT assertions", .pme_code = 0x83, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CORE_0", .pme_udesc = "Core 0", .pme_ucode = 0x01, }, { .pme_uname = "CORE_1", .pme_udesc = "Core 1", .pme_ucode = 0x02, }, { .pme_uname = "CORE_2", .pme_udesc = "Core 2", .pme_ucode = 0x04, }, { .pme_uname = "CORE_3", .pme_udesc = "Core 3", .pme_ucode = 0x08, }, }, .pme_numasks = 4 }, { .pme_name = "UNC_TURBO_MODE", .pme_desc = "uncore cycles that a core is operating in turbo mode", .pme_code = 0x84, .pme_flags = PFMLIB_NHM_UNC, .pme_umasks = { { .pme_uname = "CORE_0", .pme_udesc = "Core 0", .pme_ucode = 0x01, }, { .pme_uname = "CORE_1", .pme_udesc = "Core 1", .pme_ucode = 0x02, }, { .pme_uname = "CORE_2", .pme_udesc = "Core 2", .pme_ucode = 0x04, }, { .pme_uname = "CORE_3", .pme_udesc = "Core 3", .pme_ucode = 0x08, }, }, .pme_numasks = 4 }, { .pme_name = "UNC_CYCLES_UNHALTED_L3_FLL_ENABLE", .pme_desc = "uncore cycles where at least one core is unhalted and all L3 ways are enabled", .pme_code = 0x0285, }, { .pme_name = "UNC_CYCLES_UNHALTED_L3_FLL_DISABLE", .pme_desc = "uncore cycles where at least one core is unhalted and all L3 ways are disabled", .pme_code = 0x0186, }, }; #define PME_INTEL_WSM_UNC_CYCLE 0 #define PME_WSM_UNC_EVENT_COUNT (sizeof(intel_wsm_unc_pe)/sizeof(pme_nhm_entry_t)) papi-5.5.1/src/libpfm-3.y/config.mk0000644000307100002310000001133313013651447016727 0ustar yarkhangraduate# # Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. # Contributed by Stephane Eranian # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies # of the Software, and to permit persons to whom the Software is furnished to do so, # subject to the following conditions: # # The above copyright notice and this permission notice shall be included in all # copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, # INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A # PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT # HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE # OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # # This file is part of libpfm, a performance monitoring support library for # applications on Linux. # # # This file defines the global compilation settings. # It is included by every Makefile # # SYS := $(shell uname -s) ARCH := $(shell uname -m) ifeq (i686,$(findstring i686,$(ARCH))) override ARCH=ia32 endif ifeq (i586,$(findstring i586,$(ARCH))) override ARCH=ia32 endif ifeq (i486,$(findstring i486,$(ARCH))) override ARCH=ia32 endif ifeq (i386,$(findstring i386,$(ARCH))) override ARCH=ia32 endif ifeq (ppc,$(findstring ppc,$(ARCH))) override ARCH=powerpc endif ifeq (sparc64,$(findstring sparc64,$(ARCH))) override ARCH=sparc endif # # CONFIG_PFMLIB_SHARED: y=compile static and shared versions, n=static only # CONFIG_PFMLIB_OLD_PFMV2: enable old ( 2.x, x <=4) perfmon2 (mutually exclusive with v3 support) CONFIG_PFMLIB_SHARED?=y CONFIG_PFMLIB_OLD_PFMV2?=n # # Cray-X2 is cross-compiled. Check the programming environment # PE := $(shell echo $${CRAY_PE_TARGET}) ifeq (cray-x2,$(PE)) override ARCH=crayx2 endif # # Cell Broadband Engine is reported as PPC but needs special handling. # ifeq ($(SYS),Linux) MACHINE := $(shell grep -q 'Cell Broadband Engine' /proc/cpuinfo && echo cell) ifeq (cell,$(MACHINE)) override ARCH=cell endif endif # # Library version # VERSION=3 REVISION=10 AGE=0 # # Where should things (lib, headers, man) go in the end. # install_prefix?=/usr/local PREFIX?=$(install_prefix) LIBDIR=$(PREFIX)/lib INCDIR=$(PREFIX)/include MANDIR=$(PREFIX)/share/man EXAMPLESDIR=$(PREFIX)/share/doc/libpfm-$(VERSION).$(REVISION).$(AGE)/examples # # Configuration Paramaters for libpfm library # ifeq ($(ARCH),ia64) CONFIG_PFMLIB_ARCH_IA64=y endif ifeq ($(ARCH),x86_64) CONFIG_PFMLIB_ARCH_X86_64=y endif ifeq ($(ARCH),ia32) CONFIG_PFMLIB_ARCH_I386=y endif ifeq ($(ARCH),mips64) CONFIG_PFMLIB_ARCH_MIPS64=y # # SiCortex/Linux # MACHINE := $(shell test -f /etc/sicortex-release && echo sicortex) ifeq (sicortex,$(MACHINE)) CONFIG_PFMLIB_ARCH_SICORTEX=y endif endif ifeq ($(ARCH),powerpc) CONFIG_PFMLIB_ARCH_POWERPC=y endif ifeq ($(ARCH),sparc) CONFIG_PFMLIB_ARCH_SPARC=y endif ifeq ($(XTPE_COMPILE_TARGET),linux) CONFIG_PFMLIB_ARCH_CRAYXT=y CONFIG_PFMLIB_SHARED=n CONFIG_PFMLIB_OLD_PFMV2=y endif ifeq ($(XTPE_COMPILE_TARGET),catamount) CONFIG_PFMLIB_ARCH_CRAYXT=y CONFIG_PFMLIB_SHARED=n CONFIG_PFMLIB_OLD_PFMV2=y endif ifeq ($(ARCH),crayx2) CONFIG_PFMLIB_ARCH_CRAYX2=y CONFIG_PFMLIB_SHARED=n CONFIG_PFMLIB_OLD_PFMV2=y endif ifeq ($(ARCH),cell) CONFIG_PFMLIB_CELL=y endif # handle special cases for 64-bit builds ifeq ($(BITMODE),64) ifeq ($(ARCH),powerpc) CONFIG_PFMLIB_ARCH_POWERPC64=y endif endif # # you shouldn't have to touch anything beyond this point # # # The entire package can be compiled using # icc the Intel Itanium Compiler (7.x,8.x, 9.x) # or GNU C #CC=icc CC?=gcc LIBS= INSTALL=install LN?=ln -sf PFMINCDIR=$(TOPDIR)/include PFMLIBDIR=$(TOPDIR)/lib DBG?=-g -Wall -Werror # gcc/mips64 bug ifeq ($(CONFIG_PFMLIB_ARCH_SICORTEX),y) OPTIM?=-O else OPTIM?=-O2 endif CFLAGS+=$(OPTIM) $(DBG) -I$(PFMINCDIR) MKDEP=makedepend PFMLIB=$(PFMLIBDIR)/libpfm.a # Reset options for Cray XT ifeq ($(CONFIG_PFMLIB_ARCH_CRAYXT),y) LDFLAGS+=-static CONFIG_PFMLIB_OLD_PFMV2=y endif # Reset the compiler for Cray-X2 (load x2-gcc module) ifeq ($(CONFIG_PFMLIB_ARCH_CRAYX2),y) CC=craynv-cray-linux-gnu-gcc LDFLAGS+=-static CONFIG_PFMLIB_OLD_PFMV2=y endif ifeq ($(CONFIG_PFMLIB_ARCH_SICORTEX),y) CONFIG_PFMLIB_OLD_PFMV2=y endif ifeq ($(CONFIG_PFMLIB_ARCH_POWERPC64),y) CFLAGS+= -m64 LDFLAGS+= -m64 LIBDIR=$(PREFIX)/lib64 endif ifeq ($(CONFIG_PFMLIB_OLD_PFMV2),y) CFLAGS +=-DPFMLIB_OLD_PFMV2 endif papi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/0000755000307100002310000000000013013651447020336 5ustar yarkhangraduatepapi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/task_attach.c0000644000307100002310000002030213013651447022765 0ustar yarkhangraduate/* * task_attach.c - example of how to attach to another task for monitoring * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } int parent(pid_t pid) { pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfarg_context_t ctx[1]; pfarg_reg_t pc[NUM_PMCS]; pfarg_reg_t pd[NUM_PMDS]; pfarg_load_t load_args; pfm_msg_t msg; unsigned int i, num_counters; int status, ret; int ctx_fd; char name[MAX_EVT_NAME_LEN]; memset(pc, 0, sizeof(ctx)); memset(pd, 0, sizeof(ctx)); memset(ctx, 0, sizeof(ctx)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&load_args,0, sizeof(load_args)); pfm_get_num_counters(&num_counters); if (pfm_get_cycle_event(&inp.pfp_events[0]) != PFMLIB_SUCCESS) fatal_error("cannot find cycle event\n"); if (pfm_get_inst_retired_event(&inp.pfp_events[1]) != PFMLIB_SUCCESS) fatal_error("cannot find inst retired event\n"); i = 2; /* * set the privilege mode: * PFM_PLM3 : user level * PFM_PLM0 : kernel level */ inp.pfp_dfl_plm = PFM_PLM3; if (num_counters < i) { i = num_counters; printf("too many events provided (max=%d events), using first %d event(s)\n", num_counters, i); } /* * how many counters we use */ inp.pfp_event_count = i; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); } /* * now create a context. we will later attach it to the task we are creating. */ if (perfmonctl(0, PFM_CREATE_CONTEXT, ctx, 1) == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * extract the identifier for our context */ ctx_fd = ctx[0].ctx_fd; /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events causes extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * the PMC controlling the event ALWAYS come first, that's why this loop * is safe even when extra PMC are needed to support a particular event. */ for (i=0; i < inp.pfp_event_count; i++) { pd[i].reg_num = pc[i].reg_num; } /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more thann counting monitors. */ if (perfmonctl(ctx_fd, PFM_WRITE_PMCS, pc, outp.pfp_pmc_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMCS errno %d\n",errno); } if (perfmonctl(ctx_fd, PFM_WRITE_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMDS errno %d\n",errno); } ret = ptrace(PTRACE_ATTACH, pid, NULL, 0); if (ret == -1) { fatal_error("cannot attach to %d: %s\n", pid, strerror(errno)); } /* * wait for the child to be actually stopped */ waitpid(pid, &status, WUNTRACED); /* * check if process exited early */ if (WIFEXITED(status)) { fatal_error("command process %d exited too early with status %d\n", pid, WEXITSTATUS(status)); } /* * the task is stopped at this point */ /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = pid; if (perfmonctl(ctx_fd, PFM_LOAD_CONTEXT, &load_args, 1) == -1) { fatal_error("perfmonctl error PFM_LOAD_CONTEXT errno %d\n",errno); } /* * activate monitoring. The task is still STOPPED at this point. Monitoring * will not take effect until the execution of the task is resumed. */ if (perfmonctl(ctx_fd, PFM_START, NULL, 0) == -1) { fatal_error("perfmonctl error PFM_START errno %d\n",errno); } /* * now resume execution of the task, effectively activating * monitoring. */ ptrace(PTRACE_DETACH, pid, NULL, 0); /* * now the task is running */ /* * We cannot simply do a waitpid() because we may be attaching to a process * totally unrelated to our program. Instead we use a perfmon facility that * notifies us when the monitoring task is exiting. * * When a task with a monitoring context attached to it exits, a PFM_MSG_END * is generated. It can be retrieve with a simple read() on the context's descriptor. * * Another reason why you might return from the read is if there was a counter * overflow, unlikely in this example. * * To measure only for short period of time, use select or poll with a timeout, * see task_attach_timeout.c * */ ret = read(ctx_fd, &msg, sizeof(msg)); if (ret == -1) { fatal_error("cannot read from descriptor: %s\n", strerror(errno)); } if (msg.type != PFM_MSG_END) { fatal_error("unexpected msg type : %d\n", msg.type); } /* * the task has exited, we can simply read the results */ /* * now simply read the results. */ if (perfmonctl(ctx_fd, PFM_READ_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error("perfmonctl error READ_PMDS errno %d\n",errno); return -1; } /* * print the results * * It is important to realize, that the first event we specified may not * be in PMD4. Not all events can be measured by any monitor. That's why * we need to use the pc[] array to figure out where event i was allocated. * */ for (i=0; i < inp.pfp_event_count; i++) { pfm_get_full_event_name(&inp.pfp_events[i], name, MAX_EVT_NAME_LEN); printf("PMD%u %20"PRIu64" %s\n", pd[i].reg_num, pd[i].reg_value, name); } /* * free the context */ close(ctx_fd); return 0; } int main(int argc, char **argv) { pfmlib_options_t pfmlib_options; pid_t pid; if (argc < 2) { fatal_error("usage: %s pid\n", argv[0]); } pid = atoi(argv[1]); /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) { printf("Can't initialize library\n"); exit(1); } /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); return parent(pid); } papi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/syst.c0000644000307100002310000002114613013651447021510 0ustar yarkhangraduate/* * syst.c - example of a simple system wide monitoring program * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #include #include #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } #ifndef __NR_sched_setaffinity #ifdef __ia64__ #define __NR_sched_setaffinity 1231 #endif #endif /* * Hack to get this to work without libc support */ int my_setaffinity(pid_t pid, unsigned int len, unsigned long *mask) { return syscall(__NR_sched_setaffinity, pid, len, mask); } int main(int argc, char **argv) { char **p; unsigned long my_mask; pfarg_reg_t pc[NUM_PMCS]; pfarg_reg_t pd[NUM_PMDS]; pfarg_context_t ctx[1]; pfarg_load_t load_args; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_options_t pfmlib_options; unsigned int which_cpu; int ret, ctx_fd; unsigned int i; unsigned int num_counters; char name[MAX_EVT_NAME_LEN]; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) { printf("Can't initialize library\n"); exit(1); } pfm_get_num_counters(&num_counters); /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); memset(pc, 0, sizeof(pc)); memset(pd, 0, sizeof(pd)); memset(ctx, 0, sizeof(ctx)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); /* * be nice to user! */ if (argc > 1) { p = argv+1; for (i=0; *p ; i++, p++) { if (pfm_find_event(*p, &inp.pfp_events[i].event) != PFMLIB_SUCCESS) { fatal_error("Cannot find %s event\n", *p); } } } else { if (pfm_get_cycle_event(&inp.pfp_events[0]) != PFMLIB_SUCCESS) { fatal_error("cannot find cycle event\n"); } if (pfm_get_inst_retired_event(&inp.pfp_events[1]) != PFMLIB_SUCCESS) { fatal_error("cannot find inst retired event\n"); } i = 2; } /* * set the privilege mode: * PFM_PLM3 : user level * PFM_PLM0 : kernel level */ inp.pfp_dfl_plm = PFM_PLM3|PFM_PLM0; if (i > num_counters) { i = num_counters; printf("too many events provided (max=%d events), using first %d event(s)\n", num_counters, i); } /* * how many counters we use */ inp.pfp_event_count = i; /* * indicate we are using the monitors for a system-wide session. * This may impact the way the library sets up the PMC values. */ inp.pfp_flags = PFMLIB_PFP_SYSTEMWIDE; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); } /* * In system wide mode, the perfmon context cannot be inherited. * Also in this mode, we cannot use the blocking form of user level notification. */ ctx[0].ctx_flags = PFM_FL_SYSTEM_WIDE; /* * pick a random CPU. Assumes CPU are numbered with no holes */ srandom(getpid()); which_cpu = random() % sysconf(_SC_NPROCESSORS_ONLN); /* * perfmon relies on the application to have the task pinned * on one CPU by the time the PFM_CONTEXT_LOAD command is issued. * The perfmon context will record the active CPU at the time of PFM_CONTEXT_LOAD * and will reject any access coming from another CPU. Therefore it * is advisable to pin the task ASAP before doing any perfmon calls. * * On RHAS and 2.5/2.6, this can be easily achieved using the * sched_setaffinity() system call. */ my_mask = 1UL << which_cpu; ret = my_setaffinity(getpid(), sizeof(unsigned long), &my_mask); if (ret == -1) { fatal_error("cannot set affinity to 0x%lx: %s\n", my_mask, strerror(errno)); } /* * after the call the task is pinned to which_cpu */ /* * now create the context for self monitoring/per-task */ if (perfmonctl(0, PFM_CREATE_CONTEXT, ctx, 1) == -1 ) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * extact our file descriptor */ ctx_fd = ctx->ctx_fd; /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events causes extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * the PMC controlling the event ALWAYS come first, that's why this loop * is safe even when extra PMC are needed to support a particular event. */ for (i=0; i < inp.pfp_event_count; i++) { pd[i].reg_num = outp.pfp_pmcs[i].reg_num; } /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more thann coutning monitors. */ if (perfmonctl(ctx_fd, PFM_WRITE_PMCS, pc, outp.pfp_pmc_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMCS errno %d\n",errno); } if (perfmonctl(ctx_fd, PFM_WRITE_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMDS errno %d\n",errno); } /* * for system wide session, we can only attached to ourself */ load_args.load_pid = getpid(); if (perfmonctl(ctx_fd, PFM_LOAD_CONTEXT, &load_args, 1) == -1) { fatal_error("perfmonctl error PFM_LOAD_CONTEXT errno %d\n",errno); } /* * start monitoring. We must go to the kernel because psr.pp cannot be * changed at the user level. */ if (perfmonctl(ctx_fd, PFM_START, 0, 0) == -1) { fatal_error("perfmonctl error PFM_START errno %d\n",errno); } printf("\n", which_cpu); printf("\n"); getchar(); /* * stop monitoring. We must go to the kernel because psr.pp cannot be * changed at the user level. */ if (perfmonctl(ctx_fd, PFM_STOP, 0, 0) == -1) { fatal_error("perfmonctl error PFM_STOP errno %d\n",errno); } printf("\n\n", which_cpu); /* * now read the results */ if (perfmonctl(ctx_fd, PFM_READ_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error( "perfmonctl error READ_PMDS errno %d\n",errno); return -1; } /* * print the results * * It is important to realize, that the first event we specified may not * be in PMD4. Not all events can be measured by any monitor. That's why * we need to use the pc[] array to figure out where event i was allocated. * */ for (i=0; i < inp.pfp_event_count; i++) { pfm_get_full_event_name(&inp.pfp_events[i], name, MAX_EVT_NAME_LEN); printf("CPU%-2d PMD%u %20"PRIu64" %s\n", which_cpu, pd[i].reg_num, pd[i].reg_value, name); } /* * let's stop this now */ close(ctx_fd); return 0; } papi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/mont_etb.c0000644000307100002310000003276713013651447022330 0ustar yarkhangraduate/* * mont_btb.c - example of how use the BTB with the Dual-Core Itanium 2 PMU * * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #include #include #include #include #include #include #include #include #include #include #include #include #include typedef pfm_default_smpl_hdr_t etb_hdr_t; typedef pfm_default_smpl_entry_t etb_entry_t; typedef pfm_default_smpl_ctx_arg_t etb_ctx_arg_t; #define BTB_FMT_UUID PFM_DEFAULT_SMPL_UUID static pfm_uuid_t buf_fmt_id = BTB_FMT_UUID; #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 #define MAX_PMU_NAME_LEN 32 /* * The BRANCH_EVENT is increment by 1 for each branch event. Such event is composed of * two entries in the BTB: a source and a target entry. The BTB is full after 4 branch * events. */ #define SMPL_PERIOD (4UL*256) /* * We use a small buffer size to exercise the overflow handler */ #define SMPL_BUF_NENTRIES 64 #define M_PMD(x) (1UL<<(x)) #define ETB_REGS_MASK (M_PMD(38)| M_PMD(39)| \ M_PMD(48)|M_PMD(49)|M_PMD(50)|M_PMD(51)|M_PMD(52)|M_PMD(53)|M_PMD(54)|M_PMD(55)|\ M_PMD(56)|M_PMD(57)|M_PMD(58)|M_PMD(59)|M_PMD(60)|M_PMD(61)|M_PMD(62)|M_PMD(63)) static void *smpl_vaddr; static size_t entry_size; static int id; #if defined(__ECC) && defined(__INTEL_COMPILER) /* if you do not have this file, your compiler is too old */ #include #define hweight64(x) _m64_popcnt(x) #elif defined(__GNUC__) static __inline__ int hweight64 (unsigned long x) { unsigned long result; __asm__ ("popcnt %0=%1" : "=r" (result) : "r" (x)); return (int)result; } #else #error "you need to provide inline assembly from your compiler" #endif /* * we don't use static to make sure the compiler does not inline the function */ long func1(void) { return random();} long func2(void) { return random();} long do_test(unsigned long loop) { long sum = 0; while(loop--) { if (loop & 0x1) sum += func1(); else sum += loop + func2(); } return sum; } static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } /* * print content of sampling buffer * * XXX: using stdio to print from a signal handler is not safe with multi-threaded * applications */ #define safe_printf printf static void show_etb_reg(int j, pfm_mont_pmd_reg_t reg, pfm_mont_pmd_reg_t pmd39) { unsigned long bruflush, b1, etb_ext; unsigned long addr; int is_valid; is_valid = reg.pmd48_63_etb_mont_reg.etb_s == 0 && reg.pmd48_63_etb_mont_reg.etb_mp == 0 ? 0 : 1; /* * the joy of the ETB extension register layout! */ if (j < 8) etb_ext = (pmd39.pmd_val>>(8*j)) & 0xf; else etb_ext = (pmd39.pmd_val>>(4+8*(j-1))) & 0xf; b1 = etb_ext & 0x1; bruflush = (etb_ext >> 1) & 0x1; safe_printf("\tPMD%-2d: 0x%016lx s=%d mp=%d bru=%ld b1=%ld valid=%c\n", j+48, reg.pmd_val, reg.pmd48_63_etb_mont_reg.etb_s, reg.pmd48_63_etb_mont_reg.etb_mp, bruflush, b1, is_valid ? 'Y' : 'N'); if (!is_valid) return; if (reg.pmd48_63_etb_mont_reg.etb_s) { addr = (reg.pmd48_63_etb_mont_reg.etb_addr+b1)<<4; addr |= reg.pmd48_63_etb_mont_reg.etb_slot < 3 ? reg.pmd48_63_etb_mont_reg.etb_slot : 0; safe_printf("\t Source Address: 0x%016lx\n" "\t Taken=%c Prediction:%s\n\n", addr, reg.pmd48_63_etb_mont_reg.etb_slot < 3 ? 'Y' : 'N', reg.pmd48_63_etb_mont_reg.etb_mp ? "FE Failure" : bruflush ? "BE Failure" : "Success"); } else { safe_printf("\t Target Address:0x%016lx\n\n", (unsigned long)(reg.pmd48_63_etb_mont_reg.etb_addr<<4)); } } static void show_etb(pfm_mont_pmd_reg_t *etb) { int i, last; pfm_mont_pmd_reg_t pmd38, pmd39; pmd38.pmd_val = etb[0].pmd_val; pmd39.pmd_val = etb[1].pmd_val; i = pmd38.pmd38_mont_reg.etbi_full ? pmd38.pmd38_mont_reg.etbi_ebi : 0; last = pmd38.pmd38_mont_reg.etbi_ebi; safe_printf("btb_trace: i=%d last=%d bbi=%d full=%d\n", i, last, pmd38.pmd38_mont_reg.etbi_ebi, pmd38.pmd38_mont_reg.etbi_full); do { show_etb_reg(i, etb[i], pmd39); i = (i+1) % 16; } while (i != last); } void process_smpl_buffer(void) { etb_hdr_t *hdr; etb_entry_t *ent; unsigned long pos; unsigned long smpl_entry = 0; pfm_mont_pmd_reg_t *reg; size_t count; static unsigned long last_ovfl = ~0UL; hdr = (etb_hdr_t *)smpl_vaddr; /* * check that we are not diplaying the previous set of samples again. * Required to take care of the last batch of samples. */ if (hdr->hdr_overflows <= last_ovfl && last_ovfl != ~0UL) { printf("skipping identical set of samples %lu <= %lu\n", hdr->hdr_overflows, last_ovfl); return; } pos = (unsigned long)(hdr+1); count = hdr->hdr_count; /* * walk through all the entries recored in the buffer */ while(count--) { ent = (etb_entry_t *)pos; /* * print entry header */ safe_printf("Entry %ld PID:%d TID:%d CPU:%d STAMP:0x%lx IIP:0x%016lx\n", smpl_entry++, ent->tgid, ent->pid, ent->cpu, ent->tstamp, ent->ip); /* * point to first recorded register (always contiguous with entry header) */ reg = (pfm_mont_pmd_reg_t*)(ent+1); /* * in this particular example, we have pmd48-pmd63 has the ETB. We have also * included pmd38/pmd39 (ETB index and extenseion) has part of the registers * to record. This trick allows us to get the index to decode the sequential * order of the BTB. * * Recorded registers are always recorded in increasing index order. So we know * that where to find pmd38/pmd39. */ show_etb(reg); /* * move to next entry */ pos += entry_size; } } static void overflow_handler(int n, struct siginfo *info, struct sigcontext *sc) { process_smpl_buffer(); /* * And resume monitoring */ if (perfmonctl(id, PFM_RESTART, NULL, 0)) fatal_error("pfm_restart errno %d\n", errno); } int main(void) { int ret; int type = 0; pfarg_reg_t pd[NUM_PMDS]; pfarg_reg_t pc[NUM_PMCS]; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_mont_input_param_t mont_inp; etb_ctx_arg_t ctx; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; struct sigaction act; unsigned int i; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) fatal_error("Can't initialize library\n"); /* * Let's make sure we run this on the right CPU */ pfm_get_pmu_type(&type); if (type != PFMLIB_MONTECITO_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with %s PMU\n", model); } /* * Install the overflow handler (SIGIO) */ memset(&act, 0, sizeof(act)); act.sa_handler = (sig_t)overflow_handler; sigaction (SIGIO, &act, 0); /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 0; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); memset(pd, 0, sizeof(pd)); memset(&ctx, 0, sizeof(ctx)); /* * prepare parameters to library. we don't use any Itanium * specific features here. so the pfp_model is NULL. */ memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&mont_inp,0, sizeof(mont_inp)); /* * Before calling pfm_find_dispatch(), we must specify what kind * of branches we want to capture. We are interested in all taken * branches * therefore we program we set the various fields to: */ mont_inp.pfp_mont_etb.etb_used = 1; mont_inp.pfp_mont_etb.etb_tm = 0x2; mont_inp.pfp_mont_etb.etb_ptm = 0x3; mont_inp.pfp_mont_etb.etb_ppm = 0x3; mont_inp.pfp_mont_etb.etb_brt = 0x0; mont_inp.pfp_mont_etb.etb_plm = PFM_PLM3; /* * To count the number of occurence of this instruction, we must * program a counting monitor with the IA64_TAGGED_INST_RETIRED_PMC8 * event. */ if (pfm_find_full_event("BRANCH_EVENT", &inp.pfp_events[0]) != PFMLIB_SUCCESS) fatal_error("cannot find event BRANCH_EVENT\n"); /* * set the (global) privilege mode: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = 1; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, &mont_inp, &outp, NULL)) != PFMLIB_SUCCESS) fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); /* * We initialize the format specific information. * The format is identified by its UUID which must be copied * into the ctx_buf_fmt_id field. */ memcpy(ctx.ctx_arg.ctx_smpl_buf_id, buf_fmt_id, sizeof(pfm_uuid_t)); /* * the size of the buffer is indicated in bytes (not entries). * * The kernel will record into the buffer up to a certain point. * No partial samples are ever recorded. */ ctx.buf_arg.buf_size = getpagesize(); /* * now create the context for self monitoring/per-task */ if (perfmonctl(0, PFM_CREATE_CONTEXT, &ctx, 1) == -1 ) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * extract our file descriptor */ id = ctx.ctx_arg.ctx_fd; /* * retrieve the virtual address at which the sampling * buffer has been mapped */ smpl_vaddr = ctx.ctx_arg.ctx_smpl_vaddr; if (smpl_vaddr == MAP_FAILED) fatal_error("cannot mmap sampling buffer errno %d\n", errno); printf("Sampling buffer mapped at %p\n", smpl_vaddr); /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events cause extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * figure out pmd mapping from output pmc * PMD38 returned as used PMD by libpfm, will be reset */ for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * indicate we want notification when buffer is full and randomization */ pc[0].reg_flags |= PFM_REGFL_OVFL_NOTIFY | PFM_REGFL_RANDOM; /* * Now prepare the argument to initialize the PMD and the sampling period * We know we use only one PMD in this case, therefore pmd[0] corresponds * to our first event which is our sampling period. */ pd[0].reg_value = - SMPL_PERIOD; pd[0].reg_long_reset = - SMPL_PERIOD; pd[0].reg_short_reset = - SMPL_PERIOD; /* * indicate PMD to collect in each sample (good up to PMD63) */ pc[0].reg_smpl_pmds[0] = ETB_REGS_MASK; /* * compute size of each sample: fixed-size header + all our BTB regs */ entry_size = sizeof(etb_entry_t)+(hweight64(ETB_REGS_MASK)<<3); /* * When our counter overflows, we want to ETB index to be reset, so that we keep * in sync. */ pc[0].reg_reset_pmds[0] = M_PMD(38); /* * Now program the registers */ if (perfmonctl(id, PFM_WRITE_PMCS, pc, outp.pfp_pmc_count)) fatal_error("pfm_write_pmcs error errno %d\n",errno); /* * we use 2 registers = 1 for the branch_event + 1 to reset PMD38 */ if (perfmonctl(id, PFM_WRITE_PMDS, pd, outp.pfp_pmd_count)) fatal_error("pfm_write_pmds error errno %d\n",errno); /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = getpid(); if (perfmonctl(id, PFM_LOAD_CONTEXT, &load_args, 1)) fatal_error("pfm_load_context error errno %d\n",errno); /* * setup asynchronous notification on the file descriptor */ ret = fcntl(id, F_SETFL, fcntl(id, F_GETFL, 0) | O_ASYNC); if (ret == -1) fatal_error("cannot set ASYNC: %s\n", strerror(errno)); /* * get ownership of the descriptor */ ret = fcntl(id, F_SETOWN, getpid()); if (ret == -1) fatal_error("cannot setown: %s\n", strerror(errno)); /* * Let's roll now. */ pfm_self_start(id); do_test(1000); pfm_self_stop(id); /* * We must call the processing routine to cover the last entries recorded * in the sampling buffer. Note that the buffer may not be full at this point. * */ process_smpl_buffer(); /* * let's stop this now */ close(id); return 0; } papi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/ita_opcode.c0000644000307100002310000002032513013651447022612 0ustar yarkhangraduate/* * ita_opcode.c - example of how to use the opcode matcher with the Itanium PMU * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #include #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 #define MAX_PMU_NAME_LEN 32 /* * we don't use static to make sure the compiler does not inline the function */ int do_test(unsigned long loop) { unsigned long sum = 0; while(loop--) sum += loop; return sum; } static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } int main(void) { int ret; int type = 0; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_ita_input_param_t ita_inp; pfarg_reg_t pd[NUM_PMDS]; pfarg_reg_t pc[NUM_PMCS]; pfarg_context_t ctx[1]; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; unsigned int i; int id; char name[MAX_EVT_NAME_LEN]; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) { fatal_error("Can't initialize library\n"); } /* * Let's make sure we run this on the right CPU */ pfm_get_pmu_type(&type); if (type != PFMLIB_ITANIUM_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with the %s PMU\n", model); } /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 0; /* set to 1 for verbose */ pfm_set_options(&pfmlib_options); memset(pd, 0, sizeof(pd)); memset(ctx, 0, sizeof(ctx)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&ita_inp,0, sizeof(ita_inp)); memset(&load_args,0, sizeof(load_args)); /* * We indicate that we are using the PMC8 opcode matcher. This is required * otherwise the library add PMC8 to the list of PMC to pogram during * pfm_dispatch_events(). */ ita_inp.pfp_ita_pmc8.opcm_used = 1; /* * We want to match all the br.cloop in our test function. * This branch is an IP-relative branch for which the major * opcode (bits [40-37]=4) and the btype field is 5 (which represents * bits[6-8]) so it is included in the match/mask fields of PMC8. * It is necessarily in a B slot. * * We don't care which operands are used with br.cloop therefore * the mask field of pmc8 is set such that only the 4 bits of the * opcode and 3 bits of btype must match exactly. This is accomplished by * clearing the top 4 bits and bits [6-8] of the mask field and setting the * remaining bits. Similarly, the match field only has the opcode value and btype * set according to the encoding of br.cloop, the * remaining bits are zero. Bit 60 of PMC8 is set to indicate * that we look only in B slots (this is the only possibility for * this instruction anyway). * * So the binary representation of the value for PMC8 is as follows: * * 6666555555555544444444443333333333222222222211111111110000000000 * 3210987654321098765432109876543210987654321098765432109876543210 * ---------------------------------------------------------------- * 0001010000000000000000101000000000000011111111111111000111111000 * * which yields a value of 0x1400028003fff1f8. * * Depending on the level of optimization to compile this code, it may * be that the count reported could be zero, if the compiler uses a br.cond * instead of br.cloop. */ ita_inp.pfp_ita_pmc8.pmc_val = 0x1400028003fff1f8; /* * To count the number of occurence of this instruction, we must * program a counting monitor with the IA64_TAGGED_INST_RETIRED_PMC8 * event. */ if (pfm_find_full_event("IA64_TAGGED_INST_RETIRED_PMC8", &inp.pfp_events[0]) != PFMLIB_SUCCESS) { fatal_error("Cannot find event IA64_TAGGED_INST_RETIRED_PMC8\n"); } /* * set the privilege mode: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = 1; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, &ita_inp, &outp, NULL)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); } /* * now create the context for self monitoring/per-task */ if (perfmonctl(0, PFM_CREATE_CONTEXT, ctx, 1) == -1 ) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * extract our file descriptor */ id = ctx[0].ctx_fd; /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events cause extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * the PMC controlling the event ALWAYS come first, that's why this loop * is safe even when extra PMC are needed to support a particular event. */ for (i=0; i < inp.pfp_event_count; i++) { pd[i].reg_num = pc[i].reg_num; } /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more thann coutning monitors. */ if (perfmonctl(id, PFM_WRITE_PMCS, pc, outp.pfp_pmc_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMCS errno %d\n",errno); } if (perfmonctl(id, PFM_WRITE_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMDS errno %d\n",errno); } /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = getpid(); if (perfmonctl(id, PFM_LOAD_CONTEXT, &load_args, 1) == -1) { fatal_error("perfmonctl error PFM_LOAD_CONTEXT errno %d\n",errno); } /* * Let's roll now. */ pfm_self_start(id); do_test(100UL); pfm_self_stop(id); /* * now read the results */ if (perfmonctl(id, PFM_READ_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error( "perfmonctl error READ_PMDS errno %d\n",errno); } /* * print the results */ pfm_get_full_event_name(&inp.pfp_events[0], name, MAX_EVT_NAME_LEN); printf("PMD%u %20lu %s\n", pd[0].reg_num, pd[0].reg_value, name); if (pd[0].reg_value != 0) printf("compiler used br.cloop\n"); else printf("compiler did not use br.cloop\n"); /* * let's stop this now */ close(id); return 0; } papi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/ita_rr.c0000644000307100002310000003006613013651447021767 0ustar yarkhangraduate/* * ita_rr.c - example of how to use data range restriction with the Itanium PMU * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #include #define N_LOOP 100000000U #if defined(__ECC) && defined(__INTEL_COMPILER) /* if you do not have this file, your compiler is too old */ #include #define clear_psr_ac() __rum(1UL<<3) #elif defined(__GNUC__) static inline void clear_psr_ac(void) { __asm__ __volatile__("rum psr.ac;;" ::: "memory" ); } #else #error "You need to define clear_psr_ac() for your compiler" #endif #define TEST_DATA_COUNT 16 #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_PMU_NAME_LEN 32 #define MAX_EVT_NAME_LEN 128 typedef struct { char *event_name; unsigned long expected_value; } event_desc_t; static event_desc_t event_list[]={ { "misaligned_loads_retired", N_LOOP }, { "misaligned_stores_retired", N_LOOP }, { NULL, 0UL} }; typedef union { unsigned long l_tab[2]; unsigned int i_tab[4]; unsigned short s_tab[8]; unsigned char c_tab[16]; } test_data_t; static int do_test(test_data_t *data) { unsigned int *l, v; l = (unsigned int *)(data->c_tab+1); if (((unsigned long)l & 0x1) == 0) { printf("Data is not unaligned, can't run test\n"); return -1; } v = *l; v++; *l = v; return 0; } static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } int main(int argc, char **argv) { event_desc_t *p; test_data_t *test_data, *test_data_fake; unsigned long range_start, range_end; int ret, type = 0; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_ita_input_param_t ita_inp; pfmlib_ita_output_param_t ita_outp; pfarg_reg_t pd[NUM_PMDS]; pfarg_reg_t pc[NUM_PMCS]; pfarg_dbreg_t dbrs[8]; pfarg_context_t ctx[1]; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; unsigned int i; int id; char name[MAX_EVT_NAME_LEN]; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) { fatal_error("Can't initialize library\n"); } /* * Let's make sure we run this on the right CPU family */ pfm_get_pmu_type(&type); if (type != PFMLIB_ITANIUM_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with %s PMU\n", model); } /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 0; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); /* * now let's allocate the data structure we will be monitoring */ test_data = (test_data_t *)malloc(sizeof(test_data_t)*TEST_DATA_COUNT); if (test_data == NULL) { fatal_error("cannot allocate test data structure"); } test_data_fake = (test_data_t *)malloc(sizeof(test_data_t)*TEST_DATA_COUNT); if (test_data_fake == NULL) { fatal_error("cannot allocate test data structure"); } /* * Compute the range we are interested in */ range_start = (unsigned long)test_data; range_end = range_start + sizeof(test_data_t)*TEST_DATA_COUNT; memset(pd, 0, sizeof(pd)); memset(pc, 0, sizeof(pc)); memset(ctx, 0, sizeof(ctx)); memset(dbrs,0, sizeof(dbrs)); memset(&load_args, 0, sizeof(load_args)); /* * prepare parameters to library. we don't use any Itanium * specific features here. so the pfp_model is NULL. */ memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&ita_inp,0, sizeof(ita_inp)); memset(&ita_outp,0, sizeof(ita_outp)); /* * find requested event */ p = event_list; for (i=0; p->event_name ; i++, p++) { if (pfm_find_event(p->event_name, &inp.pfp_events[i].event) != PFMLIB_SUCCESS) { fatal_error("Cannot find %s event\n", p->event_name); } } /* * set the privilege mode: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = i; /* * We use the library to figure out how to program the debug registers * to cover the data range we are interested in. The rr_end parameter * must point to the byte after the last of the range (C-style range). * * Because of the masking mechanism and therefore alignment constraints used to implement * this feature, it may not be possible to exactly cover a given range. It may be that * the coverage exceeds the desired range. So it is possible to capture noise if * the surrounding addresses are also heavily used. You can figure out, the actual * start and end offsets of the generated range by checking the rr_soff and rr_eoff fields * in the pfmlib_ita_output_param_t structure when coming back from the library call. * * Upon return, the pfmlib_ita_output_param_t.pfp_ita_drange.rr_dbr array is programmed and * the number of entries used to cover the range is in rr_nbr_used. */ /* * We indicate that we are using a Data Range Restriction feature. * In this particular case this will cause, pfm_dispatch_events() to * add pmc13 to the list of PMC registers to initialize and the */ ita_inp.pfp_ita_drange.rr_used = 1; ita_inp.pfp_ita_drange.rr_limits[0].rr_start = range_start; ita_inp.pfp_ita_drange.rr_limits[0].rr_end = range_end; /* * use the library to find the monitors to use * * upon return, cnt contains the number of entries * used in pc[]. */ if ((ret=pfm_dispatch_events(&inp, &ita_inp, &outp, &ita_outp)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); } printf("data range : [0x%016lx-0x%016lx): %d pair of debug registers used\n" "start_offset:-0x%lx end_offset:+0x%lx\n", range_start, range_end, ita_outp.pfp_ita_drange.rr_nbr_used >> 1, ita_outp.pfp_ita_drange.rr_infos[0].rr_soff, ita_outp.pfp_ita_drange.rr_infos[0].rr_eoff); printf("fake data range: [0x%016lx-0x%016lx)\n", (unsigned long)test_data_fake, (unsigned long)test_data_fake+sizeof(test_data_t)*TEST_DATA_COUNT); /* * now create the context for self monitoring/per-task */ if (perfmonctl(0, PFM_CREATE_CONTEXT, ctx, 1) == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("cannot create PFM context %s\n", strerror(errno)); } /* * extract our file descriptor */ id = ctx[0].ctx_fd; /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events cause extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * the PMC controlling the event ALWAYS come first, that's why this loop * is safe even when extra PMC are needed to support a particular event. */ for (i=0; i < inp.pfp_event_count; i++) { pd[i].reg_num = pc[i].reg_num; } /* * propagate the setup for the debug registers from the library to the arguments * to the perfmonctl() syscall. The library does not know the type of the syscall * anymore. */ for (i=0; i < ita_outp.pfp_ita_drange.rr_nbr_used; i++) { dbrs[i].dbreg_num = ita_outp.pfp_ita_drange.rr_br[i].reg_num; dbrs[i].dbreg_value = ita_outp.pfp_ita_drange.rr_br[i].reg_value; } /* * Program the data debug registers. * * IMPORTANT: programming the debug register MUST always be done before the PMCs * otherwise the kernel will fail on PFM_WRITE_PMCS. This is for security reasons. */ if (perfmonctl(id, PFM_WRITE_DBRS, dbrs, ita_outp.pfp_ita_drange.rr_nbr_used) == -1) { fatal_error("perfmonctl error PFM_WRITE_DBRS errno %d\n",errno); } /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more than coutning monitors. */ if (perfmonctl(id, PFM_WRITE_PMCS, pc, outp.pfp_pmc_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMCS errno %d\n",errno); } if (perfmonctl(id, PFM_WRITE_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMDS errno %d\n",errno); } /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = getpid(); if (perfmonctl(id, PFM_LOAD_CONTEXT, &load_args, 1) == -1) { fatal_error("perfmonctl error PFM_LOAD_CONTEXT errno %d\n",errno); } /* * Let's make sure that the hardware does the unaligned accesses (do not use the * kernel software handler otherwise the PMU won't see the unaligned fault). */ clear_psr_ac(); /* * Let's roll now. * * The idea behind this test is to have two dynamically allocated data structures * which are access in a unaligned fashion. But we want to capture only the unaligned * accesses on one of the two. So the debug registers are programmed to cover the * first one ONLY. Then we activate monotoring and access the two data structures. * This is an artificial example just to demonstrate how to use data address range * restrictions. */ pfm_self_start(id); for (i=0; i < N_LOOP; i++) { do_test(test_data); do_test(test_data_fake); } pfm_self_stop(id); /* * now read the results */ if (perfmonctl(id, PFM_READ_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error( "perfmonctl error READ_PMDS errno %d\n",errno); } /* * print the results * * It is important to realize, that the first event we specified may not * be in PMD4. Not all events can be measured by any monitor. That's why * we need to use the pc[] array to figure out where event i was allocated. * * For this example, we expect to see a value of 1 for both misaligned loads * and misaligned stores. But it can be two when the test_data and test_data_fake * are allocate very close from each other and the range created with the debug * registers is larger then test_data. * */ for (i=0; i < inp.pfp_event_count; i++) { pfm_get_full_event_name(&inp.pfp_events[i], name, MAX_EVT_NAME_LEN); printf("PMD%u %20lu %s (expected %lu)\n", pd[i].reg_num, pd[i].reg_value, name, event_list[i].expected_value); if (pd[i].reg_value != event_list[i].expected_value) { printf("error: Result should be %lu for %s\n", event_list[i].expected_value, name); break; } } /* * let's stop this now */ close(id); free(test_data); free(test_data_fake); return 0; } papi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/showreset.c0000644000307100002310000000530413013651447022527 0ustar yarkhangraduate/* * showreset.c - getting the PAL reset values for the PMCs * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } int main(int argc, char **argv) { unsigned int i, cnum = 0; pfarg_reg_t pc[NUM_PMCS]; pfmlib_regmask_t impl_pmcs; unsigned int num_pmcs; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) { printf("Can't initialize library\n"); exit(1); } memset(&impl_pmcs, 0, sizeof(impl_pmcs)); memset(pc, 0, sizeof(pc)); pfm_get_impl_pmcs(&impl_pmcs); pfm_get_num_pmcs(&num_pmcs); for(i=0; num_pmcs ; i++) { if (pfm_regmask_isset(&impl_pmcs, i) == 0) continue; pc[cnum++].reg_num = i; num_pmcs--; } if (perfmonctl(0, PFM_GET_PMC_RESET_VAL, pc, cnum) == -1 ) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("cannot get reset values: %s\n", strerror(errno)); } for (i=0; i < cnum; i++) { printf("PMC%u 0x%lx\n", pc[i].reg_num, pc[i].reg_value); } return 0; } papi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/ita_dear.c0000644000307100002310000002652513013651447022264 0ustar yarkhangraduate/* * ita_dear.c - example of how use the D-EAR with the Itanium PMU * * Copyright (c) 2003-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #include #include #include #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 #define MAX_PMU_NAME_LEN 32 #define EVENT_NAME "DATA_EAR_CACHE_LAT4" #define SMPL_PERIOD (40) #define M_PMD(x) (1UL<<(x)) #define DEAR_REGS_MASK (M_PMD(2)|M_PMD(3)|M_PMD(17)) typedef pfm_default_smpl_hdr_t dear_hdr_t; typedef pfm_default_smpl_entry_t dear_entry_t; typedef pfm_default_smpl_ctx_arg_t dear_ctx_t; #define DEAR_FMT_UUID PFM_DEFAULT_SMPL_UUID static pfm_uuid_t buf_fmt_id = DEAR_FMT_UUID; static void *smpl_vaddr; static unsigned long entry_size; static int id; #if defined(__ECC) && defined(__INTEL_COMPILER) /* if you do not have this file, your compiler is too old */ #include #define hweight64(x) _m64_popcnt(x) #elif defined(__GNUC__) static __inline__ int hweight64 (unsigned long x) { unsigned long result; __asm__ ("popcnt %0=%1" : "=r" (result) : "r" (x)); return (int)result; } #else #error "you need to provide inline assembly from your compiler" #endif long do_test(unsigned long size) { unsigned long i, sum = 0; int *array; printf("buffer size %.1fMB\n", (size*sizeof(int))/1024.0); array = (int *)malloc(size * sizeof(int)); if (array == NULL ) { printf("buffer size %.1fMB\n", (size*sizeof(int))/1024.0); exit(1); } for(i=0; ihdr_overflows <= last_ovfl && last_ovfl != ~0UL) { printf("skipping identical set of samples %lu <= %lu\n", hdr->hdr_overflows, last_ovfl); return; } pos = (unsigned long)(hdr+1); /* * walk through all the entries recored in the buffer */ for(i=0; i < hdr->hdr_count; i++) { ret = 0; ent = (dear_entry_t *)pos; /* * print entry header */ safe_printf("Entry %ld PID:%d CPU:%d STAMP:0x%lx IIP:0x%016lx\n", smpl_entry++, ent->pid, ent->cpu, ent->tstamp, ent->ip); /* * point to first recorded register (always contiguous with entry header) */ reg = (pfm_ita_pmd_reg_t*)(ent+1); safe_printf("PMD2 : 0x%016lx\n", reg->pmd_val); reg++; safe_printf("PMD3 : 0x%016lx, latency %u\n", reg->pmd_val, reg->pmd3_ita_reg.dear_latency); reg++; safe_printf("PMD17: 0x%016lx, valid %c, address 0x%016lx\n", reg->pmd_val, reg->pmd17_ita_reg.dear_vl ? 'Y': 'N', (reg->pmd17_ita_reg.dear_iaddr << 4) | (unsigned long)reg->pmd17_ita_reg.dear_slot); /* * move to next entry */ pos += entry_size; } } static void overflow_handler(int n, struct siginfo *info, struct sigcontext *sc) { /* dangerous */ printf("Notification received\n"); process_smpl_buffer(); /* * And resume monitoring */ if (perfmonctl(id, PFM_RESTART,NULL, 0) == -1) { perror("PFM_RESTART"); exit(1); } } int main(void) { pfarg_reg_t pd[NUM_PMDS]; pfarg_reg_t pc[NUM_PMCS]; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_event_t ev; dear_ctx_t ctx[1]; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; struct sigaction act; unsigned int i; int ret, type = 0; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) { fatal_error("Can't initialize library\n"); } /* * Let's make sure we run this on the right CPU */ pfm_get_pmu_type(&type); if (type != PFMLIB_ITANIUM_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with %s PMU\n", model); } /* * Install the overflow handler (SIGIO) */ memset(&act, 0, sizeof(act)); act.sa_handler = (sig_t)overflow_handler; sigaction (SIGIO, &act, 0); /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 1; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); memset(pd, 0, sizeof(pd)); memset(pc, 0, sizeof(pc)); memset(ctx, 0, sizeof(ctx)); memset(&load_args, 0, sizeof(load_args)); /* * prepare parameters to library. we don't use any Itanium * specific features here. so the pfp_model is NULL. */ memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); /* * To count the number of occurence of this instruction, we must * program a counting monitor with the IA64_TAGGED_INST_RETIRED_PMC8 * event. */ if (pfm_find_full_event(EVENT_NAME, &ev) != PFMLIB_SUCCESS) { fatal_error("cannot find event %s\n", EVENT_NAME); } /* * set the (global) privilege mode: * PFM_PLM0 : kernel level only */ inp.pfp_dfl_plm = PFM_PLM0|PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = 1; /* * propagate the event descriptor */ inp.pfp_events[0] = ev; /* * let the library figure out the values for the PMCS * * We use all global settings for this EAR. */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); } /* * prepare context structure. * * format specific parameters MUST be concatenated to the regular * pfarg_context_t structure. For convenience, the default sampling * format provides a data structure that already combines the pfarg_context_t * with what is needed fot this format. */ /* * We initialize the format specific information. * The format is identified by its UUID which must be copied * into the ctx_buf_fmt_id field. */ memcpy(ctx[0].ctx_arg.ctx_smpl_buf_id, buf_fmt_id, sizeof(pfm_uuid_t)); /* * the size of the buffer is indicated in bytes (not entries). * * The kernel will record into the buffer up to a certain point. * No partial samples are ever recorded. */ ctx[0].buf_arg.buf_size = 4096; /* * now create the context for self monitoring/per-task */ if (perfmonctl(0, PFM_CREATE_CONTEXT, ctx, 1) == -1 ) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * extract the file descriptor we will use to * identify this newly created context */ id = ctx[0].ctx_arg.ctx_fd; printf("Sampling buffer mapped at %p\n", ctx[0].ctx_arg.ctx_smpl_vaddr); smpl_vaddr = ctx[0].ctx_arg.ctx_smpl_vaddr; /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events causes extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * the PMC controlling the event ALWAYS come first, that's why this loop * is safe even when extra PMC are needed to support a particular event. */ for (i=0; i < inp.pfp_event_count; i++) { pd[i].reg_num = pc[i].reg_num; } /* * indicate we want notification when buffer is full */ pc[0].reg_flags |= PFM_REGFL_OVFL_NOTIFY; /* * indicate which PMD to include in the sample */ pc[0].reg_smpl_pmds[0] = DEAR_REGS_MASK; /* * compute size of each sample: fixed-size header + all our DEAR regs */ entry_size = sizeof(dear_entry_t)+(hweight64(DEAR_REGS_MASK)<<3); /* * initialize the PMD and the sampling period */ pd[0].reg_value = (~0UL) - SMPL_PERIOD +1; pd[0].reg_long_reset = (~0UL) - SMPL_PERIOD +1; pd[0].reg_short_reset = (~0UL) - SMPL_PERIOD +1; /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more thann coutning monitors. */ if (perfmonctl(id, PFM_WRITE_PMCS, pc, outp.pfp_pmc_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMCS errno %d\n",errno); } if (perfmonctl(id, PFM_WRITE_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMDS errno %d\n",errno); } /* * attach context to stopped task */ load_args.load_pid = getpid(); if (perfmonctl(id, PFM_LOAD_CONTEXT, &load_args, 1) == -1) { fatal_error("perfmonctl error PFM_LOAD_CONTEXT errno %d\n",errno); } /* * setup asynchronous notification on the file descriptor */ ret = fcntl(id, F_SETFL, fcntl(id, F_GETFL, 0) | O_ASYNC); if (ret == -1) { fatal_error("cannot set ASYNC: %s\n", strerror(errno)); } /* * get ownership of the descriptor */ ret = fcntl(id, F_SETOWN, getpid()); if (ret == -1) { fatal_error("cannot setown: %s\n", strerror(errno)); } /* * Let's roll now. */ pfm_self_start(id); do_test(10000); pfm_self_stop(id); /* * We must call the processing routine to cover the last entries recorded * in the sampling buffer, i.e. which may not be full */ process_smpl_buffer(); /* * let's stop this now */ close(id); return 0; } papi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/task_smpl.c0000644000307100002310000003132013013651447022476 0ustar yarkhangraduate/* * task_smpl.c - example of a task sampling another one using a randomized sampling period * * Copyright (c) 2003-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include typedef pfm_default_smpl_arg_t smpl_fmt_arg_t; typedef pfm_default_smpl_hdr_t smpl_hdr_t; typedef pfm_default_smpl_entry_t smpl_entry_t; typedef pfm_default_smpl_ctx_arg_t ctx_arg_t; typedef int ctxid_t; #define FMT_UUID PFM_DEFAULT_SMPL_UUID #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define FIRST_COUNTER 4 static unsigned long collect_samples; static void *buf_addr; static pfm_uuid_t buf_fmt_id = FMT_UUID; static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void warning(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); } static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } int child(char **arg) { /* * force the task to stop before executing the first * user level instruction */ ptrace(PTRACE_TRACEME, 0, NULL, NULL); execvp(arg[0], arg); /* not reached */ exit(1); } static __inline__ int bit_weight(unsigned long x) { int sum = 0; for (; x ; x>>=1) { if (x & 0x1UL) sum++; } return sum; } static void process_smpl_buf(int id, unsigned long smpl_pmd_mask, int need_restart) { static unsigned long last_overflow = ~0UL; /* initialize to biggest value possible */ smpl_hdr_t *hdr = (smpl_hdr_t *)buf_addr; smpl_entry_t *ent; unsigned long count, entry, *reg, pos, msk; unsigned long entry_size; int j; printf("processing %s buffer at %p\n", need_restart==0 ? "leftover" : "", hdr); if (hdr->hdr_overflows <= last_overflow && last_overflow != ~0UL) { warning("skipping identical set of samples %lu <= %lu\n", hdr->hdr_overflows, last_overflow); return; } last_overflow = hdr->hdr_overflows; count = hdr->hdr_count; ent = (smpl_entry_t *)(hdr+1); pos = (unsigned long)ent; entry = collect_samples; /* * in this example program, we use fixed-size entries, therefore we * can compute the entry size in advance. Perfmon-2 supports variable * size entries. */ entry_size = sizeof(smpl_entry_t)+(bit_weight(smpl_pmd_mask)<<3); while(count--) { printf("entry %ld PID:%d CPU:%d IIP:0x%016lx\n", entry, ent->pid, ent->cpu, ent->ip); printf("\tOVFL: %d LAST_VAL: %lu\n", ent->ovfl_pmd, -ent->last_reset_val); /* * print body: additional PMDs recorded * PMD are recorded in increasing index order */ reg = (unsigned long *)(ent+1); for(j=0, msk = smpl_pmd_mask; msk; msk >>=1, j++) { if ((msk & 0x1) == 0) continue; printf("PMD%-2d = 0x%016lx\n", j, *reg); reg++; } /* * we could have removed this and used: * ent = (smpl_entry_t *)reg * instead. */ pos += entry_size; ent = (smpl_entry_t *)pos; entry++; } collect_samples = entry; /* * reactivate monitoring once we are done with the samples * * Note that this call can fail with EBUSY in non-blocking mode * as the task may have disappeared while we were processing * the samples. */ if (need_restart && perfmonctl(id, PFM_RESTART, 0, 0) == -1) { if (errno != EBUSY) fatal_error("perfmonctl error PFM_RESTART errno %d\n",errno); else warning("PFM_RESTART: task has probably terminated \n"); } } int mainloop(char **arg) { ctx_arg_t ctx; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfarg_reg_t pd[NUM_PMDS]; pfarg_reg_t pc[NUM_PMCS]; pfarg_load_t load_args; pfm_msg_t msg; unsigned long ovfl_count = 0UL; unsigned long sample_period; unsigned long smpl_pmd_mask = 0UL; pid_t pid; int status, ret, fd; unsigned int i, num_counters; /* * intialize all locals */ memset(&ctx, 0, sizeof(ctx)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(pd, 0, sizeof(pd)); memset(pc, 0, sizeof(pc)); /* * locate events */ pfm_get_num_counters(&num_counters); if (pfm_get_cycle_event(&inp.pfp_events[0]) != PFMLIB_SUCCESS) fatal_error("cannot find cycle event\n"); if (pfm_get_inst_retired_event(&inp.pfp_events[1]) != PFMLIB_SUCCESS) fatal_error("cannot find inst retired event\n"); i = 2; if (i > num_counters) { i = num_counters; printf("too many events provided (max=%d events), using first %d event(s)\n", num_counters, i); } /* * set the privilege mode: * PFM_PLM3 : user level * PFM_PLM0 : kernel level */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = i; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); } /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events causes extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * the PMC controlling the event ALWAYS come first, that's why this loop * is safe even when extra PMC are needed to support a particular event. */ for (i=0; i < inp.pfp_event_count; i++) { pd[i].reg_num = pc[i].reg_num; /* build sampling mask */ smpl_pmd_mask |= 1UL << pc[i].reg_num; } printf("smpl_pmd_mask=0x%lx\n", smpl_pmd_mask); /* * now we indicate what to record when each counter overflows. * In our case, we only have one sampling period and it is set for the * first event. Here we indicate that when the sampling period expires * then we want to record the value of all the other counters. * * We exclude the first counter in this case. */ smpl_pmd_mask &= ~(1UL << pc[0].reg_num); pc[0].reg_smpl_pmds[0] = smpl_pmd_mask; /* * we our sampling counter overflow, we want to be notified. * The notification will come ONLY when the sampling buffer * becomes full. * * We also activate randomization of the sampling period. */ pc[0].reg_flags |= PFM_REGFL_OVFL_NOTIFY | PFM_REGFL_RANDOM; /* * we also want to reset the other PMDs on * every overflow. If we do not set * this, the non-overflowed counters * will be untouched. */ pc[0].reg_reset_pmds[0] |= smpl_pmd_mask; sample_period = 1000000UL; pd[0].reg_value = (~0) - sample_period + 1; pd[0].reg_short_reset = (~0) - sample_period + 1; pd[0].reg_long_reset = (~0) - sample_period + 1; /* * setup randomization parameters, we allow a range of up to +256 here. */ pd[0].reg_random_seed = 5; pd[0].reg_random_mask = 0xff; printf("programming %u PMCS and %u PMDS\n", outp.pfp_pmc_count, inp.pfp_event_count); /* * prepare context structure. * * format specific parameters MUST be concatenated to the regular * pfarg_context_t structure. For convenience, the default sampling * format provides a data structure that already combines the pfarg_context_t * with what is needed fot this format. */ /* * We initialize the format specific information. * The format is identified by its UUID which must be copied * into the ctx_buf_fmt_id field. */ memcpy(ctx.ctx_arg.ctx_smpl_buf_id, buf_fmt_id, sizeof(pfm_uuid_t)); /* * the size of the buffer is indicated in bytes (not entries). * * The kernel will record into the buffer up to a certain point. * No partial samples are ever recorded. */ ctx.buf_arg.buf_size = 8192; /* * now create our perfmon context. */ if (perfmonctl(0, PFM_CREATE_CONTEXT, &ctx, 1) == -1 ) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * extract the file descriptor we will use to * identify this newly created context */ fd = ctx.ctx_arg.ctx_fd; /* * retrieve the virtual address at which the sampling * buffer has been mapped */ buf_addr = ctx.ctx_arg.ctx_smpl_vaddr; printf("context [%d] buffer mapped @%p\n", fd, buf_addr); /* * Now program the registers */ if (perfmonctl(fd, PFM_WRITE_PMCS, pc, outp.pfp_pmc_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMCS errno %d\n",errno); } /* * initialize the PMDs */ if (perfmonctl(fd, PFM_WRITE_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMDS errno %d\n",errno); } /* * Create the child task */ if ((pid=fork()) == -1) fatal_error("Cannot fork process\n"); /* * In order to get the PFM_END_MSG message, it is important * to ensure that the child task does not inherit the file * descriptor of the context. By default, file descriptor * are inherited during exec(). We explicitely close it * here. We could have set it up through fcntl(FD_CLOEXEC) * to achieve the same thing. */ if (pid == 0) { close(fd); child(arg); } /* * wait for the child to exec */ waitpid(pid, &status, WUNTRACED); /* * process is stopped at this point */ if (WIFEXITED(status)) { warning("task %s [%d] exited already status %d\n", arg[0], pid, WEXITSTATUS(status)); goto terminate_session; } /* * attach context to stopped task */ load_args.load_pid = pid; if (perfmonctl(fd, PFM_LOAD_CONTEXT, &load_args, 1) == -1) { fatal_error("perfmonctl error PFM_LOAD_CONTEXT errno %d\n",errno); } /* * activate monitoring for stopped task. * (nothing will be measured at this point */ if (perfmonctl(fd, PFM_START, NULL, 0) == -1) { fatal_error(" perfmonctl error PFM_START errno %d\n",errno); } /* * detach child. Side effect includes * activation of monitoring. */ ptrace(PTRACE_DETACH, pid, NULL, 0); /* * core loop */ for(;;) { /* * wait for overflow/end notification messages */ ret = read(fd, &msg, sizeof(msg)); if (ret == -1) { fatal_error("cannot read perfmon msg: %s\n", strerror(errno)); } switch(msg.type) { case PFM_MSG_OVFL: /* the sampling buffer is full */ process_smpl_buf(fd, smpl_pmd_mask, 1); ovfl_count++; break; case PFM_MSG_END: /* monitored task terminated */ printf("task terminated\n"); goto terminate_session; default: fatal_error("unknown message type %d\n", msg.type); } } terminate_session: /* * cleanup child */ waitpid(pid, &status, 0); /* * check for any leftover samples */ process_smpl_buf(fd, smpl_pmd_mask, 0); /* * destroy perfmon context */ close(fd); printf("%lu samples collected in %lu buffer overflows\n", collect_samples, ovfl_count); return 0; } int main(int argc, char **argv) { pfmlib_options_t pfmlib_options; if (argc < 2) fatal_error("You must specify a command to execute\n"); /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) { fatal_error("Can't initialize library\n"); } /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 0; /* set to 1 for verbose */ pfm_set_options(&pfmlib_options); return mainloop(argv+1); } papi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/mont_irr.c0000644000307100002310000002455213013651447022343 0ustar yarkhangraduate/* * mont_irr.c - example of how to use code range restriction with the Dual-Core Itanium 2 PMU * * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #include #include #include #include #include #include #include #include #include #include #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 #define MAX_PMU_NAME_LEN 32 #define VECTOR_SIZE 1000000UL typedef struct { char *event_name; unsigned long expected_value; } event_desc_t; static event_desc_t event_list[]={ { "fp_ops_retired", VECTOR_SIZE<<1 }, { NULL, 0UL } }; static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } void saxpy(double *a, double *b, double *c, unsigned long size) { unsigned long i; for(i=0; i < size; i++) { c[i] = 2*a[i] + b[i]; } } void saxpy2(double *a, double *b, double *c, unsigned long size) { unsigned long i; for(i=0; i < size; i++) { c[i] = 2*a[i] + b[i]; } } static int do_test(void) { unsigned long size; double *a, *b, *c; size = VECTOR_SIZE; a = malloc(size*sizeof(double)); b = malloc(size*sizeof(double)); c = malloc(size*sizeof(double)); if (a == NULL || b == NULL || c == NULL) fatal_error("Cannot allocate vectors\n"); memset(a, 0, size*sizeof(double)); memset(b, 0, size*sizeof(double)); memset(c, 0, size*sizeof(double)); saxpy(a,b,c, size); saxpy2(a,b,c, size); return 0; } int main(int argc, char **argv) { event_desc_t *p; unsigned long range_start, range_end; int ret, type = 0; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_mont_input_param_t mont_inp; pfmlib_mont_output_param_t mont_outp; pfarg_reg_t pd[NUM_PMDS]; pfarg_reg_t pc[NUM_PMCS]; pfarg_dbreg_t ibrs[8]; pfarg_context_t ctx; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; struct fd { /* function descriptor */ unsigned long addr; unsigned long gp; } *fd; unsigned int i; int id; char name[MAX_EVT_NAME_LEN]; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) fatal_error("Can't initialize library\n"); /* * Let's make sure we run this on the right CPU family */ pfm_get_pmu_type(&type); if (type != PFMLIB_MONTECITO_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with %s PMU\n", model); } /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 1; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 1; /* set to 1 for verbose */ pfm_set_options(&pfmlib_options); /* * Compute the range we are interested in * * On IA-64, the function pointer does not point directly * to the function but to a descriptor which contains two * unsigned long: the first one is the actual start address * of the function, the second is the gp (global pointer) * to load into r1 before jumping into the function. Unlesss * we're jumping into a shared library the gp is the same as * the current gp. * * In the artificial example, we also rely on the compiler/linker * NOT reordering code layout. We depend on saxpy2() being just * after saxpy(). * */ fd = (struct fd *)saxpy; range_start = fd->addr; fd = (struct fd *)saxpy2; range_end = fd->addr; memset(pc, 0, sizeof(pc)); memset(pd, 0, sizeof(pd)); memset(&ctx, 0, sizeof(ctx)); memset(ibrs,0, sizeof(ibrs)); memset(&load_args,0, sizeof(load_args)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&mont_inp,0, sizeof(mont_inp)); memset(&mont_outp,0, sizeof(mont_outp)); /* * find requested event */ p = event_list; for (i=0; p->event_name ; i++, p++) { if (pfm_find_event(p->event_name, &inp.pfp_events[i].event) != PFMLIB_SUCCESS) { fatal_error("cannot find %s event\n", p->event_name); } } /* * set the privilege mode: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = i; /* * We use the library to figure out how to program the debug registers * to cover the data range we are interested in. The rr_end parameter * must point to the byte after the last element of the range (C-style range). * * Because of the masking mechanism and therefore alignment constraints used to implement * this feature, it may not be possible to exactly cover a given range. It may be that * the coverage exceeds the desired range. So it is possible to capture noise if * the surrounding addresses are also heavily used. You can figure out by how much the * actual range is off compared to the requested range by checking the rr_soff and rr_eoff * fields on return from the library call. * * Upon return, the rr_dbr array is programmed and the number of debug registers (not pairs) * used to cover the range is in rr_nbr_used. * * In the case of code range restriction on Itanium 2, the library will try to use the fine * mode first and then it will default to using multiple pairs to cover the range. */ mont_inp.pfp_mont_irange.rr_used = 1; /* indicate we use code range restriction */ mont_inp.pfp_mont_irange.rr_limits[0].rr_start = range_start; mont_inp.pfp_mont_irange.rr_limits[0].rr_end = range_end; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, &mont_inp, &outp, &mont_outp)) != PFMLIB_SUCCESS) fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); /* * print offsets */ printf("code range : [0x%016lx-0x%016lx)\n" "start_offset:-0x%lx end_offset:+0x%lx\n" "%d pairs of debug registers used\n", range_start, range_end, mont_outp.pfp_mont_irange.rr_infos[0].rr_soff, mont_outp.pfp_mont_irange.rr_infos[0].rr_eoff, mont_outp.pfp_mont_irange.rr_nbr_used >> 1); /* * now create the context for self monitoring/per-task */ if (perfmonctl(0, PFM_CREATE_CONTEXT, &ctx, 1) == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * extract our file descriptor */ id = ctx.ctx_fd; /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events cause extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * figure out pmd mapping from output pmc */ for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * propagate IBR settings. IBRS are mapped to PMC256-PMC263 */ for (i=0; i < mont_outp.pfp_mont_irange.rr_nbr_used; i++) { ibrs[i].dbreg_num = mont_outp.pfp_mont_irange.rr_br[i].reg_num; ibrs[i].dbreg_value = mont_outp.pfp_mont_irange.rr_br[i].reg_value; } /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more than coutning monitors. */ if (perfmonctl(id, PFM_WRITE_IBRS, ibrs, mont_outp.pfp_mont_irange.rr_nbr_used) == -1) fatal_error("child: perfmonctl error PFM_WRITE_IBRS errno %d\n",errno); if (perfmonctl(id, PFM_WRITE_PMCS, pc, outp.pfp_pmc_count)) fatal_error("child: pfm_write_pmcs error errno %d\n",errno); if (perfmonctl(id, PFM_WRITE_PMDS, pd, outp.pfp_pmd_count) == -1) fatal_error("child: pfm_write_pmds error errno %d\n",errno); /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = getpid(); if (perfmonctl(id, PFM_LOAD_CONTEXT, &load_args, 1)) fatal_error("pfm_load_context error errno %d\n",errno); /* * Let's roll now. * * We run two distinct copies of the same function but we restrict measurement * to the first one (saxpy). Therefore the expected count is half what you would * get if code range restriction was not used. The core loop in both case uses * two floating point operation per iteration. */ pfm_self_start(id); do_test(); pfm_self_stop(id); /* * now read the results */ if (perfmonctl(id, PFM_READ_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error( "pfm_read_pmds error errno %d\n",errno); } /* * print the results * * It is important to realize, that the first event we specified may not * be in PMD4. Not all events can be measured by any monitor. That's why * we need to use the pc[] array to figure out where event i was allocated. */ for (i=0; i < inp.pfp_event_count; i++) { pfm_get_full_event_name(&inp.pfp_events[i], name, MAX_EVT_NAME_LEN); printf("PMD%-3u %20lu %s (expected %lu)\n", pd[i].reg_num, pd[i].reg_value, name, event_list[i].expected_value); } /* * let's stop this now */ close(id); return 0; } papi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/task_attach_timeout.c0000644000307100002310000002274213013651447024545 0ustar yarkhangraduate/* * task_attach_timeout.c - attach to another task for monitoring for a short while * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } int parent(pid_t pid, unsigned long delay) { pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfarg_context_t ctx[1]; pfarg_reg_t pc[NUM_PMCS]; pfarg_reg_t pd[NUM_PMDS]; pfarg_load_t load_args; struct pollfd pollfd; pfm_msg_t msg; unsigned int i, num_counters; int status, ret; int ctx_fd; char name[MAX_EVT_NAME_LEN]; memset(pc, 0, sizeof(ctx)); memset(pd, 0, sizeof(ctx)); memset(ctx, 0, sizeof(ctx)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&load_args,0, sizeof(load_args)); pfm_get_num_counters(&num_counters); if (pfm_get_cycle_event(&inp.pfp_events[0]) != PFMLIB_SUCCESS) fatal_error("cannot find cycle event\n"); if (pfm_get_inst_retired_event(&inp.pfp_events[1]) != PFMLIB_SUCCESS) fatal_error("cannot find inst retired event\n"); i = 2; if (num_counters < i) { i = num_counters; printf("too many events provided (max=%d events), using first %d event(s)\n", num_counters, i); } /* * set the privilege mode: * PFM_PLM3 : user level * PFM_PLM0 : kernel level */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = i; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); } /* * now create a context. we will later attach it to the task we are creating. */ if (perfmonctl(0, PFM_CREATE_CONTEXT, ctx, 1) == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * extract the identifier for our context */ ctx_fd = ctx[0].ctx_fd; /* * use our file descriptor for the poll. * we are interested in read events only. */ pollfd.fd = ctx_fd; pollfd.events = POLLIN; /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events causes extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * the PMC controlling the event ALWAYS come first, that's why this loop * is safe even when extra PMC are needed to support a particular event. */ for (i=0; i < inp.pfp_event_count; i++) { pd[i].reg_num = pc[i].reg_num; } /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more thann counting monitors. */ if (perfmonctl(ctx_fd, PFM_WRITE_PMCS, pc, outp.pfp_pmc_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMCS errno %d\n",errno); } if (perfmonctl(ctx_fd, PFM_WRITE_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMDS errno %d\n",errno); } ret = ptrace(PTRACE_ATTACH, pid, NULL, 0); if (ret == -1) { fatal_error("cannot attach to %d: %s\n", pid, strerror(errno)); } /* * wait for the child to be actually stopped */ waitpid(pid, &status, WUNTRACED); /* * check if process exited early */ if (WIFEXITED(status)) { fatal_error("command process %d exited too early with status %d\n", pid, WEXITSTATUS(status)); } /* * the task is stopped at this point */ /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = pid; if (perfmonctl(ctx_fd, PFM_LOAD_CONTEXT, &load_args, 1) == -1) { fatal_error("perfmonctl error PFM_LOAD_CONTEXT errno %d\n",errno); } /* * activate monitoring. The task is still STOPPED at this point. Monitoring * will not take effect until the execution of the task is resumed. */ if (perfmonctl(ctx_fd, PFM_START, NULL, 0) == -1) { fatal_error("perfmonctl error PFM_START errno %d\n",errno); } /* * now resume execution of the task, effectively activating * monitoring. */ ptrace(PTRACE_DETACH, pid, NULL, 0); printf("attached to [%d], timeout set to %lu seconds\n", pid, delay); /* * now the task is running */ /* * We cannot simply do a waitpid() because we may be attaching to a process * totally unrelated to our program. Instead we use a perfmon facility that * notifies us when the monitoring task is exiting. * * When a task with a monitoring context attached to it exits, a PFM_MSG_END * is generated. It can be retrieve with a simple read() on the context's descriptor. * * Another reason why you might return from the read is if there was a counter * overflow, unlikely in this example. * * To measure only for short period of time, use select or poll with a timeout, * see task_attach_timeout.c * */ ret = poll(&pollfd, 1, delay*1000); switch( ret ) { case -1: fatal_error("cannot read from descriptor: %s\n", strerror(errno)); /* no return */ case 1: /* * there is a message, i.e., the program exited before our timeout */ if (ret == 1) { /* * extract message */ ret = read(ctx_fd, &msg, sizeof(msg)); if (msg.type != PFM_MSG_END) { fatal_error("unexpected msg type : %d\n", msg.type); } } break; case 0: /* * we timed out, we need to stop the task to unload */ ret = ptrace(PTRACE_ATTACH, pid, NULL, 0); if (ret == -1) { fatal_error("cannot attach to %d: %s\n", pid, strerror(errno)); } /* * wait for task to be actually stopped */ waitpid(pid, &status, WUNTRACED); /* * check if process exited, then no need to unload */ if (WIFEXITED(status)) goto read_results; if (perfmonctl(ctx_fd, PFM_UNLOAD_CONTEXT, NULL, 0) == -1) { fatal_error("perfmonctl error PFM_UNLOAD_CONTEXT errno %d\n",errno); } /* * let it run free again */ ptrace(PTRACE_DETACH, pid, NULL, 0); break; default: fatal_error("unexpected return from poll: %d\n", ret); } read_results: /* * now simply read the results. */ if (perfmonctl(ctx_fd, PFM_READ_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error("perfmonctl error READ_PMDS errno %d\n",errno); return -1; } /* * print the results * * It is important to realize, that the first event we specified may not * be in PMD4. Not all events can be measured by any monitor. That's why * we need to use the pc[] array to figure out where event i was allocated. * */ for (i=0; i < inp.pfp_event_count; i++) { pfm_get_full_event_name(&inp.pfp_events[i], name, MAX_EVT_NAME_LEN); printf("PMD%u %20"PRIu64" %s\n", pd[i].reg_num, pd[i].reg_value, name); } /* * free the context */ close(ctx_fd); return 0; } int main(int argc, char **argv) { pfmlib_options_t pfmlib_options; unsigned long delay; pid_t pid; if (argc < 2) { fatal_error("usage: %s pid [timeout]\n", argv[0]); } pid = atoi(argv[1]); delay = argc > 2 ? strtoul(argv[2], NULL, 10) : 10; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) { printf("Can't initialize library\n"); exit(1); } /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); return parent(pid, delay); } papi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/ita2_irr.c0000644000307100002310000002576513013651447022234 0ustar yarkhangraduate/* * ita2_irr.c - example of how to use code range restriction with the Itanium2 PMU * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #include #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 #define MAX_PMU_NAME_LEN 32 #define VECTOR_SIZE 1000000UL typedef struct { char *event_name; unsigned long expected_value; } event_desc_t; static event_desc_t event_list[]={ { "fp_ops_retired", VECTOR_SIZE<<1 }, { NULL, 0UL } }; static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } void saxpy(double *a, double *b, double *c, unsigned long size) { unsigned long i; for(i=0; i < size; i++) { c[i] = 2*a[i] + b[i]; } } void saxpy2(double *a, double *b, double *c, unsigned long size) { unsigned long i; for(i=0; i < size; i++) { c[i] = 2*a[i] + b[i]; } } static int do_test(void) { unsigned long size; double *a, *b, *c; size = VECTOR_SIZE; a = malloc(size*sizeof(double)); b = malloc(size*sizeof(double)); c = malloc(size*sizeof(double)); if (a == NULL || b == NULL || c == NULL) fatal_error("Cannot allocate vectors\n"); memset(a, 0, size*sizeof(double)); memset(b, 0, size*sizeof(double)); memset(c, 0, size*sizeof(double)); saxpy(a,b,c, size); saxpy2(a,b,c, size); return 0; } int main(int argc, char **argv) { event_desc_t *p; unsigned long range_start, range_end; int ret, type = 0; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_ita2_input_param_t ita2_inp; pfmlib_ita2_output_param_t ita2_outp; pfarg_reg_t pd[NUM_PMDS]; pfarg_reg_t pc[NUM_PMCS]; pfarg_dbreg_t ibrs[8]; pfarg_context_t ctx[1]; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; struct fd { /* function descriptor */ unsigned long addr; unsigned long gp; } *fd; unsigned int i; int id; char name[MAX_EVT_NAME_LEN]; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) { fatal_error("Can't initialize library\n"); } /* * Let's make sure we run this on the right CPU family */ pfm_get_pmu_type(&type); if (type != PFMLIB_ITANIUM2_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with %s PMU\n", model); } /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 1; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 1; /* set to 1 for verbose */ pfm_set_options(&pfmlib_options); /* * Compute the range we are interested in * * On IA-64, the function pointer does not point directly * to the function but to a descriptor which contains two * unsigned long: the first one is the actual start address * of the function, the second is the gp (global pointer) * to load into r1 before jumping into the function. Unlesss * we're jumping into a shared library the gp is the same as * the current gp. * * In the artificial example, we also rely on the compiler/linker * NOT reordering code layout. We depend on saxpy2() being just * after saxpy(). * */ fd = (struct fd *)saxpy; range_start = fd->addr; fd = (struct fd *)saxpy2; range_end = fd->addr; memset(pc, 0, sizeof(pc)); memset(pd, 0, sizeof(pd)); memset(ctx, 0, sizeof(ctx)); memset(ibrs,0, sizeof(ibrs)); memset(&load_args,0, sizeof(load_args)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&ita2_inp,0, sizeof(ita2_inp)); memset(&ita2_outp,0, sizeof(ita2_outp)); /* * find requested event */ p = event_list; for (i=0; p->event_name ; i++, p++) { if (pfm_find_event(p->event_name, &inp.pfp_events[i].event) != PFMLIB_SUCCESS) { fatal_error("cannot find %s event\n", p->event_name); } } /* * set the privilege mode: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = i; /* * We use the library to figure out how to program the debug registers * to cover the data range we are interested in. The rr_end parameter * must point to the byte after the last element of the range (C-style range). * * Because of the masking mechanism and therefore alignment constraints used to implement * this feature, it may not be possible to exactly cover a given range. It may be that * the coverage exceeds the desired range. So it is possible to capture noise if * the surrounding addresses are also heavily used. You can figure out by how much the * actual range is off compared to the requested range by checking the rr_soff and rr_eoff * fields on return from the library call. * * Upon return, the rr_dbr array is programmed and the number of debug registers (not pairs) * used to cover the range is in rr_nbr_used. * * In the case of code range restriction on Itanium 2, the library will try to use the fine * mode first and then it will default to using multiple pairs to cover the range. */ ita2_inp.pfp_ita2_irange.rr_used = 1; /* indicate we use code range restriction */ ita2_inp.pfp_ita2_irange.rr_limits[0].rr_start = range_start; ita2_inp.pfp_ita2_irange.rr_limits[0].rr_end = range_end; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, &ita2_inp, &outp, &ita2_outp)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); } /* * print offsets */ printf("code range : [0x%016lx-0x%016lx)\n" "start_offset:-0x%lx end_offset:+0x%lx\n" "%d pairs of debug registers used\n", range_start, range_end, ita2_outp.pfp_ita2_irange.rr_infos[0].rr_soff, ita2_outp.pfp_ita2_irange.rr_infos[0].rr_eoff, ita2_outp.pfp_ita2_irange.rr_nbr_used >> 1); /* * now create the context for self monitoring/per-task */ if (perfmonctl(0, PFM_CREATE_CONTEXT, ctx, 1) == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * extract our file descriptor */ id = ctx[0].ctx_fd; /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events cause extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * the PMC controlling the event ALWAYS come first, that's why this loop * is safe even when extra PMC are needed to support a particular event. */ for (i=0; i < inp.pfp_event_count; i++) { pd[i].reg_num = pc[i].reg_num; } /* * propagate the setup for the debug registers from the library to the arguments * to the perfmonctl() syscall. The library does not know the type of the syscall * anymore. */ for (i=0; i < ita2_outp.pfp_ita2_irange.rr_nbr_used; i++) { ibrs[i].dbreg_num = ita2_outp.pfp_ita2_irange.rr_br[i].reg_num; ibrs[i].dbreg_value = ita2_outp.pfp_ita2_irange.rr_br[i].reg_value; } /* * Program the code debug registers. * * IMPORTANT: programming the debug register MUST always be done before the PMCs * otherwise the kernel will fail on PFM_WRITE_PMCS. This is for security reasons. */ if (perfmonctl(id, PFM_WRITE_IBRS, ibrs, ita2_outp.pfp_ita2_irange.rr_nbr_used) == -1) { fatal_error("child: perfmonctl error PFM_WRITE_IBRS errno %d\n",errno); } /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more than coutning monitors. */ if (perfmonctl(id, PFM_WRITE_PMCS, pc, outp.pfp_pmc_count) == -1) { fatal_error("child: perfmonctl error PFM_WRITE_PMCS errno %d\n",errno); } if (perfmonctl(id, PFM_WRITE_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error("child: perfmonctl error PFM_WRITE_PMDS errno %d\n",errno); } /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = getpid(); if (perfmonctl(id, PFM_LOAD_CONTEXT, &load_args, 1) == -1) { fatal_error("perfmonctl error PFM_LOAD_CONTEXT errno %d\n",errno); } /* * Let's roll now. * * We run two distinct copies of the same function but we restrict measurement * to the first one (saxpy). Therefore the expected count is half what you would * get if code range restriction was not used. The core loop in both case uses * two floating point operation per iteration. */ pfm_self_start(id); do_test(); pfm_self_stop(id); /* * now read the results */ if (perfmonctl(id, PFM_READ_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error( "perfmonctl error READ_PMDS errno %d\n",errno); } /* * print the results * * It is important to realize, that the first event we specified may not * be in PMD4. Not all events can be measured by any monitor. That's why * we need to use the pc[] array to figure out where event i was allocated. */ for (i=0; i < inp.pfp_event_count; i++) { pfm_get_full_event_name(&inp.pfp_events[i], name, MAX_EVT_NAME_LEN); printf("PMD%u %20lu %s (expected %lu)\n", pd[i].reg_num, pd[i].reg_value, name, event_list[i].expected_value); } /* * let's stop this now */ close(id); return 0; } papi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/Makefile0000644000307100002310000000465313013651447022006 0ustar yarkhangraduate# # Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. # Contributed by Stephane Eranian # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies # of the Software, and to permit persons to whom the Software is furnished to do so, # subject to the following conditions: # # The above copyright notice and this permission notice shall be included in all # copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, # INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A # PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT # HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE # OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # # This file is part of libpfm, a performance monitoring support library for # applications on Linux. # # # IMPORTANT: compatibility examples are meant FOR IA-64 host ONLY! # TOPDIR := $(shell if [ "$$PWD" != "" ]; then echo $$PWD; else pwd; fi)/.. include ../config.mk include ../rules.mk CFLAGS += -pthread LDFLAGS+=-static LIBS += -lm INCDIR=-I$(PFMINCDIR) TARGETS=self task task_attach task_attach_timeout syst \ notify_self notify_self2 notify_self3 \ whichpmu showreset multiplex\ task_smpl notify_self_fork SRCS +=ita_rr.c ita_irr.c ita_opcode.c ita_btb.c ita_dear.c TARGETS +=ita_rr ita_irr ita_opcode ita_btb ita_dear SRCS +=ita2_opcode.c ita2_rr.c ita2_irr.c ita2_dear.c TARGETS +=ita2_dear ita2_btb ita2_opcode ita2_rr ita2_irr SRCS +=mont_opcode.c mont_rr.c mont_irr.c mont_dear.c mont_etb.c TARGETS +=mont_dear mont_opcode mont_rr mont_irr mont_etb PFMLIB=$(PFMLIBDIR)/libpfm.a all: $(TARGETS) notify_self2.o: notify_self2.c $(CC) $(INCDIR) $(CFLAGS) -D_GNU_SOURCE -c $*.c $(TARGETS): %:%.o $(PFMLIB) $(CC) -o $@ $(CFLAGS) $(LDFLAGS) $^ $(LIBS) clean: $(RM) -f *.o $(TARGETS) *~ distclean: clean depend: $(MKDEP) $(INCDIR) $(CFLAGS) $(SRCS) # # examples are installed as part of the RPM install, typically in /usr/share/doc/libpfm-X.Y/ # papi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/ita2_dear.c0000644000307100002310000002657113013651447022347 0ustar yarkhangraduate/* * ita2_dear.c - example of how use the D-EAR with the Itanium 2 PMU * * Copyright (c) 2003-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #include #include #include #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 #define MAX_PMU_NAME_LEN 32 #define SMPL_PERIOD (40) #define EVENT_NAME "data_ear_cache_lat4" #define M_PMD(x) (1UL<<(x)) #define DEAR_REGS_MASK (M_PMD(2)|M_PMD(3)|M_PMD(17)) typedef pfm_default_smpl_hdr_t dear_hdr_t; typedef pfm_default_smpl_entry_t dear_entry_t; typedef pfm_default_smpl_ctx_arg_t dear_ctx_t; #define DEAR_FMT_UUID PFM_DEFAULT_SMPL_UUID static pfm_uuid_t buf_fmt_id = DEAR_FMT_UUID; static void *smpl_vaddr; static unsigned long entry_size; static int id; #if defined(__ECC) && defined(__INTEL_COMPILER) /* if you do not have this file, your compiler is too old */ #include #define hweight64(x) _m64_popcnt(x) #elif defined(__GNUC__) static __inline__ int hweight64 (unsigned long x) { unsigned long result; __asm__ ("popcnt %0=%1" : "=r" (result) : "r" (x)); return (int)result; } #else #error "you need to provide inline assembly from your compiler" #endif long do_test(unsigned long size) { unsigned long i, sum = 0; int *array; printf("buffer size %.1fMB\n", (size*sizeof(int))/1024.0); array = (int *)malloc(size * sizeof(int)); if (array == NULL ) { printf("line = %d No memory available!\n", __LINE__); exit(1); } for(i=0; ihdr_overflows <= last_ovfl && last_ovfl != ~0UL) { printf("skipping identical set of samples %lu <= %lu\n", hdr->hdr_overflows, last_ovfl); return; } pos = (unsigned long)(hdr+1); /* * walk through all the entries recored in the buffer */ for(i=0; i < hdr->hdr_count; i++) { ret = 0; ent = (dear_entry_t *)pos; /* * print entry header */ safe_printf("Entry %ld PID:%d CPU:%d STAMP:0x%lx IIP:0x%016lx\n", smpl_entry++, ent->pid, ent->cpu, ent->tstamp, ent->ip); /* * point to first recorded register (always contiguous with entry header) */ reg = (pfm_ita2_pmd_reg_t*)(ent+1); safe_printf("PMD2 : 0x%016lx\n", reg->pmd_val); reg++; safe_printf("PMD3 : 0x%016lx, latency %u\n", reg->pmd_val, reg->pmd3_ita2_reg.dear_latency); reg++; safe_printf("PMD17: 0x%016lx, valid %c, address 0x%016lx\n", reg->pmd_val, reg->pmd17_ita2_reg.dear_vl ? 'Y': 'N', (reg->pmd17_ita2_reg.dear_iaddr << 4) | (unsigned long)reg->pmd17_ita2_reg.dear_slot); /* * move to next entry */ pos += entry_size; } } static void overflow_handler(int n, struct siginfo *info, struct sigcontext *sc) { /* dangerous */ printf("Notification received\n"); process_smpl_buffer(); /* * And resume monitoring */ if (perfmonctl(id, PFM_RESTART,NULL, 0) == -1) { perror("PFM_RESTART"); exit(1); } } int main(void) { pfarg_reg_t pd[NUM_PMDS]; pfarg_reg_t pc[NUM_PMCS]; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_event_t ev; dear_ctx_t ctx[1]; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; struct sigaction act; unsigned int i; int ret, type = 0; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) { fatal_error("Can't initialize library\n"); } /* * Let's make sure we run this on the right CPU */ pfm_get_pmu_type(&type); if (type != PFMLIB_ITANIUM2_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with %s PMU\n", model); } /* * Install the overflow handler (SIGIO) */ memset(&act, 0, sizeof(act)); act.sa_handler = (sig_t)overflow_handler; sigaction (SIGIO, &act, 0); /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 1; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); memset(pd, 0, sizeof(pd)); memset(pc, 0, sizeof(pc)); memset(pc, 0, sizeof(pc)); memset(ctx, 0, sizeof(ctx)); memset(&load_args, 0, sizeof(load_args)); /* * prepare parameters to library. we don't use any Itanium * specific features here. so the pfp_model is NULL. */ memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); /* * To count the number of occurence of this instruction, we must * program a counting monitor with the IA64_TAGGED_INST_RETIRED_PMC8 * event. */ if (pfm_find_full_event(EVENT_NAME, &ev) != PFMLIB_SUCCESS) { fatal_error("cannot find event %s\n", EVENT_NAME); } /* * set the (global) privilege mode: * PFM_PLM0 : kernel level only */ inp.pfp_dfl_plm = PFM_PLM3|PFM_PLM0; /* * how many counters we use */ inp.pfp_event_count = 1; /* * propagate the event descriptor */ inp.pfp_events[0] = ev; /* * let the library figure out the values for the PMCS * * We use all global settings for this EAR. */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); } /* * prepare context structure. * * format specific parameters MUST be concatenated to the regular * pfarg_context_t structure. For convenience, the default sampling * format provides a data structure that already combines the pfarg_context_t * with what is needed fot this format. */ /* * We initialize the format specific information. * The format is identified by its UUID which must be copied * into the ctx_buf_fmt_id field. */ memcpy(ctx[0].ctx_arg.ctx_smpl_buf_id, buf_fmt_id, sizeof(pfm_uuid_t)); /* * the size of the buffer is indicated in bytes (not entries). * * The kernel will record into the buffer up to a certain point. * No partial samples are ever recorded. */ ctx[0].buf_arg.buf_size = 4096; /* * now create the context for self monitoring/per-task */ if (perfmonctl(0, PFM_CREATE_CONTEXT, ctx, 1) == -1 ) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * extract the file descriptor we will use to * identify this newly created context */ id = ctx[0].ctx_arg.ctx_fd; printf("Sampling buffer mapped at %p\n", ctx[0].ctx_arg.ctx_smpl_vaddr); smpl_vaddr = ctx[0].ctx_arg.ctx_smpl_vaddr; /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events causes extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * the PMC controlling the event ALWAYS come first, that's why this loop * is safe even when extra PMC are needed to support a particular event. */ for (i=0; i < inp.pfp_event_count; i++) { pd[i].reg_num = pc[i].reg_num; } /* * indicate we want notification when buffer is full */ pc[0].reg_flags |= PFM_REGFL_OVFL_NOTIFY; /* * indicate which PMD to include in the sample */ pc[0].reg_smpl_pmds[0] = DEAR_REGS_MASK; /* * compute size of each sample: fixed-size header + all our DEAR regs */ entry_size = sizeof(dear_entry_t)+(hweight64(DEAR_REGS_MASK)<<3); /* * initialize the PMD and the sampling period */ pd[0].reg_value = (~0UL) - SMPL_PERIOD +1; pd[0].reg_long_reset = (~0UL) - SMPL_PERIOD +1; pd[0].reg_short_reset = (~0UL) - SMPL_PERIOD +1; /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more thann coutning monitors. */ if (perfmonctl(id, PFM_WRITE_PMCS, pc, outp.pfp_pmc_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMCS errno %d\n",errno); } if (perfmonctl(id, PFM_WRITE_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMDS errno %d\n",errno); } /* * attach context to stopped task */ load_args.load_pid = getpid(); if (perfmonctl(id, PFM_LOAD_CONTEXT, &load_args, 1) == -1) { fatal_error("perfmonctl error PFM_LOAD_CONTEXT errno %d\n",errno); } /* * setup asynchronous notification on the file descriptor */ ret = fcntl(id, F_SETFL, fcntl(id, F_GETFL, 0) | O_ASYNC); if (ret == -1) { fatal_error("cannot set ASYNC: %s\n", strerror(errno)); } /* * get ownership of the descriptor */ ret = fcntl(id, F_SETOWN, getpid()); if (ret == -1) { fatal_error("cannot setown: %s\n", strerror(errno)); } /* * Let's roll now. */ pfm_self_start(id); do_test(10000); pfm_self_stop(id); /* * We must call the processing routine to cover the last entries recorded * in the sampling buffer, i.e. which may not be full */ process_smpl_buffer(); /* * let's stop this now */ close(id); return 0; } papi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/task.c0000644000307100002310000001751413013651447021454 0ustar yarkhangraduate/* * task.c - example of a task monitoring another one * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } int child(char **arg) { /* * will cause the program to stop before executing the first * user level instruction. We can only attach (load) a context * if the task is in the STOPPED state. */ ptrace(PTRACE_TRACEME, 0, NULL, NULL); /* * execute the requested command */ execvp(arg[0], arg); fatal_error("cannot exec: %s\n", arg[0]); /* not reached */ } int parent(char **arg) { pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfarg_context_t ctx[1]; pfarg_reg_t pc[NUM_PMCS]; pfarg_reg_t pd[NUM_PMDS]; pfarg_load_t load_args; unsigned int i, num_counters; int status, ret; int ctx_fd; pid_t pid; char name[MAX_EVT_NAME_LEN]; memset(pc, 0, sizeof(ctx)); memset(pd, 0, sizeof(ctx)); memset(ctx, 0, sizeof(ctx)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&load_args,0, sizeof(load_args)); pfm_get_num_counters(&num_counters); if (pfm_get_cycle_event(&inp.pfp_events[0]) != PFMLIB_SUCCESS) fatal_error("cannot find cycle event\n"); if (pfm_get_inst_retired_event(&inp.pfp_events[1]) != PFMLIB_SUCCESS) fatal_error("cannot find inst retired event\n"); i = 2; if (num_counters < i) { i = num_counters; printf("too many events provided (max=%d events), using first %d event(s)\n", num_counters, i); } /* * set the privilege mode: * PFM_PLM3 : user level * PFM_PLM0 : kernel level */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = i; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); } /* * now create a context. we will later attach it to the task we are creating. */ if (perfmonctl(0, PFM_CREATE_CONTEXT, ctx, 1) == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * extract the identifier for our context */ ctx_fd = ctx[0].ctx_fd; /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events causes extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * the PMC controlling the event ALWAYS come first, that's why this loop * is safe even when extra PMC are needed to support a particular event. */ for (i=0; i < inp.pfp_event_count; i++) { pd[i].reg_num = pc[i].reg_num; } /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more thann counting monitors. */ if (perfmonctl(ctx_fd, PFM_WRITE_PMCS, pc, outp.pfp_pmc_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMCS errno %d\n",errno); } if (perfmonctl(ctx_fd, PFM_WRITE_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMDS errno %d\n",errno); } /* * Create the child task */ if ((pid=fork()) == -1) fatal_error("Cannot fork process\n"); /* * and launch the child code */ if (pid == 0) exit(child(arg)); /* * wait for the child to exec */ waitpid(pid, &status, WUNTRACED); /* * check if process exited early */ if (WIFEXITED(status)) { fatal_error("command %s exited too early with status %d\n", arg[0], WEXITSTATUS(status)); } /* * the task is stopped at this point */ /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = pid; if (perfmonctl(ctx_fd, PFM_LOAD_CONTEXT, &load_args, 1) == -1) { fatal_error("perfmonctl error PFM_LOAD_CONTEXT errno %d\n",errno); } /* * activate monitoring. The task is still STOPPED at this point. Monitoring * will not take effect until the execution of the task is resumed. */ if (perfmonctl(ctx_fd, PFM_START, NULL, 0) == -1) { fatal_error("perfmonctl error PFM_START errno %d\n",errno); } /* * now resume execution of the task, effectively activating * monitoring. */ ptrace(PTRACE_DETACH, pid, NULL, 0); /* * now the task is running */ /* * simply wait for completion */ waitpid(pid, &status, 0); /* * the task has disappeared at this point but our context is still * present and contains all the latest counts. */ /* * now simply read the results. */ if (perfmonctl(ctx_fd, PFM_READ_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error("perfmonctl error READ_PMDS errno %d\n",errno); return -1; } /* * print the results * * It is important to realize, that the first event we specified may not * be in PMD4. Not all events can be measured by any monitor. That's why * we need to use the pc[] array to figure out where event i was allocated. * */ for (i=0; i < inp.pfp_event_count; i++) { pfm_get_full_event_name(&inp.pfp_events[i], name, MAX_EVT_NAME_LEN); printf("PMD%u %20"PRIu64" %s\n", pd[i].reg_num, pd[i].reg_value, name); } /* * free the context */ close(ctx_fd); return 0; } int main(int argc, char **argv) { pfmlib_options_t pfmlib_options; if (argc < 2) { fatal_error("You must specify a command to execute\n"); } /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) { printf("Can't initialize library\n"); exit(1); } /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); return parent(argv+1); } papi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/multiplex.c0000644000307100002310000004327513013651447022540 0ustar yarkhangraduate/* * multiplex.c - example of user-level event multiplexing * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * This file is part of pfmon, a sample tool to measure performance * of applications on Linux/ia64. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA * 02111-1307 USA */ #ifndef _GNU_SOURCE #define _GNU_SOURCE /* for getline */ #endif #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define MULTIPLEX_VERSION "0.1" #define MIN_FULL_PERIODS 100 #define SMPL_FREQ_IN_HZ 100 #define NUM_PMCS PMU_MAX_PMCS #define NUM_PMDS PMU_MAX_PMDS #define MAX_NUM_COUNTERS 32 #define MAX_PMU_NAME_LEN 32 typedef struct { struct { int opt_plm; /* which privilege level to monitor (more than one possible) */ int opt_debug; /* print debug information */ int opt_verbose; /* verbose output */ int opt_us_format; /* print large numbers with comma for thousands */ } program_opt_flags; unsigned long max_counters; /* maximum number of counter for the platform */ unsigned long smpl_freq; unsigned long smpl_period; unsigned long cpu_mhz; unsigned long full_periods; } program_options_t; #define opt_plm program_opt_flags.opt_plm #define opt_debug program_opt_flags.opt_debug #define opt_verbose program_opt_flags.opt_verbose #define opt_us_format program_opt_flags.opt_us_format typedef struct { char *event_names[MAX_NUM_COUNTERS]; pfmlib_input_param_t pfm_inp; pfmlib_output_param_t pfm_outp; pfarg_reg_t pmcs[MAX_NUM_COUNTERS]; pfarg_reg_t pmds[MAX_NUM_COUNTERS]; unsigned long values[MAX_NUM_COUNTERS]; unsigned long n_runs; unsigned int n_counters; unsigned int n_pmcs; } event_set_t; typedef int pfm_ctxid_t; static pfm_ctxid_t ctxid; static int current_set; static program_options_t options; /* * NO MORE THAN MAX_COUNTERS-1 (3) EVENTS PER SET */ static event_set_t events[]={ { {"BACK_END_BUBBLE_ALL","BACK_END_BUBBLE_L1D_FPU_RSE","BE_EXE_BUBBLE_ALL", },}, { {"BACK_END_BUBBLE_FE", "BACK_END_BUBBLE_L1D_FPU_RSE", "BE_RSE_BUBBLE_ALL",},}, { {"BE_L1D_FPU_BUBBLE_ALL", "BE_L1D_FPU_BUBBLE_L1D", "BE_EXE_BUBBLE_FRALL",},}, { {"BE_EXE_BUBBLE_GRALL", "BE_EXE_BUBBLE_GRGR", },}, { {"NOPS_RETIRED", "CPU_CYCLES", },} }; #define N_SETS (sizeof(events)/sizeof(event_set_t)) static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void vbprintf(char *fmt, ...) { va_list ap; if (options.opt_verbose == 0) return; va_start(ap, fmt); vprintf(fmt, ap); va_end(ap); } static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } static unsigned long get_cpu_speed(void) { FILE *fp1; unsigned long f = 0; char buffer[128], *p, *value; memset(buffer, 0, sizeof(buffer)); fp1 = fopen("/proc/cpuinfo", "r"); if (fp1 == NULL) return 0; for (;;) { buffer[0] = '\0'; p = fgets(buffer, 127, fp1); if (p == NULL) goto end; /* skip blank lines */ if (*p == '\n') continue; p = strchr(buffer, ':'); if (p == NULL) goto end; /* * p+2: +1 = space, +2= firt character * strlen()-1 gets rid of \n */ *p = '\0'; value = p+2; value[strlen(value)-1] = '\0'; if (!strncmp("cpu MHz", buffer, 7)) { sscanf(value, "%lu", &f); goto end; } } end: fclose(fp1); return f; } static void update_set(pfm_ctxid_t ctxid, int set_idx) { event_set_t *cset = events + set_idx; int count; int ret; int i; /* * we do not read the last counter (cpu_cycles) to avoid overwriting * the reg_value field which will be used for next round * * We need to retry the read in case we get EBUSY because it means that * the child task context is not yet available from inspection by PFM_READ_PMDS. * */ count = cset->n_counters - 1; ret = perfmonctl(ctxid, PFM_READ_PMDS, cset->pmds, count); if (ret == -1) { fatal_error("update_set reading set %d: %s\n", set_idx, strerror(errno)); } /* update counts for this set */ for (i=0; i < count; i++) { cset->values[i] += cset->pmds[i].reg_value; cset->pmds[i].reg_value = 0UL; /* reset for next round */ } } #if 0 static void update_last_set(pfm_ctxid_t ctxid, int set_idx) { event_set_t *cset = events + set_idx; unsigned long cycles; int i; /* * this time we read ALL the counters (including CPU_CYCLES) because we * need it to scale the last period */ if (perfmonctl(ctxid, PFM_READ_PMDS, cset->pmds, cset->n_counters) == -1) { fatal_error("update_last_set reading set %d\n", set_idx); } cycles = ~0UL - cset->pmds[cset->n_counters-1].reg_value; printf("last period = %4.1f%% of full period\n", (cycles*100.0)/options.smpl_period); /* this time we scale the value to the length of this last period */ for (i=0; i < cset->n_counters-1; i++) { cset->values[i] += (cset->pmds[i].reg_value*cycles)/options.smpl_period; } } #endif int child(char **arg) { ptrace(PTRACE_TRACEME, 0, NULL, NULL); execvp(arg[0], arg); /* not reached */ exit(1); } static void dec2sep(char *str2, char *str, char sep) { int i, l, b, j, c=0; l = strlen(str2); if (l <= 3) { strcpy(str, str2); return; } b = l + l /3 - (l%3 == 0); /* l%3=correction to avoid extraneous comma at the end */ for(i=l, j=0; i >= 0; i--, j++) { if (j) c++; str[b-j] = str2[i]; if (c == 3) { str[b-++j] = sep; c = 0; } } } static void print_results(void) { unsigned int i, j; event_set_t *e; char tmp1[32], tmp2[32]; char mtotal_str[32], *mtotal; char stotal_str[32], *stotal; /* * print the results * * It is important to realize, that the first event we specified may not * be in PMD4. Not all events can be measured by any monitor. That's why * we need to use the pc[] array to figure out where event i was allocated. * */ printf("%lu Hz period = %lu cycles @ %lu Mhz\n", options.smpl_freq, options.smpl_period, options.cpu_mhz); printf("%lu full periods\n", options.full_periods); printf("%lu event sets\n", N_SETS); printf("set measured total #runs scaled total event name\n"); printf("-------------------------------------------------------------------\n"); for (i=0; i < N_SETS; i++) { e = events + i; for(j=0; j < e->n_counters-1; j++) { sprintf(tmp1, "%"PRIu64, e->values[j]); if (options.opt_us_format) { dec2sep(tmp1, mtotal_str, ','); mtotal = mtotal_str; } else { mtotal = tmp1; } sprintf(tmp2, "%"PRIu64, (e->values[j]*options.full_periods)/e->n_runs); /* stupid scaling */ if (options.opt_us_format) { dec2sep(tmp2, stotal_str, ','); stotal = stotal_str; } else { stotal = tmp2; } printf("%03d: %20s %8"PRIu64" %20s %s\n", i, mtotal, e->n_runs, stotal, e->event_names[j]); } } } static void switch_sets(void) { event_set_t *cset; update_set(ctxid, current_set); current_set = (current_set+1) % N_SETS; cset = events+current_set; cset->n_runs++; vbprintf("starting run %lu for set %d n_pmcs=%d pmd=%"PRIu64"\n", cset->n_runs, current_set, cset->n_pmcs, cset->pmds[cset->n_counters-1].reg_value); /* * if one set as less events than another one, the left-over events will continue * to count for nothing. That's fine because we will restore their values when * the correspinding set is reloaded */ if (perfmonctl(ctxid, PFM_WRITE_PMCS, cset->pmcs, cset->n_pmcs) == -1) { fatal_error("overflow handler writing pmcs set %d : %d\n", current_set, errno); } if (perfmonctl(ctxid, PFM_WRITE_PMDS, cset->pmds, cset->n_counters) == -1) { fatal_error("overflow handler writing pmds set %d\n", current_set); } options.full_periods++; if (perfmonctl(ctxid, PFM_RESTART,NULL, 0) == -1) { perror("PFM_RESTART"); exit(1); } } int parent(char **arg) { event_set_t *e; pfarg_context_t ctx[1]; pfarg_load_t load_arg; event_set_t *cset; pfm_msg_t msg; struct pollfd ctx_pollfd; pfmlib_regmask_t impl_counters, used_pmcs; pfmlib_event_t cycle_event; unsigned int i, j, k, l,idx; int r, status, ret; unsigned int max_counters, allowed_counters; pid_t pid; pfm_get_num_counters(&max_counters); if (max_counters < 2) fatal_error("not enough counter to do anything meaningful\n"); allowed_counters = max_counters-1; /* reserve one slot for our sampling period */ memset(&used_pmcs, 0, sizeof(used_pmcs)); memset(&impl_counters, 0, sizeof(impl_counters)); pfm_get_impl_counters(&impl_counters); memset(ctx, 0, sizeof(ctx)); memset(&load_arg, 0, sizeof(load_arg)); if (pfm_get_cycle_event(&cycle_event) != PFMLIB_SUCCESS) { fatal_error("Cannot find cycle event\n"); } options.smpl_period = (options.cpu_mhz*1000000)/options.smpl_freq; vbprintf("%lu Hz period = %lu cycles @ %lu Mhz\n", options.smpl_freq, options.smpl_period, options.cpu_mhz); for (i=0; i < N_SETS; i++) { e = events+i; memset(&e->pfm_inp,0, sizeof(pfmlib_input_param_t)); memset(&e->pfm_outp,0, sizeof(pfmlib_output_param_t)); for(j=0; e->event_names[j] && j < allowed_counters; j++) { if (pfm_find_event(e->event_names[j], &idx) != PFMLIB_SUCCESS) { fatal_error("Cannot find %s event\n", e->event_names[j]); } e->pfm_inp.pfp_events[j].event = idx; } if (e->event_names[j]) { fatal_error("cannot have more than %d events per set (CPU_CYCLES uses 1 slot)\n", allowed_counters); } e->pfm_inp.pfp_events[j] = cycle_event; e->pfm_inp.pfp_event_count = j+1; e->pfm_inp.pfp_dfl_plm = options.opt_plm; e->n_pmcs = j+1; /* used pmcs +1=sampling period */ e->n_counters = j+1; /* used pmd/pmc counter pairs +1=sampling period */ vbprintf("PMU programming for set %d\n", i); if ((ret=pfm_dispatch_events(&e->pfm_inp, NULL, &e->pfm_outp, NULL)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events for set %d: %s\n", i, pfm_strerror(ret)); } /* * propagate from libpfm to kernel data structures */ for (j=0; j < e->n_counters; j++) { e->pmcs[j].reg_num = e->pfm_outp.pfp_pmcs[j].reg_num; e->pmcs[j].reg_value = e->pfm_outp.pfp_pmcs[j].reg_value; e->pmds[j].reg_num = e->pmcs[j].reg_num; pfm_regmask_set(&used_pmcs, e->pmcs[j].reg_num); } /* last counter contains our sampling counter */ e->pmcs[j-1].reg_flags |= PFM_REGFL_OVFL_NOTIFY; e->pmds[j-1].reg_value = (~0) - options.smpl_period + 1; e->pmds[j-1].reg_short_reset = (~0) - options.smpl_period + 1; e->pmds[j-1].reg_long_reset = (~0) - options.smpl_period + 1; for (j=0; j < e->n_counters-1; j++) { vbprintf("[pmd[%u]=0x%"PRIx64"/0x%"PRIx64"/0x%"PRIx64"]\n", e->pmds[j].reg_num, e->pmds[j].reg_value, e->pmds[j].reg_short_reset, e->pmds[j].reg_long_reset); } vbprintf("[pmd[%u]=0x%"PRIx64"/0x%"PRIx64"/0x%"PRIx64"]\n", e->pmds[j].reg_num, e->pmds[j].reg_value, e->pmds[j].reg_short_reset, e->pmds[j].reg_long_reset); /* * we blank the unused pmcs to make sure every set uses all the counters, i.e., * cannot overflow due to some previous sampling periods that uses a counter * beyond the number used by the current set */ for(j=0, k=e->n_pmcs, l=0; l < max_counters; j++) { if (pfm_regmask_isset(&impl_counters, j) == 0) continue; l++; if (pfm_regmask_isset(&used_pmcs, j)) continue; e->pmcs[k].reg_num = j; e->pmcs[k].reg_value = 0UL; k++; } e->n_pmcs= k; } /* * point to first set of counters */ current_set = 0; /* * we block on counter overflow */ ctx[0].ctx_flags = PFM_FL_NOTIFY_BLOCK; /* * attach the context to the task */ if (perfmonctl(0, PFM_CREATE_CONTEXT, ctx, 1) == -1 ) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * extract context id */ ctxid = ctx[0].ctx_fd; /* * set close-on-exec to ensure we will be getting the PFM_END_MSG, i.e., * fd not visible to child. */ if (fcntl(ctxid, F_SETFD, FD_CLOEXEC)) fatal_error("cannot set CLOEXEC: %s\n", strerror(errno)); ctx_pollfd.fd = ctxid; ctx_pollfd.events = POLLIN; cset = events + current_set; cset->n_runs++; /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more thann coutning monitors. */ if (perfmonctl(ctxid, PFM_WRITE_PMCS, cset->pmcs, cset->n_pmcs) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMCS errno %d\n",errno); } /* * initialize the PMDs */ if (perfmonctl(ctxid, PFM_WRITE_PMDS, cset->pmds, cset->n_counters) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMDS errno %d\n",errno); } /* * now launch the child code */ if ((pid= fork()) == -1) fatal_error("Cannot fork process\n"); if (pid == 0) exit(child(arg)); /* * wait for the child to exec */ r = waitpid(pid, &status, WUNTRACED); if (r < 0 || WIFEXITED(status)) fatal_error("error command already terminated, exit code %d\n", WEXITSTATUS(status)); vbprintf("child created and stopped\n"); /* * the child is stopped, load context */ load_arg.load_pid = pid; if (perfmonctl(ctxid, PFM_LOAD_CONTEXT, &load_arg, 1) == -1) { fatal_error("perfmonctl error PFM_LOAD_CONTEXT errno %d\n",errno); } /* * make sure monitoring will be activated when the execution is resumed */ if (perfmonctl(ctxid, PFM_START, NULL, 0) == -1) { fatal_error("perfmonctl error PFM_START errno %d\n",errno); } /* * resume execution */ ptrace(PTRACE_DETACH, pid, NULL, 0); /* * mainloop */ for(;;) { ret = read(ctxid, &msg, sizeof(msg)); if (ret < 0) break; switch(msg.type) { case PFM_MSG_OVFL: switch_sets(); break; case PFM_MSG_END: goto finish_line; default: printf("unknown message type %d\n", msg.type); } } finish_line: if (options.full_periods < MIN_FULL_PERIODS) { fatal_error("Not enough periods (%lu) to print results\n", options.full_periods); } //update_last_set(pid, current_set); waitpid(pid, &status, 0); print_results(); if (ctxid) close(ctxid); return 0; } static struct option multiplex_options[]={ { "help", 0, 0, 1}, { "freq", 1, 0, 2 }, { "kernel-level", 0, 0, 3 }, { "user-level", 0, 0, 4 }, { "version", 0, 0, 5 }, { "verbose", 0, &options.opt_verbose, 1 }, { "debug", 0, &options.opt_debug, 1 }, { "us-counter-format", 0, &options.opt_us_format, 1}, { 0, 0, 0, 0} }; static void print_usage(char **argv) { printf("usage: %s [OPTIONS]... COMMAND\n", argv[0]); printf( "-h, --help\t\t\t\tdisplay this help and exit\n" "-V, --version\t\t\t\toutput version information and exit\n" "-u, --user-level\t\t\tmonitor at the user level for all events\n" "-k, --kernel-level\t\t\tmonitor at the kernel level for all events\n" "-c, --us-counter-format\tprint large counts with comma for thousands\n" "--freq=number\t\t\t\tset sampling frequency in Hz\n" "--verbose\t\t\t\tprint more information during execution\n" ); } int main(int argc, char **argv) { char *endptr = NULL; pfmlib_options_t pfmlib_options; int c, type; while ((c=getopt_long(argc, argv,"+vhkuVc", multiplex_options, 0)) != -1) { switch(c) { case 0: continue; /* fast path for options */ case 1: print_usage(argv); exit(0); case 'v': options.opt_verbose = 1; break; case 'c': options.opt_us_format = 1; break; case 2: case 'V': if (options.smpl_freq) fatal_error("sampling frequency set twice\n"); options.smpl_freq = strtoul(optarg, &endptr, 10); if (*endptr != '\0') fatal_error("invalid freqyency: %s\n", optarg); break; case 3: case 'k': options.opt_plm |= PFM_PLM0; break; case 4: case 'u': options.opt_plm |= PFM_PLM3; break; case 5: printf("multiplex version " MULTIPLEX_VERSION " Date: " __DATE__ "\n" "Copyright (C) 2002 Hewlett-Packard Company\n"); exit(0); default: fatal_error(""); /* just quit silently now */ } } if (optind == argc) fatal_error("you need to specify a command to measure\n"); /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) { fatal_error("can't initialize library\n"); } /* * Let's make sure we run this on the right CPU family */ pfm_get_pmu_type(&type); if (type != PFMLIB_ITANIUM2_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with %s PMU\n", model); } if ((options.cpu_mhz = get_cpu_speed()) == 0) { fatal_error("can't get CPU speed\n"); } if (options.smpl_freq == 0UL) options.smpl_freq = SMPL_FREQ_IN_HZ; if (options.opt_plm == 0) options.opt_plm = PFM_PLM3; /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = options.opt_verbose; /* set to 1 for verbose */ pfm_set_options(&pfmlib_options); return parent(argv+optind); } papi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/ita2_rr.c0000644000307100002310000002726613013651447022061 0ustar yarkhangraduate/* * ita2_rr.c - example of how to use data range restriction with the Itanium2 PMU * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #include #if defined(__ECC) && defined(__INTEL_COMPILER) /* if you do not have this file, your compiler is too old */ #include #define clear_psr_ac() __rum(1UL<<3) #elif defined(__GNUC__) static inline void clear_psr_ac(void) { __asm__ __volatile__("rum psr.ac;;" ::: "memory" ); } #else #error "You need to define clear_psr_ac() for your compiler" #endif #define TEST_DATA_COUNT 16 #define N_LOOP 100000000UL #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 #define MAX_PMU_NAME_LEN 32 /* * here we capture only misaligned_loads because it cannot * be measured with misaligned_stores_retired at the same time */ static char *event_list[]={ "misaligned_loads_retired", NULL }; typedef union { unsigned long l_tab[2]; unsigned int i_tab[4]; unsigned short s_tab[8]; unsigned char c_tab[16]; } test_data_t; static int do_test(test_data_t *data) { unsigned int *l, v; l = (unsigned int *)(data->c_tab+1); if (((unsigned long)l & 0x1) == 0) { printf("Data is not unaligned, can't run test\n"); return -1; } v = *l; v++; *l = v; return 0; } static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } int main(int argc, char **argv) { char **p; test_data_t *test_data, *test_data_fake; unsigned long range_start, range_end; int ret, type = 0; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_ita2_input_param_t ita2_inp; pfmlib_ita2_output_param_t ita2_outp; pfarg_reg_t pd[NUM_PMDS]; pfarg_reg_t pc[NUM_PMCS]; pfarg_dbreg_t dbrs[8]; pfarg_context_t ctx[1]; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; unsigned int i; int id; char name[MAX_EVT_NAME_LEN]; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) { fatal_error("Can't initialize library\n"); } /* * Let's make sure we run this on the right CPU family */ pfm_get_pmu_type(&type); if (type != PFMLIB_ITANIUM2_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with %s PMU\n", model); } /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 0; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); /* * now let's allocate the data structure we will be monitoring */ test_data = (test_data_t *)malloc(sizeof(test_data_t)*TEST_DATA_COUNT); if (test_data == NULL) { fatal_error("cannot allocate test data structure"); } test_data_fake = (test_data_t *)malloc(sizeof(test_data_t)*TEST_DATA_COUNT); if (test_data_fake == NULL) { fatal_error("cannot allocate test data structure"); } /* * Compute the range we are interested in */ range_start = (unsigned long)test_data; range_end = range_start + sizeof(test_data_t)*TEST_DATA_COUNT; memset(pd, 0, sizeof(pd)); memset(pc, 0, sizeof(pc)); memset(ctx, 0, sizeof(ctx)); memset(dbrs, 0, sizeof(dbrs)); memset(&load_args, 0, sizeof(load_args)); /* * prepare parameters to library. we don't use any Itanium * specific features here. so the pfp_model is NULL. */ memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&ita2_inp,0, sizeof(ita2_inp)); memset(&ita2_outp,0, sizeof(ita2_outp)); /* * find requested event */ p = event_list; for (i=0; *p ; i++, p++) { if (pfm_find_event(*p, &inp.pfp_events[i].event) != PFMLIB_SUCCESS) { fatal_error("Cannot find %s event\n", *p); } } /* * set the privilege mode: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = i; /* * We use the library to figure out how to program the debug registers * to cover the data range we are interested in. The rr_end parameter * must point to the byte after the last element of the range (C-style range). * * Because of the masking mechanism and therefore alignment constraints used to implement * this feature, it may not be possible to exactly cover a given range. It may be that * the coverage exceeds the desired range. So it is possible to capture noise if * the surrounding addresses are also heavily used. You can figure out by how much the * actual range is off compared to the requested range by checking the rr_soff and rr_eoff * fields in rr_infos on return from the library call. * * Upon return, the rr_dbr array is programmed and the number of debug registers (not pairs) * used to cover the range is in rr_nbr_used. */ ita2_inp.pfp_ita2_drange.rr_used = 1; ita2_inp.pfp_ita2_drange.rr_limits[0].rr_start = range_start; ita2_inp.pfp_ita2_drange.rr_limits[0].rr_end = range_end; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, &ita2_inp, &outp, &ita2_outp)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); } printf("data range : [0x%016lx-0x%016lx): %d pair of debug registers used\n" "start_offset:-0x%lx end_offset:+0x%lx\n", range_start, range_end, ita2_outp.pfp_ita2_drange.rr_nbr_used >> 1, ita2_outp.pfp_ita2_drange.rr_infos[0].rr_soff, ita2_outp.pfp_ita2_drange.rr_infos[0].rr_eoff); printf("fake data range: [0x%016lx-0x%016lx)\n", (unsigned long)test_data_fake, (unsigned long)test_data_fake+sizeof(test_data_t)*TEST_DATA_COUNT); /* * now create the context for self monitoring/per-task */ if (perfmonctl(0, PFM_CREATE_CONTEXT, ctx, 1) == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * extract the unique identifier for our context, a regular file descriptor */ id = ctx[0].ctx_fd; /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events causes extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * the PMC controlling the event ALWAYS come first, that's why this loop * is safe even when extra PMC are needed to support a particular event. */ for (i=0; i < inp.pfp_event_count; i++) { pd[i].reg_num = pc[i].reg_num; } /* * propagate the setup for the debug registers from the library to the arguments * to the perfmonctl() syscall. The library does not know the type of the syscall * anymore. */ for (i=0; i < ita2_outp.pfp_ita2_drange.rr_nbr_used; i++) { dbrs[i].dbreg_num = ita2_outp.pfp_ita2_drange.rr_br[i].reg_num; dbrs[i].dbreg_value = ita2_outp.pfp_ita2_drange.rr_br[i].reg_value; } /* * Program the data debug registers. * * IMPORTANT: programming the debug register MUST always be done before the PMCs * otherwise the kernel will fail on PFM_WRITE_PMCS. This is for security reasons. */ if (perfmonctl(id, PFM_WRITE_DBRS, dbrs, ita2_outp.pfp_ita2_drange.rr_nbr_used) == -1) { fatal_error( "child: perfmonctl error PFM_WRITE_DBRS errno %d\n",errno); } /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more than coutning monitors. */ if (perfmonctl(id, PFM_WRITE_PMCS, pc, outp.pfp_pmc_count) == -1) { fatal_error("child: perfmonctl error PFM_WRITE_PMCS errno %d\n",errno); } if (perfmonctl(id, PFM_WRITE_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error( "child: perfmonctl error PFM_WRITE_PMDS errno %d\n",errno); } /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = getpid(); if (perfmonctl(id, PFM_LOAD_CONTEXT, &load_args, 1) == -1) { fatal_error("perfmonctl error PFM_LOAD_CONTEXT errno %d\n",errno); } /* * Let's make sure that the hardware does the unaligned accesses (do not use the * kernel software handler otherwise the PMU won't see the unaligned fault). */ clear_psr_ac(); /* * Let's roll now. * * The idea behind this test is to have two dynamically allocated data structures * which are access in a unaligned fashion. But we want to capture only the unaligned * accesses on one of the two. So the debug registers are programmed to cover the * first one ONLY. Then we activate monotoring and access the two data structures. * This is an artificial example just to demonstrate how to use data address range * restrictions. */ pfm_self_start(id); for(i=0; i < N_LOOP; i++) { do_test(test_data); do_test(test_data_fake); } pfm_self_stop(id); /* * now read the results */ if (perfmonctl(id, PFM_READ_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error( "perfmonctl error READ_PMDS errno %d\n",errno); } /* * print the results * * It is important to realize, that the first event we specified may not * be in PMD4. Not all events can be measured by any monitor. That's why * we need to use the pc[] array to figure out where event i was allocated. * * For this example, we expect to see a value of 1 for misaligned loads. * But it can be two when the test_data and test_data_fake * are allocated very close from each other and the range created with the debug * registers is larger then test_data. * */ for (i=0; i < inp.pfp_event_count; i++) { pfm_get_full_event_name(&inp.pfp_events[i], name, MAX_EVT_NAME_LEN); printf("PMD%u %20lu %s (expected %lu)\n", pd[i].reg_num, pd[i].reg_value, name, N_LOOP); if (pd[i].reg_value != N_LOOP) { printf("error: Result should be 1 for %s\n", name); break; } } /* * let's stop this now */ close(id); free(test_data); free(test_data_fake); return 0; } papi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/ita_btb.c0000644000307100002310000003277513013651447022124 0ustar yarkhangraduate/* * ita_btb.c - example of how use the BTB with the Itanium PMU * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #include #include #include typedef pfm_default_smpl_hdr_t btb_hdr_t; typedef pfm_default_smpl_entry_t btb_entry_t; typedef pfm_default_smpl_ctx_arg_t btb_ctx_arg_t; #define BTB_FMT_UUID PFM_DEFAULT_SMPL_UUID static pfm_uuid_t buf_fmt_id = BTB_FMT_UUID; #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 #define MAX_PMU_NAME_LEN 32 /* * The BRANCH_EVENT is increment by 1 for each branch event. Such event is composed of * two entries in the BTB: a source and a target entry. The BTB is full after 4 branch * events. */ #define SMPL_PERIOD (4UL*256) /* * We use a small buffer size to exercise the overflow handler */ #define SMPL_BUF_NENTRIES 64 #define M_PMD(x) (1UL<<(x)) #define BTB_REGS_MASK (M_PMD(8)|M_PMD(9)|M_PMD(10)|M_PMD(11)|M_PMD(12)|M_PMD(13)|M_PMD(14)|M_PMD(15)|M_PMD(16)) static void *smpl_vaddr; static unsigned int entry_size; static int id; #if defined(__ECC) && defined(__INTEL_COMPILER) /* if you do not have this file, your compiler is too old */ #include #define hweight64(x) _m64_popcnt(x) #elif defined(__GNUC__) static __inline__ int hweight64 (unsigned long x) { unsigned long result; __asm__ ("popcnt %0=%1" : "=r" (result) : "r" (x)); return (int)result; } #else #error "you need to provide inline assembly from your compiler" #endif /* * we don't use static to make sure the compiler does not inline the function */ long func1(void) { return 0;} long do_test(unsigned long loop) { long sum = 0; while(loop--) { if (loop & 0x1) sum += func1(); else sum += loop; } return sum; } static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } /* * print content of sampling buffer * * XXX: using stdio to print from a signal handler is not safe with multi-threaded * applications */ #define safe_printf printf static int show_btb_reg(int j, pfm_ita_pmd_reg_t reg) { int ret; int is_valid = reg.pmd8_15_ita_reg.btb_b == 0 && reg.pmd8_15_ita_reg.btb_mp == 0 ? 0 :1; ret = safe_printf("\tPMD%-2d: 0x%016lx b=%d mp=%d valid=%c\n", j, reg.pmd_val, reg.pmd8_15_ita_reg.btb_b, reg.pmd8_15_ita_reg.btb_mp, is_valid ? 'Y' : 'N'); if (!is_valid) return ret; if (reg.pmd8_15_ita_reg.btb_b) { unsigned long addr; addr = reg.pmd8_15_ita_reg.btb_addr<<4; addr |= reg.pmd8_15_ita_reg.btb_slot < 3 ? reg.pmd8_15_ita_reg.btb_slot : 0; ret = safe_printf("\t Source Address: 0x%016lx\n" "\t Taken=%c Prediction: %s\n\n", addr, reg.pmd8_15_ita_reg.btb_slot < 3 ? 'Y' : 'N', reg.pmd8_15_ita_reg.btb_mp ? "Failure" : "Success"); } else { ret = safe_printf("\t Target Address: 0x%016lx\n\n", (unsigned long)reg.pmd8_15_ita_reg.btb_addr<<4); } return ret; } static void show_btb(pfm_ita_pmd_reg_t *btb, pfm_ita_pmd_reg_t *pmd16) { int i, last; i = (pmd16->pmd16_ita_reg.btbi_full) ? pmd16->pmd16_ita_reg.btbi_bbi : 0; last = pmd16->pmd16_ita_reg.btbi_bbi; safe_printf("btb_trace: i=%d last=%d bbi=%d full=%d\n", i, last,pmd16->pmd16_ita_reg.btbi_bbi, pmd16->pmd16_ita_reg.btbi_full); do { show_btb_reg(i+8, btb[i]); i = (i+1) % 8; } while (i != last); } static void process_smpl_buffer(void) { btb_hdr_t *hdr; btb_entry_t *ent; unsigned long pos; unsigned long smpl_entry = 0; pfm_ita_pmd_reg_t *reg, *pmd16; unsigned long i; int ret; static unsigned long last_ovfl = ~0UL; hdr = (btb_hdr_t *)smpl_vaddr; /* * check that we are not diplaying the previous set of samples again. * Required to take care of the last batch of samples. */ if (hdr->hdr_overflows <= last_ovfl && last_ovfl != ~0UL) { printf("skipping identical set of samples %lu <= %lu\n", hdr->hdr_overflows, last_ovfl); return; } pos = (unsigned long)(hdr+1); /* * walk through all the entries recored in the buffer */ for(i=0; i < hdr->hdr_count; i++) { ret = 0; ent = (btb_entry_t *)pos; /* * print entry header */ safe_printf("Entry %ld PID:%d CPU:%d STAMP:0x%lx IIP:0x%016lx\n", smpl_entry++, ent->pid, ent->cpu, ent->tstamp, ent->ip); /* * point to first recorded register (always contiguous with entry header) */ reg = (pfm_ita_pmd_reg_t*)(ent+1); /* * in this particular example, we have pmd8-pmd15 has the BTB. We have also * included pmd16 (BTB index) has part of the registers to record. This trick * allows us to get the index to decode the sequential order of the BTB. * * Recorded registers are always recorded in increasing order. So we know * that pmd16 is at a fixed offset (+8*sizeof(unsigned long)) from pmd8. */ pmd16 = reg+8; show_btb(reg, pmd16); /* * move to next entry */ pos += entry_size; } } static void overflow_handler(int n, struct siginfo *info, struct sigcontext *sc) { /* dangerous */ printf("Notification received\n"); process_smpl_buffer(); /* * And resume monitoring */ if (perfmonctl(id, PFM_RESTART,NULL, 0) == -1) { perror("PFM_RESTART"); exit(1); } } int main(void) { int ret; int type = 0; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_ita_input_param_t ita_inp; pfarg_reg_t pd[NUM_PMDS]; pfarg_reg_t pc[NUM_PMCS]; btb_ctx_arg_t ctx[1]; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; struct sigaction act; unsigned int i; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) { fatal_error("Can't initialize library\n"); } /* * Let's make sure we run this on the right CPU */ pfm_get_pmu_type(&type); if (type != PFMLIB_ITANIUM_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with %s PMU\n", model); } /* * Install the overflow handler (SIGIO) */ memset(&act, 0, sizeof(act)); act.sa_handler = (sig_t)overflow_handler; sigaction (SIGIO, &act, 0); /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 0; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); memset(pd, 0, sizeof(pd)); memset(ctx, 0, sizeof(ctx)); memset(&inp, 0, sizeof(inp)); memset(&outp, 0, sizeof(outp)); memset(&ita_inp,0, sizeof(ita_inp)); /* * Before calling pfm_find_dispatch(), we must specify what kind * of branches we want to capture. We are interesteed in all the mispredicted branches, * therefore we program we set the various fields of the BTB config to: */ ita_inp.pfp_ita_btb.btb_used = 1; ita_inp.pfp_ita_btb.btb_tar = 0x1; ita_inp.pfp_ita_btb.btb_tm = 0x2; ita_inp.pfp_ita_btb.btb_ptm = 0x3; ita_inp.pfp_ita_btb.btb_tac = 0x1; ita_inp.pfp_ita_btb.btb_bac = 0x1; ita_inp.pfp_ita_btb.btb_ppm = 0x3; ita_inp.pfp_ita_btb.btb_plm = PFM_PLM3; /* * To count the number of occurence of this instruction, we must * program a counting monitor with the IA64_TAGGED_INST_RETIRED_PMC8 * event. */ if (pfm_find_full_event("BRANCH_EVENT", &inp.pfp_events[0]) != PFMLIB_SUCCESS) { fatal_error("cannot find event BRANCH_EVENT\n"); } /* * set the (global) privilege mode: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = 1; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, &ita_inp, &outp, NULL)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); } /* * We initialize the format specific information. * The format is identified by its UUID which must be copied * into the ctx_buf_fmt_id field. */ memcpy(ctx[0].ctx_arg.ctx_smpl_buf_id, buf_fmt_id, sizeof(pfm_uuid_t)); /* * the size of the buffer is indicated in bytes (not entries). * * The kernel will record into the buffer up to a certain point. * No partial samples are ever recorded. */ ctx[0].buf_arg.buf_size = 8192; /* * now create the context for self monitoring/per-task */ if (perfmonctl(0, PFM_CREATE_CONTEXT, ctx, 1) == -1 ) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } printf("Sampling buffer mapped at %p\n", ctx[0].ctx_arg.ctx_smpl_vaddr); smpl_vaddr = ctx[0].ctx_arg.ctx_smpl_vaddr; /* * extract our file descriptor */ id = ctx[0].ctx_arg.ctx_fd; /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events cause extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * the PMC controlling the event ALWAYS come first, that's why this loop * is safe even when extra PMC are needed to support a particular event. */ for (i=0; i < inp.pfp_event_count; i++) { pd[i].reg_num = pc[i].reg_num; } /* * indicate we want notification when buffer is full */ pc[0].reg_flags |= PFM_REGFL_OVFL_NOTIFY; /* * Now prepare the argument to initialize the PMD and the sampling period * We know we use only one PMD in this case, therefore pmd[0] corresponds * to our first event which is our sampling period. */ pd[0].reg_value = (~0UL) - SMPL_PERIOD +1; pd[0].reg_long_reset = (~0UL) - SMPL_PERIOD +1; pd[0].reg_short_reset = (~0UL) - SMPL_PERIOD +1; /* * indicate PMD to collect in each sample */ pc[0].reg_smpl_pmds[0] = BTB_REGS_MASK; /* * compute size of each sample: fixed-size header + all our BTB regs */ entry_size = sizeof(btb_entry_t)+(hweight64(BTB_REGS_MASK)<<3); /* * When our counter overflows, we want to BTB index to be reset, so that we keep * in sync. This is required to make it possible to interpret pmd16 on overflow * to avoid repeating the same branch several times. */ pc[0].reg_reset_pmds[0] = M_PMD(16); /* * reset pmd16 (BTB index), short and long reset value are set to zero as well * * We use slot 1 of our pd[] array for this. */ pd[1].reg_num = 16; pd[1].reg_value = 0UL; /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more thann coutning monitors. */ if (perfmonctl(id, PFM_WRITE_PMCS, pc, outp.pfp_pmc_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMCS errno %d\n",errno); } /* * we use 2 = 1 for the branch_event + 1 for the reset of PMD16. */ if (perfmonctl(id, PFM_WRITE_PMDS, pd, 2) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMDS errno %d\n",errno); } /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = getpid(); if (perfmonctl(id, PFM_LOAD_CONTEXT, &load_args, 1) == -1) { fatal_error("perfmonctl error PFM_LOAD_CONTEXT errno %d\n",errno); } /* * setup asynchronous notification on the file descriptor */ ret = fcntl(id, F_SETFL, fcntl(id, F_GETFL, 0) | O_ASYNC); if (ret == -1) { fatal_error("cannot set ASYNC: %s\n", strerror(errno)); } /* * get ownership of the descriptor */ ret = fcntl(id, F_SETOWN, getpid()); if (ret == -1) { fatal_error("cannot setown: %s\n", strerror(errno)); } /* * Let's roll now. */ pfm_self_start(id); do_test(100000); pfm_self_stop(id); /* * We must call the processing routine to cover the last entries recorded * in the sampling buffer. Note that the buffer may not be full at this point. * */ process_smpl_buffer(); /* * let's stop this now */ close(id); return 0; } papi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/mont_dear.c0000644000307100002310000002633013013651447022456 0ustar yarkhangraduate/* * mont_dear.c - example of how use the D-EAR with the Dual-Core Itanium 2 PMU * * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 #define MAX_PMU_NAME_LEN 32 #define SMPL_PERIOD (40) #define EVENT_NAME "data_ear_cache_lat4" #define M_PMD(x) (1UL<<(x)) #define DEAR_REGS_MASK (M_PMD(32)|M_PMD(33)|M_PMD(36)) typedef pfm_default_smpl_hdr_t dear_hdr_t; typedef pfm_default_smpl_entry_t dear_entry_t; typedef pfm_default_smpl_ctx_arg_t dear_ctx_t; #define DEAR_FMT_UUID PFM_DEFAULT_SMPL_UUID static pfm_uuid_t buf_fmt_id = DEAR_FMT_UUID; static void *smpl_vaddr; static unsigned long entry_size; static int id; #if defined(__ECC) && defined(__INTEL_COMPILER) /* if you do not have this file, your compiler is too old */ #include #define hweight64(x) _m64_popcnt(x) #elif defined(__GNUC__) static __inline__ int hweight64 (unsigned long x) { unsigned long result; __asm__ ("popcnt %0=%1" : "=r" (result) : "r" (x)); return (int)result; } #else #error "you need to provide inline assembly from your compiler" #endif long do_test(unsigned long size) { unsigned long i, sum = 0; int *array; printf("buffer size %.1fMB\n", (size*sizeof(int))/1024.0); array = (int *)malloc(size * sizeof(int)); if (array == NULL ) { printf("line = %d No memory available!\n", __LINE__); exit(1); } for(i=0; ihdr_overflows <= last_ovfl && last_ovfl != ~0UL) { printf("skipping identical set of samples %lu <= %lu\n", hdr->hdr_overflows, last_ovfl); return; } pos = (unsigned long)(hdr+1); count = hdr->hdr_count; /* * walk through all the entries recored in the buffer */ while(count--) { ret = 0; ent = (dear_entry_t *)pos; /* * print entry header */ safe_printf("Entry %ld PID:%d TID:%d CPU:%d STAMP:0x%lx IIP:0x%016lx\n", smpl_entry++, ent->tgid, ent->pid, ent->cpu, ent->tstamp, ent->ip); /* * point to first recorded register (always contiguous with entry header) */ reg = (pfm_mont_pmd_reg_t*)(ent+1); safe_printf("PMD32: 0x%016lx\n", reg->pmd32_mont_reg.dear_daddr); reg++; safe_printf("PMD33: 0x%016lx, latency %u\n", reg->pmd_val, reg->pmd33_mont_reg.dear_latency); reg++; safe_printf("PMD36: 0x%016lx, valid %c, address 0x%016lx\n", reg->pmd_val, reg->pmd36_mont_reg.dear_vl ? 'Y': 'N', (reg->pmd36_mont_reg.dear_iaddr << 4) | (unsigned long)reg->pmd36_mont_reg.dear_slot); /* * move to next entry */ pos += entry_size; } } static void overflow_handler(int n, struct siginfo *info, struct sigcontext *sc) { process_smpl_buffer(); /* * And resume monitoring */ if (perfmonctl(id, PFM_RESTART, NULL, 0)) fatal_error("pfm_restart"); } int main(void) { pfarg_reg_t pd[NUM_PMDS]; pfarg_reg_t pc[NUM_PMCS]; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_event_t ev; dear_ctx_t ctx; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; struct sigaction act; unsigned int i; int ret, type = 0; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) fatal_error("Can't initialize library\n"); /* * Let's make sure we run this on the right CPU */ pfm_get_pmu_type(&type); if (type != PFMLIB_MONTECITO_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with %s PMU\n", model); } /* * Install the overflow handler (SIGIO) */ memset(&act, 0, sizeof(act)); act.sa_handler = (sig_t)overflow_handler; sigaction (SIGIO, &act, 0); /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 1; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); memset(pd, 0, sizeof(pd)); memset(pc, 0, sizeof(pc)); memset(pc, 0, sizeof(pc)); memset(&ctx, 0, sizeof(ctx)); memset(&load_args, 0, sizeof(load_args)); /* * prepare parameters to library. we don't use any Itanium * specific features here. so the pfp_model is NULL. */ memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); /* * To count the number of occurence of this instruction, we must * program a counting monitor with the IA64_TAGGED_INST_RETIRED_PMC8 * event. */ if (pfm_find_full_event(EVENT_NAME, &ev) != PFMLIB_SUCCESS) fatal_error("cannot find event %s\n", EVENT_NAME); /* * set the (global) privilege mode: * PFM_PLM0 : kernel level only */ inp.pfp_dfl_plm = PFM_PLM3|PFM_PLM0; /* * how many counters we use */ inp.pfp_event_count = 1; /* * propagate the event descriptor */ inp.pfp_events[0] = ev; /* * let the library figure out the values for the PMCS * * We use all global settings for this EAR. */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); /* * prepare context structure. * * format specific parameters MUST be concatenated to the regular * pfarg_ctx_t structure. For convenience, the default sampling * format provides a data structure that already combines the pfarg_ctx_t * with what is needed fot this format. */ /* * We initialize the format specific information. * The format is identified by its UUID which must be copied * into the ctx_buf_fmt_id field. */ memcpy(ctx.ctx_arg.ctx_smpl_buf_id, buf_fmt_id, sizeof(pfm_uuid_t)); /* * the size of the buffer is indicated in bytes (not entries). * * The kernel will record into the buffer up to a certain point. * No partial samples are ever recorded. */ ctx.buf_arg.buf_size = getpagesize(); /* * now create the context for self monitoring/per-task */ if (perfmonctl(0, PFM_CREATE_CONTEXT, &ctx, 1) == -1 ) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * extract the file descriptor we will use to * identify this newly created context */ id = ctx.ctx_arg.ctx_fd; /* * retrieve the virtual address at which the sampling * buffer has been mapped */ smpl_vaddr =ctx.ctx_arg.ctx_smpl_vaddr; printf("Sampling buffer mapped at %p\n", smpl_vaddr); /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events causes extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * figure out pmd mapping from output pmc */ for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * indicate we want notification when buffer is full */ pc[0].reg_flags |= PFM_REGFL_OVFL_NOTIFY; /* * indicate which PMD to include in the sample */ pc[0].reg_smpl_pmds[0] = DEAR_REGS_MASK; /* * compute size of each sample: fixed-size header + all our DEAR regs */ entry_size = sizeof(dear_entry_t)+(hweight64(DEAR_REGS_MASK)<<3); /* * initialize the PMD and the sampling period */ pd[0].reg_value = - SMPL_PERIOD; pd[0].reg_long_reset = - SMPL_PERIOD; pd[0].reg_short_reset = - SMPL_PERIOD; /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more thann coutning monitors. */ if (perfmonctl(id, PFM_WRITE_PMCS, pc, outp.pfp_pmc_count)) fatal_error("pfm_write_pmcs error errno %d\n",errno); if (perfmonctl(id, PFM_WRITE_PMDS, pd, outp.pfp_pmd_count)) fatal_error("pfm_write_pmds error errno %d\n",errno); /* * attach context to stopped task */ load_args.load_pid = getpid(); if (perfmonctl(id, PFM_LOAD_CONTEXT, &load_args, 1)) fatal_error("pfm_load_context error errno %d\n",errno); /* * setup asynchronous notification on the file descriptor */ ret = fcntl(id, F_SETFL, fcntl(id, F_GETFL, 0) | O_ASYNC); if (ret == -1) fatal_error("cannot set ASYNC: %s\n", strerror(errno)); /* * get ownership of the descriptor */ ret = fcntl(id, F_SETOWN, getpid()); if (ret == -1) fatal_error("cannot setown: %s\n", strerror(errno)); /* * Let's roll now. */ pfm_self_start(id); do_test(100000); pfm_self_stop(id); /* * We must call the processing routine to cover the last entries recorded * in the sampling buffer, i.e. which may not be full */ process_smpl_buffer(); /* * let's stop this now */ close(id); return 0; } papi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/notify_self.c0000644000307100002310000001737113013651447023034 0ustar yarkhangraduate/* * notify_self.c - example of how you can use overflow notifications * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #include #include #include #define SMPL_PERIOD 1000000000UL static volatile unsigned long notification_received; #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS static pfarg_reg_t pd[NUM_PMDS]; static int ctx_fd; static char *event1_name; static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } static void sigio_handler(int n, struct siginfo *info, struct sigcontext *sc) { pfm_msg_t msg; int fd = ctx_fd; int r; if (fd != ctx_fd) { fatal_error("handler does not get valid file descriptor\n"); } if (event1_name && perfmonctl(fd, PFM_READ_PMDS, pd+1, 1) == -1) { fatal_error("PFM_READ_PMDS: %s", strerror(errno)); } r = read(fd, &msg, sizeof(msg)); if (r != sizeof(msg)) { fatal_error("cannot read overflow message: %s\n", strerror(errno)); } if (msg.type != PFM_MSG_OVFL) { fatal_error("unexpected msg type: %d\n",msg.type); } /* * XXX: risky to do printf() in signal handler! */ if (event1_name) printf("Notification %lu: %"PRIu64" %s\n", notification_received, pd[1].reg_value, event1_name); else printf("Notification %lu\n", notification_received); /* * At this point, the counter used for the sampling period has already * be reset by the kernel because we are in non-blocking mode, self-monitoring. */ /* * increment our notification counter */ notification_received++; /* * And resume monitoring */ if (perfmonctl(fd, PFM_RESTART,NULL, 0) == -1) { fatal_error("PFM_RESTART: %s", strerror(errno)); } } /* * infinite loop waiting for notification to get out */ void busyloop(void) { /* * busy loop to burn CPU cycles */ for(;notification_received < 3;) ; } int main(int argc, char **argv) { pfarg_context_t ctx[1]; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfarg_reg_t pc[NUM_PMCS]; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; struct sigaction act; unsigned int i, num_counters; size_t len; int ret; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) { printf("Can't initialize library\n"); exit(1); } /* * Install the signal handler (SIGIO) */ memset(&act, 0, sizeof(act)); act.sa_handler = (sig_t)sigio_handler; sigaction (SIGIO, &act, 0); /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); memset(pc, 0, sizeof(pc)); memset(ctx, 0, sizeof(ctx)); memset(&load_args, 0, sizeof(load_args)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); pfm_get_num_counters(&num_counters); if (pfm_get_cycle_event(&inp.pfp_events[0]) != PFMLIB_SUCCESS) fatal_error("cannot find cycle event\n"); if (pfm_get_inst_retired_event(&inp.pfp_events[1]) != PFMLIB_SUCCESS) fatal_error("cannot find inst retired event\n"); i = 2; /* * set the default privilege mode for all counters: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; if (i > num_counters) { i = num_counters; printf("too many events provided (max=%d events), using first %d event(s)\n", num_counters, i); } /* * how many counters we use */ inp.pfp_event_count = i; pfm_get_max_event_name_len(&len); event1_name = malloc(len+1); if (event1_name == NULL) fatal_error("cannot allocate event name\n"); pfm_get_full_event_name(&inp.pfp_events[1], event1_name, len+1); /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) { fatal_error("Cannot configure events: %s\n", pfm_strerror(ret)); } /* * now create the context for self monitoring/per-task */ if (perfmonctl(0, PFM_CREATE_CONTEXT, ctx, 1) == -1 ) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } ctx_fd = ctx->ctx_fd; /* * Now prepare the argument to initialize the PMDs and PMCS. * We use pfp_pmc_count to determine the number of registers to * setup. Note that this field can be >= pfp_event_count. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } for (i=0; i < inp.pfp_event_count; i++) { pd[i].reg_num = pc[i].reg_num; } /* * We want to get notified when the counter used for our first * event overflows */ pc[0].reg_flags |= PFM_REGFL_OVFL_NOTIFY; pc[0].reg_reset_pmds[0] |= 1UL << outp.pfp_pmcs[1].reg_num; /* * we arm the first counter, such that it will overflow * after SMPL_PERIOD events have been observed */ pd[0].reg_value = (~0UL) - SMPL_PERIOD + 1; pd[0].reg_long_reset = (~0UL) - SMPL_PERIOD + 1; pd[0].reg_short_reset = (~0UL) - SMPL_PERIOD + 1; /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more than counting monitors. */ if (perfmonctl(ctx_fd, PFM_WRITE_PMCS, pc, outp.pfp_pmc_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMCS errno %d\n",errno); } if (perfmonctl(ctx_fd, PFM_WRITE_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMDS errno %d\n",errno); } /* * we want to monitor ourself */ load_args.load_pid = getpid(); if (perfmonctl(ctx_fd, PFM_LOAD_CONTEXT, &load_args, 1) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMDS errno %d\n",errno); } /* * setup asynchronous notification on the file descriptor */ ret = fcntl(ctx_fd, F_SETFL, fcntl(ctx_fd, F_GETFL, 0) | O_ASYNC); if (ret == -1) { fatal_error("cannot set ASYNC: %s\n", strerror(errno)); } /* * get ownership of the descriptor */ ret = fcntl(ctx_fd, F_SETOWN, getpid()); if (ret == -1) { fatal_error("cannot setown: %s\n", strerror(errno)); } /* * Let's roll now */ pfm_self_start(ctx_fd); busyloop(); pfm_self_stop(ctx_fd); /* * free our context */ close(ctx_fd); return 0; } papi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/mont_opcode.c0000644000307100002310000001661113013651447023015 0ustar yarkhangraduate/* * mont_opcode.c - example of how to use the opcode matcher with the Dual-Core Itanium 2 PMU * * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #include #include #include #include #include #include #include #include #include #include #define OPCM_EVENT "IA64_TAGGED_INST_RETIRED_IBRP0_PMC32_33" #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 #define MAX_PMU_NAME_LEN 32 #define NLOOP 200UL /* * we don't use static to make sure the compiler does not inline the function */ int do_test(unsigned long loop) { unsigned long sum = 0; while(loop--) sum += loop; return sum; } static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } int main(void) { pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_mont_input_param_t mont_inp; pfarg_reg_t pd[NUM_PMDS]; pfarg_reg_t pc[NUM_PMCS]; pfarg_context_t ctx; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; int ret; int type = 0; int id; unsigned int i; char name[MAX_EVT_NAME_LEN]; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) fatal_error("Can't initialize library\n"); /* * Let's make sure we run this on the right CPU */ pfm_get_pmu_type(&type); if (type != PFMLIB_MONTECITO_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with the %s PMU\n", model); } /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 1; /* set to 1 for verbose */ pfm_set_options(&pfmlib_options); memset(pd, 0, sizeof(pd)); memset(pc, 0, sizeof(pc)); memset(&ctx, 0, sizeof(ctx)); memset(&load_args, 0, sizeof(load_args)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&mont_inp,0, sizeof(mont_inp)); /* * We indicate that we are using the first opcode matcher (PMC32/PMC33). */ mont_inp.pfp_mont_opcm1.opcm_used = 1; /* * We want to match all the br.cloop in our test function. * This branch is an IP-relative branch for which the major * opcode (bits [40-37]) is 4 and the btype field (bits[6-8]) is 5. * We ignore all the other fields in the opcode. * * On Montecito, the opcode matcher covers the full 41 bits of each * instruction but we'll ignore them in this example. Hence the * match value is: * * match = (4<<37)| (5<<6) = 0x8000000140 * * On Montecito, the match field covers the full 41 bits of each instruction. * But for this example, we only care about the major and btype field, * and we ignore all other bits. When a bit is set in the mask it means * that the corresponding match bit value is a "don't care". A bit * with value of zero indicates that the corresponding match bit * must match. Hence we build the following mask: * * mask = ~((0xf<<37) | (0x3<<6)) = 0x1fffffff3f; * * The 0xf comes from the fact that major opcode is 4-bit wide. * The 0x3 comes from the fact that btype is 3-bit wide. */ mont_inp.pfp_mont_opcm1.opcm_b = 1; mont_inp.pfp_mont_opcm1.opcm_match = 0x8000000140; mont_inp.pfp_mont_opcm1.opcm_mask = 0x1fffffff3f; /* * To count the number of occurence of this instruction, we must * program a counting monitor with the IA64_TAGGED_INST_RETIRED_PMC8 * event. */ if (pfm_find_full_event(OPCM_EVENT, &inp.pfp_events[0]) != PFMLIB_SUCCESS) fatal_error("cannot find event %s\n", OPCM_EVENT); /* * set the privilege mode: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = 1; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, &mont_inp, &outp, NULL)) != PFMLIB_SUCCESS) fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); /* * now create the context for self monitoring/per-task */ if (perfmonctl(0, PFM_CREATE_CONTEXT, &ctx, 1) == -1 ) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * extract the unique identifier for our context, a regular file descriptor */ id = ctx.ctx_fd; /* * Now prepare the argument to initialize the PMDs and PMCS. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * figure out pmd mapping from output pmc */ for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more thann coutning monitors. */ if (perfmonctl(id, PFM_WRITE_PMCS, pc, outp.pfp_pmc_count)) fatal_error("pfm_write_pmcs error errno %d\n",errno); if (perfmonctl(id, PFM_WRITE_PMDS, pd, outp.pfp_pmd_count)) fatal_error("pfm_write_pmds error errno %d\n",errno); /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = getpid(); if (perfmonctl(id, PFM_LOAD_CONTEXT, &load_args, 1)) fatal_error("pfm_load_context error errno %d\n",errno); /* * Let's roll now. */ pfm_self_start(id); do_test(NLOOP); pfm_self_stop(id); /* * now read the results */ if (perfmonctl(id, PFM_READ_PMDS, pd, inp.pfp_event_count)) fatal_error("pfm_read_pmds error errno %d\n",errno); /* * print the results */ pfm_get_full_event_name(&inp.pfp_events[0], name, MAX_EVT_NAME_LEN); printf("PMD%-3u %20lu %s (expected %lu)\n", pd[0].reg_num, pd[0].reg_value, name, NLOOP); if (pd[0].reg_value != 0) printf("compiler used br.cloop\n"); else printf("compiler did not use br.cloop\n"); /* * let's stop this now */ close(id); return 0; } papi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/notify_self3.c0000644000307100002310000002040713013651447023111 0ustar yarkhangraduate/* * notify_self3.c - example of how you can use overflow notifications with no messages * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #include #include #include #define SMPL_PERIOD 1000000000UL static volatile unsigned long notification_received; #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS static pfarg_reg_t pd[NUM_PMDS]; static int ctx_fd; static char *event1_name; static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } static void sigio_handler(int n, struct siginfo *info, struct sigcontext *sc) { if (perfmonctl(ctx_fd, PFM_READ_PMDS, pd+1, 1) == -1) { fatal_error("PFM_READ_PMDS: %s", strerror(errno)); } /* * we do not need to extract the overflow message, we know * where it is coming from. */ /* * XXX: risky to do printf() in signal handler! */ if (event1_name) printf("Notification %02lu: %"PRIu64" %s\n", notification_received, pd[1].reg_value, event1_name); else printf("Notification %02lu:\n", notification_received); /* * At this point, the counter used for the sampling period has already * be reset by the kernel because we are in non-blocking mode, self-monitoring. */ /* * increment our notification counter */ notification_received++; /* * And resume monitoring */ if (perfmonctl(ctx_fd, PFM_RESTART,NULL, 0) == -1) { fatal_error("PFM_RESTART: %s", strerror(errno)); } } /* * infinite loop waiting for notification to get out */ void busyloop(void) { /* * busy loop to burn CPU cycles */ for(;notification_received < 40;) ; } int main(int argc, char **argv) { pfarg_context_t ctx[1]; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfarg_reg_t pc[NUM_PMCS]; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; struct sigaction act; size_t len; unsigned int i, num_counters; int ret; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) { printf("Can't initialize library\n"); exit(1); } /* * Install the signal handler (SIGIO) */ memset(&act, 0, sizeof(act)); act.sa_handler = (sig_t)sigio_handler; sigaction (SIGIO, &act, 0); /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); memset(pc, 0, sizeof(pc)); memset(ctx, 0, sizeof(ctx)); memset(&load_args, 0, sizeof(load_args)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); pfm_get_num_counters(&num_counters); if (pfm_get_cycle_event(&inp.pfp_events[0]) != PFMLIB_SUCCESS) fatal_error("cannot find cycle event\n"); if (pfm_get_inst_retired_event(&inp.pfp_events[1]) != PFMLIB_SUCCESS) fatal_error("cannot find inst retired event\n"); i = 2; if (i > num_counters) { i = num_counters; printf("too many events provided (max=%d events), using first %d event(s)\n", num_counters, i); } /* * set the default privilege mode for all counters: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = i; /* * how many counters we use */ if (i > 1) { inp.pfp_event_count = i; pfm_get_max_event_name_len(&len); event1_name = malloc(len+1); if (event1_name == NULL) fatal_error("cannot allocate event name\n"); pfm_get_full_event_name(&inp.pfp_events[1], event1_name, len+1); } /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) { fatal_error("Cannot configure events: %s\n", pfm_strerror(ret)); } /* * when we know we are self-monitoring and we have only one context, then * when we get an overflow we know where it is coming from. Therefore we can * save the call to the kernel to extract the notification message. By default, * a message is generated. The queue of messages has a limited size, therefore * it is important to clear the queue by reading the message on overflow. Failure * to do so may result in a queue full and you will lose notification messages. * * With the PFM_FL_OVFL_NO_MSG, no message will be queue, but you will still get * the signal. Similarly, the PFM_MSG_END will be generated. */ ctx[0].ctx_flags = PFM_FL_OVFL_NO_MSG; /* * now create the context for self monitoring/per-task */ if (perfmonctl(0, PFM_CREATE_CONTEXT, ctx, 1) == -1 ) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } ctx_fd = ctx->ctx_fd; /* * Now prepare the argument to initialize the PMDs and PMCS. * We use pfp_pmc_count to determine the number of registers to * setup. Note that this field can be >= pfp_event_count. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } for (i=0; i < inp.pfp_event_count; i++) { pd[i].reg_num = pc[i].reg_num; } /* * We want to get notified when the counter used for our first * event overflows */ pc[0].reg_flags |= PFM_REGFL_OVFL_NOTIFY; pc[0].reg_reset_pmds[0] |= 1UL << outp.pfp_pmcs[1].reg_num; /* * we arm the first counter, such that it will overflow * after SMPL_PERIOD events have been observed */ pd[0].reg_value = (~0UL) - SMPL_PERIOD + 1; pd[0].reg_long_reset = (~0UL) - SMPL_PERIOD + 1; pd[0].reg_short_reset = (~0UL) - SMPL_PERIOD + 1; /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more than counting monitors. */ if (perfmonctl(ctx_fd, PFM_WRITE_PMCS, pc, outp.pfp_pmc_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMCS errno %d\n",errno); } if (perfmonctl(ctx_fd, PFM_WRITE_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMDS errno %d\n",errno); } /* * we want to monitor ourself */ load_args.load_pid = getpid(); if (perfmonctl(ctx_fd, PFM_LOAD_CONTEXT, &load_args, 1) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMDS errno %d\n",errno); } /* * setup asynchronous notification on the file descriptor */ ret = fcntl(ctx_fd, F_SETFL, fcntl(ctx_fd, F_GETFL, 0) | O_ASYNC); if (ret == -1) { fatal_error("cannot set ASYNC: %s\n", strerror(errno)); } /* * get ownership of the descriptor */ ret = fcntl(ctx_fd, F_SETOWN, getpid()); if (ret == -1) { fatal_error("cannot setown: %s\n", strerror(errno)); } /* * Let's roll now */ pfm_self_start(ctx_fd); busyloop(); pfm_self_stop(ctx_fd); /* * free our context */ close(ctx_fd); return 0; } papi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/self.c0000644000307100002310000001630413013651447021437 0ustar yarkhangraduate/* * self.c - example of a simple self monitoring task * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #include #include #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 static volatile int quit; void sig_handler(int n) { quit = 1; } /* * our test code (function cannot be made static otherwise it is optimized away) */ void noploop(void) { for(;quit == 0;); } static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } int main(int argc, char **argv) { char **p; unsigned int i; int ret, ctx_fd; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfarg_reg_t pd[NUM_PMDS]; pfarg_reg_t pc[NUM_PMCS]; pfarg_context_t ctx[1]; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; unsigned int num_counters; char name[MAX_EVT_NAME_LEN]; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) { printf("Can't initialize library\n"); exit(1); } pfm_get_num_counters(&num_counters); /* * check that the user did not specify too many events */ if ((unsigned int)(argc-1) > num_counters) { printf("Too many events specified\n"); exit(1); } /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); memset(pd, 0, sizeof(pd)); memset(pc, 0, sizeof(pc)); memset(ctx, 0, sizeof(ctx)); memset(&load_args, 0, sizeof(load_args)); /* * prepare parameters to library. we don't use any Itanium * specific features here. so the pfp_model is NULL. */ memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); /* * be nice to user! */ if (argc > 1) { p = argv+1; for (i=0; *p ; i++, p++) { if (pfm_find_event(*p, &inp.pfp_events[i].event) != PFMLIB_SUCCESS) { fatal_error("Cannot find %s event\n", *p); } } } else { if (pfm_get_cycle_event(&inp.pfp_events[0]) != PFMLIB_SUCCESS) fatal_error("cannot find cycle event\n"); if (pfm_get_inst_retired_event(&inp.pfp_events[1]) != PFMLIB_SUCCESS) fatal_error("cannot find inst retired event\n"); i = 2; } /* * set the default privilege mode for all counters: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; if (i > num_counters) { i = num_counters; printf("too many events provided (max=%d events), using first %d event(s)\n", num_counters, i); } /* * how many counters we use */ inp.pfp_event_count = i; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); } /* * now create a new context, per process context. * This just creates a new context with some initial state, it is not * active nor attached to any process. */ if (perfmonctl(0, PFM_CREATE_CONTEXT, ctx, 1) == -1 ) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * extract the unique identifier for our context, a regular file descriptor */ ctx_fd = ctx[0].ctx_fd; /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events causes extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * the PMC controlling the event ALWAYS come first, that's why this loop * is safe even when extra PMC are needed to support a particular event. */ for (i=0; i < inp.pfp_event_count; i++) { pd[i].reg_num = pc[i].reg_num; } /* * Now program the registers * * We don't use the same variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events (pmd) we specified, i.e., contains more than counting * monitors. */ if (perfmonctl(ctx_fd, PFM_WRITE_PMCS, pc, outp.pfp_pmc_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMCS errno %d\n",errno); } if (perfmonctl(ctx_fd, PFM_WRITE_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMDS errno %d\n",errno); } /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = getpid(); if (perfmonctl(ctx_fd, PFM_LOAD_CONTEXT, &load_args, 1) == -1) { fatal_error("perfmonctl error PFM_LOAD_CONTEXT errno %d\n",errno); } /* * Let's roll now */ signal(SIGALRM, sig_handler); pfm_self_start(ctx_fd); alarm(10); noploop(); pfm_self_stop(ctx_fd); /* * now read the results */ if (perfmonctl(ctx_fd, PFM_READ_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error( "perfmonctl error READ_PMDS errno %d\n",errno); return -1; } /* * print the results * * It is important to realize, that the first event we specified may not * be in PMD4. Not all events can be measured by any monitor. That's why * we need to use the pc[] array to figure out where event i was allocated. * */ for (i=0; i < inp.pfp_event_count; i++) { pfm_get_full_event_name(&inp.pfp_events[i], name, MAX_EVT_NAME_LEN); printf("PMD%u %20"PRIu64" %s\n", pd[i].reg_num, pd[i].reg_value, name); } /* * and destroy our context */ close(ctx_fd); return 0; } papi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/ita_irr.c0000644000307100002310000002544413013651447022144 0ustar yarkhangraduate/* * ita_irr.c - example of how to use code range restriction with the Itanium PMU * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #include #define VECTOR_SIZE 1000000UL #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 #define MAX_PMU_NAME_LEN 32 typedef struct { char *event_name; unsigned long expected_value; } event_desc_t; static event_desc_t event_list[]={ { "fp_ops_retired_hi", 0UL} , { "fp_ops_retired_lo", VECTOR_SIZE<<1 }, { NULL, 0UL } }; static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } void saxpy(double *a, double *b, double *c, unsigned long size) { unsigned long i; for(i=0; i < size; i++) { c[i] = 2*a[i] + b[i]; } } void saxpy2(double *a, double *b, double *c, unsigned long size) { unsigned long i; for(i=0; i < size; i++) { c[i] = 2*a[i] + b[i]; } } static int do_test(void) { unsigned long size; double *a, *b, *c; size = VECTOR_SIZE; a = malloc(size*sizeof(double)); b = malloc(size*sizeof(double)); c = malloc(size*sizeof(double)); if (a == NULL || b == NULL || c == NULL) fatal_error("Cannot allocate vectors\n"); memset(a, 0, size*sizeof(double)); memset(b, 0, size*sizeof(double)); memset(c, 0, size*sizeof(double)); saxpy(a,b,c, size); saxpy2(a,b,c, size); return 0; } int main(int argc, char **argv) { event_desc_t *p; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_ita_input_param_t ita_inp; pfmlib_ita_output_param_t ita_outp; pfarg_reg_t pd[NUM_PMDS]; pfarg_reg_t pc[NUM_PMCS]; pfarg_dbreg_t ibrs[8]; pfarg_context_t ctx[1]; pfarg_load_t load_args; unsigned long range_start, range_end; pfmlib_options_t pfmlib_options; struct fd { /* function descriptor */ unsigned long addr; unsigned long gp; } *fd; int ret, type = 0; unsigned int i; int id; char name[MAX_EVT_NAME_LEN]; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) { fatal_error("Can't initialize library\n"); } /* * Let's make sure we run this on the right CPU family */ pfm_get_pmu_type(&type); if (type != PFMLIB_ITANIUM_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with %s PMU\n", model); } /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 1; /* set to 1 for verbose */ pfm_set_options(&pfmlib_options); /* * Compute the range we are interested in * * On IA-64, the function pointer does not point directly * to the function but to a descriptor which contains two * unsigned long: the first one is the actual start address * of the function, the second is the gp (global pointer) * to load into r1 before jumping into the function. Unlesss * we're jumping into a shared library the gp is the same as * the current gp. * * In the artificial example, we also rely on the compiler/linker * NOT reordering code layout. We depend on saxpy2() being just * after saxpy(). * */ fd = (struct fd *)saxpy; range_start = fd->addr; fd = (struct fd *)saxpy2; range_end = fd->addr; memset(pd, 0, sizeof(pd)); memset(ctx, 0, sizeof(ctx)); memset(ibrs,0, sizeof(ibrs)); memset(&load_args,0, sizeof(load_args)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&ita_inp,0, sizeof(ita_inp)); memset(&ita_outp,0, sizeof(ita_outp)); /* * find requested event */ p = event_list; for (i=0; p->event_name ; i++, p++) { if (pfm_find_event(p->event_name, &inp.pfp_events[i].event) != PFMLIB_SUCCESS) { fatal_error("Cannot find %s event\n", p->event_name); } } /* * set the privilege mode: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = i; /* * We use the library to figure out how to program the debug registers * to cover the data range we are interested in. The rr_end parameter * must point to the byte after the last element of the range (C-style range). * * Because of the masking mechanism and therefore alignment constraints used to implement * this feature, it may not be possible to exactly cover a given range. It may be that * the coverage exceeds the desired range. So it is possible to capture noise if * the surrounding addresses are also heavily used. You can figure out by how much the * actual range is off compared to the requested range by checking the rr_soff and rr_eoff * fields of rr_infos on return from the library call. * * Upon return, the rr_dbr array is programmed and the number of debug registers (not pairs) * used to cover the range is in rr_nbr_used. * */ ita_inp.pfp_ita_irange.rr_used = 1; /* indicate we use code range restriction */ ita_inp.pfp_ita_irange.rr_limits[0].rr_start = range_start; ita_inp.pfp_ita_irange.rr_limits[0].rr_end = range_end; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, &ita_inp, &outp, &ita_outp)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); } /* * print offsets */ printf("code range : [0x%016lx-0x%016lx)\n" "start_offset:-0x%lx end_offset:+0x%lx\n" "%d pairs of debug registers used\n", range_start, range_end, ita_outp.pfp_ita_irange.rr_infos[0].rr_soff, ita_outp.pfp_ita_irange.rr_infos[0].rr_eoff, ita_outp.pfp_ita_irange.rr_nbr_used >> 1); /* * now create the context for self monitoring/per-task */ if (perfmonctl(0, PFM_CREATE_CONTEXT, ctx, 1) == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("cannot create PFM context %s\n", strerror(errno)); } /* * extract our file descriptor */ id = ctx[0].ctx_fd; /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events cause extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * the PMC controlling the event ALWAYS come first, that's why this loop * is safe even when extra PMC are needed to support a particular event. */ for (i=0; i < inp.pfp_event_count; i++) { pd[i].reg_num = pc[i].reg_num; } /* * propagate the setup for the debug registers from the library to the arguments * to the perfmonctl() syscall. The library does not know the type of the syscall * anymore. */ for (i=0; i < ita_outp.pfp_ita_drange.rr_nbr_used; i++) { ibrs[i].dbreg_num = ita_outp.pfp_ita_irange.rr_br[i].reg_num; ibrs[i].dbreg_value = ita_outp.pfp_ita_irange.rr_br[i].reg_value; } /* * Program the code debug registers. * * IMPORTANT: programming the debug register MUST always be done before the PMCs * otherwise the kernel will fail on PFM_WRITE_PMCS. This is for security reasons. */ if (perfmonctl(id, PFM_WRITE_IBRS, ibrs, ita_outp.pfp_ita_irange.rr_nbr_used) == -1) { fatal_error("perfmonctl error PFM_WRITE_IBRS errno %d\n",errno); } /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more than coutning monitors. */ if (perfmonctl(id, PFM_WRITE_PMCS, pc, outp.pfp_pmc_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMCS errno %d\n",errno); } if (perfmonctl(id, PFM_WRITE_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMDS errno %d\n",errno); } /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = getpid(); if (perfmonctl(id, PFM_LOAD_CONTEXT, &load_args, 1) == -1) { fatal_error("perfmonctl error PFM_LOAD_CONTEXT errno %d\n",errno); } /* * Let's roll now. * * We run two distinct copies of the same function but we restrict measurement * to the first one (saxpy). Therefore the expected count is half what you would * get if code range restriction was not used. The core loop in both case uses * two floating point operation per iteration. */ pfm_self_start(id); do_test(); pfm_self_stop(id); /* * now read the results */ if (perfmonctl(id, PFM_READ_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error("perfmonctl error READ_PMDS errno %d\n",errno); } /* * print the results * * It is important to realize, that the first event we specified may not * be in PMD4. Not all events can be measured by any monitor. That's why * we need to use the pc[] array to figure out where event i was allocated. */ for (i=0; i < inp.pfp_event_count; i++) { pfm_get_full_event_name(&inp.pfp_events[i], name, MAX_EVT_NAME_LEN); printf("PMD%u %20lu %s (expected %lu)\n", pd[i].reg_num, pd[i].reg_value, name, event_list[i].expected_value); } /* * let's stop this now */ close(id); return 0; } papi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/whichpmu.c0000644000307100002310000000726513013651447022340 0ustar yarkhangraduate/* * whichpmu.c - example of how to figure out the host PMU model detected by pfmlib * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #define MAX_PMU_NAME_LEN 32 int main(void) { pfmlib_regmask_t impl_pmds; pfmlib_regmask_t impl_pmcs; pfmlib_regmask_t impl_counters; unsigned int num_pmds, num_pmcs, num_counters, num_events; unsigned int width = 0; unsigned int i; char model[MAX_PMU_NAME_LEN]; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) { printf("Can't initialize library\n"); return 1; } memset(&impl_pmcs, 0, sizeof(impl_pmcs)); memset(&impl_pmds, 0, sizeof(impl_pmds)); memset(&impl_counters, 0, sizeof(impl_counters)); /* * Now simply print the CPU model detected by pfmlib * * When the CPU model is not directly supported AND the generic support * is compiled into the library, the detected will yield "Generic" which * mean that only the architected features will be supported. * * This call can be used to tune applications based on the detected host * CPU model. This is useful because some features are CPU model specific, * such as address range restriction which is an Itanium feature. * */ pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); pfm_get_hw_counter_width(&width); pfm_get_impl_pmds(&impl_pmds); pfm_get_impl_pmcs(&impl_pmcs); pfm_get_impl_counters(&impl_counters); pfm_get_num_events(&num_events); pfm_get_num_pmds(&num_pmds); pfm_get_num_pmcs(&num_pmcs); pfm_get_num_counters(&num_counters); printf("PMU model detected by pfmlib: %s\n", model); printf("]\nnumber of PMD registers : %u\n", num_pmds); printf("implemented PMD registers : [ "); for (i=0; num_pmds; i++) { if (pfm_regmask_isset(&impl_pmds, i) == 0) continue; printf("%-3u", i); num_pmds--; } printf("]\nnumber of PMC registers : %u\n", num_pmcs); printf("implemented PMC registers : [ "); for (i=0; num_pmcs; i++) { if (pfm_regmask_isset(&impl_pmcs, i) == 0) continue; printf("%-3u", i); num_pmcs--; } printf("]\nnumber of counters : %u\n", num_counters); printf("implemented counters : [ "); for (i=0; num_counters; i++) { if (pfm_regmask_isset(&impl_counters, i) == 0) continue; printf("%-3u", i); num_counters--; } printf("]\nhardware counter width : %u\n", width); printf("number of events supported : %u\n", num_events); return 0; } papi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/ita2_btb.c0000644000307100002310000003347513013651447022204 0ustar yarkhangraduate/* * ita2_btb.c - example of how use the BTB with the Itanium 2 PMU * * Copyright (c) 2003-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #include #include #include typedef pfm_default_smpl_hdr_t btb_hdr_t; typedef pfm_default_smpl_entry_t btb_entry_t; typedef pfm_default_smpl_ctx_arg_t btb_ctx_arg_t; #define BTB_FMT_UUID PFM_DEFAULT_SMPL_UUID static pfm_uuid_t buf_fmt_id = BTB_FMT_UUID; #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 #define MAX_PMU_NAME_LEN 32 /* * The BRANCH_EVENT is increment by 1 for each branch event. Such event is composed of * two entries in the BTB: a source and a target entry. The BTB is full after 4 branch * events. */ #define SMPL_PERIOD (4UL*256) /* * We use a small buffer size to exercise the overflow handler */ #define SMPL_BUF_NENTRIES 64 #define M_PMD(x) (1UL<<(x)) #define BTB_REGS_MASK (M_PMD(8)|M_PMD(9)|M_PMD(10)|M_PMD(11)|M_PMD(12)|M_PMD(13)|M_PMD(14)|M_PMD(15)|M_PMD(16)) static void *smpl_vaddr; static unsigned int entry_size; static int id; #if defined(__ECC) && defined(__INTEL_COMPILER) /* if you do not have this file, your compiler is too old */ #include #define hweight64(x) _m64_popcnt(x) #elif defined(__GNUC__) static __inline__ int hweight64 (unsigned long x) { unsigned long result; __asm__ ("popcnt %0=%1" : "=r" (result) : "r" (x)); return (int)result; } #else #error "you need to provide inline assembly from your compiler" #endif /* * we don't use static to make sure the compiler does not inline the function */ long func1(void) { return 0;} long do_test(unsigned long loop) { long sum = 0; while(loop--) { if (loop & 0x1) sum += func1(); else sum += loop; } return sum; } static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } /* * print content of sampling buffer * * XXX: using stdio to print from a signal handler is not safe with multi-threaded * applications */ #define safe_printf printf static void show_btb_reg(int j, pfm_ita2_pmd_reg_t reg, pfm_ita2_pmd_reg_t pmd16) { unsigned long bruflush, b1; int is_valid = reg.pmd8_15_ita2_reg.btb_b == 0 && reg.pmd8_15_ita2_reg.btb_mp == 0 ? 0 :1; b1 = (pmd16.pmd_val >> (4 + 4*(j-8))) & 0x1; bruflush = (pmd16.pmd_val >> (5 + 4*(j-8))) & 0x1; safe_printf("\tPMD%-2d: 0x%016lx b=%d mp=%d bru=%ld b1=%ld valid=%c\n", j, reg.pmd_val, reg.pmd8_15_ita2_reg.btb_b, reg.pmd8_15_ita2_reg.btb_mp, bruflush, b1, is_valid ? 'Y' : 'N'); if (!is_valid) return; if (reg.pmd8_15_ita2_reg.btb_b) { unsigned long addr; addr = (reg.pmd8_15_ita2_reg.btb_addr+b1)<<4; addr |= reg.pmd8_15_ita2_reg.btb_slot < 3 ? reg.pmd8_15_ita2_reg.btb_slot : 0; safe_printf("\t Source Address: 0x%016lx\n" "\t Taken=%c Prediction: %s\n\n", addr, reg.pmd8_15_ita2_reg.btb_slot < 3 ? 'Y' : 'N', reg.pmd8_15_ita2_reg.btb_mp ? "FE Failure" : bruflush ? "BE Failure" : "Success"); } else { safe_printf("\t Target Address: 0x%016lx\n\n", ((unsigned long)reg.pmd8_15_ita2_reg.btb_addr<<4)); } } static void show_btb(pfm_ita2_pmd_reg_t *btb, pfm_ita2_pmd_reg_t *pmd16) { int i, last; i = (pmd16->pmd16_ita2_reg.btbi_full) ? pmd16->pmd16_ita2_reg.btbi_bbi : 0; last = pmd16->pmd16_ita2_reg.btbi_bbi; safe_printf("btb_trace: i=%d last=%d bbi=%d full=%d\n", i, last,pmd16->pmd16_ita2_reg.btbi_bbi, pmd16->pmd16_ita2_reg.btbi_full); do { show_btb_reg(i+8, btb[i], *pmd16); i = (i+1) % 8; } while (i != last); } void process_smpl_buffer(void) { btb_hdr_t *hdr; btb_entry_t *ent; unsigned long pos; unsigned long smpl_entry = 0; pfm_ita2_pmd_reg_t *reg, *pmd16; unsigned long i; int ret; static unsigned long last_ovfl = ~0UL; hdr = (btb_hdr_t *)smpl_vaddr; /* * check that we are not diplaying the previous set of samples again. * Required to take care of the last batch of samples. */ if (hdr->hdr_overflows <= last_ovfl && last_ovfl != ~0UL) { printf("skipping identical set of samples %lu <= %lu\n", hdr->hdr_overflows, last_ovfl); return; } pos = (unsigned long)(hdr+1); /* * walk through all the entries recored in the buffer */ for(i=0; i < hdr->hdr_count; i++) { ret = 0; ent = (btb_entry_t *)pos; /* * print entry header */ safe_printf("Entry %ld PID:%d CPU:%d STAMP:0x%lx IIP:0x%016lx\n", smpl_entry++, ent->pid, ent->cpu, ent->tstamp, ent->ip); /* * point to first recorded register (always contiguous with entry header) */ reg = (pfm_ita2_pmd_reg_t*)(ent+1); /* * in this particular example, we have pmd8-pmd15 has the BTB. We have also * included pmd16 (BTB index) has part of the registers to record. This trick * allows us to get the index to decode the sequential order of the BTB. * * Recorded registers are always recorded in increasing order. So we know * that pmd16 is at a fixed offset (+8*sizeof(unsigned long)) from pmd8. */ pmd16 = reg+8; show_btb(reg, pmd16); /* * move to next entry */ pos += entry_size; } } static void overflow_handler(int n, struct siginfo *info, struct sigcontext *sc) { /* dangerous */ printf("Notification received\n"); process_smpl_buffer(); /* * And resume monitoring */ if (perfmonctl(id, PFM_RESTART,NULL, 0) == -1) { perror("PFM_RESTART"); exit(1); } } int main(void) { int ret; int type = 0; pfarg_reg_t pd[NUM_PMDS]; pfarg_reg_t pc[NUM_PMCS]; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_ita2_input_param_t ita2_inp; btb_ctx_arg_t ctx[1]; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; struct sigaction act; unsigned int i; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) { fatal_error("Can't initialize library\n"); } /* * Let's make sure we run this on the right CPU */ pfm_get_pmu_type(&type); if (type != PFMLIB_ITANIUM2_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with %s PMU\n", model); } /* * Install the overflow handler (SIGIO) */ memset(&act, 0, sizeof(act)); act.sa_handler = (sig_t)overflow_handler; sigaction (SIGIO, &act, 0); /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 0; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); memset(pd, 0, sizeof(pd)); memset(ctx, 0, sizeof(ctx)); /* * prepare parameters to library. we don't use any Itanium * specific features here. so the pfp_model is NULL. */ memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&ita2_inp,0, sizeof(ita2_inp)); /* * Before calling pfm_find_dispatch(), we must specify what kind * of branches we want to capture. We are interesteed in all the mispredicted branches, * therefore we program we set the various fields of the BTB config to: */ ita2_inp.pfp_ita2_btb.btb_used = 1; ita2_inp.pfp_ita2_btb.btb_ds = 0; ita2_inp.pfp_ita2_btb.btb_tm = 0x3; ita2_inp.pfp_ita2_btb.btb_ptm = 0x3; ita2_inp.pfp_ita2_btb.btb_ppm = 0x3; ita2_inp.pfp_ita2_btb.btb_brt = 0x0; ita2_inp.pfp_ita2_btb.btb_plm = PFM_PLM3; /* * To count the number of occurence of this instruction, we must * program a counting monitor with the IA64_TAGGED_INST_RETIRED_PMC8 * event. */ if (pfm_find_full_event("BRANCH_EVENT", &inp.pfp_events[0]) != PFMLIB_SUCCESS) { fatal_error("cannot find event BRANCH_EVENT\n"); } /* * set the (global) privilege mode: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = 1; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, &ita2_inp, &outp, NULL)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); } /* * We initialize the format specific information. * The format is identified by its UUID which must be copied * into the ctx_buf_fmt_id field. */ memcpy(ctx[0].ctx_arg.ctx_smpl_buf_id, buf_fmt_id, sizeof(pfm_uuid_t)); /* * the size of the buffer is indicated in bytes (not entries). * * The kernel will record into the buffer up to a certain point. * No partial samples are ever recorded. */ ctx[0].buf_arg.buf_size = 8192; /* * now create the context for self monitoring/per-task */ if (perfmonctl(0, PFM_CREATE_CONTEXT, ctx, 1) == -1 ) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } printf("Sampling buffer mapped at %p\n", ctx[0].ctx_arg.ctx_smpl_vaddr); smpl_vaddr = ctx[0].ctx_arg.ctx_smpl_vaddr; /* * extract our file descriptor */ id = ctx[0].ctx_arg.ctx_fd; /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events cause extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * the PMC controlling the event ALWAYS come first, that's why this loop * is safe even when extra PMC are needed to support a particular event. */ for (i=0; i < inp.pfp_event_count; i++) { pd[i].reg_num = pc[i].reg_num; } /* * indicate we want notification when buffer is full */ pc[0].reg_flags |= PFM_REGFL_OVFL_NOTIFY; /* * Now prepare the argument to initialize the PMD and the sampling period * We know we use only one PMD in this case, therefore pmd[0] corresponds * to our first event which is our sampling period. */ pd[0].reg_value = (~0UL) - SMPL_PERIOD +1; pd[0].reg_long_reset = (~0UL) - SMPL_PERIOD +1; pd[0].reg_short_reset = (~0UL) - SMPL_PERIOD +1; /* * indicate PMD to collect in each sample */ pc[0].reg_smpl_pmds[0] = BTB_REGS_MASK; /* * compute size of each sample: fixed-size header + all our BTB regs */ entry_size = sizeof(btb_entry_t)+(hweight64(BTB_REGS_MASK)<<3); /* * When our counter overflows, we want to BTB index to be reset, so that we keep * in sync. This is required to make it possible to interpret pmd16 on overflow * to avoid repeating the same branch several times. */ pc[0].reg_reset_pmds[0] = M_PMD(16); /* * reset pmd16 (BTB index), short and long reset value are set to zero as well * * We use slot 1 of our pd[] array for this. */ pd[1].reg_num = 16; pd[1].reg_value = 0UL; /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more thann coutning monitors. */ if (perfmonctl(id, PFM_WRITE_PMCS, pc, outp.pfp_pmc_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMCS errno %d\n",errno); } /* * we use 2 = 1 for the branch_event + 1 for the reset of PMD16. */ if (perfmonctl(id, PFM_WRITE_PMDS, pd, 2) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMDS errno %d\n",errno); } /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = getpid(); if (perfmonctl(id, PFM_LOAD_CONTEXT, &load_args, 1) == -1) { fatal_error("perfmonctl error PFM_LOAD_CONTEXT errno %d\n",errno); } /* * setup asynchronous notification on the file descriptor */ ret = fcntl(id, F_SETFL, fcntl(id, F_GETFL, 0) | O_ASYNC); if (ret == -1) { fatal_error("cannot set ASYNC: %s\n", strerror(errno)); } /* * get ownership of the descriptor */ ret = fcntl(id, F_SETOWN, getpid()); if (ret == -1) { fatal_error("cannot setown: %s\n", strerror(errno)); } /* * Let's roll now. */ pfm_self_start(id); do_test(100000); pfm_self_stop(id); /* * We must call the processing routine to cover the last entries recorded * in the sampling buffer. Note that the buffer may not be full at this point. * */ process_smpl_buffer(); /* * let's stop this now */ close(id); return 0; } papi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/ita2_opcode.c0000644000307100002310000002075613013651447022704 0ustar yarkhangraduate/* * ita2_opcode.c - example of how to use the opcode matcher with the Itanium2 PMU * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #include #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 #define MAX_PMU_NAME_LEN 32 /* * we don't use static to make sure the compiler does not inline the function */ int do_test(unsigned long loop) { unsigned long sum = 0; while(loop--) sum += loop; return sum; } static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } int main(void) { pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_ita2_input_param_t ita2_inp; pfarg_reg_t pd[NUM_PMDS]; pfarg_reg_t pc[NUM_PMCS]; pfarg_context_t ctx[1]; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; int ret; int type = 0; int id; unsigned int i; char name[MAX_EVT_NAME_LEN]; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) { fatal_error("Can't initialize library\n"); } /* * Let's make sure we run this on the right CPU */ pfm_get_pmu_type(&type); if (type != PFMLIB_ITANIUM2_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with the %s PMU\n", model); } /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 0; /* set to 1 for verbose */ pfm_set_options(&pfmlib_options); memset(pd, 0, sizeof(pd)); memset(pc, 0, sizeof(pc)); memset(ctx, 0, sizeof(ctx)); memset(&load_args, 0, sizeof(load_args)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&ita2_inp,0, sizeof(ita2_inp)); /* * We indicate that we are using the PMC8 opcode matcher. This is required * otherwise the library add PMC8 to the list of PMC to pogram during * pfm_dispatch_events(). */ ita2_inp.pfp_ita2_pmc8.opcm_used = 1; /* * We want to match all the br.cloop in our test function. * This branch is an IP-relative branch for which the major * opcode (bits [40-37]=4) and the btype field is 5 (which represents * bits[6-8]) so it is included in the match/mask fields of PMC8. * It is necessarily in a B slot. * * We don't care which operands are used with br.cloop therefore * the mask field of pmc8 is set such that only the 4 bits of the * opcode and 3 bits of btype must match exactly. This is accomplished by * clearing the top 4 bits and bits [6-8] of the mask field and setting the * remaining bits. Similarly, the match field only has the opcode value and btype * set according to the encoding of br.cloop, the * remaining bits are zero. Bit 60 of PMC8 is set to indicate * that we look only in B slots (this is the only possibility for * this instruction anyway). * * So the binary representation of the value for PMC8 is as follows: * * 6666555555555544444444443333333333222222222211111111110000000000 * 3210987654321098765432109876543210987654321098765432109876543210 * ---------------------------------------------------------------- * 0001010000000000000000101000000000000011111111111111000111111000 * * which yields a value of 0x1400028003fff1f8. * * Depending on the level of optimization to compile this code, it may * be that the count reported could be zero, if the compiler uses a br.cond * instead of br.cloop. * * * The 0x1 sets the ig_ad field to make sure we ignore any range restriction. * Also bit 2 must always be set */ ita2_inp.pfp_ita2_pmc8.pmc_val = 0x1400028003fff1fa; /* * To count the number of occurence of this instruction, we must * program a counting monitor with the IA64_TAGGED_INST_RETIRED_PMC8 * event. */ if (pfm_find_full_event("IA64_TAGGED_INST_RETIRED_IBRP0_PMC8", &inp.pfp_events[0]) != PFMLIB_SUCCESS) { fatal_error("cannot find event IA64_TAGGED_INST_RETIRED_IBRP0_PMC8\n"); } /* * set the privilege mode: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = 1; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, &ita2_inp, &outp, NULL)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); } /* * now create the context for self monitoring/per-task */ if (perfmonctl(0, PFM_CREATE_CONTEXT, ctx, 1) == -1 ) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * extract the unique identifier for our context, a regular file descriptor */ id = ctx[0].ctx_fd; /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events causes extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * the PMC controlling the event ALWAYS come first, that's why this loop * is safe even when extra PMC are needed to support a particular event. */ for (i=0; i < inp.pfp_event_count; i++) { pd[i].reg_num = pc[i].reg_num; } printf("event_count=%d id=%d\n", inp.pfp_event_count, id); /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more thann coutning monitors. */ if (perfmonctl(id, PFM_WRITE_PMCS, pc, outp.pfp_pmc_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMCS errno %d\n",errno); } if (perfmonctl(id, PFM_WRITE_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMDS errno %d\n",errno); } /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = getpid(); if (perfmonctl(id, PFM_LOAD_CONTEXT, &load_args, 1) == -1) { fatal_error("perfmonctl error PFM_LOAD_CONTEXT errno %d\n",errno); } /* * Let's roll now. */ pfm_self_start(id); do_test(100UL); pfm_self_stop(id); /* * now read the results */ if (perfmonctl(id, PFM_READ_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error("perfmonctl error READ_PMDS errno %d\n",errno); } /* * print the results */ pfm_get_full_event_name(&inp.pfp_events[0], name, MAX_EVT_NAME_LEN); printf("PMD%u %20lu %s\n", pd[0].reg_num, pd[0].reg_value, name); if (pd[0].reg_value != 0) printf("compiler used br.cloop\n"); else printf("compiler did not use br.cloop\n"); /* * let's stop this now */ close(id); return 0; } papi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/mont_rr.c0000644000307100002310000002633613013651447022174 0ustar yarkhangraduate/* * mont_rr.c - example of how to use data range restriction with the Dual-Core Itanium 2 PMU * * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #include #include #include #include #include #include #include #include #include #include #if defined(__ECC) && defined(__INTEL_COMPILER) /* if you do not have this file, your compiler is too old */ #include #define clear_psr_ac() __rum(1UL<<3) #elif defined(__GNUC__) static inline void clear_psr_ac(void) { __asm__ __volatile__("rum psr.ac;;" ::: "memory" ); } #else #error "You need to define clear_psr_ac() for your compiler" #endif #define TEST_DATA_COUNT 16 #define N_LOOP 100000000UL #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 #define MAX_PMU_NAME_LEN 32 /* * here we capture only misaligned_loads because it cannot * be measured with misaligned_stores_retired at the same time */ static char *event_list[]={ "misaligned_loads_retired", NULL }; typedef union { unsigned long l_tab[2]; unsigned int i_tab[4]; unsigned short s_tab[8]; unsigned char c_tab[16]; } test_data_t; static int do_test(test_data_t *data) { unsigned int *l, v; l = (unsigned int *)(data->c_tab+1); if (((unsigned long)l & 0x1) == 0) { printf("Data is not unaligned, can't run test\n"); return -1; } v = *l; v++; *l = v; return 0; } static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } int main(int argc, char **argv) { char **p; test_data_t *test_data, *test_data_fake; unsigned long range_start, range_end; int ret, type = 0; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_mont_input_param_t mont_inp; pfmlib_mont_output_param_t mont_outp; pfarg_reg_t pd[NUM_PMDS]; pfarg_reg_t pc[NUM_PMCS]; pfarg_dbreg_t dbrs[8]; pfarg_context_t ctx; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; unsigned int i; int id, num_pmcs = 0; char name[MAX_EVT_NAME_LEN]; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) fatal_error("Can't initialize library\n"); /* * Let's make sure we run this on the right CPU family */ pfm_get_pmu_type(&type); if (type != PFMLIB_MONTECITO_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with %s PMU\n", model); } /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 1; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); /* * now let's allocate the data structure we will be monitoring */ test_data = (test_data_t *)malloc(sizeof(test_data_t)*TEST_DATA_COUNT); if (test_data == NULL) fatal_error("cannot allocate test data structure"); test_data_fake = (test_data_t *)malloc(sizeof(test_data_t)*TEST_DATA_COUNT); if (test_data_fake == NULL) fatal_error("cannot allocate test data structure"); /* * Compute the range we are interested in */ range_start = (unsigned long)test_data; range_end = range_start + sizeof(test_data_t)*TEST_DATA_COUNT; memset(pd, 0, sizeof(pd)); memset(pc, 0, sizeof(pc)); memset(&ctx, 0, sizeof(ctx)); memset(&load_args, 0, sizeof(load_args)); /* * prepare parameters to library. we don't use any Itanium * specific features here. so the pfp_model is NULL. */ memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&mont_inp,0, sizeof(mont_inp)); memset(&mont_outp,0, sizeof(mont_outp)); /* * find requested event */ p = event_list; for (i=0; *p ; i++, p++) { if (pfm_find_event(*p, &inp.pfp_events[i].event) != PFMLIB_SUCCESS) { fatal_error("Cannot find %s event\n", *p); } } /* * set the privilege mode: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = i; /* * We use the library to figure out how to program the debug registers * to cover the data range we are interested in. The rr_end parameter * must point to the byte after the last element of the range (C-style range). * * Because of the masking mechanism and therefore alignment constraints used to implement * this feature, it may not be possible to exactly cover a given range. It may be that * the coverage exceeds the desired range. So it is possible to capture noise if * the surrounding addresses are also heavily used. You can figure out by how much the * actual range is off compared to the requested range by checking the rr_soff and rr_eoff * fields in rr_infos on return from the library call. * * Upon return, the rr_dbr array is programmed and the number of debug registers (not pairs) * used to cover the range is in rr_nbr_used. */ mont_inp.pfp_mont_drange.rr_used = 1; mont_inp.pfp_mont_drange.rr_limits[0].rr_start = range_start; mont_inp.pfp_mont_drange.rr_limits[0].rr_end = range_end; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, &mont_inp, &outp, &mont_outp)) != PFMLIB_SUCCESS) fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); printf("data range : [0x%016lx-0x%016lx): %d pair of debug registers used\n" "start_offset:-0x%lx end_offset:+0x%lx\n", range_start, range_end, mont_outp.pfp_mont_drange.rr_nbr_used >> 1, mont_outp.pfp_mont_drange.rr_infos[0].rr_soff, mont_outp.pfp_mont_drange.rr_infos[0].rr_eoff); printf("fake data range: [0x%016lx-0x%016lx)\n", (unsigned long)test_data_fake, (unsigned long)test_data_fake+sizeof(test_data_t)*TEST_DATA_COUNT); /* * now create the context for self monitoring/per-task */ if (perfmonctl(0, PFM_CREATE_CONTEXT, &ctx, 1) == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * extract the unique identifier for our context, a regular file descriptor */ id = ctx.ctx_fd; /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events causes extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++, num_pmcs++) { pc[num_pmcs].reg_num = outp.pfp_pmcs[i].reg_num; pc[num_pmcs].reg_value = outp.pfp_pmcs[i].reg_value; } /* * propagate the setup for the data debug registers. DBRS are mapped * at PMC264-PMC271 */ memset(dbrs, 0, sizeof(dbrs)); for (i=0; i < mont_outp.pfp_mont_drange.rr_nbr_used; i++) { dbrs[i].dbreg_num = mont_outp.pfp_mont_drange.rr_br[i].reg_num; dbrs[i].dbreg_value = mont_outp.pfp_mont_drange.rr_br[i].reg_value; } /* * figure out pmd mapping from output pmc */ for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more than coutning monitors. */ if (perfmonctl(id, PFM_WRITE_DBRS, dbrs, mont_outp.pfp_mont_drange.rr_nbr_used) == -1) { fatal_error( "child: perfmonctl error PFM_WRITE_DBRS errno %d\n",errno); } if (perfmonctl(id, PFM_WRITE_PMCS, pc, num_pmcs)) fatal_error("child: pfm_write_pmcs error errno %d\n",errno); if (perfmonctl(id, PFM_WRITE_PMDS, pd, outp.pfp_pmd_count)) fatal_error( "child: pfm_write_pmds error errno %d\n",errno); /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = getpid(); if (perfmonctl(id, PFM_LOAD_CONTEXT, &load_args, 1)) fatal_error("pfm_load_context error errno %d\n",errno); /* * Let's make sure that the hardware does the unaligned accesses (do not use the * kernel software handler otherwise the PMU won't see the unaligned fault). */ clear_psr_ac(); /* * Let's roll now. * * The idea behind this test is to have two dynamically allocated data structures * which are access in a unaligned fashion. But we want to capture only the unaligned * accesses on one of the two. So the debug registers are programmed to cover the * first one ONLY. Then we activate monotoring and access the two data structures. * This is an artificial example just to demonstrate how to use data address range * restrictions. */ pfm_self_start(id); for(i=0; i < N_LOOP; i++) { do_test(test_data); do_test(test_data_fake); } pfm_self_stop(id); /* * now read the results */ if (perfmonctl(id, PFM_READ_PMDS, pd, inp.pfp_event_count)) fatal_error("pfm_read_pmds error errno %d\n",errno); /* * print the results * * It is important to realize, that the first event we specified may not * be in PMD4. Not all events can be measured by any monitor. That's why * we need to use the pc[] array to figure out where event i was allocated. * * For this example, we expect to see a value of 1 for misaligned loads. * But it can be two when the test_data and test_data_fake * are allocated very close from each other and the range created with the debug * registers is larger then test_data. * */ for (i=0; i < inp.pfp_event_count; i++) { pfm_get_full_event_name(&inp.pfp_events[i], name, MAX_EVT_NAME_LEN); printf("PMD%-3u %20lu %s (expected %lu)\n", pd[i].reg_num, pd[i].reg_value, name, N_LOOP); if (pd[i].reg_value != N_LOOP) { printf("error: Result should be 1 for %s\n", name); break; } } /* * let's stop this now */ close(id); free(test_data); free(test_data_fake); return 0; } papi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/notify_self_fork.c0000755000307100002310000002032613013651447024052 0ustar yarkhangraduate/* * notify_self.c - example of how you can use overflow notifications * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * Modified by Phil Mucci to add the fork() * Adapted to v2.0 interface by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #include #include #include #define SMPL_PERIOD 1000000000UL static volatile unsigned long notification_received; #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS static pfarg_reg_t pd[NUM_PMDS]; static int ctx_fd; static char *event1_name; static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } static void sigio_handler(int n, struct siginfo *info, struct sigcontext *sc) { pfm_msg_t msg; int fd = ctx_fd; int r; if (fd != ctx_fd) { fatal_error("handler does not get valid file descriptor\n"); } if (event1_name && perfmonctl(fd, PFM_READ_PMDS, pd+1, 1) == -1) { fatal_error("PFM_READ_PMDS: %s", strerror(errno)); } r = read(fd, &msg, sizeof(msg)); if (r != sizeof(msg)) { fatal_error("cannot read overflow message: %s\n", strerror(errno)); } if (msg.type != PFM_MSG_OVFL) { fatal_error("unexpected msg type: %d\n",msg.type); } /* * XXX: risky to do printf() in signal handler! */ if (event1_name) printf("Notification %lu: %"PRIu64" %s\n", notification_received, pd[1].reg_value, event1_name); else printf("Notification %lu\n", notification_received); /* * At this point, the counter used for the sampling period has already * be reset by the kernel because we are in non-blocking mode, self-monitoring. */ /* * increment our notification counter */ notification_received++; /* * And resume monitoring */ if (perfmonctl(fd, PFM_RESTART,NULL, 0) == -1) { fatal_error("PFM_RESTART: %s", strerror(errno)); } } /* * infinite loop waiting for notification to get out */ void busyloop(void) { /* * busy loop to burn CPU cycles */ for(;notification_received < 3;) ; /* * forking causes the context to be shared with the child * When the child terminates, it closes its descriptor. * The parent's remains and notification keep on coming. */ if (fork() == 0) { printf("child terminates\n"); fflush(stdout); exit(0); } printf("after fork\n"); fflush(stdout); for(;notification_received < 6;) ; } int main(int argc, char **argv) { pfarg_context_t ctx[1]; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfarg_reg_t pc[NUM_PMCS]; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; struct sigaction act; unsigned int i, num_counters; size_t len; int ret; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) { printf("Can't initialize library\n"); exit(1); } /* * Install the signal handler (SIGIO) */ memset(&act, 0, sizeof(act)); act.sa_handler = (sig_t)sigio_handler; sigaction (SIGIO, &act, 0); /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); memset(pc, 0, sizeof(pc)); memset(ctx, 0, sizeof(ctx)); memset(&load_args, 0, sizeof(load_args)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); pfm_get_num_counters(&num_counters); if (pfm_get_cycle_event(&inp.pfp_events[0]) != PFMLIB_SUCCESS) fatal_error("cannot find cycle event\n"); if (pfm_get_inst_retired_event(&inp.pfp_events[1]) != PFMLIB_SUCCESS) fatal_error("cannot find inst retired event\n"); i = 2; /* * set the default privilege mode for all counters: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; if (i > num_counters) { i = num_counters; printf("too many events provided (max=%d events), using first %d event(s)\n", num_counters, i); } /* * how many counters we use */ inp.pfp_event_count = i; pfm_get_max_event_name_len(&len); event1_name = malloc(len+1); if (event1_name == NULL) fatal_error("cannot allocate event name\n"); pfm_get_full_event_name(&inp.pfp_events[1], event1_name, len+1); /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) { fatal_error("Cannot configure events: %s\n", pfm_strerror(ret)); } /* * now create the context for self monitoring/per-task */ if (perfmonctl(0, PFM_CREATE_CONTEXT, ctx, 1) == -1 ) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } ctx_fd = ctx->ctx_fd; /* * Now prepare the argument to initialize the PMDs and PMCS. * We use pfp_pmc_count to determine the number of registers to * setup. Note that this field can be >= pfp_event_count. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } for (i=0; i < inp.pfp_event_count; i++) { pd[i].reg_num = pc[i].reg_num; } /* * We want to get notified when the counter used for our first * event overflows */ pc[0].reg_flags |= PFM_REGFL_OVFL_NOTIFY; pc[0].reg_reset_pmds[0] |= 1UL << outp.pfp_pmcs[1].reg_num; /* * we arm the first counter, such that it will overflow * after SMPL_PERIOD events have been observed */ pd[0].reg_value = (~0UL) - SMPL_PERIOD + 1; pd[0].reg_long_reset = (~0UL) - SMPL_PERIOD + 1; pd[0].reg_short_reset = (~0UL) - SMPL_PERIOD + 1; /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more than counting monitors. */ if (perfmonctl(ctx_fd, PFM_WRITE_PMCS, pc, outp.pfp_pmc_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMCS errno %d\n",errno); } if (perfmonctl(ctx_fd, PFM_WRITE_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMDS errno %d\n",errno); } /* * we want to monitor ourself */ load_args.load_pid = getpid(); if (perfmonctl(ctx_fd, PFM_LOAD_CONTEXT, &load_args, 1) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMDS errno %d\n",errno); } /* * setup asynchronous notification on the file descriptor */ ret = fcntl(ctx_fd, F_SETFL, fcntl(ctx_fd, F_GETFL, 0) | O_ASYNC); if (ret == -1) { fatal_error("cannot set ASYNC: %s\n", strerror(errno)); } /* * get ownership of the descriptor */ ret = fcntl(ctx_fd, F_SETOWN, getpid()); if (ret == -1) { fatal_error("cannot setown: %s\n", strerror(errno)); } /* * Let's roll now */ pfm_self_start(ctx_fd); busyloop(); pfm_self_stop(ctx_fd); /* * free our context */ close(ctx_fd); return 0; } papi-5.5.1/src/libpfm-3.y/examples_ia64_v2.0/notify_self2.c0000644000307100002310000002054113013651447023107 0ustar yarkhangraduate/* * notify_self2.c - example of how you can use overflow notifications with F_SETSIG * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #include #include #include #define SMPL_PERIOD 1000000000UL static volatile unsigned long notification_received; #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS static pfarg_reg_t pd[NUM_PMDS]; static int ctx_fd; static char *event1_name; static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } static void sigio_handler(int n, struct siginfo *info, struct sigcontext *sc) { pfm_msg_t msg; int fd = info->si_fd; int r; if (fd != ctx_fd) { fatal_error("handler does not get valid file descriptor\n"); } if (perfmonctl(fd, PFM_READ_PMDS, pd+1, 1) == -1) { fatal_error("PFM_READ_PMDS: %s", strerror(errno)); } r = read(fd, &msg, sizeof(msg)); if (r != sizeof(msg)) { fatal_error("cannot read overflow message: %s\n", strerror(errno)); } if (msg.type != PFM_MSG_OVFL) { fatal_error("unexpected msg type: %d\n",msg.type); } /* * XXX: risky to do printf() in signal handler! */ if (event1_name) printf("Notification %lu: %"PRIu64" %s\n", notification_received, pd[1].reg_value, event1_name); else printf("Notification %lu\n", notification_received); /* * At this point, the counter used for the sampling period has already * be reset by the kernel because we are in non-blocking mode, self-monitoring. */ /* * increment our notification counter */ notification_received++; /* * And resume monitoring */ if (perfmonctl(fd, PFM_RESTART,NULL, 0) == -1) { fatal_error("PFM_RESTART: %s", strerror(errno)); } } /* * infinite loop waiting for notification to get out */ void busyloop(void) { /* * busy loop to burn CPU cycles */ for(;notification_received < 3;) ; } int main(int argc, char **argv) { pfarg_context_t ctx[1]; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfarg_reg_t pc[NUM_PMCS]; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; struct sigaction act; unsigned int i, num_counters; size_t len; int ret; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) { printf("Can't initialize library\n"); exit(1); } /* * Install the signal handler (SIGIO) */ memset(&act, 0, sizeof(act)); act.sa_handler = (sig_t)sigio_handler; sigaction (SIGIO, &act, 0); /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); memset(pc, 0, sizeof(pc)); memset(ctx, 0, sizeof(ctx)); memset(&load_args, 0, sizeof(load_args)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); pfm_get_num_counters(&num_counters); if (pfm_get_cycle_event(&inp.pfp_events[0]) != PFMLIB_SUCCESS) fatal_error("cannot find cycle event\n"); if (pfm_get_inst_retired_event(&inp.pfp_events[1]) != PFMLIB_SUCCESS) fatal_error("cannot find inst retired event\n"); i = 2; /* * set the default privilege mode for all counters: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; if (i > num_counters) { i = num_counters; printf("too many events provided (max=%d events), using first %d event(s)\n", num_counters, i); } /* * how many counters we use */ inp.pfp_event_count = i; if (i > 1) { pfm_get_max_event_name_len(&len); event1_name = malloc(len+1); if (event1_name == NULL) fatal_error("cannot allocate event name\n"); pfm_get_full_event_name(&inp.pfp_events[1], event1_name, len+1); } /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) { fatal_error("Cannot configure events: %s\n", pfm_strerror(ret)); } /* * now create the context for self monitoring/per-task */ if (perfmonctl(0, PFM_CREATE_CONTEXT, ctx, 1) == -1 ) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } ctx_fd = ctx->ctx_fd; /* * Now prepare the argument to initialize the PMDs and PMCS. * We use pfp_pmc_count to determine the number of registers to * setup. Note that this field can be >= pfp_event_count. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } for (i=0; i < inp.pfp_event_count; i++) { pd[i].reg_num = pc[i].reg_num; } /* * We want to get notified when the counter used for our first * event overflows */ pc[0].reg_flags |= PFM_REGFL_OVFL_NOTIFY; pc[0].reg_reset_pmds[0] |= 1UL << outp.pfp_pmcs[1].reg_num; /* * we arm the first counter, such that it will overflow * after SMPL_PERIOD events have been observed */ pd[0].reg_value = (~0UL) - SMPL_PERIOD + 1; pd[0].reg_long_reset = (~0UL) - SMPL_PERIOD + 1; pd[0].reg_short_reset = (~0UL) - SMPL_PERIOD + 1; /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more than counting monitors. */ if (perfmonctl(ctx_fd, PFM_WRITE_PMCS, pc, outp.pfp_pmc_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMCS errno %d\n",errno); } if (perfmonctl(ctx_fd, PFM_WRITE_PMDS, pd, inp.pfp_event_count) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMDS errno %d\n",errno); } /* * we want to monitor ourself */ load_args.load_pid = getpid(); if (perfmonctl(ctx_fd, PFM_LOAD_CONTEXT, &load_args, 1) == -1) { fatal_error("perfmonctl error PFM_WRITE_PMDS errno %d\n",errno); } /* * setup asynchronous notification on the file descriptor */ ret = fcntl(ctx_fd, F_SETFL, fcntl(ctx_fd, F_GETFL, 0) | O_ASYNC); if (ret == -1) { fatal_error("cannot set ASYNC: %s\n", strerror(errno)); } /* * get ownership of the descriptor */ ret = fcntl(ctx_fd, F_SETOWN, getpid()); if (ret == -1) { fatal_error("cannot setown: %s\n", strerror(errno)); } #ifndef _GNU_SOURCE #error "this program must be compiled with -D_GNU_SOURCE" #else /* * when you explicitely declare that you want a particular signal, * even with you use the default signal, the kernel will send more * information concerning the event to the signal handler. * * In particular, it will send the file descriptor from which the * event is originating which can be quite useful when monitoring * multiple tasks from a single thread. */ ret = fcntl(ctx_fd, F_SETSIG, SIGIO); if (ret == -1) { fatal_error("cannot setsig: %s\n", strerror(errno)); } #endif /* * Let's roll now */ pfm_self_start(ctx_fd); busyloop(); pfm_self_stop(ctx_fd); /* * free our context */ close(ctx_fd); return 0; } papi-5.5.1/src/libpfm-3.y/python/0000755000307100002310000000000013013651451016444 5ustar yarkhangraduatepapi-5.5.1/src/libpfm-3.y/python/src/0000755000307100002310000000000013013651451017233 5ustar yarkhangraduatepapi-5.5.1/src/libpfm-3.y/python/src/session.py0000644000307100002310000001611413013651451021273 0ustar yarkhangraduate#!/usr/bin/env python # # Copyright (c) 2008 Google, Inc. # Contributed by Arun Sharma # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), # to deal in the Software without restriction, including without limitation # the rights to use, copy, modify, merge, publish, distribute, sublicense, # and/or sell copies of the Software, and to permit persons to whom the # Software is furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice shall be included # in all copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR # OTHER DEALINGS IN THE SOFTWARE. # from perfmon import * from linux import sched import os import sys from threading import Thread # Shouldn't be necessary for python version >= 2.5 from Queue import Queue # http://aspn.activestate.com/ASPN/Cookbook/Python/Recipe/425445 def once(func): "A decorator that runs a function only once." def decorated(*args, **kwargs): try: return decorated._once_result except AttributeError: decorated._once_result = func(*args, **kwargs) return decorated._once_result return decorated @once def pfm_initialize_once(): # Initialize once opts = pfmlib_options_t() opts.pfm_verbose = 1 pfm_set_options(opts) pfm_initialize() # Common base class class Session: def __init__(self, n): self.system = System() pfm_initialize_once() # Setup context self.ctxts = [] self.fds = [] self.inps = [] self.outps = [] self.pmcs = [] self.pmds = [] for i in xrange(n): ctx = pfarg_ctx_t() ctx.zero() ctx.ctx_flags = self.ctx_flags fd = pfm_create_context(ctx, None, None, 0) self.ctxts.append(ctx) self.fds.append(fd) def __del__(self): if self.__dict__.has_key("fds"): for fd in self.fds: os.close(fd) def dispatch_event_one(self, events, which): # Select and dispatch events inp = pfmlib_input_param_t() for i in xrange(0, len(events)): pfm_find_full_event(events[i], inp.pfp_events[i]) inp.pfp_dfl_plm = self.default_pl inp.pfp_flags = self.pfp_flags outp = pfmlib_output_param_t() cnt = len(events) inp.pfp_event_count = cnt pfm_dispatch_events(inp, None, outp, None) # pfp_pm_count may be > cnt cnt = outp.pfp_pmc_count pmcs = pmc(outp.pfp_pmc_count) pmds = pmd(outp.pfp_pmd_count) for i in xrange(outp.pfp_pmc_count): npmc = pfarg_pmc_t() npmc.reg_num = outp.pfp_pmcs[i].reg_num npmc.reg_value = outp.pfp_pmcs[i].reg_value pmcs[i] = npmc self.npmds = outp.pfp_pmd_count for i in xrange(outp.pfp_pmd_count): npmd = pfarg_pmd_t() npmd.reg_num = outp.pfp_pmds[i].reg_num pmds[i] = npmd # Program PMCs and PMDs fd = self.fds[which] pfm_write_pmcs(fd, pmcs, outp.pfp_pmc_count) pfm_write_pmds(fd, pmds, outp.pfp_pmd_count) # Save all the state in various vectors self.inps.append(inp) self.outps.append(outp) self.pmcs.append(pmcs) self.pmds.append(pmds) def dispatch_events(self, events): for i in xrange(len(self.fds)): self.dispatch_event_one(events, i) def load_one(self, i): fd = self.fds[i] load = pfarg_load_t() load.zero() load.load_pid = self.targets[i] try: pfm_load_context(fd, load) except OSError, err: import errno if (err.errno == errno.EBUSY): err.strerror = "Another conflicting perfmon session?" raise err def load(self): for i in xrange(len(self.fds)): self.load_one(i) def start_one(self, i): pfm_start(self.fds[i], None) def start(self): for i in xrange(len(self.fds)): self.start_one(i) def stop_one(self, i): fd = self.fds[i] pmds = self.pmds[i] pfm_stop(fd) pfm_read_pmds(fd, pmds, self.npmds) def stop(self): for i in xrange(len(self.fds)): self.stop_one(i) class PerfmonThread(Thread): def __init__(self, session, i, cpu): Thread.__init__(self) self.cpu = cpu self.session = session self.index = i self.done = 0 self.started = 0 def run(self): queue = self.session.queues[self.index] exceptions = self.session.exceptions[self.index] cpu_set = sched.cpu_set_t() cpu_set.set(self.cpu) sched.setaffinity(0, cpu_set) while not self.done: # wait for a command from the master method = queue.get() try: method(self.session, self.index) except: exceptions.put(sys.exc_info()) queue.task_done() break queue.task_done() def run_in_other_thread(func): "A decorator that runs a function in another thread (second argument)" def decorated(*args, **kwargs): self = args[0] i = args[1] # Tell thread i to call func() self.queues[i].put(func) self.queues[i].join() if not self.exceptions[i].empty(): exc = self.exceptions[i].get() # Let the main thread know we had an exception self.exceptions[i].put(exc) print "CPU: %d, exception: %s" % (i, exc) raise exc[1] return decorated class SystemWideSession(Session): def __init__(self, cpulist): self.default_pl = PFM_PLM3 | PFM_PLM0 self.targets = cpulist self.ctx_flags = PFM_FL_SYSTEM_WIDE self.pfp_flags = PFMLIB_PFP_SYSTEMWIDE self.threads = [] self.queues = [] self.exceptions = [] n = len(cpulist) for i in xrange(n): t = PerfmonThread(self, i, cpulist[i]) self.threads.append(t) self.queues.append(Queue(0)) self.exceptions.append(Queue(0)) t.start() Session.__init__(self, n) def __del__(self): self.cleanup() Session.__del__(self) def cleanup(self): for t in self.threads: t.done = 1 # join only threads with no exceptions if self.exceptions[t.index].empty(): if t.started: self.stop_one(t.index) else: self.wakeup(t.index) t.join() self.threads = [] @run_in_other_thread def load_one(self, i): Session.load_one(self, i) @run_in_other_thread def start_one(self, i): Session.start_one(self, i) self.threads[i].started = 1 @run_in_other_thread def stop_one(self, i): Session.stop_one(self, i) self.threads[i].started = 0 @run_in_other_thread def wakeup(self, i): "Do nothing. Just wakeup the other thread" pass class PerThreadSession(Session): def __init__(self, pid): self.targets = [pid] self.default_pl = PFM_PLM3 self.ctx_flags = 0 self.pfp_flags = 0 Session.__init__(self, 1) def __del__(self): Session.__del__(self) papi-5.5.1/src/libpfm-3.y/python/src/perfmon_int.i0000644000307100002310000001276513013651451021740 0ustar yarkhangraduate/* * Copyright (c) 2008 Google, Inc. * Contributed by Arun Sharma * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Python Bindings for perfmon. */ %module perfmon_int %{ #include #include static PyObject *libpfm_err; %} %include "carrays.i" %include "cstring.i" %include /* Some typemaps for corner cases SWIG can't handle */ /* Convert from Python --> C */ %typemap(memberin) pfmlib_event_t[ANY] { int i; for (i = 0; i < $1_dim0; i++) { $1[i] = $input[i]; } } %typemap(out) pfmlib_event_t[ANY] { int len, i; len = $1_dim0; $result = PyList_New(len); for (i = 0; i < len; i++) { PyObject *o = SWIG_NewPointerObj(SWIG_as_voidptr(&$1[i]), SWIGTYPE_p_pfmlib_event_t, 0 | 0 ); PyList_SetItem($result, i, o); } } /* Convert from Python --> C */ %typemap(memberin) pfmlib_reg_t[ANY] { int i; for (i = 0; i < $1_dim0; i++) { $1[i] = $input[i]; } } %typemap(out) pfmlib_reg_t[ANY] { int len, i; len = $1_dim0; $result = PyList_New(len); for (i = 0; i < len; i++) { PyObject *o = SWIG_NewPointerObj(SWIG_as_voidptr(&$1[i]), SWIGTYPE_p_pfmlib_reg_t, 0 | 0 ); PyList_SetItem($result, i, o); } } /* Convert libpfm errors into exceptions */ %typemap(out) os_err_t { if (result == -1) { PyErr_SetFromErrno(PyExc_OSError); SWIG_fail; } resultobj = SWIG_From_int((int)(result)); }; %typemap(out) pfm_err_t { if (result != PFMLIB_SUCCESS) { PyObject *obj = Py_BuildValue("(i,s)", result, pfm_strerror(result)); PyErr_SetObject(libpfm_err, obj); SWIG_fail; } else { PyErr_Clear(); } resultobj = SWIG_From_int((int)(result)); } /* Convert libpfm errors into exceptions */ %typemap(out) os_err_t { if (result == -1) { PyErr_SetFromErrno(PyExc_OSError); SWIG_fail; } resultobj = SWIG_From_int((int)(result)); }; %typemap(out) pfm_err_t { if (result != PFMLIB_SUCCESS) { PyObject *obj = Py_BuildValue("(i,s)", result, pfm_strerror(result)); PyErr_SetObject(libpfm_err, obj); SWIG_fail; } else { PyErr_Clear(); } resultobj = SWIG_From_int((int)(result)); } %cstring_output_maxsize(char *name, size_t maxlen) %cstring_output_maxsize(char *name, int maxlen) %extend pfmlib_regmask_t { unsigned int weight() { unsigned int w = 0; pfm_regmask_weight($self, &w); return w; } } /* Kernel interface */ %include %array_class(pfarg_pmc_t, pmc) %array_class(pfarg_pmd_t, pmd) /* Library interface */ %include %extend pfarg_ctx_t { void zero() { memset(self, 0, sizeof(self)); } } %extend pfarg_load_t { void zero() { memset(self, 0, sizeof(self)); } } %init %{ libpfm_err = PyErr_NewException("perfmon.libpfmError", NULL, NULL); PyDict_SetItemString(d, "libpfmError", libpfm_err); %} %inline %{ /* Helper functions to avoid pointer classes */ int pfm_py_get_pmu_type(void) { int tmp = -1; pfm_get_pmu_type(&tmp); return tmp; } unsigned int pfm_py_get_hw_counter_width(void) { unsigned int tmp = 0; pfm_get_hw_counter_width(&tmp); return tmp; } unsigned int pfm_py_get_num_events(void) { unsigned int tmp = 0; pfm_get_num_events(&tmp); return tmp; } int pfm_py_get_event_code(int idx) { int tmp = 0; pfm_get_event_code(idx, &tmp); return tmp; } unsigned int pfm_py_get_num_event_masks(int idx) { unsigned int tmp = 0; pfm_get_num_event_masks(idx, &tmp); return tmp; } unsigned int pfm_py_get_event_mask_code(int idx, int i) { unsigned int tmp = 0; pfm_get_event_mask_code(idx, i, &tmp); return tmp; } #define PFMON_MAX_EVTNAME_LEN 128 PyObject *pfm_py_get_event_name(int idx) { char name[PFMON_MAX_EVTNAME_LEN]; pfm_get_event_name(idx, name, PFMON_MAX_EVTNAME_LEN); return PyString_FromString(name); } PyObject *pfm_py_get_event_mask_name(int idx, int i) { char name[PFMON_MAX_EVTNAME_LEN]; pfm_get_event_mask_name(idx, i, name, PFMON_MAX_EVTNAME_LEN); return PyString_FromString(name); } PyObject *pfm_py_get_event_description(int idx) { char *desc; PyObject *ret; pfm_get_event_description(idx, &desc); ret = PyString_FromString(desc); free(desc); return ret; } PyObject *pfm_py_get_event_mask_description(int idx, int i) { char *desc; PyObject *ret; pfm_get_event_mask_description(idx, i, &desc); ret = PyString_FromString(desc); free(desc); return ret; } %} papi-5.5.1/src/libpfm-3.y/python/src/__init__.py0000644000307100002310000000010213013651451021335 0ustar yarkhangraduatefrom perfmon_int import * from pmu import * from session import * papi-5.5.1/src/libpfm-3.y/python/src/pmu.py0000644000307100002310000000663513013651451020420 0ustar yarkhangraduate#!/usr/bin/env python # # Copyright (c) 2008 Google, Inc. # Contributed by Arun Sharma # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), # to deal in the Software without restriction, including without limitation # the rights to use, copy, modify, merge, publish, distribute, sublicense, # and/or sell copies of the Software, and to permit persons to whom the # Software is furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice shall be included # in all copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR # OTHER DEALINGS IN THE SOFTWARE. # import os from perfmon import * def public_members(self): s = "{ " for k, v in self.__dict__.iteritems(): if not k[0] == '_': s += "%s : %s, " % (k, v) s += " }" return s class System: def __init__(self): self.ncpus = os.sysconf('SC_NPROCESSORS_ONLN') self.pmu = PMU() def __repr__(self): return public_members(self) class Event: def __init__(self): pass def __repr__(self): return '\n' + public_members(self) class EventMask: def __init__(self): pass def __repr__(self): return '\n\t' + public_members(self) class PMU: def __init__(self): pfm_initialize() self.type = pfm_py_get_pmu_type() self.name = pfm_get_pmu_name(PFMON_MAX_EVTNAME_LEN)[1] self.width = pfm_py_get_hw_counter_width() # What does the PMU support? self.__implemented_pmcs = pfmlib_regmask_t() self.__implemented_pmds = pfmlib_regmask_t() self.__implemented_counters = pfmlib_regmask_t() pfm_get_impl_pmcs(self.__implemented_pmcs) pfm_get_impl_pmds(self.__implemented_pmds) pfm_get_impl_counters(self.__implemented_counters) self.implemented_pmcs = self.__implemented_pmcs.weight() self.implemented_pmds = self.__implemented_pmds.weight() self.implemented_counters = self.__implemented_counters.weight() self.__events = None def __parse_events(self): nevents = pfm_py_get_num_events() self.__events = [] for idx in range(0, nevents): e = Event() e.name = pfm_py_get_event_name(idx) e.code = pfm_py_get_event_code(idx) e.__counters = pfmlib_regmask_t() pfm_get_event_counters(idx, e.__counters) # Now the event masks e.masks = [] nmasks = pfm_py_get_num_event_masks(idx) for mask_idx in range(0, nmasks): em = EventMask() em.name = pfm_py_get_event_mask_name(idx, mask_idx) em.code = pfm_py_get_event_mask_code(idx, mask_idx) em.desc = pfm_py_get_event_mask_description(idx, mask_idx) e.masks.append(em) self.__events.append(e) def events(self): if not self.__events: self.__parse_events() return self.__events def __repr__(self): return public_members(self) if __name__ == '__main__': from perfmon import * s = System() print s print s.pmu.events() papi-5.5.1/src/libpfm-3.y/python/Makefile0000644000307100002310000000242313013651451020105 0ustar yarkhangraduate# # Copyright (c) 2008 Google, Inc. # Contributed by Arun Sharma # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies # of the Software, and to permit persons to whom the Software is furnished to do so, # subject to the following conditions: # # The above copyright notice and this permission notice shall be included in all # copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, # INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A # PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT # HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE # OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # all: ./setup.py build install: ./setup.py install clean: $(RM) src/perfmon_int_wrap.c src/perfmon_int.py src/*.pyc $(RM) -r build papi-5.5.1/src/libpfm-3.y/python/README0000644000307100002310000000037113013651451017325 0ustar yarkhangraduateRequirements: To use the python bindings, you need the following packages: 1. swig (http://www.swig.org) 2. python-dev (http://www.python.org) 3. pycpuid (http://code.google.com/p/pycpuid) linux.sched is python package that comes with pycpuid. papi-5.5.1/src/libpfm-3.y/python/self.py0000755000307100002310000000401213013651451017747 0ustar yarkhangraduate#!/usr/bin/env python # # Copyright (c) 2008 Google, Inc. # Contributed by Arun Sharma # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), # to deal in the Software without restriction, including without limitation # the rights to use, copy, modify, merge, publish, distribute, sublicense, # and/or sell copies of the Software, and to permit persons to whom the # Software is furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice shall be included # in all copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR # OTHER DEALINGS IN THE SOFTWARE. # # Self monitoring example. Copied from self.c import os from optparse import OptionParser import random import errno from perfmon import * if __name__ == '__main__': parser = OptionParser() parser.add_option("-e", "--events", help="Events to use", action="store", dest="events") (options, args) = parser.parse_args() s = PerThreadSession(int(os.getpid())) if options.events: events = options.events.split(",") else: raise "You need to specify events to monitor" s.dispatch_events(events) s.load() s.start() # code to be measured # # note that this is not identical to what examples/self.c does # thus counts will be different in the end for i in range(1, 10000000): random.random() s.stop() # read the counts for i in xrange(s.npmds): print """PMD%d\t%lu""" % (s.pmds[0][i].reg_num, s.pmds[0][i].reg_value) papi-5.5.1/src/libpfm-3.y/python/sys.py0000755000307100002310000000437313013651451017646 0ustar yarkhangraduate#!/usr/bin/env python # # Copyright (c) 2008 Google, Inc. # Contributed by Arun Sharma # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), # to deal in the Software without restriction, including without limitation # the rights to use, copy, modify, merge, publish, distribute, sublicense, # and/or sell copies of the Software, and to permit persons to whom the # Software is furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice shall be included # in all copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR # OTHER DEALINGS IN THE SOFTWARE. # # System wide monitoring example. Copied from syst.c # # Run as: ./sys.py -c cpulist -e eventlist import sys import os from optparse import OptionParser import time from perfmon import * if __name__ == '__main__': parser = OptionParser() parser.add_option("-e", "--events", help="Events to use", action="store", dest="events") parser.add_option("-c", "--cpulist", help="CPUs to monitor", action="store", dest="cpulist") parser.set_defaults(cpu=0) (options, args) = parser.parse_args() cpus = options.cpulist.split(',') cpus = [ int(c) for c in cpus ] try: s = SystemWideSession(cpus) if options.events: events = options.events.split(",") else: raise "You need to specify events to monitor" s.dispatch_events(events) s.load() # Measuring loop for i in range(1, 10): s.start() time.sleep(1) s.stop() # Print the counts for cpu in xrange(len(cpus)): for i in xrange(s.npmds): print "CPU%d.PMD%d\t%lu""" % (cpu, s.pmds[cpu][i].reg_num, s.pmds[cpu][i].reg_value) finally: s.cleanup() papi-5.5.1/src/libpfm-3.y/python/setup.py0000755000307100002310000000124013013651451020156 0ustar yarkhangraduate#!/usr/bin/env python from distutils.core import setup, Extension from distutils.command.install_data import install_data setup(name='perfmon', version='0.1', author='Arun Sharma', author_email='arun.sharma@google.com', description='libpfm wrapper', packages=['perfmon'], package_dir={ 'perfmon' : 'src' }, py_modules=['perfmon.perfmon_int'], ext_modules=[Extension('perfmon._perfmon_int', sources = ['src/perfmon_int.i'], libraries = ['pfm'], library_dirs = ['../lib'], include_dirs = ['../include'], swig_opts=['-I../include'])]) papi-5.5.1/src/libpfm-3.y/Makefile0000644000307100002310000000432113013651447016570 0ustar yarkhangraduate# # Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. # Contributed by Stephane Eranian # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies # of the Software, and to permit persons to whom the Software is furnished to do so, # subject to the following conditions: # # The above copyright notice and this permission notice shall be included in all # copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, # INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A # PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT # HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE # OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # # # Look in config.mk for options # TOPDIR := $(shell if [ "$$PWD" != "" ]; then echo $$PWD; else pwd; fi) include config.mk DIRS=lib include docs EXAMPLES_DIRS = examples_v2.x ifneq ($(CONFIG_PFMLIB_OLD_PFMV2),y) EXAMPLES_DIRS += examples_v3.x endif ifeq ($(ARCH),ia64) DIRS +=examples_ia64_v2.0 endif ifeq ($(SYS),Linux) DIRS +=libpfms endif DIRS += $(EXAMPLES_DIRS) all: @echo Compiling for \'$(ARCH)\' target @set -e ; for d in $(DIRS) ; do $(MAKE) -C $$d $@ ; done lib: $(MAKE) -C lib clean: @set -e ; for d in $(DIRS) ; do $(MAKE) -C $$d $@ ; done distclean: clean depend: @set -e ; for d in $(DIRS) ; do $(MAKE) -C $$d $@ ; done tar: clean a=`basename $$PWD`; cd ..; tar zcf $$a.tar.gz $$a; echo generated ../$$a.tar.gz; tarcvs: clean a=`basename $$PWD`; cd ..; tar --exclude=CVS -zcf $$a.tar.gz $$a; echo generated ../$$a.tar.gz; install: @set -e ; for d in $(DIRS) ; do $(MAKE) -C $$d $@ ; done install_examples: @set -e ; for d in $(EXAMPLES_DIRS) ; do $(MAKE) -C $$d $@ ; done .PHONY: tar tarcvs lib # DO NOT DELETE papi-5.5.1/src/libpfm-3.y/libpfms/0000755000307100002310000000000013013651451016557 5ustar yarkhangraduatepapi-5.5.1/src/libpfm-3.y/libpfms/lib/0000755000307100002310000000000013013651451017325 5ustar yarkhangraduatepapi-5.5.1/src/libpfm-3.y/libpfms/lib/Makefile0000644000307100002310000000515613013651450020773 0ustar yarkhangraduate# # Copyright (c) 2006 Hewlett-Packard Development Company, L.P. # Contributed by Stephane Eranian # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies # of the Software, and to permit persons to whom the Software is furnished to do so, # subject to the following conditions: # # The above copyright notice and this permission notice shall be included in all # copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, # INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A # PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT # HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE # OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # TOPDIR := $(shell if [ "$$PWD" != "" ]; then echo $$PWD; else pwd; fi)/../.. include $(TOPDIR)/config.mk include $(TOPDIR)/rules.mk CFLAGS+= -pthread -D_GNU_SOURCE LDFLAGS+=-static PFMSINCDIR=../include # # Library version # VERSION=0 REVISION=1 AGE=0 SRCS=libpfms.c HEADERS=../include/libpfms.h ALIBPFM=libpfms.a TARGETS=$(ALIBPFM) ifneq ($(CONFIG_PFMLIB_ARCH_CRAYX2),y) SLIBPFM=libpfms.so.$(VERSION).$(REVISION).$(AGE) VLIBPFM=libpfms.so.$(VERSION) endif OBJS=$(SRCS:.c=.o) SOBJS=$(OBJS:.o=.lo) # # assume that if llibpfm built static, libpfms should # also be static, i.e., likely platform does not support # shared libraries. # ifeq ($(CONFIG_PFMLIB_SHARED),y) TARGETS += $(SLIBPFM) endif ifeq ($(SYS),Linux) SLDFLAGS=-shared -Wl,-soname -Wl,libpfms.so.$(VERSION) endif CFLAGS+=-I$(PFMSINCDIR) all: $(TARGETS) $(OBJS) $(SOBJS): $(HEADERS) $(TOPDIR)/config.mk $(TOPDIR)/rules.mk Makefile libpfms.a: $(OBJS) $(RM) $@ $(AR) cru $@ $(OBJS) $(SLIBPFM): $(SOBJS) $(CC) $(CFLAGS) $(SLDFLAGS) -o $@ $(SOBJS) $(LN) -sf $@ libpfms.so.$(VERSION) clean: $(RM) -f *.o *.lo *.a *.so* *~ distclean: clean install: $(TARGETS) install: -mkdir -p $(DESTDIR)$(LIBDIR) $(INSTALL) -m 644 $(ALIBPFM) $(DESTDIR)$(LIBDIR) $(INSTALL) $(SLIBPFM) $(DESTDIR)$(LIBDIR) cd $(DESTDIR)$(LIBDIR); $(LN) $(SLIBPFM) $(VLIBPFM) cd $(DESTDIR)$(LIBDIR); $(LN) $(SLIBPFM) libpfms.so -mkdir -p $(DESTDIR)$(INCDIR)/perfmon $(INSTALL) -m 644 $(HEADERS) $(DESTDIR)$(INCDIR)/perfmon papi-5.5.1/src/libpfm-3.y/libpfms/lib/libpfms.c0000644000307100002310000004324613013651451021136 0ustar yarkhangraduate#include #include #include #include #include #include #include #include #include #include #include #include #include "libpfms.h" //#define dprint(format, arg...) fprintf(stderr, "%s.%d: " format , __FUNCTION__ , __LINE__, ## arg) #define dprint(format, arg...) typedef enum { CMD_NONE, CMD_CTX, CMD_LOAD, CMD_UNLOAD, CMD_WPMCS, CMD_WPMDS, CMD_RPMDS, CMD_STOP, CMD_START, CMD_CLOSE } pfms_cmd_t; typedef struct _barrier { pthread_mutex_t mutex; pthread_cond_t cond; uint32_t counter; uint32_t max; uint64_t generation; /* avoid race condition on wake-up */ } barrier_t; typedef struct { uint32_t cpu; uint32_t fd; void *smpl_vaddr; size_t smpl_buf_size; } pfms_cpu_t; typedef struct _pfms_thread { uint32_t cpu; pfms_cmd_t cmd; void *data; uint32_t ndata; sem_t cmd_sem; int ret; pthread_t tid; barrier_t *barrier; } pfms_thread_t; typedef struct { barrier_t barrier; uint32_t ncpus; } pfms_session_t; static uint32_t ncpus; static pfms_thread_t *tds; static pthread_mutex_t tds_lock = PTHREAD_MUTEX_INITIALIZER; static int barrier_init(barrier_t *b, uint32_t count) { int r; r = pthread_mutex_init(&b->mutex, NULL); if (r == -1) return -1; r = pthread_cond_init(&b->cond, NULL); if (r == -1) return -1; b->max = b->counter = count; b->generation = 0; return 0; } static void cleanup_barrier(void *arg) { barrier_t *b = (barrier_t *)arg; int r; r = pthread_mutex_unlock(&b->mutex); dprint("free barrier mutex r=%d\n", r); (void) r; } static int barrier_wait(barrier_t *b) { uint64_t generation; int oldstate; pthread_cleanup_push(cleanup_barrier, b); pthread_mutex_lock(&b->mutex); pthread_testcancel(); if (--b->counter == 0) { /* reset barrier */ b->counter = b->max; /* * bump generation number, this avoids thread getting stuck in the * wake up loop below in case a thread just out of the barrier goes * back in right away before all the thread from the previous "round" * have "escaped". */ b->generation++; pthread_cond_broadcast(&b->cond); } else { generation = b->generation; pthread_setcancelstate(PTHREAD_CANCEL_ENABLE, &oldstate); while (b->counter != b->max && generation == b->generation) { pthread_cond_wait(&b->cond, &b->mutex); } pthread_setcancelstate(oldstate, NULL); } pthread_mutex_unlock(&b->mutex); pthread_cleanup_pop(0); return 0; } /* * placeholder for pthread_setaffinity_np(). This stuff is ugly * and I could not figure out a way to get it compiled while also preserving * the pthread_*cancel(). There are issues with LinuxThreads and NPTL. I * decided to quit on this and implement my own affinity call until this * settles. */ static int pin_cpu(uint32_t cpu) { uint64_t *mask; size_t size; pid_t pid; int ret; pid = syscall(__NR_gettid); size = ncpus * sizeof(uint64_t); mask = calloc(1, size); if (mask == NULL) { dprint("CPU%u: cannot allocate bitvector\n", cpu); return -1; } mask[cpu>>6] = 1ULL << (cpu & 63); ret = syscall(__NR_sched_setaffinity, pid, size, mask); free(mask); return ret; } static void pfms_thread_mainloop(void *arg) { long k = (long )arg; uint32_t mycpu = (uint32_t)k; pfarg_ctx_t myctx, *ctx; pfarg_load_t load_args; int fd = -1; pfms_thread_t *td; sem_t *cmd_sem; int ret = 0; memset(&load_args, 0, sizeof(load_args)); load_args.load_pid = mycpu; td = tds+mycpu; ret = pin_cpu(mycpu); dprint("CPU%u wthread created and pinned ret=%d\n", mycpu, ret); cmd_sem = &tds[mycpu].cmd_sem; for(;;) { dprint("CPU%u waiting for cmd\n", mycpu); sem_wait(cmd_sem); switch(td->cmd) { case CMD_NONE: ret = 0; break; case CMD_CTX: /* * copy context to get private fd */ ctx = td->data; myctx = *ctx; fd = pfm_create_context(&myctx, NULL, NULL, 0); ret = fd < 0 ? -1 : 0; dprint("CPU%u CMD_CTX ret=%d errno=%d fd=%d\n", mycpu, ret, errno, fd); break; case CMD_LOAD: ret = pfm_load_context(fd, &load_args); dprint("CPU%u CMD_LOAD ret=%d errno=%d fd=%d\n", mycpu, ret, errno, fd); break; case CMD_UNLOAD: ret = pfm_unload_context(fd); dprint("CPU%u CMD_UNLOAD ret=%d errno=%d fd=%d\n", mycpu, ret, errno, fd); break; case CMD_START: ret = pfm_start(fd, NULL); dprint("CPU%u CMD_START ret=%d errno=%d fd=%d\n", mycpu, ret, errno, fd); break; case CMD_STOP: ret = pfm_stop(fd); dprint("CPU%u CMD_STOP ret=%d errno=%d fd=%d\n", mycpu, ret, errno, fd); break; case CMD_WPMCS: ret = pfm_write_pmcs(fd,(pfarg_pmc_t *)td->data, td->ndata); dprint("CPU%u CMD_WPMCS ret=%d errno=%d fd=%d\n", mycpu, ret, errno, fd); break; case CMD_WPMDS: ret = pfm_write_pmds(fd,(pfarg_pmd_t *)td->data, td->ndata); dprint("CPU%u CMD_WPMDS ret=%d errno=%d fd=%d\n", mycpu, ret, errno, fd); break; case CMD_RPMDS: ret = pfm_read_pmds(fd,(pfarg_pmd_t *)td->data, td->ndata); dprint("CPU%u CMD_RPMDS ret=%d errno=%d fd=%d\n", mycpu, ret, errno, fd); break; case CMD_CLOSE: dprint("CPU%u CMD_CLOSE fd=%d\n", mycpu, fd); ret = close(fd); fd = -1; break; default: break; } td->ret = ret; dprint("CPU%u td->ret=%d\n", mycpu, ret); barrier_wait(td->barrier); } } static int create_one_wthread(int cpu) { int ret; sem_init(&tds[cpu].cmd_sem, 0, 0); ret = pthread_create(&tds[cpu].tid, NULL, (void *(*)(void *))pfms_thread_mainloop, (void *)(long)cpu); return ret; } /* * must be called with tds_lock held */ static int create_wthreads(uint64_t *cpu_list, uint32_t n) { uint64_t v; uint32_t i,k, cpu; int ret = 0; for(k=0, cpu = 0; k < n; k++, cpu+= 64) { v = cpu_list[k]; for(i=0; v && i < 63; i++, v>>=1, cpu++) { if ((v & 0x1) && tds[cpu].tid == 0) { ret = create_one_wthread(cpu); if (ret) break; } } } if (ret) dprint("cannot create wthread on CPU%u\n", cpu); return ret; } int pfms_initialize(void) { printf("cpu_t=%zu thread=%zu session_t=%zu\n", sizeof(pfms_cpu_t), sizeof(pfms_thread_t), sizeof(pfms_session_t)); ncpus = (uint32_t)sysconf(_SC_NPROCESSORS_ONLN); if (ncpus == -1) { dprint("cannot retrieve number of online processors\n"); return -1; } dprint("configured for %u CPUs\n", ncpus); /* * XXX: assuming CPU are contiguously indexed */ tds = calloc(ncpus, sizeof(*tds)); if (tds == NULL) { dprint("cannot allocate thread descriptors\n"); return -1; } return 0; } int pfms_create(uint64_t *cpu_list, size_t n, pfarg_ctx_t *ctx, pfms_ovfl_t *ovfl, void **desc) { uint64_t v; size_t k, i; uint32_t num, cpu; pfms_session_t *s; int ret; if (cpu_list == NULL || n == 0 || ctx == NULL || desc == NULL) { dprint("invalid parameters\n"); return -1; } if ((ctx->ctx_flags & PFM_FL_SYSTEM_WIDE) == 0) { dprint("only works for system wide\n"); return -1; } *desc = NULL; /* * XXX: assuming CPU are contiguously indexed */ num = 0; for(k=0, cpu = 0; k < n; k++, cpu+=64) { v = cpu_list[k]; for(i=0; v && i < 63; i++, v>>=1, cpu++) { if (v & 0x1) { if (cpu >= ncpus) { dprint("unavailable CPU%u\n", cpu); return -1; } num++; } } } if (num == 0) return 0; s = calloc(1, sizeof(*s)); if (s == NULL) { dprint("cannot allocate %u contexts\n", num); return -1; } s->ncpus = num; printf("%u-way session\n", num); /* * +1 to account for main thread waiting */ ret = barrier_init(&s->barrier, num + 1); if (ret) { dprint("cannot init barrier\n"); goto error_free; } /* * lock thread descriptor table, no other create_session, close_session * can occur */ pthread_mutex_lock(&tds_lock); if (create_wthreads(cpu_list, n)) goto error_free_unlock; /* * check all needed threads are available */ for(k=0, cpu = 0; k < n; k++, cpu += 64) { v = cpu_list[k]; for(i=0; v && i < 63; i++, v>>=1, cpu++) { if (v & 0x1) { if (tds[cpu].barrier) { dprint("CPU%u already managing a session\n", cpu); goto error_free_unlock; } } } } /* * send create context order */ for(k=0, cpu = 0; k < n; k++, cpu += 64) { v = cpu_list[k]; for(i=0; v && i < 63; i++, v>>=1, cpu++) { if (v & 0x1) { tds[cpu].cmd = CMD_CTX; tds[cpu].data = ctx; tds[cpu].barrier = &s->barrier; sem_post(&tds[cpu].cmd_sem); } } } barrier_wait(&s->barrier); ret = 0; /* * check for errors */ for(k=0; k < ncpus; k++) { if (tds[k].barrier == &s->barrier) { ret = tds[k].ret; if (ret) break; } } /* * undo if error found */ if (k < ncpus) { for(k=0; k < ncpus; k++) { if (tds[k].barrier == &s->barrier) { if (tds[k].ret == 0) { tds[k].cmd = CMD_CLOSE; sem_post(&tds[k].cmd_sem); } /* mark as free */ tds[k].barrier = NULL; } } } pthread_mutex_unlock(&tds_lock); if (ret == 0) *desc = s; return ret ? -1 : 0; error_free_unlock: pthread_mutex_unlock(&tds_lock); error_free: free(s); return -1; } int pfms_load(void *desc) { uint32_t k; pfms_session_t *s; int ret; if (desc == NULL) { dprint("invalid parameters\n"); return -1; } s = (pfms_session_t *)desc; if (s->ncpus == 0) { dprint("invalid session content 0 CPUS\n"); return -1; } /* * send create context order */ for(k=0; k < ncpus; k++) { if (tds[k].barrier == &s->barrier) { tds[k].cmd = CMD_LOAD; sem_post(&tds[k].cmd_sem); } } barrier_wait(&s->barrier); ret = 0; /* * check for errors */ for(k=0; k < ncpus; k++) { if (tds[k].barrier == &s->barrier) { ret = tds[k].ret; if (ret) { dprint("failure on CPU%u\n", k); break; } } } /* * if error, unload all others */ if (k < ncpus) { for(k=0; k < ncpus; k++) { if (tds[k].barrier == &s->barrier) { if (tds[k].ret == 0) { tds[k].cmd = CMD_UNLOAD; sem_post(&tds[k].cmd_sem); } } } } return ret ? -1 : 0; } static int __pfms_do_simple_cmd(pfms_cmd_t cmd, void *desc, void *data, uint32_t n) { size_t k; pfms_session_t *s; int ret; if (desc == NULL) { dprint("invalid parameters\n"); return -1; } s = (pfms_session_t *)desc; if (s->ncpus == 0) { dprint("invalid session content 0 CPUS\n"); return -1; } /* * send create context order */ for(k=0; k < ncpus; k++) { if (tds[k].barrier == &s->barrier) { tds[k].cmd = cmd; tds[k].data = data; tds[k].ndata = n; sem_post(&tds[k].cmd_sem); } } barrier_wait(&s->barrier); ret = 0; /* * check for errors */ for(k=0; k < ncpus; k++) { if (tds[k].barrier == &s->barrier) { ret = tds[k].ret; if (ret) { dprint("failure on CPU%zu\n", k); break; } } } /* * simple commands cannot be undone */ return ret ? -1 : 0; } int pfms_unload(void *desc) { return __pfms_do_simple_cmd(CMD_UNLOAD, desc, NULL, 0); } int pfms_start(void *desc) { return __pfms_do_simple_cmd(CMD_START, desc, NULL, 0); } int pfms_stop(void *desc) { return __pfms_do_simple_cmd(CMD_STOP, desc, NULL, 0); } int pfms_write_pmcs(void *desc, pfarg_pmc_t *pmcs, uint32_t n) { return __pfms_do_simple_cmd(CMD_WPMCS, desc, pmcs, n); } int pfms_write_pmds(void *desc, pfarg_pmd_t *pmds, uint32_t n) { return __pfms_do_simple_cmd(CMD_WPMDS, desc, pmds, n); } int pfms_close(void *desc) { size_t k; pfms_session_t *s; int ret; if (desc == NULL) { dprint("invalid parameters\n"); return -1; } s = (pfms_session_t *)desc; if (s->ncpus == 0) { dprint("invalid session content 0 CPUS\n"); return -1; } for(k=0; k < ncpus; k++) { if (tds[k].barrier == &s->barrier) { tds[k].cmd = CMD_CLOSE; sem_post(&tds[k].cmd_sem); } } barrier_wait(&s->barrier); ret = 0; pthread_mutex_lock(&tds_lock); /* * check for errors */ for(k=0; k < ncpus; k++) { if (tds[k].barrier == &s->barrier) { if (tds[k].ret) { dprint("failure on CPU%zu\n", k); } ret |= tds[k].ret; tds[k].barrier = NULL; } } pthread_mutex_unlock(&tds_lock); free(s); /* * XXX: we cannot undo close */ return ret ? -1 : 0; } int pfms_read_pmds(void *desc, pfarg_pmd_t *pmds, uint32_t n) { pfms_session_t *s; uint32_t k, pmds_per_cpu; int ret; if (desc == NULL) { dprint("invalid parameters\n"); return -1; } s = (pfms_session_t *)desc; if (s->ncpus == 0) { dprint("invalid session content 0 CPUS\n"); return -1; } if (n % s->ncpus) { dprint("invalid number of pfarg_pmd_t provided, must be multiple of %u\n", s->ncpus); return -1; } pmds_per_cpu = n / s->ncpus; dprint("n=%u ncpus=%u per_cpu=%u\n", n, s->ncpus, pmds_per_cpu); for(k=0; k < ncpus; k++) { if (tds[k].barrier == &s->barrier) { tds[k].cmd = CMD_RPMDS; tds[k].data = pmds; tds[k].ndata= pmds_per_cpu; sem_post(&tds[k].cmd_sem); pmds += pmds_per_cpu; } } barrier_wait(&s->barrier); ret = 0; /* * check for errors */ for(k=0; k < ncpus; k++) { if (tds[k].barrier == &s->barrier) { ret = tds[k].ret; if (ret) { dprint("failure on CPU%u\n", k); break; } } } /* * cannot undo pfm_read_pmds */ return ret ? -1 : 0; } #if 0 /* * beginning of test program */ #include #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } static uint32_t popcount(uint64_t c) { uint32_t count = 0; for(; c; c>>=1) { if (c & 0x1) count++; } return count; } int main(int argc, char **argv) { pfarg_ctx_t ctx; pfarg_pmc_t pc[NUM_PMCS]; pfarg_pmd_t *pd; pfmlib_input_param_t inp; pfmlib_output_param_t outp; uint64_t cpu_list; void *desc; unsigned int num_counters; uint32_t i, j, k, l, ncpus, npmds; size_t len; int ret; char *name; if (pfm_initialize() != PFMLIB_SUCCESS) fatal_error("cannot initialize libpfm\n"); if (pfms_initialize()) fatal_error("cannot initialize libpfms\n"); pfm_get_num_counters(&num_counters); pfm_get_max_event_name_len(&len); name = malloc(len+1); if (name == NULL) fatal_error("cannot allocate memory for event name\n"); memset(&ctx, 0, sizeof(ctx)); memset(pc, 0, sizeof(pc)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); cpu_list = argc > 1 ? strtoul(argv[1], NULL, 0) : 0x3; ncpus = popcount(cpu_list); if (pfm_get_cycle_event(&inp.pfp_events[0].event) != PFMLIB_SUCCESS) fatal_error("cannot find cycle event\n"); if (pfm_get_inst_retired_event(&inp.pfp_events[1].event) != PFMLIB_SUCCESS) fatal_error("cannot find inst retired event\n"); i = 2; inp.pfp_dfl_plm = PFM_PLM3|PFM_PLM0; if (i > num_counters) { i = num_counters; printf("too many events provided (max=%d events), using first %d event(s)\n", num_counters, i); } /* * how many counters we use */ inp.pfp_event_count = i; /* * indicate we are using the monitors for a system-wide session. * This may impact the way the library sets up the PMC values. */ inp.pfp_flags = PFMLIB_PFP_SYSTEMWIDE; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); npmds = ncpus * inp.pfp_event_count; dprint("ncpus=%u npmds=%u\n", ncpus, npmds); pd = calloc(npmds, sizeof(pfarg_pmd_t)); if (pd == NULL) fatal_error("cannot allocate pd array\n"); for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } for(l=0, k = 0; l < ncpus; l++) { for (i=0, j=0; i < inp.pfp_event_count; i++, k++) { pd[k].reg_num = outp.pfp_pmcs[j].reg_pmd_num; for(; j < outp.pfp_pmc_count; j++) if (outp.pfp_pmcs[j].reg_evt_idx != i) break; } } /* * create a context on all CPUs we asked for * * libpfms only works for system-wide, so we set the flag in * the master context. the context argument is not modified by * call. * * desc is an opaque descriptor used to identify session. */ ctx.ctx_flags = PFM_FL_SYSTEM_WIDE; ret = pfms_create(&cpu_list, 1, &ctx, NULL, &desc); if (ret == -1) fatal_error("create error %d\n", ret); /* * program the PMC registers on all CPUs of interest */ ret = pfms_write_pmcs(desc, pc, outp.pfp_pmc_count); if (ret == -1) fatal_error("write_pmcs error %d\n", ret); /* * program the PMD registers on all CPUs of interest */ ret = pfms_write_pmds(desc, pd, inp.pfp_event_count); if (ret == -1) fatal_error("write_pmds error %d\n", ret); /* * load context on all CPUs of interest */ ret = pfms_load(desc); if (ret == -1) fatal_error("load error %d\n", ret); /* * start monitoring on all CPUs of interest */ ret = pfms_start(desc); if (ret == -1) fatal_error("start error %d\n", ret); /* * simulate some work */ sleep(10); /* * stop monitoring on all CPUs of interest */ ret = pfms_stop(desc); if (ret == -1) fatal_error("stop error %d\n", ret); /* * read the PMD registers on all CPUs of interest. * The pd[] array must be organized such that to * read 2 PMDs on each CPU you need: * - 2 * number of CPUs of interest * - the first 2 elements of pd[] read on 1st CPU * - the next 2 elements of pd[] read on the 2nd CPU * - and so on */ ret = pfms_read_pmds(desc, pd, npmds); if (ret == -1) fatal_error("read_pmds error %d\n", ret); /* * pre per-CPU results */ for(j=0, k= 0; j < ncpus; j++) { for (i=0; i < inp.pfp_event_count; i++, k++) { pfm_get_full_event_name(&inp.pfp_events[i], name, len); printf("CPU%-3d PMD%u %20"PRIu64" %s\n", j, pd[k].reg_num, pd[k].reg_value, name); } } /* * destroy context on all CPUs of interest. * After this call desc is invalid */ ret = pfms_close(desc); if (ret == -1) fatal_error("close error %d\n", ret); free(name); return 0; } #endif papi-5.5.1/src/libpfm-3.y/libpfms/Makefile0000644000307100002310000000355113013651450020222 0ustar yarkhangraduate# # Copyright (c) 2006 Hewlett-Packard Development Company, L.P. # Contributed by Stephane Eranian # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies # of the Software, and to permit persons to whom the Software is furnished to do so, # subject to the following conditions: # # The above copyright notice and this permission notice shall be included in all # copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, # INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A # PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT # HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE # OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # TOPDIR := $(shell if [ "$$PWD" != "" ]; then echo $$PWD; else pwd; fi)/.. include $(TOPDIR)/config.mk include $(TOPDIR)/rules.mk DIRS=lib CFLAGS+= -pthread -D_GNU_SOURCE -I./include LIBS += -L$(TOPDIR)/libpfms/lib -lpfms $(PFMLIB) -lm TARGETS=syst_smp all: $(TARGETS) syst_smp: ./lib/libpfms.a syst_smp.o $(CC) $(CFLAGS) $(LDFLAGS) -o $@ syst_smp.o $(LIBS) -lpthread clean: @set -e ; for d in $(DIRS) ; do $(MAKE) -C $$d $@ ; done $(RM) -f *.o $(TARGETS) *~ distclean: clean .FORCE: lib/libpfms.a lib/libpfms.a: @set -e ; $(MAKE) -C lib all install depend: $(TARGETS) install depend: ifeq ($(CONFIG_PFMLIB_ARCH_SICORTEX),y) @set -e ; for d in $(DIRS) ; do $(MAKE) -C $$d $@ ; done endif papi-5.5.1/src/libpfm-3.y/libpfms/syst_smp.c0000644000307100002310000001575613013651451020622 0ustar yarkhangraduate/* * syst_smp.c - system-wide monitoring for SMP machine using libpfms helper * library * * Copyright (c) 2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } static uint32_t popcount(uint64_t c) { uint32_t count = 0; for(; c; c>>=1) { if (c & 0x1) count++; } return count; } int main(int argc, char **argv) { pfarg_ctx_t ctx; pfarg_pmc_t pc[NUM_PMCS]; pfarg_pmd_t *pd; pfmlib_input_param_t inp; pfmlib_output_param_t outp; uint64_t cpu_list; void *desc; unsigned int num_counters; uint32_t i, j, l, k, ncpus, npmds; size_t len; int ret; char *name; if (pfm_initialize() != PFMLIB_SUCCESS) fatal_error("cannot initialize libpfm\n"); if (pfms_initialize()) fatal_error("cannot initialize libpfms\n"); memset(&ctx, 0, sizeof(ctx)); memset(pc, 0, sizeof(pc)); ncpus = (uint32_t)sysconf(_SC_NPROCESSORS_ONLN); if (ncpus == -1) fatal_error("cannot retrieve number of online processors\n"); if (argc > 1) { cpu_list = strtoul(argv[1],NULL,0); if (popcount(cpu_list) > ncpus) fatal_error("too many processors specified\n"); } else { cpu_list = ((1< num_counters) { i = num_counters; printf("too many events provided (max=%d events), using first %d event(s)\n", num_counters, i); } /* * how many counters we use */ inp.pfp_event_count = i; /* * indicate we are using the monitors for a system-wide session. * This may impact the way the library sets up the PMC values. */ inp.pfp_flags = PFMLIB_PFP_SYSTEMWIDE; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); npmds = ncpus * inp.pfp_event_count; printf("ncpus=%u npmds=%u\n", ncpus, npmds); pd = calloc(npmds, sizeof(pfarg_pmd_t)); if (pd == NULL) fatal_error("cannot allocate pd array\n"); for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * We use inp.pfp_event_count PMD registers for our events per-CPU. * We need to setup the PMDs we use. They are determined based on the * PMC registers used. The following loop prepares the pd[] array * for pfm_write_pmds(). With libpfms, on PMD write we need to pass * only pfp_event_count PMD registers. But on PMD read, we need * to pass pfp_event_count PMD registers per-CPU because libpfms * does not aggregate counts. To prepapre for PMD read, we therefore * propagate the PMD setup beyond just the first pfp_event_count * elements of pd[]. */ for(l=0, k= 0; l < ncpus; l++) { for (i=0; i < outp.pfp_pmd_count; i++, k++) pd[k].reg_num = outp.pfp_pmds[i].reg_num; } /* * create a context on all CPUs we asked for * * libpfms only works for system-wide, so we set the flag in * the master context. the context argument is not modified by * call. * * desc is an opaque descriptor used to identify session. */ ctx.ctx_flags = PFM_FL_SYSTEM_WIDE; ret = pfms_create(&cpu_list, 1, &ctx, NULL, &desc); if (ret == -1) fatal_error("create error %d\n", ret); /* * program the PMC registers on all CPUs of interest */ ret = pfms_write_pmcs(desc, pc, outp.pfp_pmc_count); if (ret == -1) fatal_error("write_pmcs error %d\n", ret); /* * program the PMD registers on all CPUs of interest */ ret = pfms_write_pmds(desc, pd, outp.pfp_pmd_count); if (ret == -1) fatal_error("write_pmds error %d\n", ret); /* * load context on all CPUs of interest */ ret = pfms_load(desc); if (ret == -1) fatal_error("load error %d\n", ret); printf("monitoring for 10s on all CPUs\n"); /* * start monitoring on all CPUs of interest */ ret = pfms_start(desc); if (ret == -1) fatal_error("start error %d\n", ret); /* * stop and listen to activity for 10s */ sleep(10); /* * stop monitoring on all CPUs of interest */ ret = pfms_stop(desc); if (ret == -1) fatal_error("stop error %d\n", ret); /* * read the PMD registers on all CPUs of interest. * The pd[] array must be organized such that to * read 2 PMDs on each CPU you need: * - 2 * number of CPUs of interest * - the first 2 elements of pd[] read on CPU0 * - the next 2 elements of pd[] read on CPU1 * - and so on */ ret = pfms_read_pmds(desc, pd, npmds); if (ret == -1) fatal_error("read_pmds error %d\n", ret); /* * print per-CPU results */ for(j=0, k= 0; j < ncpus; j++) { for (i=0; i < inp.pfp_event_count; i++, k++) { pfm_get_full_event_name(&inp.pfp_events[i], name, len); printf("CPU%-3d PMD%u %20"PRIu64" %s\n", j, pd[k].reg_num, pd[k].reg_value, name); } } /* * destroy context on all CPUs of interest. * After this call desc is invalid */ ret = pfms_close(desc); if (ret == -1) fatal_error("close error %d\n", ret); free(name); return 0; } papi-5.5.1/src/libpfm-3.y/libpfms/include/0000755000307100002310000000000013013651450020201 5ustar yarkhangraduatepapi-5.5.1/src/libpfm-3.y/libpfms/include/libpfms.h0000644000307100002310000000363013013651450022010 0ustar yarkhangraduate/* * libpfms.h - header file for libpfms - a helper library for perfmon SMP monitoring * * Copyright (c) 2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef __LIBPFMS_H__ #define __LIBPFMS_H__ #ifdef __cplusplus extern "C" { #endif typedef int (*pfms_ovfl_t)(pfarg_msg_t *msg); int pfms_initialize(void); int pfms_create(uint64_t *cpu_list, size_t n, pfarg_ctx_t *ctx, pfms_ovfl_t *ovfl, void **desc); int pfms_write_pmcs(void *desc, pfarg_pmc_t *pmcs, uint32_t n); int pfms_write_pmds(void *desc, pfarg_pmd_t *pmds, uint32_t n); int pfms_read_pmds(void *desc, pfarg_pmd_t *pmds, uint32_t n); int pfms_start(void *desc); int pfms_stop(void *desc); int pfms_close(void *desc); int pfms_unload(void *desc); int pfms_load(void *desc); #ifdef __cplusplus /* extern C */ } #endif #endif /* __LIBPFMS_H__ */ papi-5.5.1/src/libpfm-3.y/TODO0000644000307100002310000000043313013651447015620 0ustar yarkhangraduateTODO list: ---------- - add Linux/ia64 perfmon support to GNU libc, this would avoid having the perfmon.h perfmon_default_smpl.h headers here. - add library interface to help setup system-wide mode SMP on Linux/ia64 - add support for cumulative calls to pfm_dispatch_events() papi-5.5.1/src/libpfm-3.y/README0000644000307100002310000000670113013651447016014 0ustar yarkhangraduate ------------------------------------------------------ libpfm-3.10: a helper library to program the Performance Monitoring Unit (PMU) ------------------------------------------------------ Copyright (c) 2001-2007 Hewlett-Packard Development Company, L.P. Contributed by Stephane Eranian This package provides a library, called libpfm, which can be used to develop monitoring tools which use the Performance Monitoring Unit (PMU) of several modern processors. This version of libpfm supports: - For Intel IA-64: Itanium (Merced), Itanium 2 (McKinley, Madison, Deerfield), Itanium 2 9000/9100 (Montecito, Montvale) and Generic - For AMD X86: AMD64 (K8, family 10h) - For Intel X86: Intel P6 (Pentium II, Pentium Pro, Pentium III, Pentium M) Intel Yonah (Core Duo/Core Solo), Intel Netburst (Pentium 4, Xeon) Intel Core (Merom, Penryn, Dunnington) Core 2 and Quad Intel Atom Intel Nehalem (Nehalem, Westmere) Intel architectural perfmon v1, v2, v3 - For MIPS: 5K, 20K, 25KF, 34K, 5KC, 74K, R10000, R12000, RM7000, RM9000, SB1, VR5432, VR5500, SiCortex ICA9A/ICE9B - For Cray: XT3, XT4, XT5, XT5h, X2 - For IBM: IBM Cell processor POWER: PPC970, PPC970MP, POWER4+, POWER5, POWER5+, POWER6, POWER7 - For Sun: Sparc: Ultra12, Ultra3, Ultra3i, Ultra3Plus, Ultra4Plus, Sparc: Niagara1, Niagara2 The core library is generic and does not depend on the perfmon interface. It is possible to use it on other operating systems. WHAT'S THERE ------------- - the library source code including support for all processors listed above - a set of examples showing how the library can be used with the perfmon2 and perfmon3 kernel interface. - a set of older examples for IA-64 only using the legacy perfmon2 interface (v2.0). - a set of library header files and the perfmon2 and perfmon3 kernel interface headers - libpfms: a simple library to help setup SMP system-wide monitoring sessions. It comes with a simple example. This library is not part of libpfm. - man pages for all the library entry points - Python bindings for libpfm and the perfmon interface (experimental). INSTALLATION ------------ - edit config.mk to : - update some of the configuration variables - make your compiler options - type make - type make install - To compile and install the Python bindings, you need to go to the python sub-directory and type make. Python is not systematically built - to compile the library for another ABI (e.g. 32-bit x86 on a 64-bit x86) system, you can pass the ABI flag to the compiler as follows (assuming you have the multilib version of gcc): $ make OPTION="-m32 -O2" REQUIREMENTS: ------------- - to run the programs in the examples subdir, you MUST be using a linux kernel with perfmon3. Perfmon3 is available as a branch of the perfmon kernel GIT tree on kernel.org. - to run the programs in the examples_v2x subdir, you MUST be using a linux kernel with perfmon2. Perfmon2 is available as the main branch of the perfmon kernel GIT tree on kernel.org. - On IA-64, the examples in old_interface_ia64_examples work with any 2.6.x kernels. - to compile the Python bindings, you need to have SWIG and the python development packages installed DOCUMENTATION ------------- - man pages for all entry points - More information can be found on library web site: http://perfmon2.sf.net papi-5.5.1/src/libpfm-3.y/examples_v2.x/0000755000307100002310000000000013013651447017623 5ustar yarkhangraduatepapi-5.5.1/src/libpfm-3.y/examples_v2.x/task_attach.c0000644000307100002310000002070613013651447022262 0ustar yarkhangraduate/* * task_attach.c - example of how to attach to another task for monitoring * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include "detect_pmcs.h" #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } int parent(pid_t pid) { pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfarg_ctx_t ctx[1]; pfarg_pmc_t pc[NUM_PMCS]; pfarg_pmd_t pd[NUM_PMDS]; pfarg_load_t load_args; pfarg_msg_t msg; unsigned int i, num_counters; int status, ret; int ctx_fd; char name[MAX_EVT_NAME_LEN]; memset(pc, 0, sizeof(pc)); memset(pd, 0, sizeof(pd)); memset(ctx, 0, sizeof(ctx)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&load_args,0, sizeof(load_args)); pfm_get_num_counters(&num_counters); if (pfm_get_cycle_event(&inp.pfp_events[0]) != PFMLIB_SUCCESS) { fatal_error("cannot find cycle event\n"); } if (pfm_get_inst_retired_event(&inp.pfp_events[1]) != PFMLIB_SUCCESS) { fatal_error("cannot find inst retired event\n"); } i = 2; /* * set the privilege mode: * PFM_PLM3 : user level * PFM_PLM0 : kernel level */ inp.pfp_dfl_plm = PFM_PLM3; if (i > num_counters) { i = num_counters; printf("too many events provided (max=%d events), using first %d event(s)\n", num_counters, i); } /* * how many counters we use */ inp.pfp_event_count = i; /* * now create a context. we will later attach it to the task we are creating. */ ctx_fd = pfm_create_context(ctx, NULL, NULL, 0); if (ctx_fd == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * build the pfp_unavail_pmcs bitmask by looking * at what perfmon has available. It is not always * the case that all PMU registers are actually available * to applications. For instance, on IA-32 platforms, some * registers may be reserved for the NMI watchdog timer. * * With this bitmap, the library knows which registers NOT to * use. Of source, it is possible that no valid assignement may * be possible if certina PMU registers are not available. */ detect_unavail_pmcs(ctx_fd, &inp.pfp_unavail_pmcs); /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); } /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events causes extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } for(i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more thann counting monitors. */ if (pfm_write_pmcs(ctx_fd, pc, outp.pfp_pmc_count) == -1) fatal_error("pfm_write_pmcs error errno %d\n",errno); /* * To be read, each PMD must be either written or declared * as being part of a sample (reg_smpl_pmds) */ if (pfm_write_pmds(ctx_fd, pd, outp.pfp_pmd_count) == -1) fatal_error("pfm_write_pmds error errno %d\n",errno); ret = ptrace(PTRACE_ATTACH, pid, NULL, 0); if (ret == -1) { fatal_error("cannot attach to %d: %s\n", pid, strerror(errno)); } /* * wait for the child to be actually stopped */ waitpid(pid, &status, WUNTRACED); /* * check if process exited early */ if (WIFEXITED(status)) { fatal_error("command process %d exited too early with status %d\n", pid, WEXITSTATUS(status)); } /* * the task is stopped at this point */ /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = pid; if (pfm_load_context(ctx_fd, &load_args) == -1) { fatal_error("pfm_load_context error errno %d\n",errno); } /* * activate monitoring. The task is still STOPPED at this point. Monitoring * will not take effect until the execution of the task is resumed. */ if (pfm_start(ctx_fd, NULL) == -1) { fatal_error("pfm_start error errno %d\n",errno); } /* * now resume execution of the task, effectively activating * monitoring. */ ptrace(PTRACE_DETACH, pid, NULL, 0); /* * now the task is running */ /* * We cannot simply do a waitpid() because we may be attaching to a process * totally unrelated to our program. Instead we use a perfmon facility that * notifies us when the monitoring task is exiting. * * When a task with a monitoring context attached to it exits, a PFM_MSG_END * is generated. It can be retrieve with a simple read() on the context's descriptor. * * Another reason why you might return from the read is if there was a counter * overflow, unlikely in this example. * * To measure only for short period of time, use select or poll with a timeout, * see task_attach_timeout.c * */ ret = read(ctx_fd, &msg, sizeof(msg)); if (ret == -1) { fatal_error("cannot read from descriptor: %s\n", strerror(errno)); } if (msg.type != PFM_MSG_END) { fatal_error("unexpected msg type : %d\n", msg.type); } /* * the task has exited, we can simply read the results */ /* * now simply read the results. */ if (pfm_read_pmds(ctx_fd, pd, inp.pfp_event_count) == -1) { fatal_error("pfm_read_pmds error errno %d\n",errno); return -1; } /* * print the results * * It is important to realize, that the first event we specified may not * be in PMD4. Not all events can be measured by any monitor. That's why * we need to use the pc[] array to figure out where event i was allocated. * */ for (i=0; i < inp.pfp_event_count; i++) { pfm_get_full_event_name(&inp.pfp_events[i], name, MAX_EVT_NAME_LEN); printf("PMD%-3u %20"PRIu64" %s\n", pd[i].reg_num, pd[i].reg_value, name); } /* * free the context */ close(ctx_fd); return 0; } int main(int argc, char **argv) { pfmlib_options_t pfmlib_options; pid_t pid; int ret; if (argc < 2) { fatal_error("usage: %s pid\n", argv[0]); } pid = atoi(argv[1]); /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) fatal_error("Cannot initialize library: %s\n", pfm_strerror(ret)); return parent(pid); } papi-5.5.1/src/libpfm-3.y/examples_v2.x/syst.c0000644000307100002310000001777713013651447021014 0ustar yarkhangraduate/* * syst.c - example of a simple system wide monitoring program * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include "detect_pmcs.h" #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } #define MAX_CPUS 2048 int pin_cpu(pid_t pid, unsigned int cpu) { cpu_set_t my_set; CPU_ZERO(&my_set); if (cpu >= MAX_CPUS) fatal_error("this program supports only up to %d CPUs\n", MAX_CPUS); CPU_SET(cpu, &my_set); return sched_setaffinity(pid, sizeof(cpu_set_t), &my_set); } int main(int argc, char **argv) { char **p; pfarg_pmc_t pc[NUM_PMCS]; pfarg_pmd_t pd[NUM_PMDS]; uint64_t pdo[NUM_PMDS]; pfarg_ctx_t ctx[1]; pfarg_load_t load_args; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_options_t pfmlib_options; unsigned int which_cpu; int ret, ctx_fd; unsigned int i, l; unsigned int num_counters; char name[MAX_EVT_NAME_LEN]; /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) fatal_error("Cannot initialize library: %s\n", pfm_strerror(ret)); pfm_get_num_counters(&num_counters); memset(pc, 0, sizeof(pc)); memset(pd, 0, sizeof(pd)); memset(pdo, 0, sizeof(pdo)); memset(ctx, 0, sizeof(ctx)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&load_args,0, sizeof(load_args)); /* * be nice to user! */ if (argc > 1) { p = argv+1; for (i=0; *p ; i++, p++) { if (pfm_find_full_event(*p, &inp.pfp_events[i]) != PFMLIB_SUCCESS) { fatal_error("Cannot find %s event\n", *p); } } } else { if (pfm_get_cycle_event(&inp.pfp_events[0]) != PFMLIB_SUCCESS) { fatal_error("cannot find cycle event\n"); } if (pfm_get_inst_retired_event(&inp.pfp_events[1]) != PFMLIB_SUCCESS) { fatal_error("cannot find inst retired event\n"); } i = 2; } /* * set the privilege mode: * PFM_PLM3 : user level * PFM_PLM0 : kernel level */ inp.pfp_dfl_plm = PFM_PLM3|PFM_PLM0; if (i > num_counters) { i = num_counters; printf("too many events provided (max=%d events), using first %d event(s)\n", num_counters, i); } /* * how many counters we use */ inp.pfp_event_count = i; /* * indicate we are using the monitors for a system-wide session. * This may impact the way the library sets up the PMC values. */ inp.pfp_flags = PFMLIB_PFP_SYSTEMWIDE; /* * In system wide mode, the perfmon context cannot be inherited. * Also in this mode, we cannot use the blocking form of user level notification. */ ctx[0].ctx_flags = PFM_FL_SYSTEM_WIDE; /* * pick a random CPU. Assumes CPU are numbered with no holes */ srandom(getpid()); which_cpu = random() % sysconf(_SC_NPROCESSORS_ONLN); /* * The monitored CPU is determined by the processor core * executing the PFM_LOAD_CONTEXT command. To ensure, we * measure the right core, we pin the thread before making * the call. */ ret = pin_cpu(getpid(), which_cpu); if (ret == -1) fatal_error("cannot set affinity to CPU%d: %s\n", which_cpu, strerror(errno)); /* * after the call the task is pinned to which_cpu */ /* * now create the context for self monitoring/per-task */ ctx_fd = pfm_create_context(ctx, NULL, NULL, 0); if (ctx_fd == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * build the pfp_unavail_pmcs bitmask by looking * at what perfmon has available. It is not always * the case that all PMU registers are actually available * to applications. For instance, on IA-32 platforms, some * registers may be reserved for the NMI watchdog timer. * * With this bitmap, the library knows which registers NOT to * use. Of source, it is possible that no valid assignement may * be possible if certina PMU registers are not available. */ detect_unavail_pmcs(ctx_fd, &inp.pfp_unavail_pmcs); /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); /* * Now prepare the argument to initialize the PMDs and PMCS. * We use pfp_pmc_count to determine the number of PMC to intialize. * We use pfp_pmd_count to determine the number of PMD to initialize. * Some events/features may cause extra PMCs to be used, leading to: * - pfp_pmc_count may be >= pfp_event_count * - pfp_pmd_count may be >= pfp_event_count */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * Now program the registers */ if (pfm_write_pmcs(ctx_fd, pc, outp.pfp_pmc_count) == -1) fatal_error("pfm_write_pmcs error errno %d\n",errno); if (pfm_write_pmds(ctx_fd, pd, outp.pfp_pmd_count) == -1) fatal_error("pfm_write_pmds error errno %d\n",errno); /* * in system-wide mode, this field must provide the CPU the caller wants * to monitor. The kernel checks and if calling from the wrong CPU, the * call fails. The affinity is not affected. */ load_args.load_pid = which_cpu; if (pfm_load_context(ctx_fd, &load_args) == -1) fatal_error("pfm_load_context error errno %d\n",errno); printf("\n", which_cpu); for(l=0; l < 10; l++) { /* * start monitoring */ if (pfm_start(ctx_fd, NULL) == -1) fatal_error("pfm_start error errno %d\n",errno); sleep(2); /* * stop monitoring. * changed at the user level. */ if (pfm_stop(ctx_fd) == -1) fatal_error("pfm_stop error errno %d\n",errno); /* * read the results */ if (pfm_read_pmds(ctx_fd, pd, inp.pfp_event_count) == -1) fatal_error( "pfm_read_pmds error errno %d\n",errno); /* * print the results */ puts("------------------------"); for (i=0; i < inp.pfp_event_count; i++) { pfm_get_full_event_name(&inp.pfp_events[i], name, MAX_EVT_NAME_LEN); printf("CPU%-2d PMD%-3u raw=%-20"PRIu64" delta=%-20"PRIu64" %s\n", which_cpu, pd[i].reg_num, pd[i].reg_value, pd[i].reg_value - pdo[i], name); pdo[i] = pd[i].reg_value; } } /* * destroy everything */ close(ctx_fd); return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/syst_multi_np.c0000644000307100002310000001531413013651447022704 0ustar yarkhangraduate/* * syst_multi_np.c - simple system-wide counting no thread * * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Based on: * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include "detect_pmcs.h" #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 int main(int argc, char **argv) { char **p; pfarg_pmc_t pc[NUM_PMCS]; pfarg_pmd_t pd[NUM_PMDS]; pfarg_ctx_t ctx[1]; pfarg_load_t load_args; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_options_t pfmlib_options; uint64_t *pdo; int *fds; int ret, i; unsigned int l; long n, ncpus; unsigned int num_counters; char name[MAX_EVT_NAME_LEN]; /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) errx(1, "Cannot initialize library: %s", pfm_strerror(ret)); pfm_get_num_counters(&num_counters); memset(pc, 0, sizeof(pc)); memset(pd, 0, sizeof(pd)); memset(ctx, 0, sizeof(ctx)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&load_args,0, sizeof(load_args)); /* * be nice to user! */ if (argc > 1) { p = argv+1; for (i=0; *p ; i++, p++) { if (pfm_find_full_event(*p, &inp.pfp_events[i]) != PFMLIB_SUCCESS) errx(1, "cannot find %s event", *p); } } else { if (pfm_get_cycle_event(&inp.pfp_events[0]) != PFMLIB_SUCCESS) errx(1, "cannot find cycle event"); if (pfm_get_inst_retired_event(&inp.pfp_events[1]) != PFMLIB_SUCCESS) errx(1, "cannot find inst retired event"); i = 2; } /* * set the privilege mode: * PFM_PLM3 : user level * PFM_PLM0 : kernel level */ inp.pfp_dfl_plm = PFM_PLM3|PFM_PLM0; if (i > num_counters) { i = num_counters; warnx("too many events provided (max=%d events), using first %d event(s)", num_counters, i); } /* * how many counters we use */ inp.pfp_event_count = i; /* * indicate we are using the monitors for a system-wide session. * This may impact the way the library sets up the PMC values. */ inp.pfp_flags = PFMLIB_PFP_SYSTEMWIDE; /* * In system wide mode, the perfmon context cannot be inherited. * Also in this mode, we cannot use the blocking form of user level notification. */ ctx[0].ctx_flags = PFM_FL_SYSTEM_WIDE; /* * build the pfp_unavail_pmcs bitmask by looking * at what perfmon has available. It is not always * the case that all PMU registers are actually available * to applications. For instance, on IA-32 platforms, some * registers may be reserved for the NMI watchdog timer. * * With this bitmap, the library knows which registers NOT to * use. Of source, it is possible that no valid assignement may * be possible if certina PMU registers are not available. */ detect_unavail_pmcs(-1, &inp.pfp_unavail_pmcs); /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) errx(1, "cannot configure events: %s", pfm_strerror(ret)); /* * Now prepare the argument to initialize the PMDs and PMCS. * We use pfp_pmc_count to determine the number of PMC to intialize. * We use pfp_pmd_count to determine the number of PMD to initialize. * Some events/features may cause extra PMCs to be used, leading to: * - pfp_pmc_count may be >= pfp_event_count * - pfp_pmd_count may be >= pfp_event_count */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; ncpus = sysconf(_SC_NPROCESSORS_ONLN); if (ncpus < 1) ncpus = 1; fds = malloc(ncpus * sizeof(int)); if (!fds) err(1, "cannot allocate fds"); pdo = calloc(ncpus * outp.pfp_pmd_count, sizeof(uint64_t)); if (!pdo) err(1, "cannot allocate pdo"); printf("ncpus=%ld pmd=%d\n", ncpus, outp.pfp_pmd_count); /* * create and load contexts */ for(n=0; n < ncpus; n++) { fds[n] = pfm_create_context(ctx, NULL, NULL, 0); if (fds[n] == -1) { if (errno == ENOSYS) { errx(1, "your kernel does not have performance monitoring support!\n"); } err(1, "cannot create context"); } if (pfm_write_pmcs(fds[n], pc, outp.pfp_pmc_count)) err(1, "pfm_write_pmcs error"); if (pfm_write_pmds(fds[n], pd, outp.pfp_pmd_count)) err(1, "pfm_write_pmds error"); load_args.load_pid = n; if (pfm_load_context(fds[n], &load_args)) err(1, "pfm_load_context error"); } /* * start all */ for(n=0; n < ncpus; n++) { if (pfm_start(fds[n], NULL) == -1) err(1, "pfm_start error"); } for(l=0; l < 20; l++) { sleep(1); /* * read the results */ puts("------------------------"); for(n=0; n < ncpus; n++) { if (pfm_read_pmds(fds[n], pd, outp.pfp_pmd_count)) err(1, "pfm_read_pmds error"); for (i=0; i < outp.pfp_pmd_count; i++) { pfm_get_full_event_name(&inp.pfp_events[i], name, MAX_EVT_NAME_LEN); printf("CPU%-2ld PMD%-3u %-20"PRIu64" %s\n", n, pd[i].reg_num, pd[i].reg_value - pdo[n*outp.pfp_pmd_count+i], name); pdo[n*outp.pfp_pmd_count+i] = pd[i].reg_value; } } } for(n=0; n < ncpus; n++) close(fds[n]); free(fds); free(pdo); return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/showreginfo.c0000644000307100002310000001413613013651447022326 0ustar yarkhangraduate/* * showreginfo.c - show PMU register information * * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #include #include #include #include #include #include #include #include #include #include #include static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } static int get_value(char *fn, char *buffer, size_t maxlen) { int fd; ssize_t ret; fd = open(fn, O_RDONLY); if (fd == -1) return -1; ret = read(fd, buffer, maxlen-1); if (ret == -1) fatal_error("cannot read from %s\n", fn); buffer[ret-1] = '\0'; close(fd); return 0; } /* * This example shows how to retrieve the PMU register mapping information. * It does not use the libpfm library. * The mapping gives the translation between the logical register names, * as exposed by the perfmon interface, and the actual hardware registers. * Depending on the PMU and perfmon implementation, not all registers are * necessarily PMU registers, some may correspond to software resources. */ int main(int argc, char **argv) { unsigned long long dfl, rsvd; unsigned long hw_addr; pfarg_ctx_t ctx; char pname[64]; char name[64], buffer[32]; unsigned int i, num_pmcs = 0, num_pmds = 0; int c, ret, ret2 = 0; int use_html = 0; while((c=getopt(argc, argv, "hH")) != -1) { switch(c) { case 'h': printf("usage: showreginfo [-h] [-H]\n"); return 0; case 'H': use_html = 1; break; default: return -1; } } try_again: ret = get_value("/sys/kernel/perfmon/pmu_desc/model", buffer, sizeof(buffer)); if (ret == -1) { /* * try to trigger automatic PMU description loading */ if (ret2 == 0) { memset(&ctx, 0, sizeof(ctx)); ret2 = pfm_create_context(&ctx, NULL, NULL, 0); if (ret2 > 0) { close(ret2); goto try_again; } fatal_error("invalid or missing perfmon support for your CPU (need at least v2.3)\n"); } } if (use_html) { puts(""); puts(""); puts(""); puts(""); puts(""); printf("\n", buffer); puts(""); puts(""); puts(""); } else { printf("model : %s\n", buffer); puts( "----------------------------------------------------------------------------\n" "name | default value | reserved mask | hw address | description\n" "-------+--------------------+--------------------+------------+-------------"); } for(i=0; i < PFM_MAX_PMCS; i++) { sprintf(pname, "/sys/kernel/perfmon/pmu_desc/pmc%d/name", i); ret = get_value(pname, name, sizeof(name)); if (ret) continue; num_pmcs++; sprintf(pname, "/sys/kernel/perfmon/pmu_desc/pmc%d/dfl_val", i); get_value(pname, buffer, sizeof(buffer)); dfl = strtoull(buffer, NULL, 16); sprintf(pname, "/sys/kernel/perfmon/pmu_desc/pmc%d/rsvd_msk", i); get_value(pname, buffer, sizeof(buffer)); rsvd = strtoull(buffer, NULL, 16); sprintf(pname, "/sys/kernel/perfmon/pmu_desc/pmc%d/addr", i); get_value(pname, buffer, sizeof(buffer)); hw_addr = strtoul(buffer, NULL, 0); if (use_html) { printf("\n", i, hw_addr, name); } else { printf("pmc%-3d | 0x%016llx | 0x%016llx | 0x%-8lx | %s\n", i, dfl, rsvd, hw_addr, name); } } if (use_html) puts(""); else puts("-------+--------------------+--------------------+------------+-------------"); for(i=0; i < PFM_MAX_PMDS; i++) { sprintf(pname, "/sys/kernel/perfmon/pmu_desc/pmd%d/name", i); ret = get_value(pname, name, sizeof(name)); if (ret) continue; num_pmds++; sprintf(pname, "/sys/kernel/perfmon/pmu_desc/pmd%d/dfl_val", i); get_value(pname, buffer, sizeof(buffer)); dfl = strtoull(buffer, NULL, 16); sprintf(pname, "/sys/kernel/perfmon/pmu_desc/pmd%d/rsvd_msk", i); get_value(pname, buffer, sizeof(buffer)); rsvd = strtoull(buffer, NULL, 16); sprintf(pname, "/sys/kernel/perfmon/pmu_desc/pmd%d/addr", i); get_value(pname, buffer, sizeof(buffer)); hw_addr = strtoul(buffer, NULL, 0); if (use_html) { printf("\n", i, hw_addr, name); } else { printf("pmd%-3d | 0x%016llx | 0x%016llx | 0x%-8lx | %s\n", i, dfl, rsvd, hw_addr, name); } } if (use_html) { puts("
%s
NameHW ADDRDescription
PMC%d0x%lx%s
PMC%d0x%lx%s
"); puts(""); puts(""); } else { puts("----------------------------------------------------------------------------"); printf("%u PMC registers, %u PMD registers\n", num_pmcs, num_pmds); } return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/syst_np.c0000644000307100002310000001744413013651447021500 0ustar yarkhangraduate/* * syst_np.c - simple cpu-wide counting but forced on a remote CPU * * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Based on: * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include "detect_pmcs.h" #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 #define MAX_CPUS 2048 int pin_cpu(pid_t pid, unsigned int cpu) { cpu_set_t my_set; CPU_ZERO(&my_set); if (cpu >= MAX_CPUS) errx(1, "this program supports only up to %d CPUs", MAX_CPUS); CPU_SET(cpu, &my_set); return sched_setaffinity(pid, sizeof(cpu_set_t), &my_set); } int main(int argc, char **argv) { char **p; pfarg_pmc_t pc[NUM_PMCS]; pfarg_pmd_t pd[NUM_PMDS]; uint64_t pdo[NUM_PMDS]; pfarg_ctx_t ctx[1]; pfarg_load_t load_args; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_options_t pfmlib_options; int user_cpu, kern_cpu; int ret, ctx_fd; unsigned int i, l; unsigned int num_counters; char name[MAX_EVT_NAME_LEN]; /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) errx(1, "Cannot initialize library: %s", pfm_strerror(ret)); pfm_get_num_counters(&num_counters); memset(pc, 0, sizeof(pc)); memset(pd, 0, sizeof(pd)); memset(pdo, 0, sizeof(pdo)); memset(ctx, 0, sizeof(ctx)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&load_args,0, sizeof(load_args)); /* * be nice to user! */ if (argc > 1) { p = argv+1; for (i=0; *p ; i++, p++) { if (pfm_find_full_event(*p, &inp.pfp_events[i]) != PFMLIB_SUCCESS) errx(1, "cannot find %s event", *p); } } else { if (pfm_get_cycle_event(&inp.pfp_events[0]) != PFMLIB_SUCCESS) errx(1, "cannot find cycle event"); if (pfm_get_inst_retired_event(&inp.pfp_events[1]) != PFMLIB_SUCCESS) errx(1, "cannot find inst retired event"); i = 2; } /* * set the privilege mode: * PFM_PLM3 : user level * PFM_PLM0 : kernel level */ inp.pfp_dfl_plm = PFM_PLM3|PFM_PLM0; if (i > num_counters) { i = num_counters; warnx("too many events provided (max=%d events), using first %d event(s)", num_counters, i); } /* * how many counters we use */ inp.pfp_event_count = i; /* * indicate we are using the monitors for a system-wide session. * This may impact the way the library sets up the PMC values. */ inp.pfp_flags = PFMLIB_PFP_SYSTEMWIDE; /* * In system wide mode, the perfmon context cannot be inherited. * Also in this mode, we cannot use the blocking form of user level notification. */ ctx[0].ctx_flags = PFM_FL_SYSTEM_WIDE; /* * pick a random CPU. Assumes CPU are numbered with no holes */ srandom(getpid()); kern_cpu = random() % sysconf(_SC_NPROCESSORS_ONLN); user_cpu = (kern_cpu+1) % sysconf(_SC_NPROCESSORS_ONLN); /* * The monitored CPU is determined by the processor core * executing the PFM_LOAD_CONTEXT command. To ensure, we * measure the right core, we pin the thread before making * the call. */ ret = pin_cpu(getpid(), user_cpu); if (ret == -1) err(1, "cannot set affinity to CPU%d", user_cpu); printf("user program pinned to CPU%d\n", user_cpu); printf("monitoring CPU%d\n", kern_cpu); /* * after the call the task is pinned to which_cpu */ /* * now create the context for self monitoring/per-task */ ctx_fd = pfm_create_context(ctx, NULL, NULL, 0); if (ctx_fd == -1) { if (errno == ENOSYS) { errx(1, "your kernel does not have performance monitoring support!\n"); } err(1, "cannot create context"); } /* * build the pfp_unavail_pmcs bitmask by looking * at what perfmon has available. It is not always * the case that all PMU registers are actually available * to applications. For instance, on IA-32 platforms, some * registers may be reserved for the NMI watchdog timer. * * With this bitmap, the library knows which registers NOT to * use. Of source, it is possible that no valid assignement may * be possible if certina PMU registers are not available. */ detect_unavail_pmcs(ctx_fd, &inp.pfp_unavail_pmcs); /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) errx(1, "cannot configure events: %s", pfm_strerror(ret)); /* * Now prepare the argument to initialize the PMDs and PMCS. * We use pfp_pmc_count to determine the number of PMC to intialize. * We use pfp_pmd_count to determine the number of PMD to initialize. * Some events/features may cause extra PMCs to be used, leading to: * - pfp_pmc_count may be >= pfp_event_count * - pfp_pmd_count may be >= pfp_event_count */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * Now program the registers */ if (pfm_write_pmcs(ctx_fd, pc, outp.pfp_pmc_count)) err(1, "pfm_write_pmcs error"); if (pfm_write_pmds(ctx_fd, pd, outp.pfp_pmd_count)) err(1, "pfm_write_pmds error"); /* * in system-wide mode, this field must provide the CPU the caller wants * to monitor. The kernel checks and if calling from the wrong CPU, the * call fails. The affinity is not affected. */ load_args.load_pid = kern_cpu; if (pfm_load_context(ctx_fd, &load_args)) err(1, "pfm_load_context error"); printf("\n", kern_cpu); /* * start monitoring */ if (pfm_start(ctx_fd, NULL) == -1) err(1, "pfm_start error"); for(l=0; l < 10; l++) { sleep(2); /* * read the results */ if (pfm_read_pmds(ctx_fd, pd, inp.pfp_event_count)) err(1, "pfm_read_pmds error"); /* * print the results */ puts("------------------------"); for (i=0; i < inp.pfp_event_count; i++) { pfm_get_full_event_name(&inp.pfp_events[i], name, MAX_EVT_NAME_LEN); printf("CPU%-2d PMD%-3u raw=%-20"PRIu64" delta=%-20"PRIu64" %s\n", kern_cpu, pd[i].reg_num, pd[i].reg_value, pd[i].reg_value - pdo[i], name); pdo[i] = pd[i].reg_value; } } /* * stop monitoring. * changed at the user level. */ if (pfm_stop(ctx_fd)) err(1, "pfm_stop error"); /* * destroy everything */ close(ctx_fd); return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/multiplex2.c0000644000307100002310000007521313013651447022104 0ustar yarkhangraduate/* * multiplex2.c - example of kernel-level time-based or overflow-based event multiplexing * * Copyright (c) 2004-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA * 02111-1307 USA */ #ifndef _GNU_SOURCE #define _GNU_SOURCE /* for getline */ #endif #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "detect_pmcs.h" #define MAX_EVT_NAME_LEN 128 #define MULTIPLEX_VERSION "0.2" #define SMPL_FREQ_IN_HZ 100 #define NUM_PMCS 256 typedef struct { struct { int opt_plm; /* which privilege level to monitor (more than one possible) */ int opt_debug; /* print debug information */ int opt_verbose; /* verbose output */ int opt_us_format; /* print large numbers with comma for thousands */ int opt_ovfl_switch; /* overflow-based switching */ int opt_is_system; /* use system-wide */ int opt_excl_idle; /* exclude idle task */ int opt_excl_intr; /* exclude interrupts */ int opt_intr_only; /* interrupts only*/ int opt_no_cmd_out; /* redirect cmd output to /dev/null */ int opt_no_header; /* no header */ } program_opt_flags; unsigned long max_counters; /* maximum number of counter for the platform */ uint64_t smpl_freq_hz; uint64_t smpl_freq_ns; unsigned long session_timeout; uint64_t smpl_period; uint64_t clock_res; unsigned long cpu_mhz; pid_t attach_pid; int pin_cmd_cpu; int pin_cpu; } program_options_t; #define opt_plm program_opt_flags.opt_plm #define opt_debug program_opt_flags.opt_debug #define opt_verbose program_opt_flags.opt_verbose #define opt_us_format program_opt_flags.opt_us_format #define opt_ovfl_switch program_opt_flags.opt_ovfl_switch #define opt_is_system program_opt_flags.opt_is_system #define opt_excl_idle program_opt_flags.opt_excl_idle #define opt_excl_intr program_opt_flags.opt_excl_intr #define opt_intr_only program_opt_flags.opt_intr_only #define opt_no_cmd_out program_opt_flags.opt_no_cmd_out #define opt_no_header program_opt_flags.opt_no_header typedef struct _event_set_t { struct _event_set_t *next; char *event_str; unsigned int n_events; } event_set_t; typedef int pfm_ctxid_t; static program_options_t options; static pfarg_pmc_t *all_pmcs; static pfarg_pmd_t *all_pmds; static pfarg_setdesc_t *all_sets; static event_set_t *all_events; static unsigned int num_pmds, num_pmcs, num_sets, total_events; static volatile int time_to_quit; static jmp_buf jbuf; static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void vbprintf(char *fmt, ...) { va_list ap; if (options.opt_verbose == 0) return; va_start(ap, fmt); vprintf(fmt, ap); va_end(ap); } static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } /* * unreliable for CPU with variable clock speed */ static unsigned long get_cpu_speed(void) { FILE *fp1; unsigned long f1 = 0, f2 = 0; char buffer[128], *p, *value; memset(buffer, 0, sizeof(buffer)); fp1 = fopen("/proc/cpuinfo", "r"); if (fp1 == NULL) return 0; for (;;) { buffer[0] = '\0'; p = fgets(buffer, 127, fp1); if (p == NULL) break; /* skip blank lines */ if (*p == '\n') continue; p = strchr(buffer, ':'); if (p == NULL) break; /* * p+2: +1 = space, +2= firt character * strlen()-1 gets rid of \n */ *p = '\0'; value = p+2; value[strlen(value)-1] = '\0'; if (!strncasecmp("cpu MHz", buffer, 7)) { float fl; sscanf(value, "%f", &fl); f1 = lroundf(fl); break; } if (!strncasecmp("BogoMIPS", buffer, 8)) { float fl; sscanf(value, "%f", &fl); f2 = lroundf(fl); } } fclose(fp1); return f1 == 0 ? f2 : f1; } /* * pin task to CPU */ #ifndef __NR_sched_setaffinity #error "you need to define __NR_sched_setaffinity" #endif #define MAX_CPUS 2048 #define NR_CPU_BITS (MAX_CPUS>>3) int pin_cpu(pid_t pid, unsigned int cpu) { uint64_t my_mask[NR_CPU_BITS]; if (cpu >= MAX_CPUS) fatal_error("this program supports only up to %d CPUs\n", MAX_CPUS); my_mask[cpu>>6] = 1ULL << (cpu&63); return syscall(__NR_sched_setaffinity, pid, sizeof(my_mask), &my_mask); } int child(char **arg) { ptrace(PTRACE_TRACEME, 0, NULL, NULL); if (options.pin_cmd_cpu != -1) { pin_cpu(getpid(), options.pin_cmd_cpu); vbprintf("command running on CPU core %d\n", options.pin_cmd_cpu); } if (options.opt_no_cmd_out) { close(1); close(2); } execvp(arg[0], arg); /* not reached */ exit(1); } static void dec2sep(char *str2, char *str, char sep) { int i, l, b, j, c=0; l = strlen(str2); if (l <= 3) { strcpy(str, str2); return; } b = l + l /3 - (l%3 == 0); /* l%3=correction to avoid extraneous comma at the end */ for(i=l, j=0; i >= 0; i--, j++) { if (j) c++; str[b-j] = str2[i]; if (c == 3 && i>0) { str[b-++j] = sep; c = 0; } } } static void print_results(int ctxid, uint64_t *eff_timeout) { unsigned int i, j, cnt, ovfl_event; uint64_t value, tot_runs = 0; uint64_t tot_dur = 0, c; pfarg_setinfo_t *all_setinfos; event_set_t *e; char *p; char tmp1[32], tmp2[32], *str; char mtotal_str[32], *mtotal; char stotal_str[32], *stotal; int ret; all_setinfos = malloc(sizeof(pfarg_setinfo_t)*num_sets); if (all_setinfos == NULL) fatal_error("cannot allocate all_setinfo\n"); memset(all_setinfos, 0, sizeof(pfarg_setinfo_t)*num_sets); for(i=0; i < num_sets; i++) all_setinfos[i].set_id = i; /* * read all counters in one call * * There is a limitation on the size of the argument vector and * it may be necesarry to split into multiple calls. That limit * is usally at page size (16KB) */ ret = pfm_read_pmds(ctxid, all_pmds, num_pmds); if (ret == -1) fatal_error("cannot read pmds: %s\n", strerror(errno)); /* * extract all set information * * There is a limitation on the size of the argument vector and * it may be necesarry to split into multiple calls. That limit * is usually at page size (16KB) */ ret = pfm_getinfo_evtsets(ctxid, all_setinfos, num_sets); if (ret == -1) fatal_error("cannot get set info: %s\n", strerror(errno)); /* * compute average number of runs * * the number of runs per set can be at most off by 1 between all sets */ for (i=0, cnt = 0; i < num_sets; i++) { if (all_setinfos[i].set_runs == 0) fatal_error("not enough runs to collect meaningful results: set%u did not run\n", i); tot_runs += all_setinfos[i].set_runs; tot_dur += all_setinfos[i].set_act_duration; } /* * print the results * * It is important to realize, that the first event we specified may not * be in PMD4. Not all events can be measured by any monitor. That's why * we need to use the pc[] array to figure out where event i was allocated. * */ if (options.opt_no_header == 0) { printf("# %.2fHz period = %"PRIu64"nsecs\n# %"PRIu64" cycles @ %lu MHz\n", 1000000000.0 / options.smpl_freq_ns, options.smpl_freq_ns, options.smpl_period, options.cpu_mhz); if (options.opt_ovfl_switch == 0) printf("# using time-based multiplexing\n" "# %"PRIu64" nsecs effective switch timeout\n", *eff_timeout); else printf("# using overflow-based multiplexing\n"); if (options.opt_is_system) printf("# system-wide mode on CPU core %d\n",options.pin_cpu); printf("# %d sets\n", num_sets); printf("# %.2f average run per set\n", (double)tot_runs/num_sets); printf("# %.2f average ns per set\n", (double)tot_dur/num_sets); printf("# set measured total #runs scaled total event name\n"); printf("# ------------------------------------------------------------------\n"); } ovfl_event = options.opt_ovfl_switch ? 1 : 0; for (i=0, e = all_events, cnt = 0; i < num_sets; i++, e = e->next) { str = e->event_str; for(j=0; j < e->n_events-ovfl_event; j++, cnt++) { value = all_pmds[cnt].reg_value; sprintf(tmp1, "%"PRIu64, value); if (options.opt_us_format) { dec2sep(tmp1, mtotal_str, ','); } else { strcpy(mtotal_str, tmp1); } mtotal = mtotal_str; /* * scaling * We use duration rather than number of runs to compute a more precise * scaled value. This avoids overcounting when the last set only partially * ran. * * We use double to avoid overflowing of the 64-bit count in case of very * large total duration */ c = llround(((double)value*tot_dur)/(double)all_setinfos[i].set_act_duration); sprintf(tmp2, "%"PRIu64, c); if (options.opt_us_format) { dec2sep(tmp2, stotal_str, ','); } else { strcpy(stotal_str, tmp2); } stotal = stotal_str; printf(" %03d %20s %8"PRIu64" %20s %s\n", i, mtotal, all_setinfos[i].set_runs, stotal, str); p = strchr(str, '\0'); if (p) str = p+1; } /* * skip first event */ if (options.opt_ovfl_switch) cnt++; } } static void sigintr_handler(int sig) { if (sig == SIGALRM) time_to_quit = 1; else time_to_quit = 2; longjmp(jbuf, 1); } static int measure_one_task(char **argv) { int ctxid; pfarg_ctx_t ctx[1]; pfarg_setdesc_t *my_sets; pfarg_pmc_t *my_pmcs; pfarg_pmd_t *my_pmds; pfarg_load_t load_arg; uint64_t eff_timeout; pfarg_msg_t msg; pid_t pid; int status, ret; my_pmcs = malloc(sizeof(pfarg_pmc_t)*num_pmcs); my_pmds = malloc(sizeof(pfarg_pmd_t)*num_pmds); my_sets = malloc(sizeof(pfarg_setdesc_t)*num_sets); if (my_pmcs == NULL || my_pmds == NULL || my_sets == NULL) fatal_error("cannot allocate event tables\n"); /* * make private copies */ memcpy(my_pmcs, all_pmcs, sizeof(pfarg_pmc_t)*num_pmcs); memcpy(my_pmds, all_pmds, sizeof(pfarg_pmd_t)*num_pmds); memcpy(my_sets, all_sets, sizeof(pfarg_setdesc_t)*num_sets); memset(ctx, 0, sizeof(ctx)); memset(&load_arg, 0, sizeof(load_arg)); /* * create the context */ ctxid = pfm_create_context(ctx, NULL, NULL, 0); if (ctxid == -1 ) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * set close-on-exec to ensure we will be getting the PFM_END_MSG, i.e., * fd not visible to child. */ if (fcntl(ctxid, F_SETFD, FD_CLOEXEC)) fatal_error("cannot set CLOEXEC: %s\n", strerror(errno)); /* * create the event sets * * event set 0 is always exist by default for backward compatibility * reason. However to avoid special casing set0 for creation, a PFM_CREATE_EVTSETS * for set0 does not complain and behaves as a PFM_CHANGE_EVTSETS */ vbprintf("requested timeout %"PRIu64" nsecs\n", my_sets[0].set_timeout); if (pfm_create_evtsets(ctxid, my_sets, num_sets)) fatal_error("cannot create sets\n"); eff_timeout = my_sets[0].set_timeout; vbprintf("effective timeout %"PRIu64" nsecs\n", my_sets[0].set_timeout); /* * Now program the all the registers in one call * * Note that there is a limitation on the size of the argument vector * that can be passed. It is usually set to a page size (16KB). */ if (pfm_write_pmcs(ctxid, my_pmcs, num_pmcs) == -1) fatal_error("pfm_write_pmcs error errno %d\n",errno); /* * initialize the PMD registers. * * To be read, each PMD must be either written or declared * as being part of a sample (reg_smpl_pmds) */ if (pfm_write_pmds(ctxid, my_pmds, num_pmds) == -1) fatal_error("pfm_write_pmds error errno %d\n",errno); /* * now launch the child code */ if (options.attach_pid == 0) { if ((pid= fork()) == -1) fatal_error("Cannot fork process\n"); if (pid == 0) exit(child(argv)); } else { pid = options.attach_pid; ret = ptrace(PTRACE_ATTACH, pid, NULL, 0); if (ret) { fatal_error("cannot attach to task %d: %s\n",options.attach_pid, strerror(errno)); } } ret = waitpid(pid, &status, WUNTRACED); if (ret < 0 || WIFEXITED(status)) fatal_error("error command already terminated, exit code %d\n", WEXITSTATUS(status)); vbprintf("child created and stopped\n"); /* * now attach the context */ load_arg.load_pid = pid; if (pfm_load_context(ctxid, &load_arg) == -1) fatal_error("pfm_load_context error errno %d\n",errno); /* * start monitoring */ if (pfm_start(ctxid, NULL) == -1) fatal_error("pfm_start error errno %d\n",errno); ptrace(PTRACE_DETACH, pid, NULL, 0); vbprintf("child restarted\n"); if (setjmp(jbuf) == 1) { if (time_to_quit == 1) { printf("timeout expired\n"); } if (time_to_quit == 2) printf("session interrupted\n"); goto finish_line; } signal(SIGALRM, sigintr_handler); signal(SIGINT, sigintr_handler); if (options.session_timeout) { printf("\n", options.session_timeout); alarm(options.session_timeout); } /* * mainloop */ ret = read(ctxid, &msg, sizeof(msg)); if (ret < sizeof(msg)) fatal_error("interrupted read\n"); switch(msg.type) { case PFM_MSG_OVFL: fatal_error("unexpected ovfl message\n"); break; case PFM_MSG_END: break; default: printf("unknown message type %d\n", msg.type); } finish_line: /* * cleanup after an alarm timeout */ if (time_to_quit) { /* stop monitored task */ ptrace(PTRACE_ATTACH, pid, NULL, 0); waitpid(pid, NULL, WUNTRACED); /* detach context */ pfm_unload_context(ctxid); } if (options.attach_pid == 0) { kill(pid, SIGKILL); waitpid(pid, &status, 0); } else { ptrace(PTRACE_DETACH, pid, NULL, 0); } if (time_to_quit < 2) print_results(ctxid, &eff_timeout); close(ctxid); return 0; } static int measure_one_cpu(char **argv) { int ctxid, status; pfarg_ctx_t ctx[1]; pfarg_pmc_t *my_pmcs; pfarg_pmd_t *my_pmds; pfarg_setdesc_t *my_sets; pfarg_load_t load_arg; pid_t pid = 0; int ret; my_pmcs = malloc(sizeof(pfarg_pmc_t)*total_events); my_pmds = malloc(sizeof(pfarg_pmd_t)*total_events); my_sets = malloc(sizeof(pfarg_setdesc_t)*num_sets); if (my_pmcs == NULL || my_pmds == NULL || my_sets == NULL) fatal_error("cannot allocate event tables\n"); /* * make private copies */ memcpy(my_pmcs, all_pmcs, sizeof(pfarg_pmc_t)*num_pmcs); memcpy(my_pmds, all_pmds, sizeof(pfarg_pmd_t)*num_pmds); memcpy(my_sets, all_sets, sizeof(pfarg_setdesc_t)*num_sets); memset(ctx, 0, sizeof(ctx)); memset(&load_arg, 0, sizeof(load_arg)); if (options.pin_cpu == -1) { options.pin_cpu = 0; printf("forcing monitoring onto CPU core 0\n"); pin_cpu(getpid(), 0); } ctx[0].ctx_flags = PFM_FL_SYSTEM_WIDE; /* * create the context */ ctxid = pfm_create_context(ctx, NULL, NULL, 0); if (ctxid == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * set close-on-exec to ensure we will be getting the PFM_END_MSG, i.e., * fd not visible to child. */ if (fcntl(ctxid, F_SETFD, FD_CLOEXEC)) fatal_error("cannot set CLOEXEC: %s\n", strerror(errno)); /* * create the event sets * * event set 0 is always created by default for backward compatibility * reason. However to avoid special casing set0 for creation, a PFM_CREATE_EVTSETS * for set0 does not complain and behaves as a PFM_CHANGE_EVTSETS */ if (pfm_create_evtsets(ctxid, my_sets, num_sets)) fatal_error("cannot create sets\n"); /* * Now program the all the registers in one call * * Note that there is a limitation on the size of the argument vector * that can be passed. It is usually set to a page size (16KB). */ if (pfm_write_pmcs(ctxid, my_pmcs, num_pmcs) == -1) fatal_error("pfm_write_pmcs error errno %d\n",errno); /* * initialize the PMD registers. * * To be read, each PMD must be either written or declared * as being part of a sample (reg_smpl_pmds) */ if (pfm_write_pmds(ctxid, my_pmds, num_pmds) == -1) fatal_error("pfm_write_pmds error errno %d\n",errno); /* * now launch the child code */ if (*argv) { if ((pid = fork()) == -1) fatal_error("Cannot fork process\n"); if (pid == 0) exit(child(argv)); } /* * wait for the child to exec or be stopped * We do this even in system-wide mode to ensure * that the task does not start until we are ready * to monitor. */ if (pid) { ret = waitpid(pid, &status, WUNTRACED); if (ret < 0 || WIFEXITED(status)) fatal_error("error command already terminated, exit code %d\n", WEXITSTATUS(status)); vbprintf("child created and stopped\n"); } /* * now attach the context */ load_arg.load_pid = options.opt_is_system ? getpid() : pid; if (pfm_load_context(ctxid, &load_arg) == -1) fatal_error("pfm_load_context error errno %d\n",errno); /* * start monitoring */ if (pfm_start(ctxid, NULL) == -1) fatal_error("pfm_start error errno %d\n",errno); if (pid) ptrace(PTRACE_DETACH, pid, NULL, 0); if (pid == 0) { if (options.session_timeout == 0) { printf("\n"); getchar(); } else { printf("\n", options.session_timeout); sleep(options.session_timeout); } } else { ret = waitpid(pid, &status, 0); } print_results(ctxid, &my_sets[0].set_timeout); if (ctxid) close(ctxid); return 0; } int mainloop(char **argv) { event_set_t *e; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_regmask_t impl_counters, used_pmcs; pfmlib_event_t cycle_event; unsigned int i, j; char *p, *str; int ret; unsigned int max_counters, allowed_counters; pfm_get_num_counters(&max_counters); if (max_counters < 2 && options.opt_ovfl_switch) fatal_error("not enough counter to get overflow switching to work\n"); allowed_counters = max_counters; /* * account for overflow counter (cpu cycles) */ if (options.opt_ovfl_switch) allowed_counters--; memset(&used_pmcs, 0, sizeof(used_pmcs)); memset(&impl_counters, 0, sizeof(impl_counters)); pfm_get_impl_counters(&impl_counters); options.smpl_period = (options.cpu_mhz*1000000)/options.smpl_freq_hz; vbprintf("%"PRIu64"Hz period = %"PRIu64" cycles @ %luMhz\n", options.smpl_freq_hz, options.smpl_period, options.cpu_mhz); for (e = all_events; e; e = e->next) { for (p = str = e->event_str; p ; ) { p = strchr(str, ','); if (p) str = p +1; total_events++; } } /* * account for extra event per set (cycle event) */ if (options.opt_ovfl_switch) { total_events += num_sets; /* * look for our trigger event */ if (pfm_get_cycle_event(&cycle_event) != PFMLIB_SUCCESS) fatal_error("Cannot find cycle event\n"); } vbprintf("total_events=%u\n", total_events); /* * assumes number of pmds = number of events * cannot assume number of pmcs = num of events (e.g., P4 2 PMCS per event) */ all_pmcs = calloc(NUM_PMCS, sizeof(pfarg_pmc_t)); all_pmds = calloc(total_events, sizeof(pfarg_pmd_t)); all_sets = calloc(num_sets, sizeof(pfarg_setdesc_t)); if (all_pmcs == NULL || all_pmds == NULL || all_sets == NULL) fatal_error("cannot allocate event tables\n"); /* * use the library to figure out assignments for all events of all sets */ for (i=0, e = all_events; i < num_sets; i++, e = e->next) { memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); /* * build the pfp_unavail_pmcs bitmask by looking * at what perfmon has available. It is not always * the case that all PMU registers are actually available * to applications. For instance, on IA-32 platforms, some * registers may be reserved for the NMI watchdog timer. * * With this bitmap, the library knows which registers NOT to * use. Of source, it is possible that no valid assignement may * be possible if certina PMU registers are not available. */ detect_unavail_pmcs(-1, &inp.pfp_unavail_pmcs); str = e->event_str; for(j=0, p = str; p && j < allowed_counters; j++) { p = strchr(str, ','); if (p) *p = '\0'; ret = pfm_find_full_event(str, &inp.pfp_events[j]); if (ret != PFMLIB_SUCCESS) fatal_error("event %s for set %d event %d: %s\n", str, i, j, pfm_strerror(ret)); if (p) str = p + 1; } if (p) { fatal_error("error in set %d: cannot have more than %d event(s) per set %s\n", i, allowed_counters, options.opt_ovfl_switch ? "(overflow switch mode)": "(hardware limit)"); } /* * add the cycle event as the last event when we switch on overflow */ if (options.opt_ovfl_switch) { inp.pfp_events[j] = cycle_event; inp.pfp_event_count = j+1; inp.pfp_dfl_plm = options.opt_plm; e->n_events = j+1; } else { e->n_events = j; inp.pfp_event_count = j; } inp.pfp_dfl_plm = options.opt_plm; if (options.opt_is_system) inp.pfp_flags = PFMLIB_PFP_SYSTEMWIDE; vbprintf("PMU programming for set %d\n", i); /* * let the library do the hard work */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) fatal_error("cannot configure events for set %d: %s\n", i, pfm_strerror(ret)); /* * propagate from libpfm to kernel data structures */ for (j=0; j < outp.pfp_pmc_count; j++, num_pmcs++) { all_pmcs[num_pmcs].reg_num = outp.pfp_pmcs[j].reg_num; all_pmcs[num_pmcs].reg_value = outp.pfp_pmcs[j].reg_value; all_pmcs[num_pmcs].reg_set = i; } for (j=0; j < outp.pfp_pmd_count; j++, num_pmds++) { all_pmds[num_pmds].reg_num = outp.pfp_pmds[j].reg_num; all_pmds[num_pmds].reg_set = i; } /* * setup event set properties */ all_sets[i].set_id = i; if (options.opt_ovfl_switch) { all_sets[i].set_flags = PFM_SETFL_OVFL_SWITCH; /* * last counter contains our sampling counter * * the first overflow of our trigger counter does * trigger a switch. */ all_pmds[num_pmds-1].reg_ovfl_switch_cnt = 1; /* * We do this even in system-wide mode to ensure * that the task does not start until we are ready * to monitor. * setup the sampling period */ all_pmds[num_pmds-1].reg_value = - options.smpl_period; all_pmds[num_pmds-1].reg_short_reset = - options.smpl_period; all_pmds[num_pmds-1].reg_long_reset = - options.smpl_period; } else { /* * setup the switch timeout (in nanoseconds) * Note that the actual timeout may be bigger than requested * due to timer tick granularity. It is always advised to * check the set_timeout value upon return from set creation. * The structure will by then contain the actual timeout. */ all_sets[i].set_flags = PFM_SETFL_TIME_SWITCH; all_sets[i].set_timeout = options.smpl_freq_ns; } #ifdef __ia64__ if (options.opt_excl_intr && options.opt_is_system) all_sets[i].set_flags |= PFM_ITA_SETFL_EXCL_INTR; if (options.opt_intr_only && options.opt_is_system) all_sets[i].set_flags |= PFM_ITA_SETFL_INTR_ONLY; #endif } if (options.opt_is_system) return measure_one_cpu(argv); return measure_one_task(argv); } static struct option multiplex_options[]={ { "help", 0, 0, 1}, { "freq", 1, 0, 2 }, { "kernel-level", 0, 0, 3 }, { "user-level", 0, 0, 4 }, { "version", 0, 0, 5 }, { "set", 1, 0, 6 }, { "session-timeout", 1, 0, 7 }, { "attach-task", 1, 0, 8 }, { "pin-cmd", 1, 0, 9 }, { "cpu", 1, 0, 10 }, { "verbose", 0, &options.opt_verbose, 1 }, { "debug", 0, &options.opt_debug, 1 }, { "us-counter-format", 0, &options.opt_us_format, 1}, { "ovfl-switch", 0, &options.opt_ovfl_switch, 1}, { "system-wide", 0, &options.opt_is_system, 1}, #ifdef __ia64__ { "excl-intr", 0, &options.opt_excl_intr, 1}, { "intr-only", 0, &options.opt_intr_only, 1}, #endif { "no-cmd-output", 0, &options.opt_no_cmd_out, 1}, { "no-header", 0, &options.opt_no_header, 1}, { 0, 0, 0, 0} }; static void generate_default_sets(void) { event_set_t *es, *tail = NULL; pfmlib_event_t events[2]; size_t len; char *name; unsigned int i; int ret; ret = pfm_get_cycle_event(&events[0]); if (ret != PFMLIB_SUCCESS) fatal_error("cannot find cycle event\n"); ret = pfm_get_inst_retired_event(&events[1]); if (ret != PFMLIB_SUCCESS) fatal_error("cannot find instruction retired event\n"); pfm_get_max_event_name_len(&len); for (i=0; i < 2; i++) { name = malloc(len+1); if (name == NULL) fatal_error("cannot allocate space for event name\n"); pfm_get_full_event_name(events+i, name, len+1); es = (event_set_t *)malloc(sizeof(event_set_t)); if (es == NULL) fatal_error("cannot allocate new event set\n"); memset(es, 0, sizeof(*es)); es->event_str = name; es->next = NULL; es->n_events = 0; if (all_events == NULL) all_events = es; else tail->next = es; tail = es; } num_sets = i; } static void print_usage(char **argv) { printf("usage: %s [OPTIONS]... COMMAND\n", argv[0]); printf( "-h, --help\t\t\t\tdisplay this help and exit\n" "-V, --version\t\t\t\toutput version information and exit\n" "-u, --user-level\t\t\tmonitor at the user level for all events\n" "-k, --kernel-level\t\t\tmonitor at the kernel level for all events\n" "-c, --us-counter-format\t\t\tprint large counts with comma for thousands\n" "-p pid, --attach-task pid\t\tattach to a running task\n" "--set=ev1[,ev2,ev3,ev4,...]\t\tdescribe one set\n" "--freq=number\t\t\t\tset set switching frequency in Hz\n" "-c cpu, --cpu=cpu\t\t\tCPU to use for system-wide [default current]\n" "--ovfl-switch\t\t\t\tuse overflow based multiplexing (default: time-based)\n" "--verbose\t\t\t\tprint more information during execution\n" "--system-wide\t\t\t\tuse system-wide (only one CPU at a time)\n" "--excl-idle\t\t\t\texclude idle task(system-wide only)\n" "--excl-intr\t\t\t\texclude interrupt triggered execution(system-wide only)\n" "--intr-only\t\t\t\tinclude only interrupt triggered execution(system-wide only)\n" "--session-timeout=sec\t\t\tsession timeout in seconds (system-wide only)\n" "--no-cmd-output\t\t\t\toutput of executed command redirected to /dev/null\n" "--pin-cmd=cpu\t\t\t\tpin executed command onto a specific cpu\n" ); } int main(int argc, char **argv) { char *endptr = NULL; pfmlib_options_t pfmlib_options; event_set_t *tail = NULL, *es; unsigned long long_val; struct timespec ts; uint64_t f_ns, d, f_final; int c, ret; options.pin_cmd_cpu = options.pin_cpu = -1; while ((c=getopt_long(argc, argv,"+vhkuVct:p:", multiplex_options, 0)) != -1) { switch(c) { case 0: continue; /* fast path for options */ case 'h': case 1: print_usage(argv); exit(0); case 'v': options.opt_verbose = 1; break; case 'c': options.opt_us_format = 1; break; case 2: if (options.smpl_freq_hz) fatal_error("sampling frequency set twice\n"); options.smpl_freq_hz = strtoull(optarg, &endptr, 10); if (*endptr != '\0') fatal_error("invalid frequency: %s\n", optarg); break; case 3: case 'k': options.opt_plm |= PFM_PLM0; break; case 4: case 'u': options.opt_plm |= PFM_PLM3; break; case 'V': case 5: printf("multiplex version " MULTIPLEX_VERSION " Date: " __DATE__ "\n" "Copyright (C) 2004 Hewlett-Packard Company\n"); exit(0); case 6: es = (event_set_t *)malloc(sizeof(event_set_t)); if (es == NULL) fatal_error("cannot allocate new event set\n"); es->event_str = optarg; es->next = NULL; es->n_events = 0; if (all_events == NULL) all_events = es; else tail->next = es; tail = es; num_sets++; break; case 't': case 7: if (options.session_timeout) fatal_error("too many timeouts\n"); if (*optarg == '\0') fatal_error("--session-timeout needs an argument\n"); long_val = strtoul(optarg,&endptr, 10); if (*endptr != '\0') fatal_error("invalid number of seconds for timeout: %s\n", optarg); if (long_val >= UINT_MAX) fatal_error("timeout is too big, must be < %u\n", UINT_MAX); options.session_timeout = (unsigned int)long_val; break; case 'p': case 8: if (options.attach_pid) fatal_error("process to attach specified twice\n"); options.attach_pid = (pid_t)atoi(optarg); break; case 9: if (options.pin_cmd_cpu != -1) fatal_error("cannot pin command twice\n"); options.pin_cmd_cpu = atoi(optarg); break; case 10: if (options.pin_cpu != -1) fatal_error("cannot pin to more than one cpu\n"); options.pin_cpu = atoi(optarg); break; default: fatal_error(""); /* just quit silently now */ } } if (optind == argc && options.opt_is_system == 0 && options.attach_pid == 0) fatal_error("you need to specify a command to measure\n"); /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = options.opt_verbose; /* set to 1 for verbose */ pfm_set_options(&pfmlib_options); /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) fatal_error("Cannot initialize library: %s\n", pfm_strerror(ret)); if ((options.cpu_mhz = get_cpu_speed()) == 0) fatal_error("can't get CPU speed\n"); /* * extract kernel clock resolution */ clock_getres(CLOCK_MONOTONIC, &ts); options.clock_res = ts.tv_sec * 1000000000 + ts.tv_nsec; /* * adjust frequency to be a multiple of clock resolution * otherwise kernel will fail pfm_create_evtsets() */ /* * f_ns = run period in ns (1s/hz) * default switch period is clock resolution */ if (options.smpl_freq_hz == 0) f_ns = options.clock_res; else f_ns = 1000000000 / options.smpl_freq_hz; /* round up period in nanoseconds */ d = (f_ns+options.clock_res-1) / options.clock_res; /* final period (multilple of clock_res */ f_final = d * options.clock_res; if (options.opt_ovfl_switch) printf("clock_res=%"PRIu64"ns(%.2fHz) ask period=%"PRIu64"ns(%.2fHz) get period=%"PRIu64"ns(%.2fHz)\n", options.clock_res, 1000000000.0 / options.clock_res, f_ns, 1000000000.0 / f_ns, f_final, 1000000000.0 / f_final); if (f_ns != f_final) printf("Not getting the expected frequency due to kernel/hw limitation\n"); /* adjust period */ options.smpl_freq_ns = f_final; /* not used */ options.smpl_freq_hz = 1000000000 / f_final; if (options.opt_plm == 0) options.opt_plm = PFM_PLM3; if (num_sets == 0) generate_default_sets(); return mainloop(argv+optind); } papi-5.5.1/src/libpfm-3.y/examples_v2.x/task_smpl.c0000644000307100002310000003735413013651447022000 0ustar yarkhangraduate/* * task_smpl.c - example of a task sampling another one using a randomized sampling period * * Copyright (c) 2003-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "detect_pmcs.h" #define SAMPLING_PERIOD 100000 typedef struct { int opt_no_show; int opt_block; } options_t; typedef pfm_dfl_smpl_arg_t smpl_fmt_arg_t; typedef pfm_dfl_smpl_hdr_t smpl_hdr_t; typedef pfm_dfl_smpl_entry_t smpl_entry_t; typedef pfm_dfl_smpl_arg_t smpl_arg_t; #define FMT_NAME PFM_DFL_SMPL_NAME #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS static uint64_t collected_samples, collected_partial; static options_t options; static struct option the_options[]={ { "help", 0, 0, 1}, { "ovfl-block", 0, &options.opt_block, 1}, { "no-show", 0, &options.opt_no_show, 1}, { 0, 0, 0, 0} }; static void fatal_error(char *fmt,...) __attribute__((noreturn)); #define BPL (sizeof(uint64_t)<<3) #define LBPL 6 static inline void pfm_bv_set(uint64_t *bv, uint16_t rnum) { bv[rnum>>LBPL] |= 1UL << (rnum&(BPL-1)); } static inline int pfm_bv_isset(uint64_t *bv, uint16_t rnum) { return bv[rnum>>LBPL] & (1UL <<(rnum&(BPL-1))) ? 1 : 0; } static inline void pfm_bv_copy(uint64_t *d, uint64_t *j, uint16_t n) { if (n <= BPL) *d = *j; else { memcpy(d, j, (n>>LBPL)*sizeof(uint64_t)); } } static void warning(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); } static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } int child(char **arg) { /* * force the task to stop before executing the first * user level instruction */ ptrace(PTRACE_TRACEME, 0, NULL, NULL); execvp(arg[0], arg); /* not reached */ exit(1); } void show_task_rusage(const struct timeval *start, const struct timeval *end, const struct rusage *ru) { long secs, suseconds, end_usec; secs = end->tv_sec - start->tv_sec; end_usec = end->tv_usec; if (end_usec < start->tv_usec) { end_usec += 1000000; secs--; } suseconds = end_usec - start->tv_usec; printf ("real %ldh%02ldm%02ld.%03lds user %ldh%02ldm%02ld.%03lds sys %ldh%02ldm%02ld.%03lds\n", secs / 3600, (secs % 3600) / 60, secs % 60, suseconds / 1000, ru->ru_utime.tv_sec / 3600, (ru->ru_utime.tv_sec % 3600) / 60, ru->ru_utime.tv_sec% 60, (long)(ru->ru_utime.tv_usec / 1000), ru->ru_stime.tv_sec / 3600, (ru->ru_stime.tv_sec % 3600) / 60, ru->ru_stime.tv_sec% 60, (long)(ru->ru_stime.tv_usec / 1000) ); } static void process_smpl_buf(smpl_hdr_t *hdr, uint64_t *smpl_pmds, unsigned int num_smpl_pmds, size_t entry_size) { static uint64_t last_overflow = ~0; /* initialize to biggest value possible */ static uint64_t last_count; smpl_entry_t *ent; size_t pos, count; uint64_t entry, *reg; unsigned int j, n; if (hdr->hdr_overflows == last_overflow && hdr->hdr_count == last_count) { warning("skipping identical set of samples %"PRIu64" = %"PRIu64"\n", hdr->hdr_overflows, last_overflow); return; } count = hdr->hdr_count; if (options.opt_no_show) { collected_samples += count; return; } ent = (smpl_entry_t *)(hdr+1); pos = (unsigned long)ent; entry = collected_samples; while(count--) { printf("entry %"PRIu64" PID:%d TID:%d CPU:%d LAST_VAL:%"PRIu64" IIP:0x%llx\n", entry, ent->tgid, ent->pid, ent->cpu, -ent->last_reset_val, (unsigned long long)ent->ip); /* * print body: additional PMDs recorded * PMD are recorded in increasing index order */ reg = (uint64_t *)(ent+1); n = num_smpl_pmds; for(j=0; n; j++) { if (pfm_bv_isset(smpl_pmds, j)) { printf("PMD%-3d:0x%016"PRIx64"\n", j, *reg); reg++; n--; } } pos += entry_size; ent = (smpl_entry_t *)pos; entry++; } collected_samples = entry; last_overflow = hdr->hdr_overflows; if (last_count != hdr->hdr_count && (last_count || last_overflow == 0)) collected_partial += hdr->hdr_count; last_count = hdr->hdr_count; } int mainloop(char **arg) { smpl_hdr_t *hdr; pfarg_ctx_t ctx; smpl_arg_t buf_arg; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfarg_pmd_t pd[NUM_PMDS]; pfarg_pmc_t pc[NUM_PMCS]; pfarg_load_t load_args; struct timeval start_time, end_time; struct rusage rusage; pfarg_msg_t msg; uint64_t ovfl_count = 0; size_t entry_size; void *buf_addr; pid_t pid; int status, ret, fd; unsigned int i, num_counters; unsigned int max_pmd = 0, num_smpl_pmds = 0; /* * intialize all locals */ memset(&ctx, 0, sizeof(ctx)); memset(&buf_arg, 0, sizeof(buf_arg)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(pd, 0, sizeof(pd)); memset(pc, 0, sizeof(pc)); memset(&load_args, 0, sizeof(load_args)); pfm_get_num_counters(&num_counters); if (pfm_get_cycle_event(&inp.pfp_events[0]) != PFMLIB_SUCCESS) fatal_error("cannot find cycle event\n"); if (pfm_get_inst_retired_event(&inp.pfp_events[1]) != PFMLIB_SUCCESS) fatal_error("cannot find inst retired event\n"); i = 2; /* * set the privilege mode: * PFM_PLM3 : user level * PFM_PLM0 : kernel level */ inp.pfp_dfl_plm = PFM_PLM3; if (i > num_counters) { i = num_counters; printf("too many events provided (max=%d events), using first %d event(s)\n", num_counters, i); } /* * how many counters we use */ inp.pfp_event_count = i; /* * build the pfp_unavail_pmcs bitmask by looking * at what perfmon has available. It is not always * the case that all PMU registers are actually available * to applications. For instance, on IA-32 platforms, some * registers may be reserved for the NMI watchdog timer. * * With this bitmap, the library knows which registers NOT to * use. Of source, it is possible that no valid assignement may * be possible if certina PMU registers are not available. */ detect_unavail_pmcs(-1, &inp.pfp_unavail_pmcs); /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); /* * Now prepare the argument to initialize the PMDs and PMCS. * We use pfp_pmc_count to determine the number of PMC to intialize. * We use pfp_pmd_count to determine the number of PMD to initialize. * Some events/features may cause extra PMCs to be used, leading to: * - pfp_pmc_count may be >= pfp_event_count * - pfp_pmd_count may be >= pfp_event_count */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } for (i=0; i < outp.pfp_pmd_count; i++) { pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * skip first counter (sampling period) * track highest PMD */ if (i) { pfm_bv_set(pd[0].reg_smpl_pmds, pd[i].reg_num); if (pd[i].reg_num > max_pmd) max_pmd = pd[i].reg_num; num_smpl_pmds++; } } /* * we our sampling counter overflow, we want to be notified. * The notification will come ONLY when the sampling buffer * becomes full. * * We also activate randomization of the sampling period. */ pd[0].reg_flags |= PFM_REGFL_OVFL_NOTIFY | PFM_REGFL_RANDOM; /* * we also want to reset the other PMDs on * every overflow. If we do not set * this, the non-overflowed counters * will be untouched. */ pfm_bv_copy(pd[0].reg_reset_pmds, pd[0].reg_smpl_pmds, max_pmd); pd[0].reg_value = - SAMPLING_PERIOD; pd[0].reg_short_reset = - SAMPLING_PERIOD; pd[0].reg_long_reset = - SAMPLING_PERIOD; /* * setup randomization parameters, we allow a range of up to +256 here. */ pd[0].reg_random_seed = 5; pd[0].reg_random_mask = 0xff; /* * in this example program, we use fixed-size entries, therefore we * can compute the entry size in advance. Perfmon-2 supports variable * size entries. */ entry_size = sizeof(smpl_entry_t)+(num_smpl_pmds<<3); printf("programming %u PMCS and %u PMDS\n", outp.pfp_pmc_count, inp.pfp_event_count); /* * prepare context structure. */ /* * We initialize the format specific information. * The format is identified by its UUID which must be copied * into the ctx_buf_fmt_id field. */ ctx.ctx_flags = options.opt_block ? PFM_FL_NOTIFY_BLOCK : 0; /* * the size of the buffer is indicated in bytes (not entries). * * The kernel will record into the buffer up to a certain point. * No partial samples are ever recorded. */ buf_arg.buf_size = 3*getpagesize()+512; /* * now create our perfmon context. */ fd = pfm_create_context(&ctx, FMT_NAME, &buf_arg, sizeof(buf_arg)); if (fd == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * retrieve the virtual address at which the sampling * buffer has been mapped */ buf_addr = mmap(NULL, (size_t)buf_arg.buf_size, PROT_READ, MAP_PRIVATE, fd, 0); if (buf_addr == MAP_FAILED) fatal_error("cannot mmap sampling buffer: %s\n", strerror(errno)); printf("buffer mapped @%p\n", buf_addr); hdr = (smpl_hdr_t *)buf_addr; printf("hdr_cur_offs=%llu version=%u.%u\n", (unsigned long long)hdr->hdr_cur_offs, PFM_VERSION_MAJOR(hdr->hdr_version), PFM_VERSION_MINOR(hdr->hdr_version)); if (PFM_VERSION_MAJOR(hdr->hdr_version) < 1) fatal_error("invalid buffer format version\n"); /* * Now program the registers */ if (pfm_write_pmcs(fd, pc, outp.pfp_pmc_count)) fatal_error("pfm_write_pmcs error errno %d\n",errno); /* * initialize the PMDs * To be read, each PMD must be either written or declared * as being part of a sample (reg_smpl_pmds, reg_reset_pmds) */ if (pfm_write_pmds(fd, pd, outp.pfp_pmd_count)) fatal_error("pfm_write_pmds error errno %d\n",errno); /* * Create the child task */ if ((pid=fork()) == -1) fatal_error("Cannot fork process\n"); /* * In order to get the PFM_END_MSG message, it is important * to ensure that the child task does not inherit the file * descriptor of the context. By default, file descriptor * are inherited during exec(). We explicitely close it * here. We could have set it up through fcntl(FD_CLOEXEC) * to achieve the same thing. */ if (pid == 0) { close(fd); child(arg); } /* * wait for the child to exec */ waitpid(pid, &status, WUNTRACED); /* * process is stopped at this point */ if (WIFEXITED(status)) { warning("task %s [%d] exited already status %d\n", arg[0], pid, WEXITSTATUS(status)); goto terminate_session; } /* * attach context to stopped task */ load_args.load_pid = pid; if (pfm_load_context (fd, &load_args)) fatal_error("pfm_load_context error errno %d\n",errno); /* * activate monitoring for stopped task. * (nothing will be measured at this point */ if (pfm_start(fd, NULL)) fatal_error("pfm_start error errno %d\n",errno); /* * detach child. Side effect includes * activation of monitoring. */ ptrace(PTRACE_DETACH, pid, NULL, 0); gettimeofday(&start_time, NULL); /* * core loop */ for(;;) { /* * wait for overflow/end notification messages */ ret = read(fd, &msg, sizeof(msg)); if (ret == -1) { if(ret == -1 && errno == EINTR) { warning("read interrupted, retrying\n"); continue; } fatal_error("cannot read perfmon msg: %s\n", strerror(errno)); } switch(msg.type) { case PFM_MSG_OVFL: /* the sampling buffer is full */ process_smpl_buf(hdr, pd[0].reg_smpl_pmds, num_smpl_pmds, entry_size); ovfl_count++; /* * reactivate monitoring once we are done with the samples * * Note that this call can fail with EBUSY in non-blocking mode * as the task may have disappeared while we were processing * the samples. */ if (pfm_restart(fd)) { if (errno != EBUSY) fatal_error("pfm_restart error errno %d\n",errno); else warning("pfm_restart: task probably terminated \n"); } break; case PFM_MSG_END: /* monitored task terminated */ printf("task terminated\n"); goto terminate_session; default: fatal_error("unknown message type %d\n", msg.type); } } terminate_session: /* * cleanup child */ wait4(pid, &status, 0, &rusage); gettimeofday(&end_time, NULL); /* * check for any leftover samples */ process_smpl_buf(hdr, pd[0].reg_smpl_pmds, num_smpl_pmds, entry_size); /* * close file descritor. Because of mmap() the number of reference to the * "file" is 2, thus the context is only freed when the last reference is closed * either by closed or munmap() depending on the order in which those calls are * made: * - close() -> munmap(): context and buffer destroyed after munmap(). * buffer remains accessible after close(). * - munmap() -> close(): buffer unaccessible after munmap(), context and * buffer destroyed after close(). * * It is important to free the resources cleanly, especially because the sampling * buffer reserves locked memory. */ close(fd); /* * unmap buffer, actually free the buffer and context because placed after * the close(), i.e. is the last reference. See comments about close() above. */ ret = munmap(hdr, (size_t)buf_arg.buf_size); if (ret) fatal_error("cannot unmap buffer: %s\n", strerror(errno)); printf("%"PRIu64" samples (%"PRIu64" in partial buffer) collected in %"PRIu64" buffer overflows\n", collected_samples, collected_partial, ovfl_count); show_task_rusage(&start_time, &end_time, &rusage); return 0; } static void usage(void) { printf("usage: task_smpl [-h] [--help] [--no-show] [--ovfl-block] cmd\n"); } int main(int argc, char **argv) { pfmlib_options_t pfmlib_options; int c, ret; while ((c=getopt_long(argc, argv,"h", the_options, 0)) != -1) { switch(c) { case 0: continue; case 1: case 'h': usage(); exit(0); default: fatal_error(""); } } if (argv[optind] == NULL) { fatal_error("You must specify a command to execute\n"); } /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 1; /* set to 1 for verbose */ pfm_set_options(&pfmlib_options); /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) fatal_error("Cannot initialize library: %s\n", pfm_strerror(ret)); return mainloop(argv+optind); } papi-5.5.1/src/libpfm-3.y/examples_v2.x/check_events.c0000644000307100002310000001016213013651447022430 0ustar yarkhangraduate/* * check_events.c - check if event assignment is possible * * Copyright (c) 2008 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #include #include #include #include #include #include #include #include #include #include #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_PMU_NAME_LEN 32 static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } /* * The goal of this program is to exercise the event assignment * code for a specific PMU model. This program is independent of * the kernel API. */ int main(int argc, char **argv) { char **p; unsigned int i; int ret; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_options_t pfmlib_options; char model[MAX_PMU_NAME_LEN]; unsigned int num_counters; /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 0; /* set to 1 for verbose */ pfm_set_options(&pfmlib_options); /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) fatal_error("Cannot initialize library: %s\n", pfm_strerror(ret)); pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); printf("PMU model: %s\n", model); pfm_get_num_counters(&num_counters); printf("%u counters available\n", num_counters); /* * prepare parameters to library. */ memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); /* * be nice to user! */ if (argc > 1) { p = argv+1; for (i=0; *p ; i++, p++) { ret = pfm_find_full_event(*p, &inp.pfp_events[i]); if (ret != PFMLIB_SUCCESS) fatal_error("event %s: %s\n", *p, pfm_strerror(ret)); } } else { if (pfm_get_cycle_event(&inp.pfp_events[0]) != PFMLIB_SUCCESS) fatal_error("cannot find cycle event\n"); if (pfm_get_inst_retired_event(&inp.pfp_events[1]) != PFMLIB_SUCCESS) fatal_error("cannot find inst retired event\n"); i = 2; } /* * set the default privilege mode for all counters: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; if (i > num_counters) { i = num_counters; printf("too many events provided (max=%d events), using first %d event(s)\n", num_counters, i); } /* * how many counters we use */ inp.pfp_event_count = i; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); for (i=0; i < outp.pfp_pmc_count; i++) printf("PMC%u=0x%llx\n", outp.pfp_pmcs[i].reg_num, outp.pfp_pmcs[i].reg_value); for (i=0; i < outp.pfp_pmd_count; i++) printf("PMD%u\n", outp.pfp_pmds[i].reg_num); return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/x86/0000755000307100002310000000000013013651447020250 5ustar yarkhangraduatepapi-5.5.1/src/libpfm-3.y/examples_v2.x/x86/smpl_p4_pebs.c0000644000307100002310000002627613013651447023020 0ustar yarkhangraduate/* * smpl_pebs.c - PEBS standalone (no libpfm) sampling example for P4/Xeon * (support 32-bit and 64-bit modes) * * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #ifndef _GNU_SOURCE #define _GNU_SOURCE /* for getline */ #endif #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define NUM_PMCS 32 #define NUM_PMDS 32 #define SMPL_PERIOD 100000ULL /* must not use more bits than actual HW counter width */ typedef pfm_pebs_p4_smpl_hdr_t smpl_hdr_t; typedef pfm_pebs_p4_smpl_entry_t smpl_entry_t; typedef pfm_pebs_p4_smpl_arg_t smpl_arg_t; #define FMT_NAME PFM_PEBS_P4_SMPL_NAME static uint64_t collected_samples; static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } static void warning(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); } int child(char **arg) { /* * force the task to stop before executing the first * user level instruction */ ptrace(PTRACE_TRACEME, 0, NULL, NULL); execvp(arg[0], arg); /* not reached */ exit(1); } static void process_smpl_buf(smpl_hdr_t *hdr) { static uint64_t last_overflow = ~0; /* initialize to biggest value possible */ static uint64_t last_count; smpl_entry_t *ent; unsigned long count; uint64_t entry; count = (hdr->ds.pebs_index - hdr->ds.pebs_buf_base)/sizeof(*ent); if (hdr->overflows == last_overflow && last_count == count) { warning("skipping identical set of samples %"PRIu64" = %"PRIu64"\n", hdr->overflows, last_overflow); return; } last_count = count; last_overflow = hdr->overflows; /* * the beginning of the buffer does not necessarily follow the header * due to alignement. */ ent = (smpl_entry_t *)((unsigned long)(hdr+1)+ hdr->start_offs); entry = collected_samples; while(count--) { printf("entry %06"PRIu64" eflags:0x%08lx EAX:0x%08lx ESP:0x%08lx IP:0x%08lx\n", entry, ent->eflags, ent->eax, ent->esp, ent->ip); ent++; entry++; } collected_samples = entry; } static int get_cpuinfo_attr(char *attr, char *ret_buf, size_t maxlen) { FILE *fp; int ret = -1; size_t attr_len, buf_len = 0; char *p, *value = NULL; char *buffer = NULL; if (attr == NULL || ret_buf == NULL || maxlen < 1) return -1; attr_len = strlen(attr); fp = fopen("/proc/cpuinfo", "r"); if (fp == NULL) return -1; while(getline(&buffer, &buf_len, fp) != -1){ /* skip blank lines */ if (*buffer == '\n') continue; p = strchr(buffer, ':'); if (p == NULL) goto error; /* * p+2: +1 = space, +2= firt character * strlen()-1 gets rid of \n */ *p = '\0'; value = p+2; value[strlen(value)-1] = '\0'; if (!strncmp(attr, buffer, attr_len)) break; } strncpy(ret_buf, value, maxlen-1); ret_buf[maxlen-1] = '\0'; ret = 0; error: free(buffer); fclose(fp); return ret; } static void check_valid_cpu(void) { int ret, siblings, family, cores; char buffer[128]; ret = get_cpuinfo_attr("vendor_id", buffer, sizeof(buffer)); if (ret == -1 || strcmp(buffer, "GenuineIntel")) fatal_error("this programs works only with Intel processors\n"); ret = get_cpuinfo_attr("cpu family", buffer, sizeof(buffer)); if (ret == -1) fatal_error("cannot determine processor family\n"); family = atoi(buffer); if (family != 15) fatal_error("this program only works for P4/Xeon with PEBS (found family=%d)\n", family); ret = get_cpuinfo_attr("siblings", buffer, sizeof(buffer)); if (ret == -1) fatal_error("cannot deterimine number of siblings\n"); siblings = atoi(buffer); ret = get_cpuinfo_attr("cpu cores", buffer, sizeof(buffer)); if (ret == -1) fatal_error("cannot determine number of cpu cores\n"); cores = atoi(buffer); if (siblings > cores) fatal_error("PEBS does not work when HyperThreading is enabled\n"); } int main(int argc, char **argv) { pfarg_pmd_t pd[NUM_PMDS]; pfarg_pmc_t pc[NUM_PMCS]; pfarg_ctx_t ctx; smpl_arg_t buf_arg; pfarg_load_t load_args; pfarg_msg_t msg; smpl_hdr_t *hdr; void *buf_addr; pid_t pid; int ret, fd, status, npmcs = 0; check_valid_cpu(); if (argc < 2) fatal_error("you need to pass a program to sample\n"); memset(pd, 0, sizeof(pd)); memset(pc, 0, sizeof(pc)); memset(&ctx, 0, sizeof(ctx)); memset(&buf_arg, 0, sizeof(buf_arg)); memset(&load_args, 0, sizeof(load_args)); buf_arg.buf_size = getpagesize(); buf_arg.cnt_reset = -SMPL_PERIOD; ctx.ctx_flags = 0; /* * trigger interrupt when reached 90% of buffer */ buf_arg.intr_thres = (buf_arg.buf_size/sizeof(smpl_entry_t))*90/100; fd = pfm_create_context(&ctx, FMT_NAME, &buf_arg, sizeof(buf_arg)); if (fd == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s, maybe you do not have the P4/Xeon PEBS sampling format in the kernel.\n Check /sys/kernel/perfmon\n", strerror(errno)); } /* * retrieve the virtual address at which the sampling * buffer has been mapped */ buf_addr = mmap(NULL, (size_t)buf_arg.buf_size, PROT_READ, MAP_PRIVATE, fd, 0); if (buf_addr == MAP_FAILED) fatal_error("cannot mmap sampling buffer errno %d\n", errno); printf("context [%d] buffer mapped @%p\n", fd, buf_addr); hdr = (smpl_hdr_t *)buf_addr; printf("pebs_base=0x%lx pebs_end=0x%lx index=0x%lx\n" "intr=0x%lx version=%u.%u\n" "entry_size=%zu ds_size=%zu\n", hdr->ds.pebs_buf_base, hdr->ds.pebs_abs_max, hdr->ds.pebs_index, hdr->ds.pebs_intr_thres, PFM_VERSION_MAJOR(hdr->version), PFM_VERSION_MINOR(hdr->version), sizeof(smpl_entry_t), sizeof(hdr->ds)); if (PFM_VERSION_MAJOR(hdr->version) < 1) fatal_error("invalid buffer format version\n"); /* * using the replay_event event * * CRU_ESCR2.usr=1 * CRU_ESCR2.event_mask=1 (NBOGUS) * CRU_ESCR2.event_select=0x9 (replay_event) */ pc[npmcs].reg_num = 21; pc[npmcs].reg_value = (9ULL <<25) | (1ULL<<9) |(1ULL<<2); npmcs++; /* * for PEBS, must use IQ_CCCR4 for thread0 * IQ_CCCR4.escr_select = 5 * IQ_CCCR4.enable= 1 * IQ_CCCR4.active_thread= 3 * * We must disable 64-bit emulation by the kernel * on the associated counter when using PEBS. Otherwise * we received a spurious interrupt for every counter overflow. */ pc[npmcs].reg_num = 31; pc[npmcs].reg_flags = PFM_REGFL_NO_EMUL64; pc[npmcs].reg_value = (5ULL << 13) | (1ULL<<12) | (3ULL<<16); npmcs++; /* * PEBS_MATRIX_VERT.bit0=1 (1st level cache load miss retired) */ pc[npmcs].reg_num = 63; pc[npmcs].reg_value = 1; npmcs++; /* * PEBS_ENABLE.enable=1 (bit0) * PEBS_ENABLE.uops=1 (bit 24) * PEBS_ENABLE.my_thr=1 (bit 25) */ pc[npmcs].reg_num = 64; pc[npmcs].reg_value = (1ULL<<25)|(1ULL<<24) | 1ULL; npmcs++; /* * Must use IQ_CCCR4/IQ_CTR4 with PEBS for thread0 * * IMPORTANT: * SMPL_PERIOD MUST not exceed width of HW counter * because no 64-bit virtualization is done by the * kernel. */ pd[0].reg_num = 8; pd[0].reg_flags = PFM_REGFL_OVFL_NOTIFY; pd[0].reg_value = -SMPL_PERIOD; pd[0].reg_long_reset = -SMPL_PERIOD; pd[0].reg_short_reset = -SMPL_PERIOD; /* * Now program the registers */ if (pfm_write_pmcs(fd, pc, npmcs) == -1) fatal_error("pfm_write_pmcs error errno %d\n",errno); if (pfm_write_pmds(fd, pd, 1) == -1) fatal_error("pfm_write_pmds error errno %d\n",errno); signal(SIGCHLD, SIG_IGN); /* * Create the child task */ if ((pid=fork()) == -1) fatal_error("Cannot fork process\n"); /* * In order to get the PFM_END_MSG message, it is important * to ensure that the child task does not inherit the file * descriptor of the context. By default, file descriptor * are inherited during exec(). We explicitely close it * here. We could have set it up through fcntl(FD_CLOEXEC) * to achieve the same thing. */ if (pid == 0) { close(fd); child(argv+1); } /* * wait for the child to exec */ waitpid(pid, &status, WUNTRACED); /* * process is stopped at this point */ if (WIFEXITED(status)) { warning("task %s [%d] exited already status %d\n", argv[1], pid, WEXITSTATUS(status)); goto terminate_session; } /* * attach the context to self */ load_args.load_pid = pid; if (pfm_load_context(fd, &load_args) == -1) fatal_error("pfm_load_context error errno %d\n",errno); /* * start monitoring */ if (pfm_start(fd, NULL) == -1) fatal_error("pfm_start error errno %d\n",errno); /* * detach child. Side effect includes * activation of monitoring. */ ptrace(PTRACE_DETACH, pid, NULL, 0); /* * core loop */ for(;;) { /* * wait for overflow/end notification messages */ ret = read(fd, &msg, sizeof(msg)); if (ret == -1) { if(ret == -1 && errno == EINTR) { warning("read interrupted, retrying\n"); continue; } fatal_error("cannot read perfmon msg: %s\n", strerror(errno)); } switch(msg.type) { case PFM_MSG_OVFL: /* the sampling buffer is full */ process_smpl_buf(hdr); /* * reactivate monitoring once we are done with the samples * * Note that this call can fail with EBUSY in non-blocking mode * as the task may have disappeared while we were processing * the samples. */ if (pfm_restart(fd) == -1) { if (errno != EBUSY) fatal_error("pfm_restart error errno %d\n",errno); else warning("pfm_restart: task has probably terminated \n"); } break; case PFM_MSG_END: /* monitored task terminated */ warning("task terminated\n"); goto terminate_session; default: fatal_error("unknown message type %d\n", msg.type); } } terminate_session: /* * cleanup child */ wait4(pid, &status, 0, NULL); /* * check for any leftover samples */ process_smpl_buf(hdr); munmap(buf_addr, (size_t)buf_arg.buf_size); close(fd); return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/x86/smpl_nhm_lbr.c0000644000307100002310000002564313013651447023102 0ustar yarkhangraduate/* * smpl_nhm_lbr.c - Intel Nehalem LBR sampling * * Copyright (c) 2008 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "../detect_pmcs.h" #define SAMPLING_PERIOD 100000 #define EVENT_NAME "br_inst_retired:all_branches" typedef pfm_dfl_smpl_arg_t smpl_fmt_arg_t; typedef pfm_dfl_smpl_hdr_t smpl_hdr_t; typedef pfm_dfl_smpl_entry_t smpl_entry_t; typedef pfm_dfl_smpl_arg_t smpl_arg_t; #define FMT_NAME PFM_DFL_SMPL_NAME #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS static jmp_buf jbuf; static uint64_t collected_samples, collected_partial, ovfl_count; static void fatal_error(char *fmt,...) __attribute__((noreturn)); #define BPL (sizeof(uint64_t)<<3) #define LBPL 6 static void handler (int n) { longjmp(jbuf, 1); } static inline void pfm_bv_set(uint64_t *bv, uint16_t rnum) { bv[rnum>>LBPL] |= 1UL << (rnum&(BPL-1)); } static void warning(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); } static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } int child(char **arg) { /* * force the task to stop before executing the first * user level instruction */ ptrace(PTRACE_TRACEME, 0, NULL, NULL); execvp(arg[0], arg); /* not reached */ exit(1); } static void process_smpl_buf(smpl_hdr_t *hdr) { static uint64_t last_overflow = ~0; /* initialize to biggest value possible */ static uint64_t last_count; smpl_entry_t *ent; size_t pos, count, entry_size; uint64_t entry, *reg; uint64_t tos, i; if (hdr->hdr_overflows == last_overflow && hdr->hdr_count == last_count) { warning("skipping identical set of samples %"PRIu64" = %"PRIu64"\n", hdr->hdr_overflows, last_overflow); return; } /* * 33 = 32 LBR registers + LBR_TOS */ entry_size = sizeof(smpl_entry_t) + 33 * sizeof(uint64_t); count = hdr->hdr_count; ent = (smpl_entry_t *)(hdr+1); pos = (unsigned long)ent; entry = collected_samples; while(count--) { printf("entry %"PRIu64" PID:%d TID:%d CPU:%d LAST_VAL:%"PRIu64" OVFL:%u IIP:0x%llx\n", entry, ent->tgid, ent->pid, ent->cpu, -ent->last_reset_val, ent->ovfl_pmd, (unsigned long long)ent->ip); /* * TOS is pmd31 and comes first * TOs points to most recent entry */ reg = (uint64_t *)(ent+1); tos = reg[0] * 2; /* * i points to oldest entry, the one to print first */ i = (tos + 2) % 32; /* * iterate over the 16 branches printing src -> dst */ while (i != tos) { printf("0x%016"PRIx64" -> 0x%016"PRIx64"\n", reg[1+i], reg[1+i+1]); i = (i + 2) % 32; } pos += entry_size; ent = (smpl_entry_t *)pos; entry++; } collected_samples = entry; last_overflow = hdr->hdr_overflows; if (last_count != hdr->hdr_count && (last_count || last_overflow == 0)) collected_partial += hdr->hdr_count; last_count = hdr->hdr_count; } int mainloop(char **arg) { smpl_hdr_t *hdr; pfarg_ctx_t ctx; smpl_arg_t buf_arg; pfmlib_input_param_t inp; pfmlib_nhm_input_param_t mod_inp; pfmlib_output_param_t outp; pfarg_pmd_t pd[NUM_PMDS]; pfarg_pmc_t pc[NUM_PMCS]; pfarg_load_t load_args; pfarg_msg_t msg; void *buf_addr; pid_t pid; int i, status, ret, fd; /* * intialize all locals */ memset(&ctx, 0, sizeof(ctx)); memset(&buf_arg, 0, sizeof(buf_arg)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(pd, 0, sizeof(pd)); memset(pc, 0, sizeof(pc)); memset(&load_args, 0, sizeof(load_args)); memset(&mod_inp, 0, sizeof(mod_inp)); ret = pfm_find_full_event(EVENT_NAME, &inp.pfp_events[0]); if (ret != PFMLIB_SUCCESS) fatal_error("cannot find event %s\n", EVENT_NAME); /* * set the privilege mode: * PFM_PLM3 : user level * PFM_PLM0 : kernel level */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = 1; mod_inp.pfp_nhm_lbr.lbr_used = 1; mod_inp.pfp_nhm_lbr.lbr_plm = 0; /* inherit from pfp_dfl_plm */ /* * setup LBR filter * * By default all types of branches are captured * * it is possible to filter out some types of branches using * the macros in pfmlib_intel_nhm.c. * * for instance, to only capture nears calls, you do: * * lbr_filter = PFM_NHM_LBR_NEAR_REL_CALL */ mod_inp.pfp_nhm_lbr.lbr_filter = 0; /* * the size of the buffer is indicated in bytes (not entries). * * The kernel will record into the buffer up to a certain point. * No partial samples are ever recorded. */ buf_arg.buf_size = 4 * getpagesize(); /* * now create our perfmon context. */ fd = pfm_create_context(&ctx, FMT_NAME, &buf_arg, sizeof(buf_arg)); if (fd == -1) { if (errno == ENOSYS) fatal_error("Your kernel does not have performance monitoring support!\n"); fatal_error("cannot create PFM context %s\n", strerror(errno)); } detect_unavail_pmcs(fd, &inp.pfp_unavail_pmcs); /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, &mod_inp, &outp, NULL)) != PFMLIB_SUCCESS) fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * we use only one counter */ pd[0].reg_num = outp.pfp_pmds[0].reg_num; pd[0].reg_flags = PFM_REGFL_OVFL_NOTIFY; /* * add 2 x 16 LBR entries + LBR_TOS to smpl_pmds */ for(i=31; i < 64; i++) pfm_bv_set(pd[0].reg_smpl_pmds, i); /* * we need to reset LBR after each sample to be able to determine * whether or not we get new data * * LBR_TOS(PMD31) is read-only, it is not included in reset_pmds */ for(i=32; i < 64; i++) pfm_bv_set(pd[0].reg_reset_pmds, i); /* * set sampling periods */ pd[0].reg_value = - SAMPLING_PERIOD; pd[0].reg_short_reset = - SAMPLING_PERIOD; pd[0].reg_long_reset = - SAMPLING_PERIOD; /* * prepare context structure. */ /* * retrieve the virtual address at which the sampling * buffer has been mapped */ buf_addr = mmap(NULL, (size_t)buf_arg.buf_size, PROT_READ, MAP_PRIVATE, fd, 0); if (buf_addr == MAP_FAILED) fatal_error("cannot mmap sampling buffer: %s\n", strerror(errno)); printf("buffer mapped @%p\n", buf_addr); hdr = (smpl_hdr_t *)buf_addr; printf("hdr_cur_offs=%llu version=%u.%u\n", (unsigned long long)hdr->hdr_cur_offs, PFM_VERSION_MAJOR(hdr->hdr_version), PFM_VERSION_MINOR(hdr->hdr_version)); if (PFM_VERSION_MAJOR(hdr->hdr_version) < 1) fatal_error("invalid buffer format version\n"); /* * program the PMCs */ if (pfm_write_pmcs(fd, pc, outp.pfp_pmc_count)) fatal_error("pfm_write_pmcs error errno %d\n",errno); /* * program our counter */ if (pfm_write_pmds(fd, pd, 1)) fatal_error("pfm_write_pmds error errno %d\n",errno); /* * create the child task */ if ((pid=fork()) == -1) fatal_error("Cannot fork process\n"); /* * create child * make sure child does not inherit the file descriptor */ if (pid == 0) { close(fd); child(arg); } /* * wait for the child to exec */ waitpid(pid, &status, WUNTRACED); /* * process is stopped at this point */ if (WIFEXITED(status)) { warning("task %s [%d] exited already status %d\n", arg[0], pid, WEXITSTATUS(status)); goto terminate_session; } /* * attach context to stopped task */ load_args.load_pid = pid; if (pfm_load_context (fd, &load_args)) fatal_error("pfm_load_context error errno %d\n",errno); /* * activate monitoring for stopped task. * (nothing will be measured at this point */ if (pfm_start(fd, NULL)) fatal_error("pfm_start error errno %d\n",errno); /* * detach child. Side effect includes * activation of monitoring. */ ptrace(PTRACE_DETACH, pid, NULL, 0); signal(SIGCHLD, handler); if (setjmp(jbuf) == 1) goto terminate_session; /* * core loop */ for(;;) { ret = read(fd, &msg, sizeof(msg)); if (ret == -1) { if(ret == -1 && errno == EINTR) { warning("read interrupted, retrying\n"); continue; } fatal_error("cannot read perfmon msg: %s\n", strerror(errno)); } if (msg.type == PFM_MSG_OVFL) { process_smpl_buf(hdr); ovfl_count++; /* * reactivate monitoring once we are done with the samples * * Note that this call can fail with EBUSY in non-blocking mode * as the task may have disappeared while we were processing * the samples. */ if (pfm_restart(fd)) { if (errno != EBUSY) fatal_error("pfm_restart error errno %d\n",errno); } } } terminate_session: /* * cleanup child */ wait4(pid, &status, 0, NULL); /* * check for any leftover samples */ process_smpl_buf(hdr); close(fd); ret = munmap(hdr, (size_t)buf_arg.buf_size); if (ret) fatal_error("cannot unmap buffer: %s\n", strerror(errno)); printf("%"PRIu64" samples (%"PRIu64" in partial buffer) collected in %"PRIu64" buffer overflows\n", collected_samples, collected_partial, ovfl_count); return 0; } int main(int argc, char **argv) { pfmlib_options_t pfmlib_options; int ret; if (argc == 1) fatal_error("You must specify a command to execute\n"); /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 1; /* set to 1 for verbose */ pfm_set_options(&pfmlib_options); /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) fatal_error("Cannot initialize library: %s\n", pfm_strerror(ret)); return mainloop(argv+1); } papi-5.5.1/src/libpfm-3.y/examples_v2.x/x86/smpl_pebs.c0000644000307100002310000002645513013651447022414 0ustar yarkhangraduate/* * smpl_pebs.c - Unified Intel PEBS sampling example * * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "../detect_pmcs.h" #define SMPL_EVENT "INST_RETIRED:ANY_P" /* PEBS event on all processors */ #define NUM_PMCS 16 #define NUM_PMDS 16 #define SMPL_PERIOD 240000ULL /* must not use more bits than actual HW counter width */ typedef pfm_pebs_smpl_hdr_t smpl_hdr_t; typedef pfm_pebs_smpl_arg_t smpl_arg_t; #define FMT_NAME PFM_PEBS_SMPL_NAME static uint64_t collected_samples; static uint64_t last_overflow = ~0; /* initialize to biggest value possible */ static void (*print_entry)(uint64_t entry, void *addr); static int maxpebs = 1; /* 1=Atom/Core, up to 4 on Nehalem */ int child(char **arg) { /* * force the task to stop before executing the first * user level instruction */ ptrace(PTRACE_TRACEME, 0, NULL, NULL); execvp(arg[0], arg); /* not reached */ exit(1); } static void print_p4_entry(uint64_t entry, void *addr) { pfm_pebs_p4_smpl_entry_t *ent = addr; printf("entry %06"PRIu64" eflags:0x%08llx EAX:0x%08llx ESP:0x%08llx IP:0x%08llx\n", entry, (unsigned long long)ent->eflags, (unsigned long long)ent->eax, (unsigned long long)ent->esp, (unsigned long long)ent->ip); } static void print_core_entry(uint64_t entry, void *addr) { pfm_pebs_core_smpl_entry_t *ent = addr; printf("entry %06"PRIu64" eflags:0x%08llx EAX:0x%08llx ESP:0x%08llx IP:0x%08llx\n", entry, (unsigned long long)ent->eflags, (unsigned long long)ent->eax, (unsigned long long)ent->esp, (unsigned long long)ent->ip); } static void print_nhm_entry(uint64_t entry, void *addr) { pfm_pebs_nhm_smpl_entry_t *ent = addr; printf("entry %06"PRIu64" eflags:0x%08llx EAX:0x%08llx ESP:0x%08llx IP:0x%08llx OVFL:0x%08llx\n", entry, (unsigned long long)ent->eflags, (unsigned long long)ent->eax, (unsigned long long)ent->esp, (unsigned long long)ent->ip, (unsigned long long)ent->ia32_perf_global_status); } static void process_smpl_buf(smpl_hdr_t *hdr) { static uint64_t last_count; void *ent; uint64_t entry; unsigned long count; count = hdr->count; if (hdr->overflows == last_overflow && last_count == count) { warnx("skipping identical set of samples %"PRIu64" = %"PRIu64"\n", hdr->overflows, last_overflow); return; } last_count = count; last_overflow = hdr->overflows; /* * the beginning of the buffer does not necessarily follow the header * due to alignement. */ ent = (hdr+1); entry = collected_samples; while(count--) { (*print_entry)(entry, ent); ent += hdr->entry_size; entry++; } collected_samples = entry; } int main(int argc, char **argv) { pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_core_input_param_t core_inp; pfmlib_nhm_input_param_t nhm_inp; void *mod_inp = NULL; pfmlib_options_t pfmlib_options; pfarg_pmd_t pd[NUM_PMDS]; pfarg_pmc_t pc[NUM_PMCS]; pfarg_ctx_t ctx; smpl_arg_t buf_arg; pfarg_load_t load_args; pfarg_msg_t msg; smpl_hdr_t *hdr; void *buf_addr; pid_t pid; int ret, fd, status, type; unsigned int i; if (argc < 2) errx(1, "you need to pass a program to sample"); if (pfm_initialize() != PFMLIB_SUCCESS) errx(1, "libpfm intialization failed"); memset(&core_inp, 0, sizeof(core_inp)); memset(&nhm_inp, 0, sizeof(nhm_inp)); /* * check we are on an Intel Core PMU */ pfm_get_pmu_type(&type); switch(type) { case PFMLIB_INTEL_CORE_PMU: case PFMLIB_INTEL_ATOM_PMU: print_entry = print_core_entry; core_inp.pfp_core_pebs.pebs_used = 1; mod_inp = &core_inp; break; case PFMLIB_INTEL_NHM_PMU: print_entry = print_nhm_entry; nhm_inp.pfp_nhm_pebs.pebs_used = 1; mod_inp = &nhm_inp; break; case PFMLIB_PENTIUM4_PMU: print_entry = print_p4_entry; break; default: errx(1, "PMU model does not have PEBS support"); } /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 1; /* set to 1 for verbose */ pfm_set_options(&pfmlib_options); memset(pd, 0, sizeof(pd)); memset(pc, 0, sizeof(pc)); memset(&inp, 0, sizeof(inp)); memset(&outp, 0, sizeof(outp)); memset(&ctx, 0, sizeof(ctx)); memset(&buf_arg, 0, sizeof(buf_arg)); memset(&load_args, 0, sizeof(load_args)); /* * search for our sampling event */ if (pfm_find_full_event(SMPL_EVENT, &inp.pfp_events[0]) != PFMLIB_SUCCESS) errx(1, "cannot find sampling event %s", SMPL_EVENT); for(i=1; i < maxpebs; i++) inp.pfp_events[i] = inp.pfp_events[0]; inp.pfp_event_count = i; inp.pfp_dfl_plm = PFM_PLM3|PFM_PLM0; /* * sampling buffer parameters */ buf_arg.buf_size = 2 * getpagesize(); for(i=0; i < maxpebs; i++) buf_arg.cnt_reset[i] = -SMPL_PERIOD; /* * create context and sampling buffer */ fd = pfm_create_context(&ctx, FMT_NAME, &buf_arg, sizeof(buf_arg)); if (fd == -1) { if (errno == ENOSYS) { errx(1, "Your kernel does not have performance monitoring support!\n"); } err(1, "cannot create session, maybe you do not have the PEBS" " sampling format in the kernel. You need perfmon_pebs_smpl." "\nCheck /sys/kernel/perfmon/formats"); } /* * map buffer into our address space */ buf_addr = mmap(NULL, (size_t)buf_arg.buf_size, PROT_READ, MAP_PRIVATE, fd, 0); if (buf_addr == MAP_FAILED) err(1, "cannot mmap sampling buffer"); printf("context [%d] buffer mapped @%p\n", fd, buf_addr); hdr = (smpl_hdr_t *)buf_addr; printf("pebs_start=%p pebs_end=%p version=%u.%u.%u entry_size=%u\n", hdr+1, hdr+1, (hdr->version >> 16) & 0xff, (hdr->version >> 8) & 0xff, hdr->version & 0xff, hdr->entry_size); printf("max PEBS entries: %zu\n", (size_t)hdr->pebs_size / hdr->entry_size); if (((hdr->version >> 16) & 0xff) < 1) errx(1, "invalid buffer format version"); /* * get which PMC registers are available */ detect_unavail_pmcs(fd, &inp.pfp_unavail_pmcs); /* * let libpfm figure out how to assign event onto PMU registers */ if (pfm_dispatch_events(&inp, mod_inp, &outp, NULL) != PFMLIB_SUCCESS) errx(1, "cannot assign event %s\n", SMPL_EVENT); /* * propagate PMC setup from libpfm to perfmon */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; /* * must disable 64-bit emulation on the PMC0 counter * PMC0 is the only counter useable with PEBS. We must disable * 64-bit emulation to avoid getting interrupts for each * sampling period, PEBS takes care of this part. */ if (pc[i].reg_num == 0) pc[i].reg_flags = PFM_REGFL_NO_EMUL64; } /* * propagate PMD set from libpfm to perfmon */ for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * setup sampling period for first counter * we want notification on overflow, i.e., when buffer is full */ for(i=0; i < maxpebs; i++) { pd[i].reg_flags = PFM_REGFL_OVFL_NOTIFY; pd[i].reg_value = -SMPL_PERIOD; pd[i].reg_long_reset = -SMPL_PERIOD; pd[i].reg_short_reset = -SMPL_PERIOD; } /* * Now program the registers */ if (pfm_write_pmcs(fd, pc, outp.pfp_pmc_count) == -1) err(1, "pfm_write_pmcs error"); if (pfm_write_pmds(fd, pd, outp.pfp_pmd_count) == -1) err(1, "pfm_write_pmds error"); signal(SIGCHLD, SIG_IGN); /* * Create the child task */ if ((pid=fork()) == -1) err(1, "cannot fork process"); /* * In order to get the PFM_END_MSG message, it is important * to ensure that the child task does not inherit the file * descriptor of the context. By default, file descriptor * are inherited during exec(). We explicitely close it * here. We could have set it up through fcntl(FD_CLOEXEC) * to achieve the same thing. */ if (pid == 0) { close(fd); child(argv+1); } /* * wait for the child to exec */ waitpid(pid, &status, WUNTRACED); /* * process is stopped at this point */ if (WIFEXITED(status)) { warnx("task %s [%d] exited already status %d\n", argv[1], pid, WEXITSTATUS(status)); goto terminate_session; } /* * attach the context to child */ load_args.load_pid = pid; if (pfm_load_context(fd, &load_args) == -1) err(1, "pfm_load_context error"); /* * start monitoring */ if (pfm_start(fd, NULL) == -1) err(1, "pfm_start error"); /* * detach child. Side effect includes * activation of monitoring. */ ptrace(PTRACE_DETACH, pid, NULL, 0); /* * core loop */ for(;;) { /* * wait for overflow/end notification messages */ ret = read(fd, &msg, sizeof(msg)); if (ret == -1) { if(ret == -1 && errno == EINTR) { warnx("read interrupted, retrying"); continue; } err(1, "cannot read perfmon msg"); } switch(msg.type) { case PFM_MSG_OVFL: /* the sampling buffer is full */ process_smpl_buf(hdr); /* * reactivate monitoring once we are done with the samples * * Note that this call can fail with EBUSY in non-blocking mode * as the task may have disappeared while we were processing * the samples. */ if (pfm_restart(fd) == -1) { if (errno != EBUSY) err(1, "pfm_restart error"); else warnx("pfm_restart: task has probably terminated \n"); } break; case PFM_MSG_END: /* monitored task terminated */ warnx("TASK terminated"); goto terminate_session; default: errx(1, "unknown message type %d", msg.type); } } terminate_session: /* * cleanup child */ wait4(pid, &status, 0, NULL); /* * check for any leftover samples */ process_smpl_buf(hdr); printf("collected samples %"PRIu64", %"PRIu64" overflows\n", collected_samples, last_overflow); /* * close context */ close(fd); /* * unmap sampling buffer and actually free the perfmon context */ munmap(buf_addr, (size_t)buf_arg.buf_size); return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/x86/smpl_core_pebs.c0000644000307100002310000002600713013651447023415 0ustar yarkhangraduate/* * smpl_core_pebs.c - Intel Core processor PEBS example * * Copyright (c) 2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "../detect_pmcs.h" #define SMPL_EVENT "INST_RETIRED:ANY_P" /* not all events support PEBS */ #define NUM_PMCS 16 #define NUM_PMDS 16 #define SMPL_PERIOD 100000ULL /* must not use more bits than actual HW counter width */ typedef pfm_pebs_core_smpl_hdr_t smpl_hdr_t; typedef pfm_pebs_core_smpl_entry_t smpl_entry_t; typedef pfm_pebs_core_smpl_arg_t smpl_arg_t; #define FMT_NAME PFM_PEBS_CORE_SMPL_NAME static uint64_t collected_samples; static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } static void warning(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); } int child(char **arg) { /* * force the task to stop before executing the first * user level instruction */ ptrace(PTRACE_TRACEME, 0, NULL, NULL); execvp(arg[0], arg); /* not reached */ exit(1); } static void process_smpl_buf(smpl_hdr_t *hdr) { static uint64_t last_overflow = ~0; /* initialize to biggest value possible */ static uint64_t last_count; smpl_entry_t *ent; uint64_t entry; unsigned long count; count = (hdr->ds.pebs_index - hdr->ds.pebs_buf_base)/sizeof(*ent); if (hdr->overflows == last_overflow && last_count == count) { warning("skipping identical set of samples %"PRIu64" = %"PRIu64"\n", hdr->overflows, last_overflow); return; } last_count = count; last_overflow = hdr->overflows; /* * the beginning of the buffer does not necessarily follow the header * due to alignement. */ ent = (smpl_entry_t *)((unsigned long)(hdr+1)+ hdr->start_offs); entry = collected_samples; while(count--) { /* * print some of the machine registers of each sample */ printf("entry %06"PRIu64" eflags:0x%08llx EAX:0x%08llx ESP:0x%08llx IP:0x%08llx\n", entry, (unsigned long long)ent->eflags, (unsigned long long)ent->eax, (unsigned long long)ent->esp, (unsigned long long)ent->ip); ent++; entry++; } collected_samples = entry; } int main(int argc, char **argv) { pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_core_input_param_t mod_inp; pfmlib_options_t pfmlib_options; pfarg_pmd_t pd[NUM_PMDS]; pfarg_pmc_t pc[NUM_PMCS]; pfarg_ctx_t ctx; smpl_arg_t buf_arg; pfarg_load_t load_args; pfarg_msg_t msg; smpl_hdr_t *hdr; void *buf_addr; pid_t pid; int ret, fd, status, type; unsigned int i; if (argc < 2) fatal_error("you need to pass a program to sample\n"); if (pfm_initialize() != PFMLIB_SUCCESS) fatal_error("libpfm intialization failed\n"); /* * check we are on an Intel Core PMU */ pfm_get_pmu_type(&type); if (type != PFMLIB_INTEL_CORE_PMU && type != PFMLIB_INTEL_ATOM_PMU) fatal_error("This program only works with an Intel Core processor\n"); /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 1; /* set to 1 for verbose */ pfm_set_options(&pfmlib_options); memset(pd, 0, sizeof(pd)); memset(pc, 0, sizeof(pc)); memset(&inp, 0, sizeof(inp)); memset(&outp, 0, sizeof(outp)); memset(&mod_inp, 0, sizeof(mod_inp)); memset(&ctx, 0, sizeof(ctx)); memset(&buf_arg, 0, sizeof(buf_arg)); memset(&load_args, 0, sizeof(load_args)); /* * search for our sampling event */ if (pfm_find_full_event(SMPL_EVENT, &inp.pfp_events[0]) != PFMLIB_SUCCESS) fatal_error("cannot find sampling event %s\n", SMPL_EVENT); inp.pfp_event_count = 1; inp.pfp_dfl_plm = PFM_PLM3|PFM_PLM0; /* * important: inform libpfm we do use PEBS */ mod_inp.pfp_core_pebs.pebs_used = 1; /* * sampling buffer parameters */ buf_arg.buf_size = 4*getpagesize(); /* * sampling period cannot use more bits than HW counter can supoprt */ buf_arg.cnt_reset = -SMPL_PERIOD; /* * trigger notification (interrupt) when reached 90% of buffer */ buf_arg.intr_thres = (buf_arg.buf_size/sizeof(smpl_entry_t))*90/100; /* * create context and sampling buffer */ fd = pfm_create_context(&ctx, FMT_NAME, &buf_arg, sizeof(buf_arg)); if (fd == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("cannot create PFM context %s, maybe you do not have the PEBS sampling format in the kernel.\nCheck /sys/kernel/perfmon/formats\n", strerror(errno)); } /* * map buffer into our address space */ buf_addr = mmap(NULL, (size_t)buf_arg.buf_size, PROT_READ, MAP_PRIVATE, fd, 0); printf("context [%d] buffer mapped @%p\n", fd, buf_addr); if (buf_addr == MAP_FAILED) fatal_error("cannot mmap sampling buffer errno %d\n", errno); hdr = (smpl_hdr_t *)buf_addr; printf("pebs_base=0x%llx pebs_end=0x%llx index=0x%llx\n" "intr=0x%llx version=%u.%u\n" "entry_size=%zu ds_size=%zu\n", (unsigned long long)hdr->ds.pebs_buf_base, (unsigned long long)hdr->ds.pebs_abs_max, (unsigned long long)hdr->ds.pebs_index, (unsigned long long)hdr->ds.pebs_intr_thres, PFM_VERSION_MAJOR(hdr->version), PFM_VERSION_MINOR(hdr->version), sizeof(smpl_entry_t), sizeof(hdr->ds)); if (PFM_VERSION_MAJOR(hdr->version) < 1) fatal_error("invalid buffer format version\n"); /* * get which PMC registers are available */ detect_unavail_pmcs(fd, &inp.pfp_unavail_pmcs); /* * let libpfm figure out how to assign event onto PMU registers */ if (pfm_dispatch_events(&inp, &mod_inp, &outp, NULL) != PFMLIB_SUCCESS) fatal_error("cannot assign event %s\n", SMPL_EVENT); /* * propagate PMC setup from libpfm to perfmon */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; /* * must disable 64-bit emulation on the PMC0 counter * PMC0 is the only counter useable with PEBS. We must disable * 64-bit emulation to avoid getting interrupts for each * sampling period, PEBS takes care of this part. * * This is obsolete with 2.6.30 */ if (pc[i].reg_num == 0) pc[i].reg_flags = PFM_REGFL_NO_EMUL64; } /* * propagate PMD set from libpfm to perfmon */ for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * setup sampling period for first counter * we want notification on overflow, i.e., when buffer is full */ pd[0].reg_flags = PFM_REGFL_OVFL_NOTIFY; pd[0].reg_value = -SMPL_PERIOD; pd[0].reg_long_reset = -SMPL_PERIOD; pd[0].reg_short_reset = -SMPL_PERIOD; /* * Now program the registers */ if (pfm_write_pmcs(fd, pc, outp.pfp_pmc_count) == -1) fatal_error("pfm_write_pmcs error errno %d\n",errno); if (pfm_write_pmds(fd, pd, outp.pfp_pmd_count) == -1) fatal_error("pfm_write_pmds error errno %d\n",errno); signal(SIGCHLD, SIG_IGN); /* * Create the child task */ if ((pid=fork()) == -1) fatal_error("Cannot fork process\n"); /* * In order to get the PFM_END_MSG message, it is important * to ensure that the child task does not inherit the file * descriptor of the context. By default, file descriptor * are inherited during exec(). We explicitely close it * here. We could have set it up through fcntl(FD_CLOEXEC) * to achieve the same thing. */ if (pid == 0) { close(fd); child(argv+1); } /* * wait for the child to exec */ waitpid(pid, &status, WUNTRACED); /* * process is stopped at this point */ if (WIFEXITED(status)) { warning("task %s [%d] exited already status %d\n", argv[1], pid, WEXITSTATUS(status)); goto terminate_session; } /* * attach the context to child */ load_args.load_pid = pid; if (pfm_load_context(fd, &load_args) == -1) fatal_error("pfm_load_context error errno %d\n",errno); /* * start monitoring */ if (pfm_start(fd, NULL) == -1) fatal_error("pfm_start error errno %d\n",errno); /* * detach child. Side effect includes * activation of monitoring. */ ptrace(PTRACE_DETACH, pid, NULL, 0); /* * core loop */ for(;;) { /* * wait for overflow/end notification messages */ ret = read(fd, &msg, sizeof(msg)); if (ret == -1) { if(ret == -1 && errno == EINTR) { warning("read interrupted, retrying\n"); continue; } fatal_error("cannot read perfmon msg: %s\n", strerror(errno)); } switch(msg.type) { case PFM_MSG_OVFL: /* the sampling buffer is full */ process_smpl_buf(hdr); /* * reactivate monitoring once we are done with the samples * * Note that this call can fail with EBUSY in non-blocking mode * as the task may have disappeared while we were processing * the samples. */ if (pfm_restart(fd) == -1) { if (errno != EBUSY) fatal_error("pfm_restart error errno %d\n",errno); else warning("pfm_restart: task has probably terminated \n"); } break; case PFM_MSG_END: /* monitored task terminated */ warning("task terminated\n"); goto terminate_session; default: fatal_error("unknown message type %d\n", msg.type); } } terminate_session: /* * cleanup child */ wait4(pid, &status, 0, NULL); /* * check for any leftover samples */ process_smpl_buf(hdr); printf("collected samples %"PRIu64"n", collected_samples); /* * close context */ close(fd); /* * unmap sampling buffer and actually free the perfmon context */ munmap(buf_addr, (size_t)buf_arg.buf_size); return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/x86/Makefile0000644000307100002310000000354313013651447021715 0ustar yarkhangraduate# # Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. # Contributed by Stephane Eranian # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies # of the Software, and to permit persons to whom the Software is furnished to do so, # subject to the following conditions: # # The above copyright notice and this permission notice shall be included in all # copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, # INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A # PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT # HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE # OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # TOPDIR := $(shell if [ "$$PWD" != "" ]; then echo $$PWD; else pwd; fi)/../.. include $(TOPDIR)/config.mk include $(TOPDIR)/rules.mk LIBS += -lm ifeq ($(SYS),Linux) TARGETS=smpl_p4_pebs smpl_core_pebs smpl_amd64_ibs smpl_nhm_lbr smpl_pebs endif all: $(TARGETS) $(TARGETS): %:%.o $(PFMLIB) ../detect_pmcs.o $(CC) -o $@ $(CFLAGS) $(LDFLAGS) $^ $(LIBS) clean: $(RM) -f *.o $(TARGETS) *~ distclean: clean install_examples: $(TARGETS) install_examples: @echo installing: $(TARGETS) -mkdir -p $(DESTDIR)$(EXAMPLESDIR)/v2/x86 $(INSTALL) -m 755 $(TARGETS) $(DESTDIR)$(EXAMPLESDIR)/v2/x86 # # examples are installed as part of the RPM install, typically in /usr/share/doc/libpfm-X.Y/ # papi-5.5.1/src/libpfm-3.y/examples_v2.x/x86/smpl_amd64_ibs.c0000644000307100002310000004521213013651447023223 0ustar yarkhangraduate/* * smpl_amd64_ibs.c - AMD64 Family 10h IBS sampling * * Copyright (c) 2007 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Copyright (c) 2008 Advanced Mirco Devices Inc. * Contributed by Robert Richter * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include typedef struct { int opt_no_show; int opt_block; int opt_setup; } options_t; enum { OPT_IBSOP, /* 0: default */ OPT_IBSFETCH, OPT_IBSOP_NATIVE, }; typedef pfm_dfl_smpl_arg_t smpl_fmt_arg_t; typedef pfm_dfl_smpl_hdr_t smpl_hdr_t; typedef pfm_dfl_smpl_entry_t smpl_entry_t; typedef pfm_dfl_smpl_arg_t smpl_arg_t; #define FMT_NAME PFM_DFL_SMPL_NAME #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define PMD_IBSOP_NUM 7 #define PMD_IBSFETCH_NUM 3 static uint64_t collected_samples, collected_partial; static options_t options; static struct option the_options[]={ { "help", 0, 0, 1}, { "ovfl-block", 0, &options.opt_block, 1}, { "no-show", 0, &options.opt_no_show, 1}, { "ibsop", 0, &options.opt_setup, OPT_IBSOP}, { "ibsfetch", 0, &options.opt_setup, OPT_IBSFETCH}, { "ibsop-native", 0, &options.opt_setup, OPT_IBSOP_NATIVE}, { 0, 0, 0, 0} }; static void fatal_error(char *fmt,...) __attribute__((noreturn)); #define BPL (sizeof(uint64_t)<<3) #define LBPL 6 static inline void pfm_bv_set(uint64_t *bv, uint16_t rnum) { bv[rnum>>LBPL] |= 1UL << (rnum&(BPL-1)); } static inline int pfm_bv_isset(uint64_t *bv, uint16_t rnum) { return bv[rnum>>LBPL] & (1UL <<(rnum&(BPL-1))) ? 1 : 0; } static inline void pfm_bv_copy(uint64_t *d, uint64_t *j, uint16_t n) { if (n <= BPL) *d = *j; else { memcpy(d, j, (n>>LBPL)*sizeof(uint64_t)); } } static void warning(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); } static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } int child(char **arg) { /* * force the task to stop before executing the first * user level instruction */ ptrace(PTRACE_TRACEME, 0, NULL, NULL); execvp(arg[0], arg); /* not reached */ exit(1); } static void process_smpl_buf(smpl_hdr_t *hdr, uint64_t *smpl_pmds, unsigned int num_smpl_pmds, size_t entry_size) { static uint64_t last_overflow = ~0; /* initialize to biggest value possible */ static uint64_t last_count; smpl_entry_t *ent; size_t pos, count; ibsopdata_t *opdata; ibsopdata2_t *opdata2; ibsopdata3_t *opdata3; uint64_t entry, *reg; unsigned int j, n; if (hdr->hdr_overflows == last_overflow && hdr->hdr_count == last_count) { warning("skipping identical set of samples %"PRIu64" = %"PRIu64"\n", hdr->hdr_overflows, last_overflow); return; } count = hdr->hdr_count; if (options.opt_no_show) { collected_samples += count; return; } ent = (smpl_entry_t *)(hdr+1); pos = (unsigned long)ent; entry = collected_samples; while(count--) { printf("entry %"PRIu64" PID:%d TID:%d CPU:%d LAST_VAL:%"PRIu64" IIP:0x%llx\n", entry, ent->tgid, ent->pid, ent->cpu, -ent->last_reset_val, (unsigned long long)ent->ip); /* * print body: additional PMDs recorded * PMD are recorded in increasing index order */ reg = (uint64_t *)(ent+1); n = num_smpl_pmds; for(j=0; n; j++) { if (pfm_bv_isset(smpl_pmds, j)) { switch(j) { case 7: printf("PMD%-3d:0x%016"PRIx64"\n", j, *reg); /* check valid "record" bit */ if ((*reg & (1ull<<18)) == 0) { printf("no data captured\n"); goto skip; } break; case 9: /*IBSOPSDATA */ opdata = (ibsopdata_t *)reg; printf("PMD%-3d:0x%016"PRIx64" : comptoret=%u tagtoretctr=%u opbrnresync=%u opmispret=%u opret=%u brntk=%u brnmips=%u bnrret=%u\n", j, *reg, opdata->reg.ibscomptoretctr, opdata->reg.ibstagtoretctr, opdata->reg.ibsopbrnresync, opdata->reg.ibsopmispreturn, opdata->reg.ibsopreturn, opdata->reg.ibsopbrntaken, opdata->reg.ibsopbrnmisp, opdata->reg.ibsopbrnret); break; case 10: opdata2 = (ibsopdata2_t *)reg; printf("PMD%-3d:0x%016"PRIx64" : reqsrc=%u reqdstproc=%s reqcachehitst=%u\n", j, *reg, opdata2->reg.nbibsreqsrc, opdata2->reg.nbibsreqdstproc ? "local" : "remote", opdata2->reg.nbibsreqcachehitst); break; case 11: opdata3 = (ibsopdata3_t *)reg; printf("PMD%-3d:0x%016"PRIx64" : ld=%u st=%u L1TLBmiss=%u L2TLBmiss=%u L1TLBhit2M=%u L1TLBhit1G=%u L2TLBhit2M=%u miss=%u misalign=%u ld_bankconf=%u st_bankconf=%u st_to_ld_conf=%u st_to_ld_canc=%u UCaccess=%u WCaccess=%u lock=%u MAB=%u linevalid=%u physvalid=%u miss_lat=%u\n", j, *reg, opdata3->reg.ibsldop, opdata3->reg.ibsstop, opdata3->reg.ibsdcl1tlbmiss, opdata3->reg.ibsdcl2tlbmiss, opdata3->reg.ibsdcl1tlbhit2m, opdata3->reg.ibsdcl1tlbhit1g, opdata3->reg.ibsdcl2tlbhit2m, opdata3->reg.ibsdcmiss, opdata3->reg.ibsdcmissacc, opdata3->reg.ibsdcldbnkcon, opdata3->reg.ibsdcstbnkcon, opdata3->reg.ibsdcsttoldfwd, opdata3->reg.ibsdcsttoldcan, opdata3->reg.ibsdcucmemacc, opdata3->reg.ibsdcwcmemacc, opdata3->reg.ibsdclockedop, opdata3->reg.ibsdcmabhit, opdata3->reg.ibsdclinaddrvalid, opdata3->reg.ibsdcphyaddrvalid, opdata3->reg.ibsdcmisslat); break; default: printf("PMD%-3d:0x%016"PRIx64"\n", j, *reg); } reg++; n--; } } skip: pos += entry_size; ent = (smpl_entry_t *)pos; entry++; } collected_samples = entry; last_overflow = hdr->hdr_overflows; if (last_count != hdr->hdr_count && (last_count || last_overflow == 0)) collected_partial += hdr->hdr_count; last_count = hdr->hdr_count; } static int setup_pmu_ibsop_native(pfarg_pmc_t *pc, pfarg_pmd_t *pd) { uint64_t ibs_ops_smpl; /* * OBSCTL sampling period (20 bits) * bits 3:0 must be zero */ ibs_ops_smpl = 0xffff0; /* * IBSOPSCTL config * * bit 17: enable * bits 0-15: bit 19-4 of sampling period */ pc[0].reg_num = 5; pc[0].reg_value = (1ULL <<17) | ((ibs_ops_smpl >> 4) & 0xffffULL); /* IBSOPSCTL data * * point to the same MSR register. It correspond to the associated * data register, i.e., the register to which the IBS interrupt will * be associated. * * Randomization on IBS control register (IBSOPSCTL, IBSFETCHCTL) is * ignored. * * The value, short_reset, long_reset values are ignored. Use the * corresponding PMC registers to set sampling period. * * If the last_reset-value is important for your program, then you can * get it frmo the controlling PMC (4, 5). Alternatively, you can set * the reg_value field to the value of the corresponding PMC register. */ pd[0].reg_num = 7; pd[0].reg_flags = PFM_REGFL_OVFL_NOTIFY; pd[0].reg_value = pc[0].reg_value; pd[0].reg_long_reset = pc[0].reg_value; pd[0].reg_short_reset = pc[0].reg_value; pfm_bv_set(pd[0].reg_smpl_pmds, 7); pfm_bv_set(pd[0].reg_smpl_pmds, 8); pfm_bv_set(pd[0].reg_smpl_pmds, 9); pfm_bv_set(pd[0].reg_smpl_pmds, 10); pfm_bv_set(pd[0].reg_smpl_pmds, 11); pfm_bv_set(pd[0].reg_smpl_pmds, 12); pfm_bv_set(pd[0].reg_smpl_pmds, 13); return PFMLIB_SUCCESS; } static int setup_pmu_ibsop(pfarg_pmc_t *pc, pfarg_pmd_t *pd) { pfmlib_amd64_input_param_t inp_mod; pfmlib_output_param_t outp; pfmlib_amd64_output_param_t outp_mod; int ret; memset(&inp_mod,0, sizeof(inp_mod)); memset(&outp,0, sizeof(outp)); memset(&outp_mod,0, sizeof(outp_mod)); /* setup ibsopctl register */ inp_mod.ibsop.maxcnt = 0xFFFF0; inp_mod.flags |= PFMLIB_AMD64_USE_IBSOP; /* setup Perfmon2 registers */ ret = pfm_dispatch_events(NULL, &inp_mod, &outp, &outp_mod); if (ret != PFMLIB_SUCCESS) { fprintf(stderr, "cannot dispatch events: %s\n", pfm_strerror(ret)); return ret; } if (outp.pfp_pmc_count != 1) { fprintf(stderr, "Unexpected PMC register count: %d\n", outp.pfp_pmc_count); return PFMLIB_ERR_INVAL; } if (outp.pfp_pmd_count != 1) { fprintf(stderr, "Unexpected PMD register count: %d\n", outp.pfp_pmd_count); return PFMLIB_ERR_INVAL; } if (outp_mod.ibsop_base != 0) { fprintf(stderr, "Unexpected IBSOP base register: %d\n", outp_mod.ibsop_base); return PFMLIB_ERR_INVAL; } /* PMC_IBSOPCTL */ pc[0].reg_num = outp.pfp_pmcs[0].reg_num; pc[0].reg_value = outp.pfp_pmcs[0].reg_value; /* PMD_IBSOPCTL */ pd[0].reg_num = outp.pfp_pmds[0].reg_num; pd[0].reg_value = 0; /* setup all IBSOP registers for sampling */ pd[0].reg_flags = PFM_REGFL_OVFL_NOTIFY; if (pd[0].reg_num > 64 - PMD_IBSOP_NUM) { fprintf(stderr, "Unexpected IBSOP base: %d\n", (int)pd[0].reg_num); return PFMLIB_ERR_INVAL; } pd[0].reg_smpl_pmds[0] = ((1UL << PMD_IBSOP_NUM) - 1) << outp.pfp_pmds[0].reg_num; return PFMLIB_SUCCESS; } static int setup_pmu_ibsfetch(pfarg_pmc_t *pc, pfarg_pmd_t *pd) { pfmlib_amd64_input_param_t inp_mod; pfmlib_output_param_t outp; pfmlib_amd64_output_param_t outp_mod; int ret; memset(&inp_mod,0, sizeof(inp_mod)); memset(&outp,0, sizeof(outp)); memset(&outp_mod,0, sizeof(outp_mod)); /* setup ibsfetchctl register */ inp_mod.ibsfetch.maxcnt = 0xFFFF0; inp_mod.flags |= PFMLIB_AMD64_USE_IBSFETCH; /* setup Perfmon2 registers */ ret = pfm_dispatch_events(NULL, &inp_mod, &outp, &outp_mod); if (ret != PFMLIB_SUCCESS) { fprintf(stderr, "cannot dispatch events: %s\n", pfm_strerror(ret)); return ret; } if (outp.pfp_pmc_count != 1) { fprintf(stderr, "Unexpected PMC register count: %d\n", outp.pfp_pmc_count); return PFMLIB_ERR_INVAL; } if (outp.pfp_pmd_count != 1) { fprintf(stderr, "Unexpected PMD register count: %d\n", outp.pfp_pmd_count); return PFMLIB_ERR_INVAL; } if (outp_mod.ibsfetch_base != 0) { fprintf(stderr, "Unexpected IBSFETCH base register: %d\n", outp_mod.ibsfetch_base); return PFMLIB_ERR_INVAL; } /* PMC_IBSFETCHCTL */ pc[0].reg_num = outp.pfp_pmcs[0].reg_num; pc[0].reg_value = outp.pfp_pmcs[0].reg_value; /* PMD_IBSFETCHCTL */ pd[0].reg_num = outp.pfp_pmds[0].reg_num; pd[0].reg_value = 0; /* setup all IBSFETCH registers for sampling */ pd[0].reg_flags = PFM_REGFL_OVFL_NOTIFY; if (pd[0].reg_num > 64 - PMD_IBSFETCH_NUM) { fprintf(stderr, "Unexpected IBSFETCH base: %d\n", (int)pd[0].reg_num); return PFMLIB_ERR_INVAL; } pd[0].reg_smpl_pmds[0] = ((1UL << PMD_IBSFETCH_NUM) - 1) << outp.pfp_pmds[0].reg_num; return PFMLIB_SUCCESS; } int mainloop(char **arg) { pfarg_pmc_t pc[1]; pfarg_pmd_t pd[1]; smpl_hdr_t *hdr; pfarg_ctx_t ctx; smpl_arg_t buf_arg; pfarg_load_t load_arg; struct timeval start_time, end_time; pfarg_msg_t msg; uint64_t ovfl_count = 0; size_t entry_size; void *buf_addr; pid_t pid; int status, ret, fd; int pmc_count, pmd_count; unsigned int num_smpl_pmds = 0; memset(&ctx,0, sizeof(ctx)); memset(pd, 0, sizeof(pd)); memset(pc, 0, sizeof(pc)); memset(&load_arg, 0, sizeof(load_arg)); /* defaults */ num_smpl_pmds = 7; pmc_count = pmd_count = 1; switch (options.opt_setup) { case OPT_IBSOP: ret = setup_pmu_ibsop(pc, pd); break; case OPT_IBSOP_NATIVE: ret = setup_pmu_ibsop_native(pc, pd); break; case OPT_IBSFETCH: num_smpl_pmds = 3; ret = setup_pmu_ibsfetch(pc, pd); break; default: ret = PFMLIB_ERR_NOTSUPP; break; } if (ret != PFMLIB_SUCCESS) { fatal_error("Can't setup #%d\n", options.opt_setup); exit(1); } /* * in this example program, we use fixed-size entries, therefore we * can compute the entry size in advance. Perfmon-2 supports variable * size entries. */ entry_size = sizeof(smpl_entry_t)+(num_smpl_pmds<<3); /* * prepare context structure. */ /* * We initialize the format specific information. * The format is identified by its UUID which must be copied * into the ctx_buf_fmt_id field. */ ctx.ctx_flags = options.opt_block ? PFM_FL_NOTIFY_BLOCK : 0; /* * the size of the buffer is indicated in bytes (not entries). * * The kernel will record into the buffer up to a certain point. * No partial samples are ever recorded. */ buf_arg.buf_size = 3*getpagesize(); /* * now create our perfmon context. */ fd = pfm_create_context(&ctx, FMT_NAME, &buf_arg, sizeof(buf_arg)); if (fd == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * retrieve the virtual address at which the sampling * buffer has been mapped */ buf_addr = mmap(NULL, (size_t)buf_arg.buf_size, PROT_READ, MAP_PRIVATE, fd, 0); if (buf_addr == MAP_FAILED) fatal_error("cannot mmap sampling buffer: %s\n", strerror(errno)); printf("buffer mapped @%p\n", buf_addr); hdr = (smpl_hdr_t *)buf_addr; printf("hdr_cur_offs=%llu version=%u.%u\n", (unsigned long long)hdr->hdr_cur_offs, PFM_VERSION_MAJOR(hdr->hdr_version), PFM_VERSION_MINOR(hdr->hdr_version)); if (PFM_VERSION_MAJOR(hdr->hdr_version) < 1) fatal_error("invalid buffer format version\n"); /* * Now program the registers */ if (pfm_write_pmcs(fd, pc, pmc_count)) fatal_error("pfm_write_pmcs error errno %d\n",errno); /* * initialize the PMDs * To be read, each PMD must be either written or declared * as being part of a sample (reg_smpl_pmds, reg_reset_pmds) */ if (pfm_write_pmds(fd, pd, pmd_count)) fatal_error("pfm_write_pmds error errno %d\n",errno); /* * Create the child task */ if ((pid=fork()) == -1) fatal_error("Cannot fork process\n"); /* * In order to get the PFM_END_MSG message, it is important * to ensure that the child task does not inherit the file * descriptor of the context. By default, file descriptor * are inherited during exec(). We explicitely close it * here. We could have set it up through fcntl(FD_CLOEXEC) * to achieve the same thing. */ if (pid == 0) { close(fd); child(arg); } /* * wait for the child to exec */ waitpid(pid, &status, WUNTRACED); /* * process is stopped at this point */ if (WIFEXITED(status)) { warning("task %s [%d] exited already status %d\n", arg[0], pid, WEXITSTATUS(status)); goto terminate_session; } /* * attach context to stopped task */ load_arg.load_pid = pid; if (pfm_load_context (fd, &load_arg)) fatal_error("pfm_load_context error errno %d\n",errno); /* * activate monitoring for stopped task. * (nothing will be measured at this point */ if (pfm_start(fd, NULL)) fatal_error("pfm_start error errno %d\n",errno); /* * detach child. Side effect includes * activation of monitoring. */ ptrace(PTRACE_DETACH, pid, NULL, 0); gettimeofday(&start_time, NULL); /* * core loop */ for(;;) { /* * wait for overflow/end notification messages */ ret = read(fd, &msg, sizeof(msg)); if (ret == -1) { if(ret == -1 && errno == EINTR) { warning("read interrupted, retrying\n"); continue; } fatal_error("cannot read perfmon msg: %s\n", strerror(errno)); } switch(msg.type) { case PFM_MSG_OVFL: /* the sampling buffer is full */ process_smpl_buf(hdr, pd[0].reg_smpl_pmds, num_smpl_pmds, entry_size); ovfl_count++; /* * reactivate monitoring once we are done with the samples * * Note that this call can fail with EBUSY in non-blocking mode * as the task may have disappeared while we were processing * the samples. */ if (pfm_restart(fd)) { if (errno != EBUSY) fatal_error("pfm_restart error errno %d\n",errno); else warning("pfm_restart: task probably terminated \n"); } break; case PFM_MSG_END: /* monitored task terminated */ printf("task terminated\n"); goto terminate_session; default: fatal_error("unknown message type %d\n", msg.type); } } terminate_session: /* * cleanup child */ wait4(pid, &status, 0, NULL); gettimeofday(&end_time, NULL); /* * check for any leftover samples */ process_smpl_buf(hdr, pd[0].reg_smpl_pmds, num_smpl_pmds, entry_size); close(fd); /* * unmap buffer, actually free the buffer and context because placed after * the close(), i.e. is the last reference. See comments about close() above. */ ret = munmap(hdr, (size_t)buf_arg.buf_size); if (ret) fatal_error("cannot unmap buffer: %s\n", strerror(errno)); printf("%"PRIu64" samples (%"PRIu64" in partial buffer) collected in %"PRIu64" buffer overflows\n", collected_samples, collected_partial, ovfl_count); return 0; } static void usage(void) { printf("usage: task_smpl [-h] [--help] [--no-show] [--ovfl-block] " "[--ibsop] [--ibsfetch] [--ibsop-native] cmd\n"); } int main(int argc, char **argv) { pfmlib_options_t pfmlib_options; int c, ret; while ((c=getopt_long(argc, argv,"h", the_options, 0)) != -1) { switch(c) { case 0: continue; case 1: case 'h': usage(); exit(0); default: fatal_error(""); } } if (argv[optind] == NULL) { fatal_error("You must specify a command to execute\n"); } /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 1; /* set to 1 for verbose */ pfm_set_options(&pfmlib_options); /* * Initialize pfm library */ ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) fatal_error("Cannot initialize library: %s\n", pfm_strerror(ret)); pfm_get_pmu_type(&c); if (c != PFMLIB_AMD64_PMU) { fatal_error("not running on an AMD64 processor\n"); } /* * XXX: would need to check for family 10h */ return mainloop(argv+optind); } papi-5.5.1/src/libpfm-3.y/examples_v2.x/set_notify.c0000644000307100002310000002722213013651447022157 0ustar yarkhangraduate/* * set_notify.c - example of how to get notification at the end of a set chain * * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #include #include #include #include #include #include #include #include #include #include #include #include #include "detect_pmcs.h" #define NUM_SETS 3 #define THE_TIMEOUT 1 static volatile unsigned long notification_received; #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS static int ctx_fd; static char *event1_name; static pfarg_setinfo_t setinfo[NUM_SETS]; static pfarg_pmd_t pd[2]; static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } static void warning(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); } static void sigio_handler(int n, struct siginfo *info, void *data) { pfarg_msg_t msg; unsigned int k; int r; retry: r = read(ctx_fd, &msg, sizeof(msg)); if (r != sizeof(msg)) { if(r == -1 && errno == EINTR) { warning("read interrupted, retrying\n"); goto retry; } fatal_error("cannot read overflow message: %s\n", strerror(errno)); } if (msg.type != PFM_MSG_OVFL) { fatal_error("unexpected msg type: %d\n",msg.type); } if (pfm_getinfo_evtsets(ctx_fd, setinfo, NUM_SETS) == -1) { fatal_error("pfm_getinfo_evtsets: %s", strerror(errno)); } if (pfm_read_pmds(ctx_fd, pd, 2) == -1) { fatal_error("pfm_read_pmds: %s", strerror(errno)); } /* * XXX: risky to do printf() in signal handler! */ printf("Notification %lu: set%u pd[0]=%"PRIx64" pd[1]=%"PRIx64"\n", notification_received, pd[0].reg_set, pd[0].reg_value, pd[1].reg_value); for(k=0; k < NUM_SETS; k++) printf("set%u %"PRIu64" runs\n", setinfo[k].set_id, setinfo[k].set_runs); /* * At this point, the counter used for the sampling period has already * be reset by the kernel because we are in non-blocking mode, self-monitoring. */ /* * increment our notification counter */ notification_received++; /* * And resume monitoring */ if (pfm_restart(ctx_fd) == -1) { fatal_error("pfm_restart: %s", strerror(errno)); } } /* * infinite loop waiting for notification to get out */ void busyloop(void) { /* * busy loop to burn CPU cycles */ for(;notification_received < 3;) ; } #ifdef __ia64__ #define FUDGE 1 #else #define FUDGE 0x100 #endif /* * build end marker set */ void setup_end_marker(int fd, unsigned int set_id, uint64_t num_ovfls, int plm_mask) { pfarg_setdesc_t setdesc; pfarg_pmc_t pc[8]; pfmlib_input_param_t inp; pfmlib_output_param_t outp; unsigned int i; int ret; memset(&setdesc, 0, sizeof(setdesc)); memset(pc, 0, sizeof(pc)); memset(pd, 0, sizeof(pd)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); /* * we use the cycle event twice: * - first as sampling period to force switch to set 0 * - second as sampling period to force notification */ if (pfm_get_cycle_event(&inp.pfp_events[0]) != PFMLIB_SUCCESS) fatal_error("cannot find cycle event\n"); inp.pfp_events[1] = inp.pfp_events[0]; inp.pfp_dfl_plm = plm_mask; inp.pfp_event_count = 2; /* * build the pfp_unavail_pmcs bitmask by looking * at what perfmon has available. It is not always * the case that all PMU registers are actually available * to applications. For instance, on IA-32 platforms, some * registers may be reserved for the NMI watchdog timer. * * With this bitmap, the library knows which registers NOT to * use. Of source, it is possible that no valid assignement may * be possible if certina PMU registers are not available. */ detect_unavail_pmcs(fd, &inp.pfp_unavail_pmcs); if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) fatal_error("Cannot configure events: %s\n", pfm_strerror(ret)); for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; pc[i].reg_set = set_id; } for (i=0; i < outp.pfp_pmd_count; i++) { pd[i].reg_num = outp.pfp_pmds[i].reg_num; pd[i].reg_set = set_id; } /* * first cycle overflow: no notification, simply trigger a switch */ pd[0].reg_flags = 0; pd[0].reg_value = -1; pd[0].reg_long_reset = -1; pd[0].reg_short_reset = -1; pd[0].reg_ovfl_switch_cnt = 1; /* * second cycle overflow: generate notification, switch on restart */ pd[1].reg_flags = PFM_REGFL_OVFL_NOTIFY; pd[1].reg_value = -num_ovfls*FUDGE; pd[1].reg_long_reset = -num_ovfls*FUDGE; pd[1].reg_short_reset = -num_ovfls*FUDGE; pd[1].reg_ovfl_switch_cnt = 1; /* * set uses overflow switch */ setdesc.set_id = set_id; setdesc.set_flags = PFM_SETFL_OVFL_SWITCH; setdesc.set_timeout = 0; if (pfm_create_evtsets(fd, &setdesc, 1) == -1) fatal_error("pfm_create_evtsets error errno %d\n",errno); if (pfm_write_pmcs(fd, pc, outp.pfp_pmc_count) == -1) fatal_error("pfm_write_pmcs error errno %d\n",errno); /* * To be read, each PMD must be either written or declared * as being part of a sample (reg_smpl_pmds) */ if (pfm_write_pmds(fd, pd, outp.pfp_pmd_count) == -1) fatal_error("pfm_write_pmds error errno %d\n",errno); } int main(int argc, char **argv) { pfarg_ctx_t ctx[1]; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfarg_pmc_t pc[NUM_PMCS]; pfarg_pmd_t pd[NUM_PMDS]; pfarg_load_t load_args; pfarg_setdesc_t setdesc; pfmlib_options_t pfmlib_options; struct sigaction act; uint64_t num_ovfls; unsigned int i, k; size_t len; int ret; /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 1; /* set to 1 for verbose */ pfm_set_options(&pfmlib_options); /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) fatal_error("Cannot initialize library: %s\n", pfm_strerror(ret)); num_ovfls = argc > 1 ? strtoull(argv[1], NULL, 10) : 3; printf("chain contains %d sets, time switching every %u seconds\n" "notification every %"PRIu64" times the end of the chain is reached\n", NUM_SETS, THE_TIMEOUT, num_ovfls); /* * Install the signal handler (SIGIO) * * SA_SIGINFO required on some platforms * to get siginfo passed to handler. */ memset(&act, 0, sizeof(act)); act.sa_handler = (sig_t)sigio_handler; act.sa_flags = SA_SIGINFO; sigaction (SIGIO, &act, 0); memset(pc, 0, sizeof(pc)); memset(ctx, 0, sizeof(ctx)); memset(&load_args, 0, sizeof(load_args)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&setdesc,0, sizeof(setdesc)); if (pfm_get_cycle_event(&inp.pfp_events[0]) != PFMLIB_SUCCESS) fatal_error("cannot find cycle event\n"); pfm_get_max_event_name_len(&len); event1_name = malloc(len+1); if (event1_name == NULL) { fatal_error("cannot allocate event name\n"); } pfm_get_full_event_name(&inp.pfp_events[1], event1_name, len+1); /* * set the default privilege mode for all counters: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = 1; /* * now create the context for self monitoring/per-task */ ctx_fd = pfm_create_context(ctx, NULL, NULL, 0); if (ctx_fd == -1) { if (errno == ENOSYS) fatal_error("Your kernel does not have performance monitoring support!\n"); fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * build the pfp_unavail_pmcs bitmask by looking * at what perfmon has available. It is not always * the case that all PMU registers are actually available * to applications. For instance, on IA-32 platforms, some * registers may be reserved for the NMI watchdog timer. * * With this bitmap, the library knows which registers NOT to * use. Of source, it is possible that no valid assignement may * be possible if certina PMU registers are not available. */ detect_unavail_pmcs(ctx_fd, &inp.pfp_unavail_pmcs); /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) fatal_error("Cannot configure events: %s\n", pfm_strerror(ret)); /* * Now prepare the argument to initialize the PMDs and PMCS. * We use pfp_pmc_count to determine the number of registers to * setup. Note that this field can be >= pfp_event_count. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; pd[0].reg_value = 0; pd[0].reg_long_reset = 0; pd[0].reg_short_reset = 0; pd[0].reg_ovfl_switch_cnt = 0; for(k=0; k < NUM_SETS; k++) { setdesc.set_id = setinfo[k].set_id = k; setdesc.set_flags = PFM_SETFL_TIME_SWITCH; setdesc.set_timeout = THE_TIMEOUT * 1000000000; /* in nsecs */ for (i=0; i < outp.pfp_pmc_count; i++) pc[i].reg_set = k; for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_set = k; if (pfm_create_evtsets(ctx_fd, &setdesc, 1) == -1) fatal_error("pfm_create_evtsets error errno %d\n",errno); if (pfm_write_pmcs(ctx_fd, pc, outp.pfp_pmc_count) == -1) fatal_error("pfm_write_pmcs error errno %d\n",errno); /* * To be read, each PMD must be either written or declared * as being part of a sample (reg_smpl_pmds) */ if (pfm_write_pmds(ctx_fd, pd, outp.pfp_pmd_count) == -1) fatal_error("pfm_write_pmds error errno %d\n",errno); } setup_end_marker(ctx_fd, k, num_ovfls, inp.pfp_dfl_plm); /* * we want to monitor ourself */ load_args.load_pid = getpid(); load_args.load_set = 0; if (pfm_load_context(ctx_fd, &load_args) == -1) { fatal_error("pfm_load_context error errno %d\n",errno); } /* * setup asynchronous notification on the file descriptor */ ret = fcntl(ctx_fd, F_SETFL, fcntl(ctx_fd, F_GETFL, 0) | O_ASYNC); if (ret == -1) { fatal_error("cannot set ASYNC: %s\n", strerror(errno)); } /* * get ownership of the descriptor */ ret = fcntl(ctx_fd, F_SETOWN, getpid()); if (ret == -1) { fatal_error("cannot setown: %s\n", strerror(errno)); } /* * Let's roll now */ pfm_start(ctx_fd, NULL); busyloop(); pfm_stop(ctx_fd); close(ctx_fd); free(event1_name); return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/ia64/0000755000307100002310000000000013013651447020366 5ustar yarkhangraduatepapi-5.5.1/src/libpfm-3.y/examples_v2.x/ia64/mont_etb.c0000644000307100002310000003110213013651447022336 0ustar yarkhangraduate/* * mont_btb.c - example of how use the ETB with the Dual-Core Itanium 2 PMU * * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #include #include #include #include #include #include #include #include #include #include #include #include #include typedef pfm_dfl_smpl_hdr_t etb_hdr_t; typedef pfm_dfl_smpl_entry_t etb_entry_t; typedef pfm_dfl_smpl_arg_t smpl_arg_t; #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 #define MAX_PMU_NAME_LEN 32 /* * The ETB_EVENT is increment by 1 for each branch event. Such event is composed of * two entries in the ETB: a source and a target entry. The ETB is full after 4 branch * events. */ #define SMPL_PERIOD (4UL*256) /* * We use a small buffer size to exercise the overflow handler */ #define SMPL_BUF_NENTRIES 64 static void *smpl_vaddr; static size_t entry_size; static int id; #define BPL (sizeof(uint64_t)<<3) #define LBPL 6 static inline void pfm_bv_set(uint64_t *bv, uint16_t rnum) { bv[rnum>>LBPL] |= 1UL << (rnum&(BPL-1)); } /* * we don't use static to make sure the compiler does not inline the function */ long func1(void) { return random();} long func2(void) { return random();} long do_test(unsigned long loop) { long sum = 0; while(loop--) { if (loop & 0x1) sum += func1(); else sum += loop + func2(); } return sum; } static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } /* * print content of sampling buffer * * XXX: using stdio to print from a signal handler is not safe with multi-threaded * applications */ #define safe_printf printf static void show_etb_reg(int j, pfm_mont_pmd_reg_t reg, pfm_mont_pmd_reg_t pmd39) { unsigned long bruflush, b1, etb_ext; unsigned long addr; int is_valid; is_valid = reg.pmd48_63_etb_mont_reg.etb_s == 0 && reg.pmd48_63_etb_mont_reg.etb_mp == 0 ? 0 : 1; /* * the joy of the ETB extension register layout! */ if (j < 8) etb_ext = (pmd39.pmd_val>>(8*j)) & 0xf; else etb_ext = (pmd39.pmd_val>>(4+8*(j-8))) & 0xf; b1 = etb_ext & 0x1; bruflush = (etb_ext >> 1) & 0x1; safe_printf("\tPMD%-2d: 0x%016lx s=%d mp=%d bru=%ld b1=%ld valid=%c\n", j+48, reg.pmd_val, reg.pmd48_63_etb_mont_reg.etb_s, reg.pmd48_63_etb_mont_reg.etb_mp, bruflush, b1, is_valid ? 'Y' : 'N'); if (!is_valid) return; if (reg.pmd48_63_etb_mont_reg.etb_s) { addr = (reg.pmd48_63_etb_mont_reg.etb_addr+b1)<<4; addr |= reg.pmd48_63_etb_mont_reg.etb_slot < 3 ? reg.pmd48_63_etb_mont_reg.etb_slot : 0; safe_printf("\t Source Address: 0x%016lx\n" "\t Taken=%c Prediction:%s\n\n", addr, reg.pmd48_63_etb_mont_reg.etb_slot < 3 ? 'Y' : 'N', reg.pmd48_63_etb_mont_reg.etb_mp ? "FE Failure" : bruflush ? "BE Failure" : "Success"); } else { safe_printf("\t Target Address:0x%016lx\n\n", (unsigned long)(reg.pmd48_63_etb_mont_reg.etb_addr<<4)); } } static void show_etb(pfm_mont_pmd_reg_t *etb) { int i, last; pfm_mont_pmd_reg_t pmd38, pmd39; pmd38.pmd_val = etb[0].pmd_val; pmd39.pmd_val = etb[1].pmd_val; i = pmd38.pmd38_mont_reg.etbi_full ? pmd38.pmd38_mont_reg.etbi_ebi : 0; last = pmd38.pmd38_mont_reg.etbi_ebi; safe_printf("btb_trace: i=%d last=%d bbi=%d full=%d\n", i, last, pmd38.pmd38_mont_reg.etbi_ebi, pmd38.pmd38_mont_reg.etbi_full); /* * i+2 = skip over PMD38/pmd39 */ do { show_etb_reg(i, etb[i+2], pmd39); i = (i+1) % 16; } while (i != last); } void process_smpl_buffer(void) { etb_hdr_t *hdr; etb_entry_t *ent; unsigned long pos; unsigned long smpl_entry = 0; pfm_mont_pmd_reg_t *reg; size_t count; static unsigned long last_ovfl = ~0UL; hdr = (etb_hdr_t *)smpl_vaddr; /* * check that we are not diplaying the previous set of samples again. * Required to take care of the last batch of samples. */ if (hdr->hdr_overflows <= last_ovfl && last_ovfl != ~0UL) { printf("skipping identical set of samples %lu <= %lu\n", hdr->hdr_overflows, last_ovfl); return; } pos = (unsigned long)(hdr+1); count = hdr->hdr_count; /* * walk through all the entries recored in the buffer */ while(count--) { ent = (etb_entry_t *)pos; /* * print entry header */ safe_printf("Entry %ld PID:%d TID:%d CPU:%d STAMP:0x%lx IIP:0x%016lx\n", smpl_entry++, ent->tgid, ent->pid, ent->cpu, ent->tstamp, ent->ip); /* * point to first recorded register (always contiguous with entry header) */ reg = (pfm_mont_pmd_reg_t*)(ent+1); /* * in this particular example, we have pmd48-pmd63 has the ETB. We have also * included pmd38/pmd39 (ETB index and extenseion) has part of the registers * to record. This trick allows us to get the index to decode the sequential * order of the ETB. * * Recorded registers are always recorded in increasing index order. So we know * that where to find pmd38/pmd39. */ show_etb(reg); /* * move to next entry */ pos += entry_size; } } static void overflow_handler(int n, struct siginfo *info, struct sigcontext *sc) { process_smpl_buffer(); /* * And resume monitoring */ if (pfm_restart(id)) fatal_error("pfm_restart errno %d\n", errno); } int main(void) { int ret; int type = 0; pfarg_pmd_t pd[NUM_PMDS]; pfarg_pmc_t pc[NUM_PMCS]; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_mont_input_param_t mont_inp; pfarg_ctx_t ctx; smpl_arg_t buf_arg; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; struct sigaction act; unsigned int i; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) fatal_error("Can't initialize library\n"); /* * Let's make sure we run this on the right CPU */ pfm_get_pmu_type(&type); if (type != PFMLIB_MONTECITO_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with %s PMU\n", model); } /* * Install the overflow handler (SIGIO) */ memset(&act, 0, sizeof(act)); act.sa_handler = (sig_t)overflow_handler; sigaction (SIGIO, &act, 0); /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 0; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); memset(pd, 0, sizeof(pd)); memset(&ctx, 0, sizeof(ctx)); memset(&buf_arg, 0, sizeof(buf_arg)); /* * prepare parameters to library. we don't use any Itanium * specific features here. so the pfp_model is NULL. */ memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&mont_inp,0, sizeof(mont_inp)); /* * Before calling pfm_find_dispatch(), we must specify what kind * of branches we want to capture. We are interested in all taken * branches * therefore we program we set the various fields to: */ mont_inp.pfp_mont_etb.etb_used = 1; mont_inp.pfp_mont_etb.etb_tm = 0x2; mont_inp.pfp_mont_etb.etb_ptm = 0x3; mont_inp.pfp_mont_etb.etb_ppm = 0x3; mont_inp.pfp_mont_etb.etb_brt = 0x0; mont_inp.pfp_mont_etb.etb_plm = PFM_PLM3; if (pfm_find_full_event("ETB_EVENT", &inp.pfp_events[0]) != PFMLIB_SUCCESS) fatal_error("cannot find event ETB_EVENT\n"); /* * set the (global) privilege mode: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = 1; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, &mont_inp, &outp, NULL)) != PFMLIB_SUCCESS) fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); /* * the size of the buffer is indicated in bytes (not entries). * * The kernel will record into the buffer up to a certain point. * No partial samples are ever recorded. */ buf_arg.buf_size = getpagesize(); /* * now create the context for self monitoring/per-task */ id = pfm_create_context(&ctx, "default", &buf_arg, sizeof(buf_arg)); if (id == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * retrieve the virtual address at which the sampling * buffer has been mapped */ smpl_vaddr = mmap(NULL, (size_t)buf_arg.buf_size, PROT_READ, MAP_PRIVATE, id, 0); if (smpl_vaddr == MAP_FAILED) fatal_error("cannot mmap sampling buffer errno %d\n", errno); printf("Sampling buffer mapped at %p\n", smpl_vaddr); /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events cause extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * figure out pmd mapping from output pmc * PMD38 is part of the set of used PMD returned by libpfm. * It will be reset automatically */ for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * indicate we want notification when buffer is full and randomization */ pd[0].reg_flags |= PFM_REGFL_OVFL_NOTIFY | PFM_REGFL_RANDOM; /* * Now prepare the argument to initialize the PMD and the sampling period * We know we use only one PMD in this case, therefore pmd[0] corresponds * to our first event which is our sampling period. */ pd[0].reg_value = - SMPL_PERIOD; pd[0].reg_long_reset = - SMPL_PERIOD; pd[0].reg_short_reset = - SMPL_PERIOD; /* * populate our smpl_pmds bitmask to include all of the ETB PMDs, * including index, extensions */ pfm_bv_set(pd[0].reg_smpl_pmds, 38); pfm_bv_set(pd[0].reg_smpl_pmds, 39); entry_size = sizeof(etb_entry_t) + 2 * 8; for(i=48; i < 64; i++) { pfm_bv_set(pd[0].reg_smpl_pmds, i); entry_size += 8; } /* * When our counter overflows, we want to ETB index to be reset, so that we keep * in sync. */ pfm_bv_set(pd[0].reg_reset_pmds, 38); /* * Now program the registers */ if (pfm_write_pmcs(id, pc, outp.pfp_pmc_count)) fatal_error("pfm_write_pmcs error errno %d\n",errno); if (pfm_write_pmds(id, pd, outp.pfp_pmd_count)) fatal_error("pfm_write_pmds error errno %d\n",errno); /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = getpid(); if (pfm_load_context(id, &load_args)) fatal_error("pfm_load_context error errno %d\n",errno); /* * setup asynchronous notification on the file descriptor */ ret = fcntl(id, F_SETFL, fcntl(id, F_GETFL, 0) | O_ASYNC); if (ret == -1) fatal_error("cannot set ASYNC: %s\n", strerror(errno)); /* * get ownership of the descriptor */ ret = fcntl(id, F_SETOWN, getpid()); if (ret == -1) fatal_error("cannot setown: %s\n", strerror(errno)); /* * Let's roll now. */ pfm_self_start(id); do_test(1000); pfm_self_stop(id); /* * We must call the processing routine to cover the last entries recorded * in the sampling buffer. Note that the buffer may not be full at this point. * */ process_smpl_buffer(); /* * let's stop this now */ munmap(smpl_vaddr, (size_t)buf_arg.buf_size); close(id); return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/ia64/ita_opcode.c0000644000307100002310000001773613013651447022656 0ustar yarkhangraduate/* * ita_opcode.c - example of how to use the opcode matcher with the Itanium PMU * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #include #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 #define MAX_PMU_NAME_LEN 32 /* * we don't use static to make sure the compiler does not inline the function */ int do_test(unsigned long loop) { unsigned long sum = 0; while(loop--) sum += loop; return sum; } static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } int main(void) { int ret; int type = 0; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_ita_input_param_t ita_inp; pfarg_pmd_t pd[NUM_PMDS]; pfarg_pmc_t pc[NUM_PMCS]; pfarg_ctx_t ctx[1]; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; unsigned int i; int id; char name[MAX_EVT_NAME_LEN]; /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) fatal_error("Cannot initialize library: %s\n", pfm_strerror(ret)); /* * Let's make sure we run this on the right CPU */ pfm_get_pmu_type(&type); if (type != PFMLIB_ITANIUM_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with the %s PMU\n", model); } /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 0; /* set to 1 for verbose */ pfm_set_options(&pfmlib_options); memset(pd, 0, sizeof(pd)); memset(ctx, 0, sizeof(ctx)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&ita_inp,0, sizeof(ita_inp)); memset(&load_args,0, sizeof(load_args)); /* * We indicate that we are using the PMC8 opcode matcher. This is required * otherwise the library add PMC8 to the list of PMC to pogram during * pfm_dispatch_events(). */ ita_inp.pfp_ita_pmc8.opcm_used = 1; /* * We want to match all the br.cloop in our test function. * This branch is an IP-relative branch for which the major * opcode (bits [40-37]=4) and the btype field is 5 (which represents * bits[6-8]) so it is included in the match/mask fields of PMC8. * It is necessarily in a B slot. * * We don't care which operands are used with br.cloop therefore * the mask field of pmc8 is set such that only the 4 bits of the * opcode and 3 bits of btype must match exactly. This is accomplished by * clearing the top 4 bits and bits [6-8] of the mask field and setting the * remaining bits. Similarly, the match field only has the opcode value and btype * set according to the encoding of br.cloop, the * remaining bits are zero. Bit 60 of PMC8 is set to indicate * that we look only in B slots (this is the only possibility for * this instruction anyway). * * So the binary representation of the value for PMC8 is as follows: * * 6666555555555544444444443333333333222222222211111111110000000000 * 3210987654321098765432109876543210987654321098765432109876543210 * ---------------------------------------------------------------- * 0001010000000000000000101000000000000011111111111111000111111000 * * which yields a value of 0x1400028003fff1f8. * * Depending on the level of optimization to compile this code, it may * be that the count reported could be zero, if the compiler uses a br.cond * instead of br.cloop. */ ita_inp.pfp_ita_pmc8.pmc_val = 0x1400028003fff1f8; /* * To count the number of occurence of this instruction, we must * program a counting monitor with the IA64_TAGGED_INST_RETIRED_PMC8 * event. */ if (pfm_find_full_event("IA64_TAGGED_INST_RETIRED_PMC8", &inp.pfp_events[0]) != PFMLIB_SUCCESS) fatal_error("Cannot find event IA64_TAGGED_INST_RETIRED_PMC8\n"); /* * set the privilege mode: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = 1; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, &ita_inp, &outp, NULL)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); } /* * now create the context for self monitoring/per-task */ id = pfm_create_context(ctx, NULL, NULL, 0); if (id == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events cause extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * figure out pmd mapping from output pmc */ for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more thann coutning monitors. */ if (pfm_write_pmcs(id, pc, outp.pfp_pmc_count) == -1) fatal_error("pfm_write_pmcs error errno %d\n",errno); if (pfm_write_pmds(id, pd, outp.pfp_pmd_count) == -1) fatal_error("pfm_write_pmds error errno %d\n",errno); /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = getpid(); if (pfm_load_context(id, &load_args) == -1) fatal_error("pfm_load_context error errno %d\n",errno); /* * Let's roll now. */ pfm_self_start(id); do_test(100UL); pfm_self_stop(id); /* * now read the results */ if (pfm_read_pmds(id, pd, inp.pfp_event_count) == -1) fatal_error( "pfm_read_pmds error errno %d\n",errno); /* * print the results */ pfm_get_full_event_name(&inp.pfp_events[0], name, MAX_EVT_NAME_LEN); printf("PMD%-3u %20lu %s\n", pd[0].reg_num, pd[0].reg_value, name); if (pd[0].reg_value != 0) printf("compiler used br.cloop\n"); else printf("compiler did not use br.cloop\n"); /* * let's stop this now */ close(id); return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/ia64/ita_rr.c0000644000307100002310000002741613013651447022024 0ustar yarkhangraduate/* * ita_rr.c - example of how to use data range restriction with the Itanium PMU * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #include #define N_LOOP 100000000U #if defined(__ECC) && defined(__INTEL_COMPILER) /* if you do not have this file, your compiler is too old */ #include #define clear_psr_ac() __rum(1UL<<3) #elif defined(__GNUC__) static inline void clear_psr_ac(void) { __asm__ __volatile__("rum psr.ac;;" ::: "memory" ); } #else #error "You need to define clear_psr_ac() for your compiler" #endif #define TEST_DATA_COUNT 16 #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_PMU_NAME_LEN 32 #define MAX_EVT_NAME_LEN 128 typedef struct { char *event_name; unsigned long expected_value; } event_desc_t; static event_desc_t event_list[]={ { "misaligned_loads_retired", N_LOOP }, { "misaligned_stores_retired", N_LOOP }, { NULL, 0UL} }; typedef union { unsigned long l_tab[2]; unsigned int i_tab[4]; unsigned short s_tab[8]; unsigned char c_tab[16]; } test_data_t; static int do_test(test_data_t *data) { unsigned int *l, v; l = (unsigned int *)(data->c_tab+1); if (((unsigned long)l & 0x1) == 0) { printf("Data is not unaligned, can't run test\n"); return -1; } v = *l; v++; *l = v; return 0; } static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } int main(int argc, char **argv) { event_desc_t *p; test_data_t *test_data, *test_data_fake; unsigned long range_start, range_end; int ret, type = 0; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_ita_input_param_t ita_inp; pfmlib_ita_output_param_t ita_outp; pfarg_pmd_t pd[NUM_PMDS]; pfarg_pmc_t pc[NUM_PMCS]; pfarg_pmc_t dbrs[8]; pfarg_ctx_t ctx[1]; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; unsigned int i; int id; char name[MAX_EVT_NAME_LEN]; /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) fatal_error("Cannot initialize library: %s\n", pfm_strerror(ret)); /* * Let's make sure we run this on the right CPU family */ pfm_get_pmu_type(&type); if (type != PFMLIB_ITANIUM_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with %s PMU\n", model); } /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 0; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); /* * now let's allocate the data structure we will be monitoring */ test_data = (test_data_t *)malloc(sizeof(test_data_t)*TEST_DATA_COUNT); if (test_data == NULL) { fatal_error("cannot allocate test data structure"); } test_data_fake = (test_data_t *)malloc(sizeof(test_data_t)*TEST_DATA_COUNT); if (test_data_fake == NULL) { fatal_error("cannot allocate test data structure"); } /* * Compute the range we are interested in */ range_start = (unsigned long)test_data; range_end = range_start + sizeof(test_data_t)*TEST_DATA_COUNT; memset(pd, 0, sizeof(pd)); memset(pc, 0, sizeof(pc)); memset(ctx, 0, sizeof(ctx)); memset(dbrs,0, sizeof(dbrs)); memset(&load_args, 0, sizeof(load_args)); /* * prepare parameters to library. we don't use any Itanium * specific features here. so the pfp_model is NULL. */ memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&ita_inp,0, sizeof(ita_inp)); memset(&ita_outp,0, sizeof(ita_outp)); /* * find requested event */ p = event_list; for (i=0; p->event_name ; i++, p++) { if (pfm_find_event(p->event_name, &inp.pfp_events[i].event) != PFMLIB_SUCCESS) { fatal_error("Cannot find %s event\n", p->event_name); } } /* * set the privilege mode: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = i; /* * We use the library to figure out how to program the debug registers * to cover the data range we are interested in. The rr_end parameter * must point to the byte after the last of the range (C-style range). * * Because of the masking mechanism and therefore alignment constraints used to implement * this feature, it may not be possible to exactly cover a given range. It may be that * the coverage exceeds the desired range. So it is possible to capture noise if * the surrounding addresses are also heavily used. You can figure out, the actual * start and end offsets of the generated range by checking the rr_soff and rr_eoff fields * in the pfmlib_ita_output_param_t structure when coming back from the library call. * * Upon return, the pfmlib_ita_output_param_t.pfp_ita_drange.rr_dbr array is programmed and * the number of entries used to cover the range is in rr_nbr_used. */ /* * We indicate that we are using a Data Range Restriction feature. * In this particular case this will cause, pfm_dispatch_events() to * add pmc13 to the list of PMC registers to initialize and the */ ita_inp.pfp_ita_drange.rr_used = 1; ita_inp.pfp_ita_drange.rr_limits[0].rr_start = range_start; ita_inp.pfp_ita_drange.rr_limits[0].rr_end = range_end; /* * use the library to find the monitors to use * * upon return, cnt contains the number of entries * used in pc[]. */ if ((ret=pfm_dispatch_events(&inp, &ita_inp, &outp, &ita_outp)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); } printf("data range : [0x%016lx-0x%016lx): %d pair of debug registers used\n" "start_offset:-0x%lx end_offset:+0x%lx\n", range_start, range_end, ita_outp.pfp_ita_drange.rr_nbr_used >> 1, ita_outp.pfp_ita_drange.rr_infos[0].rr_soff, ita_outp.pfp_ita_drange.rr_infos[0].rr_eoff); printf("fake data range: [0x%016lx-0x%016lx)\n", (unsigned long)test_data_fake, (unsigned long)test_data_fake+sizeof(test_data_t)*TEST_DATA_COUNT); /* * now create the context for self monitoring/per-task */ id =pfm_create_context(ctx, NULL, NULL, 0); if (id == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("cannot create PFM context %s\n", strerror(errno)); } /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events cause extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * the PMC controlling the event ALWAYS come first, that's why this loop * is safe even when extra PMC are needed to support a particular event. */ for (i=0; i < inp.pfp_event_count; i++) { pd[i].reg_num = pc[i].reg_num; } /* * propagate the setup for the debug registers from the library to the arguments * to the syscall. The library does not know the type of the syscall * anymore. DBRS are ampped at PMC264+PMC271 */ for (i=0; i < ita_outp.pfp_ita_drange.rr_nbr_used; i++) { dbrs[i].reg_num = 264+ita_outp.pfp_ita_drange.rr_br[i].reg_num; dbrs[i].reg_value = ita_outp.pfp_ita_drange.rr_br[i].reg_value; } /* * Program the data debug registers. */ if (pfm_write_pmcs(id, dbrs, ita_outp.pfp_ita_drange.rr_nbr_used) == -1) { fatal_error("pfm_write_pmcs error errno %d\n",errno); } /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more than coutning monitors. */ if (pfm_write_pmcs(id, pc, outp.pfp_pmc_count) == -1) { fatal_error("pfm_write_pmcs error errno %d\n",errno); } if (pfm_write_pmds(id, pd, inp.pfp_event_count) == -1) { fatal_error("pfm_write_pmds error errno %d\n",errno); } /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = getpid(); if (pfm_load_context(id, &load_args) == -1) { fatal_error("pfm_load_context error errno %d\n",errno); } /* * Let's make sure that the hardware does the unaligned accesses (do not use the * kernel software handler otherwise the PMU won't see the unaligned fault). */ clear_psr_ac(); /* * Let's roll now. * * The idea behind this test is to have two dynamically allocated data structures * which are access in a unaligned fashion. But we want to capture only the unaligned * accesses on one of the two. So the debug registers are programmed to cover the * first one ONLY. Then we activate monotoring and access the two data structures. * This is an artificial example just to demonstrate how to use data address range * restrictions. */ pfm_self_start(id); for (i=0; i < N_LOOP; i++) { do_test(test_data); do_test(test_data_fake); } pfm_self_stop(id); /* * now read the results */ if (pfm_read_pmds(id, pd, inp.pfp_event_count) == -1) { fatal_error( "pfm_read_pmds error errno %d\n",errno); } /* * print the results * * It is important to realize, that the first event we specified may not * be in PMD4. Not all events can be measured by any monitor. That's why * we need to use the pc[] array to figure out where event i was allocated. * * For this example, we expect to see a value of 1 for both misaligned loads * and misaligned stores. But it can be two when the test_data and test_data_fake * are allocate very close from each other and the range created with the debug * registers is larger then test_data. * */ for (i=0; i < inp.pfp_event_count; i++) { pfm_get_full_event_name(&inp.pfp_events[i], name, MAX_EVT_NAME_LEN); printf("PMD%u %20lu %s (expected %lu)\n", pd[i].reg_num, pd[i].reg_value, name, event_list[i].expected_value); if (pd[i].reg_value != event_list[i].expected_value) { printf("error: Result should be %lu for %s\n", event_list[i].expected_value, name); break; } } /* * let's stop this now */ close(id); free(test_data); free(test_data_fake); return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/ia64/ita_dear.c0000644000307100002310000002513313013651447022306 0ustar yarkhangraduate/* * ita_dear.c - example of how use the D-EAR with the Itanium PMU * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 #define MAX_PMU_NAME_LEN 32 #define EVENT_NAME "DATA_EAR_CACHE_LAT4" #define SMPL_PERIOD (40) #define M_PMD(x) (1UL<<(x)) #define DEAR_REGS_MASK (M_PMD(2)|M_PMD(3)|M_PMD(17)) typedef pfm_dfl_smpl_hdr_t dear_hdr_t; typedef pfm_dfl_smpl_entry_t dear_entry_t; typedef pfm_dfl_smpl_arg_t smpl_arg_t; static void *smpl_vaddr; static unsigned long entry_size; static int id; #define BPL (sizeof(uint64_t)<<3) #define LBPL 6 static inline void pfm_bv_set(uint64_t *bv, uint16_t rnum) { bv[rnum>>LBPL] |= 1UL << (rnum&(BPL-1)); } long do_test(unsigned long size) { unsigned long i, sum = 0; int *array; printf("buffer size %.1fMB\n", (size*sizeof(int))/1024.0); array = (int *)malloc(size * sizeof(int)); if (array == NULL ) { printf("buffer size %.1fMB\n", (size*sizeof(int))/1024.0); exit(1); } for(i=0; ihdr_overflows <= last_ovfl && last_ovfl != ~0UL) { printf("skipping identical set of samples %lu <= %lu\n", hdr->hdr_overflows, last_ovfl); return; } pos = (unsigned long)(hdr+1); /* * walk through all the entries recored in the buffer */ for(i=0; i < hdr->hdr_count; i++) { ret = 0; ent = (dear_entry_t *)pos; /* * print entry header */ safe_printf("Entry %ld PID:%d TID:%d CPU:%d STAMP:0x%lx IIP:0x%016lx\n", smpl_entry++, ent->tgid, ent->pid, ent->cpu, ent->tstamp, ent->ip); /* * point to first recorded register (always contiguous with entry header) */ reg = (pfm_ita_pmd_reg_t*)(ent+1); safe_printf("PMD2 : 0x%016lx\n", reg->pmd_val); reg++; safe_printf("PMD3 : 0x%016lx, latency %u\n", reg->pmd_val, reg->pmd3_ita_reg.dear_latency); reg++; safe_printf("PMD17: 0x%016lx, valid %c, address 0x%016lx\n", reg->pmd_val, reg->pmd17_ita_reg.dear_vl ? 'Y': 'N', (reg->pmd17_ita_reg.dear_iaddr << 4) | (unsigned long)reg->pmd17_ita_reg.dear_slot); /* * move to next entry */ pos += entry_size; } } static void overflow_handler(int n, struct siginfo *info, struct sigcontext *sc) { /* dangerous */ printf("Notification received\n"); process_smpl_buffer(); /* * And resume monitoring */ if (pfm_restart(id) == -1) { perror("pfm_restart"); exit(1); } } int main(void) { pfarg_pmd_t pd[NUM_PMDS]; pfarg_pmc_t pc[NUM_PMCS]; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfarg_ctx_t ctx; smpl_arg_t buf_arg; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; struct sigaction act; unsigned int i; int ret, type = 0; /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) fatal_error("Cannot initialize library: %s\n", pfm_strerror(ret)); /* * Let's make sure we run this on the right CPU */ pfm_get_pmu_type(&type); if (type != PFMLIB_ITANIUM_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with %s PMU\n", model); } /* * Install the overflow handler (SIGIO) */ memset(&act, 0, sizeof(act)); act.sa_handler = (sig_t)overflow_handler; sigaction (SIGIO, &act, 0); /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 1; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); memset(pd, 0, sizeof(pd)); memset(pc, 0, sizeof(pc)); memset(&ctx, 0, sizeof(ctx)); memset(&buf_arg, 0, sizeof(buf_arg)); memset(&load_args, 0, sizeof(load_args)); /* * prepare parameters to library. we don't use any Itanium * specific features here. so the pfp_model is NULL. */ memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); /* * To count the number of occurence of this instruction, we must * program a counting monitor with the IA64_TAGGED_INST_RETIRED_PMC8 * event. */ if (pfm_find_full_event(EVENT_NAME, &inp.pfp_events[0]) != PFMLIB_SUCCESS) { fatal_error("cannot find event %s\n", EVENT_NAME); } /* * set the (global) privilege mode: * PFM_PLM0 : kernel level only */ inp.pfp_dfl_plm = PFM_PLM0|PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = 1; /* * let the library figure out the values for the PMCS * * We use all global settings for this EAR. */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); } /* * prepare context structure. * * format specific parameters MUST be concatenated to the regular * pfarg_ctx_t structure. For convenience, the default sampling * format provides a data structure that already combines the pfarg_ctx_t * with what is needed fot this format. */ /* * the size of the buffer is indicated in bytes (not entries). * * The kernel will record into the buffer up to a certain point. * No partial samples are ever recorded. */ buf_arg.buf_size = getpagesize(); /* * now create the context for self monitoring/per-task */ id = pfm_create_context(&ctx, "default", &buf_arg, sizeof(buf_arg)); if (id == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * retrieve the virtual address at which the sampling * buffer has been mapped */ smpl_vaddr = mmap(NULL, (size_t)buf_arg.buf_size, PROT_READ, MAP_PRIVATE, id, 0); if (smpl_vaddr == MAP_FAILED) fatal_error("cannot mmap sampling buffer errno %d\n", errno); printf("Sampling buffer mapped at %p\n", smpl_vaddr); /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events causes extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * figure out pmd mapping from output pmc */ for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * indicate we want notification when buffer is full */ pd[0].reg_flags |= PFM_REGFL_OVFL_NOTIFY; pfm_bv_set(pd[0].reg_smpl_pmds, 2); pfm_bv_set(pd[0].reg_smpl_pmds, 3); pfm_bv_set(pd[0].reg_smpl_pmds, 17); entry_size = sizeof(dear_entry_t) + 3 * 8; /* * initialize the PMD and the sampling period */ pd[0].reg_value = - SMPL_PERIOD; pd[0].reg_long_reset = - SMPL_PERIOD; pd[0].reg_short_reset = - SMPL_PERIOD; /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more thann coutning monitors. */ if (pfm_write_pmcs(id, pc, outp.pfp_pmc_count) == -1) fatal_error("pfm_write_pmcs error errno %d\n",errno); if (pfm_write_pmds(id, pd, outp.pfp_pmd_count) == -1) fatal_error("pfm_write_pmds error errno %d\n",errno); /* * attach context to stopped task */ load_args.load_pid = getpid(); if (pfm_load_context(id, &load_args) == -1) fatal_error("pfm_load_context error errno %d\n",errno); /* * setup asynchronous notification on the file descriptor */ ret = fcntl(id, F_SETFL, fcntl(id, F_GETFL, 0) | O_ASYNC); if (ret == -1) fatal_error("cannot set ASYNC: %s\n", strerror(errno)); /* * get ownership of the descriptor */ ret = fcntl(id, F_SETOWN, getpid()); if (ret == -1) fatal_error("cannot setown: %s\n", strerror(errno)); /* * Let's roll now. */ pfm_self_start(id); do_test(10000); pfm_self_stop(id); /* * We must call the processing routine to cover the last entries recorded * in the sampling buffer, i.e. which may not be full */ process_smpl_buffer(); /* * let's stop this now */ munmap(smpl_vaddr, (size_t)buf_arg.buf_size); close(id); return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/ia64/mont_irr.c0000644000307100002310000002477513013651447022402 0ustar yarkhangraduate/* * mont_irr.c - example of how to use code range restriction with the Dual-Core Itanium 2 PMU * * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #include #include #include #include #include #include #include #include #include #include #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 #define MAX_PMU_NAME_LEN 32 #define VECTOR_SIZE 1000000UL typedef struct { char *event_name; unsigned long expected_value; } event_desc_t; static event_desc_t event_list[]={ { "fp_ops_retired", VECTOR_SIZE<<1 }, { NULL, 0UL } }; static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } void saxpy(double *a, double *b, double *c, unsigned long size) { unsigned long i; for(i=0; i < size; i++) { c[i] = 2*a[i] + b[i]; } printf("saxpy done\n"); } void saxpy2(double *a, double *b, double *c, unsigned long size) { unsigned long i; for(i=0; i < size; i++) { c[i] = 2*a[i] + b[i]; } printf("saxpy2 done\n"); } static int do_test(void) { unsigned long size; double *a, *b, *c; size = VECTOR_SIZE; a = malloc(size*sizeof(double)); b = malloc(size*sizeof(double)); c = malloc(size*sizeof(double)); if (a == NULL || b == NULL || c == NULL) fatal_error("Cannot allocate vectors\n"); memset(a, 0, size*sizeof(double)); memset(b, 0, size*sizeof(double)); memset(c, 0, size*sizeof(double)); saxpy(a,b,c, size); saxpy2(a,b,c, size); return 0; } int main(int argc, char **argv) { event_desc_t *p; unsigned long range_start, range_end; int ret, type = 0; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_mont_input_param_t mont_inp; pfmlib_mont_output_param_t mont_outp; pfarg_pmd_t pd[NUM_PMDS]; pfarg_pmc_t pc[NUM_PMCS]; pfarg_pmc_t ibrs[8]; pfarg_ctx_t ctx; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; struct fd { /* function descriptor */ unsigned long addr; unsigned long gp; } *fd; unsigned int i; int id; char name[MAX_EVT_NAME_LEN]; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) fatal_error("Can't initialize library\n"); /* * Let's make sure we run this on the right CPU family */ pfm_get_pmu_type(&type); if (type != PFMLIB_MONTECITO_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with %s PMU\n", model); } /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 1; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 1; /* set to 1 for verbose */ pfm_set_options(&pfmlib_options); /* * Compute the range we are interested in * * On IA-64, the function pointer does not point directly * to the function but to a descriptor which contains two * unsigned long: the first one is the actual start address * of the function, the second is the gp (global pointer) * to load into r1 before jumping into the function. Unlesss * we're jumping into a shared library the gp is the same as * the current gp. * * In the artificial example, we also rely on the compiler/linker * NOT reordering code layout. We depend on saxpy2() being just * after saxpy(). * */ fd = (struct fd *)saxpy; range_start = fd->addr; fd = (struct fd *)saxpy2; range_end = fd->addr; /* * linker may reorder saxpy() and saxpy2() */ if (range_end < range_start) { unsigned long tmp; tmp = range_start; range_start = range_end; range_end = tmp; } memset(pc, 0, sizeof(pc)); memset(pd, 0, sizeof(pd)); memset(&ctx, 0, sizeof(ctx)); memset(ibrs,0, sizeof(ibrs)); memset(&load_args,0, sizeof(load_args)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&mont_inp,0, sizeof(mont_inp)); memset(&mont_outp,0, sizeof(mont_outp)); /* * find requested event */ p = event_list; for (i=0; p->event_name ; i++, p++) { if (pfm_find_event(p->event_name, &inp.pfp_events[i].event) != PFMLIB_SUCCESS) { fatal_error("cannot find %s event\n", p->event_name); } } /* * set the privilege mode: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = i; /* * We use the library to figure out how to program the debug registers * to cover the data range we are interested in. The rr_end parameter * must point to the byte after the last element of the range (C-style range). * * Because of the masking mechanism and therefore alignment constraints used to implement * this feature, it may not be possible to exactly cover a given range. It may be that * the coverage exceeds the desired range. So it is possible to capture noise if * the surrounding addresses are also heavily used. You can figure out by how much the * actual range is off compared to the requested range by checking the rr_soff and rr_eoff * fields on return from the library call. * * Upon return, the rr_dbr array is programmed and the number of debug registers (not pairs) * used to cover the range is in rr_nbr_used. * * In the case of code range restriction on Itanium 2, the library will try to use the fine * mode first and then it will default to using multiple pairs to cover the range. */ mont_inp.pfp_mont_irange.rr_used = 1; /* indicate we use code range restriction */ mont_inp.pfp_mont_irange.rr_limits[0].rr_start = range_start; mont_inp.pfp_mont_irange.rr_limits[0].rr_end = range_end; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, &mont_inp, &outp, &mont_outp)) != PFMLIB_SUCCESS) fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); /* * print offsets */ printf("code range : [0x%016lx-0x%016lx)\n" "start_offset:-0x%lx end_offset:+0x%lx\n" "%d pairs of debug registers used\n", range_start, range_end, mont_outp.pfp_mont_irange.rr_infos[0].rr_soff, mont_outp.pfp_mont_irange.rr_infos[0].rr_eoff, mont_outp.pfp_mont_irange.rr_nbr_used >> 1); /* * now create the context for self monitoring/per-task */ id = pfm_create_context(&ctx, NULL, NULL, 0); if (id == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events cause extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * figure out pmd mapping from output pmc */ for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * propagate IBR settings. IBRS are mapped to PMC256-PMC263 */ for (i=0; i < mont_outp.pfp_mont_irange.rr_nbr_used; i++) { ibrs[i].reg_num = 256+mont_outp.pfp_mont_irange.rr_br[i].reg_num; ibrs[i].reg_value = mont_outp.pfp_mont_irange.rr_br[i].reg_value; } /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more than coutning monitors. */ if (pfm_write_pmcs(id, pc, outp.pfp_pmc_count)) fatal_error("child: pfm_write_pmcs error errno %d\n",errno); /* * Program the code debug registers. */ if (pfm_write_pmcs (id, ibrs, mont_outp.pfp_mont_irange.rr_nbr_used)) fatal_error("child: pfm_write_pmcs error for IBRS errno %d\n",errno); if (pfm_write_pmds(id, pd, outp.pfp_pmd_count) == -1) fatal_error("child: pfm_write_pmds error errno %d\n",errno); /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = getpid(); if (pfm_load_context(id, &load_args)) fatal_error("pfm_load_context error errno %d\n",errno); /* * Let's roll now. * * We run two distinct copies of the same function but we restrict measurement * to the first one (saxpy). Therefore the expected count is half what you would * get if code range restriction was not used. The core loop in both case uses * two floating point operation per iteration. */ pfm_self_start(id); do_test(); pfm_self_stop(id); /* * now read the results */ if (pfm_read_pmds(id, pd, inp.pfp_event_count) == -1) { fatal_error( "pfm_read_pmds error errno %d\n",errno); } /* * print the results * * It is important to realize, that the first event we specified may not * be in PMD4. Not all events can be measured by any monitor. That's why * we need to use the pc[] array to figure out where event i was allocated. */ for (i=0; i < inp.pfp_event_count; i++) { pfm_get_full_event_name(&inp.pfp_events[i], name, MAX_EVT_NAME_LEN); printf("PMD%-3u %20lu %s (expected %lu)\n", pd[i].reg_num, pd[i].reg_value, name, event_list[i].expected_value); } /* * let's stop this now */ close(id); return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/ia64/ita2_irr.c0000644000307100002310000002553313013651447022255 0ustar yarkhangraduate/* * ita2_irr.c - example of how to use code range restriction with the Itanium2 PMU * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #include #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 #define MAX_PMU_NAME_LEN 32 #define VECTOR_SIZE 1000000UL typedef struct { char *event_name; unsigned long expected_value; } event_desc_t; static event_desc_t event_list[]={ { "fp_ops_retired", VECTOR_SIZE<<1 }, { NULL, 0UL } }; static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } void saxpy(double *a, double *b, double *c, unsigned long size) { unsigned long i; for(i=0; i < size; i++) { c[i] = 2*a[i] + b[i]; } printf("done saxpy\n"); } void saxpy2(double *a, double *b, double *c, unsigned long size) { unsigned long i; for(i=0; i < size; i++) { c[i] = 2*a[i] + b[i]; } printf("done saxpy2\n"); } static int do_test(void) { unsigned long size; double *a, *b, *c; size = VECTOR_SIZE; a = malloc(size*sizeof(double)); b = malloc(size*sizeof(double)); c = malloc(size*sizeof(double)); if (a == NULL || b == NULL || c == NULL) fatal_error("Cannot allocate vectors\n"); memset(a, 0, size*sizeof(double)); memset(b, 0, size*sizeof(double)); memset(c, 0, size*sizeof(double)); saxpy(a,b,c, size); saxpy2(a,b,c, size); return 0; } int main(int argc, char **argv) { event_desc_t *p; unsigned long range_start, range_end; int ret, type = 0; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_ita2_input_param_t ita2_inp; pfmlib_ita2_output_param_t ita2_outp; pfarg_pmd_t pd[NUM_PMDS]; pfarg_pmc_t pc[NUM_PMCS]; pfarg_pmc_t ibrs[8]; pfarg_ctx_t ctx[1]; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; struct fd { /* function descriptor */ unsigned long addr; unsigned long gp; } *fd; unsigned int i; int id; char name[MAX_EVT_NAME_LEN]; /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) fatal_error("Cannot initialize library: %s\n", pfm_strerror(ret)); /* * Let's make sure we run this on the right CPU family */ pfm_get_pmu_type(&type); if (type != PFMLIB_ITANIUM2_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with %s PMU\n", model); } /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 1; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 1; /* set to 1 for verbose */ pfm_set_options(&pfmlib_options); /* * Compute the range we are interested in * * On IA-64, the function pointer does not point directly * to the function but to a descriptor which contains two * unsigned long: the first one is the actual start address * of the function, the second is the gp (global pointer) * to load into r1 before jumping into the function. Unlesss * we're jumping into a shared library the gp is the same as * the current gp. * * In the artificial example, we also rely on the compiler/linker * NOT reordering code layout. We depend on saxpy2() being just * after saxpy(). * */ fd = (struct fd *)saxpy; range_start = fd->addr; fd = (struct fd *)saxpy2; range_end = fd->addr; /* * linker may reorder saxpy() and saxpy2() */ if (range_end < range_start) { unsigned long tmp; tmp = range_start; range_start = range_end; range_end = tmp; } memset(pc, 0, sizeof(pc)); memset(pd, 0, sizeof(pd)); memset(ctx, 0, sizeof(ctx)); memset(ibrs,0, sizeof(ibrs)); memset(&load_args,0, sizeof(load_args)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&ita2_inp,0, sizeof(ita2_inp)); memset(&ita2_outp,0, sizeof(ita2_outp)); /* * find requested event */ p = event_list; for (i=0; p->event_name ; i++, p++) { if (pfm_find_event(p->event_name, &inp.pfp_events[i].event) != PFMLIB_SUCCESS) { fatal_error("cannot find %s event\n", p->event_name); } } /* * set the privilege mode: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = i; /* * We use the library to figure out how to program the debug registers * to cover the data range we are interested in. The rr_end parameter * must point to the byte after the last element of the range (C-style range). * * Because of the masking mechanism and therefore alignment constraints used to implement * this feature, it may not be possible to exactly cover a given range. It may be that * the coverage exceeds the desired range. So it is possible to capture noise if * the surrounding addresses are also heavily used. You can figure out by how much the * actual range is off compared to the requested range by checking the rr_soff and rr_eoff * fields on return from the library call. * * Upon return, the rr_dbr array is programmed and the number of debug registers (not pairs) * used to cover the range is in rr_nbr_used. * * In the case of code range restriction on Itanium 2, the library will try to use the fine * mode first and then it will default to using multiple pairs to cover the range. */ ita2_inp.pfp_ita2_irange.rr_used = 1; /* indicate we use code range restriction */ ita2_inp.pfp_ita2_irange.rr_limits[0].rr_start = range_start; ita2_inp.pfp_ita2_irange.rr_limits[0].rr_end = range_end; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, &ita2_inp, &outp, &ita2_outp)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); } /* * print offsets */ printf("code range : [0x%016lx-0x%016lx)\n" "start_offset:-0x%lx end_offset:+0x%lx\n" "%d pairs of debug registers used\n", range_start, range_end, ita2_outp.pfp_ita2_irange.rr_infos[0].rr_soff, ita2_outp.pfp_ita2_irange.rr_infos[0].rr_eoff, ita2_outp.pfp_ita2_irange.rr_nbr_used >> 1); /* * now create the context for self monitoring/per-task */ id = pfm_create_context(ctx, NULL, NULL, 0); if (id == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events cause extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * figure out pmd mapping from output pmc */ for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * propagate the setup for the debug registers from the library to the arguments * to the syscall. The library does not know the type of the syscall * anymore. The code debug registers start at PMC256 on all Itanium processors. */ for (i=0; i < ita2_outp.pfp_ita2_irange.rr_nbr_used; i++) { ibrs[i].reg_num = 256+ita2_outp.pfp_ita2_irange.rr_br[i].reg_num; ibrs[i].reg_value = ita2_outp.pfp_ita2_irange.rr_br[i].reg_value; } /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more than coutning monitors. */ if (pfm_write_pmcs(id, pc, outp.pfp_pmc_count) == -1) fatal_error("child: pfm_write_pmcs error errno %d\n",errno); /* * Program the code debug registers. */ if (pfm_write_pmcs(id, ibrs, ita2_outp.pfp_ita2_irange.rr_nbr_used) == -1) fatal_error("child: pfm_write_pmcs error errno %d\n",errno); if (pfm_write_pmds(id, pd, outp.pfp_pmd_count) == -1) fatal_error("child: pfm_write_pmds error errno %d\n",errno); /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = getpid(); if (pfm_load_context(id, &load_args) == -1) { fatal_error("pfm_load_context error errno %d\n",errno); } /* * Let's roll now. * * We run two distinct copies of the same function but we restrict measurement * to the first one (saxpy). Therefore the expected count is half what you would * get if code range restriction was not used. The core loop in both case uses * two floating point operation per iteration. */ pfm_self_start(id); do_test(); pfm_self_stop(id); /* * now read the results */ if (pfm_read_pmds(id, pd, inp.pfp_event_count) == -1) fatal_error("pfm_read_pmds error errno %d\n",errno); /* * print the results * * It is important to realize, that the first event we specified may not * be in PMD4. Not all events can be measured by any monitor. That's why * we need to use the pc[] array to figure out where event i was allocated. */ for (i=0; i < inp.pfp_event_count; i++) { pfm_get_full_event_name(&inp.pfp_events[i], name, MAX_EVT_NAME_LEN); printf("PMD%-3u %20lu %s (expected %lu)\n", pd[i].reg_num, pd[i].reg_value, name, event_list[i].expected_value); } /* * let's stop this now */ close(id); return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/ia64/Makefile0000644000307100002310000000420013013651447022022 0ustar yarkhangraduate# # Copyright (c) 2002-2005 Hewlett-Packard Development Company, L.P. # Contributed by Stephane Eranian # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies # of the Software, and to permit persons to whom the Software is furnished to do so, # subject to the following conditions: # # The above copyright notice and this permission notice shall be included in all # copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, # INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A # PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT # HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE # OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # # This file is part of libpfm, a performance monitoring support library for # applications on Linux/ia64. # TOPDIR := $(shell if [ "$$PWD" != "" ]; then echo $$PWD; else pwd; fi)/../.. include $(TOPDIR)/config.mk include $(TOPDIR)/rules.mk LDFLAGS+=-static LIBS += -lm SRCS +=ita_rr.c ita_irr.c ita_opcode.c ita_btb.c ita_dear.c SRCS +=ita2_opcode.c ita2_rr.c ita2_irr.c ita2_dear.c ita2_btb.c SRCS +=mont_opcode.c mont_rr.c mont_irr.c mont_dear.c mont_etb.c TARGETS = $(SRCS:.c=) PFMLIB=$(PFMLIBDIR)/libpfm.a all: $(TARGETS) $(TARGETS): %:%.o $(PFMLIB) $(CC) -o $@ $(CFLAGS) $(LDFLAGS) $^ $(LIBS) clean: $(RM) -f *.o $(TARGETS) distclean: clean depend: $(MKDEP) $(CFLAGS) $(SRCS) install_examples: $(TARGETS) install_examples: @echo installing: $(TARGETS) -mkdir -p $(DESTDIR)$(EXAMPLESDIR)/ia64 $(INSTALL) -m 755 $(TARGETS) $(DESTDIR)$(EXAMPLESDIR)/ia64 # # examples are installed as part of the RPM install, typically in /usr/share/doc/libpfm-X.Y/ # papi-5.5.1/src/libpfm-3.y/examples_v2.x/ia64/ita2_dear.c0000644000307100002310000002505313013651447022371 0ustar yarkhangraduate/* * ita2_dear.c - example of how use the D-EAR with the Itanium 2 PMU * * Copyright (c) 2003-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 #define MAX_PMU_NAME_LEN 32 #define SMPL_PERIOD (40) #define EVENT_NAME "data_ear_cache_lat4" typedef pfm_dfl_smpl_hdr_t dear_hdr_t; typedef pfm_dfl_smpl_entry_t dear_entry_t; typedef pfm_dfl_smpl_arg_t smpl_arg_t; static void *smpl_vaddr; static unsigned long entry_size; static int id; #define BPL (sizeof(uint64_t)<<3) #define LBPL 6 static inline void pfm_bv_set(uint64_t *bv, uint16_t rnum) { bv[rnum>>LBPL] |= 1UL << (rnum&(BPL-1)); } long do_test(unsigned long size) { unsigned long i, sum = 0; int *array; printf("buffer size %.1fMB\n", (size*sizeof(int))/1024.0); array = (int *)malloc(size * sizeof(int)); if (array == NULL ) { printf("line = %d No memory available!\n", __LINE__); exit(1); } for(i=0; ihdr_overflows <= last_ovfl && last_ovfl != ~0UL) { printf("skipping identical set of samples %lu <= %lu\n", hdr->hdr_overflows, last_ovfl); return; } pos = (unsigned long)(hdr+1); /* * walk through all the entries recored in the buffer */ for(i=0; i < hdr->hdr_count; i++) { ret = 0; ent = (dear_entry_t *)pos; /* * print entry header */ safe_printf("Entry %ld PID:%d TID:%d CPU:%d STAMP:0x%lx IIP:0x%016lx\n", smpl_entry++, ent->tgid, ent->pid, ent->cpu, ent->tstamp, ent->ip); /* * point to first recorded register (always contiguous with entry header) */ reg = (pfm_ita2_pmd_reg_t*)(ent+1); safe_printf("PMD2 : 0x%016lx\n", reg->pmd_val); reg++; safe_printf("PMD3 : 0x%016lx, latency %u\n", reg->pmd_val, reg->pmd3_ita2_reg.dear_latency); reg++; safe_printf("PMD17: 0x%016lx, valid %c, address 0x%016lx\n", reg->pmd_val, reg->pmd17_ita2_reg.dear_vl ? 'Y': 'N', (reg->pmd17_ita2_reg.dear_iaddr << 4) | (unsigned long)reg->pmd17_ita2_reg.dear_slot); /* * move to next entry */ pos += entry_size; } } static void overflow_handler(int n, struct siginfo *info, struct sigcontext *sc) { /* dangerous */ printf("Notification received\n"); process_smpl_buffer(); /* * And resume monitoring */ if (pfm_restart(id) == -1) { perror("pfm_restart"); exit(1); } } int main(void) { pfarg_pmd_t pd[NUM_PMDS]; pfarg_pmc_t pc[NUM_PMCS]; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfarg_ctx_t ctx; smpl_arg_t buf_arg; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; struct sigaction act; unsigned int i; int ret, type = 0; /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) fatal_error("Cannot initialize library: %s\n", pfm_strerror(ret)); /* * Let's make sure we run this on the right CPU */ pfm_get_pmu_type(&type); if (type != PFMLIB_ITANIUM2_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with %s PMU\n", model); } /* * Install the overflow handler (SIGIO) */ memset(&act, 0, sizeof(act)); act.sa_handler = (sig_t)overflow_handler; sigaction (SIGIO, &act, 0); /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 1; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); memset(pd, 0, sizeof(pd)); memset(pc, 0, sizeof(pc)); memset(pc, 0, sizeof(pc)); memset(&ctx, 0, sizeof(ctx)); memset(&buf_arg, 0, sizeof(buf_arg)); memset(&load_args, 0, sizeof(load_args)); /* * prepare parameters to library. we don't use any Itanium * specific features here. so the pfp_model is NULL. */ memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); /* * To count the number of occurence of this instruction, we must * program a counting monitor with the IA64_TAGGED_INST_RETIRED_PMC8 * event. */ if (pfm_find_full_event(EVENT_NAME, &inp.pfp_events[0]) != PFMLIB_SUCCESS) { fatal_error("cannot find event %s\n", EVENT_NAME); } /* * set the (global) privilege mode: * PFM_PLM0 : kernel level only */ inp.pfp_dfl_plm = PFM_PLM3|PFM_PLM0; /* * how many counters we use */ inp.pfp_event_count = 1; /* * let the library figure out the values for the PMCS * * We use all global settings for this EAR. */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); } /* * prepare context structure. * * format specific parameters MUST be concatenated to the regular * pfarg_ctx_t structure. For convenience, the default sampling * format provides a data structure that already combines the pfarg_ctx_t * with what is needed fot this format. */ /* * the size of the buffer is indicated in bytes (not entries). * * The kernel will record into the buffer up to a certain point. * No partial samples are ever recorded. */ buf_arg.buf_size = getpagesize(); /* * now create the context for self monitoring/per-task */ id = pfm_create_context(&ctx, "default", &buf_arg, sizeof(buf_arg)); if (id == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * retrieve the virtual address at which the sampling * buffer has been mapped */ smpl_vaddr = mmap(NULL, (size_t)buf_arg.buf_size, PROT_READ, MAP_PRIVATE, id, 0); if (smpl_vaddr == MAP_FAILED) fatal_error("cannot mmap sampling buffer errno %d\n", errno); printf("Sampling buffer mapped at %p\n", smpl_vaddr); /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events causes extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * figure out pmd mapping from output pmc */ for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * indicate we want notification when buffer is full */ pd[0].reg_flags |= PFM_REGFL_OVFL_NOTIFY; pfm_bv_set(pd[0].reg_smpl_pmds, 2); pfm_bv_set(pd[0].reg_smpl_pmds, 3); pfm_bv_set(pd[0].reg_smpl_pmds, 17); entry_size = sizeof(dear_entry_t) + 3 * 8; /* * initialize the PMD and the sampling period */ pd[0].reg_value = - SMPL_PERIOD; pd[0].reg_long_reset = - SMPL_PERIOD; pd[0].reg_short_reset = - SMPL_PERIOD; /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more thann coutning monitors. */ if (pfm_write_pmcs(id, pc, outp.pfp_pmc_count) == -1) fatal_error("pfm_write_pmcs error errno %d\n",errno); if (pfm_write_pmds(id, pd, outp.pfp_pmd_count) == -1) fatal_error("pfm_write_pmds error errno %d\n",errno); /* * attach context to stopped task */ load_args.load_pid = getpid(); if (pfm_load_context(id, &load_args) == -1) fatal_error("pfm_load_context error errno %d\n",errno); /* * setup asynchronous notification on the file descriptor */ ret = fcntl(id, F_SETFL, fcntl(id, F_GETFL, 0) | O_ASYNC); if (ret == -1) fatal_error("cannot set ASYNC: %s\n", strerror(errno)); /* * get ownership of the descriptor */ ret = fcntl(id, F_SETOWN, getpid()); if (ret == -1) fatal_error("cannot setown: %s\n", strerror(errno)); /* * Let's roll now. */ pfm_self_start(id); do_test(100000); pfm_self_stop(id); /* * We must call the processing routine to cover the last entries recorded * in the sampling buffer, i.e. which may not be full */ process_smpl_buffer(); /* * let's stop this now */ munmap(smpl_vaddr, (size_t)buf_arg.buf_size); close(id); return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/ia64/ita2_rr.c0000644000307100002310000002571513013651447022106 0ustar yarkhangraduate/* * ita2_rr.c - example of how to use data range restriction with the Itanium2 PMU * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #include #if defined(__ECC) && defined(__INTEL_COMPILER) /* if you do not have this file, your compiler is too old */ #include #define clear_psr_ac() __rum(1UL<<3) #elif defined(__GNUC__) static inline void clear_psr_ac(void) { __asm__ __volatile__("rum psr.ac;;" ::: "memory" ); } #else #error "You need to define clear_psr_ac() for your compiler" #endif #define TEST_DATA_COUNT 16 #define N_LOOP 100000000UL #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 #define MAX_PMU_NAME_LEN 32 /* * here we capture only misaligned_loads because it cannot * be measured with misaligned_stores_retired at the same time */ static char *event_list[]={ "misaligned_loads_retired", NULL }; typedef union { unsigned long l_tab[2]; unsigned int i_tab[4]; unsigned short s_tab[8]; unsigned char c_tab[16]; } test_data_t; static int do_test(test_data_t *data) { unsigned int *l, v; l = (unsigned int *)(data->c_tab+1); if (((unsigned long)l & 0x1) == 0) { printf("Data is not unaligned, can't run test\n"); return -1; } v = *l; v++; *l = v; return 0; } static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } int main(int argc, char **argv) { char **p; test_data_t *test_data, *test_data_fake; unsigned long range_start, range_end; int ret, type = 0; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_ita2_input_param_t ita2_inp; pfmlib_ita2_output_param_t ita2_outp; pfarg_pmd_t pd[NUM_PMDS]; pfarg_pmc_t pc[NUM_PMCS]; pfarg_ctx_t ctx[1]; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; unsigned int i; int id, num_pmcs = 0; char name[MAX_EVT_NAME_LEN]; /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) fatal_error("Cannot initialize library: %s\n", pfm_strerror(ret)); /* * Let's make sure we run this on the right CPU family */ pfm_get_pmu_type(&type); if (type != PFMLIB_ITANIUM2_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with %s PMU\n", model); } /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 1; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); /* * now let's allocate the data structure we will be monitoring */ test_data = (test_data_t *)malloc(sizeof(test_data_t)*TEST_DATA_COUNT); if (test_data == NULL) { fatal_error("cannot allocate test data structure"); } test_data_fake = (test_data_t *)malloc(sizeof(test_data_t)*TEST_DATA_COUNT); if (test_data_fake == NULL) { fatal_error("cannot allocate test data structure"); } /* * Compute the range we are interested in */ range_start = (unsigned long)test_data; range_end = range_start + sizeof(test_data_t)*TEST_DATA_COUNT; memset(pd, 0, sizeof(pd)); memset(pc, 0, sizeof(pc)); memset(ctx, 0, sizeof(ctx)); memset(&load_args, 0, sizeof(load_args)); /* * prepare parameters to library. we don't use any Itanium * specific features here. so the pfp_model is NULL. */ memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&ita2_inp,0, sizeof(ita2_inp)); memset(&ita2_outp,0, sizeof(ita2_outp)); /* * find requested event */ p = event_list; for (i=0; *p ; i++, p++) { if (pfm_find_event(*p, &inp.pfp_events[i].event) != PFMLIB_SUCCESS) { fatal_error("Cannot find %s event\n", *p); } } /* * set the privilege mode: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = i; /* * We use the library to figure out how to program the debug registers * to cover the data range we are interested in. The rr_end parameter * must point to the byte after the last element of the range (C-style range). * * Because of the masking mechanism and therefore alignment constraints used to implement * this feature, it may not be possible to exactly cover a given range. It may be that * the coverage exceeds the desired range. So it is possible to capture noise if * the surrounding addresses are also heavily used. You can figure out by how much the * actual range is off compared to the requested range by checking the rr_soff and rr_eoff * fields in rr_infos on return from the library call. * * Upon return, the rr_dbr array is programmed and the number of debug registers (not pairs) * used to cover the range is in rr_nbr_used. */ ita2_inp.pfp_ita2_drange.rr_used = 1; ita2_inp.pfp_ita2_drange.rr_limits[0].rr_start = range_start; ita2_inp.pfp_ita2_drange.rr_limits[0].rr_end = range_end; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, &ita2_inp, &outp, &ita2_outp)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); } printf("data range : [0x%016lx-0x%016lx): %d pair of debug registers used\n" "start_offset:-0x%lx end_offset:+0x%lx\n", range_start, range_end, ita2_outp.pfp_ita2_drange.rr_nbr_used >> 1, ita2_outp.pfp_ita2_drange.rr_infos[0].rr_soff, ita2_outp.pfp_ita2_drange.rr_infos[0].rr_eoff); printf("fake data range: [0x%016lx-0x%016lx)\n", (unsigned long)test_data_fake, (unsigned long)test_data_fake+sizeof(test_data_t)*TEST_DATA_COUNT); /* * now create the context for self monitoring/per-task */ id = pfm_create_context(ctx, NULL, NULL, 0); if (id == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events causes extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++, num_pmcs++) { pc[num_pmcs].reg_num = outp.pfp_pmcs[i].reg_num; pc[num_pmcs].reg_value = outp.pfp_pmcs[i].reg_value; } /* * propagate the setup for the debug registers from the library to the arguments * to the syscall. */ for (i=0; i < ita2_outp.pfp_ita2_drange.rr_nbr_used; i++, num_pmcs++) { pc[num_pmcs].reg_num = 264+ita2_outp.pfp_ita2_drange.rr_br[i].reg_num; pc[num_pmcs].reg_value = ita2_outp.pfp_ita2_drange.rr_br[i].reg_value; } /* * figure out pmd mapping from output pmc */ for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more than coutning monitors. */ if (pfm_write_pmcs(id, pc, num_pmcs) == -1) fatal_error("child: pfm_write_pmc error errno %d\n",errno); if (pfm_write_pmds(id, pd, outp.pfp_pmd_count) == -1) fatal_error( "child: pfm_write_pmds error errno %d\n",errno); /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = getpid(); if (pfm_load_context(id, &load_args) == -1) { fatal_error("pfm_load_context error errno %d\n",errno); } /* * Let's make sure that the hardware does the unaligned accesses (do not use the * kernel software handler otherwise the PMU won't see the unaligned fault). */ clear_psr_ac(); /* * Let's roll now. * * The idea behind this test is to have two dynamically allocated data structures * which are access in a unaligned fashion. But we want to capture only the unaligned * accesses on one of the two. So the debug registers are programmed to cover the * first one ONLY. Then we activate monotoring and access the two data structures. * This is an artificial example just to demonstrate how to use data address range * restrictions. */ pfm_self_start(id); for(i=0; i < N_LOOP; i++) { do_test(test_data); do_test(test_data_fake); } pfm_self_stop(id); /* * now read the results */ if (pfm_read_pmds(id, pd, inp.pfp_event_count) == -1) fatal_error( "pfm_read_pmds error errno %d\n",errno); /* * print the results * * It is important to realize, that the first event we specified may not * be in PMD4. Not all events can be measured by any monitor. That's why * we need to use the pc[] array to figure out where event i was allocated. * * For this example, we expect to see a value of 1 for misaligned loads. * But it can be two when the test_data and test_data_fake * are allocated very close from each other and the range created with the debug * registers is larger then test_data. * */ for (i=0; i < inp.pfp_event_count; i++) { pfm_get_full_event_name(&inp.pfp_events[i], name, MAX_EVT_NAME_LEN); printf("PMD%-3u %20lu %s (expected %lu)\n", pd[i].reg_num, pd[i].reg_value, name, N_LOOP); if (pd[i].reg_value != N_LOOP) { printf("error: Result should be 1 for %s\n", name); break; } } /* * let's stop this now */ close(id); free(test_data); free(test_data_fake); return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/ia64/ita_btb.c0000644000307100002310000003115713013651447022145 0ustar yarkhangraduate/* * ita_btb.c - example of how use the BTB with the Itanium PMU * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #include #include #include #include typedef pfm_dfl_smpl_hdr_t btb_hdr_t; typedef pfm_dfl_smpl_entry_t btb_entry_t; typedef pfm_dfl_smpl_arg_t smpl_arg_t; #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 #define MAX_PMU_NAME_LEN 32 /* * The BRANCH_EVENT is increment by 1 for each branch event. Such event is composed of * two entries in the BTB: a source and a target entry. The BTB is full after 4 branch * events. */ #define SMPL_PERIOD (4UL*256) /* * We use a small buffer size to exercise the overflow handler */ #define SMPL_BUF_NENTRIES 64 static void *smpl_vaddr; static unsigned int entry_size; static int id; #define BPL (sizeof(uint64_t)<<3) #define LBPL 6 static inline void pfm_bv_set(uint64_t *bv, uint16_t rnum) { bv[rnum>>LBPL] |= 1UL << (rnum&(BPL-1)); } /* * we don't use static to make sure the compiler does not inline the function */ long func1(void) { return 0;} long do_test(unsigned long loop) { long sum = 0; while(loop--) { if (loop & 0x1) sum += func1(); else sum += loop; } return sum; } static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } /* * print content of sampling buffer * * XXX: using stdio to print from a signal handler is not safe with multi-threaded * applications */ #define safe_printf printf static int show_btb_reg(int j, pfm_ita_pmd_reg_t reg) { int ret; int is_valid = reg.pmd8_15_ita_reg.btb_b == 0 && reg.pmd8_15_ita_reg.btb_mp == 0 ? 0 :1; ret = safe_printf("\tPMD%-2d: 0x%016lx b=%d mp=%d valid=%c\n", j, reg.pmd_val, reg.pmd8_15_ita_reg.btb_b, reg.pmd8_15_ita_reg.btb_mp, is_valid ? 'Y' : 'N'); if (!is_valid) return ret; if (reg.pmd8_15_ita_reg.btb_b) { unsigned long addr; addr = reg.pmd8_15_ita_reg.btb_addr<<4; addr |= reg.pmd8_15_ita_reg.btb_slot < 3 ? reg.pmd8_15_ita_reg.btb_slot : 0; ret = safe_printf("\t Source Address: 0x%016lx\n" "\t Taken=%c Prediction: %s\n\n", addr, reg.pmd8_15_ita_reg.btb_slot < 3 ? 'Y' : 'N', reg.pmd8_15_ita_reg.btb_mp ? "Failure" : "Success"); } else { ret = safe_printf("\t Target Address: 0x%016lx\n\n", (unsigned long)(reg.pmd8_15_ita_reg.btb_addr<<4)); } return ret; } static void show_btb(pfm_ita_pmd_reg_t *btb, pfm_ita_pmd_reg_t *pmd16) { int i, last; i = (pmd16->pmd16_ita_reg.btbi_full) ? pmd16->pmd16_ita_reg.btbi_bbi : 0; last = pmd16->pmd16_ita_reg.btbi_bbi; safe_printf("btb_trace: i=%d last=%d bbi=%d full=%d\n", i, last,pmd16->pmd16_ita_reg.btbi_bbi, pmd16->pmd16_ita_reg.btbi_full); do { show_btb_reg(i+8, btb[i]); i = (i+1) % 8; } while (i != last); } static void process_smpl_buffer(void) { btb_hdr_t *hdr; btb_entry_t *ent; unsigned long pos; unsigned long smpl_entry = 0; pfm_ita_pmd_reg_t *reg, *pmd16; unsigned long i; int ret; static unsigned long last_ovfl = ~0UL; hdr = (btb_hdr_t *)smpl_vaddr; /* * check that we are not diplaying the previous set of samples again. * Required to take care of the last batch of samples. */ if (hdr->hdr_overflows <= last_ovfl && last_ovfl != ~0UL) { printf("skipping identical set of samples %lu <= %lu\n", hdr->hdr_overflows, last_ovfl); return; } pos = (unsigned long)(hdr+1); /* * walk through all the entries recored in the buffer */ for(i=0; i < hdr->hdr_count; i++) { ret = 0; ent = (btb_entry_t *)pos; /* * print entry header */ safe_printf("Entry %ld PID:%d TID:%d CPU:%d STAMP:0x%lx IIP:0x%016lx\n", smpl_entry++, ent->tgid, ent->pid, ent->cpu, ent->tstamp, ent->ip); /* * point to first recorded register (always contiguous with entry header) */ reg = (pfm_ita_pmd_reg_t*)(ent+1); /* * in this particular example, we have pmd8-pmd15 has the BTB. We have also * included pmd16 (BTB index) has part of the registers to record. This trick * allows us to get the index to decode the sequential order of the BTB. * * Recorded registers are always recorded in increasing order. So we know * that pmd16 is at a fixed offset (+8*sizeof(unsigned long)) from pmd8. */ pmd16 = reg+8; show_btb(reg, pmd16); /* * move to next entry */ pos += entry_size; } } static void overflow_handler(int n, struct siginfo *info, struct sigcontext *sc) { /* dangerous */ printf("Notification received\n"); process_smpl_buffer(); /* * And resume monitoring */ if (pfm_restart(id) == -1) { perror("pfm_restart"); exit(1); } } int main(void) { int ret; int type = 0; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_ita_input_param_t ita_inp; pfarg_pmd_t pd[NUM_PMDS]; pfarg_pmc_t pc[NUM_PMCS]; pfarg_ctx_t ctx; smpl_arg_t buf_arg; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; struct sigaction act; unsigned int i; /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) fatal_error("Cannot initialize library: %s\n", pfm_strerror(ret)); /* * Let's make sure we run this on the right CPU */ pfm_get_pmu_type(&type); if (type != PFMLIB_ITANIUM_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with %s PMU\n", model); } /* * Install the overflow handler (SIGIO) */ memset(&act, 0, sizeof(act)); act.sa_handler = (sig_t)overflow_handler; sigaction (SIGIO, &act, 0); /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 0; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); memset(pd, 0, sizeof(pd)); memset(&ctx, 0, sizeof(ctx)); memset(&buf_arg, 0, sizeof(buf_arg)); memset(&inp, 0, sizeof(inp)); memset(&outp, 0, sizeof(outp)); memset(&ita_inp,0, sizeof(ita_inp)); /* * Before calling pfm_find_dispatch(), we must specify what kind * of branches we want to capture. We are interesteed in all the mispredicted branches, * therefore we program we set the various fields of the BTB config to: */ ita_inp.pfp_ita_btb.btb_used = 1; ita_inp.pfp_ita_btb.btb_tar = 0x1; ita_inp.pfp_ita_btb.btb_tm = 0x2; ita_inp.pfp_ita_btb.btb_ptm = 0x3; ita_inp.pfp_ita_btb.btb_tac = 0x1; ita_inp.pfp_ita_btb.btb_bac = 0x1; ita_inp.pfp_ita_btb.btb_ppm = 0x3; ita_inp.pfp_ita_btb.btb_plm = PFM_PLM3; /* * To count the number of occurence of this instruction, we must * program a counting monitor with the IA64_TAGGED_INST_RETIRED_PMC8 * event. */ if (pfm_find_full_event("BRANCH_EVENT", &inp.pfp_events[0]) != PFMLIB_SUCCESS) fatal_error("cannot find event BRANCH_EVENT\n"); /* * set the (global) privilege mode: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = 1; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, &ita_inp, &outp, NULL)) != PFMLIB_SUCCESS) fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); /* * the size of the buffer is indicated in bytes (not entries). * * The kernel will record into the buffer up to a certain point. * No partial samples are ever recorded. */ buf_arg.buf_size = getpagesize(); /* * now create the context for self monitoring/per-task */ id = pfm_create_context(&ctx, "default", &buf_arg, sizeof(buf_arg)); if (id == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * retrieve the virtual address at which the sampling * buffer has been mapped */ smpl_vaddr = mmap(NULL, (size_t)buf_arg.buf_size, PROT_READ, MAP_PRIVATE, id, 0); if (smpl_vaddr == MAP_FAILED) fatal_error("cannot mmap sampling buffer errno %d\n", errno); printf("Sampling buffer mapped at %p\n", smpl_vaddr); /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events cause extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * figure out pmd mapping from output pmc * PMD16 is part of the set of used PMD returned by libpfm. * It will be reset automatically */ for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * indicate we want notification when buffer is full */ pd[0].reg_flags |= PFM_REGFL_OVFL_NOTIFY; /* * Now prepare the argument to initialize the PMD and the sampling period * We know we use only one PMD in this case, therefore pmd[0] corresponds * to our first event which is our sampling period. */ pd[0].reg_value = - SMPL_PERIOD; pd[0].reg_long_reset = - SMPL_PERIOD; pd[0].reg_short_reset = - SMPL_PERIOD; pfm_bv_set(pd[0].reg_smpl_pmds, 16); entry_size = sizeof(btb_entry_t) + 1 * 8; for(i=8; i < 16; i++) { pfm_bv_set(pd[0].reg_smpl_pmds, i); entry_size += 8; } /* * When our counter overflows, we want to BTB index to be reset, so that we keep * in sync. This is required to make it possible to interpret pmd16 on overflow * to avoid repeating the same branch several times. */ pfm_bv_set(pd[0].reg_reset_pmds, 16); /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more thann coutning monitors. */ if (pfm_write_pmcs(id, pc, outp.pfp_pmc_count) == -1) fatal_error("pfm_write_pmcs error errno %d\n",errno); if (pfm_write_pmds(id, pd, outp.pfp_pmd_count) == -1) fatal_error("pfm_write_pmds error errno %d\n",errno); /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = getpid(); if (pfm_load_context(id, &load_args) == -1) fatal_error("pfm_load_context error errno %d\n",errno); /* * setup asynchronous notification on the file descriptor */ ret = fcntl(id, F_SETFL, fcntl(id, F_GETFL, 0) | O_ASYNC); if (ret == -1) fatal_error("cannot set ASYNC: %s\n", strerror(errno)); /* * get ownership of the descriptor */ ret = fcntl(id, F_SETOWN, getpid()); if (ret == -1) fatal_error("cannot setown: %s\n", strerror(errno)); /* * Let's roll now. */ pfm_self_start(id); do_test(100000); pfm_self_stop(id); /* * We must call the processing routine to cover the last entries recorded * in the sampling buffer. Note that the buffer may not be full at this point. * */ process_smpl_buffer(); /* * let's stop this now */ munmap(smpl_vaddr, (size_t)buf_arg.buf_size); close(id); return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/ia64/mont_dear.c0000644000307100002310000002474113013651447022512 0ustar yarkhangraduate/* * mont_dear.c - example of how use the D-EAR with the Dual-core Itanium 2 PMU * * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 #define MAX_PMU_NAME_LEN 32 #define SMPL_PERIOD (40) #define EVENT_NAME "data_ear_cache_lat4" typedef pfm_dfl_smpl_hdr_t dear_hdr_t; typedef pfm_dfl_smpl_entry_t dear_entry_t; typedef pfm_dfl_smpl_arg_t dear_smpl_arg_t; static void *smpl_vaddr; static unsigned long entry_size; static int id; #define BPL (sizeof(uint64_t)<<3) #define LBPL 6 static inline void pfm_bv_set(uint64_t *bv, uint16_t rnum) { bv[rnum>>LBPL] |= 1UL << (rnum&(BPL-1)); } long do_test(unsigned long size) { unsigned long i, sum = 0; int *array; printf("buffer size %.1fMB\n", (size*sizeof(int))/1024.0); array = (int *)malloc(size * sizeof(int)); if (array == NULL ) { printf("line = %d No memory available!\n", __LINE__); exit(1); } for(i=0; ihdr_overflows <= last_ovfl && last_ovfl != ~0UL) { printf("skipping identical set of samples %lu <= %lu\n", hdr->hdr_overflows, last_ovfl); return; } pos = (unsigned long)(hdr+1); count = hdr->hdr_count; /* * walk through all the entries recored in the buffer */ while(count--) { ret = 0; ent = (dear_entry_t *)pos; /* * print entry header */ safe_printf("Entry %ld PID:%d TID:%d CPU:%d STAMP:0x%lx IIP:0x%016lx\n", smpl_entry++, ent->tgid, ent->pid, ent->cpu, ent->tstamp, ent->ip); /* * point to first recorded register (always contiguous with entry header) */ reg = (pfm_mont_pmd_reg_t*)(ent+1); safe_printf("PMD32: 0x%016lx\n", reg->pmd32_mont_reg.dear_daddr); reg++; safe_printf("PMD33: 0x%016lx, latency %u\n", reg->pmd_val, reg->pmd33_mont_reg.dear_latency); reg++; safe_printf("PMD36: 0x%016lx, valid %c, address 0x%016lx\n", reg->pmd_val, reg->pmd36_mont_reg.dear_vl ? 'Y': 'N', (reg->pmd36_mont_reg.dear_iaddr << 4) | (unsigned long)reg->pmd36_mont_reg.dear_slot); /* * move to next entry */ pos += entry_size; } } static void overflow_handler(int n, struct siginfo *info, struct sigcontext *sc) { process_smpl_buffer(); /* * And resume monitoring */ if (pfm_restart(id)) fatal_error("pfm_restart"); } int main(void) { pfarg_pmd_t pd[NUM_PMDS]; pfarg_pmc_t pc[NUM_PMCS]; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfarg_ctx_t ctx; dear_smpl_arg_t buf_arg; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; struct sigaction act; unsigned int i; int ret, type = 0; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) fatal_error("Can't initialize library\n"); /* * Let's make sure we run this on the right CPU */ pfm_get_pmu_type(&type); if (type != PFMLIB_MONTECITO_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with %s PMU\n", model); } /* * Install the overflow handler (SIGIO) */ memset(&act, 0, sizeof(act)); act.sa_handler = (sig_t)overflow_handler; sigaction (SIGIO, &act, 0); /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 1; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); memset(pd, 0, sizeof(pd)); memset(pc, 0, sizeof(pc)); memset(pc, 0, sizeof(pc)); memset(&ctx, 0, sizeof(ctx)); memset(&buf_arg, 0, sizeof(buf_arg)); memset(&load_args, 0, sizeof(load_args)); /* * prepare parameters to library. we don't use any Itanium * specific features here. so the pfp_model is NULL. */ memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); /* * To count the number of occurence of this instruction, we must * program a counting monitor with the IA64_TAGGED_INST_RETIRED_PMC8 * event. */ if (pfm_find_full_event(EVENT_NAME, &inp.pfp_events[0]) != PFMLIB_SUCCESS) fatal_error("cannot find event %s\n", EVENT_NAME); /* * set the (global) privilege mode: * PFM_PLM0 : kernel level only */ inp.pfp_dfl_plm = PFM_PLM3|PFM_PLM0; /* * how many counters we use */ inp.pfp_event_count = 1; /* * let the library figure out the values for the PMCS * * We use all global settings for this EAR. */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); /* * prepare context structure. * * format specific parameters MUST be concatenated to the regular * pfarg_ctx_t structure. For convenience, the default sampling * format provides a data structure that already combines the pfarg_ctx_t * with what is needed fot this format. */ /* * the size of the buffer is indicated in bytes (not entries). * * The kernel will record into the buffer up to a certain point. * No partial samples are ever recorded. */ buf_arg.buf_size = getpagesize(); /* * now create the context for self monitoring/per-task */ id = pfm_create_context(&ctx, "default", &buf_arg, sizeof(buf_arg)); if (id == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * retrieve the virtual address at which the sampling * buffer has been mapped */ smpl_vaddr = mmap(NULL, (size_t)buf_arg.buf_size, PROT_READ, MAP_PRIVATE, id, 0); if (smpl_vaddr == MAP_FAILED) fatal_error("cannot mmap sampling buffer errno %d\n", errno); printf("Sampling buffer mapped at %p\n", smpl_vaddr); /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events causes extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * figure out pmd mapping from output pmc */ for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * indicate we want notification when buffer is full */ pd[0].reg_flags |= PFM_REGFL_OVFL_NOTIFY; pfm_bv_set(pd[0].reg_smpl_pmds, 32); pfm_bv_set(pd[0].reg_smpl_pmds, 33); pfm_bv_set(pd[0].reg_smpl_pmds, 36); entry_size = sizeof(dear_entry_t) + 3 * 8; /* * initialize the PMD and the sampling period */ pd[0].reg_value = - SMPL_PERIOD; pd[0].reg_long_reset = - SMPL_PERIOD; pd[0].reg_short_reset = - SMPL_PERIOD; /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more thann coutning monitors. */ if (pfm_write_pmcs(id, pc, outp.pfp_pmc_count)) fatal_error("pfm_write_pmcs error errno %d\n",errno); if (pfm_write_pmds(id, pd, outp.pfp_pmd_count)) fatal_error("pfm_write_pmds error errno %d\n",errno); /* * attach context to stopped task */ load_args.load_pid = getpid(); if (pfm_load_context(id, &load_args)) fatal_error("pfm_load_context error errno %d\n",errno); /* * setup asynchronous notification on the file descriptor */ ret = fcntl(id, F_SETFL, fcntl(id, F_GETFL, 0) | O_ASYNC); if (ret == -1) fatal_error("cannot set ASYNC: %s\n", strerror(errno)); /* * get ownership of the descriptor */ ret = fcntl(id, F_SETOWN, getpid()); if (ret == -1) fatal_error("cannot setown: %s\n", strerror(errno)); /* * Let's roll now. */ pfm_self_start(id); do_test(100000); pfm_self_stop(id); /* * We must call the processing routine to cover the last entries recorded * in the sampling buffer, i.e. which may not be full */ process_smpl_buffer(); /* * let's stop this now */ munmap(smpl_vaddr, (size_t)buf_arg.buf_size); close(id); return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/ia64/mont_opcode.c0000644000307100002310000001635713013651447023054 0ustar yarkhangraduate/* * mont_opcode.c - example of how to use the opcode matcher with the Dual-Core Itanium 2 PMU * * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #include #include #include #include #include #include #include #include #include #include #define OPCM_EVENT "IA64_TAGGED_INST_RETIRED_IBRP0_PMC32_33" #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 #define MAX_PMU_NAME_LEN 32 #define NLOOP 200UL /* * we don't use static to make sure the compiler does not inline the function */ int do_test(unsigned long loop) { unsigned long sum = 0; while(loop--) sum += loop; return sum; } static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } int main(void) { pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_mont_input_param_t mont_inp; pfarg_pmd_t pd[NUM_PMDS]; pfarg_pmc_t pc[NUM_PMCS]; pfarg_ctx_t ctx; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; int ret; int type = 0; int id; unsigned int i; char name[MAX_EVT_NAME_LEN]; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) fatal_error("Can't initialize library\n"); /* * Let's make sure we run this on the right CPU */ pfm_get_pmu_type(&type); if (type != PFMLIB_MONTECITO_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with the %s PMU\n", model); } /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 1; /* set to 1 for verbose */ pfm_set_options(&pfmlib_options); memset(pd, 0, sizeof(pd)); memset(pc, 0, sizeof(pc)); memset(&ctx, 0, sizeof(ctx)); memset(&load_args, 0, sizeof(load_args)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&mont_inp,0, sizeof(mont_inp)); /* * We indicate that we are using the first opcode matcher (PMC32/PMC33). */ mont_inp.pfp_mont_opcm1.opcm_used = 1; /* * We want to match all the br.cloop in our test function. * This branch is an IP-relative branch for which the major * opcode (bits [40-37]) is 4 and the btype field (bits[6-8]) is 5. * We ignore all the other fields in the opcode. * * On Montecito, the opcode matcher covers the full 41 bits of each * instruction but we'll ignore them in this example. Hence the * match value is: * * match = (4<<37)| (5<<6) = 0x8000000140 * * On Montecito, the match field covers the full 41 bits of each instruction. * But for this example, we only care about the major and btype field, * and we ignore all other bits. When a bit is set in the mask it means * that the corresponding match bit value is a "don't care". A bit * with value of zero indicates that the corresponding match bit * must match. Hence we build the following mask: * * mask = ~((0xf<<37) | (0x3<<6)) = 0x1fffffff3f; * * The 0xf comes from the fact that major opcode is 4-bit wide. * The 0x3 comes from the fact that btype is 3-bit wide. */ mont_inp.pfp_mont_opcm1.opcm_b = 1; mont_inp.pfp_mont_opcm1.opcm_match = 0x8000000140; mont_inp.pfp_mont_opcm1.opcm_mask = 0x1fffffff3f; /* * To count the number of occurence of this instruction, we must * program a counting monitor with the IA64_TAGGED_INST_RETIRED_PMC8 * event. */ if (pfm_find_full_event(OPCM_EVENT, &inp.pfp_events[0]) != PFMLIB_SUCCESS) fatal_error("cannot find event %s\n", OPCM_EVENT); /* * set the privilege mode: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = 1; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, &mont_inp, &outp, NULL)) != PFMLIB_SUCCESS) fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); /* * now create the context for self monitoring/per-task */ id = pfm_create_context(&ctx, NULL, NULL, 0); if (id == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * Now prepare the argument to initialize the PMDs and PMCS. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * figure out pmd mapping from output pmc */ for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more thann coutning monitors. */ if (pfm_write_pmcs(id, pc, outp.pfp_pmc_count)) fatal_error("pfm_write_pmcs error errno %d\n",errno); if (pfm_write_pmds(id, pd, outp.pfp_pmd_count)) fatal_error("pfm_write_pmds error errno %d\n",errno); /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = getpid(); if (pfm_load_context(id, &load_args)) fatal_error("pfm_load_context error errno %d\n",errno); /* * Let's roll now. */ pfm_self_start(id); do_test(NLOOP); pfm_self_stop(id); /* * now read the results */ if (pfm_read_pmds(id, pd, inp.pfp_event_count)) fatal_error("pfm_read_pmds error errno %d\n",errno); /* * print the results */ pfm_get_full_event_name(&inp.pfp_events[0], name, MAX_EVT_NAME_LEN); printf("PMD%-3u %20lu %s (expected %lu)\n", pd[0].reg_num, pd[0].reg_value, name, NLOOP); if (pd[0].reg_value != 0) printf("compiler used br.cloop\n"); else printf("compiler did not use br.cloop\n"); /* * let's stop this now */ close(id); return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/ia64/ita_irr.c0000644000307100002310000002526513013651447022175 0ustar yarkhangraduate/* * ita_irr.c - example of how to use code range restriction with the Itanium PMU * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #include #define VECTOR_SIZE 1000000UL #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 #define MAX_PMU_NAME_LEN 32 typedef struct { char *event_name; unsigned long expected_value; } event_desc_t; static event_desc_t event_list[]={ { "fp_ops_retired_hi", 0UL} , { "fp_ops_retired_lo", VECTOR_SIZE<<1 }, { NULL, 0UL } }; static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } void saxpy(double *a, double *b, double *c, unsigned long size) { unsigned long i; for(i=0; i < size; i++) { c[i] = 2*a[i] + b[i]; } } void saxpy2(double *a, double *b, double *c, unsigned long size) { unsigned long i; for(i=0; i < size; i++) { c[i] = 2*a[i] + b[i]; } } static int do_test(void) { unsigned long size; double *a, *b, *c; size = VECTOR_SIZE; a = malloc(size*sizeof(double)); b = malloc(size*sizeof(double)); c = malloc(size*sizeof(double)); if (a == NULL || b == NULL || c == NULL) fatal_error("Cannot allocate vectors\n"); memset(a, 0, size*sizeof(double)); memset(b, 0, size*sizeof(double)); memset(c, 0, size*sizeof(double)); saxpy(a,b,c, size); saxpy2(a,b,c, size); return 0; } int main(int argc, char **argv) { event_desc_t *p; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_ita_input_param_t ita_inp; pfmlib_ita_output_param_t ita_outp; pfarg_pmd_t pd[NUM_PMDS]; pfarg_pmc_t pc[NUM_PMCS]; pfarg_pmc_t ibrs[8]; pfarg_ctx_t ctx[1]; pfarg_load_t load_args; unsigned long range_start, range_end; pfmlib_options_t pfmlib_options; struct fd { /* function descriptor */ unsigned long addr; unsigned long gp; } *fd; int ret, type = 0; unsigned int i; int id; char name[MAX_EVT_NAME_LEN]; /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) fatal_error("Cannot initialize library: %s\n", pfm_strerror(ret)); /* * Let's make sure we run this on the right CPU family */ pfm_get_pmu_type(&type); if (type != PFMLIB_ITANIUM_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with %s PMU\n", model); } /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 1; /* set to 1 for verbose */ pfm_set_options(&pfmlib_options); /* * Compute the range we are interested in * * On IA-64, the function pointer does not point directly * to the function but to a descriptor which contains two * unsigned long: the first one is the actual start address * of the function, the second is the gp (global pointer) * to load into r1 before jumping into the function. Unlesss * we're jumping into a shared library the gp is the same as * the current gp. * * In the artificial example, we also rely on the compiler/linker * NOT reordering code layout. We depend on saxpy2() being just * after saxpy(). * */ fd = (struct fd *)saxpy; range_start = fd->addr; fd = (struct fd *)saxpy2; range_end = fd->addr; /* * linker may reorder saxpy() and saxpy2() */ if (range_end < range_start) { unsigned long tmp; tmp = range_start; range_start = range_end; range_end = tmp; } memset(pd, 0, sizeof(pd)); memset(ctx, 0, sizeof(ctx)); memset(ibrs,0, sizeof(ibrs)); memset(&load_args,0, sizeof(load_args)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&ita_inp,0, sizeof(ita_inp)); memset(&ita_outp,0, sizeof(ita_outp)); /* * find requested event */ p = event_list; for (i=0; p->event_name ; i++, p++) { if (pfm_find_event(p->event_name, &inp.pfp_events[i].event) != PFMLIB_SUCCESS) { fatal_error("Cannot find %s event\n", p->event_name); } } /* * set the privilege mode: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = i; /* * We use the library to figure out how to program the debug registers * to cover the data range we are interested in. The rr_end parameter * must point to the byte after the last element of the range (C-style range). * * Because of the masking mechanism and therefore alignment constraints used to implement * this feature, it may not be possible to exactly cover a given range. It may be that * the coverage exceeds the desired range. So it is possible to capture noise if * the surrounding addresses are also heavily used. You can figure out by how much the * actual range is off compared to the requested range by checking the rr_soff and rr_eoff * fields of rr_infos on return from the library call. * * Upon return, the rr_dbr array is programmed and the number of debug registers (not pairs) * used to cover the range is in rr_nbr_used. * */ ita_inp.pfp_ita_irange.rr_used = 1; /* indicate we use code range restriction */ ita_inp.pfp_ita_irange.rr_limits[0].rr_start = range_start; ita_inp.pfp_ita_irange.rr_limits[0].rr_end = range_end; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, &ita_inp, &outp, &ita_outp)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); } /* * print offsets */ printf("code range : [0x%016lx-0x%016lx)\n" "start_offset:-0x%lx end_offset:+0x%lx\n" "%d pairs of debug registers used\n", range_start, range_end, ita_outp.pfp_ita_irange.rr_infos[0].rr_soff, ita_outp.pfp_ita_irange.rr_infos[0].rr_eoff, ita_outp.pfp_ita_irange.rr_nbr_used >> 1); /* * now create the context for self monitoring/per-task */ id = pfm_create_context(ctx, NULL, NULL, 0); if (id == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("cannot create PFM context %s\n", strerror(errno)); } /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events cause extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } for (i=0; i < outp.pfp_pmd_count; i++) { pd[i].reg_num = outp.pfp_pmds[i].reg_num; } /* * propagate the setup for the debug registers from the library to the arguments * to the syscall. The library does not know the type of the syscall * anymore. IBRs are mapped to PMC256-PMC263 */ for (i=0; i < ita_outp.pfp_ita_drange.rr_nbr_used; i++) { ibrs[i].reg_num = 256+ita_outp.pfp_ita_irange.rr_br[i].reg_num; ibrs[i].reg_value = ita_outp.pfp_ita_irange.rr_br[i].reg_value; } /* * Program the code debug registers. * * IMPORTANT: programming the debug register MUST always be done before the PMCs * otherwise the kernel will fail on PFM_WRITE_PMCS. This is for security reasons. */ if (pfm_write_pmcs(id, ibrs, ita_outp.pfp_ita_irange.rr_nbr_used) == -1) fatal_error("pfm_write_pmcs error errno %d\n",errno); /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more than coutning monitors. */ if (pfm_write_pmcs(id, pc, outp.pfp_pmc_count) == -1) fatal_error("pfm_write_pmcs error errno %d\n",errno); if (pfm_write_pmds(id, pd, outp.pfp_pmd_count) == -1) fatal_error("pfm_write_pmds error errno %d\n",errno); /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = getpid(); if (pfm_load_context(id, &load_args) == -1) { fatal_error("pfm_load_context error errno %d\n",errno); } /* * Let's roll now. * * We run two distinct copies of the same function but we restrict measurement * to the first one (saxpy). Therefore the expected count is half what you would * get if code range restriction was not used. The core loop in both case uses * two floating point operation per iteration. */ pfm_self_start(id); do_test(); pfm_self_stop(id); /* * now read the results */ if (pfm_read_pmds(id, pd, inp.pfp_event_count) == -1) { fatal_error("pfm_read_pmds error errno %d\n",errno); } /* * print the results * * It is important to realize, that the first event we specified may not * be in PMD4. Not all events can be measured by any monitor. That's why * we need to use the pc[] array to figure out where event i was allocated. */ for (i=0; i < inp.pfp_event_count; i++) { pfm_get_full_event_name(&inp.pfp_events[i], name, MAX_EVT_NAME_LEN); printf("PMD%-3u %20lu %s (expected %lu)\n", pd[i].reg_num, pd[i].reg_value, name, event_list[i].expected_value); } /* * let's stop this now */ close(id); return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/ia64/ita2_btb.c0000644000307100002310000003107713013651447022230 0ustar yarkhangraduate/* * ita2_btb.c - example of how use the BTB with the Itanium 2 PMU * * Copyright (c) 2003-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #include #include #include #include #include #include #include #include #include #include #include #include #include typedef pfm_dfl_smpl_hdr_t btb_hdr_t; typedef pfm_dfl_smpl_entry_t btb_entry_t; typedef pfm_dfl_smpl_arg_t smpl_arg_t; #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 #define MAX_PMU_NAME_LEN 32 /* * The BRANCH_EVENT is increment by 1 for each branch event. Such event is composed of * two entries in the BTB: a source and a target entry. The BTB is full after 4 branch * events. */ #define SMPL_PERIOD (4UL*256) static void *smpl_vaddr; static unsigned int entry_size; static int id; #define BPL (sizeof(uint64_t)<<3) #define LBPL 6 static inline void pfm_bv_set(uint64_t *bv, uint16_t rnum) { bv[rnum>>LBPL] |= 1UL << (rnum&(BPL-1)); } /* * we don't use static to make sure the compiler does not inline the function */ long func1(void) { return 0;} long do_test(unsigned long loop) { long sum = 0; while(loop--) { if (loop & 0x1) sum += func1(); else sum += loop; } return sum; } static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } /* * print content of sampling buffer * * XXX: using stdio to print from a signal handler is not safe with multi-threaded * applications */ #define safe_printf printf static void show_btb_reg(int j, pfm_ita2_pmd_reg_t reg, pfm_ita2_pmd_reg_t pmd16) { unsigned long bruflush, b1; int is_valid = reg.pmd8_15_ita2_reg.btb_b == 0 && reg.pmd8_15_ita2_reg.btb_mp == 0 ? 0 :1; b1 = (pmd16.pmd_val >> (4 + 4*(j-8))) & 0x1; bruflush = (pmd16.pmd_val >> (5 + 4*(j-8))) & 0x1; safe_printf("\tPMD%-2d: 0x%016lx b=%d mp=%d bru=%ld b1=%ld valid=%c\n", j, reg.pmd_val, reg.pmd8_15_ita2_reg.btb_b, reg.pmd8_15_ita2_reg.btb_mp, bruflush, b1, is_valid ? 'Y' : 'N'); if (!is_valid) return; if (reg.pmd8_15_ita2_reg.btb_b) { unsigned long addr; addr = (reg.pmd8_15_ita2_reg.btb_addr+b1)<<4; addr |= reg.pmd8_15_ita2_reg.btb_slot < 3 ? reg.pmd8_15_ita2_reg.btb_slot : 0; safe_printf("\t Source Address: 0x%016lx\n" "\t Taken=%c Prediction: %s\n\n", addr, reg.pmd8_15_ita2_reg.btb_slot < 3 ? 'Y' : 'N', reg.pmd8_15_ita2_reg.btb_mp ? "FE Failure" : bruflush ? "BE Failure" : "Success"); } else { safe_printf("\t Target Address: 0x%016lx\n\n", (unsigned long)(reg.pmd8_15_ita2_reg.btb_addr<<4)); } } static void show_btb(pfm_ita2_pmd_reg_t *btb, pfm_ita2_pmd_reg_t *pmd16) { int i, last; i = (pmd16->pmd16_ita2_reg.btbi_full) ? pmd16->pmd16_ita2_reg.btbi_bbi : 0; last = pmd16->pmd16_ita2_reg.btbi_bbi; safe_printf("btb_trace: i=%d last=%d bbi=%d full=%d\n", i, last,pmd16->pmd16_ita2_reg.btbi_bbi, pmd16->pmd16_ita2_reg.btbi_full); do { show_btb_reg(i+8, btb[i], *pmd16); i = (i+1) % 8; } while (i != last); } void process_smpl_buffer(void) { btb_hdr_t *hdr; btb_entry_t *ent; unsigned long pos; unsigned long smpl_entry = 0; pfm_ita2_pmd_reg_t *reg, *pmd16; unsigned long i; int ret; static unsigned long last_ovfl = ~0UL; hdr = (btb_hdr_t *)smpl_vaddr; /* * check that we are not diplaying the previous set of samples again. * Required to take care of the last batch of samples. */ if (hdr->hdr_overflows <= last_ovfl && last_ovfl != ~0UL) { printf("skipping identical set of samples %lu <= %lu\n", hdr->hdr_overflows, last_ovfl); return; } pos = (unsigned long)(hdr+1); /* * walk through all the entries recored in the buffer */ for(i=0; i < hdr->hdr_count; i++) { ret = 0; ent = (btb_entry_t *)pos; /* * print entry header */ safe_printf("Entry %ld PID:%d TID:%d CPU:%d STAMP:0x%lx IIP:0x%016lx\n", smpl_entry++, ent->tgid, ent->pid, ent->cpu, ent->tstamp, ent->ip); /* * point to first recorded register (always contiguous with entry header) */ reg = (pfm_ita2_pmd_reg_t*)(ent+1); /* * in this particular example, we have pmd8-pmd15 has the BTB. We have also * included pmd16 (BTB index) has part of the registers to record. This trick * allows us to get the index to decode the sequential order of the BTB. * * Recorded registers are always recorded in increasing order. So we know * that pmd16 is at a fixed offset (+8*sizeof(unsigned long)) from pmd8. */ pmd16 = reg+8; show_btb(reg, pmd16); /* * move to next entry */ pos += entry_size; } } static void overflow_handler(int n, struct siginfo *info, struct sigcontext *sc) { /* dangerous */ printf("Notification received\n"); process_smpl_buffer(); /* * And resume monitoring */ if (pfm_restart(id) == -1) { perror("pfm_restart"); exit(1); } } int main(void) { int ret; int type = 0; pfarg_pmd_t pd[NUM_PMDS]; pfarg_pmc_t pc[NUM_PMCS]; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_ita2_input_param_t ita2_inp; pfarg_ctx_t ctx; smpl_arg_t buf_arg; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; struct sigaction act; unsigned int i; /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) fatal_error("Cannot initialize library: %s\n", pfm_strerror(ret)); /* * Let's make sure we run this on the right CPU */ pfm_get_pmu_type(&type); if (type != PFMLIB_ITANIUM2_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with %s PMU\n", model); } /* * Install the overflow handler (SIGIO) */ memset(&act, 0, sizeof(act)); act.sa_handler = (sig_t)overflow_handler; sigaction (SIGIO, &act, 0); /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 1; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); memset(pd, 0, sizeof(pd)); memset(&ctx, 0, sizeof(ctx)); memset(&buf_arg, 0, sizeof(buf_arg)); /* * prepare parameters to library. we don't use any Itanium * specific features here. so the pfp_model is NULL. */ memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&ita2_inp,0, sizeof(ita2_inp)); /* * Before calling pfm_find_dispatch(), we must specify what kind * of branches we want to capture. We are interested in all the * mispredicted (target, taken/not taken) branches, therefore we * program the various fields of the BTB config to: */ ita2_inp.pfp_ita2_btb.btb_used = 1; ita2_inp.pfp_ita2_btb.btb_ds = 0; /* capture target */ ita2_inp.pfp_ita2_btb.btb_tm = 0x3; /* all branches */ ita2_inp.pfp_ita2_btb.btb_ptm = 0x1; /* target mispredicted */ ita2_inp.pfp_ita2_btb.btb_ppm = 0x1; /* mispredicted path */ ita2_inp.pfp_ita2_btb.btb_brt = 0x0; /* all types captured */ ita2_inp.pfp_ita2_btb.btb_plm = PFM_PLM3; if (pfm_find_full_event("BRANCH_EVENT", &inp.pfp_events[0]) != PFMLIB_SUCCESS) { fatal_error("cannot find event BRANCH_EVENT\n"); } /* * set the (global) privilege mode: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = 1; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, &ita2_inp, &outp, NULL)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); } /* * the size of the buffer is indicated in bytes (not entries). * * The kernel will record into the buffer up to a certain point. * No partial samples are ever recorded. */ buf_arg.buf_size = getpagesize(); /* * now create the context for self monitoring/per-task */ id = pfm_create_context(&ctx, "default", &buf_arg, sizeof(buf_arg)); if (id == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * retrieve the virtual address at which the sampling * buffer has been mapped */ smpl_vaddr = mmap(NULL, (size_t)buf_arg.buf_size, PROT_READ, MAP_PRIVATE, id, 0); if (smpl_vaddr == MAP_FAILED) fatal_error("cannot mmap sampling buffer errno %d\n", errno); printf("Sampling buffer mapped at %p\n", smpl_vaddr); /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events cause extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * figure out pmd mapping from output pmc * PMD16 is part of the set of used PMD returned by libpfm. * It will be reset automatically */ for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * indicate we want notification when buffer is full */ pd[0].reg_flags |= PFM_REGFL_OVFL_NOTIFY; /* * Now prepare the argument to initialize the PMD and the sampling period * We know we use only one PMD in this case, therefore pmd[0] corresponds * to our first event which is our sampling period. */ pd[0].reg_value = - SMPL_PERIOD; pd[0].reg_long_reset = - SMPL_PERIOD; pd[0].reg_short_reset = - SMPL_PERIOD; pfm_bv_set(pd[0].reg_smpl_pmds, 16); entry_size = sizeof(btb_entry_t) + 1 * 8; for(i=8; i < 16; i++) { pfm_bv_set(pd[0].reg_smpl_pmds, i); entry_size += 8; } /* * When our counter overflows, we want to BTB index to be reset, so that we keep * in sync. This is required to make it possible to interpret pmd16 on overflow * to avoid repeating the same branch several times. */ pfm_bv_set(pd[0].reg_reset_pmds, 16); /* * Now program the registers */ if (pfm_write_pmcs(id, pc, outp.pfp_pmc_count) == -1) fatal_error("pfm_write_pmcs error errno %d\n",errno); if (pfm_write_pmds(id, pd, outp.pfp_pmd_count) == -1) fatal_error("pfm_write_pmds error errno %d\n",errno); /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = getpid(); if (pfm_load_context(id, &load_args) == -1) fatal_error("pfm_load_context error errno %d\n",errno); /* * setup asynchronous notification on the file descriptor */ ret = fcntl(id, F_SETFL, fcntl(id, F_GETFL, 0) | O_ASYNC); if (ret == -1) fatal_error("cannot set ASYNC: %s\n", strerror(errno)); /* * get ownership of the descriptor */ ret = fcntl(id, F_SETOWN, getpid()); if (ret == -1) fatal_error("cannot setown: %s\n", strerror(errno)); /* * Let's roll now. */ pfm_self_start(id); do_test(100000); pfm_self_stop(id); /* * We must call the processing routine to cover the last entries recorded * in the sampling buffer. Note that the buffer may not be full at this point. * */ process_smpl_buffer(); /* * let's stop this now */ munmap(smpl_vaddr, (size_t)buf_arg.buf_size); close(id); return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/ia64/ita2_opcode.c0000644000307100002310000002023213013651447022721 0ustar yarkhangraduate/* * ita2_opcode.c - example of how to use the opcode matcher with the Itanium2 PMU * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux/ia64. */ #include #include #include #include #include #include #include #include #include #include #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 #define MAX_PMU_NAME_LEN 32 /* * we don't use static to make sure the compiler does not inline the function */ int do_test(unsigned long loop) { unsigned long sum = 0; while(loop--) sum += loop; return sum; } static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } int main(void) { pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_ita2_input_param_t ita2_inp; pfarg_pmd_t pd[NUM_PMDS]; pfarg_pmc_t pc[NUM_PMCS]; pfarg_ctx_t ctx[1]; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; int ret; int type = 0; int id; unsigned int i; char name[MAX_EVT_NAME_LEN]; /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) fatal_error("Cannot initialize library: %s\n", pfm_strerror(ret)); /* * Let's make sure we run this on the right CPU */ pfm_get_pmu_type(&type); if (type != PFMLIB_ITANIUM2_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with the %s PMU\n", model); } /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 0; /* set to 1 for verbose */ pfm_set_options(&pfmlib_options); memset(pd, 0, sizeof(pd)); memset(pc, 0, sizeof(pc)); memset(ctx, 0, sizeof(ctx)); memset(&load_args, 0, sizeof(load_args)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&ita2_inp,0, sizeof(ita2_inp)); /* * We indicate that we are using the PMC8 opcode matcher. This is required * otherwise the library add PMC8 to the list of PMC to pogram during * pfm_dispatch_events(). */ ita2_inp.pfp_ita2_pmc8.opcm_used = 1; /* * We want to match all the br.cloop in our test function. * This branch is an IP-relative branch for which the major * opcode (bits [40-37]=4) and the btype field is 5 (which represents * bits[6-8]) so it is included in the match/mask fields of PMC8. * It is necessarily in a B slot. * * We don't care which operands are used with br.cloop therefore * the mask field of pmc8 is set such that only the 4 bits of the * opcode and 3 bits of btype must match exactly. This is accomplished by * clearing the top 4 bits and bits [6-8] of the mask field and setting the * remaining bits. Similarly, the match field only has the opcode value and btype * set according to the encoding of br.cloop, the * remaining bits are zero. Bit 60 of PMC8 is set to indicate * that we look only in B slots (this is the only possibility for * this instruction anyway). * * So the binary representation of the value for PMC8 is as follows: * * 6666555555555544444444443333333333222222222211111111110000000000 * 3210987654321098765432109876543210987654321098765432109876543210 * ---------------------------------------------------------------- * 0001010000000000000000101000000000000011111111111111000111111000 * * which yields a value of 0x1400028003fff1f8. * * Depending on the level of optimization to compile this code, it may * be that the count reported could be zero, if the compiler uses a br.cond * instead of br.cloop. * * * The 0x1 sets the ig_ad field to make sure we ignore any range restriction. * Also bit 2 must always be set */ ita2_inp.pfp_ita2_pmc8.pmc_val = 0x1400028003fff1fa; /* * To count the number of occurence of this instruction, we must * program a counting monitor with the IA64_TAGGED_INST_RETIRED_PMC8 * event. */ if (pfm_find_full_event("IA64_TAGGED_INST_RETIRED_IBRP0_PMC8", &inp.pfp_events[0]) != PFMLIB_SUCCESS) fatal_error("cannot find event IA64_TAGGED_INST_RETIRED_IBRP0_PMC8\n"); /* * set the privilege mode: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = 1; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, &ita2_inp, &outp, NULL)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); } /* * now create the context for self monitoring/per-task */ id = pfm_create_context(ctx, NULL, NULL, 0); if (id == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events causes extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * figure out pmd mapping from output pmc */ for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more thann coutning monitors. */ if (pfm_write_pmcs(id, pc, outp.pfp_pmc_count) == -1) fatal_error("pfm_write_pmcs error errno %d\n",errno); if (pfm_write_pmds(id, pd, outp.pfp_pmd_count) == -1) fatal_error("pfm_write_pmds error errno %d\n",errno); /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = getpid(); if (pfm_load_context(id, &load_args) == -1) { fatal_error("pfm_load_context error errno %d\n",errno); } /* * Let's roll now. */ pfm_self_start(id); do_test(100UL); pfm_self_stop(id); /* * now read the results */ if (pfm_read_pmds(id, pd, inp.pfp_event_count) == -1) { fatal_error("pfm_read_pmds error errno %d\n",errno); } /* * print the results */ pfm_get_full_event_name(&inp.pfp_events[0], name, MAX_EVT_NAME_LEN); printf("PMD%-3u %20lu %s\n", pd[0].reg_num, pd[0].reg_value, name); if (pd[0].reg_value != 0) printf("compiler used br.cloop\n"); else printf("compiler did not use br.cloop\n"); /* * let's stop this now */ close(id); return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/ia64/mont_rr.c0000644000307100002310000002555713013651447022230 0ustar yarkhangraduate/* * mont_rr.c - example of how to use data range restriction with the Itanium 3 PMU * * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #include #include #include #include #include #include #include #include #include #include #if defined(__ECC) && defined(__INTEL_COMPILER) /* if you do not have this file, your compiler is too old */ #include #define clear_psr_ac() __rum(1UL<<3) #elif defined(__GNUC__) static inline void clear_psr_ac(void) { __asm__ __volatile__("rum psr.ac;;" ::: "memory" ); } #else #error "You need to define clear_psr_ac() for your compiler" #endif #define TEST_DATA_COUNT 16 #define N_LOOP 100000000UL #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 #define MAX_PMU_NAME_LEN 32 /* * here we capture only misaligned_loads because it cannot * be measured with misaligned_stores_retired at the same time */ static char *event_list[]={ "misaligned_loads_retired", NULL }; typedef union { unsigned long l_tab[2]; unsigned int i_tab[4]; unsigned short s_tab[8]; unsigned char c_tab[16]; } test_data_t; static int do_test(test_data_t *data) { unsigned int *l, v; l = (unsigned int *)(data->c_tab+1); if (((unsigned long)l & 0x1) == 0) { printf("Data is not unaligned, can't run test\n"); return -1; } v = *l; v++; *l = v; return 0; } static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } int main(int argc, char **argv) { char **p; test_data_t *test_data, *test_data_fake; unsigned long range_start, range_end; int ret, type = 0; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_mont_input_param_t mont_inp; pfmlib_mont_output_param_t mont_outp; pfarg_pmd_t pd[NUM_PMDS]; pfarg_pmc_t pc[NUM_PMCS]; pfarg_ctx_t ctx; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; unsigned int i; int id, num_pmcs = 0; char name[MAX_EVT_NAME_LEN]; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) fatal_error("Can't initialize library\n"); /* * Let's make sure we run this on the right CPU family */ pfm_get_pmu_type(&type); if (type != PFMLIB_MONTECITO_PMU) { char model[MAX_PMU_NAME_LEN]; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); fatal_error("this program does not work with %s PMU\n", model); } /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 1; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); /* * now let's allocate the data structure we will be monitoring */ test_data = (test_data_t *)malloc(sizeof(test_data_t)*TEST_DATA_COUNT); if (test_data == NULL) fatal_error("cannot allocate test data structure"); test_data_fake = (test_data_t *)malloc(sizeof(test_data_t)*TEST_DATA_COUNT); if (test_data_fake == NULL) fatal_error("cannot allocate test data structure"); /* * Compute the range we are interested in */ range_start = (unsigned long)test_data; range_end = range_start + sizeof(test_data_t)*TEST_DATA_COUNT; memset(pd, 0, sizeof(pd)); memset(pc, 0, sizeof(pc)); memset(&ctx, 0, sizeof(ctx)); memset(&load_args, 0, sizeof(load_args)); /* * prepare parameters to library. we don't use any Itanium * specific features here. so the pfp_model is NULL. */ memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&mont_inp,0, sizeof(mont_inp)); memset(&mont_outp,0, sizeof(mont_outp)); /* * find requested event */ p = event_list; for (i=0; *p ; i++, p++) { if (pfm_find_event(*p, &inp.pfp_events[i].event) != PFMLIB_SUCCESS) { fatal_error("Cannot find %s event\n", *p); } } /* * set the privilege mode: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ inp.pfp_event_count = i; /* * We use the library to figure out how to program the debug registers * to cover the data range we are interested in. The rr_end parameter * must point to the byte after the last element of the range (C-style range). * * Because of the masking mechanism and therefore alignment constraints used to implement * this feature, it may not be possible to exactly cover a given range. It may be that * the coverage exceeds the desired range. So it is possible to capture noise if * the surrounding addresses are also heavily used. You can figure out by how much the * actual range is off compared to the requested range by checking the rr_soff and rr_eoff * fields in rr_infos on return from the library call. * * Upon return, the rr_dbr array is programmed and the number of debug registers (not pairs) * used to cover the range is in rr_nbr_used. */ mont_inp.pfp_mont_drange.rr_used = 1; mont_inp.pfp_mont_drange.rr_limits[0].rr_start = range_start; mont_inp.pfp_mont_drange.rr_limits[0].rr_end = range_end; /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, &mont_inp, &outp, &mont_outp)) != PFMLIB_SUCCESS) fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); printf("data range : [0x%016lx-0x%016lx): %d pair of debug registers used\n" "start_offset:-0x%lx end_offset:+0x%lx\n", range_start, range_end, mont_outp.pfp_mont_drange.rr_nbr_used >> 1, mont_outp.pfp_mont_drange.rr_infos[0].rr_soff, mont_outp.pfp_mont_drange.rr_infos[0].rr_eoff); printf("fake data range: [0x%016lx-0x%016lx)\n", (unsigned long)test_data_fake, (unsigned long)test_data_fake+sizeof(test_data_t)*TEST_DATA_COUNT); /* * now create the context for self monitoring/per-task */ id = pfm_create_context(&ctx, NULL, NULL, 0); if (id == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events causes extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++, num_pmcs++) { pc[num_pmcs].reg_num = outp.pfp_pmcs[i].reg_num; pc[num_pmcs].reg_value = outp.pfp_pmcs[i].reg_value; } /* * propagate the setup for the data debug registers. DBRS are mapped * at PMC264-PMC271 */ for (i=0; i < mont_outp.pfp_mont_drange.rr_nbr_used; i++, num_pmcs++) { pc[num_pmcs].reg_num = 264+mont_outp.pfp_mont_drange.rr_br[i].reg_num; pc[num_pmcs].reg_value = mont_outp.pfp_mont_drange.rr_br[i].reg_value; } /* * figure out pmd mapping from output pmc */ for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more than coutning monitors. */ if (pfm_write_pmcs(id, pc, num_pmcs)) fatal_error("child: pfm_write_pmcs error errno %d\n",errno); if (pfm_write_pmds(id, pd, outp.pfp_pmd_count)) fatal_error( "child: pfm_write_pmds error errno %d\n",errno); /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = getpid(); if (pfm_load_context(id, &load_args)) fatal_error("pfm_load_context error errno %d\n",errno); /* * Let's make sure that the hardware does the unaligned accesses (do not use the * kernel software handler otherwise the PMU won't see the unaligned fault). */ clear_psr_ac(); /* * Let's roll now. * * The idea behind this test is to have two dynamically allocated data structures * which are access in a unaligned fashion. But we want to capture only the unaligned * accesses on one of the two. So the debug registers are programmed to cover the * first one ONLY. Then we activate monotoring and access the two data structures. * This is an artificial example just to demonstrate how to use data address range * restrictions. */ pfm_self_start(id); for(i=0; i < N_LOOP; i++) { do_test(test_data); do_test(test_data_fake); } pfm_self_stop(id); /* * now read the results */ if (pfm_read_pmds(id, pd, inp.pfp_event_count)) fatal_error("pfm_read_pmds error errno %d\n",errno); /* * print the results * * It is important to realize, that the first event we specified may not * be in PMD4. Not all events can be measured by any monitor. That's why * we need to use the pc[] array to figure out where event i was allocated. * * For this example, we expect to see a value of 1 for misaligned loads. * But it can be two when the test_data and test_data_fake * are allocated very close from each other and the range created with the debug * registers is larger then test_data. * */ for (i=0; i < inp.pfp_event_count; i++) { pfm_get_full_event_name(&inp.pfp_events[i], name, MAX_EVT_NAME_LEN); printf("PMD%-3u %20lu %s (expected %lu)\n", pd[i].reg_num, pd[i].reg_value, name, N_LOOP); if (pd[i].reg_value != N_LOOP) { printf("error: Result should be 1 for %s\n", name); break; } } /* * let's stop this now */ close(id); free(test_data); free(test_data_fake); return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/task_attach_timeout.c0000644000307100002310000002327613013651447024035 0ustar yarkhangraduate/* * task_attach_timeout.c - attach to another task for monitoring for a short while * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "detect_pmcs.h" #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } int parent(pid_t pid, unsigned long delay) { pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfarg_ctx_t ctx[1]; pfarg_pmc_t pc[NUM_PMCS]; pfarg_pmd_t pd[NUM_PMDS]; pfarg_load_t load_args; struct pollfd pollfd; pfarg_msg_t msg; unsigned int i, num_counters; int status, ret; int ctx_fd; char name[MAX_EVT_NAME_LEN]; memset(pc, 0, sizeof(pc)); memset(pd, 0, sizeof(pd)); memset(ctx, 0, sizeof(ctx)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&load_args,0, sizeof(load_args)); pfm_get_num_counters(&num_counters); if (pfm_get_cycle_event(&inp.pfp_events[0]) != PFMLIB_SUCCESS) { fatal_error("cannot find cycle event\n"); } if (pfm_get_inst_retired_event(&inp.pfp_events[1]) != PFMLIB_SUCCESS) { fatal_error("cannot find inst retired event\n"); } i = 2; /* * set the privilege mode: * PFM_PLM3 : user level * PFM_PLM0 : kernel level */ inp.pfp_dfl_plm = PFM_PLM3; if (i > num_counters) { i = num_counters; printf("too many events provided (max=%d events), using first %d event(s)\n", num_counters, i); } /* * how many counters we use */ inp.pfp_event_count = i; /* * now create a context. we will later attach it to the task we are creating. */ ctx_fd = pfm_create_context(ctx, NULL, NULL, 0); if (ctx_fd == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * build the pfp_unavail_pmcs bitmask by looking * at what perfmon has available. It is not always * the case that all PMU registers are actually available * to applications. For instance, on IA-32 platforms, some * registers may be reserved for the NMI watchdog timer. * * With this bitmap, the library knows which registers NOT to * use. Of source, it is possible that no valid assignement may * be possible if certina PMU registers are not available. */ detect_unavail_pmcs(ctx_fd, &inp.pfp_unavail_pmcs); /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); } /* * use our file descriptor for the poll. * we are interested in read events only. */ pollfd.fd = ctx_fd; pollfd.events = POLLIN; /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events causes extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more thann counting monitors. */ if (pfm_write_pmcs(ctx_fd, pc, outp.pfp_pmc_count) == -1) fatal_error("pfm_write_pmcs error errno %d\n",errno); /* * To be read, each PMD must be either written or declared * as being part of a sample (reg_smpl_pmds) */ if (pfm_write_pmds(ctx_fd, pd, outp.pfp_pmd_count) == -1) fatal_error("pfm_write_pmds error errno %d\n",errno); ret = ptrace(PTRACE_ATTACH, pid, NULL, 0); if (ret == -1) { fatal_error("cannot attach to %d: %s\n", pid, strerror(errno)); } /* * wait for the child to be actually stopped */ waitpid(pid, &status, WUNTRACED); /* * check if process exited early */ if (WIFEXITED(status)) { fatal_error("command process %d exited too early with status %d\n", pid, WEXITSTATUS(status)); } /* * the task is stopped at this point */ /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = pid; if (pfm_load_context(ctx_fd, &load_args) == -1) { fatal_error("pfm_load_context error errno %d\n",errno); } /* * activate monitoring. The task is still STOPPED at this point. Monitoring * will not take effect until the execution of the task is resumed. */ if (pfm_start(ctx_fd, NULL) == -1) { fatal_error("pfm_start error errno %d\n",errno); } /* * now resume execution of the task, effectively activating * monitoring. */ ptrace(PTRACE_DETACH, pid, NULL, 0); printf("attached to [%d], timeout set to %lu seconds\n", pid, delay); /* * now the task is running */ /* * We cannot simply do a waitpid() because we may be attaching to a process * totally unrelated to our program. Instead we use a perfmon facility that * notifies us when the monitoring task is exiting. * * When a task with a monitoring context attached to it exits, a PFM_MSG_END * is generated. It can be retrieve with a simple read() on the context's descriptor. * * Another reason why you might return from the read is if there was a counter * overflow, unlikely in this example. * * To measure only for short period of time, use select or poll with a timeout, * see task_attach_timeout.c * */ ret = poll(&pollfd, 1, delay*1000); switch( ret ) { case -1: fatal_error("cannot read from descriptor: %s\n", strerror(errno)); /* no return */ case 1: /* * there is a message, i.e., the program exited before our timeout */ if (ret == 1) { /* * extract message */ ret = read(ctx_fd, &msg, sizeof(msg)); if (msg.type != PFM_MSG_END) { fatal_error("unexpected msg type : %d\n", msg.type); } } break; case 0: /* * we timed out, we need to stop the task to unload */ ret = ptrace(PTRACE_ATTACH, pid, NULL, 0); if (ret == -1) { fatal_error("cannot attach to %d: %s\n", pid, strerror(errno)); } /* * wait for task to be actually stopped */ waitpid(pid, &status, WUNTRACED); /* * check if process exited, then no need to unload */ if (WIFEXITED(status)) goto read_results; if (pfm_unload_context(ctx_fd) == -1) { fatal_error("pfm_unload_context error errno %d\n",errno); } /* * let it run free again */ ptrace(PTRACE_DETACH, pid, NULL, 0); break; default: fatal_error("unexpected return from poll: %d\n", ret); } read_results: /* * now simply read the results. */ if (pfm_read_pmds(ctx_fd, pd, inp.pfp_event_count) == -1) { fatal_error("pfm_read_pmds error errno %d\n",errno); return -1; } /* * print the results * * It is important to realize, that the first event we specified may not * be in PMD4. Not all events can be measured by any monitor. That's why * we need to use the pc[] array to figure out where event i was allocated. * */ for (i=0; i < inp.pfp_event_count; i++) { pfm_get_full_event_name(&inp.pfp_events[i], name, MAX_EVT_NAME_LEN); printf("PMD%-3u %20"PRIu64" %s\n", pd[i].reg_num, pd[i].reg_value, name); } /* * free the context */ close(ctx_fd); return 0; } int main(int argc, char **argv) { pfmlib_options_t pfmlib_options; unsigned long delay; pid_t pid; int ret; if (argc < 2) fatal_error("usage: %s pid [timeout]\n", argv[0]); pid = atoi(argv[1]); delay = argc > 2 ? strtoul(argv[2], NULL, 10) : 10; /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) fatal_error("Cannot initialize library: %s\n", pfm_strerror(ret)); return parent(pid, delay); } papi-5.5.1/src/libpfm-3.y/examples_v2.x/Makefile0000644000307100002310000000565713013651447021300 0ustar yarkhangraduate# # Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. # Contributed by Stephane Eranian # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies # of the Software, and to permit persons to whom the Software is furnished to do so, # subject to the following conditions: # # The above copyright notice and this permission notice shall be included in all # copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, # INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A # PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT # HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF # CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE # OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # TOPDIR := $(shell if [ "$$PWD" != "" ]; then echo $$PWD; else pwd; fi)/.. include $(TOPDIR)/config.mk include $(TOPDIR)/rules.mk DIRS= ifeq ($(ARCH),ia64) DIRS +=ia64 endif ifeq ($(ARCH),ia32) DIRS +=x86 endif ifeq ($(ARCH),x86_64) DIRS +=x86 endif ifeq ($(CONFIG_PFMLIB_ARCH_CRAYXT),y) CFLAGS += -DCONFIG_PFMLIB_ARCH_CRAYXT endif CFLAGS+= -I. -D_GNU_SOURCE LIBS += -lm ifeq ($(SYS),Linux) CFLAGS+= -pthread LIBS += -lrt endif TARGET_GEN=showevtinfo check_events ifeq ($(SYS),Linux) TARGET_LINUX +=self task task_attach task_attach_timeout syst \ notify_self notify_self2 notify_self3 \ multiplex multiplex2 set_notify whichpmu \ showreginfo task_smpl task_smpl_user \ pfmsetup self_smpl_multi self_pipe \ notify_self_fork self_smpl \ task_attach_timeout_np syst_np syst_multi_np XTRA += rtop endif all: $(TARGET_GEN) $(TARGET_LINUX) $(XTRA) @set -e ; for d in $(DIRS) ; do $(MAKE) -C $$d $@ ; done # Many systems don't have ncurses installed rtop: rtop.o detect_pmcs.o $(PFMLIB) -$(CC) $(CFLAGS) $(LDFLAGS) -D_GNU_SOURCE -o $@ $^ $(LIBS) -lpthread -lncurses $(TARGET_LINUX): %:%.o detect_pmcs.o $(PFMLIB) $(CC) $(CFLAGS) -o $@ $(LDFLAGS) $^ $(LIBS) $(TARGET_GEN): %:%.o $(PFMLIB) $(CC) $(CFLAGS) -o $@ $(LDFLAGS) $^ $(LIBS) clean: @set -e ; for d in $(DIRS) ; do $(MAKE) -C $$d $@ ; done $(RM) -f *.o $(TARGET_LINUX) $(TARGET_GEN) $(XTRA) *~ distclean: clean install_examples: $(TARGET_LINUX) $(TARGET_GEN) install_examples: @echo installing: $(TARGET_LINUX) $(TARGET_GEN) -mkdir -p $(DESTDIR)$(EXAMPLESDIR)/v2 $(INSTALL) -m 755 $(TARGET_LINUX) $(TARGET_GEN) $(DESTDIR)$(EXAMPLESDIR)/v2 @set -e ; for d in $(DIRS) ; do $(MAKE) -C $$d $@ ; done # # examples are installed as part of the RPM install, typically in /usr/share/doc/libpfm-X.Y/ # papi-5.5.1/src/libpfm-3.y/examples_v2.x/task_attach_timeout_np.c0000644000307100002310000001654613013651447024534 0ustar yarkhangraduate/* * task_attach_timeout_np.c - attach to another task without ptrace() * * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Based on: * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "detect_pmcs.h" #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 int parent(pid_t pid, unsigned long delay) { pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfarg_ctx_t ctx[1]; pfarg_pmc_t pc[NUM_PMCS]; pfarg_pmd_t pd[NUM_PMDS]; uint64_t prev_pd[NUM_PMDS]; pfarg_load_t load_args; pfarg_msg_t msg; unsigned int i, num_counters; int ret; int ctx_fd; char name[MAX_EVT_NAME_LEN]; memset(pc, 0, sizeof(pc)); memset(pd, 0, sizeof(pd)); memset(ctx, 0, sizeof(ctx)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&load_args,0, sizeof(load_args)); memset(prev_pd,0, sizeof(prev_pd)); pfm_get_num_counters(&num_counters); if (pfm_get_cycle_event(&inp.pfp_events[0]) != PFMLIB_SUCCESS) errx(1, "cannot find cycle event\n"); if (pfm_get_inst_retired_event(&inp.pfp_events[1]) != PFMLIB_SUCCESS) errx(1, "cannot find inst retired event\n"); i = 2; /* * set the privilege mode: * PFM_PLM3 : user level * PFM_PLM0 : kernel level */ inp.pfp_dfl_plm = PFM_PLM3; if (i > num_counters) { i = num_counters; printf("too many events provided (max=%d events), using first %d event(s)\n", num_counters, i); } /* * how many counters we use */ inp.pfp_event_count = i; /* * now create a context. we will later attach it to the task we are creating. */ ctx_fd = pfm_create_context(ctx, NULL, NULL, 0); if (ctx_fd == -1) { if (errno == ENOSYS) errx(1, "your kernel does not have performance monitoring support!\n"); err(1, "cannot create PFM context"); } /* * build the pfp_unavail_pmcs bitmask by looking * at what perfmon has available. It is not always * the case that all PMU registers are actually available * to applications. For instance, on IA-32 platforms, some * registers may be reserved for the NMI watchdog timer. * * With this bitmap, the library knows which registers NOT to * use. Of source, it is possible that no valid assignement may * be possible if certina PMU registers are not available. */ detect_unavail_pmcs(ctx_fd, &inp.pfp_unavail_pmcs); /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) errx(1, "cannot configure events: %s\n", pfm_strerror(ret)); /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events causes extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more thann counting monitors. */ if (pfm_write_pmcs(ctx_fd, pc, outp.pfp_pmc_count)) err(1, "pfm_write_pmcs error"); /* * To be read, each PMD must be either written or declared * as being part of a sample (reg_smpl_pmds) */ if (pfm_write_pmds(ctx_fd, pd, outp.pfp_pmd_count)) err(1, "pfm_write_pmds error"); /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = pid; if (pfm_load_context(ctx_fd, &load_args)) err(1, "pfm_load_context"); /* * activate monitoring. The task is still STOPPED at this point. Monitoring * will not take effect until the execution of the task is resumed. */ if (pfm_start(ctx_fd, NULL)) err(1, "pfm_start"); /* * now resume execution of the task, effectively activating * monitoring. */ printf("attached to [%d], timeout set to %lu seconds\n", pid, delay); /* * we wil be polling on the context fd, so enable non-blocking mode */ ret = fcntl(ctx_fd, F_SETFL, fcntl(ctx_fd, F_GETFL) | O_NONBLOCK); if (ret) errx(1, "fcntl"); for(;delay--;) { sleep(1); /* * read the results, no stopping necessary */ if (pfm_read_pmds(ctx_fd, pd, inp.pfp_event_count)) err(1, "pfm_read_pmds"); /* * print the results */ for (i=0; i < inp.pfp_event_count; i++) { pfm_get_full_event_name(&inp.pfp_events[i], name, MAX_EVT_NAME_LEN); printf("PMD%-3u %20"PRIu64" %s\n", pd[i].reg_num, pd[i].reg_value - prev_pd[i], name); prev_pd[i] = pd[i].reg_value; } /* * check if task has exited */ ret = read(ctx_fd, &msg, sizeof(msg)); if (ret == sizeof(msg)) { if (msg.type != PFM_MSG_END) errx(1, "unexpected msg type : %d\n", msg.type); printf("[%d] terminated\n", pid); goto done; } } if (pfm_unload_context(ctx_fd)) err(1, "pfm_unload_context"); printf("detached from [%d]\n", pid); done: /* * free the context */ close(ctx_fd); return 0; } int main(int argc, char **argv) { pfmlib_options_t pfmlib_options; unsigned long delay; pid_t pid; int ret; if (argc < 2) errx(1, "usage: %s pid [timeout]\n", argv[0]); pid = atoi(argv[1]); delay = argc > 2 ? strtoul(argv[2], NULL, 10) : 10; /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) errx(1, "cannot initialize library: %s\n", pfm_strerror(ret)); return parent(pid, delay); } papi-5.5.1/src/libpfm-3.y/examples_v2.x/task.c0000644000307100002310000001730313013651447020735 0ustar yarkhangraduate/* * task.c - example of a task monitoring another one * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include "detect_pmcs.h" #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS #define MAX_EVT_NAME_LEN 128 static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } int child(char **arg) { /* * will cause the program to stop before executing the first * user level instruction. We can only attach (load) a context * if the task is in the STOPPED state. */ ptrace(PTRACE_TRACEME, 0, NULL, NULL); /* * execute the requested command */ execvp(arg[0], arg); fatal_error("cannot exec: %s\n", arg[0]); /* not reached */ } int parent(char **arg) { pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfarg_ctx_t ctx[1]; pfarg_pmc_t pc[NUM_PMCS]; pfarg_pmd_t pd[NUM_PMDS]; pfarg_load_t load_args; unsigned int i, num_counters; int status, ret; int ctx_fd; pid_t pid; char name[MAX_EVT_NAME_LEN]; memset(pc, 0, sizeof(pc)); memset(pd, 0, sizeof(pd)); memset(ctx, 0, sizeof(ctx)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(&load_args,0, sizeof(load_args)); pfm_get_num_counters(&num_counters); if (pfm_get_cycle_event(&inp.pfp_events[0]) != PFMLIB_SUCCESS) fatal_error("cannot find cycle event\n"); if (pfm_get_inst_retired_event(&inp.pfp_events[1]) != PFMLIB_SUCCESS) fatal_error("cannot find inst retired event\n"); i = 2; /* * set the privilege mode: * PFM_PLM3 : user level * PFM_PLM0 : kernel level */ inp.pfp_dfl_plm = PFM_PLM3; /* * how many counters we use */ if (num_counters < i) { i = num_counters; printf("too many events provided (max=%d events), using first %d event(s)\n", num_counters, i); } inp.pfp_event_count = i; /* * now create a context. we will later attach it to the task we are creating. */ ctx_fd = pfm_create_context(ctx, NULL, NULL, 0); if (ctx_fd == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * build the pfp_unavail_pmcs bitmask by looking * at what perfmon has available. It is not always * the case that all PMU registers are actually available * to applications. For instance, on IA-32 platforms, some * registers may be reserved for the NMI watchdog timer. * * With this bitmap, the library knows which registers NOT to * use. Of source, it is possible that no valid assignement may * be possible if certina PMU registers are not available. */ detect_unavail_pmcs(ctx_fd, &inp.pfp_unavail_pmcs); /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); } /* * Now prepare the argument to initialize the PMDs and PMCS. * We use pfp_pmc_count to determine the number of PMC to intialize. * We use pfp_pmd_count to determine the number of PMD to initialize. * Some events/features may cause extra PMCs to be used, leading to: * - pfp_pmc_count may be >= pfp_event_count * - pfp_pmd_count may be >= pfp_event_count */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } for(i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * Now program the registers */ if (pfm_write_pmcs(ctx_fd, pc, outp.pfp_pmc_count) == -1) fatal_error("pfm_write_pmcs error errno %d\n",errno); if (pfm_write_pmds(ctx_fd, pd, outp.pfp_pmd_count) == -1) fatal_error("pfm_write_pmds error errno %d\n",errno); /* * Create the child task */ if ((pid=fork()) == -1) fatal_error("Cannot fork process\n"); /* * and launch the child code */ if (pid == 0) { close(ctx_fd); exit(child(arg)); } /* * wait for the child to exec */ waitpid(pid, &status, WUNTRACED); /* * check if process exited early */ if (WIFEXITED(status)) fatal_error("command %s exited too early with status %d\n", arg[0], WEXITSTATUS(status)); /* * the task is stopped at this point */ /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = pid; if (pfm_load_context(ctx_fd, &load_args) == -1) fatal_error("pfm_load_context error errno %d\n",errno); /* * activate monitoring. The task is still STOPPED at this point. Monitoring * will not take effect until the execution of the task is resumed. */ if (pfm_start(ctx_fd, NULL) == -1) fatal_error("pfm_start error errno %d\n",errno); /* * now resume execution of the task, effectively activating * monitoring. */ ptrace(PTRACE_DETACH, pid, NULL, 0); /* * now the task is running */ /* * simply wait for completion */ waitpid(pid, &status, 0); /* * the task has disappeared at this point but our context is still * present and contains all the latest counts. */ /* * now simply read the results. */ if (pfm_read_pmds(ctx_fd, pd, inp.pfp_event_count) == -1) fatal_error("pfm_read_pmds error errno %d\n",errno); /* * print the results * * It is important to realize, that the first event we specified may not * be in PMD4. Not all events can be measured by any monitor. That's why * we need to use the pc[] array to figure out where event i was allocated. * */ for (i=0; i < inp.pfp_event_count; i++) { pfm_get_full_event_name(&inp.pfp_events[i], name, MAX_EVT_NAME_LEN); printf("PMD%-3u %20"PRIu64" %s\n", pd[i].reg_num, pd[i].reg_value, name); } /* * free the context */ close(ctx_fd); return 0; } int main(int argc, char **argv) { pfmlib_options_t pfmlib_options; int ret; if (argc < 2) { fatal_error("You must specify a command to execute\n"); } /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose= 1; /* set to 1 for verbose */ pfm_set_options(&pfmlib_options); /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) fatal_error("Cannot initialize library: %s\n", pfm_strerror(ret)); return parent(argv+1); } papi-5.5.1/src/libpfm-3.y/examples_v2.x/multiplex.c0000644000307100002310000006716413013651447022030 0ustar yarkhangraduate/* * multiplex2.c - example of kernel-level time-based or overflow-based event multiplexing * * Copyright (c) 2004-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA * 02111-1307 USA */ #ifndef _GNU_SOURCE #define _GNU_SOURCE /* for getline */ #endif #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "detect_pmcs.h" #define MIN_FULL_PERIODS 2 #define MAX_EVT_NAME_LEN 128 #define MULTIPLEX_VERSION "0.2" #define SMPL_FREQ_IN_HZ 300 #define NUM_PMCS PMU_MAX_PMCS #define NUM_PMDS PMU_MAX_PMDS #define MAX_NUM_COUNTERS NUM_PMDS #define MAX_PMU_NAME_LEN 32 typedef struct { struct { int opt_plm; /* which privilege level to monitor (more than one possible) */ int opt_debug; /* print debug information */ int opt_verbose; /* verbose output */ int opt_us_format; /* print large numbers with comma for thousands */ int opt_ovfl_switch; /* overflow-based switching */ int opt_is_system; /* use system-wide */ int opt_intr_only; /* interrupts only*/ int opt_no_cmd_out; /* redirect cmd output to /dev/null */ int opt_no_header; /* no header */ } program_opt_flags; unsigned long max_counters; /* maximum number of counter for the platform */ unsigned long session_timeout; uint64_t smpl_period; uint32_t smpl_freq; unsigned long cpu_mhz; pid_t attach_pid; int pin_cmd_cpu; int pin_cpu; struct timespec switch_timeout; } program_options_t; #define opt_plm program_opt_flags.opt_plm #define opt_debug program_opt_flags.opt_debug #define opt_verbose program_opt_flags.opt_verbose #define opt_us_format program_opt_flags.opt_us_format #define opt_ovfl_switch program_opt_flags.opt_ovfl_switch #define opt_is_system program_opt_flags.opt_is_system #define opt_intr_only program_opt_flags.opt_intr_only #define opt_no_cmd_out program_opt_flags.opt_no_cmd_out #define opt_no_header program_opt_flags.opt_no_header typedef struct _event_set_t { struct _event_set_t *next; unsigned short id; unsigned int n_events; unsigned int pmcs_base; unsigned int pmds_base; int npmcs; int npmds; unsigned long set_runs; char *event_str; } event_set_t; static program_options_t options; static pfarg_pmc_t *all_pmcs; static pfarg_pmd_t *all_pmds; static uint64_t *all_values; static event_set_t *current_set, *all_sets; static unsigned int num_pmds, num_pmcs, num_sets, total_events; static unsigned long full_periods; static volatile int time_to_quit; static jmp_buf jbuf; static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void vbprintf(char *fmt, ...) { va_list ap; if (options.opt_verbose == 0) return; va_start(ap, fmt); vprintf(fmt, ap); va_end(ap); } static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } /* * unreliable for CPU with variable clock speed */ static unsigned long get_cpu_speed(void) { FILE *fp1; unsigned long f1 = 0, f2 = 0; char buffer[128], *p, *value; memset(buffer, 0, sizeof(buffer)); fp1 = fopen("/proc/cpuinfo", "r"); if (fp1 == NULL) return 0; for (;;) { buffer[0] = '\0'; p = fgets(buffer, 127, fp1); if (p == NULL) break; /* skip blank lines */ if (*p == '\n') continue; p = strchr(buffer, ':'); if (p == NULL) break; /* * p+2: +1 = space, +2= firt character * strlen()-1 gets rid of \n */ *p = '\0'; value = p+2; value[strlen(value)-1] = '\0'; if (!strncmp("cpu MHz", buffer, 7)) { float fl; sscanf(value, "%f", &fl); f1 = lroundf(fl); break; } if (!strncmp("BogoMIPS", buffer, 8)) { float fl; sscanf(value, "%f", &fl); f2 = lroundf(fl); } } fclose(fp1); return f1 == 0 ? f2 : f1; } /* * pin task to CPU */ #ifndef __NR_sched_setaffinity #error "you need to define __NR_sched_setaffinity" #endif #define MAX_CPUS 2048 #define NR_CPU_BITS (MAX_CPUS>>3) int pin_cpu(pid_t pid, unsigned int cpu) { uint64_t my_mask[NR_CPU_BITS]; if (cpu >= MAX_CPUS) fatal_error("this program supports only up to %d CPUs\n", MAX_CPUS); my_mask[cpu>>6] = 1ULL << (cpu&63); return syscall(__NR_sched_setaffinity, pid, sizeof(my_mask), &my_mask); } int child(char **arg) { ptrace(PTRACE_TRACEME, 0, NULL, NULL); if (options.pin_cmd_cpu != -1) { pin_cpu(getpid(), options.pin_cmd_cpu); vbprintf("command running on CPU core %d\n", options.pin_cmd_cpu); } if (options.opt_no_cmd_out) { close(1); close(2); } execvp(arg[0], arg); /* not reached */ exit(1); } static void dec2sep(char *str2, char *str, char sep) { int i, l, b, j, c=0; l = strlen(str2); if (l <= 3) { strcpy(str, str2); return; } b = l + l /3 - (l%3 == 0); /* l%3=correction to avoid extraneous comma at the end */ for(i=l, j=0; i >= 0; i--, j++) { if (j) c++; str[b-j] = str2[i]; if (c == 3 && i>0) { str[b-++j] = sep; c = 0; } } } static void print_results(void) { unsigned int i, j, cnt; int ovfl_adj; uint64_t value, set_runs; event_set_t *e; char *p; char tmp1[32], tmp2[32], *str; char mtotal_str[32], *mtotal; char stotal_str[32], *stotal; if (full_periods < num_sets) fatal_error("not all sets have been activated, need to run longer %lu\n", full_periods); /* * print the results * * It is important to realize, that the first event we specified may not * be in PMD4. Not all events can be measured by any monitor. That's why * we need to use the pc[] array to figure out where event i was allocated. * */ if (options.opt_no_header == 0) { printf("# %u Hz period = %u usecs\n# %"PRIu64" cycles @ %lu MHz\n", options.smpl_freq, 1000000 / options.smpl_freq, options.smpl_period, options.cpu_mhz); if (options.opt_ovfl_switch == 0) printf("# using time-based multiplexing\n" "# %uus effective switch timeout\n", 1000000 / options.smpl_freq); else printf("# using overflow-based multiplexing\n"); if (options.opt_is_system) printf("# system-wide mode on CPU core %d\n",options.pin_cpu); printf("# %d sets\n", num_sets); printf("# %.2f average run per set\n", (double)full_periods/num_sets); printf("# set measured total #runs scaled total event name\n"); printf("# ------------------------------------------------------------------\n"); } ovfl_adj= options.opt_ovfl_switch ? 1 : 0; for (i=0, e = all_sets, cnt = 0; i < num_sets; i++, e = e->next) { set_runs = e->set_runs; str = e->event_str; for(j=0; j < e->npmds-ovfl_adj; j++, cnt++) { value = all_values[j+e->pmds_base]; sprintf(tmp1, "%"PRIu64, value); if (options.opt_us_format) { dec2sep(tmp1, mtotal_str, ','); } else { strcpy(mtotal_str, tmp1); } mtotal = mtotal_str; /* * scaling */ sprintf(tmp2, "%"PRIu64, ((value*full_periods)/set_runs)); if (options.opt_us_format) { dec2sep(tmp2, stotal_str, ','); } else { strcpy(stotal_str, tmp2); } stotal = stotal_str; printf(" %03d %20s %8"PRIu64" %20s %s\n", i, mtotal, set_runs, stotal, str); p = strchr(str, '\0'); if (p) str = p+1; } /* * skip first event */ if (options.opt_ovfl_switch) cnt++; } } static void update_set(int ctxid) { int count; int base; int ret; int i; base = current_set->pmds_base; /* * we do not read the last counter (cpu_cycles) to avoid overwriting * the reg_value field which will be used for next round * * We need to retry the read in case we get EBUSY because it means that * the child task context is not yet available from inspection by PFM_READ_PMDS2. * */ count = current_set->npmds; if (options.opt_ovfl_switch) count--; ret = pfm_read_pmds(ctxid, all_pmds + base, count); if (ret == -1) fatal_error("error reading set: %s\n", strerror(errno)); /* update counts for this set */ for (i=0; i < count; i++) { all_values[base+i] += all_pmds[base+i].reg_value; /* reset for next round */ all_pmds[base+i].reg_value = 0UL; } } static void switch_sets(int ctxid) { update_set(ctxid); current_set = current_set->next; if (current_set == NULL) current_set = all_sets; current_set->set_runs++; vbprintf("starting set %d run %lu\n", current_set->id, current_set->set_runs); /* * we must reprogram all avaibale PMCs (or PMDS) to ensure that no * state is left over from the previous set and which could conflict * on restart */ if (pfm_write_pmcs(ctxid, all_pmcs+current_set->pmcs_base, current_set->npmcs) == -1) { fatal_error("error writing pmcs: %s\n", strerror(errno)); } if (pfm_write_pmds(ctxid, all_pmds+current_set->pmds_base, current_set->npmds) == -1) { fatal_error("error writing pmds: %s\n", strerror(errno)); } full_periods++; if (options.opt_ovfl_switch && pfm_restart(ctxid) == -1) { if (errno != EBUSY) fatal_error("error pfm_restart: %s\n", strerror(errno)); /* * in case of EBUSY, it probably means the task has exited now */ } } static void sigintr_handler(int sig) { if (sig == SIGALRM) time_to_quit = 1; else time_to_quit = 2; longjmp(jbuf, 1); } static void sigchld_handler(int sig) { time_to_quit = 1; } static int measure_one_task(char **argv) { int ctxid; pfarg_ctx_t ctx[1]; pfarg_load_t load_arg; struct pollfd pollfd; pid_t pid; int status, ret; memset(ctx, 0, sizeof(ctx)); memset(&load_arg, 0, sizeof(load_arg)); /* * create the context */ ctxid = pfm_create_context(ctx, NULL, NULL, 0); if (ctxid == -1 ) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * set close-on-exec to ensure we will be getting the PFM_END_MSG, i.e., * fd not visible to child. */ if (fcntl(ctxid, F_SETFD, FD_CLOEXEC)) fatal_error("cannot set CLOEXEC: %s\n", strerror(errno)); /* * write registers for first set */ if (pfm_write_pmcs(ctxid, all_pmcs+current_set->pmcs_base, current_set->npmcs) == -1) { fatal_error("error pfm_write_pmcs: %s\n", strerror(errno)); } if (pfm_write_pmds(ctxid, all_pmds+current_set->pmds_base, current_set->npmds) == -1) { fatal_error("error pfm_write_pmds: %s\n", strerror(errno)); } /* * now launch the child code */ if (options.attach_pid == 0) { if ((pid= fork()) == -1) fatal_error("Cannot fork process\n"); if (pid == 0) exit(child(argv)); } else { pid = options.attach_pid; ret = ptrace(PTRACE_ATTACH, pid, NULL, 0); if (ret) { fatal_error("cannot attach to task %d: %s\n",options.attach_pid, strerror(errno)); } } ret = waitpid(pid, &status, WUNTRACED); if (ret < 0 || WIFEXITED(status)) fatal_error("error command already terminated, exit code %d\n", WEXITSTATUS(status)); vbprintf("child created and stopped\n"); /* * now attach the context */ load_arg.load_pid = pid; if (pfm_load_context(ctxid, &load_arg) == -1) { fatal_error("pfm_load_context error errno %d\n",errno); } current_set->set_runs = 1; /* * start monitoring */ if (pfm_start(ctxid, NULL) == -1) { fatal_error("pfm_start error errno %d\n",errno); } ptrace(PTRACE_DETACH, pid, NULL, 0); if (setjmp(jbuf) == 1) { if (time_to_quit == 1) { printf("timeout expired\n"); } if (time_to_quit == 2) printf("session interrupted\n"); goto finish_line; } if (options.session_timeout) { printf("\n", options.session_timeout); alarm(options.session_timeout); } pollfd.fd = ctxid; pollfd.events = POLLIN; pollfd.revents = 0; while(time_to_quit == 0) { /* * mainloop. poll timeout is in msecs */ ret = poll(&pollfd, 1, 1000 / options.smpl_freq); switch(ret) { case 0: ret = ptrace(PTRACE_ATTACH, pid, NULL, 0); if (ret) { time_to_quit = 1; break; } ret = waitpid(pid, &status, WUNTRACED); /* * exit with time_to_quit = 0 * to avoid unloading from dead thread */ if (WIFEXITED(status)) goto finish_line; switch_sets(ctxid); ptrace(PTRACE_DETACH, pid, NULL, 0); break; case -1: fatal_error("poll error: %s\n", strerror(errno)); default: /* we don't even read END_MSG */ time_to_quit = 1; } } finish_line: /* * cleanup after an alarm timeout */ if (time_to_quit) { /* stop monitored task */ ptrace(PTRACE_ATTACH, pid, NULL, 0); waitpid(pid, NULL, WUNTRACED); /* detach context */ pfm_unload_context(ctxid); } if (options.attach_pid == 0) { kill(pid, SIGKILL); waitpid(pid, &status, 0); } else { ptrace(PTRACE_DETACH, pid, NULL, 0); } if (time_to_quit < 2) print_results(); close(ctxid); return 0; } static int measure_one_cpu(char **argv) { int ctxid, status; pfarg_ctx_t ctx[1]; pfarg_load_t load_arg; struct pollfd pollfd; pid_t pid = 0; int ret, timeout; memset(ctx, 0, sizeof(ctx)); memset(&load_arg, 0, sizeof(load_arg)); if (options.pin_cpu == -1) { options.pin_cpu = 0; printf("forcing monitoring onto CPU core 0\n"); pin_cpu(getpid(), 0); } ctx[0].ctx_flags = PFM_FL_SYSTEM_WIDE; /* * create the context */ ctxid = pfm_create_context(ctx, NULL, NULL, 0); if (ctxid == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * set close-on-exec to ensure we will be getting the PFM_END_MSG, i.e., * fd not visible to child. */ if (fcntl(ctxid, F_SETFD, FD_CLOEXEC)) fatal_error("cannot set CLOEXEC: %s\n", strerror(errno)); /* * Now program the all the registers in one call * * Note that there is a limitation on the size of the argument vector * that can be passed. It is usually set to a page size (16KB). */ if (pfm_write_pmcs(ctxid, all_pmcs+current_set->pmcs_base, current_set->npmcs) == -1) fatal_error("error: pfm_write_pmcs errno: %s\n", strerror(errno)); /* * initialize the PMD registers. * * To be read, each PMD must be either written or declared * as being part of a sample (reg_smpl_pmds) */ if (pfm_write_pmds(ctxid, all_pmds+current_set->pmds_base, current_set->npmds) == -1) fatal_error("pfm_write_pmds error errno %d\n", strerror(errno)); /* * now launch the child code */ if (*argv) { if ((pid = fork()) == -1) fatal_error("Cannot fork process\n"); if (pid == 0) exit(child(argv)); } /* * wait for the child to exec or be stopped * We do this even in system-wide mode to ensure * that the task does not start until we are ready * to monitor. */ if (pid) { ret = waitpid(pid, &status, WUNTRACED); if (ret < 0 || WIFEXITED(status)) fatal_error("error command already terminated, exit code %d\n", WEXITSTATUS(status)); vbprintf("child created and stopped\n"); } /* * now attach the context */ load_arg.load_pid = options.pin_cpu; if (pfm_load_context(ctxid, &load_arg) == -1) fatal_error("pfm_load_context error errno %d\n",errno); /* * start monitoring */ if (pfm_start(ctxid, NULL) == -1) fatal_error("pfm_start error errno %d\n",errno); if (pid) { signal(SIGCHLD, sigchld_handler); ptrace(PTRACE_DETACH, pid, NULL, 0); } /* * mainloop */ pollfd.fd = ctxid; pollfd.events = POLLIN; pollfd.revents = 0; timeout = options.opt_ovfl_switch ? -1 : (1000 / options.smpl_freq); while (time_to_quit == 0) { ret = poll(&pollfd, 1, timeout); switch(ret) { case 1: case 0: /* *we are consuming the message. * to avoid this phase we could use PFM_FL_OVFL_NO_MSG * and use signal based notification */ if (options.opt_ovfl_switch) { ssize_t r; pfarg_msg_t msg; r = read(ctxid, &msg, sizeof(msg)); (void) r; } switch_sets(ctxid); break; default: if (errno != EINTR) fatal_error("poll fails\n"); } } if (full_periods < MIN_FULL_PERIODS) fatal_error("Not enough periods (%lu) to print results\n", full_periods); if (pid) waitpid(pid, &status, 0); print_results(); close(ctxid); return 0; } int mainloop(char **argv) { event_set_t *e; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfmlib_regmask_t impl_counters, used_pmcs; pfmlib_event_t cycle_event; unsigned int i, j; char *p, *str; unsigned int max_counters, allowed_counters; int ret; pfm_get_num_counters(&max_counters); if (max_counters < 2 && options.opt_ovfl_switch) fatal_error("not enough counter to get overflow switching to work\n"); allowed_counters = max_counters; /* * account for overflow counter (cpu cycles) */ if (options.opt_ovfl_switch) allowed_counters--; memset(&used_pmcs, 0, sizeof(used_pmcs)); memset(&impl_counters, 0, sizeof(impl_counters)); pfm_get_impl_counters(&impl_counters); options.smpl_period = (options.cpu_mhz*1000000)/options.smpl_freq; vbprintf("%lu Hz period = %"PRIu64" cycles @ %lu Mhz\n", options.smpl_freq, options.smpl_period, options.cpu_mhz); for (e = all_sets; e; e = e->next) { for (p = str = e->event_str; p ; ) { p = strchr(str, ','); if (p) str = p +1; total_events++; } } /* * account for extra event per set (cycle event) */ if (options.opt_ovfl_switch) { total_events += num_sets; /* * look for our trigger event */ if (pfm_get_cycle_event(&cycle_event) != PFMLIB_SUCCESS) { fatal_error("Cannot find cycle event\n"); } } vbprintf("total_events=%u\n", total_events); all_pmcs = calloc(1, sizeof(pfarg_pmc_t)*total_events); all_pmds = calloc(1, sizeof(pfarg_pmd_t)*total_events); all_values = calloc(1, sizeof(uint64_t)*total_events); if (all_pmcs == NULL || all_pmds == NULL || all_values == NULL) fatal_error("cannot allocate event tables\n"); /* * use the library to figure out assignments for all events of all sets */ for (i=0, e = all_sets; i < num_sets; i++, e = e->next) { memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); /* * build the pfp_unavail_pmcs bitmask by looking * at what perfmon has available. It is not always * the case that all PMU registers are actually available * to applications. For instance, on IA-32 platforms, some * registers may be reserved for the NMI watchdog timer. * * With this bitmap, the library knows which registers NOT to * use. Of source, it is possible that no valid assignement may * be possible if certina PMU registers are not available. */ detect_unavail_pmcs(-1, &inp.pfp_unavail_pmcs); str = e->event_str; for(j=0, p = str; p && j < allowed_counters; j++) { p = strchr(str, ','); if (p) *p = '\0'; if (pfm_find_full_event(str, &inp.pfp_events[j]) != PFMLIB_SUCCESS) { fatal_error("Cannot find %s event for set %d event %d\n", str, i, j); } if (p) { *p = ','; str = p + 1; } } if (p) { fatal_error("error in set %d: cannot have more than %d event(s) per set %s\n", i, allowed_counters, options.opt_ovfl_switch ? "(overflow switch mode)": "(hardware limit)"); } /* * add the cycle event as the last event when we switch on overflow */ if (options.opt_ovfl_switch) { inp.pfp_events[j] = cycle_event; inp.pfp_event_count = j+1; e->n_events = j+1; } else { e->n_events = j; inp.pfp_event_count = j; } inp.pfp_dfl_plm = options.opt_plm; if (options.opt_is_system) inp.pfp_flags = PFMLIB_PFP_SYSTEMWIDE; vbprintf("PMU programming for set %d\n", i); /* * let the library do the hard work */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) { fatal_error("cannot configure events for set %d: %s\n", i, pfm_strerror(ret)); } e->id = i; e->pmcs_base = num_pmcs; e->pmds_base = num_pmds; /* * propagate from libpfm to kernel data structures */ for (j=0; j < outp.pfp_pmc_count; j++, num_pmcs++) { all_pmcs[num_pmcs].reg_num = outp.pfp_pmcs[j].reg_num; all_pmcs[num_pmcs].reg_value = outp.pfp_pmcs[j].reg_value; } for (j=0; j < outp.pfp_pmd_count; j++, num_pmds++) all_pmds[num_pmds].reg_num = outp.pfp_pmds[j].reg_num; e->npmcs = num_pmcs - e->pmcs_base; e->npmds = num_pmds - e->pmds_base; if (options.opt_ovfl_switch) { /* * We do this even in system-wide mode to ensure * that the task does not start until we are ready * to monitor. * setup the sampling period */ all_pmds[num_pmds-1].reg_value = - options.smpl_period; all_pmds[num_pmds-1].reg_short_reset = - options.smpl_period; all_pmds[num_pmds-1].reg_long_reset = - options.smpl_period; all_pmds[num_pmds-1].reg_flags = PFM_REGFL_OVFL_NOTIFY; } vbprintf("set%d pmc_base=%d pmd_base=%d npmcs=%d npmds=%d\n", e->id, e->pmcs_base, e->pmds_base, e->npmcs, e->npmds); } current_set = all_sets; signal(SIGALRM, sigintr_handler); signal(SIGINT, sigintr_handler); if (options.opt_is_system) return measure_one_cpu(argv); return measure_one_task(argv); } static struct option multiplex_options[]={ { "help", 0, 0, 1}, { "freq", 1, 0, 2 }, { "kernel-level", 0, 0, 3 }, { "user-level", 0, 0, 4 }, { "version", 0, 0, 5 }, { "set", 1, 0, 6 }, { "session-timeout", 1, 0, 7 }, { "attach-task", 1, 0, 8 }, { "pin-cmd", 1, 0, 9 }, { "cpu", 1, 0, 10 }, { "verbose", 0, &options.opt_verbose, 1 }, { "debug", 0, &options.opt_debug, 1 }, { "us-counter-format", 0, &options.opt_us_format, 1}, { "ovfl-switch", 0, &options.opt_ovfl_switch, 1}, { "system-wide", 0, &options.opt_is_system, 1}, { "no-cmd-output", 0, &options.opt_no_cmd_out, 1}, { "no-header", 0, &options.opt_no_header, 1}, { 0, 0, 0, 0} }; static void generate_default_sets(void) { event_set_t *es, *tail = NULL; pfmlib_event_t events[2]; size_t len; char *name; unsigned int i; int ret; ret = pfm_get_cycle_event(&events[0]); if (ret != PFMLIB_SUCCESS) fatal_error("cannot find cycle event\n"); ret = pfm_get_inst_retired_event(&events[1]); if (ret != PFMLIB_SUCCESS) fatal_error("cannot find instruction retired event\n"); pfm_get_max_event_name_len(&len); for (i=0; i < 2; i++) { name = malloc(len+1); if (name == NULL) { fatal_error("cannot allocate space for event name\n"); } pfm_get_full_event_name(&events[i], name, len+1); es = (event_set_t *)malloc(sizeof(event_set_t)); if (es == NULL) fatal_error("cannot allocate new event set\n"); memset(es, 0, sizeof(*es)); es->event_str = name; es->next = NULL; es->n_events = 0; if (all_sets == NULL) all_sets = es; else tail->next = es; tail = es; } num_sets = i; } static void print_usage(char **argv) { printf("usage: %s [OPTIONS]... COMMAND\n", argv[0]); printf( "-h, --help\t\t\t\tdisplay this help and exit\n" "-V, --version\t\t\t\toutput version information and exit\n" "-u, --user-level\t\t\tmonitor at the user level for all events\n" "-k, --kernel-level\t\t\tmonitor at the kernel level for all events\n" "-c, --us-counter-format\tprint large counts with comma for thousands\n" "-p pid, --attach-task pid\tattach to a running task\n" "--set=ev1[,ev2,ev3,ev4,...]\t\tdescribe one set\n" "--freq=number\t\t\t\tset set switching frequency in Hz\n" "-c cpu, --cpu=cpu\t\t\tCPU to use for system-wide [default current]\n" "--ovfl-switch\t\t\t\t\tuse overflow based multiplexing (default: time-based)\n" "--verbose\t\t\t\tprint more information during execution\n" "--system-wide\t\t\t\tuse system-wide (only one CPU at a time)\n" "--excl-idle\t\t\texclude idle task(system-wide only)\n" "--excl-intr\t\t\texclude interrupt triggered execution(system-wide only)\n" "--intr-only\t\t\tinclude only interrupt triggered execution(system-wide only)\n" "--session-timeout=sec\t\t\tsession timeout in seconds (system-wide only)\n" "--no-cmd-output\t\t\t\toutput of executed command redirected to /dev/null\n" "--pin-cmd=cpu\t\t\t\tpin executed command onto a specific cpu\n" ); } int main(int argc, char **argv) { char *endptr = NULL; pfmlib_options_t pfmlib_options; event_set_t *tail = NULL, *es; unsigned long long_val; int c, ret; options.pin_cmd_cpu = options.pin_cpu = -1; while ((c=getopt_long(argc, argv,"+vhkuVct:p:", multiplex_options, 0)) != -1) { switch(c) { case 0: continue; /* fast path for options */ case 1: print_usage(argv); exit(0); case 'v': options.opt_verbose = 1; break; case 'c': options.opt_us_format = 1; break; case 2: if (options.smpl_freq) fatal_error("sampling frequency set twice\n"); options.smpl_freq = strtoul(optarg, &endptr, 10); if (*endptr != '\0') fatal_error("invalid freqyency: %s\n", optarg); break; case 3: case 'k': options.opt_plm |= PFM_PLM0; break; case 4: case 'u': options.opt_plm |= PFM_PLM3; break; case 'V': case 5: printf("multiplex version " MULTIPLEX_VERSION " Date: " __DATE__ "\n" "Copyright (C) 2004 Hewlett-Packard Company\n"); exit(0); case 6: es = (event_set_t *)malloc(sizeof(event_set_t)); if (es == NULL) fatal_error("cannot allocate new event set\n"); es->event_str = optarg; es->next = NULL; es->n_events = 0; if (all_sets == NULL) all_sets = es; else tail->next = es; tail = es; num_sets++; break; case 't': case 7: if (options.session_timeout) fatal_error("too many timeouts\n"); if (*optarg == '\0') fatal_error("--session-timeout needs an argument\n"); long_val = strtoul(optarg,&endptr, 10); if (*endptr != '\0') fatal_error("invalid number of seconds for timeout: %s\n", optarg); if (long_val >= UINT_MAX) fatal_error("timeout is too big, must be < %u\n", UINT_MAX); options.session_timeout = (unsigned int)long_val; break; case 'p': case 8: if (options.attach_pid) fatal_error("process to attach specified twice\n"); options.attach_pid = (pid_t)atoi(optarg); break; case 9: if (options.pin_cmd_cpu != -1) fatal_error("cannot pin command twice\n"); options.pin_cmd_cpu = atoi(optarg); break; case 10: if (options.pin_cpu != -1) fatal_error("cannot pin to more than one cpu\n"); options.pin_cpu = atoi(optarg); break; default: fatal_error(""); /* just quit silently now */ } } if (optind == argc && options.opt_is_system == 0 && options.attach_pid == 0) fatal_error("you need to specify a command to measure\n"); /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = options.opt_verbose; /* set to 1 for verbose */ pfm_set_options(&pfmlib_options); /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) fatal_error("Cannot initialize library: %s\n", pfm_strerror(ret)); if ((options.cpu_mhz = get_cpu_speed()) == 0) fatal_error("can't get CPU speed\n"); if (options.smpl_freq == 0UL) options.smpl_freq = SMPL_FREQ_IN_HZ; if (options.opt_plm == 0) options.opt_plm = PFM_PLM3; if (num_sets == 0) generate_default_sets(); return mainloop(argv+optind); } papi-5.5.1/src/libpfm-3.y/examples_v2.x/task_smpl_user.c0000644000307100002310000003146013013651447023026 0ustar yarkhangraduate/* * task_smpl_user.c - example of a task collecting a profile from user level * * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "detect_pmcs.h" #define SAMPLING_PERIOD 100000 #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS typedef struct { int opt_no_show; int opt_block; int opt_sys; } options_t; static uint64_t collected_samples; static pfarg_pmd_t pd[NUM_PMDS]; static unsigned int num_pmds; static options_t options; static volatile int terminate; static struct option the_options[]={ { "help", 0, 0, 1}, { "ovfl-block", 0, &options.opt_block, 1}, { "no-show", 0, &options.opt_no_show, 1}, { "system-wide", 0, &options.opt_sys, 1}, { 0, 0, 0, 0} }; static void fatal_error(char *fmt,...) __attribute__((noreturn)); #define BPL (sizeof(uint64_t )<<3) #define LBPL 6 static inline void pfm_bv_set(uint64_t *bv, uint16_t rnum) { bv[rnum>>LBPL] |= 1UL << (rnum&(BPL-1)); } static inline int pfm_bv_isset(uint64_t *bv, uint16_t rnum) { return bv[rnum>>LBPL] & (1UL <<(rnum&(BPL-1))) ? 1 : 0; } static inline void pfm_bv_copy(uint64_t *d, uint64_t *j, uint16_t n) { if (n <= BPL) *d = *j; else { memcpy(d, j, (n>>LBPL)*sizeof(uint64_t)); } } /* * pin task to CPU */ #ifndef __NR_sched_setaffinity #error "you need to define __NR_sched_setaffinity" #endif #define MAX_CPUS 2048 #define NR_CPU_BITS (MAX_CPUS>>3) int pin_cpu(pid_t pid, unsigned int cpu) { uint64_t my_mask[NR_CPU_BITS]; if (cpu >= MAX_CPUS) fatal_error("this program supports only up to %d CPUs\n", MAX_CPUS); my_mask[cpu>>6] = 1ULL << (cpu&63); return syscall(__NR_sched_setaffinity, pid, sizeof(my_mask), &my_mask); } static void warning(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); } static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } int child(char **arg) { if (options.opt_sys) { printf("child pinned on CPU0\n"); pin_cpu(getpid(), 0); } /* * force the task to stop before executing the first * user level instruction */ ptrace(PTRACE_TRACEME, 0, NULL, NULL); execvp(arg[0], arg); /* not reached */ exit(1); } void show_task_rusage(const struct timeval *start, const struct timeval *end, const struct rusage *ru) { long secs, suseconds, end_usec; secs = end->tv_sec - start->tv_sec; end_usec = end->tv_usec; if (end_usec < start->tv_usec) { end_usec += 1000000; secs--; } suseconds = end_usec - start->tv_usec; printf ("real %ldh%02ldm%02ld.%03lds user %ldh%02ldm%02ld.%03lds sys %ldh%02ldm%02ld.%03lds\n", secs / 3600, (secs % 3600) / 60, secs % 60, suseconds / 1000, ru->ru_utime.tv_sec / 3600, (ru->ru_utime.tv_sec % 3600) / 60, ru->ru_utime.tv_sec% 60, (long)(ru->ru_utime.tv_usec / 1000), ru->ru_stime.tv_sec / 3600, (ru->ru_stime.tv_sec % 3600) / 60, ru->ru_stime.tv_sec% 60, (long)(ru->ru_stime.tv_usec / 1000) ); } static void process_sample(int fd, unsigned long ip, pid_t pid, pid_t tid, uint16_t cpu) { unsigned int j; if (pfm_read_pmds(fd, pd, num_pmds)) fatal_error("pfm_read_pmds error errno %d\n",errno); if (options.opt_no_show) goto done; printf("entry %"PRIu64" PID:%d TID: %d CPU:%u LAST_VAL: %"PRIu64" IIP:0x%lx\n", collected_samples, pid, tid, cpu, - pd[0].reg_last_reset_val, ip); for(j=1; j < num_pmds; j++) { printf("PMD%-2d = %"PRIu64"\n", pd[j].reg_num, pd[j].reg_value); } done: collected_samples++; } static void cld_handler(int n) { terminate = 1; } int mainloop(char **arg) { pfarg_ctx_t ctx; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfarg_pmc_t pc[NUM_PMCS]; pfarg_load_t load_args; struct timeval start_time, end_time; struct rusage rusage; pfarg_msg_t msg; uint64_t ovfl_count = 0; pid_t pid; int status, ret, fd; unsigned int i, num_counters; /* * intialize all locals */ memset(&ctx, 0, sizeof(ctx)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); memset(pc, 0, sizeof(pc)); memset(&load_args, 0, sizeof(load_args)); pfm_get_num_counters(&num_counters); /* * locate events */ if (pfm_get_cycle_event(&inp.pfp_events[0]) != PFMLIB_SUCCESS) fatal_error("cannot find cycle event\n"); if (pfm_get_inst_retired_event(&inp.pfp_events[1]) != PFMLIB_SUCCESS) fatal_error("cannot find inst retired event\n"); i = 2; /* * set the privilege mode: * PFM_PLM3 : user level * PFM_PLM0 : kernel level */ inp.pfp_dfl_plm = PFM_PLM3; printf("measuring at plm=0x%x\n", inp.pfp_dfl_plm); if (i > num_counters) { i = num_counters; printf("too many events provided (max=%d events), using first %d event(s)\n", num_counters, i); } /* * how many counters we use */ inp.pfp_event_count = i; inp.pfp_flags = options.opt_sys ? PFMLIB_PFP_SYSTEMWIDE : 0; /* * build the pfp_unavail_pmcs bitmask by looking * at what perfmon has available. It is not always * the case that all PMU registers are actually available * to applications. For instance, on IA-32 platforms, some * registers may be reserved for the NMI watchdog timer. * * With this bitmap, the library knows which registers NOT to * use. Of source, it is possible that no valid assignement may * be possible if certina PMU registers are not available. */ detect_unavail_pmcs(-1, &inp.pfp_unavail_pmcs); /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); /* * Now prepare the argument to initialize the PMDs and PMCS. * We use pfp_pmc_count to determine the number of PMC to intialize. * We use pfp_pmd_count to determine the number of PMD to initialize. * Some events/features may cause extra PMCs to be used, leading to: * - pfp_pmc_count may be >= pfp_event_count * - pfp_pmd_count may be >= pfp_event_count */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } for (i=0; i < outp.pfp_pmd_count; i++) { pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * we also want to reset the other PMDs on * every overflow. If we do not set * this, the non-overflowed counters * will be untouched. */ if (i) pfm_bv_set(pd[0].reg_reset_pmds, pd[i].reg_num); } /* * we our sampling counter overflow, we want to be notified. * The notification will come ONLY when the sampling buffer * becomes full. * * We also activate randomization of the sampling period. */ pd[0].reg_flags |= PFM_REGFL_OVFL_NOTIFY | PFM_REGFL_RANDOM; pd[0].reg_value = - SAMPLING_PERIOD; pd[0].reg_short_reset = - SAMPLING_PERIOD; pd[0].reg_long_reset = - SAMPLING_PERIOD; /* * setup randomization parameters, we allow a range of up to +256 here. */ pd[0].reg_random_seed = 5; pd[0].reg_random_mask = 0xff; printf("programming %u PMCS and %u PMDS\n", outp.pfp_pmc_count, inp.pfp_event_count); /* * prepare context structure. */ if (options.opt_sys) { if (options.opt_block) fatal_error("blocking mode not supported in system-wide\n"); printf("system-wide monitoring on CPU0\n"); pin_cpu(getpid(), 0); ctx.ctx_flags |= PFM_FL_SYSTEM_WIDE; } if (options.opt_block) ctx.ctx_flags |= PFM_FL_NOTIFY_BLOCK; /* * now create our perfmon context. */ fd = pfm_create_context(&ctx, NULL, NULL, 0); if (fd == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * Now program the registers */ if (pfm_write_pmcs(fd, pc, outp.pfp_pmc_count)) fatal_error("pfm_write_pmcs error errno %d\n",errno); /* * initialize the PMDs * To be read, each PMD must be either written or declared * as being part of a sample (reg_smpl_pmds) */ if (pfm_write_pmds(fd, pd, outp.pfp_pmd_count)) fatal_error("pfm_write_pmds error errno %d\n",errno); num_pmds = outp.pfp_pmd_count; signal(SIGCHLD, SIG_IGN); /* * Create the child task */ if ((pid=fork()) == -1) fatal_error("Cannot fork process\n"); /* * In order to get the PFM_END_MSG message, it is important * to ensure that the child task does not inherit the file * descriptor of the context. By default, file descriptor * are inherited during exec(). We explicitely close it * here. We could have set it up through fcntl(FD_CLOEXEC) * to achieve the same thing. */ if (pid == 0) { close(fd); child(arg); } /* * wait for the child to exec */ waitpid(pid, &status, WUNTRACED); /* * process is stopped at this point */ if (WIFEXITED(status)) { warning("task %s [%d] exited already status %d\n", arg[0], pid, WEXITSTATUS(status)); goto terminate_session; } /* * attach context to stopped task */ load_args.load_pid = options.opt_sys ? getpid() : pid; if (pfm_load_context(fd, &load_args)) fatal_error("pfm_load_context error errno %d\n",errno); /* * activate monitoring for stopped task. * (nothing will be measured at this point */ if (pfm_start(fd, NULL)) fatal_error("pfm_start error errno %d\n",errno); if (options.opt_sys) signal(SIGCHLD, cld_handler); /* * detach child. Side effect includes * activation of monitoring. */ ptrace(PTRACE_DETACH, pid, NULL, 0); gettimeofday(&start_time, NULL); /* * core loop */ while(terminate == 0) { /* * wait for overflow/end notification messages */ ret = read(fd, &msg, sizeof(msg)); if (ret == -1) { if (errno != EINTR) fatal_error("cannot read perfmon msg: %s\n", strerror(errno)); continue; } switch(msg.type) { case PFM_MSG_OVFL: /* one sample to process */ process_sample(fd, msg.pfm_ovfl_msg.msg_ovfl_ip, msg.pfm_ovfl_msg.msg_ovfl_pid, msg.pfm_ovfl_msg.msg_ovfl_tid, msg.pfm_ovfl_msg.msg_ovfl_cpu); ovfl_count++; if (pfm_restart(fd) == -1) { if (errno != EBUSY) fatal_error("pfm_restart error errno %d\n",errno); } break; case PFM_MSG_END: /* monitored task terminated (not for system-wide) */ printf("task terminated\n"); terminate = 1; break; default: fatal_error("unknown message type %d\n", msg.type); } } terminate_session: /* * cleanup child */ wait4(pid, &status, 0, &rusage); gettimeofday(&end_time, NULL); /* * destroy perfmon context */ close(fd); printf("%"PRIu64" samples collected in %"PRIu64" buffer overflows\n", collected_samples, ovfl_count); show_task_rusage(&start_time, &end_time, &rusage); return 0; } static void usage(void) { printf("usage: task_smpl [-h] [--help] [--no-show] [--ovfl-block] cmd\n"); } int main(int argc, char **argv) { pfmlib_options_t pfmlib_options; int c; while ((c=getopt_long(argc, argv,"h", the_options, 0)) != -1) { switch(c) { case 0: continue; case 1: case 'h': usage(); exit(0); default: fatal_error(""); } } if (argv[optind] == NULL) { fatal_error("You must specify a command to execute\n"); } /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 0; /* set to 1 for verbose */ pfm_set_options(&pfmlib_options); /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) { fatal_error("Can't initialize library\n"); } return mainloop(argv+optind); } papi-5.5.1/src/libpfm-3.y/examples_v2.x/self_smpl.c0000644000307100002310000002151613013651447021760 0ustar yarkhangraduate/* * self_smpl.c - example of self sampling using a kernel samplig buffer * * Copyright (c) 2009 Google, Inc * Contributed by Stephane Eranian * * Based on mont_dear.c from: * Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define SMPL_PERIOD (2400000) typedef pfm_dfl_smpl_hdr_t smpl_hdr_t; typedef pfm_dfl_smpl_entry_t smpl_entry_t; typedef pfm_dfl_smpl_arg_t smpl_arg_t; static int fd; static void *smpl_vaddr; static size_t entry_size; long do_test(unsigned long size) { unsigned long i, sum = 0; int *array; array = (int *)malloc(size * sizeof(int)); if (array == NULL ) { printf("line = %d No memory available!\n", __LINE__); exit(1); } for(i=0; ihdr_overflows <= last_ovfl && last_ovfl != ~0UL) { printf("skipping identical set of samples %"PRIu64" <= %"PRIu64"\n", hdr->hdr_overflows, last_ovfl); return; } pos = (unsigned long)(hdr+1); count = hdr->hdr_count; /* * walk through all the entries recored in the buffer */ while(count--) { ent = (smpl_entry_t *)pos; /* * print entry header */ printf("Entry %"PRIu64" PID:%d TID:%d CPU:%d STAMP:0x%"PRIx64" IIP:0x%016"PRIx64"\n", smpl_entry++, ent->tgid, ent->pid, ent->cpu, ent->tstamp, ent->ip); /* * move to next entry */ pos += entry_size; } } static void overflow_handler(int n, struct siginfo *info, struct sigcontext *sc) { process_smpl_buffer(); /* * And resume monitoring */ if (pfm_restart(fd)) errx(1, "pfm_restart"); } int main(void) { pfarg_pmd_t pd[8]; pfarg_pmc_t pc[8]; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfarg_ctx_t ctx; pfarg_load_t load_args; smpl_arg_t buf_arg; pfmlib_options_t pfmlib_options; unsigned long nloop = 10000; struct sigaction act; unsigned int i; int ret; /* * Initialize pfm library (required before we can use it) */ if (pfm_initialize() != PFMLIB_SUCCESS) errx(1, "cannot initialize library\n"); /* * Install the overflow handler (SIGIO) */ memset(&act, 0, sizeof(act)); act.sa_handler = (sig_t)overflow_handler; sigaction (SIGIO, &act, 0); /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 1; /* set to 1 for debug */ pfm_set_options(&pfmlib_options); memset(pd, 0, sizeof(pd)); memset(pc, 0, sizeof(pc)); memset(pc, 0, sizeof(pc)); memset(&ctx, 0, sizeof(ctx)); memset(&buf_arg, 0, sizeof(buf_arg)); memset(&load_args, 0, sizeof(load_args)); /* * prepare parameters to library. we don't use any Itanium * specific features here. so the pfp_model is NULL. */ memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); /* * To count the number of occurence of this instruction, we must * program a counting monitor with the IA64_TAGGED_INST_RETIRED_PMC8 * event. */ if (pfm_get_cycle_event(&inp.pfp_events[0]) != PFMLIB_SUCCESS) errx(1, "cannot find cycle event\n"); /* * set the (global) privilege mode: * PFM_PLM0 : kernel level only */ inp.pfp_dfl_plm = PFM_PLM3|PFM_PLM0; /* * how many counters we use */ inp.pfp_event_count = 1; /* * let the library figure out the values for the PMCS * * We use all global settings for this EAR. */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) errx(1, "cannot configure events: %s\n", pfm_strerror(ret)); /* * the size of the buffer is indicated in bytes (not entries). * * The kernel will record into the buffer up to a certain point. * No partial samples are ever recorded. */ buf_arg.buf_size = getpagesize(); /* * do not generate overflow notification messages */ ctx.ctx_flags = PFM_FL_OVFL_NO_MSG; /* * now create the context for self monitoring/per-task */ fd = pfm_create_context(&ctx, PFM_DFL_SMPL_NAME, &buf_arg, sizeof(buf_arg)); if (fd == -1) { if (errno == ENOSYS) errx(1, "kernel does not have performance monitoring support!\n"); errx(1, "cannot create PFM context %s\n", strerror(errno)); } /* * retrieve the virtual address at which the sampling * buffer has been mapped */ smpl_vaddr = mmap(NULL, (size_t)buf_arg.buf_size, PROT_READ, MAP_PRIVATE, fd, 0); if (smpl_vaddr == MAP_FAILED) errx(1, "cannot mmap sampling buffer errno %d\n", errno); printf("Sampling buffer mapped at %p\n", smpl_vaddr); /* * Now prepare the argument to initialize the PMDs and PMCS. * We must pfp_pmc_count to determine the number of PMC to intialize. * We must use pfp_event_count to determine the number of PMD to initialize. * Some events causes extra PMCs to be used, so pfp_pmc_count may be >= pfp_event_count. * * This step is new compared to libpfm-2.x. It is necessary because the library no * longer knows about the kernel data structures. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } /* * figure out pmd mapping from output pmc */ for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * indicate we want notification when buffer is full */ pd[0].reg_flags |= PFM_REGFL_OVFL_NOTIFY; entry_size = sizeof(smpl_entry_t); /* * initialize the PMD and the sampling period */ pd[0].reg_value = - SMPL_PERIOD; pd[0].reg_long_reset = - SMPL_PERIOD; pd[0].reg_short_reset = - SMPL_PERIOD; /* * Now program the registers * * We don't use the save variable to indicate the number of elements passed to * the kernel because, as we said earlier, pc may contain more elements than * the number of events we specified, i.e., contains more thann coutning monitors. */ if (pfm_write_pmcs(fd, pc, outp.pfp_pmc_count)) errx(1, "pfm_write_pmcs error errno %d\n",errno); if (pfm_write_pmds(fd, pd, outp.pfp_pmd_count)) errx(1, "pfm_write_pmds error errno %d\n",errno); /* * attach context to stopped task */ load_args.load_pid = getpid(); if (pfm_load_context(fd, &load_args)) errx(1, "pfm_load_context error errno %d\n",errno); /* * setup asynchronous notification on the file descriptor */ ret = fcntl(fd, F_SETFL, fcntl(fd, F_GETFL, 0) | O_ASYNC); if (ret == -1) errx(1, "cannot set ASYNC: %s\n", strerror(errno)); /* * get ownership of the descriptor */ ret = fcntl(fd, F_SETOWN, getpid()); if (ret == -1) errx(1, "cannot setown: %s\n", strerror(errno)); /* * Let's roll now. */ ret = pfm_start(fd, NULL); if (ret == -1) errx(1, "cannot pfm_start: %s\n", strerror(errno)); while(nloop--) do_test(100000); ret = pfm_stop(fd); if (ret == -1) errx(1, "cannot pfm_stop: %s\n", strerror(errno)); /* * We must call the processing routine to cover the last entries recorded * in the sampling buffer, i.e. which may not be full */ process_smpl_buffer(); /* * let's stop this now */ munmap(smpl_vaddr, (size_t)buf_arg.buf_size); close(fd); return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/showevtinfo.c0000644000307100002310000001430213013651447022342 0ustar yarkhangraduate/* * showevtinfo.c - show event information * * Copyright (c) 2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #include #include #include #include #include #include #include #include #include #include static void fatal_error(char *fmt,...) __attribute__((noreturn)); static size_t max_len; static struct { int sort; uint64_t mask; } options; typedef struct { uint64_t code; int idx; } code_info_t; static char *name; static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } int compare_codes(const void *a, const void *b) { const code_info_t *aa = a; const code_info_t *bb = b; uint64_t m = options.mask; if ((aa->code & m) < (bb->code &m)) return -1; if ((aa->code & m) == (bb->code & m)) return 0; return 1; } static void show_event_info(char *name, unsigned int idx) { pfmlib_regmask_t cnt, impl_cnt; char *desc; unsigned int n1, n2, i, c; int code, prev_code = 0, first = 1; int ret; pfm_get_event_counters(idx, &cnt); pfm_get_num_counters(&n2); pfm_get_impl_counters(&impl_cnt); n1 = n2; printf("#-----------------------------\n" "Name : %s\n", name); pfm_get_event_description(idx, &desc); printf("Desc : %s\n", desc); free(desc); printf("Code :"); for (i=0; n1; i++) { if (pfm_regmask_isset(&impl_cnt, i)) n1--; if (pfm_regmask_isset(&cnt, i)) { pfm_get_event_code_counter(idx,i,&code); if (first == 1 || code != prev_code) { printf(" 0x%x", code); first = 0; } prev_code = code; } } putchar('\n'); n1 = n2; printf("Counters : [ "); for (i=0; n1; i++) { if (pfm_regmask_isset(&impl_cnt, i)) n1--; if (pfm_regmask_isset(&cnt, i)) printf("%d ", i); } puts("]"); pfm_get_num_event_masks(idx, &n1); for (i = 0; i < n1; i++) { ret = pfm_get_event_mask_name(idx, i, name, max_len+1); if (ret != PFMLIB_SUCCESS) continue; pfm_get_event_mask_description(idx, i, &desc); pfm_get_event_mask_code(idx, i, &c); printf("Umask-%02u : 0x%02x : [%s] : %s\n", i, c, name, desc); free(desc); } } static int show_info(regex_t *preg) { unsigned int i, count = 0, match = 0; int ret; pfm_get_num_events(&count); for(i=0; i < count; i++) { ret = pfm_get_event_name(i, name, max_len+1); /* skip unsupported events */ if (ret != PFMLIB_SUCCESS) continue; if (regexec(preg, name, 0, NULL, 0) == 0) { show_event_info(name, i); match++; } } return match; } static int show_info_sorted(regex_t *preg) { unsigned int i, n, count = 0, match = 0; int code, ret; code_info_t *codes = NULL; pfm_get_num_events(&count); codes = malloc(count * sizeof(*codes)); if (!codes) fatal_error("cannot allocate memory\n"); for(i=0, n = 0; i < count; i++, n++) { ret = pfm_get_event_code(i, &code); /* skip unsupported events */ if (ret != PFMLIB_SUCCESS) continue; codes[n].idx = i; codes[n].code = code; } qsort(codes, n, sizeof(*codes), compare_codes); for(i=0; i < n; i++) { ret = pfm_get_event_name(codes[i].idx, name, max_len+1); /* skip unsupported events */ if (ret != PFMLIB_SUCCESS) continue; if (regexec(preg, name, 0, NULL, 0) == 0) { show_event_info(name, codes[i].idx); match++; } } free(codes); return match; } static void usage(void) { printf("showevtinfo [-h] [-s] [-m mask]\n" "-L\t\tlist one event per line\n" "-h\t\tget help\n" "-s\t\tsort event by PMU and by code based on -m mask\n" "-m mask\t\thexadecimal event code mask, bits to match when sorting\n"); } #define MAX_PMU_NAME_LEN 32 int main(int argc, char **argv) { static char *argv_all[2] = { ".*", NULL }; char *endptr = NULL; char **args; int c, match; regex_t preg; char model[MAX_PMU_NAME_LEN]; while ((c=getopt(argc, argv,"hsm:")) != -1) { switch(c) { case 's': options.sort = 1; break; case 'm': options.mask = strtoull(optarg, &endptr, 16); if (*endptr) fatal_error("mask must be in hexadecimal\n"); break; case 'h': usage(); exit(0); default: fatal_error("unknown error"); } } if (pfm_initialize() != PFMLIB_SUCCESS) fatal_error("PMU model not supported by library\n"); if (options.mask == 0) options.mask = ~0; if (optind == argc) { args = argv_all; } else { args = argv + optind; } pfm_get_max_event_name_len(&max_len); name = malloc(max_len+1); if (name == NULL) fatal_error("cannot allocate name buffer\n"); if (argc == 1) *argv = ".*"; /* match everything */ else ++argv; pfm_get_pmu_name(model, MAX_PMU_NAME_LEN); printf("PMU model: %s\n", model); while(*args) { if (regcomp(&preg, *args, REG_ICASE|REG_NOSUB)) fatal_error("error in regular expression for event \"%s\"", *argv); if (options.sort) match = show_info_sorted(&preg); else match = show_info(&preg); if (match == 0) fatal_error("event %s not found", *args); args++; } regfree(&preg); free(name); return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/notify_self.c0000644000307100002310000002003613013651447022311 0ustar yarkhangraduate/* * notify_self.c - example of how you can use overflow notifications * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include "detect_pmcs.h" #define SMPL_PERIOD 1000000000ULL static volatile unsigned long notification_received; #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS static pfarg_pmd_t pd[NUM_PMDS]; static int ctx_fd; static char *event1_name; static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } static void warning(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); } static void sigio_handler(int n) { pfarg_msg_t msg; int fd = ctx_fd; int r; if (event1_name && pfm_read_pmds(fd, pd+1, 1) == -1) fatal_error("pfm_read_pmds: %s", strerror(errno)); retry: r = read(fd, &msg, sizeof(msg)); if (r != sizeof(msg)) { if(r == -1 && errno == EINTR) { warning("read interrupted, retrying\n"); goto retry; } fatal_error("cannot read overflow message: %s\n", strerror(errno)); } if (msg.type != PFM_MSG_OVFL) fatal_error("unexpected msg type: %d\n",msg.type); /* * increment our notification counter */ notification_received++; /* * XXX: risky to do printf() in signal handler! */ if (event1_name) printf("Notification %lu: %"PRIu64" %s ip=0x%llx\n", notification_received, pd[1].reg_value, event1_name, (unsigned long long)msg.pfm_ovfl_msg.msg_ovfl_ip); else printf("Notification %lu ip=0x%llx\n", notification_received, (unsigned long long)msg.pfm_ovfl_msg.msg_ovfl_ip); /* * And resume monitoring */ if (pfm_restart(fd) == -1) fatal_error("pfm_restart: %d\n", errno); } /* * infinite loop waiting for notification to get out */ void busyloop(void) { /* * busy loop to burn CPU cycles */ for(;notification_received < 3;) ; } #define BPL (sizeof(uint64_t)<<3) #define LBPL 6 static inline void pfm_bv_set(uint64_t *bv, uint16_t rnum) { bv[rnum>>LBPL] |= 1UL << (rnum&(BPL-1)); } int main(int argc, char **argv) { pfarg_ctx_t ctx; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfarg_pmc_t pc[NUM_PMCS]; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; struct sigaction act; unsigned int i, num_counters; size_t len; int ret; /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 1; /* set to 1 for verbose */ pfm_set_options(&pfmlib_options); /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) fatal_error("Cannot initialize library: %s\n", pfm_strerror(ret)); /* * Install the signal handler (SIGIO) */ memset(&act, 0, sizeof(act)); act.sa_handler = sigio_handler; sigaction (SIGIO, &act, 0); memset(pc, 0, sizeof(pc)); memset(&ctx, 0, sizeof(ctx)); memset(&load_args, 0, sizeof(load_args)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); pfm_get_num_counters(&num_counters); if (pfm_get_cycle_event(&inp.pfp_events[0]) != PFMLIB_SUCCESS) fatal_error("cannot find cycle event\n"); if (pfm_get_inst_retired_event(&inp.pfp_events[1]) != PFMLIB_SUCCESS) fatal_error("cannot find inst retired event\n"); i = 2; /* * set the default privilege mode for all counters: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; if (i > num_counters) { i = num_counters; printf("too many events provided (max=%d events), using first %d event(s)\n", num_counters, i); } inp.pfp_event_count = i; /* * how many counters we use */ if (i > 1) { pfm_get_max_event_name_len(&len); event1_name = malloc(len+1); if (event1_name == NULL) fatal_error("cannot allocate event name\n"); pfm_get_full_event_name(&inp.pfp_events[1], event1_name, len+1); } /* * now create the context for self monitoring/per-task */ ctx_fd = pfm_create_context(&ctx, NULL, NULL, 0); if (ctx_fd == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * build the pfp_unavail_pmcs bitmask by looking * at what perfmon has available. It is not always * the case that all PMU registers are actually available * to applications. For instance, on IA-32 platforms, some * registers may be reserved for the NMI watchdog timer. * * With this bitmap, the library knows which registers NOT to * use. Of source, it is possible that no valid assignement may * be possible if certina PMU registers are not available. */ detect_unavail_pmcs(ctx_fd, &inp.pfp_unavail_pmcs); /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) fatal_error("Cannot configure events: %s\n", pfm_strerror(ret)); /* * Now prepare the argument to initialize the PMDs and PMCS. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * We want to get notified when the counter used for our first * event overflows */ pd[0].reg_flags |= PFM_REGFL_OVFL_NOTIFY; /* * nothing to sample when only one counter */ if (inp.pfp_event_count > 1) pfm_bv_set(pd[0].reg_reset_pmds, pd[1].reg_num); /* * we arm the first counter, such that it will overflow * after SMPL_PERIOD events have been observed */ pd[0].reg_value = - SMPL_PERIOD; pd[0].reg_long_reset = - SMPL_PERIOD; pd[0].reg_short_reset = - SMPL_PERIOD; /* * Now program the registers */ if (pfm_write_pmcs(ctx_fd, pc, outp.pfp_pmc_count)) fatal_error("pfm_write_pmcs error errno %d\n",errno); if (pfm_write_pmds(ctx_fd, pd, outp.pfp_pmd_count)) fatal_error("pfm_write_pmds error errno %d\n",errno); /* * we want to monitor ourself */ load_args.load_pid = getpid(); if (pfm_load_context(ctx_fd, &load_args)) fatal_error("pfm_load_context error errno %d\n",errno); /* * setup asynchronous notification on the file descriptor */ ret = fcntl(ctx_fd, F_SETFL, fcntl(ctx_fd, F_GETFL, 0) | O_ASYNC); if (ret == -1) fatal_error("cannot set ASYNC: %s\n", strerror(errno)); /* * get ownership of the descriptor */ ret = fcntl(ctx_fd, F_SETOWN, getpid()); if (ret == -1) fatal_error("cannot setown: %s\n", strerror(errno)); /* * Let's roll now */ pfm_self_start(ctx_fd); busyloop(); pfm_self_stop(ctx_fd); /* * free our context */ close(ctx_fd); if (event1_name) free(event1_name); return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/detect_pmcs.h0000644000307100002310000000353413013651447022273 0ustar yarkhangraduate/* * detect_pmcs.h - detect unavailable PMD/PMC registers based on perfmon2 information * * Copyright (c) 2006-2007 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #ifndef __DETECT_PMCS_H__ #define __DETECT_PMCS_H__ #include /* * if no context exists, pass -1 for fd * if do not care about PMCS, pass r_pmcs as NULL * if do not care about PMDs, pass r_pmds as NULL */ extern int detect_unavail_pmu_regs(int fd, pfmlib_regmask_t *r_pmcs, pfmlib_regmask_t *r_pmds); static inline int detect_unavail_pmcs(int fd, pfmlib_regmask_t *r_pmcs) { return detect_unavail_pmu_regs(fd, r_pmcs, NULL); } #endif /* __DETECT_PMCS_H__ */ papi-5.5.1/src/libpfm-3.y/examples_v2.x/notify_self3.c0000644000307100002310000001777213013651447022411 0ustar yarkhangraduate/* * notify_self3.c - example of how you can use overflow notifications with no messages * * Copyright (c) 2002-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include "detect_pmcs.h" #define SMPL_PERIOD 1000000000ULL static volatile unsigned long notification_received; #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS static pfarg_pmd_t pd[NUM_PMDS]; static int ctx_fd; static char *event1_name; static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } static void sigio_handler(int n) { if (pfm_read_pmds(ctx_fd, pd+1, 1) == -1) { fatal_error("pfm_read_pmds: %s", strerror(errno)); } /* * we do not need to extract the overflow message, we know * where it is coming from. */ /* * increment our notification counter */ notification_received++; /* * XXX: risky to do printf() in signal handler! */ if (event1_name) printf("Notification %02lu: %"PRIu64" %s\n", notification_received, pd[1].reg_value, event1_name); else printf("Notification %02lu:\n", notification_received); /* * And resume monitoring */ if (pfm_restart(ctx_fd)) fatal_error("error pfm_restart: %d\n", errno); } /* * infinite loop waiting for notification to get out */ void busyloop(void) { /* * busy loop to burn CPU cycles */ for(;notification_received < 40;) ; } int main(int argc, char **argv) { int ret; pfarg_ctx_t ctx; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfarg_pmc_t pc[NUM_PMCS]; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; struct sigaction act; size_t len; unsigned int i, num_counters; /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 1; /* set to 1 for verbose */ pfm_set_options(&pfmlib_options); /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) fatal_error("Cannot initialize library: %s\n", pfm_strerror(ret)); /* * Install the signal handler (SIGIO) */ memset(&act, 0, sizeof(act)); act.sa_handler = sigio_handler; sigaction (SIGIO, &act, 0); memset(pc, 0, sizeof(pc)); memset(&ctx, 0, sizeof(ctx)); memset(&load_args, 0, sizeof(load_args)); memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); pfm_get_num_counters(&num_counters); if (pfm_get_cycle_event(&inp.pfp_events[0]) != PFMLIB_SUCCESS) fatal_error("cannot find cycle event\n"); if (pfm_get_inst_retired_event(&inp.pfp_events[1]) != PFMLIB_SUCCESS) fatal_error("cannot find inst retired event\n"); i = 2; /* * set the default privilege mode for all counters: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; if (i > num_counters) { i = num_counters; printf("too many events provided (max=%d events), using first %d event(s)\n", num_counters, i); } /* * how many counters we use */ inp.pfp_event_count = i; if (i > 1) { pfm_get_max_event_name_len(&len); event1_name = malloc(len+1); if (event1_name == NULL) fatal_error("cannot allocate event name\n"); pfm_get_full_event_name(&inp.pfp_events[1], event1_name, len+1); } /* * when we know we are self-monitoring and we have only one context, then * when we get an overflow we know where it is coming from. Therefore we can * save the call to the kernel to extract the notification message. By default, * a message is generated. The queue of messages has a limited size, therefore * it is important to clear the queue by reading the message on overflow. Failure * to do so may result in a queue full and you will lose notification messages. * * With the PFM_FL_OVFL_NO_MSG, no message will be queue, but you will still get * the signal. Similarly, the PFM_MSG_END will be generated. */ ctx.ctx_flags = PFM_FL_OVFL_NO_MSG; /* * now create the context for self monitoring/per-task */ ctx_fd = pfm_create_context(&ctx, NULL, NULL, 0); if (ctx_fd == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * build the pfp_unavail_pmcs bitmask by looking * at what perfmon has available. It is not always * the case that all PMU registers are actually available * to applications. For instance, on IA-32 platforms, some * registers may be reserved for the NMI watchdog timer. * * With this bitmap, the library knows which registers NOT to * use. Of source, it is possible that no valid assignement may * be possible if certina PMU registers are not available. */ detect_unavail_pmcs(ctx_fd, &inp.pfp_unavail_pmcs); /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) fatal_error("Cannot configure events: %s\n", pfm_strerror(ret)); /* * Now prepare the argument to initialize the PMDs and PMCS. */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } for (i=0; i < outp.pfp_pmd_count; i++) pd[i].reg_num = outp.pfp_pmds[i].reg_num; /* * We want to get notified when the counter used for our first * event overflows */ pd[0].reg_flags |= PFM_REGFL_OVFL_NOTIFY; if (inp.pfp_event_count > 1) pd[0].reg_reset_pmds[0] |= 1UL << pd[1].reg_num; /* * we arm the first counter, such that it will overflow * after SMPL_PERIOD events have been observed */ pd[0].reg_value = - SMPL_PERIOD; pd[0].reg_long_reset = - SMPL_PERIOD; pd[0].reg_short_reset = - SMPL_PERIOD; /* * Now program the registers */ if (pfm_write_pmcs(ctx_fd, pc, outp.pfp_pmc_count)) fatal_error("pfm_write_pmcs error errno %d\n",errno); if (pfm_write_pmds(ctx_fd, pd, outp.pfp_pmd_count)) fatal_error("pfm_write_pmds error errno %d\n",errno); /* * we want to monitor ourself */ load_args.load_pid = getpid(); if (pfm_load_context(ctx_fd, &load_args)) fatal_error("pfm_load_context error errno %d\n",errno); /* * setup asynchronous notification on the file descriptor */ ret = fcntl(ctx_fd, F_SETFL, fcntl(ctx_fd, F_GETFL, 0) | O_ASYNC); if (ret == -1) fatal_error("cannot set ASYNC: %s\n", strerror(errno)); /* * get ownership of the descriptor */ ret = fcntl(ctx_fd, F_SETOWN, getpid()); if (ret == -1) fatal_error("cannot setown: %s\n", strerror(errno)); /* * Let's roll now */ pfm_self_start(ctx_fd); busyloop(); pfm_self_stop(ctx_fd); /* * free our context */ close(ctx_fd); if (event1_name) free(event1_name); return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/rtop.c0000644000307100002310000006042613013651447020763 0ustar yarkhangraduate/* rtop.c - a simple PMU-based CPU utilization tool * * Copyright (c) 2004-2006 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _GNU_SOURCE #define _GNU_SOURCE /* for getline */ #endif #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "detect_pmcs.h" #define SWITCH_TIMEOUT 1000000000 /* in nanoseconds */ #define RTOP_VERSION "0.1" #define RTOP_MAX_CPUS 1024 /* maximum number of CPU supported */ #define MAX_EVT_NAME_LEN 128 #define RTOP_NUM_PMCS 4 #define RTOP_NUM_PMDS 4 /* * max number of cpus (threads) supported */ #define RTOP_MAX_CPUS 1024 /* MUST BE power of 2 */ #define RTOP_CPUMASK_BITS (sizeof(unsigned long)<<3) #define RTOP_CPUMASK_COUNT (RTOP_MAX_CPUS/RTOP_CPUMASK_BITS) #define RTOP_CPUMASK_SET(m, g) ((m)[(g)/RTOP_CPUMASK_BITS] |= (1UL << ((g) % RTOP_CPUMASK_BITS))) #define RTOP_CPUMASK_CLEAR(m, g) ((m)[(g)/RTOP_CPUMASK_BITS] &= ~(1UL << ((g) % RTOP_CPUMASK_BITS))) #define RTOP_CPUMASK_ISSET(m, g) ((m)[(g)/RTOP_CPUMASK_BITS] & (1UL << ((g) % RTOP_CPUMASK_BITS))) typedef unsigned long rtop_cpumask_t[RTOP_CPUMASK_COUNT]; typedef struct { struct { int opt_verbose; int opt_delay; /* refresh delay in second */ int opt_delay_set; } program_opt_flags; rtop_cpumask_t cpu_mask; /* which CPUs to use in system wide mode */ long online_cpus; long selected_cpus; unsigned long cpu_mhz; char *outfile; } program_options_t; #define opt_verbose program_opt_flags.opt_verbose #define opt_delay program_opt_flags.opt_delay #define opt_delay_set program_opt_flags.opt_delay_set typedef struct { char *name; unsigned int plm; } eventdesc_t; typedef enum { THREAD_STARTED, THREAD_RUN, THREAD_DONE, THREAD_ERROR } thread_state_t; typedef struct { pthread_t tid; /* logical thread identification */ long cpuid; unsigned int id; thread_state_t state; int is_last; sem_t his_sem; sem_t my_sem; FILE *fp; uint64_t nsamples; int has_msg; } thread_desc_t; typedef struct _setdesc_t { pfarg_pmc_t pc[RTOP_NUM_PMDS]; pfarg_pmd_t pd[RTOP_NUM_PMCS]; pfmlib_input_param_t inp; pfmlib_output_param_t outp; uint16_t set_id; uint32_t set_flags; uint32_t set_timeout; /* actual timeout */ int (*handler)(int fd, FILE *fp, thread_desc_t *td, struct _setdesc_t *my_sdesc); void *data; eventdesc_t *evt_desc; } setdesc_t; typedef struct _barrier { pthread_mutex_t mutex; pthread_cond_t cond; unsigned long counter; unsigned long max; unsigned long generation; /* avoid race condition on wake-up */ } barrier_t; typedef enum { SESSION_INIT, SESSION_RUN, SESSION_STOP, SESSION_ABORTED } session_state_t; typedef struct { uint64_t prev_k_cycles; uint64_t prev_u_cycles; } set0_data_t; static barrier_t barrier; static session_state_t session_state; static program_options_t options; static pfarg_ctx_t master_ctx; static thread_desc_t *thread_info; static struct termios saved_tty; static int time_to_quit; static int term_rows, term_cols; static eventdesc_t set0_evt[]={ { .name = "*", .plm = PFM_PLM0 }, { .name = "*", .plm = PFM_PLM3 }, { .name = NULL} }; static int handler_set0(int fd, FILE *fp, thread_desc_t *td, setdesc_t *my_sdesc); static setdesc_t setdesc_tab[]={ { .set_id = 0, .evt_desc = set0_evt, .handler = handler_set0 } }; #define RTOP_NUM_SDESC (sizeof(setdesc_tab)/sizeof(setdesc_t)) static int barrier_init(barrier_t *b, unsigned long count) { int r; r = pthread_mutex_init(&b->mutex, NULL); if (r == -1) return -1; r = pthread_cond_init(&b->cond, NULL); if (r == -1) return -1; b->max = b->counter = count; b->generation = 0; return 0; } static void cleanup_barrier(void *arg) { int r; barrier_t *b = (barrier_t *)arg; r = pthread_mutex_unlock(&b->mutex); (void)r; } static int barrier_wait(barrier_t *b) { unsigned long generation; int oldstate; pthread_cleanup_push(cleanup_barrier, b); pthread_mutex_lock(&b->mutex); pthread_testcancel(); if (--b->counter == 0) { /* reset barrier */ b->counter = b->max; /* * bump generation number, this avoids thread getting stuck in the * wake up loop below in case a thread just out of the barrier goes * back in right away before all the thread from the previous "round" * have "escaped". */ b->generation++; pthread_cond_broadcast(&b->cond); } else { generation = b->generation; pthread_setcancelstate(PTHREAD_CANCEL_ENABLE, &oldstate); while (b->counter != b->max && generation == b->generation) { pthread_cond_wait(&b->cond, &b->mutex); } pthread_setcancelstate(oldstate, NULL); } pthread_mutex_unlock(&b->mutex); pthread_cleanup_pop(0); return 0; } static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void warning(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); } static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } int gettid(void) { int tmp; tmp = syscall(__NR_gettid); return tmp; } #ifndef __NR_sched_setaffinity #error "you need to define __NR_sched_setaffinity" #endif /* * Hack to get this to work without libc support */ int pin_self_cpu(unsigned int cpu) { unsigned long my_mask; my_mask = 1UL << cpu; return syscall(__NR_sched_setaffinity, gettid(), sizeof(my_mask), &my_mask); } static void sigint_handler(int n) { time_to_quit = 1; } static unsigned long find_cpu_speed(void) { FILE *fp1; unsigned long f1 = 0, f2 = 0; char buffer[128], *p, *value; memset(buffer, 0, sizeof(buffer)); fp1 = fopen("/proc/cpuinfo", "r"); if (fp1 == NULL) return 0; for (;;) { buffer[0] = '\0'; p = fgets(buffer, 127, fp1); if (p == NULL) break; /* skip blank lines */ if (*p == '\n') continue; p = strchr(buffer, ':'); if (p == NULL) break; /* * p+2: +1 = space, +2= firt character * strlen()-1 gets rid of \n */ *p = '\0'; value = p+2; value[strlen(value)-1] = '\0'; if (!strncasecmp("cpu MHz", buffer, 7)) { float fl; sscanf(value, "%f", &fl); f1 = lroundf(fl); break; } if (!strncasecmp("BogoMIPS", buffer, 8)) { float fl; sscanf(value, "%f", &fl); f2 = lroundf(fl); } } fclose(fp1); return f1 == 0 ? f2 : f1; } static void get_term_size(void) { int ret; struct winsize ws; ret = ioctl(1, TIOCGWINSZ, &ws); if (ret == -1) fatal_error("cannot determine screen size\n"); if (ws.ws_row > 10) { term_cols = ws.ws_col; term_rows = ws.ws_row; } else { term_cols = 80; term_rows = 24; } if (term_rows < options.selected_cpus) fatal_error("you need at least %ld rows on your terminal to display all CPUs\n", options.selected_cpus); } static void sigwinch_handler(int n) { get_term_size(); } static void setup_screen(void) { int ret; ret = tcgetattr(0, &saved_tty); if (ret == -1) fatal_error("cannot save tty settings\n"); get_term_size(); initscr(); nocbreak(); resizeterm(term_rows, term_cols); } static void close_screen(void) { int ret; endwin(); ret = tcsetattr(0, TCSAFLUSH, &saved_tty); if (ret == -1) warning("cannot restore tty settings\n"); } static void setup_signals(void) { struct sigaction act; sigset_t my_set; /* * SIGINT is a asynchronous signal * sent to the process (not a specific thread). POSIX states * that one and only one thread will execute the handler. This * could be any thread that does not have the signal blocked. */ /* * install SIGINT handler */ memset(&act,0,sizeof(act)); sigemptyset(&my_set); act.sa_handler = (__sighandler_t)sigint_handler; sigaction (SIGINT, &act, 0); /* * install SIGWINCH handler */ memset(&act,0,sizeof(act)); sigemptyset(&my_set); act.sa_handler = (__sighandler_t)sigwinch_handler; sigaction (SIGWINCH, &act, 0); } static void setup_worker_signals(void) { struct sigaction act; sigset_t my_set; /* * SIGINT is a asynchronous signal * sent to the process (not a specific thread). POSIX states * that one and only one thread will execute the handler. This * could be any thread that does not have the signal blocked. */ /* * block SIGINT, forcing it to master thread only */ memset(&act,0,sizeof(act)); sigemptyset(&my_set); sigaddset(&my_set, SIGINT); sigaddset(&my_set, SIGWINCH); pthread_sigmask(SIG_BLOCK, &my_set, NULL); } static struct option rtop_cmd_options[]={ { "help", 0, 0, 1 }, { "version", 0, 0, 2 }, { "delay", 0, 0, 3 }, { "cpu-list", 1, 0, 4 }, { "outfile", 1, 0, 5 }, { "verbose", 0, &options.opt_verbose, 1 }, { 0, 0, 0, 0} }; int handler_set0(int fd, FILE *fp, thread_desc_t *td, setdesc_t *my_sdesc) { double k_cycles, u_cycles, i_cycles; set0_data_t *sd1; uint64_t itc_delta; long mycpu; mycpu = td->cpuid; if (my_sdesc->data == NULL) { my_sdesc->data = sd1 = calloc(1, sizeof(set0_data_t)); if (sd1 == NULL) return -1; } sd1 = my_sdesc->data; /* * now read the results */ if (pfm_read_pmds(fd, my_sdesc->pd, my_sdesc->inp.pfp_event_count) == -1) { warning( "CPU%ld pfm_read_pmds error errno %d\n", mycpu, errno); return -1; } /* * expected maximum duration with monitoring active for this set * set_timeout is in nanoseconds, we need to divide mhz by 1000 * to get cycles. */ itc_delta = (my_sdesc->set_timeout*(uint64_t)options.cpu_mhz)/1000; k_cycles = (double)(my_sdesc->pd[0].reg_value - sd1->prev_k_cycles)*100.0/ (double)itc_delta; u_cycles = (double)(my_sdesc->pd[1].reg_value - sd1->prev_u_cycles)*100.0/ (double)itc_delta; i_cycles = 100.0 - (k_cycles + u_cycles); /* * adjust for rounding errors */ if (i_cycles < 0.0) i_cycles = 0.0; if (i_cycles > 100.0) i_cycles = 100.0; if (k_cycles > 100.0) k_cycles = 100.0; if (u_cycles > 100.0) u_cycles = 100.0; printw("CPU%-2ld %6.2f%% usr %6.2f%% sys %6.2f%% idle\n", mycpu, u_cycles, k_cycles, i_cycles); sd1->prev_k_cycles = my_sdesc->pd[0].reg_value; sd1->prev_u_cycles = my_sdesc->pd[1].reg_value; if (fp) fprintf(fp, "%"PRIu64" %6.2f %6.2f %6.2f\n", td->nsamples, u_cycles, k_cycles, i_cycles); td->nsamples++; return 0; } static void do_measure_one_cpu(void *data) { thread_desc_t *arg= (thread_desc_t *)data; pfarg_ctx_t ctx; pfarg_load_t load_args; pfarg_setdesc_t setd; setdesc_t *my_sdesc, *my_sdesc_tab = NULL; long mycpu; sem_t *his_sem; unsigned int id; int fd, ret, j; int old_rows; char cpu_str[16]; char *fn; FILE *fp = NULL; setup_worker_signals(); mycpu = arg->cpuid; id = arg->id; his_sem = &arg->his_sem; old_rows = term_rows; if (options.outfile) { sprintf(cpu_str,".cpu%ld", mycpu); fn = malloc(strlen(options.outfile)+1+strlen(cpu_str)); if (fn == NULL) goto error; strcpy(fn, options.outfile); strcat(fn, cpu_str); fp = fopen(fn, "w"); if (fp == NULL) { warning("cannot open %s\n", fn); free(fn); goto error; } free(fn); fprintf(fp, "# Results for CPU%ld\n" "# sample delay %d seconds\n" "# Column1 : sample number\n" "# Column2 : %% user time\n" "# Column3 : %% system time\n" "# Column4 : %% idle\n" "# Column5 : kernel entry-exit\n", mycpu, options.opt_delay); } memset(&load_args, 0, sizeof(load_args)); memset(&setd, 0, sizeof(setd)); ret = pin_self_cpu(mycpu); if (ret) { warning("CPU%ld cannot pin\n"); } ctx = master_ctx; my_sdesc_tab = malloc(sizeof(setdesc_t)*RTOP_NUM_SDESC); if (my_sdesc_tab == NULL) { warning("CPU%ld cannot allocate sdesc\n", mycpu); goto error; } memcpy(my_sdesc_tab, setdesc_tab, sizeof(setdesc_t)*RTOP_NUM_SDESC); fd = pfm_create_context(&ctx, NULL, NULL, 0); if (fd == -1) { if (errno == ENOSYS) { fatal_error("Your kernel does not have performance monitoring support!\n"); } warning("CPU%ld cannot create context: %d\n", mycpu, errno); goto error; } /* * WARNING: on processors where the idle loop goes into some power-saving * state, the results of this program may be incorrect */ for(j=0; j < RTOP_NUM_SDESC; j++) { my_sdesc = my_sdesc_tab+j; setd.set_id = my_sdesc->set_id; setd.set_flags = my_sdesc->set_flags; setd.set_timeout = SWITCH_TIMEOUT; /* in nsecs */ /* * do not bother if we have only one set */ if (RTOP_NUM_SDESC > 1 && pfm_create_evtsets(fd, &setd, 1) == -1) { warning("CPU%ld cannot create set%u: %d\n", mycpu, j, errno); goto error; } my_sdesc->set_timeout = setd.set_timeout; if (pfm_write_pmcs(fd, my_sdesc->pc, my_sdesc->outp.pfp_pmc_count) == -1) { warning("CPU%ld pfm_write_pmcs error errno %d\n", mycpu, errno); goto error; } /* * To be read, each PMD must be either written or declared * as being part of a sample (reg_smpl_pmds) */ if (pfm_write_pmds(fd, my_sdesc->pd, my_sdesc->inp.pfp_event_count) == -1) { warning("CPU%ld pfm_write_pmds error errno %d\n", mycpu, errno); goto error; } } /* * in system-wide mode, this field must provide the CPU the caller wants * to monitor. The kernel checks and if calling from the wrong CPU, the * call fails. The affinity is not affected. */ load_args.load_pid = mycpu; if (pfm_load_context(fd, &load_args) == -1) { warning("CPU%ld pfm_load_context error errno %d\n", mycpu, errno); goto error; } thread_info[id].state = THREAD_RUN; barrier_wait(&barrier); /* * must wait until we are sure the master is out of its thread_create loop */ barrier_wait(&barrier); for(;session_state == SESSION_RUN;) { if (pfm_start(fd, NULL) == -1) { warning("CPU%ld pfm_start error errno %d\n", mycpu, errno); goto error; } /* * wait for order from master */ sem_wait(his_sem); if (pfm_stop(fd) == -1) { warning("CPU%ld pfm_stop error %d\n", mycpu, errno); goto error; } if (old_rows != term_rows) { resizeterm(term_rows, term_cols); old_rows = term_rows; } for(j=0; j < RTOP_NUM_SDESC; j++) { move(id*RTOP_NUM_SDESC+j, 0); if (my_sdesc_tab[j].handler) (*my_sdesc_tab[j].handler)(fd, fp, arg, my_sdesc_tab+j); } if (session_state == SESSION_RUN) { sem_post(&arg->my_sem); barrier_wait(&barrier); } } if (fp) fclose(fp); close(fd); thread_info[id].state = THREAD_DONE; pthread_exit((void *)(0)); error: thread_info[id].state = THREAD_ERROR; barrier_wait(&barrier); if (fp) fclose(fp); if (my_sdesc_tab) free(my_sdesc_tab); pthread_exit((void *)(~0)); } static void mainloop(void) { long i, j, ncpus = 0; int ret; void *retval; struct pollfd fds; ncpus = options.selected_cpus; barrier_init(&barrier, ncpus+1); thread_info = malloc(sizeof(thread_desc_t)*ncpus); if (thread_info == NULL) { fatal_error("cannot allocate thread_desc for %ld CPUs\n", ncpus); } for(i=0, j = 0; ncpus; i++) { if (RTOP_CPUMASK_ISSET(options.cpu_mask, i) == 0) continue; thread_info[j].id = j; thread_info[j].cpuid = i; sem_init(&thread_info[j].his_sem, 0, 0); sem_init(&thread_info[j].my_sem, 0, 0); ret = pthread_create(&thread_info[j].tid, NULL, (void *(*)(void *))do_measure_one_cpu, (void *)(thread_info+j)); if (ret != 0) goto abort; ncpus--; j++; } /* set last marker */ thread_info[j-1].is_last = 1; ncpus = j; barrier_wait(&barrier); /* * check if some threads got problems */ for(i=0; i < ncpus ; i++) { if (thread_info[i].state == THREAD_ERROR) { printw("aborting\n"); refresh(); goto abort; } } session_state = SESSION_RUN; barrier_wait(&barrier); fds.fd = 0; fds.events = POLLIN; fds.revents = 0; for(;time_to_quit == 0;) { ret = poll(&fds, 1, options.opt_delay*1000); switch(ret) { case 0: for(i=0; i < ncpus ; i++) { /* give order to print */ sem_post(&thread_info[i].his_sem); /* wait for thread to be done */ sem_wait(&thread_info[i].my_sem); } /* give order to start measuring again */ refresh(); barrier_wait(&barrier); break; case -1: /* restart in case of signal */ if (errno == EINTR) continue; warning("polling error: %s\n", strerror(errno)); /* fall through */ default: time_to_quit = 1; } } session_state = SESSION_STOP; /* * get worker thread out of their mainloop */ for (i=0; i < ncpus; i++) sem_post(&thread_info[i].his_sem); join_all: for(i=0; i< ncpus; i++) { ret = pthread_join(thread_info[i].tid, &retval); if (ret !=0) fatal_error("cannot join thread %ld\n", i); } free(thread_info); return; abort: session_state = SESSION_ABORTED; for(i=0; i < ncpus; i++) { pthread_cancel(thread_info[i].tid); } goto join_all; } static void setup_measurement(void) { pfmlib_options_t pfmlib_options; eventdesc_t *evt; setdesc_t *sdesc; pfmlib_event_t trigger_event; unsigned int i, j; int ret; /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; pfmlib_options.pfm_verbose = 0; pfm_set_options(&pfmlib_options); /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) fatal_error("Cannot initialize library: %s\n", pfm_strerror(ret)); /* * In system wide mode, the perfmon context cannot be inherited. * Also in this mode, we cannot use the blocking form of user level notification. */ master_ctx.ctx_flags = PFM_FL_SYSTEM_WIDE; if (pfm_get_cycle_event(&trigger_event) != PFMLIB_SUCCESS) fatal_error("cannot find cycle event for trigger\n"); for(i=0; i < RTOP_NUM_SDESC; i++) { sdesc = setdesc_tab+i; sdesc->inp.pfp_dfl_plm = PFM_PLM3|PFM_PLM0; /* * indicate we are using the monitors for a system-wide session. * This may impact the way the library sets up the PMC values. */ sdesc->inp.pfp_flags = PFMLIB_PFP_SYSTEMWIDE; evt = sdesc->evt_desc; for(j=0; evt[j].name ; j++) { if (*evt[j].name == '*') sdesc->inp.pfp_events[j] = trigger_event; else if (pfm_find_full_event(evt[j].name, &sdesc->inp.pfp_events[j]) != PFMLIB_SUCCESS) fatal_error("cannot find %s event\n", evt[j].name); sdesc->inp.pfp_events[j].plm = evt[j].plm; } /* * how many counters we use in this set (add the overflow trigger) */ sdesc->inp.pfp_event_count = j; /* * build the pfp_unavail_pmcs bitmask by looking * at what perfmon has available. It is not always * the case that all PMU registers are actually available * to applications. For instance, on IA-32 platforms, some * registers may be reserved for the NMI watchdog timer. * * With this bitmap, the library knows which registers NOT to * use. Of source, it is possible that no valid assignement may * be possible if certina PMU registers are not available. */ detect_unavail_pmcs(-1, &sdesc->inp.pfp_unavail_pmcs); /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&sdesc->inp, NULL, &sdesc->outp, NULL)) != PFMLIB_SUCCESS) fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); for (j=0; j < sdesc->outp.pfp_pmc_count; j++) { sdesc->pc[j].reg_set = i; sdesc->pc[j].reg_num = sdesc->outp.pfp_pmcs[j].reg_num; sdesc->pc[j].reg_value = sdesc->outp.pfp_pmcs[j].reg_value; } for (j=0; j < sdesc->outp.pfp_pmd_count; j++) { sdesc->pd[j].reg_num = sdesc->outp.pfp_pmds[j].reg_num; sdesc->pd[j].reg_set = i; } } } void populate_cpumask(char *cpu_list) { char *p; unsigned long start_cpu, end_cpu = 0; unsigned long i, count = 0; options.online_cpus = sysconf(_SC_NPROCESSORS_ONLN); if (options.online_cpus == -1) fatal_error("cannot figure out the number of online processors\n"); if (cpu_list == NULL) { /* * The limit is mostly driven by the affinity support in NPTL and glibc __CPU_SETSIZE. * the kernel interface does not expose any limitation. */ if (options.online_cpus >= RTOP_MAX_CPUS) fatal_error("rtop can only handle to %u CPUs\n", RTOP_MAX_CPUS); for(i=0; i < options.online_cpus; i++) { RTOP_CPUMASK_SET(options.cpu_mask, i); } options.selected_cpus = options.online_cpus; return; } while(isdigit(*cpu_list)) { p = NULL; start_cpu = strtoul(cpu_list, &p, 0); /* auto-detect base */ if (start_cpu == ULONG_MAX || (*p != '\0' && *p != ',' && *p != '-')) goto invalid; if (p && *p == '-') { cpu_list = ++p; p = NULL; end_cpu = strtoul(cpu_list, &p, 0); /* auto-detect base */ if (end_cpu == ULONG_MAX || (*p != '\0' && *p != ',')) goto invalid; if (end_cpu < start_cpu) goto invalid_range; } else { end_cpu = start_cpu; } if (start_cpu >= RTOP_MAX_CPUS || end_cpu >= RTOP_MAX_CPUS) goto too_big; for (; start_cpu <= end_cpu; start_cpu++) { if (start_cpu >= options.online_cpus) goto not_online; /* XXX: assume contiguous range of CPUs */ if (RTOP_CPUMASK_ISSET(options.cpu_mask, start_cpu)) continue; RTOP_CPUMASK_SET(options.cpu_mask, start_cpu); count++; } if (*p) ++p; cpu_list = p; } options.selected_cpus = count; return; invalid: fatal_error("invalid cpu list argument: %s\n", cpu_list); /* no return */ not_online: fatal_error("cpu %lu is not online\n", start_cpu); /* no return */ invalid_range: fatal_error("cpu range %lu - %lu is invalid\n", start_cpu, end_cpu); /* no return */ too_big: fatal_error("rtop is limited to %u CPUs\n", RTOP_MAX_CPUS); /* no return */ } static void usage(void) { printf( "usage: rtop [options]:\n" "-h, --help\t\t\tdisplay this help and exit\n" "-v, --verbose\t\t\tverbose output\n" "-V, --version\t\t\tshow version and exit\n" "-d nsec, --delay=nsec\t\tnumber of seconds between refresh (default=1s)\n" "--cpu-list=cpu1,cpu2\t\tlist of CPUs to monitor(default=all)\n" ); } int main(int argc, char **argv) { int c; char *cpu_list = NULL; while ((c=getopt_long(argc, argv,"+vhVd:", rtop_cmd_options, 0)) != -1) { switch(c) { case 0: continue; /* fast path for options */ case 'v': options.opt_verbose = 1; break; case 1: case 'h': usage(); exit(0); case 2: case 'V': printf("rtop version " RTOP_VERSION " Date: " __DATE__ "\n" "Copyright (C) 2004 Hewlett-Packard Company\n"); exit(0); case 3: case 'd': if (options.opt_delay_set) fatal_error("cannot set delay twice\n"); options.opt_delay = atoi(optarg); if (options.opt_delay < 0) { fatal_error("invalid delay, must be >= 0\n"); } options.opt_delay_set = 1; break; case 4: if (cpu_list) fatal_error("cannot specify --cpu-list more than once\n"); if (*optarg == '\0') fatal_error("--cpu-list needs an argument\n"); cpu_list = optarg; break; case 5: if (options.outfile) fatal_error("cannot specify --outfile more than once\n"); if (*optarg == '\0') fatal_error("--outfile needs an argument\n"); options.outfile = optarg; break; default: fatal_error("unknown option\n"); } } /* * default refresh delay */ if (options.opt_delay_set == 0) options.opt_delay = 1; options.cpu_mhz = find_cpu_speed(); populate_cpumask(cpu_list); setup_measurement(); setup_signals(); setup_screen(); mainloop(); close_screen(); return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/self.c0000644000307100002310000001577313013651447020735 0ustar yarkhangraduate/* * self.c - example of a simple self monitoring task * * Copyright (c) 2002-2007 Hewlett-Packard Development Company, L.P. * Contributed by Stephane Eranian * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * This file is part of libpfm, a performance monitoring support library for * applications on Linux. */ #include #include #include #include #include #include #include #include #include #include #include #include "detect_pmcs.h" #define NUM_PMCS PFMLIB_MAX_PMCS #define NUM_PMDS PFMLIB_MAX_PMDS static volatile int quit; void sig_handler(int n) { quit = 1; } /* * our test code (function cannot be made static otherwise it is optimized away) */ void noploop(void) { for(;quit == 0;); } static void fatal_error(char *fmt,...) __attribute__((noreturn)); static void fatal_error(char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(stderr, fmt, ap); va_end(ap); exit(1); } int main(int argc, char **argv) { char **p; unsigned int i; int ret, ctx_fd; pfmlib_input_param_t inp; pfmlib_output_param_t outp; pfarg_pmd_t pd[NUM_PMDS]; pfarg_pmc_t pc[NUM_PMCS]; pfarg_ctx_t ctx; pfarg_load_t load_args; pfmlib_options_t pfmlib_options; unsigned int num_counters; size_t len; char *name; /* * pass options to library (optional) */ memset(&pfmlib_options, 0, sizeof(pfmlib_options)); pfmlib_options.pfm_debug = 0; /* set to 1 for debug */ pfmlib_options.pfm_verbose = 1; /* set to 1 for verbose */ pfm_set_options(&pfmlib_options); /* * Initialize pfm library (required before we can use it) */ ret = pfm_initialize(); if (ret != PFMLIB_SUCCESS) fatal_error("Cannot initialize library: %s\n", pfm_strerror(ret)); pfm_get_max_event_name_len(&len); name = malloc(len+1); if (!name) fatal_error("cannot allocate event name buffer\n"); pfm_get_num_counters(&num_counters); memset(pd, 0, sizeof(pd)); memset(pc, 0, sizeof(pc)); memset(&ctx, 0, sizeof(ctx)); memset(&load_args, 0, sizeof(load_args)); /* * prepare parameters to library. */ memset(&inp,0, sizeof(inp)); memset(&outp,0, sizeof(outp)); /* * be nice to user! */ if (argc > 1) { p = argv+1; for (i=0; *p ; i++, p++) { ret = pfm_find_full_event(*p, &inp.pfp_events[i]); if (ret != PFMLIB_SUCCESS) fatal_error("event %s: %s\n", *p, pfm_strerror(ret)); } } else { if (pfm_get_cycle_event(&inp.pfp_events[0]) != PFMLIB_SUCCESS) fatal_error("cannot find cycle event\n"); if (pfm_get_inst_retired_event(&inp.pfp_events[1]) != PFMLIB_SUCCESS) fatal_error("cannot find inst retired event\n"); i = 2; } /* * set the default privilege mode for all counters: * PFM_PLM3 : user level only */ inp.pfp_dfl_plm = PFM_PLM3; if (i > num_counters) { i = num_counters; printf("too many events provided (max=%d events), using first %d event(s)\n", num_counters, i); } /* * how many counters we use */ inp.pfp_event_count = i; /* * now create a new context, per process context. * This just creates a new context with some initial state, it is not * active nor attached to any process. */ ctx_fd = pfm_create_context(&ctx, NULL, NULL, 0); if (ctx_fd == -1) { if (errno == ENOSYS) fatal_error("Your kernel does not have performance monitoring support!\n"); fatal_error("Can't create PFM context %s\n", strerror(errno)); } /* * build the pfp_unavail_pmcs bitmask by looking * at what perfmon has available. It is not always * the case that all PMU registers are actually available * to applications. For instance, on IA-32 platforms, some * registers may be reserved for the NMI watchdog timer. * * With this bitmap, the library knows which registers NOT to * use. Of source, it is possible that no valid assignement may * be possible if certain PMU registers are not available. */ detect_unavail_pmcs(ctx_fd, &inp.pfp_unavail_pmcs); printf("una=0x%lx\n", inp.pfp_unavail_pmcs.bits[0]); /* * let the library figure out the values for the PMCS */ if ((ret=pfm_dispatch_events(&inp, NULL, &outp, NULL)) != PFMLIB_SUCCESS) fatal_error("cannot configure events: %s\n", pfm_strerror(ret)); /* * Now prepare the argument to initialize the PMDs and PMCS. * We use pfp_pmc_count to determine the number of PMC to intialize. * We use pfp_pmd_count to determine the number of PMD to initialize. * Some events/features may cause extra PMCs to be used, leading to: * - pfp_pmc_count may be >= pfp_event_count * - pfp_pmd_count may be >= pfp_event_count */ for (i=0; i < outp.pfp_pmc_count; i++) { pc[i].reg_num = outp.pfp_pmcs[i].reg_num; pc[i].reg_value = outp.pfp_pmcs[i].reg_value; } for (i=0; i < outp.pfp_pmd_count; i++) { pd[i].reg_num = outp.pfp_pmds[i].reg_num; } /* * Now program the registers */ if (pfm_write_pmcs(ctx_fd, pc, outp.pfp_pmc_count)) fatal_error("pfm_write_pmcs error errno %d\n",errno); if (pfm_write_pmds(ctx_fd, pd, outp.pfp_pmd_count)) fatal_error("pfm_write_pmds error errno %d\n",errno); /* * now we load (i.e., attach) the context to ourself */ load_args.load_pid = getpid(); if (pfm_load_context(ctx_fd, &load_args)) fatal_error("pfm_load_context error errno %d\n",errno); /* * Let's roll now */ if (pfm_start(ctx_fd, NULL)) fatal_error("pfm_start error errno %d\n",errno); signal(SIGALRM, sig_handler); alarm(10); noploop(); if (pfm_stop(ctx_fd)) fatal_error("pfm_stop error errno %d\n",errno); /* * now read the results. We use pfp_event_count because * libpfm guarantees that counters for the events always * come first. */ if (pfm_read_pmds(ctx_fd, pd, inp.pfp_event_count)) fatal_error( "pfm_read_pmds error errno %d\n",errno); /* * print the results */ for (i=0; i < inp.pfp_event_count; i++) { pfm_get_full_event_name(&inp.pfp_events[i], name, len+1); printf("PMD%-3u %20"PRIu64" %s\n", pd[i].reg_num, pd[i].reg_value, name); } free(name); /* * and destroy our context */ close(ctx_fd); return 0; } papi-5.5.1/src/libpfm-3.y/examples_v2.x/pfmsetup.c0000644000307100002310000013640413013651447021642 0ustar yarkhangraduate/* * (C) Copyright IBM Corp. 2006 * Contributed by Kevin Corry * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sellcopies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * * pfmsetup * * Very simple command-line tool to drive the perfmon2 kernel API. Inspired * by the dmsetup tool from device-mapper. * * Compile with: * gcc -Wall -o pfmsetup pfmsetup.c -lpfm * * Run with: * pfmsetup * * Available commands for the command_file: * * create_context [options] * Create a new context for accessing the performance counters. Each new * context automatically gets one event-set with an ID of 0. * - options: --system * --no-overflow-msg * --block-on-notify * --sampler * - : specify an integer that you want to associate with * the new context for use in other commands. * * load_context * Attach the specified context and event-set to the specified program. * - : ID that you specified when creating the context. * - : ID that you specified when creating an event-set * within the given context. All contexts automatically * have an event-set with ID of 0. * - : ID that you specified when starting a program * with the run_program command, or the number of * the CPU to attach to for system-wide mode. * * unload_context * Detach the specified context from the program that it's currently * attached to. * - : ID that you specified when creating the context. * * close_context * Clean up the specified context. After this call, the context_id will no * longer be valid. * - : ID that you specified when creating the context. * * write_pmc < >+ * Write one or more control register values. * - : ID that you specified when creating the context. * - : ID that you specified when creating an event-set * within the given context. All contexts automatically * have an event-set with ID of 0. * - : ID of the desired control register. See the register * mappings in the Perfmon kernel code to determine which * PMC represents the control register you're interested in. * - : Value to write into the specified PMC. You need to know * the exact numeric value - no translations are done from * event names or masks. Multiple PMC id/value pairs can * be given in one write_pmc command. * * write_pmd < >+ * Write one or more data register values. * - : ID that you specified when creating the context. * - : ID that you specified when creating an event-set * within the given context. All contexts automatically * have an event-set with ID of 0. * - : ID of the desired data register. See the register * mappings in the Perfmon kernel code to determine which * PMD represents the control register you're interested in. * - : Value to write into the specified PMD. Multiple PMD * id/value pairs can be given in one write_pmd command. * * read_pmd + * Read one or more data register values. * - : ID that you specified when creating the context. * - : ID that you specified when creating an event-set * within the given context. All contexts automatically * have an event-set with ID of 0. * - : ID of the desired data register. See the register * mappings in the Perfmon kernel code to determine which * PMD represents the control register you're interested in. * Multiple PMD IDs can be given in one read_pmd command. * * start_counting * Start counting using the specified context and event-set. * - : ID that you specified when creating the context. * - : ID that you specified when creating an event-set * within the given context. All contexts automatically * have an event-set with ID of 0. * * stop_counting * Stop counting on the specified context. * - : ID that you specified when creating the context. * * restart_counting * Restart counting on the specified context. * - : ID that you specified when creating the context. * * create_eventset [options] * Create a new event-set for an existing context. * - options: --next-set * --timeout * --switch-on-overflow * --exclude-idle * - : ID that you specified when creating the context. * - : specify an integer that you want to associate with * the new event-set for use in other commands. * * delete_eventset * Delete an existing event-set from an existing context. * - : ID that you specified when creating the context. * - : ID that you specified when creating the event-set. * * getinfo_eventset * Display information about an event-set. * - : ID that you specified when creating the context. * - : ID that you specified when creating the event-set. * * run_program * First step in starting a program to monitor. In order to allow time to * set up the counters to monitor the program, this command only forks a * child process. It then suspends itself using ptrace. You must call the * resume_program command to wake up the new child process and exec the * desired program. * - : Specify an integer that you want to associate with * the program for use in other commands. * - : Specify the program and its arguments * exactly as you would on the command * line. * * resume_program * When a program is 'run', a child process is forked, but the child is * ptrace'd before exec'ing the specified program. This gives you time to * do any necessary setup to monitor the program. This resume_program * command wakes up the child process and finishes exec'ing the desired * program. If a context has been loaded and started for this program, * then the counters will have actually started following this command. * - : ID that you specified when starting the program. * * wait_on_program * Wait for a program to complete and exit. After this call, the program_id * will no longer be valid. * - : ID that you specified when starting the program. * * sleep #include #include #include #include #include #include #include #include #include #include #include #define FALSE 0 #define TRUE 1 #define WHITESPACE " \t\n" #define MAX_TOKENS 32 #define PFMSETUP_NAME "pfmsetup" #define USAGE(f, x...) printf(PFMSETUP_NAME ": USAGE: " f "\n" , ## x) #define LOG_ERROR(f, x...) printf(PFMSETUP_NAME ": Error: %s: " f "\n", __FUNCTION__ , ## x) #define LOG_INFO(f, x...) printf(PFMSETUP_NAME ": " f "\n" , ## x) typedef int (*command_fn)(int argc, char **argv); struct command { const char *full_name; const char *short_name; const char *help; command_fn fn; int min_args; }; struct context { int id; int fd; int cpu; pfarg_ctx_t ctx_arg; pfm_dfl_smpl_arg_t smpl_arg; struct event_set *event_sets; struct context *next; }; struct event_set { int id; struct event_set *next; }; struct program { int id; pid_t pid; struct program *next; }; /* Global list of all contexts that have been created. List is ordered by * context id. Each context contains a list of event-sets belonging to that * context, which is ordered by event-set id. */ static struct context *contexts = NULL; /* Global list of all programs that have been started. * List is ordered by program id. */ static struct program *programs = NULL; /* * Routines to manipulate the context, event-set, and program lists. */ static struct context *find_context(int ctx_id) { struct context *ctx; for (ctx = contexts; ctx; ctx = ctx->next) { if (ctx->id == ctx_id) { break; } } return ctx; } static void insert_context(struct context *ctx) { struct context **next_ctx; for (next_ctx = &contexts; *next_ctx && (*next_ctx)->id < ctx->id; next_ctx = &((*next_ctx)->next)) { ; } ctx->next = *next_ctx; *next_ctx = ctx; } static void remove_context(struct context *ctx) { struct context **next_ctx; for (next_ctx = &contexts; *next_ctx; next_ctx = &((*next_ctx)->next)) { if (*next_ctx == ctx) { *next_ctx = ctx->next; break; } } } static struct event_set *find_event_set(struct context *ctx, int event_set_id) { struct event_set *evt; for (evt = ctx->event_sets; evt; evt = evt->next) { if (evt->id == event_set_id) { break; } } return evt; } static void insert_event_set(struct context *ctx, struct event_set *evt) { struct event_set **next_evt; for (next_evt = &ctx->event_sets; *next_evt && (*next_evt)->id < evt->id; next_evt = &((*next_evt)->next)) { ; } evt->next = *next_evt; *next_evt = evt; } static void remove_event_set(struct context *ctx, struct event_set *evt) { struct event_set **next_evt; for (next_evt = &ctx->event_sets; *next_evt; next_evt = &((*next_evt)->next)) { if (*next_evt == evt) { *next_evt = evt->next; break; } } } static struct program *find_program(int program_id) { struct program *prog; for (prog = programs; prog; prog = prog->next) { if (prog->id == program_id) { break; } } return prog; } static void insert_program(struct program *prog) { struct program **next_prog; for (next_prog = &programs; *next_prog && (*next_prog)->id < prog->id; next_prog = &((*next_prog)->next)) { ; } prog->next = *next_prog; *next_prog = prog; } static void remove_program(struct program *prog) { struct program **next_prog; for (next_prog = &programs; *next_prog; next_prog = &((*next_prog)->next)) { if (*next_prog == prog) { *next_prog = prog->next; break; } } } /** * set_affinity * * When loading or unloading a system-wide context, we must pin the pfmsetup * process to that CPU before making the system call. Also, get the current * affinity and return it to the caller so we can change it back later. **/ static int set_affinity(int cpu, cpu_set_t *old_cpu_set) { cpu_set_t new_cpu_set; int rc; rc = sched_getaffinity(0, sizeof(*old_cpu_set), old_cpu_set); if (rc) { rc = errno; LOG_ERROR("Can't get current process affinity mask: %d\n", rc); return rc; } CPU_ZERO(&new_cpu_set); CPU_SET(cpu, &new_cpu_set); rc = sched_setaffinity(0, sizeof(new_cpu_set), &new_cpu_set); if (rc) { rc = errno; LOG_ERROR("Can't set process affinity to CPU %d: %d\n", cpu, rc); return rc; } return 0; } /** * revert_affinity * * Reset the process affinity to the specified mask. **/ static void revert_affinity(cpu_set_t *old_cpu_set) { int rc; rc = sched_setaffinity(0, sizeof(*old_cpu_set), old_cpu_set); if (rc) { /* Not a fatal error if we can't reset the affinity. */ LOG_INFO("Can't revert process affinity to original value.\n"); } } /** * create_context * * Arguments: [options] * Options: --system * --no-overflow-msg * --block-on-notify * --sampler * * Call the pfm_create_context system-call to create a new perfmon context. * Add a new entry to the global 'contexts' list. **/ static int create_context(int argc, char **argv) { pfarg_ctx_t ctx_arg; pfm_dfl_smpl_arg_t smpl_arg; struct context *new_ctx = NULL; char *sampler_name = NULL; void *smpl_p; int no_overflow_msg = FALSE; int block_on_notify = FALSE; int system_wide = FALSE; int c, ctx_id = 0; int rc; size_t sz; struct option long_opts[] = { {"sampler", required_argument, NULL, 1}, {"system", no_argument, NULL, 2}, {"no-overflow-msg", no_argument, NULL, 3}, {"block-on-notify", no_argument, NULL, 4}, {NULL, 0, NULL, 0} }; memset(&ctx_arg, 0, sizeof(ctx_arg)); opterr = 0; optind = 0; while ((c = getopt_long_only(argc, argv, "", long_opts, NULL)) != EOF) { switch (c) { case 1: sampler_name = optarg; break; case 2: system_wide = TRUE; break; case 3: no_overflow_msg = TRUE; break; case 4: block_on_notify = TRUE; break; default: LOG_ERROR("invalid option: %c", optopt); rc = EINVAL; goto error; } } if (argc < optind + 1) { USAGE("create_context [options] "); rc = EINVAL; goto error; } ctx_id = strtoul(argv[optind], NULL, 0); if (ctx_id <= 0) { LOG_ERROR("Invalid context ID (%s). Must be a positive " "integer.", argv[optind]); rc = EINVAL; goto error; } /* Make sure we don't already have a context with this ID. */ new_ctx = find_context(ctx_id); if (new_ctx) { LOG_ERROR("Context with ID %d already exists.", ctx_id); rc = EINVAL; goto error; } if (sampler_name) { smpl_arg.buf_size = getpagesize(); smpl_p = &smpl_arg; sz = sizeof(smpl_arg); } else { smpl_p = NULL; sz = 0; } ctx_arg.ctx_flags = (system_wide ? PFM_FL_SYSTEM_WIDE : 0) | (no_overflow_msg ? PFM_FL_OVFL_NO_MSG : 0) | (block_on_notify ? PFM_FL_NOTIFY_BLOCK : 0); rc = pfm_create_context(&ctx_arg, sampler_name, smpl_p, sz); if (rc == -1) { rc = errno; LOG_ERROR("pfm_create_context system call returned " "an error: %d.", rc); goto error; } /* Allocate and initialize a new context structure and add it to the * global list. Every new context automatically gets one event_set * with an event ID of 0. */ new_ctx = calloc(1, sizeof(*new_ctx)); if (!new_ctx) { LOG_ERROR("Can't allocate structure for new context %d.", ctx_id); rc = ENOMEM; goto error; } new_ctx->event_sets = calloc(1, sizeof(*(new_ctx->event_sets))); if (!new_ctx->event_sets) { LOG_ERROR("Can't allocate event-set structure for new " "context %d.", ctx_id); rc = ENOMEM; goto error; } new_ctx->id = ctx_id; new_ctx->fd = rc; new_ctx->cpu = -1; new_ctx->ctx_arg = ctx_arg; new_ctx->smpl_arg = smpl_arg; insert_context(new_ctx); LOG_INFO("Created context %d with file-descriptor %d.", new_ctx->id, new_ctx->fd); return 0; error: if (new_ctx) { close(new_ctx->fd); free(new_ctx->event_sets); free(new_ctx); } return rc; } /** * load_context * * Arguments: * * Call the pfm_load_context system-call to load a perfmon context into the * system's performance monitoring unit. **/ static int load_context(int argc, char **argv) { struct context *ctx; struct event_set *evt; struct program *prog; pfarg_load_t load_arg; cpu_set_t old_cpu_set; int ctx_id, event_set_id, program_id; int system_wide, rc; ctx_id = strtoul(argv[1], NULL, 0); event_set_id = strtoul(argv[2], NULL, 0); program_id = strtoul(argv[3], NULL, 0); if (ctx_id <= 0 || event_set_id < 0 || program_id < 0) { LOG_ERROR("context ID, event-set ID, and program/CPU ID must " "be positive integers."); return EINVAL; } /* Find the context, event_set, and program in the global lists. */ ctx = find_context(ctx_id); if (!ctx) { LOG_ERROR("Can't find context with ID %d.", ctx_id); return EINVAL; } evt = find_event_set(ctx, event_set_id); if (!evt) { LOG_ERROR("Can't find event-set with ID %d in context %d.", event_set_id, ctx_id); return EINVAL; } load_arg.load_set = evt->id; system_wide = ctx->ctx_arg.ctx_flags & PFM_FL_SYSTEM_WIDE; if (system_wide) { if (ctx->cpu >= 0) { LOG_ERROR("Trying to load context %d which is already " "loaded on CPU %d.\n", ctx_id, ctx->cpu); return EBUSY; } rc = set_affinity(program_id, &old_cpu_set); if (rc) { return rc; } /* Specify the CPU as the PID. */ load_arg.load_pid = program_id; } else { prog = find_program(program_id); if (!prog) { LOG_ERROR("Can't find program with ID %d.", program_id); return EINVAL; } load_arg.load_pid = prog->pid; } rc = pfm_load_context(ctx->fd, &load_arg); if (rc) { rc = errno; LOG_ERROR("pfm_load_context system call returned " "an error: %d.", rc); return rc; } if (system_wide) { /* Keep track of which CPU this context is loaded on. */ ctx->cpu = program_id; revert_affinity(&old_cpu_set); } LOG_INFO("Loaded context %d, event-set %d onto %s %d.", ctx_id, event_set_id, system_wide ? "cpu" : "program", program_id); return 0; } /** * unload_context * * Arguments: * * Call the pfm_unload_context system-call to unload a perfmon context from * the system's performance monitoring unit. **/ static int unload_context(int argc, char **argv) { struct context *ctx; cpu_set_t old_cpu_set; int system_wide; int ctx_id; int rc; ctx_id = strtoul(argv[1], NULL, 0); if (ctx_id <= 0) { LOG_ERROR("context ID must be a positive integer."); return EINVAL; } ctx = find_context(ctx_id); if (!ctx) { LOG_ERROR("Can't find context with ID %d.", ctx_id); return EINVAL; } system_wide = ctx->ctx_arg.ctx_flags & PFM_FL_SYSTEM_WIDE; if (system_wide) { if (ctx->cpu < 0) { /* This context isn't loaded on any CPU. */ LOG_ERROR("Trying to unload context %d that isn't " "loaded.\n", ctx_id); return EINVAL; } rc = set_affinity(ctx->cpu, &old_cpu_set); if (rc) { return rc; } } rc = pfm_unload_context(ctx->fd); if (rc) { rc = errno; LOG_ERROR("pfm_unload_context system call returned " "an error: %d.", rc); return rc; } if (system_wide) { ctx->cpu = -1; revert_affinity(&old_cpu_set); } LOG_INFO("Unloaded context %d.", ctx_id); return 0; } /** * close_context * * Arguments: * * Close the context's file descriptor, remove it from the global list, and * free the context data structures. **/ static int close_context(int argc, char **argv) { struct context *ctx; struct event_set *evt, *next_evt; int ctx_id; ctx_id = strtoul(argv[1], NULL, 0); if (ctx_id <= 0) { LOG_ERROR("context ID must be a positive integer."); return EINVAL; } ctx = find_context(ctx_id); if (!ctx) { LOG_ERROR("Can't find context with ID %d.", ctx_id); return EINVAL; } /* There's no perfmon system-call to delete a context. We simply call * close on the file handle. */ close(ctx->fd); remove_context(ctx); for (evt = ctx->event_sets; evt; evt = next_evt) { next_evt = evt->next; free(evt); } free(ctx); LOG_INFO("Closed and freed context %d.", ctx_id); return 0; } /** * write_pmc * * Arguments: < >+ * * Write values to one or more control registers. **/ static int write_pmc(int argc, char **argv) { struct context *ctx; struct event_set *evt; pfarg_pmc_t *pmc_args = NULL; cpu_set_t old_cpu_set; int ctx_id, event_set_id; int pmc_id, num_pmcs; unsigned long long pmc_value; int system_wide, i, rc; ctx_id = strtoul(argv[1], NULL, 0); event_set_id = strtoul(argv[2], NULL, 0); if (ctx_id <= 0 || event_set_id < 0) { LOG_ERROR("context ID and event-set ID must be " "positive integers."); return EINVAL; } ctx = find_context(ctx_id); if (!ctx) { LOG_ERROR("Can't find context with ID %d.", ctx_id); return EINVAL; } evt = find_event_set(ctx, event_set_id); if (!evt) { LOG_ERROR("Can't find event-set with ID %d in context %d.", event_set_id, ctx_id); return EINVAL; } /* Allocate an array of PMC structures. */ num_pmcs = (argc - 3) / 2; pmc_args = calloc(num_pmcs, sizeof(*pmc_args)); if (!pmc_args) { LOG_ERROR("Can't allocate PMC argument array."); return ENOMEM; } for (i = 0; i < num_pmcs; i++) { pmc_id = strtoul(argv[3 + i*2], NULL, 0); pmc_value = strtoull(argv[4 + i*2], NULL, 0); if (pmc_id < 0) { LOG_ERROR("PMC ID must be a positive integer."); rc = EINVAL; goto out; } pmc_args[i].reg_num = pmc_id; pmc_args[i].reg_set = evt->id; pmc_args[i].reg_value = pmc_value; } system_wide = ctx->ctx_arg.ctx_flags & PFM_FL_SYSTEM_WIDE; if (system_wide && ctx->cpu >= 0) { rc = set_affinity(ctx->cpu, &old_cpu_set); if (rc) { goto out; } } rc = pfm_write_pmcs(ctx->fd, pmc_args, num_pmcs); if (rc) { rc = errno; LOG_ERROR("pfm_write_pmcs system call returned " "an error: %d.", rc); goto out; } if (system_wide && ctx->cpu >= 0) { revert_affinity(&old_cpu_set); } out: free(pmc_args); return rc; } /** * write_pmd * * Arguments: < >+ * * FIXME: Add options for other fields in pfarg_pmd_t. **/ static int write_pmd(int argc, char **argv) { struct context *ctx; struct event_set *evt; pfarg_pmd_t *pmd_args = NULL; cpu_set_t old_cpu_set; int ctx_id, event_set_id; int pmd_id, num_pmds; unsigned long long pmd_value; int system_wide, i, rc; ctx_id = strtoul(argv[1], NULL, 0); event_set_id = strtoul(argv[2], NULL, 0); if (ctx_id <= 0 || event_set_id < 0) { LOG_ERROR("context ID and event-set ID must be " "positive integers."); return EINVAL; } ctx = find_context(ctx_id); if (!ctx) { LOG_ERROR("Can't find context with ID %d.", ctx_id); return EINVAL; } evt = find_event_set(ctx, event_set_id); if (!evt) { LOG_ERROR("Can't find event-set with ID %d in context %d.", event_set_id, ctx_id); return EINVAL; } /* Allocate an array of PMD structures. */ num_pmds = (argc - 3) / 2; pmd_args = calloc(num_pmds, sizeof(*pmd_args)); if (!pmd_args) { LOG_ERROR("Can't allocate PMD argument array."); return ENOMEM; } for (i = 0; i < num_pmds; i++) { pmd_id = strtoul(argv[3 + i*2], NULL, 0); pmd_value = strtoull(argv[4 + i*2], NULL, 0); if (pmd_id < 0) { LOG_ERROR("PMD ID must be a positive integer."); rc = EINVAL; goto out; } pmd_args[i].reg_num = pmd_id; pmd_args[i].reg_set = evt->id; pmd_args[i].reg_value = pmd_value; } system_wide = ctx->ctx_arg.ctx_flags & PFM_FL_SYSTEM_WIDE; if (system_wide && ctx->cpu >= 0) { rc = set_affinity(ctx->cpu, &old_cpu_set); if (rc) { goto out; } } rc = pfm_write_pmds(ctx->fd, pmd_args, num_pmds); if (rc) { rc = errno; LOG_ERROR("pfm_write_pmds system call returned " "an error: %d.", rc); goto out; } if (system_wide && ctx->cpu >= 0) { revert_affinity(&old_cpu_set); } out: free(pmd_args); return rc; } /** * read_pmd * * Arguments: + * * FIXME: Add options for other fields in pfarg_pmd_t. **/ static int read_pmd(int argc, char **argv) { struct context *ctx; struct event_set *evt; pfarg_pmd_t *pmd_args = NULL; cpu_set_t old_cpu_set; int ctx_id, event_set_id; int pmd_id, num_pmds; int system_wide, i, rc; ctx_id = strtoul(argv[1], NULL, 0); event_set_id = strtoul(argv[2], NULL, 0); if (ctx_id <= 0 || event_set_id < 0) { LOG_ERROR("context ID and event-set ID must be " "positive integers."); return EINVAL; } ctx = find_context(ctx_id); if (!ctx) { LOG_ERROR("Can't find context with ID %d.", ctx_id); return EINVAL; } evt = find_event_set(ctx, event_set_id); if (!evt) { LOG_ERROR("Can't find event-set with ID %d in context %d.", event_set_id, ctx_id); return EINVAL; } /* Allocate an array of PMD structures. */ num_pmds = argc - 3; pmd_args = calloc(num_pmds, sizeof(*pmd_args)); if (!pmd_args) { LOG_ERROR("Can't allocate PMD argument array."); return ENOMEM; } for (i = 0; i < num_pmds; i++) { pmd_id = strtoul(argv[3 + i], NULL, 0); if (pmd_id < 0) { LOG_ERROR("PMD ID must be a positive integer."); rc = EINVAL; goto out; } pmd_args[i].reg_num = pmd_id; pmd_args[i].reg_set = evt->id; } system_wide = ctx->ctx_arg.ctx_flags & PFM_FL_SYSTEM_WIDE; if (system_wide && ctx->cpu >= 0) { rc = set_affinity(ctx->cpu, &old_cpu_set); if (rc) { goto out; } } rc = pfm_read_pmds(ctx->fd, pmd_args, num_pmds); if (rc) { rc = errno; LOG_ERROR("pfm_read_pmds system call returned " "an error: %d.", rc); goto out; } if (system_wide && ctx->cpu >= 0) { revert_affinity(&old_cpu_set); } out: free(pmd_args); return rc; } /** * start_counting * * Arguments: * * Call the pfm_start system-call to start counting for a perfmon context * that was previously stopped. **/ static int start_counting(int argc, char **argv) { pfarg_start_t start_arg; struct context *ctx; struct event_set *evt; cpu_set_t old_cpu_set; int ctx_id, event_set_id; int system_wide, rc; memset(&start_arg, 0, sizeof(start_arg)); ctx_id = strtoul(argv[1], NULL, 0); event_set_id = strtoul(argv[2], NULL, 0); if (ctx_id <= 0 || event_set_id < 0) { LOG_ERROR("context ID and event-set ID must be " "positive integers."); return EINVAL; } ctx = find_context(ctx_id); if (!ctx) { LOG_ERROR("Can't find context with ID %d.", ctx_id); return EINVAL; } evt = find_event_set(ctx, event_set_id); if (!evt) { LOG_ERROR("Can't find event-set with ID %d in context %d.", event_set_id, ctx_id); return EINVAL; } start_arg.start_set = evt->id; system_wide = ctx->ctx_arg.ctx_flags & PFM_FL_SYSTEM_WIDE; if (system_wide && ctx->cpu >= 0) { rc = set_affinity(ctx->cpu, &old_cpu_set); if (rc) { return rc; } } rc = pfm_start(ctx->fd, &start_arg); if (rc) { rc = errno; LOG_ERROR("pfm_start system call returned an error: %d.", rc); return rc; } if (system_wide && ctx->cpu >= 0) { revert_affinity(&old_cpu_set); } LOG_INFO("Started counting for context %d, event-set %d.", ctx_id, event_set_id); return 0; } /** * stop_counting * * Arguments: * * Call the pfm_stop system-call to stop counting for a perfmon context that * was previously loaded. **/ static int stop_counting(int argc, char **argv) { struct context *ctx; cpu_set_t old_cpu_set; int system_wide; int ctx_id; int rc; ctx_id = strtoul(argv[1], NULL, 0); if (ctx_id <= 0) { LOG_ERROR("context ID must be a positive integer."); return EINVAL; } ctx = find_context(ctx_id); if (!ctx) { LOG_ERROR("Can't find context with ID %d.", ctx_id); return EINVAL; } system_wide = ctx->ctx_arg.ctx_flags & PFM_FL_SYSTEM_WIDE; if (system_wide && ctx->cpu >= 0) { rc = set_affinity(ctx->cpu, &old_cpu_set); if (rc) { return rc; } } rc = pfm_stop(ctx->fd); if (rc) { rc = errno; LOG_ERROR("pfm_stop system call returned an error: %d.", rc); return rc; } if (system_wide && ctx->cpu >= 0) { revert_affinity(&old_cpu_set); } LOG_INFO("Stopped counting for context %d.", ctx_id); return 0; } /** * restart_counting * * Arguments: * * Call the pfm_restart system-call to clear the data counters and start * counting from zero for a perfmon context that was previously loaded. **/ static int restart_counting(int argc, char **argv) { struct context *ctx; cpu_set_t old_cpu_set; int system_wide; int ctx_id; int rc; ctx_id = strtoul(argv[1], NULL, 0); if (ctx_id <= 0) { LOG_ERROR("context ID must be a positive integer."); return EINVAL; } ctx = find_context(ctx_id); if (!ctx) { LOG_ERROR("Can't find context with ID %d.", ctx_id); return EINVAL; } system_wide = ctx->ctx_arg.ctx_flags & PFM_FL_SYSTEM_WIDE; if (system_wide && ctx->cpu >= 0) { rc = set_affinity(ctx->cpu, &old_cpu_set); if (rc) { return rc; } } rc = pfm_restart(ctx->fd); if (rc) { rc = errno; LOG_ERROR("pfm_restart system call returned an error: %d.", rc); return rc; } if (system_wide && ctx->cpu >= 0) { revert_affinity(&old_cpu_set); } LOG_INFO("Restarted counting for context %d.", ctx_id); return 0; } /** * create_eventset * * Arguments: [options] * Options: --timeout * --switch-on-overflow * --exclude-idle **/ static int create_eventset(int argc, char **argv) { pfarg_setdesc_t set_arg; struct context *ctx; struct event_set *evt; cpu_set_t old_cpu_set; int ctx_id, event_set_id; unsigned long timeout = 0; int switch_on_overflow = FALSE; int switch_on_timeout = FALSE; int exclude_idle = FALSE; int new_set = FALSE; int system_wide,c, rc; struct option long_opts[] = { {"next-set", required_argument, NULL, 1}, {"timeout", required_argument, NULL, 2}, {"switch-on-overflow", no_argument, NULL, 3}, {"exclude-idle", no_argument, NULL, 4}, {NULL, 0, NULL, 0} }; memset(&set_arg, 0, sizeof(set_arg)); opterr = 0; optind = 0; while ((c = getopt_long_only(argc, argv, "", long_opts, NULL)) != EOF) { switch (c) { case 1: timeout = strtoul(optarg, NULL, 0); if (!timeout) { LOG_ERROR("timeout must be a " "non-zero integer."); return EINVAL; } switch_on_timeout = TRUE; break; case 2: switch_on_overflow = TRUE; break; case 3: exclude_idle = TRUE; break; default: LOG_ERROR("invalid option: %c", optopt); return EINVAL; } } (void) exclude_idle; if (argc < optind + 2) { USAGE("create_eventset [options] "); return EINVAL; } ctx_id = strtoul(argv[optind], NULL, 0); event_set_id = strtoul(argv[optind+1], NULL, 0); if (ctx_id <= 0 || event_set_id < 0) { LOG_ERROR("context ID and event-set ID must be " "positive integers."); return EINVAL; } ctx = find_context(ctx_id); if (!ctx) { LOG_ERROR("Can't find context with ID %d.", ctx_id); return EINVAL; } if (switch_on_timeout && switch_on_overflow) { LOG_ERROR("Cannot switch set %d (context %d) on both " "timeout and overflow.", event_set_id, ctx_id); return EINVAL; } evt = find_event_set(ctx, event_set_id); if (!evt) { evt = calloc(1, sizeof(*evt)); if (!evt) { LOG_ERROR("Can't allocate structure for new event-set " "%d in context %d.", event_set_id, ctx_id); return ENOMEM; } evt->id = event_set_id; new_set = TRUE; } set_arg.set_id = event_set_id; set_arg.set_timeout = timeout; /* in nanseconds */ set_arg.set_flags = (switch_on_overflow ? PFM_SETFL_OVFL_SWITCH : 0) | (switch_on_timeout ? PFM_SETFL_TIME_SWITCH : 0); system_wide = ctx->ctx_arg.ctx_flags & PFM_FL_SYSTEM_WIDE; if (system_wide && ctx->cpu >= 0) { rc = set_affinity(ctx->cpu, &old_cpu_set); if (rc) { free(evt); return rc; } } rc = pfm_create_evtsets(ctx->fd, &set_arg, 1); if (rc) { rc = errno; LOG_ERROR("pfm_create_evtsets system call returned " "an error: %d.", rc); free(evt); return rc; } if (system_wide && ctx->cpu >= 0) { revert_affinity(&old_cpu_set); } if (new_set) { insert_event_set(ctx, evt); } LOG_INFO("%s event-set %d in context %d.", new_set ? "Created" : "Modified", event_set_id, ctx_id); if (switch_on_timeout) { LOG_INFO(" Actual timeout set to %llu ns.", (unsigned long long)set_arg.set_timeout); } return 0; } /** * delete_eventset * * Arguments: **/ static int delete_eventset(int argc, char **argv) { pfarg_setdesc_t set_arg; struct context *ctx; struct event_set *evt; cpu_set_t old_cpu_set; int ctx_id, event_set_id; int system_wide, rc; memset(&set_arg, 0, sizeof(set_arg)); ctx_id = strtoul(argv[1], NULL, 0); event_set_id = strtoul(argv[2], NULL, 0); if (ctx_id <= 0 || event_set_id < 0) { LOG_ERROR("context ID and event-set ID must be " "positive integers."); return EINVAL; } ctx = find_context(ctx_id); if (!ctx) { LOG_ERROR("Can't find context with ID %d.", ctx_id); return EINVAL; } evt = find_event_set(ctx, event_set_id); if (!evt) { LOG_ERROR("Can't find event-set with ID %d in context %d.", event_set_id, ctx_id); return EINVAL; } set_arg.set_id = evt->id; system_wide = ctx->ctx_arg.ctx_flags & PFM_FL_SYSTEM_WIDE; if (system_wide && ctx->cpu >= 0) { rc = set_affinity(ctx->cpu, &old_cpu_set); if (rc) { return rc; } } rc = pfm_delete_evtsets(ctx->fd, &set_arg, 1); if (rc) { rc = errno; LOG_ERROR("pfm_delete_evtsets system call returned " "an error: %d.", rc); return rc; } if (system_wide && ctx->cpu >= 0) { revert_affinity(&old_cpu_set); } remove_event_set(ctx, evt); free(evt); LOG_INFO("Deleted event-set %d from context %d.", event_set_id, ctx_id); return 0; } /** * getinfo_eventset * * Arguments: **/ static int getinfo_eventset(int argc, char **argv) { pfarg_setinfo_t set_arg; struct context *ctx; struct event_set *evt; cpu_set_t old_cpu_set; int ctx_id, event_set_id; int system_wide, rc; memset(&set_arg, 0, sizeof(set_arg)); ctx_id = strtoul(argv[1], NULL, 0); event_set_id = strtoul(argv[2], NULL, 0); if (ctx_id <= 0 || event_set_id < 0) { LOG_ERROR("context ID and event-set ID must be " "positive integers."); return EINVAL; } ctx = find_context(ctx_id); if (!ctx) { LOG_ERROR("Can't find context with ID %d.", ctx_id); return EINVAL; } evt = find_event_set(ctx, event_set_id); if (!evt) { LOG_ERROR("Can't find event-set with ID %d in context %d.", event_set_id, ctx_id); return EINVAL; } set_arg.set_id = evt->id; system_wide = ctx->ctx_arg.ctx_flags & PFM_FL_SYSTEM_WIDE; if (system_wide && ctx->cpu >= 0) { rc = set_affinity(ctx->cpu, &old_cpu_set); if (rc) { return rc; } } rc = pfm_getinfo_evtsets(ctx->fd, &set_arg, 1); if (rc) { rc = errno; LOG_ERROR("pfm_getinfo_evtsets system call returned " "an error: %d.", rc); return rc; } if (system_wide && ctx->cpu >= 0) { revert_affinity(&old_cpu_set); } LOG_INFO("Got info for event-set %d in context %d.", event_set_id, ctx_id); LOG_INFO(" Flags: 0x%x", set_arg.set_flags); LOG_INFO(" Runs: %llu", (unsigned long long)set_arg.set_runs); LOG_INFO(" Timeout: %"PRIu64, set_arg.set_timeout); return 0; } /** * run_program * * Arguments: * * Start the specified program. After fork'ing but before exec'ing, ptrace * the child so it will remain suspended until a corresponding resume_program * command. We do this so we can load a context for the program before it * actually starts running. This logic is taken from the task.c example in * the libpfm source code tree. **/ static int run_program(int argc, char **argv) { struct program *prog; int program_id; pid_t pid; int rc; program_id = strtoul(argv[1], NULL, 0); if (program_id <= 0) { LOG_ERROR("program ID must be a positive integer."); return EINVAL; } /* Make sure we haven't already started a program with this ID. */ prog = find_program(program_id); if (prog) { LOG_ERROR("Program with ID %d already exists.", program_id); return EINVAL; } prog = calloc(1, sizeof(*prog)); if (!prog) { LOG_ERROR("Can't allocate new program structure to run '%s'.", argv[2]); return ENOMEM; } prog->id = program_id; pid = fork(); if (pid == -1) { /* Error fork'ing. */ LOG_ERROR("Unable to fork child process."); return EINVAL; } else if (!pid) { /* Child */ /* This will cause the program to stop before executing the * first user level instruction. We can only load a context * if the program is in the STOPPED state. This child * process will sit here until we've process a resume_program * command. */ rc = ptrace(PTRACE_TRACEME, 0, NULL, NULL); if (rc) { rc = errno; LOG_ERROR("Error ptrace'ing '%s': %d", argv[2], rc); exit(rc); } execvp(argv[2], argv + 2); rc = errno; LOG_ERROR("Error exec'ing '%s': %d", argv[2], rc); exit(rc); } /* Parent */ prog->pid = pid; insert_program(prog); /* Wait for the child to exec. */ waitpid(pid, &rc, WUNTRACED); /* Check if process exited early. */ if (WIFEXITED(rc)) { LOG_ERROR("Program '%s' exited too early with status " "%d", argv[2], WEXITSTATUS(rc)); return WEXITSTATUS(rc); } LOG_INFO("Started program %d: '%s'.", program_id, argv[2]); return 0; } /** * resume_program * * Arguments: * * A program started with run_program must be 'resumed' before it actually * begins running. This allows us to load a context to the process and * start the counters before the program executes any code. **/ static int resume_program(int argc, char **argv) { struct program *prog; int program_id; int rc; program_id = strtoul(argv[1], NULL, 0); if (program_id <= 0) { LOG_ERROR("program ID must be a positive integer."); return EINVAL; } prog = find_program(program_id); if (!prog) { LOG_ERROR("Can't find program with ID %d.", program_id); return EINVAL; } /* Call ptrace to resume execution of the process. If a context has * been loaded and the counters started, this is where monitoring * is effectively activated. */ rc = ptrace(PTRACE_DETACH, prog->pid, NULL, 0); if (rc) { rc = errno; LOG_ERROR("Error detaching program %d.\n", prog->id); return rc; } LOG_INFO("Resumed program %d.", program_id); return 0; } /** * wait_on_program * * Arguments: * * Wait for the specified program to complete and exit. **/ static int wait_on_program(int argc, char **argv) { struct program *prog; int program_id; int rc; program_id = strtoul(argv[1], NULL, 0); if (program_id <= 0) { LOG_ERROR("program ID must be a positive integer."); return EINVAL; } prog = find_program(program_id); if (!prog) { LOG_ERROR("Can't find program with ID %d.", program_id); return EINVAL; } waitpid(prog->pid, &rc, 0); /* The program has exitted, but if there was a context loaded on that * process, it will still have the latest counts available to read. */ remove_program(prog); free(prog); LOG_INFO("Waited for program %d to complete.", program_id); return 0; } /** * _sleep * * Arguments: